ej2/100_star_code · Datasets at Hugging Face

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/server/captive.c

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libguestfs/nbdkit

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captive.c

/* nbdkit * Copyright Red Hat * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Red Hat nor the names of its contributors may be * used to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY RED HAT AND CONTRIBUTORS ''AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RED HAT OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include <config.h> #include <stdio.h> #include <stdlib.h> #include <stdarg.h> #include <string.h> #include <unistd.h> #include <sys/types.h> #include <signal.h> #include <assert.h> #ifdef HAVE_SYS_WAIT_H #include <sys/wait.h> #endif #include "utils.h" #include "internal.h" #ifndef WIN32 /* Handle the --run option. If run is NULL, does nothing. If run is * not NULL then run nbdkit as a captive subprocess of the command. */ void run_command (void) { FILE *fp; char *cmd = NULL; size_t len = 0; int r, status; pid_t pid; if (!run) return; if (!export_name) export_name = ""; fp = open_memstream (&cmd, &len); if (fp == NULL) { perror ("open_memstream"); exit (EXIT_FAILURE); } /* Construct $uri. */ fprintf (fp, "uri="); if (tls == 2) /* --tls=require */ fprintf (fp, "nbds"); else fprintf (fp, "nbd"); if (port) { if (!vsock) { fprintf (fp, "://localhost:"); shell_quote (port, fp); if (strcmp (export_name, "") != 0) { putc ('/', fp); uri_quote (export_name, fp); } } else { fprintf (fp, "+vsock://1:"); /* 1 = VMADDR_CID_LOCAL */ shell_quote (port, fp); if (strcmp (export_name, "") != 0) { putc ('/', fp); uri_quote (export_name, fp); } } } else if (unixsocket) { fprintf (fp, "+unix://"); if (strcmp (export_name, "") != 0) { putc ('/', fp); uri_quote (export_name, fp); } fprintf (fp, "\\?socket="); uri_quote (unixsocket, fp); } putc ('\n', fp); /* Since nbdkit 1.24, $nbd is a synonym for $uri. */ fprintf (fp, "nbd=\"$uri\"\n"); /* Expose $exportname. */ fprintf (fp, "exportname="); shell_quote (export_name, fp); putc ('\n', fp); /* Construct $tls, $port and $unixsocket. */ if (tls > 0) fprintf (fp, "tls=%d\n", tls); fprintf (fp, "port="); if (port) shell_quote (port, fp); putc ('\n', fp); fprintf (fp, "unixsocket="); if (unixsocket) shell_quote (unixsocket, fp); fprintf (fp, "\n"); /* Add the --run command. Note we don't have to quote this. */ fprintf (fp, "%s", run); if (fclose (fp) == EOF) { perror ("memstream failed"); exit (EXIT_FAILURE); } /* Fork. Captive nbdkit runs as the child process. */ pid = fork (); if (pid == -1) { perror ("fork"); exit (EXIT_FAILURE); } if (pid > 0) { /* Parent process is the run command. */ /* Restore original stdin/out */ if (dup2 (saved_stdin, STDIN_FILENO) == -1 || dup2 (saved_stdout, STDOUT_FILENO) == -1) { r = -1; } else r = system (cmd); if (r == -1) { nbdkit_error ("failure to execute external command: %m"); r = EXIT_FAILURE; } else if (WIFEXITED (r)) r = WEXITSTATUS (r); else { assert (WIFSIGNALED (r)); fprintf (stderr, "%s: external command was killed by signal %d\n", program_name, WTERMSIG (r)); r = WTERMSIG (r) + 128; } switch (waitpid (pid, &status, WNOHANG)) { case -1: nbdkit_error ("waitpid: %m"); r = EXIT_FAILURE; break; case 0: /* Captive nbdkit is still running; kill it. We want to wait * for nbdkit to exit since that ensures all cleanup is done in * the plugin before we return. However we don't care if nbdkit * returns an error, the exit code we return always comes from * the --run command. */ kill (pid, SIGTERM); waitpid (pid, NULL, 0); break; default: /* Captive nbdkit exited unexpectedly; update the exit status. */ if (WIFEXITED (status)) { if (r == 0) r = WEXITSTATUS (status); } else { assert (WIFSIGNALED (status)); fprintf (stderr, "%s: nbdkit command was killed by signal %d\n", program_name, WTERMSIG (status)); r = WTERMSIG (status) + 128; } } exit (r); } free (cmd); debug ("forked into background (new pid = %d)", getpid ()); } #else /* WIN32 */ void run_command (void) { if (!run) return; NOT_IMPLEMENTED_ON_WINDOWS ("--run"); } #endif /* WIN32 */

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/print/xmbibtex/files/patch-biblio.h

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--- biblio.h.orig 2018-08-25 16:02:49 UTC +++ biblio.h @@ -92,7 +92,7 @@ class BIBLIO { (public) CITATION **c; unsigned long last; - BIBLIO() {last=0; c='\0';} + BIBLIO() {last=0; c=NULL;} ~BIBLIO() { unsigned long n; if (c) for(n=last-1; n==0; n--) del_citation(n);

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/ni/src/lib/hlu/CoordArrays.c

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NCAR/ncl

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CoordArrays.c

/* * $Id: CoordArrays.c,v 1.42 1998-04-16 03:08:35 dbrown Exp $ */ /************************************************************************ * * * Copyright (C) 1993 * * University Corporation for Atmospheric Research * * All Rights Reserved * * * ************************************************************************/ /* * File: CoordArrays.c * * Author: Jeff W. Boote * National Center for Atmospheric Research * PO 3000, Boulder, Colorado * * Date: Tue Jan 18 12:37:23 MST 1994 * * Description: This class is used to communicate data in the format * of a CoordArray. */ #include <stdio.h> #include <string.h> #include <ncarg/hlu/CoordArraysP.h> #include <ncarg/hlu/CoordArrTableP.h> #include <ncarg/hlu/ConvertersP.h> static NrmQuark genQ = NrmNULLQUARK; static NrmQuark floatQ = NrmNULLQUARK; static NrmQuark floatgenQ = NrmNULLQUARK; static NrmQuark xarrQ = NrmNULLQUARK; static NrmQuark yarrQ = NrmNULLQUARK; static NrmQuark xmissQ = NrmNULLQUARK; static NrmQuark ymissQ = NrmNULLQUARK; static NrmQuark xmaxQ = NrmNULLQUARK; static NrmQuark ymaxQ = NrmNULLQUARK; static NrmQuark xminQ = NrmNULLQUARK; static NrmQuark yminQ = NrmNULLQUARK; typedef enum _NhlcaDType_{ XDIM, YDIM } _NhlcaDType; /************************************************************************ * * * CoordArrays Class declarations * * * ************************************************************************/ /* * Resource Declarations */ /*ARGSUSED*/ static NhlErrorTypes XCastSet #if NhlNeedProto ( NrmName name, NrmClass class, NhlPointer base, unsigned int offset ) #else (name,class,base,offset) NrmName name; NrmClass class; NhlPointer base; unsigned int offset; #endif { NhlCoordArraysLayer carrl = (NhlCoordArraysLayer)base; carrl->carr.xcast_set = False; carrl->carr.xcast = NhlMULTIPLEVECTORS; return NhlNOERROR; } /*ARGSUSED*/ static NhlErrorTypes YCastSet #if NhlNeedProto ( NrmName name, NrmClass class, NhlPointer base, unsigned int offset ) #else (name,class,base,offset) NrmName name; NrmClass class; NhlPointer base; unsigned int offset; #endif { NhlCoordArraysLayer carrl = (NhlCoordArraysLayer)base; carrl->carr.ycast_set = False; carrl->carr.ycast = NhlMULTIPLEVECTORS; return NhlNOERROR; } #define Oset(field) NhlOffset(NhlCoordArraysLayerRec,carr.field) static NhlResource resources[] = { /* Begin-documented-resources */ {NhlNcaXArray,NhlCcaXArray,NhlTGenArray,sizeof(NhlGenArray), Oset(xarray),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaYArray,NhlCcaYArray,NhlTGenArray,sizeof(NhlGenArray), Oset(yarray),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {"no.res","No.Res",NhlTBoolean,sizeof(NhlBoolean), Oset(xcast_set),NhlTImmediate,_NhlUSET((NhlPointer)True), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTBoolean,sizeof(int), Oset(ycast_set),NhlTImmediate,_NhlUSET((NhlPointer)True), _NhlRES_PRIVATE,NULL}, {NhlNcaXCast,NhlCcaCast,NhlTcaCastMode,sizeof(NhlcaCastMode), Oset(xcast),NhlTProcedure,_NhlUSET((NhlPointer)XCastSet),0,NULL}, {NhlNcaYCast,NhlCcaCast,NhlTcaCastMode,sizeof(NhlcaCastMode), Oset(ycast),NhlTProcedure,_NhlUSET((NhlPointer)YCastSet),0,NULL}, {NhlNcaCopyArrays,NhlCdiCopyData,NhlTBoolean,sizeof(NhlBoolean), Oset(copy_arrays),NhlTImmediate,_NhlUSET((NhlPointer)True),0,NULL}, {NhlNcaXMissingV,NhlCdiMissingValue,NhlTVariable,sizeof(NhlGenArray), Oset(missing_x),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaYMissingV,NhlCdiMissingValue,NhlTVariable,sizeof(NhlGenArray), Oset(missing_y),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaXMaxV,NhlCcaXMaxV,NhlTVariable,sizeof(NhlGenArray), Oset(max_x),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaYMaxV,NhlCcaYMaxV,NhlTVariable,sizeof(NhlGenArray), Oset(max_y),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaXMinV,NhlCcaXMinV,NhlTVariable,sizeof(NhlGenArray), Oset(min_x),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, {NhlNcaYMinV,NhlCcaYMinV,NhlTVariable,sizeof(NhlGenArray), Oset(min_y),NhlTImmediate,_NhlUSET((NhlPointer)NULL),0, (NhlFreeFunc)NhlFreeGenArray}, /* End-documented-resources */ /* * init private fields */ {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(my_xarray),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(my_yarray),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(xctxt),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(yctxt),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(my_missing_x),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, {"no.res","No.Res",NhlTPointer,sizeof(NhlPointer), Oset(my_missing_y),NhlTImmediate,_NhlUSET((NhlPointer)NULL), _NhlRES_PRIVATE,NULL}, }; #undef Oset /* base methods */ static NhlErrorTypes CoordArraysClassInitialize( #if NhlNeedProto void #endif ); static NhlErrorTypes CoordArraysInitialize( #if NhlNeedProto NhlClass lc, /* class */ NhlLayer req, /* requested */ NhlLayer new, /* new */ _NhlArgList args, /* args */ int nargs /* nargs */ #endif ); static NhlErrorTypes CoordArraysSetValues( #if NhlNeedProto NhlLayer old, /* old */ NhlLayer req, /* requested */ NhlLayer new, /* new */ _NhlArgList args, /* args to set */ int nargs /* nargs */ #endif ); static NhlErrorTypes CoordArraysGetValues( #if NhlNeedProto NhlLayer l, /* new */ _NhlArgList args, /* args to set */ int nargs /* nargs */ #endif ); static NhlErrorTypes CoordArraysDestroy( #if NhlNeedProto NhlLayer l /* layer to destroy */ #endif ); NhlCoordArraysClassRec NhlcoordArraysClassRec = { /* NhlBaseClassPart */ { /* class_name */ "coordArraysClass", /* nrm_class */ NrmNULLQUARK, /* layer_size */ sizeof(NhlCoordArraysLayerRec), /* class_inited */ False, /* superclass */ (NhlClass)&NhldataItemClassRec, /* cvt_table */ NULL, /* resources */ resources, /* num_resources */ NhlNumber(resources), /* all_resources */ NULL, /* callbacks */ NULL, /* num_callbacks */ 0, /* class_callbacks */ NULL, /* num_class_callbacks */ 0, /* class_part_initialize */ NULL, /* class_initialize */ CoordArraysClassInitialize, /* layer_initialize */ CoordArraysInitialize, /* layer_set_values */ CoordArraysSetValues, /* layer_set_values_hook */ NULL, /* layer_get_values */ CoordArraysGetValues, /* layer_reparent */ NULL, /* layer_destroy */ CoordArraysDestroy, /* child_resources */ NULL, /* layer_draw */ NULL, /* layer_pre_draw */ NULL, /* layer_draw_segonly */ NULL, /* layer_post_draw */ NULL, /* layer_clear */ NULL }, /* NhlDataItemClassPart */ { /* foo */ 0 }, /* NhlCoordArraysClassPart */ { /* foo */ 0 } }; NhlClass NhlcoordArraysClass = (NhlClass) &NhlcoordArraysClassRec; /* * Function: nhlfcoordarraysclass * * Description: fortran ref to contour class * * In Args: * * Out Args: * * Scope: global Fortran * Returns: NhlClass * Side Effect: */ NhlClass _NHLCALLF(nhlfcoordarraysclass,NHLFCOORDARRAYSCLASS) #if NhlNeedProto ( void ) #else () #endif { return NhlcoordArraysClass; } /************************************************************************ * New type converters - added to converter table by * * ClassInitialize * ************************************************************************/ /* * Function: CreateFloatTable * * Description: * * In Args: * * Out Args: * * Scope: static * Returns: NhlGenArray * Side Effect: */ static NhlErrorTypes CreateFloatTable #if NhlNeedProto ( NhlString cast_res, NhlString other_cast_res, NhlString error_lead, NhlGenArray gen, NhlGenArray other_gen, NhlcaCastMode cast, NhlcaCastMode other_cast, NhlGenArray *tbl, NhlGenArray *tbl_lens ) #else (cast_res,other_cast_res,error_lead,gen,other_gen,cast,other_cast,tbl,tbl_lens) NhlString cast_res; NhlString other_cast_res; NhlString error_lead; NhlGenArray gen; NhlGenArray other_gen; NhlcaCastMode cast; NhlcaCastMode other_cast; NhlGenArray *tbl; NhlGenArray *tbl_lens; #endif { ng_size_t vectors, elements; ng_size_t i,j; float **flttable, *fltvect; int *intvect; if(!gen){ *tbl = NULL; *tbl_lens = NULL; return NhlNOERROR; } switch(cast){ case NhlSINGLEVECTOR: switch(other_cast){ case NhlSINGLEVECTOR: vectors = 1; break; case NhlMULTIPLEVECTORS: vectors = other_gen->len_dimensions[0]; break; case NhlSPLITVECTORS: vectors = other_gen->len_dimensions[1]; break; default: NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:Invalid %s value", error_lead,other_cast_res); return NhlFATAL; } elements = gen->len_dimensions[0]; break; case NhlMULTIPLEVECTORS: if(gen->num_dimensions == 1){ vectors = 1; elements = gen->len_dimensions[0]; } else{ vectors = gen->len_dimensions[0]; elements = gen->len_dimensions[1]; } break; case NhlSPLITVECTORS: if(gen->num_dimensions == 1){ vectors = gen->len_dimensions[0]; elements = 1; } else{ vectors = gen->len_dimensions[1]; elements = gen->len_dimensions[0]; } break; default: NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:Invalid %s value", error_lead,cast_res); return NhlFATAL; } flttable = NhlConvertMalloc(sizeof(float*)*vectors); intvect = NhlConvertMalloc(sizeof(int)*vectors); if((flttable == NULL) || (intvect == NULL)){ NhlPError(NhlFATAL,ENOMEM,NULL); return NhlFATAL; } /* * gen is a float GenArray since it is from my_{n}array. */ fltvect = gen->data; for(i=0;i < vectors; i++){ intvect[i] = elements; switch(cast){ case NhlSINGLEVECTOR: flttable[i] = fltvect; break; case NhlMULTIPLEVECTORS: flttable[i] = fltvect + (i * elements); break; case NhlSPLITVECTORS: flttable[i] = NhlConvertMalloc(sizeof(float)*elements); if(flttable[i] == NULL){ NhlPError(NhlFATAL,ENOMEM,NULL); return NhlFATAL; } for(j=0;j<elements;j++) *(flttable[i]+j) = *(fltvect+i+(j*elements)); break; } } *tbl = _NhlConvertCreateGenArray(flttable,NhlTPointer, sizeof(NhlPointer),vectors,NULL); *tbl_lens = _NhlConvertCreateGenArray(intvect,NhlTInteger,sizeof(int), vectors,NULL); if((*tbl == NULL) || (*tbl_lens == NULL)) return NhlFATAL; return NhlNOERROR; } /* * Function: MyArray * * Description: * * In Args: * * Out Args: * * Scope: * Returns: * Side Effect: */ static NhlErrorTypes MyArray #if NhlNeedProto ( NhlGenArray *my_array, NhlGenArray array, _NhlConvertContext *context ) #else (my_array,array,context) NhlGenArray *my_array; NhlGenArray array; _NhlConvertContext *context; #endif { char func[]="MyArray"; _NhlConvertContext tctxt = NULL; NhlGenArray tgen = NULL; NrmValue from,to; NhlErrorTypes ret; if(!array) *my_array = NULL; else if(array->typeQ == floatQ) *my_array = array; else{ tctxt = _NhlCreateConvertContext(NULL); if(tctxt == NULL){ NHLPERROR((NhlFATAL,ENOMEM,NULL)); return NhlFATAL; } from.size = sizeof(NhlGenArray); from.data.ptrval = array; to.size = sizeof(NhlGenArray); to.data.ptrval = &tgen; ret = _NhlConvertData(tctxt,genQ,floatgenQ,&from,&to); if((ret < NhlWARNING) || !tgen){ NHLPERROR((NhlFATAL,NhlEUNKNOWN, "%s:Unable to convert from %s to %s",func, NhlTGenArray,NhlTFloatGenArray)); return NhlFATAL; } *my_array = tgen; } _NhlFreeConvertContext(*context); *context = tctxt; return NhlNOERROR; } /* * Function: GetMinMax * * Description: * * In Args: * * Out Args: * * Scope: * Returns: * Side Effect: */ static void GetMinMax #if NhlNeedProto ( NhlGenArray array, NhlGenArray oarray, NhlcaCastMode cast, NhlcaCastMode ocast, NhlGenArray miss, float *min, float *max ) #else (array,oarray,cast,ocast,miss,min,max) NhlGenArray array; NhlGenArray oarray; NhlcaCastMode cast; NhlcaCastMode ocast; NhlGenArray miss; float *min; float *max; #endif { float mx,mn; float *farr; if(array == NULL){ /* * array is *implied* - use indexes of other dim */ mn = 1.0; if((ocast == NhlMULTIPLEVECTORS) && (oarray->num_dimensions == 2)) mx = oarray->len_dimensions[1]; else mx = oarray->len_dimensions[0]; } else{ NhlBoolean init = False; int i,len; mx = mn = 0.0; farr = array->data; if(cast == NhlSINGLEVECTOR) len = array->len_dimensions[0]; else len = array->num_elements; for(i=0;i < len;i++){ if(miss && (farr[i]==*(float*)miss->data)) continue; if(init){ mx = MAX(farr[i],mx); mn = MIN(farr[i],mn); } else{ mx = farr[i]; mn = farr[i]; init = True; } } if(!init){ NHLPERROR((NhlWARNING,NhlEUNKNOWN, "No Valid values in Array, unable to compute Min or Max")); } } *min = mn; *max = mx; return; } /* * Function: FlushObj * * Description: * * In Args: * * Out Args: * * Scope: * Returns: * Side Effect: */ static NhlErrorTypes FlushObj #if NhlNeedProto ( _NhlcaDType dim, NhlCoordArraysLayerPart *cap ) #else (dim,cap) _NhlcaDType dim; NhlCoordArraysLayerPart *cap; #endif { char func[] = "FlushObj"; float max,min; NrmValue from,to; NhlErrorTypes ret=NhlNOERROR,lret; if(dim == XDIM){ if(!cap->my_xarray){ ret = MyArray(&cap->my_xarray,cap->xarray,&cap->xctxt); if(ret < NhlWARNING){ NhlPError(ret,NhlEUNKNOWN, "%s:Unable to convert %s to floats", func,NhlNcaXArray); return ret; } } if(!cap->my_missing_x && cap->missing_x){ if(cap->missing_x->typeQ == floatQ) cap->my_missing_x = cap->missing_x; else{ float tfloat; from.size = sizeof(NhlGenArray); from.data.ptrval = cap->missing_x; to.size = sizeof(float); to.data.ptrval = &tfloat; lret = NhlConvertData(NhlDEFAULT_APP, NhlTVariable,NhlTFloat,&from,&to); if(ret < NhlWARNING) return NhlFATAL; ret = MIN(ret,lret); cap->my_missing_x = _NhlCreateGenArray(&tfloat, NhlTFloat,sizeof(float),1,NULL,True); if(!cap->my_missing_x) return NhlFATAL; } } if(!cap->max_x || !cap->min_x){ GetMinMax(cap->my_xarray,cap->my_yarray,cap->xcast, cap->ycast,cap->my_missing_x,&min,&max); if(!cap->max_x) cap->max_x =_NhlCreateGenArray(&max,NhlTFloat, sizeof(float),1,NULL,True); if(!cap->min_x) cap->min_x =_NhlCreateGenArray(&min,NhlTFloat, sizeof(float),1,NULL,True); if(!cap->max_x || !cap->min_x){ NHLPERROR((NhlFATAL,ENOMEM,NULL)); return NhlFATAL; } } return ret; } if(dim == YDIM){ if(!cap->my_yarray){ lret = MyArray(&cap->my_yarray,cap->yarray,&cap->yctxt); if(lret < NhlWARNING){ NhlPError(ret,NhlEUNKNOWN, "%s:Unable to convert %s to floats", func,NhlNcaYArray); return lret; } ret = MIN(ret,lret); } if(!cap->my_missing_y && cap->missing_y){ if(cap->missing_y->typeQ == floatQ) cap->my_missing_y = cap->missing_y; else{ float tfloat; from.size = sizeof(NhlGenArray); from.data.ptrval = cap->missing_y; to.size = sizeof(float); to.data.ptrval = &tfloat; lret = NhlConvertData(NhlDEFAULT_APP, NhlTVariable,NhlTFloat,&from,&to); if(lret < NhlWARNING) return NhlFATAL; ret = MIN(lret,ret); cap->my_missing_y = _NhlCreateGenArray(&tfloat, NhlTFloat,sizeof(float),1,NULL,True); if(!cap->my_missing_y) return NhlFATAL; } } if(!cap->max_y || !cap->min_y){ GetMinMax(cap->my_yarray,cap->my_xarray,cap->ycast, cap->xcast,cap->my_missing_y,&min,&max); if(!cap->max_y) cap->max_y =_NhlCreateGenArray(&max,NhlTFloat, sizeof(float),1,NULL,True); if(!cap->min_y) cap->min_y =_NhlCreateGenArray(&min,NhlTFloat, sizeof(float),1,NULL,True); if(!cap->max_y || !cap->min_y){ NHLPERROR((NhlFATAL,ENOMEM,NULL)); return NhlFATAL; } } return ret; } return NhlFATAL; } /* * Function: CvtCArrToCArrTabFlt * * Description: This function is used to convert a Generic CoordArrays * to a CoordArraysFloat object. * * In Args: * * Out Args: * * Scope: private * Returns: NhlErrorTypes * Side Effect: */ /*ARGSUSED*/ static NhlErrorTypes CvtCArrToCArrTabFlt #if NhlNeedProto ( NrmValue *from, NrmValue *to, NhlConvertArgList args, int num_args ) #else (from,to,args,num_args) NrmValue *from; NrmValue *to; NhlConvertArgList args; int num_args; #endif { char func[]="CvtCArrToCArrTabFlt"; NhlErrorTypes ret = NhlNOERROR; NhlCoordArraysLayer carrl; NhlCoordArraysLayerPart *cap; int fltid; NhlCoordArrTableFloatLayer fltl; NhlCoordArrTableFloatLayerPart *fltlp; NrmValue fval,tval; if(num_args != 0){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:Called w/wrong args",func); return NhlFATAL; } carrl = (NhlCoordArraysLayer)_NhlGetLayer(from->data.intval); if((carrl == NULL)|| (carrl->base.layer_class != NhlcoordArraysClass)){ NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:Called w/ improper \"from\" object",func); return NhlFATAL; } cap = &carrl->carr; ret = NhlALCreate(&fltid,"no.name",NhlcoordArrTableFloatClass, carrl->base.id,NULL,0); *(int*)to->data.ptrval = fltid; fltl = (NhlCoordArrTableFloatLayer)_NhlGetLayer(fltid); if((ret < NhlWARNING) || (fltl == NULL)){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:Unable to convert Data", func); return NhlFATAL; } fltlp = &fltl->flt; ret = FlushObj(XDIM,cap); if(ret < NhlWARNING) return ret; ret = FlushObj(YDIM,cap); if(ret < NhlWARNING) return ret; ret = CreateFloatTable(NhlNcaXCast,NhlNcaYCast,func,cap->my_xarray, cap->my_yarray,cap->xcast,cap->ycast,&fltlp->xtable, &fltlp->xtable_lens); if(ret < NhlWARNING) return ret; ret = CreateFloatTable(NhlNcaYCast,NhlNcaXCast,func,cap->my_yarray, cap->my_xarray,cap->ycast,cap->xcast,&fltlp->ytable, &fltlp->ytable_lens); if(ret < NhlWARNING) return ret; if(cap->my_missing_x){ fltlp->missing_x = *(float*)cap->my_missing_x->data; fltlp->missing_x_set = True; } else fltlp->missing_x_set = False; if(cap->my_missing_y){ fltlp->missing_y = *(float*)cap->my_missing_y->data; fltlp->missing_y_set = True; } else fltlp->missing_y_set = False; if(cap->max_x->typeQ == floatQ) fltlp->max_x = *(float *)cap->max_x->data; else{ fval.size = sizeof(NhlGenArray); fval.data.ptrval = cap->max_x; tval.size = sizeof(float); tval.data.ptrval = &fltlp->max_x; ret = _NhlReConvertData(genQ,floatQ,&fval,&tval); if(ret < NhlINFO){ NhlPError(ret,NhlEUNKNOWN,"%s:Unable to convert %s to float", func,NhlNctXMaxV); return ret; } } if(cap->min_x->typeQ == floatQ) fltlp->min_x = *(float *)cap->min_x->data; else{ fval.size = sizeof(NhlGenArray); fval.data.ptrval = cap->min_x; tval.size = sizeof(float); tval.data.ptrval = &fltlp->min_x; ret = _NhlReConvertData(genQ,floatQ,&fval,&tval); if(ret < NhlINFO){ NhlPError(ret,NhlEUNKNOWN,"%s:Unable to convert %s to float", func,NhlNctXMinV); return ret; } } if(cap->max_y->typeQ == floatQ) fltlp->max_y = *(float *)cap->max_y->data; else{ fval.size = sizeof(NhlGenArray); fval.data.ptrval = cap->max_y; tval.size = sizeof(float); tval.data.ptrval = &fltlp->max_y; ret = _NhlReConvertData(genQ,floatQ,&fval,&tval); if(ret < NhlINFO){ NhlPError(ret,NhlEUNKNOWN,"%s:Unable to convert %s to float", func,NhlNctYMaxV); return ret; } } if(cap->min_y->typeQ == floatQ) fltlp->min_y = *(float *)cap->min_y->data; else{ fval.size = sizeof(NhlGenArray); fval.data.ptrval = cap->min_y; tval.size = sizeof(float); tval.data.ptrval = &fltlp->min_y; ret = _NhlReConvertData(genQ,floatQ,&fval,&tval); if(ret < NhlINFO){ NhlPError(ret,NhlEUNKNOWN,"%s:Unable to convert %s to float", func,NhlNctYMinV); return ret; } } return ret; } /************************************************************************ * * * Methode definitions * * * ************************************************************************/ /* * Function: CoordArraysClassInitialize * * Description: This function does one time initialization needed by the * CoordArraysClass. * * In Args: * * Out Args: * * Scope: static * Returns: NhlErrorTypes * Side Effect: */ static NhlErrorTypes CoordArraysClassInitialize #if NhlNeedProto ( void ) #else () #endif { NhlErrorTypes ret,lret; _NhlEnumVals cast_mode[] = { {NhlSINGLEVECTOR, "SingleVector"}, {NhlMULTIPLEVECTORS, "MultipleVectors"}, {NhlSPLITVECTORS, "SplitVectors"} }; floatQ = NrmStringToQuark(NhlTFloat); genQ = NrmStringToQuark(NhlTGenArray); floatgenQ = NrmStringToQuark(NhlTFloatGenArray); xarrQ = NrmStringToQuark(NhlNcaXArray); yarrQ = NrmStringToQuark(NhlNcaYArray); xmissQ = NrmStringToQuark(NhlNcaXMissingV); ymissQ = NrmStringToQuark(NhlNcaYMissingV); xmaxQ = NrmStringToQuark(NhlNcaXMaxV); ymaxQ = NrmStringToQuark(NhlNcaYMaxV); xminQ = NrmStringToQuark(NhlNcaXMinV); yminQ = NrmStringToQuark(NhlNcaYMinV); lret = _NhlRegisterEnumType(NhlcoordArraysClass,NhlTcaCastMode, cast_mode,NhlNumber(cast_mode)); ret = NhlRegisterConverter(NhlbaseClass, NhlcoordArraysClass->base_class.class_name, NhlcoordArrTableFloatClass->base_class.class_name, CvtCArrToCArrTabFlt,NULL,0,False,NULL); return MIN(ret,lret); } static NhlErrorTypes CheckArray #if NhlNeedProto ( NhlGenArray arr, NhlcaCastMode *cast, NhlBoolean *cast_set, NhlString arr_res, NhlString cast_res, NhlBoolean *imp ) #else (arr,cast,cast_set,arr_res,cast_res,imp) NhlGenArray arr; NhlcaCastMode *cast; NhlBoolean *cast_set; NhlString arr_res; NhlString cast_res; NhlBoolean *imp; #endif { char func[]="CheckArray"; NhlErrorTypes ret = NhlNOERROR; int num_elements; if(arr != NULL){ if((arr->num_dimensions > 2) || (arr->num_dimensions < 1)){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:%s must be a one or two dimensional array:ignoring", func,arr_res); return NhlFATAL; } } else *imp = True; if(*cast_set){ if((*imp) && (*cast != NhlSINGLEVECTOR)){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:%s must be %d if %s is implied",func, cast_res,NhlSINGLEVECTOR,arr_res); ret = MIN(ret,NhlWARNING); *cast = NhlSINGLEVECTOR; } } else{ *cast_set = True; if((*imp) || (arr->num_dimensions == 1)) *cast = NhlSINGLEVECTOR; else *cast = NhlMULTIPLEVECTORS; } if(!*imp){ if((arr->num_dimensions == 2) && (*cast == NhlMULTIPLEVECTORS)){ num_elements = arr->len_dimensions[1]; } else{ num_elements = arr->len_dimensions[0]; } if(num_elements < 2){ NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:Each vector in the %s array must have at least 2 elements", func,arr_res); return NhlFATAL; } } return ret; } /* * Function: CopyArray * * Description: * * In Args: * * Out Args: * * Scope: * Returns: * Side Effect: */ static NhlErrorTypes CopyArray #if NhlNeedProto ( NhlGenArray *arr, NhlGenArray *my_arr, NhlBoolean copy, _NhlConvertContext *ctxt ) #else (arr,my_arr,copy,ctxt) NhlGenArray *arr; NhlGenArray *my_arr; NhlBoolean copy; _NhlConvertContext *ctxt; #endif { NhlErrorTypes ret; if(!*arr){ *my_arr = NULL; return NhlNOERROR; } if(((*arr)->typeQ != floatQ) && copy){ ret = MyArray(my_arr,*arr,ctxt); if(ret < NhlWARNING) return ret; *arr = *my_arr; return ret; } *my_arr = *arr = _NhlCopyGenArray(*arr,copy); if(*arr == NULL) return NhlFATAL; return NhlNOERROR; } /* * Function: CoordArraysInitialize * * Description: This function initializes an instance of a CoordArrays * class object. * * In Args: * NhlClass lc, class * NhlLayer req, requested * NhlLayer new, new * _NhlArgList args, args * int nargs nargs * * Out Args: * * Scope: static * Returns: NhlErrorTypes * Side Effect: */ /*ARGSUSED*/ static NhlErrorTypes CoordArraysInitialize #if NhlNeedProto ( NhlClass lc, /* class */ NhlLayer req, /* requested */ NhlLayer new, /* new */ _NhlArgList args, /* args */ int nargs /* nargs */ ) #else (lc,req,new,args,nargs) NhlClass lc; /* class */ NhlLayer req; /* requested */ NhlLayer new; /* new */ _NhlArgList args; /* args */ int nargs; /* nargs */ #endif { char *func = "CoordArraysInitialize"; NhlCoordArraysLayer ncarr = (NhlCoordArraysLayer)new; NhlCoordArraysLayerPart *ncap = &ncarr->carr; NhlErrorTypes ret=NhlNOERROR,lret=NhlNOERROR; NhlBoolean impy = False, impx = False; ret = CheckArray(ncap->xarray,&ncap->xcast,&ncap->xcast_set, NhlNcaXArray,NhlNcaXCast,&impx); if(ret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:%s resource is invalid",func, NhlNcaXArray); return ret; } lret = CheckArray(ncap->yarray,&ncap->ycast,&ncap->ycast_set, NhlNcaYArray,NhlNcaYCast,&impy); if(lret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:%s resource is invalid",func, NhlNcaYArray); return lret; } ret = MIN(ret,lret); if(impx && impy){ NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:Cannot have Implied X and Y values",func); return NhlFATAL; } lret = CopyArray(&ncap->xarray,&ncap->my_xarray,ncap->copy_arrays, &ncap->xctxt); if(lret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:memory???",func); return lret; } ret = MIN(ret,lret); lret = CopyArray(&ncap->yarray,&ncap->my_yarray,ncap->copy_arrays, &ncap->yctxt); if(lret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN,"%s:memory???",func); return lret; } ret = MIN(ret,lret); if(ncap->missing_x){ ncap->missing_x = _NhlCopyGenArray(ncap->missing_x,True); if(!ncap->missing_x){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } } if(ncap->missing_y){ ncap->missing_y = _NhlCopyGenArray(ncap->missing_y,True); if(!ncap->missing_y){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } } if(ncap->max_x){ ncap->max_x = _NhlCopyGenArray(ncap->max_x,True); if(!ncap->max_x){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } ncap->sticky_max_x = True; } else ncap->sticky_max_x = False; if(ncap->max_y){ ncap->max_y = _NhlCopyGenArray(ncap->max_y,True); if(!ncap->max_y){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } ncap->sticky_max_y = True; } else ncap->sticky_max_y = False; if(ncap->min_x){ ncap->min_x = _NhlCopyGenArray(ncap->min_x,True); if(!ncap->min_x){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } ncap->sticky_min_x = True; } else ncap->sticky_min_x = False; if(ncap->min_y){ ncap->min_y = _NhlCopyGenArray(ncap->min_y,True); if(!ncap->min_y){ NhlPError(NhlFATAL,ENOMEM,"%s",func); return NhlFATAL; } ncap->sticky_min_y = True; } else ncap->sticky_min_y = False; return ret; } /* * Function: CoordArraysSetValues * * Description: ... * * In Args: * * Out Args: * * Scope: static * Returns: NhlErrorTypes * Side Effect: */ /*ARGSUSED*/ static NhlErrorTypes CoordArraysSetValues #if NhlNeedProto ( NhlLayer old, /* old */ NhlLayer req, /* requested */ NhlLayer new, /* new */ _NhlArgList args, /* args to set */ int nargs /* nargs */ ) #else (old,req,new,args,nargs) NhlLayer old; /* old */ NhlLayer req; /* requested */ NhlLayer new; /* new */ _NhlArgList args; /* args to set */ int nargs; /* nargs */ #endif { char func[] = "CoordArraysSetValues"; NhlErrorTypes ret = NhlNOERROR,lret = NhlNOERROR; NhlCoordArraysLayer ncarr = (NhlCoordArraysLayer)new; NhlCoordArraysLayer ocarr = (NhlCoordArraysLayer)old; NhlCoordArraysLayerPart *ncap = &ncarr->carr; NhlCoordArraysLayerPart *ocap = &ocarr->carr; NhlBoolean impx = False, impy = False; NhlBoolean status = False; NhlBoolean update_minmax = False; if(ncap->xarray != ocap->xarray){ ret = CheckArray(ncap->xarray,&ncap->xcast,&ncap->xcast_set, NhlNcaXArray,NhlNcaXCast,&impx); if(ret < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:invalid %s resource: resetting",func, NhlNcaXArray); ncap->xarray = ocap->xarray; ret = NhlWARNING; } } if(ncap->xarray == NULL) impx = True; if(ncap->yarray != ocap->yarray){ lret = CheckArray(ncap->yarray,&ncap->ycast,&ncap->ycast_set, NhlNcaYArray,NhlNcaYCast,&impy); if(lret < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:invalid %s resource: resetting",func, NhlNcaYArray); ncap->yarray = ocap->yarray; lret = NhlWARNING; } } ret = MIN(ret,lret); if(ncap->yarray == NULL) impy = True; if(impx && impy){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:Cannot have Implied X and Y values:resetting",func); ret = MIN(ret,NhlWARNING); ncap->xarray = ocap->xarray; ncap->yarray = ocap->yarray; } if((ncap->xarray != ocap->xarray) || (ncap->xarray && ncap->copy_arrays && !ncap->xarray->my_data)){ lret = CopyArray(&ncap->xarray,&ncap->my_xarray, ncap->copy_arrays,&ncap->xctxt); if(lret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:memory??? - resetting %s",func,NhlNcaXArray); ncap->xarray = ocap->xarray; ret = MIN(ret,lret); } else{ status = True; if(!ocap->xctxt) NhlFreeGenArray(ocap->xarray); } } if((ncap->yarray != ocap->yarray) || (ncap->yarray && ncap->copy_arrays && !ncap->yarray->my_data)){ lret = CopyArray(&ncap->yarray,&ncap->my_yarray, ncap->copy_arrays,&ncap->yctxt); if(lret < NhlWARNING){ NhlPError(NhlFATAL,NhlEUNKNOWN, "%s:memory??? - resetting %s",func,NhlNcaYArray); ncap->yarray = ocap->yarray; ret = MIN(ret,lret); } else{ status = True; if(!ocap->yctxt) NhlFreeGenArray(ocap->yarray); } } if(ncap->xcast != ocap->xcast) status = True; if(ncap->ycast != ocap->ycast) status = True; if(ncap->missing_x != ocap->missing_x){ ncap->missing_x = _NhlCopyGenArray(ncap->missing_x,True); if(!ncap->missing_x){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaXMissingV); ncap->missing_x = ocap->missing_x; ret = MIN(ret,NhlWARNING); } else{ status = True; ncap->my_missing_x = NULL; if(ocap->missing_x == ocap->my_missing_x) ocap->my_missing_x = NULL; NhlFreeGenArray(ocap->missing_x); NhlFreeGenArray(ocap->my_missing_x); } } if(ncap->missing_y != ocap->missing_y){ ncap->missing_y = _NhlCopyGenArray(ncap->missing_y,True); if(!ncap->missing_y){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaYMissingV); ncap->missing_y = ocap->missing_y; ret = MIN(ret,NhlWARNING); } else{ status = True; ncap->my_missing_y = NULL; if(ocap->missing_y == ocap->my_missing_y) ocap->my_missing_y = NULL; NhlFreeGenArray(ocap->missing_y); NhlFreeGenArray(ocap->my_missing_y); } } update_minmax = status; if(ncap->max_x != ocap->max_x){ ncap->max_x = _NhlCopyGenArray(ncap->max_x,True); if(!ncap->max_x){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaXMaxV); ncap->max_x = ocap->max_x; ret = MIN(ret,NhlWARNING); } else{ NhlFreeGenArray(ocap->max_x); ncap->sticky_max_x = True; status = True; } } else if(update_minmax && !ncap->sticky_max_x){ NhlFreeGenArray(ncap->max_x); ncap->max_x = NULL; } if(ncap->max_y != ocap->max_y){ ncap->max_y = _NhlCopyGenArray(ncap->max_y,True); if(!ncap->max_y){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaYMaxV); ncap->max_y = ocap->max_y; ret = MIN(ret,NhlWARNING); } else{ NhlFreeGenArray(ocap->max_y); ncap->sticky_max_y = True; status = True; } } else if(update_minmax && !ncap->sticky_max_y){ NhlFreeGenArray(ncap->max_y); ncap->max_y = NULL; } if(ncap->min_x != ocap->min_x){ ncap->min_x = _NhlCopyGenArray(ncap->min_x,True); if(!ncap->min_x){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaXMinV); ncap->min_x = ocap->min_x; ret = MIN(ret,NhlWARNING); } else{ NhlFreeGenArray(ocap->min_x); ncap->sticky_min_x = True; status = True; } } else if(update_minmax && !ncap->sticky_min_x){ NhlFreeGenArray(ncap->min_x); ncap->min_x = NULL; } if(ncap->min_y != ocap->min_y){ ncap->min_y = _NhlCopyGenArray(ncap->min_y,True); if(!ncap->min_y){ NhlPError(NhlWARNING,ENOMEM,"%s:resetting %s",func, NhlNcaYMinV); ncap->min_y = ocap->min_y; ret = MIN(ret,NhlWARNING); } else{ NhlFreeGenArray(ocap->min_y); ncap->sticky_min_y = True; status = True; } } else if(update_minmax && !ncap->sticky_min_y){ NhlFreeGenArray(ncap->min_y); ncap->min_y = NULL; } _NhlDataChanged((NhlDataItemLayer)new,status); return ret; } /* * Function: CoordArraysGetValues * * Description: ... * * In Args: * * Out Args: * * Scope: static * Returns: NhlErrorTypes * Side Effect: */ static NhlErrorTypes CoordArraysGetValues #if NhlNeedProto ( NhlLayer l, /* l */ _NhlArgList args, /* args to set */ int nargs /* nargs */ ) #else (l,args,nargs) NhlLayer l; /* l */ _NhlArgList args; /* args to set */ int nargs; /* nargs */ #endif { char func[] = "CoordArraysGetValues"; NhlErrorTypes ret = NhlNOERROR; int i; NhlCoordArraysLayer ca = (NhlCoordArraysLayer)l; NhlCoordArraysLayerPart *cap = &ca->carr; for(i=0;i < nargs;i++){ if((args[i].quark == xarrQ) && cap->xarray){ *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->xarray,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaXArray); ret = MIN(ret,NhlWARNING); } } else if((args[i].quark == yarrQ) && cap->yarray){ *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->yarray,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaYArray); ret = MIN(ret,NhlWARNING); } } else if((args[i].quark == xmissQ) && cap->missing_x){ *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->missing_x,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaXMissingV); ret = MIN(ret,NhlWARNING); } } else if((args[i].quark == ymissQ) && cap->missing_y){ *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->missing_y,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaYMissingV); ret = MIN(ret,NhlWARNING); } } else if(args[i].quark == xmaxQ){ if(!cap->max_x){ if(FlushObj(XDIM,cap) < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:Unable to determine %s", func,NhlNcaXMaxV); ret = MIN(ret,NhlWARNING); continue; } } *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->max_x,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaXMaxV); ret = MIN(ret,NhlWARNING); } } else if(args[i].quark == ymaxQ){ if(!cap->max_y){ if(FlushObj(YDIM,cap) < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:Unable to determine %s", func,NhlNcaYMaxV); ret = MIN(ret,NhlWARNING); continue; } } *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->max_y,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaYMaxV); ret = MIN(ret,NhlWARNING); } } else if(args[i].quark == xminQ){ if(!cap->min_x){ if(FlushObj(XDIM,cap) < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:Unable to determine %s", func,NhlNcaXMinV); ret = MIN(ret,NhlWARNING); continue; } } *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->min_x,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaXMinV); ret = MIN(ret,NhlWARNING); } } else if(args[i].quark == yminQ){ if(!cap->min_y){ if(FlushObj(YDIM,cap) < NhlWARNING){ NhlPError(NhlWARNING,NhlEUNKNOWN, "%s:Unable to determine %s", func,NhlNcaYMinV); ret = MIN(ret,NhlWARNING); continue; } } *(NhlGenArray*)args[i].value.ptrval = _NhlCopyGenArray(cap->min_y,True); if(*(NhlGenArray*)args[i].value.ptrval == NULL){ NhlPError(NhlWARNING,ENOMEM, "%s:Unable to allocate memory to retrieve %s", func,NhlNcaYMinV); ret = MIN(ret,NhlWARNING); } } } return ret; } /* * Function: CoordArraysDestroy * * Description: This function free's any memory that has been allocated * on behalf of this instance of the NhlCoordArraysClass. * * In Args: NhlLayer l * * Out Args: * * Scope: static * Returns: NhlErrorTypes * Side Effect: */ /*ARGSUSED*/ static NhlErrorTypes CoordArraysDestroy #if NhlNeedProto ( NhlLayer l /* layer to destroy */ ) #else (l) NhlLayer l; /* layer to destroy */ #endif { NhlCoordArraysLayer cl = (NhlCoordArraysLayer)l; NhlCoordArraysLayerPart *cap = &cl->carr; if(cap->my_xarray != cap->xarray) NhlFreeGenArray(cap->xarray); if(cap->my_yarray != cap->yarray) NhlFreeGenArray(cap->yarray); if(cap->xctxt) _NhlFreeConvertContext(cap->xctxt); else NhlFreeGenArray(cap->my_xarray); if(cap->yctxt) _NhlFreeConvertContext(cap->yctxt); else NhlFreeGenArray(cap->my_yarray); if (cap->my_missing_x == cap->missing_x) cap->my_missing_x = NULL; if (cap->my_missing_y == cap->missing_y) cap->my_missing_y = NULL; NhlFreeGenArray(cap->my_missing_x); NhlFreeGenArray(cap->my_missing_y); NhlFreeGenArray(cap->missing_x); NhlFreeGenArray(cap->missing_y); NhlFreeGenArray(cap->max_x); NhlFreeGenArray(cap->max_y); NhlFreeGenArray(cap->min_x); NhlFreeGenArray(cap->min_y); return NhlNOERROR; } /************************************************************************ * * * Private API for sub-classes * * * ************************************************************************/ /* none yet */ /************************************************************************ * * * Public API * * * ************************************************************************/ /* none yet */

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/* Read analog voltage on slow analog input */ #include <stdio.h> #include <stdlib.h> #include "rp.h" int main (int argc, char **argv) { float value [4]; uint32_t raw [4]; // Initialization of API if (rp_Init() != RP_OK) { fprintf(stderr, "Red Pitaya API init failed!\n"); return EXIT_FAILURE; } // Measure each XADC input voltage for (int i=0; i<4; i++) { rp_AIpinGetValue(i, &value[i],&raw[i]); printf("Measured voltage on AI[%i] = %1.2fV\n", i, value[i]); } // Releasing resources rp_Release(); return EXIT_SUCCESS; }

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/* tempconv - Converts temperature from Farenheight to Centigrade */ /* and Kelvin */ /* Written by: C. Severance - Tue Dec 7 23:01:34 EST 1993 */ main() { float cent,faren,kelvin; /* Prompt the user for the Farenheight temperature */ printf("enter the farenheight temperature -"); scanf("%f",&faren); /* Calculate the centigrade temperature */ cent = ( faren - 32.0 ) * ( 5.0 / 9.0 ) ; printf("centigrade temperature is - %f\n",cent); /* Calculate the kelvin temperature */ kelvin = cent + 273.0; printf(" kelvin temperature is - %f\n",kelvin); }

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/* qhasm: enter ge_p2_dbl */ /* qhasm: fe X1 */ /* qhasm: fe Y1 */ /* qhasm: fe Z1 */ /* qhasm: fe A */ /* qhasm: fe AA */ /* qhasm: fe XX */ /* qhasm: fe YY */ /* qhasm: fe B */ /* qhasm: fe X3 */ /* qhasm: fe Y3 */ /* qhasm: fe Z3 */ /* qhasm: fe T3 */ /* qhasm: XX=X1^2 */ /* asm 1: fe_sq(>XX=fe#1,<X1=fe#11); */ /* asm 2: fe_sq(>XX=r->X,<X1=p->X); */ fe_sq(r->X,p->X); /* qhasm: YY=Y1^2 */ /* asm 1: fe_sq(>YY=fe#3,<Y1=fe#12); */ /* asm 2: fe_sq(>YY=r->Z,<Y1=p->Y); */ fe_sq(r->Z,p->Y); /* qhasm: B=2*Z1^2 */ /* asm 1: fe_sq2(>B=fe#4,<Z1=fe#13); */ /* asm 2: fe_sq2(>B=r->T,<Z1=p->Z); */ fe_sq2(r->T,p->Z); /* qhasm: A=X1+Y1 */ /* asm 1: fe_add(>A=fe#2,<X1=fe#11,<Y1=fe#12); */ /* asm 2: fe_add(>A=r->Y,<X1=p->X,<Y1=p->Y); */ fe_add(r->Y,p->X,p->Y); /* qhasm: AA=A^2 */ /* asm 1: fe_sq(>AA=fe#5,<A=fe#2); */ /* asm 2: fe_sq(>AA=t0,<A=r->Y); */ fe_sq(t0,r->Y); /* qhasm: Y3=YY+XX */ /* asm 1: fe_add(>Y3=fe#2,<YY=fe#3,<XX=fe#1); */ /* asm 2: fe_add(>Y3=r->Y,<YY=r->Z,<XX=r->X); */ fe_add(r->Y,r->Z,r->X); /* qhasm: Z3=YY-XX */ /* asm 1: fe_sub(>Z3=fe#3,<YY=fe#3,<XX=fe#1); */ /* asm 2: fe_sub(>Z3=r->Z,<YY=r->Z,<XX=r->X); */ fe_sub(r->Z,r->Z,r->X); /* qhasm: X3=AA-Y3 */ /* asm 1: fe_sub(>X3=fe#1,<AA=fe#5,<Y3=fe#2); */ /* asm 2: fe_sub(>X3=r->X,<AA=t0,<Y3=r->Y); */ fe_sub(r->X,t0,r->Y); /* qhasm: T3=B-Z3 */ /* asm 1: fe_sub(>T3=fe#4,<B=fe#4,<Z3=fe#3); */ /* asm 2: fe_sub(>T3=r->T,<B=r->T,<Z3=r->Z); */ fe_sub(r->T,r->T,r->Z); /* qhasm: return */

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elf-x86-x32.c

/* * ELF object format helpers - x86:x32 * * Copyright (C) 2012 Michael Urman and H.J. Lu * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include <util.h> #include <libyasm.h> #define YASM_OBJFMT_ELF_INTERNAL #include "elf.h" #include "elf-machine.h" static elf_machine_ssym elf_x86_x32_ssyms[] = { {"plt", ELF_SSYM_SYM_RELATIVE, R_X86_64_PLT32, 32}, {"gotpcrel", ELF_SSYM_SYM_RELATIVE, R_X86_64_GOTPCREL, 32}, {"tlsgd", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_TLSGD, 32}, {"tlsld", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_TLSLD, 32}, {"gottpoff", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_GOTTPOFF, 32}, {"tpoff", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_TPOFF32, 32}, {"dtpoff", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_DTPOFF32, 32}, {"got", ELF_SSYM_SYM_RELATIVE, R_X86_64_GOT32, 32}, {"tlsdesc", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_GOTPC32_TLSDESC, 32}, {"tlscall", ELF_SSYM_SYM_RELATIVE|ELF_SSYM_THREAD_LOCAL, R_X86_64_TLSDESC_CALL, 32} }; static int elf_x86_x32_accepts_reloc(size_t val, yasm_symrec *wrt) { if (wrt) { const elf_machine_ssym *ssym = (elf_machine_ssym *) yasm_symrec_get_data(wrt, &elf_ssym_symrec_data); if (!ssym || val != ssym->size) return 0; return 1; } return (val&(val-1)) ? 0 : ((val & (8|16|32)) != 0); } static void elf_x86_x32_write_symtab_entry(unsigned char *bufp, elf_symtab_entry *entry, yasm_intnum *value_intn, yasm_intnum *size_intn) { YASM_WRITE_32_L(bufp, entry->name ? entry->name->index : 0); YASM_WRITE_32I_L(bufp, value_intn); YASM_WRITE_32I_L(bufp, size_intn); YASM_WRITE_8(bufp, ELF32_ST_INFO(entry->bind, entry->type)); YASM_WRITE_8(bufp, ELF32_ST_OTHER(entry->vis)); if (entry->sect) { elf_secthead *shead = yasm_section_get_data(entry->sect, &elf_section_data); if (!shead) yasm_internal_error(N_("symbol references section without data")); YASM_WRITE_16_L(bufp, shead->index); } else { YASM_WRITE_16_L(bufp, entry->index); } } static void elf_x86_x32_write_secthead(unsigned char *bufp, elf_secthead *shead) { YASM_WRITE_32_L(bufp, shead->name ? shead->name->index : 0); YASM_WRITE_32_L(bufp, shead->type); YASM_WRITE_32_L(bufp, shead->flags); YASM_WRITE_32_L(bufp, 0); /* vmem address */ YASM_WRITE_32_L(bufp, shead->offset); YASM_WRITE_32I_L(bufp, shead->size); YASM_WRITE_32_L(bufp, shead->link); YASM_WRITE_32_L(bufp, shead->info); YASM_WRITE_32_L(bufp, shead->align); YASM_WRITE_32_L(bufp, shead->entsize); } static void elf_x86_x32_write_secthead_rel(unsigned char *bufp, elf_secthead *shead, elf_section_index symtab_idx, elf_section_index sindex) { yasm_intnum *nreloc; yasm_intnum *relocsize; YASM_WRITE_32_L(bufp, shead->rel_name ? shead->rel_name->index : 0); YASM_WRITE_32_L(bufp, SHT_RELA); YASM_WRITE_32_L(bufp, 0); YASM_WRITE_32_L(bufp, 0); YASM_WRITE_32_L(bufp, shead->rel_offset); nreloc = yasm_intnum_create_uint(shead->nreloc); relocsize = yasm_intnum_create_uint(RELOC32A_SIZE); yasm_intnum_calc(relocsize, YASM_EXPR_MUL, nreloc); YASM_WRITE_32I_L(bufp, relocsize); /* size */ yasm_intnum_destroy(nreloc); yasm_intnum_destroy(relocsize); YASM_WRITE_32_L(bufp, symtab_idx); /* link: symtab index */ YASM_WRITE_32_L(bufp, shead->index); /* info: relocated's index */ YASM_WRITE_32_L(bufp, RELOC32_ALIGN); /* align */ YASM_WRITE_32_L(bufp, RELOC32A_SIZE); /* entity size */ } static void elf_x86_x32_handle_reloc_addend(yasm_intnum *intn, elf_reloc_entry *reloc, unsigned long offset) { /* .rela: copy value out as addend, replace original with 0 */ reloc->addend = yasm_intnum_copy(intn); yasm_intnum_zero(intn); } static unsigned int elf_x86_x32_map_reloc_info_to_type(elf_reloc_entry *reloc) { if (reloc->wrt) { const elf_machine_ssym *ssym = (elf_machine_ssym *) yasm_symrec_get_data(reloc->wrt, &elf_ssym_symrec_data); if (!ssym || reloc->valsize != ssym->size) yasm_internal_error(N_("Unsupported WRT")); /* Force TLS type; this is required by the linker. */ if (ssym->sym_rel & ELF_SSYM_THREAD_LOCAL) { elf_symtab_entry *esym; esym = yasm_symrec_get_data(reloc->reloc.sym, &elf_symrec_data); if (esym) esym->type = STT_TLS; } /* Map PC-relative GOT to appropriate relocation */ if (reloc->rtype_rel && ssym->reloc == R_X86_64_GOT32) return (unsigned char) R_X86_64_GOTPCREL; return (unsigned char) ssym->reloc; } else if (reloc->is_GOT_sym && reloc->valsize == 32) { return (unsigned char) R_X86_64_GOTPC32; } else if (reloc->is_GOT_sym && reloc->valsize == 64) { yasm_internal_error(N_("Unsupported relocation size")); } else if (reloc->rtype_rel) { switch (reloc->valsize) { case 8: return (unsigned char) R_X86_64_PC8; case 16: return (unsigned char) R_X86_64_PC16; case 32: return (unsigned char) R_X86_64_PC32; default: yasm_internal_error(N_("Unsupported relocation size")); } } else { switch (reloc->valsize) { case 8: return (unsigned char) R_X86_64_8; case 16: return (unsigned char) R_X86_64_16; case 32: return (unsigned char) R_X86_64_32; case 64: return (unsigned char) R_X86_64_64; default: yasm_internal_error(N_("Unsupported relocation size")); } } return 0; } static void elf_x86_x32_write_reloc(unsigned char *bufp, elf_reloc_entry *reloc, unsigned int r_type, unsigned int r_sym) { YASM_WRITE_32I_L(bufp, reloc->reloc.addr); YASM_WRITE_32_L(bufp, ELF32_R_INFO((unsigned long)r_sym, (unsigned char)r_type)); if (reloc->addend) YASM_WRITE_32I_L(bufp, reloc->addend); else { YASM_WRITE_32_L(bufp, 0); } } static void elf_x86_x32_write_proghead(unsigned char **bufpp, elf_offset secthead_addr, unsigned long secthead_count, elf_section_index shstrtab_index) { unsigned char *bufp = *bufpp; unsigned char *buf = bufp-4; YASM_WRITE_8(bufp, ELFCLASS32); /* elf class */ YASM_WRITE_8(bufp, ELFDATA2LSB); /* data encoding :: MSB? */ YASM_WRITE_8(bufp, EV_CURRENT); /* elf version */ YASM_WRITE_8(bufp, ELFOSABI_SYSV); /* os/abi */ YASM_WRITE_8(bufp, 0); /* SYSV v3 ABI=0 */ while (bufp-buf < EI_NIDENT) /* e_ident padding */ YASM_WRITE_8(bufp, 0); YASM_WRITE_16_L(bufp, ET_REL); /* e_type - object file */ YASM_WRITE_16_L(bufp, EM_X86_64); /* e_machine - or others */ YASM_WRITE_32_L(bufp, EV_CURRENT); /* elf version */ YASM_WRITE_32_L(bufp, 0); /* e_entry */ YASM_WRITE_32_L(bufp, 0); /* e_phoff */ YASM_WRITE_32_L(bufp, secthead_addr); /* e_shoff secthead off */ YASM_WRITE_32_L(bufp, 0); /* e_flags */ YASM_WRITE_16_L(bufp, EHDR32_SIZE); /* e_ehsize */ YASM_WRITE_16_L(bufp, 0); /* e_phentsize */ YASM_WRITE_16_L(bufp, 0); /* e_phnum */ YASM_WRITE_16_L(bufp, SHDR32_SIZE); /* e_shentsize */ YASM_WRITE_16_L(bufp, secthead_count); /* e_shnum */ YASM_WRITE_16_L(bufp, shstrtab_index); /* e_shstrndx */ *bufpp = bufp; } const elf_machine_handler elf_machine_handler_x86_x32 = { "x86", "x32", ".rela", SYMTAB32_SIZE, SYMTAB32_ALIGN, RELOC32A_SIZE, SHDR32_SIZE, EHDR32_SIZE, elf_x86_x32_accepts_reloc, elf_x86_x32_write_symtab_entry, elf_x86_x32_write_secthead, elf_x86_x32_write_secthead_rel, elf_x86_x32_handle_reloc_addend, elf_x86_x32_map_reloc_info_to_type, elf_x86_x32_write_reloc, elf_x86_x32_write_proghead, elf_x86_x32_ssyms, sizeof(elf_x86_x32_ssyms)/sizeof(elf_x86_x32_ssyms[0]), 32 };

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/* To be compiled as a shared library. Function to be called: extract_subchain Extract chain blocks that intersect the requested region. You can request subchain for the target or the query genome. Usage: extract_subchain [chain] [q/t] [target/query genome range] Arguments: chain -> string, a chain itself mode_cd -> char, "q" or "t" -> stands or "query" or "target" genome search_region -> string formatted as chrom:start-end Region in the query or reference (depending on the mode param) Function extracts chain blocks that intersect this region Output structure: list of strings each string except the last one contains the following: chain block start and end in the reference, chain block start and end in the query values are space-separated each of those chain blocks intersect the region of interest (which is specified) The last string is "END" Author: Bogdan Kirilenko, 2020; */ #include <stdio.h> #include <string.h> #include <stdlib.h> #include <unistd.h> #include <stdbool.h> #include <stdint.h> #include "chain.h" #define MAXCHAR 255 #define ALLOC_START 500 #define ALLOC_EXT 75 #define MEM_CHUNK 5 char ** extract_subchain(char *chain, char *mode_ch, char *search_region) { // read the chain file OR stdin // read genomic range mode bool mode; // the region we are interested in might lie in the target // as well as in the query genome if (strcmp(mode_ch, "t") == 0) { mode = true; // meaning it is target genome } else if (strcmp(mode_ch, "q") == 0) { mode = false; // so query genome } else { // wrong parameter, need either t or q fprintf(stderr, "Error! Either q or t parameter requested!\n"); fprintf(stderr, "Assigned to T automatically\n"); mode = true; } // parse the range | chrN:X-Y struct Regions request_region; char *reg_split = strtok(search_region, ":"); strcpy(request_region.chrom, reg_split); reg_split = strtok(NULL, ":"); char *split_range = strtok(reg_split, "-"); request_region.start = strtol(split_range, NULL, 10); split_range = strtok(NULL, "-"); request_region.end = strtol(split_range, NULL, 10); // state of the program // if reading -> we're going throw the region of interest bool head_caught = false; bool reading = false; // variables describing the block // variables called as pointers BUT // they are not pointers! (in C-meaning) int t_start_pointer = 0; int q_start_pointer = 0; int blockTStarts = 0; int blockTEnds = 0; int blockQStarts = 0; int blockQEnds = 0; int req_block_starts = 0; int req_block_ends = 0; struct Chain_info in_chain_head; unsigned long long int rows_added = 0; char * curLine = chain; // answer is an array of strings (array) // we don't know the size of this array now // so will dynamically reallocate memory for this unsigned long long int arr_size = ALLOC_START; char ** answer = (char**)malloc(sizeof(char*) * arr_size); while (curLine) { // deal with reading line-by-line business // we are not reading a file, it's just a string char * nextLine = strchr(curLine, '\n'); if (nextLine) { *nextLine = '\0'; } // parse head if it wasn't // it must happen to the first line if (!head_caught) { head_caught = true; // should happen only once in_chain_head = parse_head(curLine); // mark starting position t_start_pointer = in_chain_head.tStart; q_start_pointer = in_chain_head.qStart; // invert coordinates if needed // if strand is negative, we need to do this operation // read chain file docs for more information if ((!in_chain_head.tStrand && mode) || (!in_chain_head.qStrand && !mode)) { int temp = request_region.start; int req_chrom_size = mode ? in_chain_head.tSize : in_chain_head.qSize; request_region.start = req_chrom_size - request_region.end; request_region.end = req_chrom_size - temp; } // check chrom, it the requested region has a different chrom, // it is definitely wrong! // if we are interested in the reference region at chrom 1 // and provided chain aligned to chrom 2 -> something is definitely wrong! if (mode && strcmp(request_region.chrom, in_chain_head.tName) != 0) { fprintf(stderr, "Error! Target genome chrom differs in chain and requested region!\n"); break; } // check this also for the query else if (!mode && strcmp(request_region.chrom, in_chain_head.qName) != 0) { fprintf(stderr, "Error! Query genome chrom differs in chain and requested region!\n"); break; } } // end header parsing // we are reading a block, so update variables struct Block block = parse_block(curLine); // convert to absolute coordinates blockTStarts = t_start_pointer; blockQStarts = q_start_pointer; blockTEnds = blockTStarts + block.size; blockQEnds = blockQStarts + block.size; t_start_pointer = blockTEnds + block.dt; q_start_pointer = blockQEnds + block.dq; // then restore newline-char, just to be tidy if (nextLine) *nextLine = '\n'; curLine = nextLine ? (nextLine + 1) : NULL; // depending on mode we are interested in we look at // either the target or the query genome req_block_starts = mode ? blockTStarts : blockQStarts; req_block_ends = mode ? blockTEnds : blockQEnds; // these conditions are here to check whether anything of this is true: // 1) we haven't read the chain yet but just reached the region of interest // 2) we finished reading already and are outside the region of interest // conceptually, these conditions are mutually exclusive // if we're not reading yet but we just reached the region of interest // then start reading if (!reading && req_block_ends >= request_region.start) { // ---chainchainchainchainchain------ // ----regionregion------------------ // ^ we are here reading = true; // for each row we allocate a string in the answer answer[rows_added] = (char*)malloc(MAXCHAR * sizeof(char)); // and write this block to answer sprintf(answer[rows_added], "%d %d %d %d\n", blockTStarts, blockTEnds, blockQStarts, blockQEnds); rows_added++; // it is the first row --> a answer has place a priori continue; } else if (req_block_starts >= request_region.end) { // we have already read the region of interest // ---chainchainchainchainchain------ // ----regionregion------------------ // ^ we are here // we can simply stop reading chain then break; } if (reading) { // we are reading the chain now // need to add a block in the result // ---chainchainchainchainchain------ // ----regionregion------------------ // ^ we are here answer[rows_added] = (char*)malloc(MAXCHAR * sizeof(char)); sprintf(answer[rows_added], "%d %d %d %d\n", blockTStarts, blockTEnds, blockQStarts, blockQEnds); rows_added++; if (rows_added + MEM_CHUNK > arr_size) // make sure that we have allocated enough memory { // need to realloc answer array arr_size += ALLOC_EXT; answer = (char**)realloc(answer, sizeof(char*) * arr_size); } } // if not reading: just go to the next block // no need to write this condition } // finish answer with END // will be simpler to parse the output in the python func answer[rows_added] = (char*)malloc(MAXCHAR * sizeof(char)); sprintf(answer[rows_added], "END"); return answer; } int main() { // should be compiled with -fPIC and -shared flags! printf("Warning! This code is not intended to be compiled as a standalone tool.\n"); printf("Please compile this file with -fPIC and -shared flags.\n"); printf("and create the /modules/extract_subchain_slib.so shared library file.\n"); return 0; }

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/src/Game/GM_CameraSetAlertMask_80030850.c

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FoxdieTeam/mgs_reversing

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null

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C

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c

GM_CameraSetAlertMask_80030850.c

#include "linker.h" extern int dword_800ABA94; int SECTION(".sbss") dword_800ABA94; void GM_CameraSetAlertMask_80030850(int a1, int a2) { int v2; int result; if ((a2 & 2) != 0) { v2 = 1 << a1; } else { v2 = 0; } result = ~(1 << a1); dword_800ABA94 = (dword_800ABA94 & result) | v2; }

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/SOFTWARE/A64-TERES/linux-a64/drivers/staging/iio/meter/ade7753.c

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[ "Linux-syscall-note", "GPL-2.0-only", "GPL-1.0-or-later", "LicenseRef-scancode-free-unknown", "Apache-2.0" ]

permissive

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refs/heads/rel3

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ade7753.c

/* * ADE7753 Single-Phase Multifunction Metering IC with di/dt Sensor Interface * * Copyright 2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/delay.h> #include <linux/mutex.h> #include <linux/device.h> #include <linux/kernel.h> #include <linux/spi/spi.h> #include <linux/slab.h> #include <linux/sysfs.h> #include <linux/list.h> #include <linux/module.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> #include "meter.h" #include "ade7753.h" static int ade7753_spi_write_reg_8(struct device *dev, u8 reg_address, u8 val) { int ret; struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); mutex_lock(&st->buf_lock); st->tx[0] = ADE7753_WRITE_REG(reg_address); st->tx[1] = val; ret = spi_write(st->us, st->tx, 2); mutex_unlock(&st->buf_lock); return ret; } static int ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, u16 value) { int ret; struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); mutex_lock(&st->buf_lock); st->tx[0] = ADE7753_WRITE_REG(reg_address); st->tx[1] = (value >> 8) & 0xFF; st->tx[2] = value & 0xFF; ret = spi_write(st->us, st->tx, 3); mutex_unlock(&st->buf_lock); return ret; } static int ade7753_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); ssize_t ret; ret = spi_w8r8(st->us, ADE7753_READ_REG(reg_address)); if (ret < 0) { dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X", reg_address); return ret; } *val = ret; return 0; } static int ade7753_spi_read_reg_16(struct device *dev, u8 reg_address, u16 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); ssize_t ret; ret = spi_w8r16(st->us, ADE7753_READ_REG(reg_address)); if (ret < 0) { dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X", reg_address); return ret; } *val = ret; *val = be16_to_cpup(val); return 0; } static int ade7753_spi_read_reg_24(struct device *dev, u8 reg_address, u32 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); int ret; struct spi_transfer xfers[] = { { .tx_buf = st->tx, .bits_per_word = 8, .len = 1, }, { .rx_buf = st->tx, .bits_per_word = 8, .len = 3, } }; mutex_lock(&st->buf_lock); st->tx[0] = ADE7753_READ_REG(reg_address); ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); if (ret) { dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X", reg_address); goto error_ret; } *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2]; error_ret: mutex_unlock(&st->buf_lock); return ret; } static ssize_t ade7753_read_8bit(struct device *dev, struct device_attribute *attr, char *buf) { int ret; u8 val; struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); ret = ade7753_spi_read_reg_8(dev, this_attr->address, &val); if (ret) return ret; return sprintf(buf, "%u\n", val); } static ssize_t ade7753_read_16bit(struct device *dev, struct device_attribute *attr, char *buf) { int ret; u16 val; struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); ret = ade7753_spi_read_reg_16(dev, this_attr->address, &val); if (ret) return ret; return sprintf(buf, "%u\n", val); } static ssize_t ade7753_read_24bit(struct device *dev, struct device_attribute *attr, char *buf) { int ret; u32 val; struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); ret = ade7753_spi_read_reg_24(dev, this_attr->address, &val); if (ret) return ret; return sprintf(buf, "%u\n", val); } static ssize_t ade7753_write_8bit(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); int ret; long val; ret = strict_strtol(buf, 10, &val); if (ret) goto error_ret; ret = ade7753_spi_write_reg_8(dev, this_attr->address, val); error_ret: return ret ? ret : len; } static ssize_t ade7753_write_16bit(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); int ret; long val; ret = strict_strtol(buf, 10, &val); if (ret) goto error_ret; ret = ade7753_spi_write_reg_16(dev, this_attr->address, val); error_ret: return ret ? ret : len; } static int ade7753_reset(struct device *dev) { u16 val; ade7753_spi_read_reg_16(dev, ADE7753_MODE, &val); val |= 1 << 6; /* Software Chip Reset */ return ade7753_spi_write_reg_16(dev, ADE7753_MODE, val); } static ssize_t ade7753_write_reset(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { if (len < 1) return -1; switch (buf[0]) { case '1': case 'y': case 'Y': return ade7753_reset(dev); } return -1; } static IIO_DEV_ATTR_AENERGY(ade7753_read_24bit, ADE7753_AENERGY); static IIO_DEV_ATTR_LAENERGY(ade7753_read_24bit, ADE7753_LAENERGY); static IIO_DEV_ATTR_VAENERGY(ade7753_read_24bit, ADE7753_VAENERGY); static IIO_DEV_ATTR_LVAENERGY(ade7753_read_24bit, ADE7753_LVAENERGY); static IIO_DEV_ATTR_CFDEN(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_CFDEN); static IIO_DEV_ATTR_CFNUM(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CFNUM); static IIO_DEV_ATTR_CHKSUM(ade7753_read_8bit, ADE7753_CHKSUM); static IIO_DEV_ATTR_PHCAL(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_PHCAL); static IIO_DEV_ATTR_APOS(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_APOS); static IIO_DEV_ATTR_SAGCYC(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_SAGCYC); static IIO_DEV_ATTR_SAGLVL(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_SAGLVL); static IIO_DEV_ATTR_LINECYC(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_LINECYC); static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_WDIV); static IIO_DEV_ATTR_IRMS(S_IWUSR | S_IRUGO, ade7753_read_24bit, NULL, ADE7753_IRMS); static IIO_DEV_ATTR_VRMS(S_IRUGO, ade7753_read_24bit, NULL, ADE7753_VRMS); static IIO_DEV_ATTR_IRMSOS(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_IRMSOS); static IIO_DEV_ATTR_VRMSOS(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_VRMSOS); static IIO_DEV_ATTR_WGAIN(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_WGAIN); static IIO_DEV_ATTR_VAGAIN(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_VAGAIN); static IIO_DEV_ATTR_PGA_GAIN(S_IWUSR | S_IRUGO, ade7753_read_16bit, ade7753_write_16bit, ADE7753_GAIN); static IIO_DEV_ATTR_IPKLVL(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_IPKLVL); static IIO_DEV_ATTR_VPKLVL(S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_VPKLVL); static IIO_DEV_ATTR_IPEAK(S_IRUGO, ade7753_read_24bit, NULL, ADE7753_IPEAK); static IIO_DEV_ATTR_VPEAK(S_IRUGO, ade7753_read_24bit, NULL, ADE7753_VPEAK); static IIO_DEV_ATTR_VPERIOD(S_IRUGO, ade7753_read_16bit, NULL, ADE7753_PERIOD); static IIO_DEV_ATTR_CH_OFF(1, S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CH1OS); static IIO_DEV_ATTR_CH_OFF(2, S_IWUSR | S_IRUGO, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CH2OS); static int ade7753_set_irq(struct device *dev, bool enable) { int ret; u8 irqen; ret = ade7753_spi_read_reg_8(dev, ADE7753_IRQEN, &irqen); if (ret) goto error_ret; if (enable) irqen |= 1 << 3; /* Enables an interrupt when a data is present in the waveform register */ else irqen &= ~(1 << 3); ret = ade7753_spi_write_reg_8(dev, ADE7753_IRQEN, irqen); error_ret: return ret; } /* Power down the device */ static int ade7753_stop_device(struct device *dev) { u16 val; ade7753_spi_read_reg_16(dev, ADE7753_MODE, &val); val |= 1 << 4; /* AD converters can be turned off */ return ade7753_spi_write_reg_16(dev, ADE7753_MODE, val); } static int ade7753_initial_setup(struct iio_dev *indio_dev) { int ret; struct device *dev = &indio_dev->dev; struct ade7753_state *st = iio_priv(indio_dev); /* use low spi speed for init */ st->us->mode = SPI_MODE_3; spi_setup(st->us); /* Disable IRQ */ ret = ade7753_set_irq(dev, false); if (ret) { dev_err(dev, "disable irq failed"); goto err_ret; } ade7753_reset(dev); msleep(ADE7753_STARTUP_DELAY); err_ret: return ret; } static ssize_t ade7753_read_frequency(struct device *dev, struct device_attribute *attr, char *buf) { int ret, len = 0; u16 t; int sps; ret = ade7753_spi_read_reg_16(dev, ADE7753_MODE, &t); if (ret) return ret; t = (t >> 11) & 0x3; sps = 27900 / (1 + t); len = sprintf(buf, "%d\n", sps); return len; } static ssize_t ade7753_write_frequency(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); unsigned long val; int ret; u16 reg, t; ret = strict_strtol(buf, 10, &val); if (ret) return ret; if (val == 0) return -EINVAL; mutex_lock(&indio_dev->mlock); t = (27900 / val); if (t > 0) t--; if (t > 1) st->us->max_speed_hz = ADE7753_SPI_SLOW; else st->us->max_speed_hz = ADE7753_SPI_FAST; ret = ade7753_spi_read_reg_16(dev, ADE7753_MODE, &reg); if (ret) goto out; reg &= ~(3 << 11); reg |= t << 11; ret = ade7753_spi_write_reg_16(dev, ADE7753_MODE, reg); out: mutex_unlock(&indio_dev->mlock); return ret ? ret : len; } static IIO_DEV_ATTR_TEMP_RAW(ade7753_read_8bit); static IIO_CONST_ATTR(in_temp_offset, "-25 C"); static IIO_CONST_ATTR(in_temp_scale, "0.67 C"); static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, ade7753_read_frequency, ade7753_write_frequency); static IIO_DEV_ATTR_RESET(ade7753_write_reset); static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("27900 14000 7000 3500"); static struct attribute *ade7753_attributes[] = { &iio_dev_attr_in_temp_raw.dev_attr.attr, &iio_const_attr_in_temp_offset.dev_attr.attr, &iio_const_attr_in_temp_scale.dev_attr.attr, &iio_dev_attr_sampling_frequency.dev_attr.attr, &iio_const_attr_sampling_frequency_available.dev_attr.attr, &iio_dev_attr_reset.dev_attr.attr, &iio_dev_attr_phcal.dev_attr.attr, &iio_dev_attr_cfden.dev_attr.attr, &iio_dev_attr_aenergy.dev_attr.attr, &iio_dev_attr_laenergy.dev_attr.attr, &iio_dev_attr_vaenergy.dev_attr.attr, &iio_dev_attr_lvaenergy.dev_attr.attr, &iio_dev_attr_cfnum.dev_attr.attr, &iio_dev_attr_apos.dev_attr.attr, &iio_dev_attr_sagcyc.dev_attr.attr, &iio_dev_attr_saglvl.dev_attr.attr, &iio_dev_attr_linecyc.dev_attr.attr, &iio_dev_attr_chksum.dev_attr.attr, &iio_dev_attr_pga_gain.dev_attr.attr, &iio_dev_attr_wgain.dev_attr.attr, &iio_dev_attr_choff_1.dev_attr.attr, &iio_dev_attr_choff_2.dev_attr.attr, &iio_dev_attr_wdiv.dev_attr.attr, &iio_dev_attr_irms.dev_attr.attr, &iio_dev_attr_vrms.dev_attr.attr, &iio_dev_attr_irmsos.dev_attr.attr, &iio_dev_attr_vrmsos.dev_attr.attr, &iio_dev_attr_vagain.dev_attr.attr, &iio_dev_attr_ipklvl.dev_attr.attr, &iio_dev_attr_vpklvl.dev_attr.attr, &iio_dev_attr_ipeak.dev_attr.attr, &iio_dev_attr_vpeak.dev_attr.attr, &iio_dev_attr_vperiod.dev_attr.attr, NULL, }; static const struct attribute_group ade7753_attribute_group = { .attrs = ade7753_attributes, }; static const struct iio_info ade7753_info = { .attrs = &ade7753_attribute_group, .driver_module = THIS_MODULE, }; static int ade7753_probe(struct spi_device *spi) { int ret; struct ade7753_state *st; struct iio_dev *indio_dev; /* setup the industrialio driver allocated elements */ indio_dev = iio_device_alloc(sizeof(*st)); if (indio_dev == NULL) { ret = -ENOMEM; goto error_ret; } /* this is only used for removal purposes */ spi_set_drvdata(spi, indio_dev); st = iio_priv(indio_dev); st->us = spi; mutex_init(&st->buf_lock); indio_dev->name = spi->dev.driver->name; indio_dev->dev.parent = &spi->dev; indio_dev->info = &ade7753_info; indio_dev->modes = INDIO_DIRECT_MODE; /* Get the device into a sane initial state */ ret = ade7753_initial_setup(indio_dev); if (ret) goto error_free_dev; ret = iio_device_register(indio_dev); if (ret) goto error_free_dev; return 0; error_free_dev: iio_device_free(indio_dev); error_ret: return ret; } /* fixme, confirm ordering in this function */ static int ade7753_remove(struct spi_device *spi) { struct iio_dev *indio_dev = spi_get_drvdata(spi); iio_device_unregister(indio_dev); ade7753_stop_device(&indio_dev->dev); iio_device_free(indio_dev); return 0; } static struct spi_driver ade7753_driver = { .driver = { .name = "ade7753", .owner = THIS_MODULE, }, .probe = ade7753_probe, .remove = ade7753_remove, }; module_spi_driver(ade7753_driver); MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); MODULE_DESCRIPTION("Analog Devices ADE7753/6 Single-Phase Multifunction Meter"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("spi:ade7753");

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/* ---------------------------------------------------------------------------- * SAM Software Package License * ---------------------------------------------------------------------------- * Copyright (c) 2016, Atmel Corporation * * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * - Redistributions of source code must retain the above copyright notice, * this list of conditions and the disclaimer below. * * Atmel's name may not be used to endorse or promote products derived from * this software without specific prior written permission. * * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ---------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- * Headers *----------------------------------------------------------------------------*/ #include <assert.h> #include "compiler.h" #include "dma/dma.h" #include "dma/dma_dmac.h" #include "errno.h" #include "irq/irq.h" #include "peripherals/pmc.h" /*---------------------------------------------------------------------------- * Local definitions *----------------------------------------------------------------------------*/ #ifdef CONFIG_SOC_SAM9XX5 #define DMAC_CFG_SRC_PER_MSB_Msk 0 #define DMAC_CFG_DST_PER_MSB_Msk 0 #define DMAC_CFG_SRC_PER_MSB(x) 0 #define DMAC_CFG_DST_PER_MSB(x) 0 #endif /*---------------------------------------------------------------------------- * Exported functions *----------------------------------------------------------------------------*/ /** * \brief Enable clock of the DMA peripheral, Enable the peripheral, * setup configuration register for transfer. * \param channel Channel pointer */ int dma_prepare_channel(struct _dma_channel* channel) { Dmac *dmac = channel->hw; if (channel->state == DMA_STATE_FREE) return -EPERM; else if (channel->state == DMA_STATE_STARTED) return -EBUSY; /* Clear status */ dmac_get_global_isr(dmac); /* Enable clock of the DMA peripheral */ pmc_configure_peripheral(get_dmac_id_from_addr(dmac), NULL, true); /* Clear status */ dmac_get_channel_status(dmac); /* Disables DMAC interrupt for the given channel */ dmac_disable_global_it(dmac, -1); dmac_enable(dmac); /* Disable the given dma channel */ dmac_disable_channel(dmac, channel->id); dmac_set_src_addr(dmac, channel->id, 0); dmac_set_dest_addr(dmac, channel->id, 0); dmac_set_channel_config(dmac, channel->id, 0); dmac_set_descriptor_addr(dmac, channel->id, 0, 0); return 0; } int dmacd_configure_transfer(struct _dma_channel* channel, struct _dmacd_cfg* cfg, struct _dmac_desc* desc) { Dmac *dmac = channel->hw; uint32_t ctrlb; if (channel->state == DMA_STATE_FREE) return -EPERM; else if (channel->state == DMA_STATE_STARTED) return -EBUSY; ctrlb = desc->ctrlb; cfg->cfg &= ~(DMAC_CFG_SRC_PER_Msk | DMAC_CFG_SRC_PER_MSB_Msk | DMAC_CFG_DST_PER_Msk | DMAC_CFG_DST_PER_MSB_Msk); if ((ctrlb & DMAC_CTRLB_FC_Msk) == DMAC_CTRLB_FC_PER2MEM_DMA_FC) { cfg->cfg |= DMAC_CFG_SRC_PER(channel->src_rxif); cfg->cfg |= DMAC_CFG_SRC_PER_MSB(channel->src_rxif >> 4); } if ((ctrlb & DMAC_CTRLB_FC_Msk) == DMAC_CTRLB_FC_MEM2PER_DMA_FC) { cfg->cfg |= DMAC_CFG_DST_PER(channel->dest_txif); cfg->cfg |= DMAC_CFG_DST_PER_MSB(channel->dest_txif >> 4); } dmac_get_global_isr(dmac); dmac_get_channel_status(dmac); /* if DMAC_CTRLBx.AUTO bit is enabled, and source or destination is not fetched from linker list, set the channel with AUTO mode, in this mode, the hardware sets the Buffer Transfer Completed Interrupt when the buffer transfer has completed, It then stalls until STALx bit of DMAC_CHSR is cleared by writing in the KEEPx bit of DMAC_CHER */ if (cfg->trans_auto) { if ((cfg->s_decr_fetch) && (cfg->d_decr_fetch)){ ctrlb |= DMAC_CTRLB_AUTO_ENABLE; channel->rep_count = cfg->blocks; } } dmac_set_descriptor_addr(dmac, channel->id, 0, 0); if (cfg->s_decr_fetch) /* *Buffer Descriptor fetch operation is disabled for the source */ dmac_set_src_addr(dmac, channel->id, desc->saddr); else /* Source address is updated when the descriptor is fetched from the memory */ dmac_set_descriptor_addr(dmac, channel->id, desc, 0); if (cfg->d_decr_fetch) /* *Buffer Descriptor fetch operation is disabled for the destination */ dmac_set_dest_addr(dmac, channel->id, desc->daddr); else /* destination address is updated when the descriptor is fetched from the memory */ dmac_set_descriptor_addr(dmac, channel->id, desc, 0); dmac_set_control_a(dmac, channel->id, desc->ctrla); dmac_set_control_b(dmac, channel->id, ctrlb); dmac_set_channel_config(dmac, channel->id, cfg->cfg); return 0; } void dma_irq_handler(uint32_t source, void* user_arg) { uint32_t chan, gis; struct _dma_controller* ctrl = (struct _dma_controller*)user_arg; Dmac* dmac = ctrl->hw; gis = dmac_get_global_isr(dmac); if ((gis & 0xFFFFFFFF) == 0) return; for (chan = 0; chan < DMA_CHANNELS; chan++) { struct _dma_channel* channel = &ctrl->channels[chan]; bool exec = false; if (!(gis & ((DMAC_EBCISR_BTC0 | DMAC_EBCISR_CBTC0 | DMAC_EBCISR_ERR0) << chan))) continue; if (channel->state == DMA_STATE_FREE) continue; if (gis & (DMAC_EBCISR_CBTC0 << chan)) { if (channel->rep_count) { if (channel->rep_count == 1) { dmac_auto_clear(dmac, chan); } dmac_resume_channel(dmac, chan); channel->rep_count--; } else { channel->state = DMA_STATE_DONE; exec = 1; } } /* Execute callback */ if (exec) callback_call(&channel->callback, NULL); } }

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/* Copyright 2016 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ /* UART module for ISH */ #include "common.h" #include "math_util.h" #include "console.h" #include "uart_defs.h" #include "atomic.h" #include "task.h" #include "registers.h" #include "uart.h" #include "uart_defs.h" #include "interrupts.h" #include "system.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) #define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) #define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) static const uint32_t baud_conf[][BAUD_TABLE_MAX] = { {B9600, 9600}, {B57600, 57600}, {B115200, 115200}, {B921600, 921600}, {B2000000, 2000000}, {B3000000, 3000000}, {B3250000, 3250000}, {B3500000, 3500000}, {B4000000, 4000000}, {B19200, 19200}, }; static struct uart_ctx uart_ctx[UART_DEVICES] = { { .id = 0, .base = UART0_BASE, .input_freq = UART_ISH_INPUT_FREQ, .addr_interval = UART_ISH_ADDR_INTERVAL, .uart_state = UART_STATE_CG, }, { .id = 1, .base = UART1_BASE, .input_freq = UART_ISH_INPUT_FREQ, .addr_interval = UART_ISH_ADDR_INTERVAL, .uart_state = UART_STATE_CG, }, { .id = 2, .base = UART2_BASE, .input_freq = UART_ISH_INPUT_FREQ, .addr_interval = UART_ISH_ADDR_INTERVAL, .uart_state = UART_STATE_CG, } }; static int init_done; int uart_init_done(void) { return init_done; } void uart_tx_start(void) { if (!IS_ENABLED(CONFIG_POLLING_UART)) { if (IER(ISH_DEBUG_UART) & IER_TDRQ) return; /* Do not allow deep sleep while transmit in progress */ disable_sleep(SLEEP_MASK_UART); IER(ISH_DEBUG_UART) |= IER_TDRQ; } } void uart_tx_stop(void) { if (!IS_ENABLED(CONFIG_POLLING_UART)) { /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); IER(ISH_DEBUG_UART) &= ~IER_TDRQ; } } void uart_tx_flush(void) { if (!IS_ENABLED(CONFIG_POLLING_UART)) { while (!(LSR(ISH_DEBUG_UART) & LSR_TEMT)) continue; } } int uart_tx_ready(void) { return LSR(ISH_DEBUG_UART) & LSR_TEMT; } int uart_rx_available(void) { if (IS_ENABLED(CONFIG_POLLING_UART)) return 0; return LSR(ISH_DEBUG_UART) & LSR_DR; } void uart_write_char(char c) { /* Wait till receiver is ready */ while (!uart_tx_ready()) continue; THR(ISH_DEBUG_UART) = c; } int uart_read_char(void) { return RBR(ISH_DEBUG_UART); } void uart_ec_interrupt(void) { /* Read input FIFO until empty, then fill output FIFO */ uart_process_input(); uart_process_output(); } #ifndef CONFIG_POLLING_UART DECLARE_IRQ(ISH_DEBUG_UART_IRQ, uart_ec_interrupt); #endif static int uart_return_baud_rate_by_id(int baud_rate_id) { int i; for (i = 0; i < ARRAY_SIZE(baud_conf); i++) { if (baud_conf[i][BAUD_IDX] == baud_rate_id) return baud_conf[i][BAUD_SPEED]; } return -1; } static void uart_hw_init(enum UART_PORT id) { uint32_t divisor; /* baud rate divisor */ uint8_t mcr = 0; uint8_t fcr = 0; struct uart_ctx *ctx = &uart_ctx[id]; uint8_t fraction; /* Calculate baud rate divisor */ divisor = (ctx->input_freq / ctx->baud_rate) >> 4; if (IS_ENABLED(CONFIG_ISH_DW_UART)) { /* calculate the fractional part */ fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4); } else { MUL(ctx->id) = (divisor * ctx->baud_rate); DIV(ctx->id) = (ctx->input_freq / 16); PS(ctx->id) = 16; } /* Set the DLAB to access the baud rate divisor registers */ LCR(ctx->id) = LCR_DLAB; DLL(ctx->id) = (divisor & 0xff); DLH(ctx->id) = ((divisor >> 8) & 0xff); if (IS_ENABLED(CONFIG_ISH_DW_UART)) DLF(ctx->id) = fraction; /* 8 data bits, 1 stop bit, no parity, clear DLAB */ LCR(ctx->id) = LCR_8BIT_CHR; if (ctx->client_flags & UART_CONFIG_HW_FLOW_CONTROL) mcr = MCR_AUTO_FLOW_EN; /* needs to be set regardless of flow control */ if (!IS_ENABLED(CONFIG_ISH_DW_UART)) mcr |= MCR_INTR_ENABLE; mcr |= (MCR_RTS | MCR_DTR); MCR(ctx->id) = mcr; if (IS_ENABLED(CONFIG_ISH_DW_UART)) fcr = FCR_TET_EMPTY | FCR_RT_1CHAR; else fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1; /* configure FIFOs */ FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE | FCR_RESET_RX | FCR_RESET_TX); if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* enable UART unit */ ABR(ctx->id) = ABR_UUE; /* clear the port */ RBR(ctx->id); if (IS_ENABLED(CONFIG_POLLING_UART)) IER(ctx->id) = 0x00; else IER(ctx->id) = IER_RECV; } void uart_port_restore(void) { uart_hw_init(ISH_DEBUG_UART); } void uart_to_idle(void) { int id; for (id = 0; id < UART_DEVICES; id++) { LCR(id) = 0x80; DLL(id) = 0x1; DLH(id) = 0x0; LCR(id) = 0x0; } } static void uart_stop_hw(enum UART_PORT id) { int i; uint32_t fifo_len; if (!IS_ENABLED(CONFIG_ISH_DW_UART)) { /* Manually clearing the fifo from possible noise. * Entering D0i3 when fifo is not cleared may result in a hang. */ fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS; for (i = 0; i < fifo_len; i++) (void)RBR(id); } /* No interrupts are enabled */ IER(id) = 0; MCR(id) = 0; /* Clear and disable FIFOs */ FCR(id) = (FCR_RESET_RX | FCR_RESET_TX); if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* Disable uart unit */ ABR(id) = 0; } static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags) { if ((uart_ctx[id].base == 0) || (id >= UART_DEVICES)) return UART_ERROR; if (!bool_compare_and_swap_u32(&uart_ctx[id].is_open, 0, 1)) return UART_BUSY; uart_ctx[id].baud_rate = uart_return_baud_rate_by_id(baud_rate_id); if ((uart_ctx[id].baud_rate == -1) || (uart_ctx[id].baud_rate == 0)) uart_ctx[id].baud_rate = UART_DEFAULT_BAUD_RATE; uart_ctx[id].client_flags = flags; deprecated_atomic_and(&uart_ctx[id].uart_state, ~UART_STATE_CG); uart_hw_init(id); return EC_SUCCESS; } static void uart_drv_init(void) { int i; /* Disable UART */ for (i = 0; i < UART_DEVICES; i++) uart_stop_hw(i); if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit * to allow PMU to clock gate ISH */ HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN | GIEN_UART1_EN | GIEN_PWR_MGMT); task_enable_irq(ISH_DEBUG_UART_IRQ); } void uart_init(void) { uart_drv_init(); uart_client_init(ISH_DEBUG_UART, B115200, 0); init_done = 1; }

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/*- * ==================================================== * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. * * Developed at SunSoft, a Sun Microsystems, Inc. business. * Permission to use, copy, modify, and distribute this * software is freely granted, provided that this notice * is preserved. * ==================================================== * * k_sin.c and k_cos.c merged by Steven G. Kargl. */ #include <sys/cdefs.h> #if 0 __FBSDID("$FreeBSD: head/lib/msun/src/k_sincos.h 319047 2017-05-28 06:13:38Z mmel $"); #endif #if defined(LIBM_SCCS) && !defined(lint) __RCSID("$NetBSD: k_sincos.h,v 1.2 2022/08/29 01:48:34 riastradh Exp $"); #endif static const double S1 = -1.66666666666666324348e-01, /* 0xBFC55555, 0x55555549 */ S2 = 8.33333333332248946124e-03, /* 0x3F811111, 0x1110F8A6 */ S3 = -1.98412698298579493134e-04, /* 0xBF2A01A0, 0x19C161D5 */ S4 = 2.75573137070700676789e-06, /* 0x3EC71DE3, 0x57B1FE7D */ S5 = -2.50507602534068634195e-08, /* 0xBE5AE5E6, 0x8A2B9CEB */ S6 = 1.58969099521155010221e-10; /* 0x3DE5D93A, 0x5ACFD57C */ static const double C1 = 4.16666666666666019037e-02, /* 0x3FA55555, 0x5555554C */ C2 = -1.38888888888741095749e-03, /* 0xBF56C16C, 0x16C15177 */ C3 = 2.48015872894767294178e-05, /* 0x3EFA01A0, 0x19CB1590 */ C4 = -2.75573143513906633035e-07, /* 0xBE927E4F, 0x809C52AD */ C5 = 2.08757232129817482790e-09, /* 0x3E21EE9E, 0xBDB4B1C4 */ C6 = -1.13596475577881948265e-11; /* 0xBDA8FAE9, 0xBE8838D4 */ static inline void __kernel_sincos(double x, double y, int iy, double *sn, double *cs) { double hz, r, v, w, z; z = x * x; w = z * z; r = S2 + z * (S3 + z * S4) + z * w * (S5 + z * S6); v = z * x; if (iy == 0) *sn = x + v * (S1 + z * r); else *sn = x - ((z * (y / 2 - v * r) - y) - v * S1); r = z * (C1 + z * (C2 + z * C3)) + w * w * (C4 + z * (C5 + z * C6)); hz = z / 2; w = 1 - hz; *cs = w + (((1 - w) - hz) + (z * r - x * y)); }

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// Copyright (c) Lawrence Livermore National Security, LLC and other VisIt // Project developers. See the top-level LICENSE file for dates and other // details. No copyright assignment is required to contribute to VisIt. // ************************************************************************* // // avtL2NormQuery.C // // ************************************************************************* // #include <avtL2NormQuery.h> #include <string> // **************************************************************************** // Method: avtL2NormQuery::avtL2NormQuery // // Programmer: Hank Childs // Creation: October 2, 2003 // // **************************************************************************** avtL2NormQuery::avtL2NormQuery() { } // **************************************************************************** // Method: avtL2NormQuery::~avtL2NormQuery // // Programmer: Hank Childs // Creation: October 2, 2003 // // **************************************************************************** avtL2NormQuery::~avtL2NormQuery() { } // **************************************************************************** // Method: avtL2NormQuery::CurveQuery // // Purpose: // Computes the L2Norm number of the input curve. // // Notes: // The L2Norm can be calculated as the sum of contributions from the // line segments that make up the curve. Over line segment i, the // function f(x) is a line. The line has the form f(x) = mx+b. // We can easily calculate m and b. // // Once we know m and b, we can calculate what f(x)^2 is. It is a // parabola. Finally, once we know f(x)^2, we can calculate the integral // from x1 to x2. // It is: // m*m*x1*x1*x1/3 + mb*x1*x1 + b*b*x1 - m*m*x2*x2*x2/3 + mb*x2*x2 + b*b*x2 // // Programmer: Hank Childs // Creation: October 3, 2003 // // Modifications: // // Hank Childs, Tue Mar 15 15:43:31 PST 2005 // The assumption that x-coords won't be duplicated came from the original // implementation of this query -- the L2-norm between curves query. That // assumption is not true for this query, so add explicit checking. // // **************************************************************************** double avtL2NormQuery::CurveQuery(int n1, const float *x1, const float *y1) { double integral = 0; for (int i = 0 ; i < n1-1 ; i++) { // pt1 and pt2 will determine f(x) for the range usedX[i]-[i+1] float pt1[2], pt2[2]; pt1[0] = x1[i]; pt1[1] = y1[i]; pt2[0] = x1[i+1]; pt2[1] = y1[i+1]; // Degeneracies like this can occur from lineouts due to numerical // sensititives. They also can be in a file from a database (like // a pre-existing degeneracy in an Ultra file). if (pt1[0] == pt2[0]) continue; // Calculate the line in f(x) = mx+b notation. double rise = pt2[1] - pt1[1]; double run = pt2[0] - pt1[0]; double m = rise / run; double b = pt1[1] - m*pt1[0]; integral += m*m*pt2[0]*pt2[0]*pt2[0]/3. + m*b*pt2[0]*pt2[0] + b*b*pt2[0] - m*m*pt1[0]*pt1[0]*pt1[0]/3. - m*b*pt1[0]*pt1[0] - b*b*pt1[0]; } return sqrt(integral); } // **************************************************************************** // Method: avtL2NormQuery::CreateMessage // // Purpose: // Creates a message for the L2Norm query. // // Programmer: Hank Childs // Creation: October 3, 2003 // // Modifications: // // Cyrus Harrison, Tue Sep 18 13:45:35 PDT 2007 // Added support for user settable floating point format string // // Kathleen Biagas, Mon Feb 24 16:13:22 PST 2014 // Add Xml results. // // **************************************************************************** std::string avtL2NormQuery::CreateMessage(double l2norm) { MapNode result_node; result_node["L2Norm"] = l2norm; SetXmlResult(result_node.ToXML()); char msg[1024]; std::string format = "The L2Norm is " + queryAtts.GetFloatFormat() + "."; snprintf(msg,1024,format.c_str(), l2norm); std::string m = msg; return m; }

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Apache-2.0

2023-09-14T19:14:28

2013-06-26T14:09:07

C++

UTF-8

C

false

28,338

c

GetRatesOldVars.C

#include "TChain.h" #include "iostream" #include "fstream" #include "iomanip" #include "vector" #include "map" struct sample { TString name; TChain *chain; Double_t nEvents; Double_t xSection; }; void GetRates() { Double_t luminosity = 1.0E32; // in cm^-2 s^-1 Double_t conversion = 1.0E-27; // mb -> cm^2 /* Set the cuts for which we calculate the rates */ Double_t cutEt = 15.; // 19. Double_t cutIHcal = 3.; // 0.06 Double_t cutEoverpBarrel = 1.5; // 0.45 Double_t cutEoverpEndcap = 2.45; // 9.5 Double_t cutItrack = 0.06; // 0.45 /* ********************************************* */ TString pathName = "SingleElecs"; // Egamma path to analyze: SingleElecs, RelaxedSingleElecs, DoubleElecs, RelaxedDoubleElecs, SinglePhots, etc. // Note: High and Very High EM start with the same L1 as RelaxedSingleElecs ofstream myfile; myfile.open("RatesTableOldVars.txt"); // Output file name std::vector<sample> samples; sample thisSample; TString thisName; TChain *thisChain; Int_t sampleNum = 0; /* Set properties of input files */ /* Sample input: thisChain = new TChain("Events"); thisChain->Add("<path-to-root-file-1>"); ... thisChain->Add("<path-to-root-file-N>"); thisSample.name = "Name to be displayed in table"; thisSample.chain= thisChain; thisSample.nEvents = number of events in all files in chain combined; thisSample.xSection = cross section for process contributing to this chain; samples.push_back(thisSample); */ thisChain = new TChain("Events"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_1.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_2.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_3.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_4.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_5.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_6.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_7.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_8.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_9.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_10.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_11.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_12.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_13.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_14.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_15.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_16.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_17.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_18.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_19.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_20.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_21.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_22.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_23.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_24.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_25.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_26.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_27.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_28.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_29.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_30.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_31.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_32.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_33.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_34.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_35.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_36.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_37.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_38.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_39.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_40.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_41.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_42.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_43.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_44.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_45.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_46.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_47.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_48.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_49.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_50.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_51.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_52.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_53.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_54.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_55.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_56.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_57.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_58.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_59.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_60.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_61.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_62.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_63.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_64.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_65.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_66.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_67.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_68.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_69.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_70.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_71.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_72.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_73.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_74.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_75.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_76.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_77.root"); // thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_78.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_79.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_80.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_81.root"); thisChain->Add("../test/HLTStudyData/crab_0_071206_144326/res/QCD-0-15-HLTVars_82.root"); thisSample.name = "QCD 0-15"; thisSample.chain = thisChain; thisSample.nEvents = 810000; thisSample.xSection = 52.0; samples.push_back(thisSample); thisChain = new TChain("Events"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-0.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-1.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-2.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-3.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-4.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-5.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-6.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-7.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-8.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-9.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-10.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-11.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-12.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-13.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-14.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-15.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-16.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-17.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-18.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-19.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-20.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-21.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-22.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-23.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-24.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-25.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-26.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-27.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-28.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-29.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-30.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-31.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-32.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-33.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-34.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-35.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-36.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-37.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-38.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-39.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-40.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-41.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-42.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-43.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-44.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-45.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-46.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-47.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-48.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-49.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-50.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-51.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-52.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-53.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-54.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-55.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-56.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-57.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-58.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-59.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-60.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-61.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-62.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-63.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-64.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-65.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-66.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-67.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-68.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-69.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-70.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-71.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-72.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-73.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-74.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-75.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-76.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-77.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-78.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-79.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-80.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-81.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-82.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-83.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-84.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-85.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-86.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-87.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-88.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-89.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-90.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-91.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-92.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-93.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-94.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-95.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-96.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-97.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-98.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-99.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-100.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-101.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-102.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-103.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-104.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-105.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-106.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-107.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-108.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-109.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-110.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-111.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-112.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-113.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-114.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-115.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-116.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-117.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-118.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-119.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-120.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-121.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-122.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-123.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-124.root"); thisChain->Add("../test/HLTStudyData/QCD-15-20/QCD-15-20-HLTVars-125.root"); thisSample.name = "QCD 15-20"; thisSample.chain = thisChain; thisSample.nEvents = 1260000; thisSample.xSection = 1.46; samples.push_back(thisSample); thisChain = new TChain("Events"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-20-30-HLTVars.root"); thisSample.name = "QCD 20-30"; thisSample.chain = thisChain; thisSample.nEvents = 100000; thisSample.xSection = 6.32E-1; samples.push_back(thisSample); thisChain = new TChain("Events"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-30-50-HLTVars.root"); thisSample.name = "QCD 30-50"; thisSample.chain = thisChain; thisSample.nEvents = 100000; thisSample.xSection = 1.63E-1; samples.push_back(thisSample); thisChain = new TChain("Events"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-1.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-2.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-3.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-4.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-5.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-6.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-7.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-8.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-9.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-HLTVars-10.root"); thisSample.name = "QCD 50-80"; thisSample.chain = thisChain; thisSample.nEvents = 100000; thisSample.xSection = 2.16E-2; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-0.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-1.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-2.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-3.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-4.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-5.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-6.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-7.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-8.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/QCD-cfgs/QCD-HLTVars80120-9.root"); thisSample.name = "QCD 80-120"; thisSample.chain = thisChain; thisSample.nEvents = 239993; thisSample.xSection = 3.08E-3; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-120-170-HLTVars-2.root"); thisSample.name = "QCD 120-170"; thisSample.chain = thisChain; thisSample.nEvents = 11092; thisSample.xSection = 4.94E-4; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-170-230-HLTVars-0.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-170-230-HLTVars-1.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-170-230-HLTVars-2.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-170-230-HLTVars-3.root"); thisSample.name = "QCD 170-230"; thisSample.chain = thisChain; thisSample.nEvents = 400000; thisSample.xSection = 1.01E-4; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-230-300-HLTVars-0.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-230-300-HLTVars-1.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-230-300-HLTVars-2.root"); thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/QCD-230-300-HLTVars-3.root"); thisSample.name = "QCD 230-300"; thisSample.chain = thisChain; thisSample.nEvents = 400000; thisSample.xSection = 2.45E-5; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/ZEE-HLTVars.root"); thisSample.name = "Z->ee"; thisSample.chain = thisChain; thisSample.nEvents = 3800; thisSample.xSection = 1.62E-6; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/WENU-HLTVars.root"); thisSample.name = "W->ev"; thisSample.chain = thisChain; thisSample.nEvents = 2000; thisSample.xSection = 1.72E-5; samples.push_back(thisSample); thisChain = new TChain("Events");; thisChain->Add("../../../../../CMSSW_1_6_0/src/HLTriggerOffline/Egamma/test/HLTStudyData/TTbar-HLTVars-1e.root"); thisSample.name = "t-tbar"; thisSample.chain = thisChain; thisSample.nEvents = 100000; thisSample.xSection = 8.33E-7; samples.push_back(thisSample); /* ****************************** */ TString cutText = "", l1CutText = ""; Double_t thisPass = 0., thisPassL1 = 0.; Double_t thisEff = 0., thisEffL1 = 0.; Double_t thisRate = 0., thisRateL1 = 0., rate = 0., rateL1 = 0.; Double_t thisEffErr = 0.; Double_t thisRateErr = 0., thisRateErrL1 = 0., rateErr = 0., rateErrL1 = 0.; /* Set the formula to apply cuts */ cutText = "Sum$("; cutText += pathName; cutText += ".l1Match && "; cutText += pathName; cutText += ".Et > "; cutText += cutEt; cutText += " && "; cutText += pathName; cutText += ".IHcal < "; cutText += cutIHcal; cutText += " && "; cutText += pathName; cutText += ".pixMatch > 0 && (("; cutText += pathName; cutText += ".Eoverp < "; cutText += cutEoverpBarrel; cutText += " && fabs("; cutText += pathName; cutText += ".eta) < 1.5) || ("; cutText += pathName; cutText += ".Eoverp < "; cutText += cutEoverpEndcap; cutText += " && fabs("; cutText += pathName; cutText += ".eta) > 1.5 && fabs("; cutText += pathName; cutText += ".eta) < 2.5)) && "; cutText += pathName; cutText += ".Itrack < "; cutText += cutItrack; // cutText += " && SingleElecs.mcEt > 0.) >= 1"; Uncomment to require MC electron cutText += ") >= 1"; // Change to >= 2 for double cuts l1CutText = "Sum$(SingleElecsPT.Et > -999.)"; /* Calculate raes and fill table */ myfile<<"Rates and Efficiencies for Input Samples"<<endl; myfile<<"Name X-Section (mb) Efficiency Uncert. L1 Rate (Hz) Uncert. (Hz) Rate (Hz) Uncert. (Hz)"<<endl; myfile<<"--"<<endl; myfile.setf(ios::left); for (sampleNum = 0; sampleNum < (Int_t)samples.size(); sampleNum++) { thisPass = (Double_t)samples[sampleNum].chain->Draw("", cutText); thisPassL1 = (Double_t)samples[sampleNum].chain->Draw("", l1CutText); thisEff = thisPass / samples[sampleNum].nEvents; thisEffL1 = thisPassL1 / samples[sampleNum].nEvents; thisEffErr = sqrt(thisEff * (1. - thisEff) / samples[sampleNum].nEvents); // Simple binomial distribution uncertainty thisRate = thisEff * samples[sampleNum].xSection * luminosity * conversion; thisRateL1 = thisEffL1 * samples[sampleNum].xSection * luminosity * conversion; thisRateErr = thisEffErr * samples[sampleNum].xSection * luminosity * conversion; thisRateErrL1 = sqrt(thisEffL1 * (1. - thisEffL1) / samples[sampleNum].nEvents) * samples[sampleNum].xSection * luminosity * conversion; rate += thisRate; rateL1 += thisRateL1; rateErr = sqrt(rateErr*rateErr + thisRateErr*thisRateErr); rateErrL1 = sqrt(rateErrL1*rateErrL1 + thisRateErrL1*thisRateErrL1); thisName = samples[sampleNum].name; myfile<<setw(15)<<thisName<<setw(15)<<samples[sampleNum].xSection<<setw(15)<<setprecision(3)<<thisEff<<setw(15)<<setprecision(3)<<thisEffErr<<setw(15)<<setprecision(3)<<thisRateL1<<setw(15)<<setprecision(3)<<thisRateErrL1<<setw(15)<<setprecision(3)<<thisRate<<setw(15)<<setprecision(3)<<thisRateErr<<endl; } myfile<<"--"<<endl; myfile<<"Total "<<setw(15)<<setprecision(3)<<rate<<setw(15)<<setprecision(3)<<rateErr<<endl; myfile.close(); }

97b3c847568bfa1e0aa6c71243cea924622dc080

83e7dc1281874779c46dfadcc15b2bb66d8e599c

/demos/multilang/assets/avatars/img_multilang_avatar_4.c

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[ "MIT" ]

permissive

lvgl/lvgl

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refs/heads/master

2023-08-30T22:39:20.283922

2023-08-30T19:55:29

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MIT

2023-09-14T17:59:34

2016-06-08T04:14:34

C

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C

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394,561

c

img_multilang_avatar_4.c

#ifdef __has_include #if __has_include("lvgl.h") #ifndef LV_LVGL_H_INCLUDE_SIMPLE #define LV_LVGL_H_INCLUDE_SIMPLE #endif #endif #endif #if defined(LV_LVGL_H_INCLUDE_SIMPLE) #include "lvgl.h" #else #include "lvgl/lvgl.h" #endif #if LV_USE_DEMO_MULTILANG #ifndef LV_ATTRIBUTE_MEM_ALIGN #define LV_ATTRIBUTE_MEM_ALIGN #endif #ifndef LV_ATTRIBUTE_IMG_IMG_MULTILANG_AVATAR_4 #define LV_ATTRIBUTE_IMG_IMG_MULTILANG_AVATAR_4 #endif const LV_ATTRIBUTE_MEM_ALIGN LV_ATTRIBUTE_LARGE_CONST LV_ATTRIBUTE_IMG_IMG_MULTILANG_AVATAR_4 uint8_t img_multilang_avatar_4_map[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; const lv_img_dsc_t img_multilang_avatar_4 = { .header.cf = LV_COLOR_FORMAT_ARGB8888, .header.always_zero = 0, .header.w = 128, .header.h = 128, .data = img_multilang_avatar_4_map, }; #endif

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/utils/gapy/gen-debug-info-src/ext/bfd/bfdver.h

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GreenWaves-Technologies/gap_sdk

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bfdver.h

#define BFD_VERSION_DATE 20170505 #define BFD_VERSION 228000000 #define BFD_VERSION_STRING "(GNU Binutils) " "2.28.0.20170505" #define REPORT_BUGS_TO "<http://www.sourceware.org/bugzilla/>"

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/components/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h

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bouffalolab/bl_iot_sdk

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dtsrc_reg.h

/* * Copyright (c) 2016-2023 Bouffalolab. * * This file is part of * *** Bouffalolab Software Dev Kit *** * (see www.bouffalolab.com). * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of Bouffalo Lab nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DTSRC_REG_H__ #define __DTSRC_REG_H__ #include "bl808.h" /* 0x0 : config */ #define DTSRC_CONFIG_OFFSET (0x0) #define DTSRC_CR_ENABLE DTSRC_CR_ENABLE #define DTSRC_CR_ENABLE_POS (0U) #define DTSRC_CR_ENABLE_LEN (1U) #define DTSRC_CR_ENABLE_MSK (((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS) #define DTSRC_CR_ENABLE_UMSK (~(((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS)) #define DTSRC_CR_AXI_EN DTSRC_CR_AXI_EN #define DTSRC_CR_AXI_EN_POS (1U) #define DTSRC_CR_AXI_EN_LEN (1U) #define DTSRC_CR_AXI_EN_MSK (((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS) #define DTSRC_CR_AXI_EN_UMSK (~(((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS)) #define DTSRC_CR_MODE_CEA_861 DTSRC_CR_MODE_CEA_861 #define DTSRC_CR_MODE_CEA_861_POS (2U) #define DTSRC_CR_MODE_CEA_861_LEN (1U) #define DTSRC_CR_MODE_CEA_861_MSK (((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS) #define DTSRC_CR_MODE_CEA_861_UMSK (~(((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS)) #define DTSRC_CR_SNSR_EN DTSRC_CR_SNSR_EN #define DTSRC_CR_SNSR_EN_POS (3U) #define DTSRC_CR_SNSR_EN_LEN (1U) #define DTSRC_CR_SNSR_EN_MSK (((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS) #define DTSRC_CR_SNSR_EN_UMSK (~(((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS)) #define DTSRC_CR_SNSR_HSYNC_INV DTSRC_CR_SNSR_HSYNC_INV #define DTSRC_CR_SNSR_HSYNC_INV_POS (4U) #define DTSRC_CR_SNSR_HSYNC_INV_LEN (1U) #define DTSRC_CR_SNSR_HSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS) #define DTSRC_CR_SNSR_HSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS)) #define DTSRC_CR_SNSR_VSYNC_INV DTSRC_CR_SNSR_VSYNC_INV #define DTSRC_CR_SNSR_VSYNC_INV_POS (5U) #define DTSRC_CR_SNSR_VSYNC_INV_LEN (1U) #define DTSRC_CR_SNSR_VSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS) #define DTSRC_CR_SNSR_VSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS)) #define DTSRC_CR_AXI_SWAP_MODE DTSRC_CR_AXI_SWAP_MODE #define DTSRC_CR_AXI_SWAP_MODE_POS (7U) #define DTSRC_CR_AXI_SWAP_MODE_LEN (1U) #define DTSRC_CR_AXI_SWAP_MODE_MSK (((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS) #define DTSRC_CR_AXI_SWAP_MODE_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS)) #define DTSRC_CR_AXI_SWAP_IDX_SEL DTSRC_CR_AXI_SWAP_IDX_SEL #define DTSRC_CR_AXI_SWAP_IDX_SEL_POS (8U) #define DTSRC_CR_AXI_SWAP_IDX_SEL_LEN (4U) #define DTSRC_CR_AXI_SWAP_IDX_SEL_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS) #define DTSRC_CR_AXI_SWAP_IDX_SEL_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS)) #define DTSRC_CR_AXI_SWAP_IDX_SWM DTSRC_CR_AXI_SWAP_IDX_SWM #define DTSRC_CR_AXI_SWAP_IDX_SWM_POS (12U) #define DTSRC_CR_AXI_SWAP_IDX_SWM_LEN (1U) #define DTSRC_CR_AXI_SWAP_IDX_SWM_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS) #define DTSRC_CR_AXI_SWAP_IDX_SWM_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS)) #define DTSRC_CR_AXI_SWAP_IDX_SWV DTSRC_CR_AXI_SWAP_IDX_SWV #define DTSRC_CR_AXI_SWAP_IDX_SWV_POS (13U) #define DTSRC_CR_AXI_SWAP_IDX_SWV_LEN (1U) #define DTSRC_CR_AXI_SWAP_IDX_SWV_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS) #define DTSRC_CR_AXI_SWAP_IDX_SWV_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS)) #define DTSRC_CR_AXI_DVP_DATA_MODE DTSRC_CR_AXI_DVP_DATA_MODE #define DTSRC_CR_AXI_DVP_DATA_MODE_POS (16U) #define DTSRC_CR_AXI_DVP_DATA_MODE_LEN (3U) #define DTSRC_CR_AXI_DVP_DATA_MODE_MSK (((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS) #define DTSRC_CR_AXI_DVP_DATA_MODE_UMSK (~(((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS)) #define DTSRC_CR_AXI_B0_SEL DTSRC_CR_AXI_B0_SEL #define DTSRC_CR_AXI_B0_SEL_POS (20U) #define DTSRC_CR_AXI_B0_SEL_LEN (2U) #define DTSRC_CR_AXI_B0_SEL_MSK (((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS) #define DTSRC_CR_AXI_B0_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS)) #define DTSRC_CR_AXI_B1_SEL DTSRC_CR_AXI_B1_SEL #define DTSRC_CR_AXI_B1_SEL_POS (22U) #define DTSRC_CR_AXI_B1_SEL_LEN (2U) #define DTSRC_CR_AXI_B1_SEL_MSK (((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS) #define DTSRC_CR_AXI_B1_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS)) #define DTSRC_CR_AXI_B2_SEL DTSRC_CR_AXI_B2_SEL #define DTSRC_CR_AXI_B2_SEL_POS (24U) #define DTSRC_CR_AXI_B2_SEL_LEN (2U) #define DTSRC_CR_AXI_B2_SEL_MSK (((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS) #define DTSRC_CR_AXI_B2_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS)) /* 0x4 : frame_size_h */ #define DTSRC_FRAME_SIZE_H_OFFSET (0x4) #define DTSRC_CR_TOTAL_H DTSRC_CR_TOTAL_H #define DTSRC_CR_TOTAL_H_POS (0U) #define DTSRC_CR_TOTAL_H_LEN (12U) #define DTSRC_CR_TOTAL_H_MSK (((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS) #define DTSRC_CR_TOTAL_H_UMSK (~(((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS)) #define DTSRC_CR_BLANK_H DTSRC_CR_BLANK_H #define DTSRC_CR_BLANK_H_POS (16U) #define DTSRC_CR_BLANK_H_LEN (12U) #define DTSRC_CR_BLANK_H_MSK (((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS) #define DTSRC_CR_BLANK_H_UMSK (~(((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS)) /* 0x8 : frame_size_v */ #define DTSRC_FRAME_SIZE_V_OFFSET (0x8) #define DTSRC_CR_TOTAL_V DTSRC_CR_TOTAL_V #define DTSRC_CR_TOTAL_V_POS (0U) #define DTSRC_CR_TOTAL_V_LEN (12U) #define DTSRC_CR_TOTAL_V_MSK (((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS) #define DTSRC_CR_TOTAL_V_UMSK (~(((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS)) #define DTSRC_CR_BLANK_V DTSRC_CR_BLANK_V #define DTSRC_CR_BLANK_V_POS (16U) #define DTSRC_CR_BLANK_V_LEN (12U) #define DTSRC_CR_BLANK_V_MSK (((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS) #define DTSRC_CR_BLANK_V_UMSK (~(((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS)) /* 0xC : frame_size_cea_861 */ #define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC) #define DTSRC_CR_H_DURATION DTSRC_CR_H_DURATION #define DTSRC_CR_H_DURATION_POS (0U) #define DTSRC_CR_H_DURATION_LEN (8U) #define DTSRC_CR_H_DURATION_MSK (((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS) #define DTSRC_CR_H_DURATION_UMSK (~(((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS)) #define DTSRC_CR_H_PLACEMENT DTSRC_CR_H_PLACEMENT #define DTSRC_CR_H_PLACEMENT_POS (8U) #define DTSRC_CR_H_PLACEMENT_LEN (8U) #define DTSRC_CR_H_PLACEMENT_MSK (((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS) #define DTSRC_CR_H_PLACEMENT_UMSK (~(((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS)) #define DTSRC_CR_V_DURATION DTSRC_CR_V_DURATION #define DTSRC_CR_V_DURATION_POS (16U) #define DTSRC_CR_V_DURATION_LEN (8U) #define DTSRC_CR_V_DURATION_MSK (((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS) #define DTSRC_CR_V_DURATION_UMSK (~(((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS)) #define DTSRC_CR_V_PLACEMENT DTSRC_CR_V_PLACEMENT #define DTSRC_CR_V_PLACEMENT_POS (24U) #define DTSRC_CR_V_PLACEMENT_LEN (8U) #define DTSRC_CR_V_PLACEMENT_MSK (((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS) #define DTSRC_CR_V_PLACEMENT_UMSK (~(((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS)) /* 0x10 : pix_data_range */ #define DTSRC_PIX_DATA_RANGE_OFFSET (0x10) #define DTSRC_CR_DATA_MIN DTSRC_CR_DATA_MIN #define DTSRC_CR_DATA_MIN_POS (0U) #define DTSRC_CR_DATA_MIN_LEN (16U) #define DTSRC_CR_DATA_MIN_MSK (((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS) #define DTSRC_CR_DATA_MIN_UMSK (~(((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS)) #define DTSRC_CR_DATA_MAX DTSRC_CR_DATA_MAX #define DTSRC_CR_DATA_MAX_POS (16U) #define DTSRC_CR_DATA_MAX_LEN (16U) #define DTSRC_CR_DATA_MAX_MSK (((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS) #define DTSRC_CR_DATA_MAX_UMSK (~(((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS)) /* 0x14 : pix_data_step */ #define DTSRC_PIX_DATA_STEP_OFFSET (0x14) #define DTSRC_CR_DATA_STEP DTSRC_CR_DATA_STEP #define DTSRC_CR_DATA_STEP_POS (0U) #define DTSRC_CR_DATA_STEP_LEN (8U) #define DTSRC_CR_DATA_STEP_MSK (((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS) #define DTSRC_CR_DATA_STEP_UMSK (~(((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS)) /* 0x20 : axi2dvp_setting */ #define DTSRC_AXI2DVP_SETTING_OFFSET (0x20) #define DTSRC_CR_AXI_XLEN DTSRC_CR_AXI_XLEN #define DTSRC_CR_AXI_XLEN_POS (0U) #define DTSRC_CR_AXI_XLEN_LEN (3U) #define DTSRC_CR_AXI_XLEN_MSK (((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS) #define DTSRC_CR_AXI_XLEN_UMSK (~(((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS)) #define DTSRC_CR_AXI_DRAIN_ERR_CLR DTSRC_CR_AXI_DRAIN_ERR_CLR #define DTSRC_CR_AXI_DRAIN_ERR_CLR_POS (4U) #define DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN (1U) #define DTSRC_CR_AXI_DRAIN_ERR_CLR_MSK (((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS) #define DTSRC_CR_AXI_DRAIN_ERR_CLR_UMSK (~(((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS)) #define DTSRC_CR_AXI_420_MODE DTSRC_CR_AXI_420_MODE #define DTSRC_CR_AXI_420_MODE_POS (8U) #define DTSRC_CR_AXI_420_MODE_LEN (1U) #define DTSRC_CR_AXI_420_MODE_MSK (((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS) #define DTSRC_CR_AXI_420_MODE_UMSK (~(((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS)) #define DTSRC_CR_AXI_420_UD_SEL DTSRC_CR_AXI_420_UD_SEL #define DTSRC_CR_AXI_420_UD_SEL_POS (9U) #define DTSRC_CR_AXI_420_UD_SEL_LEN (1U) #define DTSRC_CR_AXI_420_UD_SEL_MSK (((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS) #define DTSRC_CR_AXI_420_UD_SEL_UMSK (~(((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS)) #define DTSRC_CR_QOS_SW_MODE DTSRC_CR_QOS_SW_MODE #define DTSRC_CR_QOS_SW_MODE_POS (10U) #define DTSRC_CR_QOS_SW_MODE_LEN (1U) #define DTSRC_CR_QOS_SW_MODE_MSK (((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS) #define DTSRC_CR_QOS_SW_MODE_UMSK (~(((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS)) #define DTSRC_CR_QOS_SW DTSRC_CR_QOS_SW #define DTSRC_CR_QOS_SW_POS (11U) #define DTSRC_CR_QOS_SW_LEN (1U) #define DTSRC_CR_QOS_SW_MSK (((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS) #define DTSRC_CR_QOS_SW_UMSK (~(((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS)) /* 0x24 : axi2dvp_start_addr_by */ #define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24) #define DTSRC_CR_AXI_ADDR_START_BY DTSRC_CR_AXI_ADDR_START_BY #define DTSRC_CR_AXI_ADDR_START_BY_POS (0U) #define DTSRC_CR_AXI_ADDR_START_BY_LEN (32U) #define DTSRC_CR_AXI_ADDR_START_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS) #define DTSRC_CR_AXI_ADDR_START_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS)) /* 0x28 : axi2dvp_burst_cnt */ #define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28) #define DTSRC_CR_AXI_FRAME_BC DTSRC_CR_AXI_FRAME_BC #define DTSRC_CR_AXI_FRAME_BC_POS (0U) #define DTSRC_CR_AXI_FRAME_BC_LEN (32U) #define DTSRC_CR_AXI_FRAME_BC_MSK (((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS) #define DTSRC_CR_AXI_FRAME_BC_UMSK (~(((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS)) /* 0x2C : axi2dvp_status */ #define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C) #define DTSRC_ST_AXI_FIFO_CNT_BY DTSRC_ST_AXI_FIFO_CNT_BY #define DTSRC_ST_AXI_FIFO_CNT_BY_POS (0U) #define DTSRC_ST_AXI_FIFO_CNT_BY_LEN (7U) #define DTSRC_ST_AXI_FIFO_CNT_BY_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS) #define DTSRC_ST_AXI_FIFO_CNT_BY_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS)) #define DTSRC_ST_AXI_DRAIN_ERROR_BY DTSRC_ST_AXI_DRAIN_ERROR_BY #define DTSRC_ST_AXI_DRAIN_ERROR_BY_POS (7U) #define DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN (1U) #define DTSRC_ST_AXI_DRAIN_ERROR_BY_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS) #define DTSRC_ST_AXI_DRAIN_ERROR_BY_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS)) #define DTSRC_ST_AXI_STATE_IDLE_BY DTSRC_ST_AXI_STATE_IDLE_BY #define DTSRC_ST_AXI_STATE_IDLE_BY_POS (8U) #define DTSRC_ST_AXI_STATE_IDLE_BY_LEN (1U) #define DTSRC_ST_AXI_STATE_IDLE_BY_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS) #define DTSRC_ST_AXI_STATE_IDLE_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS)) #define DTSRC_ST_AXI_STATE_FUNC_BY DTSRC_ST_AXI_STATE_FUNC_BY #define DTSRC_ST_AXI_STATE_FUNC_BY_POS (9U) #define DTSRC_ST_AXI_STATE_FUNC_BY_LEN (1U) #define DTSRC_ST_AXI_STATE_FUNC_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS) #define DTSRC_ST_AXI_STATE_FUNC_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS)) #define DTSRC_ST_AXI_STATE_FLSH_BY DTSRC_ST_AXI_STATE_FLSH_BY #define DTSRC_ST_AXI_STATE_FLSH_BY_POS (10U) #define DTSRC_ST_AXI_STATE_FLSH_BY_LEN (1U) #define DTSRC_ST_AXI_STATE_FLSH_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS) #define DTSRC_ST_AXI_STATE_FLSH_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS)) #define DTSRC_ST_AXI_FIFO_CNT_UV DTSRC_ST_AXI_FIFO_CNT_UV #define DTSRC_ST_AXI_FIFO_CNT_UV_POS (16U) #define DTSRC_ST_AXI_FIFO_CNT_UV_LEN (7U) #define DTSRC_ST_AXI_FIFO_CNT_UV_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS) #define DTSRC_ST_AXI_FIFO_CNT_UV_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS)) #define DTSRC_ST_AXI_DRAIN_ERROR_UV DTSRC_ST_AXI_DRAIN_ERROR_UV #define DTSRC_ST_AXI_DRAIN_ERROR_UV_POS (23U) #define DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN (1U) #define DTSRC_ST_AXI_DRAIN_ERROR_UV_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS) #define DTSRC_ST_AXI_DRAIN_ERROR_UV_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS)) #define DTSRC_ST_AXI_STATE_IDLE_UV DTSRC_ST_AXI_STATE_IDLE_UV #define DTSRC_ST_AXI_STATE_IDLE_UV_POS (24U) #define DTSRC_ST_AXI_STATE_IDLE_UV_LEN (1U) #define DTSRC_ST_AXI_STATE_IDLE_UV_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS) #define DTSRC_ST_AXI_STATE_IDLE_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS)) #define DTSRC_ST_AXI_STATE_FUNC_UV DTSRC_ST_AXI_STATE_FUNC_UV #define DTSRC_ST_AXI_STATE_FUNC_UV_POS (25U) #define DTSRC_ST_AXI_STATE_FUNC_UV_LEN (1U) #define DTSRC_ST_AXI_STATE_FUNC_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS) #define DTSRC_ST_AXI_STATE_FUNC_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS)) #define DTSRC_ST_AXI_STATE_FLSH_UV DTSRC_ST_AXI_STATE_FLSH_UV #define DTSRC_ST_AXI_STATE_FLSH_UV_POS (26U) #define DTSRC_ST_AXI_STATE_FLSH_UV_LEN (1U) #define DTSRC_ST_AXI_STATE_FLSH_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS) #define DTSRC_ST_AXI_STATE_FLSH_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS)) /* 0x30 : axi2dvp_swap_addr_by */ #define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30) #define DTSRC_CR_AXI_ADDR_SWAP_BY DTSRC_CR_AXI_ADDR_SWAP_BY #define DTSRC_CR_AXI_ADDR_SWAP_BY_POS (0U) #define DTSRC_CR_AXI_ADDR_SWAP_BY_LEN (32U) #define DTSRC_CR_AXI_ADDR_SWAP_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS) #define DTSRC_CR_AXI_ADDR_SWAP_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS)) /* 0x34 : axi2dvp_prefetch */ #define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34) #define DTSRC_CR_PREFETCH_V DTSRC_CR_PREFETCH_V #define DTSRC_CR_PREFETCH_V_POS (0U) #define DTSRC_CR_PREFETCH_V_LEN (12U) #define DTSRC_CR_PREFETCH_V_MSK (((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS) #define DTSRC_CR_PREFETCH_V_UMSK (~(((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS)) /* 0x38 : snsr2dvp_wait_pos */ #define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38) #define DTSRC_CR_SNSR_FIFO_TH DTSRC_CR_SNSR_FIFO_TH #define DTSRC_CR_SNSR_FIFO_TH_POS (0U) #define DTSRC_CR_SNSR_FIFO_TH_LEN (11U) #define DTSRC_CR_SNSR_FIFO_TH_MSK (((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS) #define DTSRC_CR_SNSR_FIFO_TH_UMSK (~(((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS)) /* 0x40 : axi2dvp_start_addr_uv */ #define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40) #define DTSRC_CR_AXI_ADDR_START_UV DTSRC_CR_AXI_ADDR_START_UV #define DTSRC_CR_AXI_ADDR_START_UV_POS (0U) #define DTSRC_CR_AXI_ADDR_START_UV_LEN (32U) #define DTSRC_CR_AXI_ADDR_START_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS) #define DTSRC_CR_AXI_ADDR_START_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS)) /* 0x44 : axi2dvp_swap_addr_uv */ #define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44) #define DTSRC_CR_AXI_ADDR_SWAP_UV DTSRC_CR_AXI_ADDR_SWAP_UV #define DTSRC_CR_AXI_ADDR_SWAP_UV_POS (0U) #define DTSRC_CR_AXI_ADDR_SWAP_UV_LEN (32U) #define DTSRC_CR_AXI_ADDR_SWAP_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS) #define DTSRC_CR_AXI_ADDR_SWAP_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS)) struct dtsrc_reg { /* 0x0 : config */ union { struct { uint32_t cr_enable : 1; /* [ 0], r/w, 0x0 */ uint32_t cr_axi_en : 1; /* [ 1], r/w, 0x0 */ uint32_t cr_mode_cea_861 : 1; /* [ 2], r/w, 0x0 */ uint32_t cr_snsr_en : 1; /* [ 3], r/w, 0x0 */ uint32_t cr_snsr_hsync_inv : 1; /* [ 4], r/w, 0x0 */ uint32_t cr_snsr_vsync_inv : 1; /* [ 5], r/w, 0x0 */ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ uint32_t cr_axi_swap_mode : 1; /* [ 7], r/w, 0x0 */ uint32_t cr_axi_swap_idx_sel : 4; /* [11: 8], r/w, 0x0 */ uint32_t cr_axi_swap_idx_swm : 1; /* [ 12], r/w, 0x0 */ uint32_t cr_axi_swap_idx_swv : 1; /* [ 13], r/w, 0x0 */ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ uint32_t cr_axi_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ uint32_t cr_axi_b0_sel : 2; /* [21:20], r/w, 0x0 */ uint32_t cr_axi_b1_sel : 2; /* [23:22], r/w, 0x1 */ uint32_t cr_axi_b2_sel : 2; /* [25:24], r/w, 0x2 */ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ } BF; uint32_t WORD; } config; /* 0x4 : frame_size_h */ union { struct { uint32_t cr_total_h : 12; /* [11: 0], r/w, 0x897 */ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ uint32_t cr_blank_h : 12; /* [27:16], r/w, 0x117 */ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ } BF; uint32_t WORD; } frame_size_h; /* 0x8 : frame_size_v */ union { struct { uint32_t cr_total_v : 12; /* [11: 0], r/w, 0x464 */ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ uint32_t cr_blank_v : 12; /* [27:16], r/w, 0x2c */ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ } BF; uint32_t WORD; } frame_size_v; /* 0xC : frame_size_cea_861 */ union { struct { uint32_t cr_h_duration : 8; /* [ 7: 0], r/w, 0x83 */ uint32_t cr_h_placement : 8; /* [15: 8], r/w, 0x57 */ uint32_t cr_v_duration : 8; /* [23:16], r/w, 0x8 */ uint32_t cr_v_placement : 8; /* [31:24], r/w, 0x3 */ } BF; uint32_t WORD; } frame_size_cea_861; /* 0x10 : pix_data_range */ union { struct { uint32_t cr_data_min : 16; /* [15: 0], r/w, 0x0 */ uint32_t cr_data_max : 16; /* [31:16], r/w, 0xffff */ } BF; uint32_t WORD; } pix_data_range; /* 0x14 : pix_data_step */ union { struct { uint32_t cr_data_step : 8; /* [ 7: 0], r/w, 0x1 */ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ } BF; uint32_t WORD; } pix_data_step; /* 0x18 reserved */ uint8_t RESERVED0x18[8]; /* 0x20 : axi2dvp_setting */ union { struct { uint32_t cr_axi_xlen : 3; /* [ 2: 0], r/w, 0x3 */ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ uint32_t cr_axi_drain_err_clr : 1; /* [ 4], w1p, 0x0 */ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ uint32_t cr_axi_420_mode : 1; /* [ 8], r/w, 0x0 */ uint32_t cr_axi_420_ud_sel : 1; /* [ 9], r/w, 0x0 */ uint32_t cr_qos_sw_mode : 1; /* [ 10], r/w, 0x0 */ uint32_t cr_qos_sw : 1; /* [ 11], r/w, 0x0 */ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ } BF; uint32_t WORD; } axi2dvp_setting; /* 0x24 : axi2dvp_start_addr_by */ union { struct { uint32_t cr_axi_addr_start_by : 32; /* [31: 0], r/w, 0x0 */ } BF; uint32_t WORD; } axi2dvp_start_addr_by; /* 0x28 : axi2dvp_burst_cnt */ union { struct { uint32_t cr_axi_frame_bc : 32; /* [31: 0], r/w, 0x0 */ } BF; uint32_t WORD; } axi2dvp_burst_cnt; /* 0x2C : axi2dvp_status */ union { struct { uint32_t st_axi_fifo_cnt_by : 7; /* [ 6: 0], r, 0x0 */ uint32_t st_axi_drain_error_by : 1; /* [ 7], r, 0x0 */ uint32_t st_axi_state_idle_by : 1; /* [ 8], r, 0x0 */ uint32_t st_axi_state_func_by : 1; /* [ 9], r, 0x0 */ uint32_t st_axi_state_flsh_by : 1; /* [ 10], r, 0x0 */ uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ uint32_t st_axi_fifo_cnt_uv : 7; /* [22:16], r, 0x0 */ uint32_t st_axi_drain_error_uv : 1; /* [ 23], r, 0x0 */ uint32_t st_axi_state_idle_uv : 1; /* [ 24], r, 0x0 */ uint32_t st_axi_state_func_uv : 1; /* [ 25], r, 0x0 */ uint32_t st_axi_state_flsh_uv : 1; /* [ 26], r, 0x0 */ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ } BF; uint32_t WORD; } axi2dvp_status; /* 0x30 : axi2dvp_swap_addr_by */ union { struct { uint32_t cr_axi_addr_swap_by : 32; /* [31: 0], r/w, 0x0 */ } BF; uint32_t WORD; } axi2dvp_swap_addr_by; /* 0x34 : axi2dvp_prefetch */ union { struct { uint32_t cr_prefetch_v : 12; /* [11: 0], r/w, 0x28 */ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ } BF; uint32_t WORD; } axi2dvp_prefetch; /* 0x38 : snsr2dvp_wait_pos */ union { struct { uint32_t cr_snsr_fifo_th : 11; /* [10: 0], r/w, 0x8b */ uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ } BF; uint32_t WORD; } snsr2dvp_wait_pos; /* 0x3c reserved */ uint8_t RESERVED0x3c[4]; /* 0x40 : axi2dvp_start_addr_uv */ union { struct { uint32_t cr_axi_addr_start_uv : 32; /* [31: 0], r/w, 0x0 */ } BF; uint32_t WORD; } axi2dvp_start_addr_uv; /* 0x44 : axi2dvp_swap_addr_uv */ union { struct { uint32_t cr_axi_addr_swap_uv : 32; /* [31: 0], r/w, 0x0 */ } BF; uint32_t WORD; } axi2dvp_swap_addr_uv; }; typedef volatile struct dtsrc_reg dtsrc_reg_t; #endif /* __DTSRC_REG_H__ */

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/* $NetBSD: zynq7000_uart.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $ */ /*- * Copyright (c) 2015 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include <sys/cdefs.h> __KERNEL_RCSID(0, "$NetBSD: zynq7000_uart.c,v 1.3 2022/10/25 22:49:39 jmcneill Exp $"); #include "opt_soc.h" #include "opt_console.h" #include <sys/param.h> #include <sys/bus.h> #include <sys/device.h> #include <arm/xilinx/zynq_uartreg.h> #include <arm/xilinx/zynq_uartvar.h> #include <dev/fdt/fdtvar.h> static const struct device_compatible_entry compat_data[] = { { .compat = "xlnx,xuartps" }, { .compat = "cdns,uart-r1p8" }, DEVICE_COMPAT_EOL }; int zynquart_match(device_t parent, struct cfdata *cf, void *aux) { struct fdt_attach_args * const faa = aux; return of_compatible_match(faa->faa_phandle, compat_data); } void zynquart_attach(device_t parent, device_t self, void *aux) { struct fdt_attach_args * faa = aux; const int phandle = faa->faa_phandle; char intrstr[128]; bus_addr_t addr; bus_size_t size; if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { aprint_error(": couldn't get registers\n"); return; } if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { aprint_error(": failed to decode interrupt\n"); return; } if (fdtbus_intr_establish(phandle, 0, IPL_SERIAL, IST_LEVEL, zynquartintr, device_private(self)) == NULL) { aprint_error(": failed to establish interrupt on %s\n", intrstr); return; } zynquart_attach_common(parent, self, faa->faa_bst, addr, size, 0); aprint_normal_dev(self, "interrupting on %s\n", intrstr); } /* * Console support */ static int zynq_uart_console_match(int phandle) { return of_compatible_match(phandle, compat_data); } static void zynq_uart_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) { const int phandle = faa->faa_phandle; bus_space_tag_t bst = faa->faa_bst; bus_addr_t addr; tcflag_t flags; int speed; fdtbus_get_reg(phandle, 0, &addr, NULL); speed = fdtbus_get_stdout_speed(); if (speed < 0) speed = 115200; /* default */ flags = fdtbus_get_stdout_flags(); if (zynquart_cons_attach(bst, addr, speed, flags)) panic("Cannot initialize zynq uart console"); } static const struct fdt_console zynq_uart_console = { .match = zynq_uart_console_match, .consinit = zynq_uart_console_consinit, }; FDT_CONSOLE(zynq_uart, &zynq_uart_console);

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/** * @file * * @date Jun 11, 2014 * @author: Anton Bondarev */ #ifndef TASK_ARGV_H_ #define TASK_ARGV_H_ struct task_argv; extern struct task_argv *task_resource_argv(const struct task *task); extern int task_resource_argv_argc(const struct task *task); extern char **task_resource_argv_argv(const struct task *task); extern void task_resource_argv_insert(const struct task *task, const char *arg, int index); extern char *task_resource_argv_path(const struct task *task); extern int argv_to_argc(char *const argv[]); #endif /* TASK_ARGV_H_ */

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/*------------------------------------------------------------------------- * * cdbdistributedxacts.c * Set-returning function to view gp_distributed_xacts table. * * IDENTIFICATION * *------------------------------------------------------------------------- */ #include "postgres.h" #include "funcapi.h" #include "access/heapam.h" #include "catalog/pg_type.h" #include "utils/builtins.h" #include "cdb/cdbutil.h" #include "cdb/cdbtm.h" Datum gp_distributed_xacts__(PG_FUNCTION_ARGS); PG_FUNCTION_INFO_V1(gp_distributed_xacts__); /* * pgdatabasev - produce a view of gp_distributed_xacts to include transient state */ Datum gp_distributed_xacts__(PG_FUNCTION_ARGS) { FuncCallContext *funcctx; TMGALLXACTSTATUS *allDistributedXactStatus; if (SRF_IS_FIRSTCALL()) { TupleDesc tupdesc; MemoryContext oldcontext; /* create a function context for cross-call persistence */ funcctx = SRF_FIRSTCALL_INIT(); /* * switch to memory context appropriate for multiple function calls */ oldcontext = MemoryContextSwitchTo(funcctx->multi_call_memory_ctx); /* build tupdesc for result tuples */ /* this had better match gp_distributed_xacts view in system_views.sql */ tupdesc = CreateTemplateTupleDesc(4); TupleDescInitEntry(tupdesc, (AttrNumber) 1, "distributed_xid", XIDOID, -1, 0); TupleDescInitEntry(tupdesc, (AttrNumber) 2, "state", TEXTOID, -1, 0); TupleDescInitEntry(tupdesc, (AttrNumber) 3, "gp_session_id", INT4OID, -1, 0); TupleDescInitEntry(tupdesc, (AttrNumber) 4, "xmin_distributed_snapshot", XIDOID, -1, 0); funcctx->tuple_desc = BlessTupleDesc(tupdesc); /* * Collect all the locking information that we will format and send * out as a result set. */ getAllDistributedXactStatus(&allDistributedXactStatus); funcctx->user_fctx = (void *) allDistributedXactStatus; MemoryContextSwitchTo(oldcontext); } funcctx = SRF_PERCALL_SETUP(); allDistributedXactStatus = (TMGALLXACTSTATUS *) funcctx->user_fctx; while (true) { TMGXACTSTATUS *distributedXactStatus; Datum values[6]; bool nulls[6]; HeapTuple tuple; Datum result; if (!getNextDistributedXactStatus(allDistributedXactStatus, &distributedXactStatus)) break; /* * Form tuple with appropriate data. */ MemSet(values, 0, sizeof(values)); MemSet(nulls, false, sizeof(nulls)); values[0] = TransactionIdGetDatum(distributedXactStatus->gxid); values[1] = CStringGetTextDatum(DtxStateToString(distributedXactStatus->state)); values[2] = UInt32GetDatum(distributedXactStatus->sessionId); values[3] = TransactionIdGetDatum(distributedXactStatus->xminDistributedSnapshot); tuple = heap_form_tuple(funcctx->tuple_desc, values, nulls); result = HeapTupleGetDatum(tuple); SRF_RETURN_NEXT(funcctx, result); } SRF_RETURN_DONE(funcctx); }

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# animation [![npm](https://img.shields.io/npm/v/@uni/animation.svg)](https://www.npmjs.com/package/@uni/animation) ## Installation ```bash $ npm install @uni/animation --save ``` ## createAnimation Create an animation instance `Animation`. You can use the **chain call** instance method to describe the animation, and finally export the animation data by the `export` method, and then bind the animation data to the component or HTML node. ### Supports <img alt="browser" src="https://gw.alicdn.com/tfs/TB1uYFobGSs3KVjSZPiXXcsiVXa-200-200.svg" width="25px" height="25px" title="h5" /> <img alt="miniApp" src="https://gw.alicdn.com/tfs/TB1bBpmbRCw3KVjSZFuXXcAOpXa-200-200.svg" width="25px" height="25px" title="阿里小程序" /> <img alt="wechatMiniprogram" src="https://img.alicdn.com/tfs/TB1slcYdxv1gK0jSZFFXXb0sXXa-200-200.svg" width="25px" height="25px" title="微信小程序" /> <img alt="bytedanceMicroApp" src="https://gw.alicdn.com/tfs/TB1jFtVzO_1gK0jSZFqXXcpaXXa-200-200.svg" width="25px" height="25px" title="字节跳动小程序" /> <img alt="baiduSmartProgram" src="https://img.alicdn.com/imgextra/i4/O1CN01jngdBb24yGv2Fu34G_!!6000000007459-2-tps-200-200.png" width="25px" height="25px" title="baiduSmartProgram" /> ### Usage ```js import { createAnimation } from '@uni/animation'; const animation = createAnimation(); animation .rotate(30) .translate(100, 50) .step(); // In the mini program, you need to pass `data` to the `animation` property of the component const data = animation.export(); // If you need to support web-side scenarios, the `export` method needs to pass in additional binding HTML node // const data = animation.export(document.getElementById('app')); ``` ## createTransition Create a transition animation. Create the transition animation through the **configuration option**, and finally export the animation data through the `export` method, and then bind the animation data to the component or HTML node (the same way as `createAnimation`). ### Supports <img alt="browser" src="https://gw.alicdn.com/tfs/TB1uYFobGSs3KVjSZPiXXcsiVXa-200-200.svg" width="25px" height="25px" title="h5" /> <img alt="miniApp" src="https://gw.alicdn.com/tfs/TB1bBpmbRCw3KVjSZFuXXcAOpXa-200-200.svg" width="25px" height="25px" title="阿里小程序" /> <img alt="wechatMiniprogram" src="https://img.alicdn.com/tfs/TB1slcYdxv1gK0jSZFFXXb0sXXa-200-200.svg" width="25px" height="25px" title="微信小程序" /> <img alt="bytedanceMicroApp" src="https://gw.alicdn.com/tfs/TB1jFtVzO_1gK0jSZFqXXcpaXXa-200-200.svg" width="25px" height="25px" title="字节跳动小程序" /> ### Usage ```js import { createTransition } from '@uni/animation'; const transition = createTransition({ from: { opacity: 0.6, transform: 'translate(10px, 10px) scale(1)' }, to: { opacity: 1, transform: 'translate(100px, 50px) scale(1.2)' }, options: { duration: 350 } }); // In the mini-program, you need to pass `data` to the `animation` property of the component const data = transition.export(); // If you need to support web-side scenarios, the `export` method needs to pass in additional binding HTML node // const data = animation.export(document.getElementById('app')); ``` ```jsx | inline import React from 'react'; export default class Home extends React.Component { componentDidMount() { document.querySelector('.__dumi-default-menu').style.background = '#fff'; if (location.search.split(/[?&]/).some(i => i === 'clear=1')) { document.querySelector('.__dumi-default-navbar').style.display = 'none'; document.querySelector('.__dumi-default-layout').classList = []; document.querySelector('.__dumi-default-menu').style.display = 'none'; document.querySelector('.__dumi-default-layout-toc').style.display = 'none'; document.querySelector('.__dumi-default-layout-content').querySelector('.markdown').querySelector('h1').style.marginTop = 0; parent.postMessage && parent.postMessage(parent.postMessage({ event: 'syncIframeHeight', height: document.querySelector('.__dumi-default-layout-content').offsetHeight }, '*')); } } render() { return null; } } ```

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/* GTK - The GIMP Toolkit * Copyright (C) 2017 Red Hat, Inc. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library. If not, see <http://www.gnu.org/licenses/>. * * Author: Matthias Clasen */ #include "config.h" #include <gtk/css/gtkcss.h> #include "gtk/css/gtkcsstokenizerprivate.h" #include "gtk/css/gtkcssparserprivate.h" #include "gtkcssnumbervalueprivate.h" #include "gtkcssfontvariationsvalueprivate.h" struct _GtkCssValue { GTK_CSS_VALUE_BASE GHashTable *axes; }; static GtkCssValue *default_font_variations; static GtkCssValue *gtk_css_font_variations_value_new_empty (void); static void gtk_css_font_variations_value_add_axis (GtkCssValue *value, const char *name, GtkCssValue *coord) { g_hash_table_insert (value->axes, g_strdup (name), coord); } static void gtk_css_value_font_variations_free (GtkCssValue *value) { g_hash_table_unref (value->axes); g_slice_free (GtkCssValue, value); } static GtkCssValue * gtk_css_value_font_variations_compute (GtkCssValue *specified, guint property_id, GtkStyleProvider *provider, GtkCssStyle *style, GtkCssStyle *parent_style) { return _gtk_css_value_ref (specified); } static gboolean gtk_css_value_font_variations_equal (const GtkCssValue *value1, const GtkCssValue *value2) { gpointer name, coord1, coord2; GHashTableIter iter; if (g_hash_table_size (value1->axes) != g_hash_table_size (value2->axes)) return FALSE; g_hash_table_iter_init (&iter, value1->axes); while (g_hash_table_iter_next (&iter, &name, &coord1)) { coord2 = g_hash_table_lookup (value2->axes, name); if (coord2 == NULL) return FALSE; if (!_gtk_css_value_equal (coord1, coord2)) return FALSE; } return TRUE; } static GtkCssValue * gtk_css_value_font_variations_transition (GtkCssValue *start, GtkCssValue *end, guint property_id, double progress) { const char *name; GtkCssValue *start_coord, *end_coord; GHashTableIter iter; GtkCssValue *result, *transition; /* XXX: For value that are only in start or end but not both, * we don't transition but just keep the value. * That causes an abrupt transition to the new value at the end. */ result = gtk_css_font_variations_value_new_empty (); g_hash_table_iter_init (&iter, start->axes); while (g_hash_table_iter_next (&iter, (gpointer *)&name, (gpointer *)&start_coord)) { end_coord = g_hash_table_lookup (end->axes, name); if (end_coord == NULL) transition = _gtk_css_value_ref (start_coord); else transition = _gtk_css_value_transition (start_coord, end_coord, property_id, progress); gtk_css_font_variations_value_add_axis (result, name, transition); } g_hash_table_iter_init (&iter, end->axes); while (g_hash_table_iter_next (&iter, (gpointer *)&name, (gpointer *)&end_coord)) { start_coord = g_hash_table_lookup (start->axes, name); if (start_coord != NULL) continue; gtk_css_font_variations_value_add_axis (result, name, _gtk_css_value_ref (end_coord)); } return result; } static void gtk_css_value_font_variations_print (const GtkCssValue *value, GString *string) { GHashTableIter iter; const char *name; GtkCssValue *coord; gboolean first = TRUE; if (value == default_font_variations) { g_string_append (string, "normal"); return; } g_hash_table_iter_init (&iter, value->axes); while (g_hash_table_iter_next (&iter, (gpointer *)&name, (gpointer *)&coord)) { if (first) first = FALSE; else g_string_append (string, ", "); g_string_append_printf (string, "\"%s\" ", name); _gtk_css_value_print (coord, string); } } static const GtkCssValueClass GTK_CSS_VALUE_FONT_VARIATIONS = { "GtkCssFontVariationsValue", gtk_css_value_font_variations_free, gtk_css_value_font_variations_compute, gtk_css_value_font_variations_equal, gtk_css_value_font_variations_transition, NULL, NULL, gtk_css_value_font_variations_print }; static GtkCssValue * gtk_css_font_variations_value_new_empty (void) { GtkCssValue *result; result = _gtk_css_value_new (GtkCssValue, &GTK_CSS_VALUE_FONT_VARIATIONS); result->axes = g_hash_table_new_full (g_str_hash, g_str_equal, g_free, (GDestroyNotify) _gtk_css_value_unref); result->is_computed = TRUE; return result; } GtkCssValue * gtk_css_font_variations_value_new_default (void) { if (default_font_variations == NULL) default_font_variations = gtk_css_font_variations_value_new_empty (); return _gtk_css_value_ref (default_font_variations); } static gboolean is_valid_opentype_tag (const char *s) { if (strlen (s) != 4) return FALSE; if (s[0] < 0x20 || s[0] > 0x7e || s[1] < 0x20 || s[1] > 0x7e || s[2] < 0x20 || s[2] > 0x7e || s[3] < 0x20 || s[3] > 0x7e) return FALSE; return TRUE; } GtkCssValue * gtk_css_font_variations_value_parse (GtkCssParser *parser) { GtkCssValue *result, *coord; char *name; if (gtk_css_parser_try_ident (parser, "normal")) return gtk_css_font_variations_value_new_default (); result = gtk_css_font_variations_value_new_empty (); do { name = gtk_css_parser_consume_string (parser); if (name == NULL) { _gtk_css_value_unref (result); return NULL; } if (!is_valid_opentype_tag (name)) { gtk_css_parser_error_value (parser, "Not a valid OpenType tag."); g_free (name); _gtk_css_value_unref (result); return NULL; } coord = _gtk_css_number_value_parse (parser, GTK_CSS_PARSE_NUMBER); if (coord == NULL) { g_free (name); _gtk_css_value_unref (result); return NULL; } gtk_css_font_variations_value_add_axis (result, name, coord); g_free (name); } while (gtk_css_parser_try_token (parser, GTK_CSS_TOKEN_COMMA)); return result; } char * gtk_css_font_variations_value_get_variations (GtkCssValue *value) { GtkCssValue *coord; GHashTableIter iter; gboolean first = TRUE; const char *name; GString *string; g_return_val_if_fail (value->class == &GTK_CSS_VALUE_FONT_VARIATIONS, NULL); if (value == default_font_variations) return NULL; string = g_string_new (""); g_hash_table_iter_init (&iter, value->axes); while (g_hash_table_iter_next (&iter, (gpointer *)&name, (gpointer *)&coord)) { if (first) first = FALSE; else g_string_append (string, ","); g_string_append_printf (string, "%s=%g", name, _gtk_css_number_value_get (coord, 100)); } return g_string_free (string, FALSE); }

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// ------------------------------------------------------------------------------ // // Copyright (c) 2017, Pete Batard. All rights reserved.<BR> // Copyright (c) 2021, Arm Limited. All rights reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent // // ------------------------------------------------------------------------------ #if defined (_M_ARM64) typedef unsigned __int64 size_t; #else typedef unsigned __int32 size_t; #endif void * memset ( void *, int, size_t ); #pragma intrinsic(memset) #pragma function(memset) void * memset ( void *s, int c, size_t n ) { unsigned char *d; d = s; while (n-- != 0) { *d++ = (unsigned char)c; } return s; }

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/* $OpenBSD: octeon_pcibus.h,v 1.3 2015/07/20 01:38:31 jasper Exp $ */ /* * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.com). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #ifndef ___OCTEON_PCIBUS_H__ #define ___OCTEON_PCIBUS_H__ #include <machine/octeonreg.h> #define OCTEON_PCIBUS_PCIIO_BASE 0x11A0000000000ULL #define OCTEON_PCI_CFG0 0x80011F0000001804ULL #define OCTEON_PCI_CFG1 0x80011F0000001800ULL #define OCTEON_PCI_CONFIG_BASE0 0x8001190000000004ULL #define OCTEON_PCI_CONFIG_BASE1 0x8001190000000000ULL #define OCTEON_PCI_CFG2 (OCTEON_PCI_CFG0 + 0x08UL) #define OCTEON_PCI_CFG3 (OCTEON_PCI_CFG1 + 0x08UL) #define OCTEON_PCI_CFG4 (OCTEON_PCI_CFG0 + 0x10UL) #define OCTEON_PCI_CFG5 (OCTEON_PCI_CFG1 + 0x10UL) #define OCTEON_PCI_CFG6 (OCTEON_PCI_CFG0 + 0x18UL) #define OCTEON_PCI_CFG7 (OCTEON_PCI_CFG1 + 0x18UL) #define OCTEON_PCI_CFG8 (OCTEON_PCI_CFG0 + 0x20UL) #define OCTEON_PCI_CFG9 (OCTEON_PCI_CFG1 + 0x20UL) #define OCTEON_PCI_CFG10 (OCTEON_PCI_CFG0 + 0x28UL) #define OCTEON_PCI_CFG11 (OCTEON_PCI_CFG1 + 0x28UL) #define OCTEON_PCI_CFG12 (OCTEON_PCI_CFG0 + 0x30UL) #define OCTEON_PCI_CFG13 (OCTEON_PCI_CFG1 + 0x30UL) #define OCTEON_PCI_CFG14 (OCTEON_PCI_CFG0 + 0x38UL) #define OCTEON_PCI_CFG15 (OCTEON_PCI_CFG1 + 0x38UL) #define OCTEON_PCI_CFG16 (OCTEON_PCI_CFG0 + 0x40UL) #define OCTEON_PCI_CFG17 (OCTEON_PCI_CFG1 + 0x40UL) #define OCTEON_PCI_CFG18 (OCTEON_PCI_CFG0 + 0x48UL) #define OCTEON_PCI_CFG19 (OCTEON_PCI_CFG1 + 0x48UL) #define OCTEON_PCI_CFG20 (OCTEON_PCI_CFG0 + 0x50UL) #define OCTEON_PCI_CFG21 (OCTEON_PCI_CFG1 + 0x50UL) #define OCTEON_PCI_CFG22 (OCTEON_PCI_CFG0 + 0x58UL) #define OCTEON_PCI_CFG23 (OCTEON_PCI_CFG1 + 0x58UL) #define OCTEON_PCI_CFG24 (OCTEON_PCI_CFG0 + 0x60UL) #define OCTEON_PCI_CFG25 (OCTEON_PCI_CFG1 + 0x60UL) #define OCTEON_PCI_CFG26 (OCTEON_PCI_CFG0 + 0x68UL) #define OCTEON_PCI_CFG27 (OCTEON_PCI_CFG1 + 0x68UL) #define OCTEON_PCI_CFG28 (OCTEON_PCI_CFG0 + 0x70UL) #define OCTEON_PCI_CFG29 (OCTEON_PCI_CFG1 + 0x70UL) #define OCTEON_PCI_CFG30 (OCTEON_PCI_CFG0 + 0x78UL) #define OCTEON_PCI_CFG31 (OCTEON_PCI_CFG1 + 0x78UL) #define OCTEON_PCI_CFG32 (OCTEON_PCI_CFG0 + 0x80UL) #define OCTEON_PCI_CFG33 (OCTEON_PCI_CFG1 + 0x80UL) #define OCTEON_PCI_CFG34 (OCTEON_PCI_CFG0 + 0x88UL) #define OCTEON_PCI_CFG35 (OCTEON_PCI_CFG1 + 0x88UL) #define OCTEON_PCI_CFG36 (OCTEON_PCI_CFG0 + 0x90UL) #define OCTEON_PCI_CFG37 (OCTEON_PCI_CFG1 + 0x90UL) #define OCTEON_PCI_CFG38 (OCTEON_PCI_CFG0 + 0x98UL) #define OCTEON_PCI_CFG39 (OCTEON_PCI_CFG1 + 0x98UL) #define OCTEON_PCI_CFG40 (OCTEON_PCI_CFG0 + 0xA0UL) #define OCTEON_PCI_CFG41 (OCTEON_PCI_CFG1 + 0xA0UL) #define OCTEON_PCI_CFG42 (OCTEON_PCI_CFG0 + 0xA8UL) #define OCTEON_PCI_CFG43 (OCTEON_PCI_CFG1 + 0xA8UL) #define OCTEON_PCI_CFG44 (OCTEON_PCI_CFG0 + 0xB0UL) #define OCTEON_PCI_CFG45 (OCTEON_PCI_CFG1 + 0xB0UL) #define OCTEON_PCI_CFG46 (OCTEON_PCI_CFG0 + 0xB8UL) #define OCTEON_PCI_CFG47 (OCTEON_PCI_CFG1 + 0xB8UL) #define OCTEON_PCI_CFG48 (OCTEON_PCI_CFG0 + 0xC0UL) #define OCTEON_PCI_CFG49 (OCTEON_PCI_CFG1 + 0xC0UL) #define OCTEON_PCI_CFG50 (OCTEON_PCI_CFG0 + 0xC8UL) #define OCTEON_PCI_CFG51 (OCTEON_PCI_CFG1 + 0xC8UL) #define OCTEON_PCI_CFG52 (OCTEON_PCI_CFG0 + 0xD0UL) #define OCTEON_PCI_CFG53 (OCTEON_PCI_CFG1 + 0xD0UL) #define OCTEON_PCI_CFG54 (OCTEON_PCI_CFG0 + 0xD8UL) #define OCTEON_PCI_CFG55 (OCTEON_PCI_CFG1 + 0xD8UL) #define OCTEON_PCI_CFG56 (OCTEON_PCI_CFG0 + 0xE0UL) #define OCTEON_PCI_CFG57 (OCTEON_PCI_CFG1 + 0xE0UL) #define OCTEON_PCI_CFG58 (OCTEON_PCI_CFG0 + 0xE8UL) #define OCTEON_PCI_CFG59 (OCTEON_PCI_CFG1 + 0xE8UL) #define OCTEON_PCI_CFG60 (OCTEON_PCI_CFG0 + 0xF0UL) #define OCTEON_PCI_CFG61 (OCTEON_PCI_CFG1 + 0xF0UL) #define OCTEON_PCI_CFG62 (OCTEON_PCI_CFG0 + 0xF8UL) #define OCTEON_PCI_CFG63 (OCTEON_PCI_CFG1 + 0xF8UL) #define OCTEON_PCIBUS_PCIMAPCFG_TYPE1 0x00010000 #endif /* ___OCTEON_PCIBUS_H__ */

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/* obsolete primitives for backward compatibility */ #if OLD_SOUND_PRIMS int primFMSoundmixSampleCountintostartingAtpan(void); int oldprimSampledSoundmixSampleCountintostartingAtleftVolrightVol(void); int primPluckedSoundmixSampleCountintostartingAtpan(void); int primSampledSoundmixSampleCountintostartingAtpan(void); int primWaveTableSoundmixSampleCountintostartingAtpan(void); #endif /* OLD_SOUND_PRIMS */

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/* * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-04-25 tyx the first version */ #include <rtthread.h> #include <rtdevice.h> #include <hw_bignum.h> static struct rt_hwcrypto_ctx *bignum_default; rt_inline rt_err_t hwcrypto_bignum_dev_is_init(void) { struct rt_hwcrypto_device *dev; if (bignum_default) { return RT_EOK; } dev = rt_hwcrypto_dev_default(); if (dev == RT_NULL) { return -RT_ERROR; } return rt_hwcrypto_bignum_default(dev); } /** * @brief Setting bignum default devices * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_default(struct rt_hwcrypto_device *device) { if (bignum_default) { rt_hwcrypto_ctx_destroy(bignum_default); bignum_default = RT_NULL; } if (device == RT_NULL) { return RT_EOK; } bignum_default = rt_hwcrypto_ctx_create(device, HWCRYPTO_TYPE_BIGNUM, sizeof(struct hwcrypto_bignum)); if (bignum_default == RT_NULL) { return -RT_ERROR; } return RT_EOK; } /** * @brief Init bignum obj * * @param n bignum obj */ void rt_hwcrypto_bignum_init(struct hw_bignum_mpi *n) { if(n == RT_NULL) return; n->sign = 1; n->total = 0; n->p = RT_NULL; } /** * @brief free a bignum obj * * @param Pointer to bignum obj */ void rt_hwcrypto_bignum_free(struct hw_bignum_mpi *n) { if (n) { rt_memset(n->p, 0xFF, n->total); rt_free(n->p); n->sign = 0; n->total = 0; n->p = RT_NULL; } } /** * @brief Get length of bignum as an unsigned binary buffer * * @param n bignum obj * * @return binary buffer length */ int rt_hwcrypto_bignum_get_len(const struct hw_bignum_mpi *n) { int tmp_len, total; if (n == RT_NULL || n->p == RT_NULL) { return 0; } tmp_len = 0; total = n->total; while ((total > 0) && (n->p[total - 1] == 0)) { tmp_len++; total--; } return n->total - tmp_len; } /** * @brief Export n into unsigned binary data, big endian * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer * * @return export bin length */ int rt_hwcrypto_bignum_export_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len) { int cp_len, i, j; if (n == RT_NULL || buf == RT_NULL) { return 0; } rt_memset(buf, 0, len); cp_len = (int)n->total > len ? len : (int)n->total; for(i = cp_len, j = 0; i > 0; i--, j++) { buf[i - 1] = n->p[j]; } return cp_len; } /** * @brief Import n from unsigned binary data, big endian * * @param n bignum obj * @param buf Buffer for the binary number * @param len Length of the buffer * * @return import length. */ int rt_hwcrypto_bignum_import_bin(struct hw_bignum_mpi *n, rt_uint8_t *buf, int len) { int cp_len, i, j; void *temp_p; if (n == RT_NULL || buf == RT_NULL) { return 0; } if ((int)n->total < len) { temp_p = rt_malloc(len); if (temp_p == RT_NULL) { return 0; } rt_free(n->p); n->p = temp_p; n->total = len; } n->sign = 1; rt_memset(n->p, 0, n->total); cp_len = (int)n->total > len ? len : n->total; for(i = cp_len, j = 0; i > 0; i--, j++) { n->p[j] = buf[i - 1]; } return cp_len; } /** * @brief x = a + b * * @param a bignum obj * @param b bignum obj * @param c bignum obj * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_add(struct hw_bignum_mpi *x, const struct hw_bignum_mpi *a, const struct hw_bignum_mpi *b) { struct hwcrypto_bignum *bignum_ctx; if (hwcrypto_bignum_dev_is_init() != RT_EOK) { return -RT_ERROR; } bignum_ctx = (struct hwcrypto_bignum *)bignum_default; if (bignum_ctx->ops->add) { return bignum_ctx->ops->add(bignum_ctx, x, a, b); } return -RT_ERROR; } /** * @brief x = a - b * * @param a bignum obj * @param b bignum obj * @param c bignum obj * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_sub(struct hw_bignum_mpi *x, const struct hw_bignum_mpi *a, const struct hw_bignum_mpi *b) { struct hwcrypto_bignum *bignum_ctx; if (hwcrypto_bignum_dev_is_init() != RT_EOK) { return -RT_ERROR; } bignum_ctx = (struct hwcrypto_bignum *)bignum_default; if (bignum_ctx->ops->sub) { return bignum_ctx->ops->sub(bignum_ctx, x, a, b); } return -RT_ERROR; } /** * @brief x = a * b * * @param a bignum obj * @param b bignum obj * @param c bignum obj * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mul(struct hw_bignum_mpi *x, const struct hw_bignum_mpi *a, const struct hw_bignum_mpi *b) { struct hwcrypto_bignum *bignum_ctx; if (hwcrypto_bignum_dev_is_init() != RT_EOK) { return -RT_ERROR; } bignum_ctx = (struct hwcrypto_bignum *)bignum_default; if (bignum_ctx->ops->mul) { return bignum_ctx->ops->mul(bignum_ctx, x, a, b); } return -RT_ERROR; } /** * @brief x = a * b (mod c) * * @param a bignum obj * @param b bignum obj * @param c bignum obj * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_mulmod(struct hw_bignum_mpi *x, const struct hw_bignum_mpi *a, const struct hw_bignum_mpi *b, const struct hw_bignum_mpi *c) { struct hwcrypto_bignum *bignum_ctx; if (hwcrypto_bignum_dev_is_init() != RT_EOK) { return -RT_ERROR; } bignum_ctx = (struct hwcrypto_bignum *)bignum_default; if (bignum_ctx->ops->mulmod) { return bignum_ctx->ops->mulmod(bignum_ctx, x, a, b, c); } return -RT_ERROR; } /** * @brief x = a ^ b (mod c) * * @param a bignum obj * @param b bignum obj * @param c bignum obj * * @return RT_EOK on success. */ rt_err_t rt_hwcrypto_bignum_exptmod(struct hw_bignum_mpi *x, const struct hw_bignum_mpi *a, const struct hw_bignum_mpi *b, const struct hw_bignum_mpi *c) { struct hwcrypto_bignum *bignum_ctx; if (hwcrypto_bignum_dev_is_init() != RT_EOK) { return -RT_ERROR; } bignum_ctx = (struct hwcrypto_bignum *)bignum_default; if (bignum_ctx->ops->exptmod) { return bignum_ctx->ops->exptmod(bignum_ctx, x, a, b, c); } return -RT_ERROR; }

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#include <ccd/ccd.h> int main() { ccd_t ccd; CCD_INIT(&ccd); return 0; }

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ssl_port.h

/**************************************************************************** * * Copyright 2019 Samsung Electronics All Rights Reserved. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, * software distributed under the License is distributed on an * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, * either express or implied. See the License for the specific * language governing permissions and limitations under the License. * ****************************************************************************/ // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #ifndef _SSL_PORT_H_ #define _SSL_PORT_H_ #include <string.h> #include <stdlib.h> #include <stdio.h> #ifdef __cplusplus extern "C" { #endif #define ssl_mem_zalloc(s) zalloc(s) #define ssl_mem_malloc(s) malloc(s) #define ssl_mem_free(p) free(p) #define ssl_memcpy memcpy #define ssl_strlen strlen #ifdef CONFIG_SMP #define ssl_speed_up_enter() rtc_clk_cpu_freq_set(RTC_CPU_FREQ_160M) #define ssl_speed_up_exit() rtc_clk_cpu_freq_set(RTC_CPU_FREQ_80M) #else #define ssl_speed_up_enter() #define ssl_speed_up_exit() #endif #define SSL_DEBUG_LOG printf #endif

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/* * Copyright 2015 Naver Corp. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _GW_ARRAY_H_ #define _GW_ARRAY_H_ #include "zmalloc.h" #define ARRAY_HEAD(name, type, count) \ struct name { \ int nelem; \ int nfixed; \ int nextend; \ type fixed[(count)]; \ type *extend; \ } #define ARRAY_INIT(head) do { \ (head)->nelem = 0; \ (head)->nfixed = sizeof((head)->fixed)/sizeof((head)->fixed[0]); \ (head)->nextend = 0; \ (head)->extend = NULL; \ } while (/*CONSTCOND*/0) #define ARRAY_FINALIZE(head) do { \ if ((head)->extend) { \ zfree((head)->extend); \ } \ (head)->extend = NULL; \ (head)->nelem = 0; \ (head)->nextend = 0; \ } while (/*CONSTCOND*/0) #define ARRAY_PUSH(head, data) do { \ if ((head)->nelem < (head)->nfixed) { \ (head)->fixed[(head)->nelem++] = data; \ } else if ((head)->nelem - (head)->nfixed < (head)->nextend) { \ (head)->extend[(head)->nelem - (head)->nfixed] = data; \ (head)->nelem++; \ } else { \ (head)->extend = \ zrealloc((head)->extend, sizeof((head)->fixed[0])*(head)->nelem*2); \ (head)->nextend = (head)->nelem*2; \ (head)->extend[(head)->nelem - (head)->nfixed] = data; \ (head)->nelem++; \ } \ } while (/*CONSTCOND*/0) #define ARRAY_GET(head, idx) \ (((head)->nfixed > (idx)) \ ? ((head)->fixed[(idx)]) \ : ((head)->extend[(idx) - (head)->nfixed])) #define ARRAY_GET_PTR(head, idx) \ (((head)->nfixed > (idx)) \ ? (&(head)->fixed[(idx)]) \ : (&(head)->extend[(idx) - (head)->nfixed])) #define ARRAY_SET(head, idx, value) do { \ if ((head)->nfixed > (idx)) { \ (head)->fixed[(idx)] = value; \ } else { \ (head)->extend[(idx) - (head)->nfixed] = value; \ } \ } while (/*CONSTCOND*/0) #define ARRAY_CLEAR(head) ((head)->nelem = 0) #define ARRAY_N(head) ((head)->nelem) #define ARRAY_DEL(head, elem, equal) do { \ int i, found = 0; \ for (i = 0; i < ARRAY_N((head)); i++) { \ if ((equal)(ARRAY_GET((head), i), (elem))) { \ found = 1; \ break; \ } \ } \ if (!found) break; \ for (i = i + 1; i < ARRAY_N((head)); i++) { \ *(ARRAY_GET_PTR((head), i-1)) = ARRAY_GET((head), i); \ } \ if ((head)->nelem > 0) { \ (head)->nelem--; \ } \ } while (/*CONSTCOND*/0) #endif

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/* * PowerPC atomic operations */ #ifndef _ASM_PPC_ATOMIC_H_ #define _ASM_PPC_ATOMIC_H_ #ifdef CONFIG_SMP typedef struct { volatile int counter; } atomic_t; #else typedef struct { int counter; } atomic_t; #endif #define ATOMIC_INIT(i) { (i) } #define atomic_read(v) ((v)->counter) #define atomic_set(v,i) (((v)->counter) = (i)) extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); extern void atomic_set_mask(unsigned long mask, unsigned long *addr); extern __inline__ int atomic_add_return(int a, atomic_t *v) { int t; __asm__ __volatile__("\n\ 1: lwarx %0,0,%3\n\ add %0,%2,%0\n\ stwcx. %0,0,%3\n\ bne- 1b" : "=&r" (t), "=m" (*v) : "r" (a), "r" (v), "m" (*v) : "cc"); return t; } extern __inline__ int atomic_sub_return(int a, atomic_t *v) { int t; __asm__ __volatile__("\n\ 1: lwarx %0,0,%3\n\ subf %0,%2,%0\n\ stwcx. %0,0,%3\n\ bne- 1b" : "=&r" (t), "=m" (*v) : "r" (a), "r" (v), "m" (*v) : "cc"); return t; } extern __inline__ int atomic_inc_return(atomic_t *v) { int t; __asm__ __volatile__("\n\ 1: lwarx %0,0,%2\n\ addic %0,%0,1\n\ stwcx. %0,0,%2\n\ bne- 1b" : "=&r" (t), "=m" (*v) : "r" (v), "m" (*v) : "cc"); return t; } extern __inline__ int atomic_dec_return(atomic_t *v) { int t; __asm__ __volatile__("\n\ 1: lwarx %0,0,%2\n\ addic %0,%0,-1\n\ stwcx. %0,0,%2\n\ bne 1b" : "=&r" (t), "=m" (*v) : "r" (v), "m" (*v) : "cc"); return t; } #define atomic_add(a, v) ((void) atomic_add_return((a), (v))) #define atomic_sub(a, v) ((void) atomic_sub_return((a), (v))) #define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0) #define atomic_inc(v) ((void) atomic_inc_return((v))) #define atomic_dec(v) ((void) atomic_dec_return((v))) #define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0) #endif /* _ASM_PPC_ATOMIC_H_ */

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#undef OPENSSL_LINUX #if defined(__linux) && !defined(__ANDROID__) # define OPENSSL_LINUX 1 #endif #if defined(OPENSSL_NO_ASM) # include "./opensslconf_no-asm.h" #else # include "./opensslconf_asm.h" #endif /* GOST is not included in all platform */ #ifndef OPENSSL_NO_GOST # define OPENSSL_NO_GOST #endif /* HW_PADLOCK is not included in all platform */ #ifndef OPENSSL_NO_HW_PADLOCK # define OPENSSL_NO_HW_PADLOCK #endif /* musl in Alpine Linux does not support getcontext etc.*/ #if defined(OPENSSL_LINUX) && !defined(__GLIBC__) && !defined(__clang__) # define OPENSSL_NO_ASYNC #endif

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/******************************************************************************************* * * raygui - basic calculator app with custom input box for float values * * DEPENDENCIES: * raylib 4.5 - Windowing/input management and drawing. * raygui 3.5 - Immediate-mode GUI controls. * * COMPILATION (Windows - MinGW): * gcc -o $(NAME_PART).exe $(FILE_NAME) -I../../src -lraylib -lopengl32 -lgdi32 -std=c99 * **********************************************************************************************/ #include <raylib.h> #define RAYGUI_IMPLEMENTATION #include <raygui.h> int guiFloatingPointIndex = 0; // Global variable shared by all GuiFLoatBox() float TextToFloat(const char* text); // Helper function that converts text to float int GuiFloatBox(Rectangle bounds, const char* text, float* value, int minValue, int maxValue, bool editMode); // Custom input box that works with float values. Basicly GuiValueBox(), but with some changes int main() { InitWindow(250, 100, "Basic calculator"); // General variables SetTargetFPS(60); float variableA = 0.0f; float variableB = 0.0f; float result = 0.0f; char operation[2]; operation[0] = '+'; operation[1] = '\0'; bool variableAMode = false; bool variableBMode = false; //-------------------------------------------------------------------------------------- // Main game loop while (!WindowShouldClose()) { // Draw //---------------------------------------------------------------------------------- BeginDrawing(); ClearBackground(RAYWHITE); if (GuiFloatBox((Rectangle){ 10, 10, 100, 20 }, NULL, &variableA, -1000000.0, 1000000.0, variableAMode)) variableAMode = !variableAMode; if (GuiFloatBox((Rectangle){ 140, 10, 100, 20 }, NULL, &variableB, -1000000.0, 1000000.0, variableBMode)) variableBMode = !variableBMode; if (GuiButton((Rectangle){ 10, 70, 50, 20 }, "+")) { result = variableA + variableB; operation[0] = '+'; } if (GuiButton((Rectangle){ 70, 70, 50, 20 }, "-")) { result = variableA - variableB; operation[0] = '-'; } if (GuiButton((Rectangle){ 130, 70, 50, 20 }, "*")) { result = variableA * variableB; operation[0] = '*'; } if (GuiButton((Rectangle){ 190, 70, 50, 20 }, "/")) { result = variableA / variableB; operation[0] = '/'; } DrawText(operation, 123, 15, 10, DARKGRAY); GuiFloatBox((Rectangle){ 55, 40, 135, 20 }, "= ", &result, -2000000.0, 2000000.0, false); EndDrawing(); //---------------------------------------------------------------------------------- } CloseWindow(); } // Get float value from text float TextToFloat(const char* text) { float value = 0.0f; float floatingPoint = 0.0f; int sign = 1; // deal with the sign if ((text[0] == '+') || (text[0] == '-')) { if (text[0] == '-') sign = -1; text++; } // convert text to float for (int i = 0; (((text[i] >= '0') && (text[i] <= '9')) || text[i] == '.'); i++) { if (text[i] == '.') { if (floatingPoint > 0.0f) break; floatingPoint = 10.0f; continue; } if (floatingPoint > 0.0f) // after encountering decimal separator { value += (float)(text[i] - '0') / floatingPoint; floatingPoint *= 10.0f; } else // before decimal separator value = value * 10.0f + (float)(text[i] - '0'); } return value * sign; } // Float Box control, updates input text with numbers int GuiFloatBox(Rectangle bounds, const char* text, float* value, int minValue, int maxValue, bool editMode) { #if !defined(RAYGUI_VALUEBOX_MAX_CHARS) #define RAYGUI_VALUEBOX_MAX_CHARS 32 #endif int result = 0; GuiState state = guiState; char textValue[RAYGUI_VALUEBOX_MAX_CHARS + 1] = "\0"; Rectangle textBounds = { 0 }; if (text != NULL) { textBounds.width = (float)GetTextWidth(text) + 2; textBounds.height = (float)GuiGetStyle(DEFAULT, TEXT_SIZE); textBounds.x = bounds.x + bounds.width + GuiGetStyle(VALUEBOX, TEXT_PADDING); textBounds.y = bounds.y + bounds.height / 2 - GuiGetStyle(DEFAULT, TEXT_SIZE) / 2; if (GuiGetStyle(VALUEBOX, TEXT_ALIGNMENT) == TEXT_ALIGN_LEFT) textBounds.x = bounds.x - textBounds.width - GuiGetStyle(VALUEBOX, TEXT_PADDING); } // Update control //-------------------------------------------------------------------- if ((state != STATE_DISABLED) && !guiLocked && !guiSliderDragging) { Vector2 mousePoint = GetMousePosition(); if (*value >= 0) sprintf(textValue, "+%.3f", *value); else sprintf(textValue, "%.3f", *value); bool valueHasChanged = false; int keyCount = (int)strlen(textValue) - guiFloatingPointIndex; if (editMode) { state = STATE_PRESSED; // Only allow keys in range [48..57] if (keyCount < RAYGUI_VALUEBOX_MAX_CHARS) { if (GetTextWidth(textValue) < bounds.width) { int key = GetCharPressed(); if ((key >= 48) && (key <= 57) && guiFloatingPointIndex) { if (guiFloatingPointIndex && guiFloatingPointIndex != 4) guiFloatingPointIndex--; textValue[keyCount] = (char)key; textValue[++keyCount] = '\0'; valueHasChanged = true; } } } // Delete text if (keyCount > 0) { if (IsKeyPressed(KEY_BACKSPACE)) { if (guiFloatingPointIndex < 4) guiFloatingPointIndex++; keyCount--; textValue[keyCount] = '\0'; valueHasChanged = true; } } // Change sign if (IsKeyPressed(KEY_MINUS)) { if (textValue[0] == '+') textValue[0] = '-'; else if (textValue[0] == '-') textValue[0] = '+'; valueHasChanged = true; } // Add decimal separator if ((IsKeyPressed(KEY_COMMA) || IsKeyPressed(KEY_PERIOD)) && guiFloatingPointIndex == 4) { guiFloatingPointIndex--; valueHasChanged = true; } if (valueHasChanged) { *value = TextToFloat(textValue); } if (IsKeyPressed(KEY_ENTER) || (!CheckCollisionPointRec(mousePoint, bounds) && IsMouseButtonPressed(MOUSE_LEFT_BUTTON))) { guiFloatingPointIndex = 0; result = 1; } } else { if (*value > maxValue) *value = maxValue; else if (*value < minValue) *value = minValue; if (CheckCollisionPointRec(mousePoint, bounds)) { state = STATE_FOCUSED; if (IsMouseButtonPressed(MOUSE_LEFT_BUTTON)) result = 1; } } } //-------------------------------------------------------------------- // Draw control //-------------------------------------------------------------------- Color baseColor = BLANK; sprintf(textValue, "%.3f", *value); if (state == STATE_PRESSED) { baseColor = GetColor(GuiGetStyle(VALUEBOX, BASE_COLOR_PRESSED)); textValue[(int)strlen(textValue) - guiFloatingPointIndex] = '\0'; } else if (state == STATE_DISABLED) baseColor = GetColor(GuiGetStyle(VALUEBOX, BASE_COLOR_DISABLED)); // WARNING: BLANK color does not work properly with Fade() GuiDrawRectangle(bounds, GuiGetStyle(VALUEBOX, BORDER_WIDTH), Fade(GetColor(GuiGetStyle(VALUEBOX, BORDER + (state * 3))), guiAlpha), baseColor); GuiDrawText(textValue, GetTextBounds(VALUEBOX, bounds), TEXT_ALIGN_CENTER, Fade(GetColor(GuiGetStyle(VALUEBOX, TEXT + (state * 3))), guiAlpha)); // Draw cursor if (editMode) { // NOTE: ValueBox internal text is always centered Rectangle cursor = { bounds.x + GetTextWidth(textValue) / 2 + bounds.width / 2 + 1, bounds.y + 2 * GuiGetStyle(VALUEBOX, BORDER_WIDTH), 4, bounds.height - 4 * GuiGetStyle(VALUEBOX, BORDER_WIDTH) }; GuiDrawRectangle(cursor, 0, BLANK, Fade(GetColor(GuiGetStyle(VALUEBOX, BORDER_COLOR_PRESSED)), guiAlpha)); } // Draw text label if provided GuiDrawText(text, textBounds, (GuiGetStyle(VALUEBOX, TEXT_ALIGNMENT) == TEXT_ALIGN_RIGHT) ? TEXT_ALIGN_LEFT : TEXT_ALIGN_RIGHT, Fade(GetColor(GuiGetStyle(LABEL, TEXT + (state * 3))), guiAlpha)); //-------------------------------------------------------------------- return result; }

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/* +----------------------------------------------------------------------+ | Swoole | +----------------------------------------------------------------------+ | Copyright (c) 2012-2015 The Swoole Group | +----------------------------------------------------------------------+ | This source file is subject to version 2.0 of the Apache license, | | that is bundled with this package in the file LICENSE, and is | | available through the world-wide-web at the following url: | | http://www.apache.org/licenses/LICENSE-2.0.html | | If you did not receive a copy of the Apache2.0 license and are unable| | to obtain it through the world-wide-web, please send a note to | | license@swoole.com so we can mail you a copy immediately. | +----------------------------------------------------------------------+ | Author: Tianfeng Han <rango@swoole.com> | +----------------------------------------------------------------------+ */ #pragma once #include "php_swoole_cxx.h" #include "swoole_client.h" bool php_swoole_client_check_setting(swoole::network::Client *cli, zval *zset); #ifdef SW_USE_OPENSSL void php_swoole_client_check_ssl_setting(swoole::network::Client *cli, zval *zset); #endif

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/* $NetBSD: extract.c,v 1.3 2014/02/19 19:31:08 drochner Exp $ */ #include <stdlib.h> #include <unistd.h> #include <fcntl.h> #include <stdio.h> #include <string.h> #include <errno.h> #include <err.h> #include <x86/cpu_ucode.h> FILE *in; int lc; static int getbin(void *buf, int len) { char lbuf[100], *l; uint32_t b[4]; int n; while ((l = fgets(lbuf, sizeof(lbuf), in))) { lc++; if (l[0] == '/') continue; n = sscanf(l, "0x%x, 0x%x, 0x%x, 0x%x,", &b[0], &b[1], &b[2], &b[3]); if (n != 4) errx(3, "can't digest line %d", lc); if (len < 16) errx(3, "wrong size assumption"); memcpy(buf, b, 16); len -= 16; if (len == 0) return 0; buf = (char *)buf + 16; } return (-1); } static int isnewer(const char *fn, int rev) { int fd; struct intel1_ucode_header uh; fd = open(fn, O_RDONLY, 0); if (fd < 0) err(2, "open %s", fn); read(fd, &uh, sizeof(uh)); close(fd); return (uh.uh_rev > rev); } static int link_unless_newer_exists(const char *name, const char *alias, int rev) { again: if (link(name, alias) == 0) { printf("link %s->%s\n", alias, name); return 1; } if (errno != EEXIST) err(2, "link %s->%s", alias, name); if (isnewer(alias, rev)) return 0; printf("replacing %s\n", alias); if (unlink(alias)) err(2, "unlink %s", alias); goto again; } static void writeout(struct intel1_ucode_header *uh, int len, struct intel1_ucode_ext_table *eh) { char name[18], alias[11]; int fd, used, i, j; struct intel1_ucode_proc_signature *eps; sprintf(name, "%08x.%08x", uh->uh_signature, uh->uh_rev); fd = open(name, O_WRONLY|O_CREAT|O_TRUNC|O_EXCL, 0644); if (fd < 0) err(2, "open %s", name); write(fd, uh, len); close(fd); used = 0; for (i = 0; i < 8; i++) { if (!(uh->uh_proc_flags & (1 << i))) continue; sprintf(alias, "%08x-%d", uh->uh_signature, i); used += link_unless_newer_exists(name, alias, uh->uh_rev); } if (eh) { /* extension headers are unused in rev. 20140122 */ for (j = 0; j < eh->uet_count; j++) { eps = &eh->uet_proc_sig[j]; for (i = 0; i < 8; i++) { if (!(eps->ups_proc_flags & (1 << i))) continue; sprintf(alias, "%08x-%d", eps->ups_signature, i); used += link_unless_newer_exists(name, alias, uh->uh_rev); } } } unlink(name); printf("%s: %d links\n", name, used); } int main(int argc, char **argv) { struct intel1_ucode_header uh; int datasize, totalsize; void *theupdate; struct intel1_ucode_ext_table *eh; if (argc < 2) errx(1, "need filename"); in = fopen(argv[1], "r"); if (!in) err(2, "could not open \"%s\"", argv[1]); for (;;) { if (getbin(&uh, sizeof(uh)) < 0) break; if (uh.uh_header_ver != 1) errx(3, "wrong file format, last line %d", lc); if (uh.uh_data_size) datasize = uh.uh_data_size; else datasize = 2000; if (uh.uh_total_size) totalsize = uh.uh_total_size; else totalsize = datasize + 48; theupdate = malloc(totalsize); memcpy(theupdate, &uh, 48); if (getbin((char *)theupdate + 48, totalsize - 48) < 0) errx(3, "data format"); if (totalsize != datasize + 48) eh = (void *)((char *)theupdate + 48 + datasize); else eh = NULL; writeout(theupdate, totalsize, eh); free(theupdate); } fclose(in); exit(0); }

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cv.h

#ifndef _CV_H_ #define _CV_H_ typedef struct CvCapture CvCapture; typedef struct CvMemStorage CvMemStorage; typedef struct CvHaarClassifierCascade CvHaarClassifierCascade; #endif

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struct dstTable_ { unsigned char startDay[15]; unsigned char endDay[15]; unsigned char startMonth; unsigned char endMonth; unsigned char diffMonth; char resv; int dstBias; }; typedef struct dstTable_ dstTable; // table mod by Eko, 07.okt.2008 const dstTable dstEntry[] = { // dst #0: nothing to do {{}, {}, 0, 0, 0, 0, 0}, // dst #1: 3 last sun - 10 last sun, but time diff=0 {{30, 29, 28, 27, 25, 31, 30, 29, 27, 26, 25, 31, 29, 28, 27}, {26, 25, 31, 30, 28, 27, 26, 25, 30, 29, 28, 27, 25, 31, 30}, 3, 10, 0, 0, 0}, // dst #2: US and Canada old, from 2007 use #5 {{6, 5, 4, 3, 1, 7, 6, 5, 3, 2, 1, 7, 5, 4, 3}, {26, 25, 31, 30, 28, 27, 26, 25, 30, 29, 28, 27, 25, 31, 30}, 4, 10, 0, 0, 3600}, // dst #3: European Union & Greenland [1:ooam, last Sunday in March ~ // 1:00am, last Sunday in October] {{30, 29, 28, 27, 25, 31, 30, 29, 27, 26, 25, 31, 29, 28, 27}, {26, 25, 31, 30, 28, 27, 26, 25, 30, 29, 28, 27, 25, 31, 30}, 3, 10, 0, 0, 3600}, // dst #4: Australia [2:00am, last Sunday in October ~ 3:00am, last // Sunday in March] {{26, 25, 31, 30, 28, 27, 26, 25, 30, 29, 28, 27, 25, 31, 30}, {30, 29, 28, 27, 25, 31, 30, 29, 27, 26, 25, 31, 29, 28, 27}, 10, 3, 1, 0, 3600}, // dst #5: US and Canada [from 2007, 2:00am, 2nd Sunday in March ~ // 2:00am, 1st Sunday in November] {{9, 8, 14, 13, 11, 10, 9, 8, 13, 12, 11, 10, 8, 14, 13}, {2, 1, 7, 6, 4, 3, 2, 1, 6, 5, 4, 3, 1, 7, 6}, 3, 11, 0, 0, 3600}, // dst #6: New Zealand [2:00am, 1st Sunday in October ~ 2:00am, 3rd // Sunday in March] {{5, 4, 3, 2, 7, 6, 5, 4, 2, 1, 7, 6, 4, 3, 2}, {16, 15, 21, 20, 18, 17, 16, 15, 20, 19, 18, 17, 15, 21, 20}, 10, 3, 1, 0, 3600}, // dst #7: New Zealand [2:00am, last Sunday in September ~ 2:00am, 1st // Sunday in April] {{28, 27, 26, 25, 30, 29, 28, 27, 25, 24, 30, 29, 27, 26, 25}, {6, 5, 4, 3, 1, 7, 6, 5, 3, 2, 1, 7, 5, 4, 3}, 9, 4, 1, 0, 3600}, // dst #8: Argentina [3rd Sunday in October ~ 2:00am, 3rd // Sunday in March] {{19, 18, 17, 16, 21, 20, 19, 18, 16, 15, 21, 20, 18, 17, 16}, {16, 15, 21, 20, 18, 17, 16, 15, 20, 19, 18, 17, 15, 21, 20}, 10, 3, 1, 0, 3600}, // dst #9: Australia [first Sunday in October ~ 2:00am, first // Sunday in April] {{5, 4, 3, 2, 7, 6, 5, 4, 2, 1, 7, 6, 4, 3, 2}, {6, 5, 4, 3, 1, 7, 6, 5, 3, 2, 1, 7, 5, 4, 3}, 10, 4, 1, 0, 3600}, //08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 <-- year // dst #10: Brazil + some LA countries [3rd Sunday in October ~ 2:00am, 3rd // Sunday in February] {{19, 18, 17, 16, 21, 20, 19, 18, 16, 15, 21, 20, 18, 17, 16}, {17, 15, 21, 20, 19, 17, 16, 15, 21, 19, 18, 17, 16, 21, 20}, 10, 2, 1, 0, 3600}, //08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 <-- year };

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/src/mat/tests/ex71.c

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ex71.c

static char help[] = "Passes a sparse matrix to MATLAB.\n\n"; #include <petscmat.h> int main(int argc, char **args) { PetscInt m = 4, n = 5, i, j, II, J; PetscScalar one = 1.0, v; Vec x; Mat A; PetscFunctionBeginUser; PetscCall(PetscInitialize(&argc, &args, (char *)0, help)); PetscCall(PetscOptionsGetInt(NULL, NULL, "-m", &m, NULL)); PetscCall(PetscOptionsGetInt(NULL, NULL, "-n", &n, NULL)); PetscCall(MatCreate(PETSC_COMM_WORLD, &A)); PetscCall(MatSetSizes(A, PETSC_DECIDE, PETSC_DECIDE, m * n, m * n)); PetscCall(MatSetFromOptions(A)); PetscCall(MatSetUp(A)); for (i = 0; i < m; i++) { for (j = 0; j < n; j++) { v = -1.0; II = j + n * i; if (i > 0) { J = II - n; PetscCall(MatSetValues(A, 1, &II, 1, &J, &v, INSERT_VALUES)); } if (i < m - 1) { J = II + n; PetscCall(MatSetValues(A, 1, &II, 1, &J, &v, INSERT_VALUES)); } if (j > 0) { J = II - 1; PetscCall(MatSetValues(A, 1, &II, 1, &J, &v, INSERT_VALUES)); } if (j < n - 1) { J = II + 1; PetscCall(MatSetValues(A, 1, &II, 1, &J, &v, INSERT_VALUES)); } v = 4.0; PetscCall(MatSetValues(A, 1, &II, 1, &II, &v, INSERT_VALUES)); } } PetscCall(MatAssemblyBegin(A, MAT_FINAL_ASSEMBLY)); PetscCall(MatAssemblyEnd(A, MAT_FINAL_ASSEMBLY)); #if defined(PETSC_USE_SOCKET_VIEWER) PetscCall(MatView(A, PETSC_VIEWER_SOCKET_WORLD)); #endif PetscCall(VecCreateSeq(PETSC_COMM_SELF, m, &x)); PetscCall(VecSet(x, one)); #if defined(PETSC_USE_SOCKET_VIEWER) PetscCall(VecView(x, PETSC_VIEWER_SOCKET_WORLD)); #endif PetscCall(PetscSleep(30)); PetscCall(VecDestroy(&x)); PetscCall(MatDestroy(&A)); PetscCall(PetscFinalize()); return 0; } /*TEST test: TODO: cannot test with socket viewer TEST*/

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ex-array00.c

/* Include M*LIB header */ #include "m-array.h" #include "m-string.h" #include "m-tuple.h" /* Provide several examples of different types usage with array, with the oplist to use for each case. Each time it creates and initializes an array, fills it with some number, computes its sum, and returns it. This is done for several basic C types: - integers, - floats, - pointers, - structures, - tuples */ /* Generate prototypes and inline functions for basic types. For integer and floats, there is no need to specify an oplist. M_BASIC_OPLIST will be used. For bool, M_BOOL_OPLIST will be used. */ ARRAY_DEF(r_bool, bool) /* Basic usage of the type */ static int test_bool(int n) { r_bool_t array; r_bool_init(array); for(int i = 0; i < n; i++) { r_bool_push_back(array, i & 1); } int s = 0; for(int i = 0; i < n; i++) { s += *r_bool_get(array, i); } r_bool_clear(array); return s; } /* Same with type char */ ARRAY_DEF(r_char, char) static int test_char(int n) { r_char_t array; r_char_init(array); for(int i = 0; i < n; i++) { r_char_push_back(array, i & 255); } int s = 0; for(int i = 0; i < n; i++) { s += *r_char_get(array, i); } r_char_clear(array); return s; } /* Same with type signed int. */ ARRAY_DEF(r_int, signed int) static int test_int(int n) { r_int_t array; r_int_init(array); for(int i = 0; i < n; i++) { r_int_push_back(array, i); } int s = 0; for(int i = 0; i < n; i++) { s += *r_int_get(array, i); } r_int_clear(array); return s; } /* Same with type signed int. But with an explicit oplist. This generates exactly the same code than r_int */ ARRAY_DEF(r_int2, signed int, M_BASIC_OPLIST) static int test_int2(int n) { r_int2_t array; r_int2_init(array); for(int i = 0; i < n; i++) { r_int2_push_back(array, i); } int s = 0; for(int i = 0; i < n; i++) { s += *r_int2_get(array, i); } r_int2_clear(array); return s; } /* Same with type unsigned long long */ ARRAY_DEF(r_ullong, unsigned long long) static int test_ullong(int n) { r_ullong_t array; r_ullong_init(array); for(int i = 0; i < n; i++) { r_ullong_push_back(array, i); } int s = 0; for(int i = 0; i < n; i++) { s += *r_ullong_get(array, i); } r_ullong_clear(array); return s; } /* Same with type float */ ARRAY_DEF(r_float, float) static int test_float(int n) { r_float_t array; r_float_init(array); for(int i = 0; i < n; i++) { r_float_push_back(array, i/4.0); } float s = 0; for(int i = 0; i < n; i++) { s += *r_float_get(array, i); } r_float_clear(array); return s; } /* Same with type double and an explicit oplist*/ ARRAY_DEF(r_double, double, M_BASIC_OPLIST) static int test_double(int n) { r_double_t array; r_double_init(array); for(int i = 0; i < n; i++) { r_double_push_back(array, i/4.0); } float s = 0; for(int i = 0; i < n; i++) { s += *r_double_get(array, i); } r_double_clear(array); return s; } /* Helper function strdup */ static char *my_strdup(const char *p) { size_t s = strlen(p); char *d= malloc(s+1); if(!d) abort(); strcpy(d, p); return d; } /* Same with type const char *, representing a contant C string. We *** need *** an explicit oplist to tell M*LIB to consider the type as a constant C string. The oplist to use is M_CSTR_OPLIST. We could have used M_PTR_OPLIST too, but in this case, we won't get proper string order or string equality. */ ARRAY_DEF(r_cstring, const char *, M_CSTR_OPLIST) static int test_cstring(int n) { r_cstring_t array; r_cstring_init(array); for(int i = 0; i < n; i++) { char buffer[16]; // Create a string from the integer sprintf(buffer, "%d", i); // We need to make an explicit copy of the string // since it is not supported by the basic type. char *p = my_strdup(buffer); // Push the copy in the container. r_cstring_push_back(array, p); } int s = 0; for(int i = 0; i < n; i++) { // Get back the string const char *p = *r_cstring_get(array, i); // Convert it to an integer int j = atoi(p); s += j; } // We also need a special unalloc pass // to free all constant strings we have allocated using my_strdup for(int i = 0; i < n; i++) { const char *p = *r_cstring_get(array, i); free((void*)(uintptr_t)p); } r_cstring_clear(array); return s; } /* Same with type string_t of M*LIB, representing a dynamic string. We don't need explicit oplist to tell M*LIB! The oplist to use is STRING_OPLIST, but it has been registered globaly, so we don't need to explicit give it to array_def! */ ARRAY_DEF(r_string, string_t) static int test_string(int n) { r_string_t array; string_t str; r_string_init(array); string_init (str); for(int i = 0; i < n; i++) { // create a string from an integer string_set_si(str, i); // No need to make a copy in the container! r_string_push_back(array, str); } int s = 0; for(int i = 0; i < n; i++) { // Get back the string and convert it back to an integer int j = atoi(string_get_cstr(*r_string_get(array, i))); s += j; } // No need to explicit free each term of the array string_clear(str); r_string_clear(array); return s; } /* Same with type string_t of M*LIB, representing a variable string and its explicit oplist. As said above, it generates exactly the same code. */ ARRAY_DEF(r_string2, string_t, STRING_OPLIST) /* Same with type 'volatile unsigned int *' The array stores pointers to another integer, allocated somewhere else. We need to tell M*LIB to handle the basic type as pointers without caring for what the value of the pointer is. So here, we **need** to specify the oplist of the type as M_PTR_OPLIST. */ ARRAY_DEF(r_vintptr, volatile unsigned int *, M_PTR_OPLIST) static int test_vintptr(int n) { r_vintptr_t array; // Allocate a secondary table to store the value. unsigned *tab = calloc(n, sizeof(volatile unsigned int)); if (!tab) abort(); r_vintptr_init(array); for(int i = 0; i < n; i++) { tab[i] = i*i - i; // Push the pointer to this integer in the array r_vintptr_push_back(array, &tab[i]); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the integer. // As the basic type of the container is a pointer, // and r_vintptr_get return a pointer to the basic type // we need to dereference its return value to get the pointer value. volatile unsigned *p = *r_vintptr_get(array, i); s += *p; } r_vintptr_clear(array); free(tab); return s; } /* Same with a structure type. We need to tell M*LIB to handle the basic type as POD; So here, we **need** to specify the oplist of the type as M_POD_OPLIST. */ struct rock_me_out { int n; float other; }; ARRAY_DEF(r_rockme, struct rock_me_out, M_POD_OPLIST) static int test_rockme(int n) { r_rockme_t array; r_rockme_init(array); for(int i = 0; i < n; i++) { struct rock_me_out rock; rock.n = i*i - i; rock.other = 0.0f; // Push the struct in the array r_rockme_push_back(array, rock); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the struct struct rock_me_out *p = r_rockme_get(array, i); s += p->n; } r_rockme_clear(array); return s; } /* Same with a structure type defined with [1]: We need to tell M*LIB to handle the basic type as a special array; So here, we **need** to specify the oplist of the type as M_A1_OPLIST. */ typedef struct rock_me_in { int n; float other; } rock_me_in[1]; ARRAY_DEF(r_rockme2, rock_me_in, M_A1_OPLIST) static int test_rockme2(int n) { r_rockme2_t array; r_rockme2_init(array); for(int i = 0; i < n; i++) { rock_me_in rock; rock->n = i*i - i; rock->other = 0.0f; r_rockme2_push_back(array, rock); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the struct. rock_me_in *p = r_rockme2_get(array, i); s += (*p)->n; } r_rockme2_clear(array); return s; } /* Same with a structure type defined with [1] and a global registeration. We need to tell M*LIB to handle the basic type as a special array. To do so, we register the oplist of rock_us_t by defining a macro based on M_OPL_ + type name + () which expands with the oplist of the type. Then we define the array, giving it only the type. M*LIB will look at the global registered oplist of the type, we don't need to give it explictly. Global registeration makes easier code. Registeration should be done when the type is defined. */ #define M_OPL_rock_me_in() M_A1_OPLIST ARRAY_DEF(r_rockme2b, rock_me_in) static int test_rockme2b(int n) { r_rockme2b_t array; r_rockme2b_init(array); for(int i = 0; i < n; i++) { rock_me_in rock; rock->n = i*i - i; rock->other = 0.0f; r_rockme2b_push_back(array, rock); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the struct. rock_me_in *p = r_rockme2b_get(array, i); s += (*p)->n; } r_rockme2b_clear(array); return s; } /* Same with a structure type defined as a tuple. We first define a tuple. No need to specify the oplist as it uses basic C types so M_BASIC_OPLIST is used by default. Then we define the array, giving it the oplist definition of the tuple: the macro TUPLE_OPLIST is used to build it based on the tuple name, and the oplists of the tuple. The main advantage of a tuple over a classic structure is that you get free classic methods of your structure. */ TUPLE_DEF2(rock_you, (n, int), (other, float)) ARRAY_DEF(r_rockme3, rock_you_t, TUPLE_OPLIST(rock_you, M_BASIC_OPLIST, M_BASIC_OPLIST)) static int test_rockme3(int n) { r_rockme3_t array; rock_you_t x; r_rockme3_init(array); rock_you_init(x); for(int i = 0; i < n; i++) { rock_you_set_n(x, i*i - i); r_rockme3_push_back(array, x); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the structure containing the integer. rock_you_t *p = r_rockme3_get(array, i); s += (*p)->n; } r_rockme3_clear(array); rock_you_clear(x); return s; } /* Same with a structure type defined as a tuple using global registeration. We first define a tuple. No need to specify the oplist as it uses basic C types so M_BASIC_OPLIST is used. Then we register the oplist of rock_us_t by defining a macro based on M_OPL_ + type name + () which expands with the oplist of the type. Then we define the array, giving it only the type. M*LIB will look at the global registered oplist of the type, we don't need to give it explictly. Global registeration makes easier code. */ TUPLE_DEF2(rock_us, (n, int), (other, float)) #define M_OPL_rock_us_t() TUPLE_OPLIST(rock_us, M_BASIC_OPLIST, M_BASIC_OPLIST) ARRAY_DEF(r_rockme4, rock_us_t) static int test_rockme4(int n) { r_rockme4_t array; rock_us_t x; r_rockme4_init(array); rock_us_init(x); for(int i = 0; i < n; i++) { rock_us_set_n(x, i*i - i); r_rockme4_push_back(array, x); } int s = 0; for(int i = 0; i < n; i++) { // Get the pointer to the structure containing the integer. rock_us_t *p = r_rockme4_get(array, i); s += (*p)->n; } r_rockme4_clear(array); rock_us_clear(x); return s; } int main (int argc, const char *argv[]) { int n = argc == 1 ? 10 : atoi(argv[1]); int s; s = test_bool(n); printf ("S[bool] = %d\n", s); s = test_char(n); printf ("S[char] = %d\n", s); s = test_int(n); printf ("S[int] = %d\n", s); s = test_int2(n); printf ("S[int2] = %d\n", s); s = test_ullong(n); printf ("S[ullong] = %d\n", s); s = test_float(n); printf ("S[float] = %d\n", s); s = test_double(n); printf ("S[double] = %d\n", s); s = test_cstring(n); printf ("S[cstring] = %d\n", s); s = test_string(n); printf ("S[string] = %d\n", s); s = test_vintptr(n); printf ("S[vintptr] = %d\n", s); s = test_rockme(n); printf ("S[rockme] = %d\n", s); s = test_rockme2(n); printf ("S[rockme2] = %d\n", s); s = test_rockme2b(n); printf ("S[rockme2b] = %d\n", s); s = test_rockme3(n); printf ("S[rockme3] = %d\n", s); s = test_rockme4(n); printf ("S[rockme4] = %d\n", s); exit(0); }

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/* * Copyright (c) 1986 Regents of the University of California. * All rights reserved. The Berkeley software License Agreement * specifies the terms and conditions for redistribution. */ #include <sys/param.h> #include <sys/conf.h> #include <sys/buf.h> #include <sys/time.h> #include <sys/ioctl.h> #include <sys/resource.h> #include <sys/inode.h> #include <sys/proc.h> #include <sys/clist.h> #include <sys/tty.h> #include <sys/systm.h> #include <sys/errno.h> #include <machine/uart.h> #include <sys/gpanel.h> #include <sys/spi.h> #include <sys/gpio.h> #include <sys/swap.h> extern int strcmp(char *s1, char *s2); #ifdef SD_ENABLED # include <machine/sd.h> #endif #ifdef RC_ENABLED # include <machine/sramc.h> #endif #ifdef DR_ENABLED # include <machine/sdramp.h> #endif #ifdef MR_ENABLED # include <machine/mrams.h> #endif #ifdef SR_ENABLED # include <machine/spirams.h> #endif #ifdef UARTUSB_ENABLED # include <machine/usb_uart.h> #endif #ifdef ADC_ENABLED # include <machine/adc.h> #endif #ifdef GLCD_ENABLED # include <sys/glcd.h> #endif #ifdef PWM_ENABLED # include <sys/pwm.h> #endif #ifdef PICGA_ENABLED # include <sys/picga.h> #endif #ifdef PTY_ENABLED # include <sys/pty.h> #endif #ifdef SKEL_ENABLED # include <sys/skel.h> #endif /* * Null routine; placed in insignificant entries * in the bdevsw and cdevsw tables. */ int nulldev() { return 0; } int noopen(dev, flag, mode) dev_t dev; int flag, mode; { return ENXIO; } int norw(dev, uio, flag) dev_t dev; struct uio *uio; int flag; { return 0; } int noioctl(dev, cmd, data, flag) dev_t dev; u_int cmd; caddr_t data; int flag; { return EIO; } /* * root attach routine */ daddr_t nosize(dev) dev_t dev; { return 0; } #define NOBDEV \ noopen, noopen, nostrategy, \ nosize, noioctl, /* * The RetroDisks require the same master number as the disk entry in the * rdisk.c file. A bit of a bind, but it means that the RetroDisk * devices must be numbered from master 0 upwards. */ const struct bdevsw bdevsw[] = { { /* 0 - sd */ #ifdef SD_ENABLED sdopen, sdclose, sdstrategy, sdsize, sdioctl, #else NOBDEV #endif }, { /* 1 - sramc */ #ifdef RC_ENABLED sramc_open, sramc_close, sramc_strategy, sramc_size, sramc_ioctl, #else NOBDEV #endif }, { /* 2 - sdramp */ #ifdef DR_ENABLED sdramp_open, sdramp_close, sdramp_strategy, sdramp_size, sdramp_ioctl, #else NOBDEV #endif }, { /* 3 - mrams */ #ifdef MR_ENABLED mrams_open, mrams_close, mrams_strategy, mrams_size, mrams_ioctl, #else NOBDEV #endif }, { /* 4 - swap */ swopen, swclose, swstrategy, swsize, swcioctl, }, { /* 5 - spirams */ #ifdef SR_ENABLED spirams_open, spirams_close, spirams_strategy, spirams_size, spirams_ioctl, #else NOBDEV #endif }, { 0 }, }; const int nblkdev = sizeof(bdevsw) / sizeof(bdevsw[0]) - 1; #define NOCDEV \ noopen, noopen, norw, norw, \ noioctl, nulldev, 0, seltrue, \ nostrategy, 0, 0, const struct cdevsw cdevsw[] = { /* * Static drivers - every system has these: */ { /* 0 - console */ cnopen, cnclose, cnread, cnwrite, cnioctl, nulldev, cnttys, cnselect, nostrategy, 0, 0, }, { /* 1 - mem, kmem, null, zero */ #if MEM_MAJOR != 1 # error Wrong MEM_MAJOR value! #endif nulldev, nulldev, mmrw, mmrw, noioctl, nulldev, 0, seltrue, nostrategy, 0, 0, }, { /* 2 - tty */ syopen, nulldev, syread, sywrite, syioctl, nulldev, 0, syselect, nostrategy, 0, 0, }, { /* 3 - fd */ fdopen, nulldev, norw, norw, noioctl, nulldev, 0, seltrue, nostrategy, 0, 0, }, { /* 4 - temp (temporary allocation in swap space) */ swcopen, swcclose, swcread, swcwrite, swcioctl, nulldev, 0, seltrue, nostrategy, 0, 0, }, /* * Optional drivers from here on: */ { /* 5 - log */ #ifdef LOG_ENABLED logopen, logclose, logread, norw, logioctl, nulldev, 0, logselect, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 6 - tty uart */ #if UART_MAJOR != 6 # error Wrong UART_MAJOR value! #endif #if defined(UART1_ENABLED) || defined(UART2_ENABLED) || \ defined(UART3_ENABLED) || defined(UART4_ENABLED) || \ defined(UART5_ENABLED) || defined(UART6_ENABLED) uartopen, uartclose, uartread, uartwrite, uartioctl, nulldev, uartttys, uartselect, nostrategy, uartgetc, uartputc, #else NOCDEV #endif }, { /* 7 - tty usb */ #if UARTUSB_MAJOR != 7 # error Wrong UARTUSB_MAJOR value! #endif #ifdef UARTUSB_ENABLED usbopen, usbclose, usbread, usbwrite, usbioctl, nulldev, usbttys, usbselect, nostrategy, usbgetc, usbputc, #else NOCDEV #endif }, { /* 8, 9 - pty */ #ifdef PTY_ENABLED ptsopen, ptsclose, ptsread, ptswrite, ptyioctl, nulldev, pt_tty, ptcselect, nostrategy, 0, 0, }, { ptcopen, ptcclose, ptcread, ptcwrite, ptyioctl, nulldev, pt_tty, ptcselect, nostrategy, 0, 0, #else NOCDEV }, { NOCDEV #endif }, { /* 10 - gpio */ #if defined(GPIO_ENABLED) || defined(GPIO1_ENABLED) || \ defined(GPIO2_ENABLED) || defined(GPIO3_ENABLED) || \ defined(GPIO4_ENABLED) || defined(GPIO5_ENABLED) || \ defined(GPIO6_ENABLED) gpioopen, gpioclose, gpioread, gpiowrite, gpioioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 11 - adc */ #ifdef ADC_ENABLED adc_open, adc_close, adc_read, adc_write, adc_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 12 - spi */ #if defined(SPI1_ENABLED) || defined(SPI2_ENABLED) || \ defined(SPI3_ENABLED) || defined(SPI4_ENABLED) spidev_open, spidev_close, spidev_read, spidev_write, spidev_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 13 - glcd */ #ifdef GLCD_ENABLED glcd_open, glcd_close, glcd_read, glcd_write, glcd_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 14 - pwm */ #ifdef PWM_ENABLED pwm_open, pwm_close, pwm_read, pwm_write, pwm_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 15 - picga */ // Ignore this for now - it's WIP. #ifdef PICGA_ENABLED picga_open, picga_close, picga_read, picga_write, picga_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 16 - hxtft or . * All LCD display drivers share the same device. * Only one such driver can be present in the kernel. */ #if GPANEL_MAJOR != 16 # error Wrong GPANEL_MAJOR value! #endif #if defined(HXTFT_ENABLED) || defined(GPANEL_ENABLED) || \ defined(SGPANEL_ENABLED) gpanel_open, gpanel_close, gpanel_read, gpanel_write, gpanel_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, { /* 17 - skel */ #ifdef SKEL_ENABLED skeldev_open, skeldev_close, skeldev_read, skeldev_write, skeldev_ioctl, nulldev, 0, seltrue, nostrategy, 0, 0, #else NOCDEV #endif }, /* * End the list with a blank entry */ { 0 }, }; const int nchrdev = sizeof(cdevsw) / sizeof(cdevsw[0]) - 1; /* * Routine that identifies /dev/mem and /dev/kmem. * * A minimal stub routine can always return 0. */ int iskmemdev(dev) register dev_t dev; { if (major(dev) == 1 && (minor(dev) == 0 || minor(dev) == 1)) return 1; return 0; } /* * Routine to determine if a device is a disk. * * A minimal stub routine can always return 0. */ int isdisk(dev, type) dev_t dev; register int type; { if (type != IFBLK) return 0; switch (major(dev)) { case 0: /* rd0 */ case 1: /* rd1 */ case 2: /* rd2 */ case 3: /* rd3 */ case 4: /* sw */ return 1; default: return 0; } /* NOTREACHED */ } /* * Routine to convert from character to block device number. * A minimal stub routine can always return NODEV. */ int chrtoblk(dev_t dev) { return NODEV; }

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#ifndef NULLC_INTERNAL_INCLUDED #define NULLC_INTERNAL_INCLUDED #include "nullcdef.h" #include "Compiler.h" /************************************************************************/ /* Internal functions */ CompilerContext* nullcGetCompilerContext(); #define NULLC_BUILTIN_SQRT 1 nullres nullcBindModuleFunctionBuiltin(const char* module, const char* name, int index, unsigned builtinIndex); #define NULLC_ATTRIBUTE_NO_MEMORY_WRITE 0 nullres nullcSetModuleFunctionAttribute(const char* module, const char* name, int index, unsigned attribute, unsigned value); void nullcVisitParseTreeNodes(SynBase *syntax, void *context, void(*accept)(void *context, SynBase *child)); void nullcVisitExpressionTreeNodes(ExprBase *expression, void *context, void(*accept)(void *context, ExprBase *child)); #endif

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// The Computer Language Benchmarks Game // http://benchmarksgame.alioth.debian.org/ // // Contributed by Kevin Miller // // ver 2: added a couple of optimizations // - Reduced number of times a vector of 8 was checked to see if // they had all escaped, similar to Dominic Letz's C #5 entry. // - Processed 64 pixels at a time if width was a multiple of 64, // thereby reducing writes to the bitmap. // // compile with following gcc flags // -pipe -Wall -O3 -ffast-math -fno-finite-math-only -march=native -mfpmath=sse -msse3 -fopenmp #include <stdlib.h> #include <stdio.h> #include <unistd.h> #include <emmintrin.h> long numDigits(long n) { long len = 0; while(n) { n=n/10; len++; } return len; } inline long vec_nle(__m128d *v, double f) { return (v[0][0] <= f || v[0][1] <= f || v[1][0] <= f || v[1][1] <= f || v[2][0] <= f || v[2][1] <= f || v[3][0] <= f || v[3][1] <= f) ? 0 : -1; } inline void clrPixels_nle(__m128d *v, double f, unsigned long * pix8) { if(!(v[0][0] <= f)) *pix8 &= 0x7f; if(!(v[0][1] <= f)) *pix8 &= 0xbf; if(!(v[1][0] <= f)) *pix8 &= 0xdf; if(!(v[1][1] <= f)) *pix8 &= 0xef; if(!(v[2][0] <= f)) *pix8 &= 0xf7; if(!(v[2][1] <= f)) *pix8 &= 0xfb; if(!(v[3][0] <= f)) *pix8 &= 0xfd; if(!(v[3][1] <= f)) *pix8 &= 0xfe; } inline void calcSum(__m128d *r, __m128d *i, __m128d *sum, __m128d *init_r, __m128d init_i) { for(long pair=0; pair<4; pair++) { __m128d r2 = r[pair] * r[pair]; __m128d i2 = i[pair] * i[pair]; __m128d ri = r[pair] * i[pair]; sum[pair] = r2 + i2; r[pair]=r2 - i2 + init_r[pair]; i[pair]=ri + ri + init_i; } } inline unsigned long mand8(__m128d *init_r, __m128d init_i) { __m128d r[4], i[4], sum[4]; for(long pair=0; pair<4; pair++) { r[pair]=init_r[pair]; i[pair]=init_i; } unsigned long pix8 = 0xff; for (long j = 0; j < 6; j++) { for(long k=0; k<8; k++) calcSum(r, i, sum, init_r, init_i); if (vec_nle(sum, 4.0)) { pix8 = 0x00; break; } } if (pix8) { calcSum(r, i, sum, init_r, init_i); calcSum(r, i, sum, init_r, init_i); clrPixels_nle(sum, 4.0, &pix8); } return pix8; } unsigned long mand64(__m128d *init_r, __m128d init_i) { unsigned long pix64 = 0; for(long byte=0; byte<8; byte++) { unsigned long pix8 = mand8(init_r, init_i); pix64 = (pix64 >> 8) | (pix8 << 56); init_r += 4; } return pix64; } int main(int argc, char ** argv) { // get width/height from arguments long wid_ht = 16000; if (argc >= 2) { wid_ht = atoi(argv[1]); } wid_ht = (wid_ht+7) & ~7; // allocate memory for header and pixels long headerLength = numDigits(wid_ht)*2+5; long pad = ((headerLength + 7) & ~7) - headerLength; // pad aligns pixels on 8 long dataLength = headerLength + wid_ht*(wid_ht>>3); unsigned char * const buffer = malloc(pad + dataLength); unsigned char * const header = buffer + pad; unsigned char * const pixels = header + headerLength; // generate the bitmap header sprintf((char *)header, "P4\n%ld %ld\n", wid_ht, wid_ht); // calculate initial values, store in r0, i0 __m128d r0[wid_ht/2]; double i0[wid_ht]; for(long xy=0; xy<wid_ht; xy+=2) { r0[xy>>1] = 2.0 / wid_ht * (__m128d){xy, xy+1} - 1.5; i0[xy] = 2.0 / wid_ht * xy - 1.0; i0[xy+1] = 2.0 / wid_ht * (xy+1) - 1.0; } // generate the bitmap long use8 = wid_ht%64; if (use8) { // process 8 pixels (one byte) at a time #pragma omp parallel for schedule(guided) for(long y=0; y<wid_ht; y++) { __m128d init_i = (__m128d){i0[y], i0[y]}; long rowstart = y*wid_ht/8; for(long x=0; x<wid_ht; x+=8) { pixels[rowstart + x/8] = mand8(r0+x/2, init_i); } } } else { // process 64 pixels (8 bytes) at a time #pragma omp parallel for schedule(guided) for(long y=0; y<wid_ht; y++) { __m128d init_i = (__m128d){i0[y], i0[y]}; long rowstart = y*wid_ht/64; for(long x=0; x<wid_ht; x+=64) { ((unsigned long *)pixels)[rowstart + x/64] = mand64(r0+x/2, init_i); } } } // write the data long ret = ret = write(STDOUT_FILENO, header, dataLength); free(buffer); return 0; }

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test_clGetSupportedImageFormats.c

#include <stdio.h> #include <stdlib.h> #include "poclu.h" #define MAX_DEVICES 2 int main(void) { cl_int err; cl_image_format *img_formats; cl_uint num_entries; cl_context ctx = NULL; cl_device_id dev = NULL; cl_command_queue cq = NULL; err = poclu_get_any_device(&ctx, &dev, &cq); CHECK_OPENCL_ERROR_IN("poclu_get_any_device"); TEST_ASSERT(dev != NULL); cl_bool img_support = 0; err = clGetDeviceInfo(dev, CL_DEVICE_IMAGE_SUPPORT, sizeof(cl_bool), &img_support, 0); CHECK_OPENCL_ERROR_IN ("clGetDeviceInfo"); if (img_support != CL_TRUE) return 77; err = clGetSupportedImageFormats (ctx, 0, CL_MEM_OBJECT_IMAGE2D, 0, NULL, &num_entries); CHECK_OPENCL_ERROR_IN("clGetSupportedImageFormats"); if (num_entries == 0) return EXIT_SUCCESS; img_formats = (cl_image_format*)malloc (sizeof(cl_image_format)*num_entries); err = clGetSupportedImageFormats (ctx, 0, CL_MEM_OBJECT_IMAGE2D, num_entries, img_formats, NULL); CHECK_OPENCL_ERROR_IN("clGetSupportedImageFormats"); TEST_ASSERT(num_entries != 0); CHECK_CL_ERROR (clReleaseCommandQueue (cq)); CHECK_CL_ERROR (clReleaseContext (ctx)); free (img_formats); CHECK_CL_ERROR (clUnloadCompiler ()); printf ("OK\n"); return EXIT_SUCCESS; }

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/* * Copyright 2018 Scott Vokes * * See LICENCE for the full copyright terms. */ #ifndef RE_INTERNAL_PRINT_H #define RE_INTERNAL_PRINT_H #include <stdio.h> struct ast; struct fsm_options; typedef void (ast_print)(FILE *f, const struct fsm_options *opt, enum re_flags re_flags, const struct ast *ast); ast_print ast_print_dot; ast_print ast_print_abnf; ast_print ast_print_pcre; ast_print ast_print_tree; #endif

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/* Adventure Kid Waveforms (AKWF) converted for use with Teensy Audio Library * * Adventure Kid Waveforms(AKWF) Open waveforms library * https://www.adventurekid.se/akrt/waveforms/adventure-kid-waveforms/ * * This code is in the public domain, CC0 1.0 Universal (CC0 1.0) * https://creativecommons.org/publicdomain/zero/1.0/ * * Converted by Brad Roy, https://github.com/prosper00 */ /* AKWF_sinharm_0015 256 samples +-----------------------------------------------------------------------------------------------------------------+ | *** ***** | | ** **** | | ** *** | | ** *** | | ** *** | |** ** ********** | |* ** ***** *** | | *** *************** *** | | *** ***** ** *| | ********** *** * | | *** ** | | *** ** | | *** *** | | **** ** | | ***** *** | +-----------------------------------------------------------------------------------------------------------------+ */ const uint16_t AKWF_sinharm_0015 [] = { 33542, 35682, 37625, 39644, 41568, 43494, 45346, 47158, 48899, 50573, 52172, 53687, 55124, 56461, 57718, 58868, 59933, 60889, 61762, 62525, 63207, 63782, 64279, 64680, 65005, 65243, 65413, 65506, 65535, 65505, 65419, 65279, 65094, 64865, 64599, 64300, 63970, 63613, 63230, 62829, 62404, 61966, 61507, 61034, 60545, 60037, 59515, 58974, 58414, 57836, 57235, 56612, 55963, 55290, 54588, 53858, 53096, 52304, 51481, 50624, 49737, 48817, 47867, 46889, 45882, 44850, 43798, 42726, 41640, 40543, 39439, 38336, 37235, 36144, 35069, 34013, 32984, 31989, 31028, 30112, 29244, 28427, 27668, 26970, 26336, 25770, 25274, 24848, 24494, 24215, 24007, 23870, 23805, 23805, 23872, 23998, 24184, 24423, 24708, 25037, 25402, 25799, 26221, 26663, 27119, 27582, 28047, 28510, 28962, 29402, 29825, 30225, 30600, 30946, 31263, 31548, 31802, 32022, 32211, 32367, 32494, 32592, 32665, 32716, 32748, 32764, 32771, 32770, 32767, 32765, 32770, 32784, 32814, 32863, 32931, 33026, 33148, 33300, 33484, 33699, 33947, 34229, 34541, 34884, 35254, 35652, 36071, 36509, 36959, 37420, 37885, 38349, 38806, 39251, 39677, 40077, 40448, 40783, 41076, 41320, 41513, 41649, 41724, 41736, 41680, 41553, 41356, 41087, 40745, 40330, 39844, 39287, 38663, 37974, 37224, 36415, 35555, 34644, 33690, 32700, 31676, 30623, 29551, 28461, 27363, 26259, 25155, 24056, 22969, 21894, 20839, 19804, 18795, 17811, 16856, 15932, 15040, 14179, 13350, 12554, 11787, 11053, 10347, 9670, 9017, 8391, 7786, 7205, 6643, 6100, 5574, 5066, 4573, 4096, 3636, 3194, 2768, 2363, 1978, 1617, 1283, 978, 708, 473, 282, 134, 41, 0, 23, 104, 264, 490, 804, 1192, 1676, 2239, 2905, 3656, 4513, 5457, 6506, 7644, 8884, 10212, 11630, 13140, 14720, 16392, 18115, 19926, 21761, 23690, 25599, 27625, 29551, 31700, };

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bigalloc.h

/* -*- Mode: C; tab-width: 4; c-basic-offset: 4; indent-tabs-mode: nil -*- */ /* * Copyright 2014-2020 Couchbase, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef RDB_BIGALLOC #define RDB_BIGALLOC #include "list.h" #include <stdio.h> #ifdef __cplusplus extern "C" { #endif /** * Big block allocator. This allocator will allocate large chunks of memory with * the assumption that will typically not be wasted too quickly. It also keeps * track of an allocation history, so that it can adjust to the current * "climate". * * This header file exists for internal use. To create an allocator instance, * refer to rdb_bigalloc_new() in rope.h */ typedef struct { rdb_ALLOCATOR base; lcb_clist_t bufs; /* list of pooled segments */ unsigned refcount; unsigned min_blk_alloc; /* minimum alloc size */ unsigned max_blk_alloc; /* maximum alloc size (bigger than this is not pooled) */ unsigned max_blk_count; /* maximum number of blocks to pool */ unsigned n_requests; /* number of requests. Reset every RECHECK_RATE */ unsigned n_toobig; /* number of requests > max_blk_alloc */ unsigned n_toosmall; /* number of requests < min_blk_alloc */ /** counters updated at the end only */ unsigned total_malloc; unsigned total_requests; unsigned total_toobig; unsigned total_toosmall; } rdb_BIGALLOC; #define RDB_BIGALLOC_ALLOCSZ_MAX 65536 #define RDB_BIGALLOC_ALLOCSZ_MIN 256 #define RDB_BIGALLOC_BLKCNT_MAX 8 /** Readjust thresholds every <n> requests. <n> is defined here */ #define RDB_BIGALLOC_RECHECK_RATE 15 /** * Dumps a textual representation of the specified allocator to a FILE * @param alloc * @param fp */ void rdb_bigalloc_dump(rdb_BIGALLOC *alloc, FILE *fp); #ifdef __cplusplus } #endif #endif

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UnitTestConductionSolutionUpdate.C

// Copyright 2017 National Technology & Engineering Solutions of Sandia, LLC // (NTESS), National Renewable Energy Laboratory, University of Texas Austin, // Northwest Research Associates. Under the terms of Contract DE-NA0003525 // with NTESS, the U.S. Government retains certain rights in this software. // // This software is released under the BSD 3-clause license. See LICENSE file // for more details. // #include "StkConductionFixture.h" #include "Teuchos_RCP.hpp" #include "matrix_free/ConductionFields.h" #include "matrix_free/ConductionSolutionUpdate.h" #include "matrix_free/MatrixFreeSolver.h" #include "matrix_free/StkSimdConnectivityMap.h" #include "matrix_free/StkToTpetraMap.h" #include "gtest/gtest.h" #include "KokkosInterface.h" #include "Teuchos_ParameterList.hpp" #include "Tpetra_Export.hpp" #include "Tpetra_Map.hpp" #include "Tpetra_MultiVector.hpp" #include "stk_mesh/base/Bucket.hpp" #include "stk_mesh/base/BulkData.hpp" #include "stk_mesh/base/CoordinateSystems.hpp" #include "stk_mesh/base/Entity.hpp" #include "stk_mesh/base/Field.hpp" #include "stk_mesh/base/FieldBase.hpp" #include "stk_mesh/base/FieldState.hpp" #include "stk_mesh/base/FieldTraits.hpp" #include "stk_mesh/base/GetNgpField.hpp" #include "stk_mesh/base/MetaData.hpp" #include "stk_mesh/base/Ngp.hpp" #include "stk_mesh/base/NgpField.hpp" #include "stk_mesh/base/NgpFieldParallel.hpp" #include "stk_mesh/base/NgpForEachEntity.hpp" #include "stk_mesh/base/Selector.hpp" #include "stk_mesh/base/Types.hpp" #include "stk_mesh/base/GetNgpMesh.hpp" #include "stk_topology/topology.hpp" #include <math.h> #include <memory> #include <vector> #include <type_traits> namespace sierra { namespace nalu { namespace matrix_free { namespace test_solution_update { static constexpr Kokkos::Array<double, 3> gammas = {{0, 0, 0}}; } class ConductionSolutionUpdateFixture : public ::ConductionFixture { protected: ConductionSolutionUpdateFixture() : ConductionFixture(nx, scale), linsys( stk::mesh::get_updated_ngp_mesh(bulk), meta.universal_part(), gid_field_ngp), exporter( Teuchos::rcpFromRef(linsys.owned_and_shared), Teuchos::rcpFromRef(linsys.owned)), offset_views( stk::mesh::get_updated_ngp_mesh(bulk), linsys.stk_lid_to_tpetra_lid, meta.universal_part()), field_update(Teuchos::ParameterList{}, linsys, exporter, offset_views) { auto& coordField = *meta.get_field<stk::mesh::Field<double, stk::mesh::Cartesian3d>>( stk::topology::NODE_RANK, "coordinates"); for (auto ib : bulk.get_buckets(stk::topology::NODE_RANK, meta.universal_part())) { for (auto node : *ib) { const auto* coordptr = stk::mesh::field_data(coordField, node); *stk::mesh::field_data( q_field.field_of_state(stk::mesh::StateNP1), node) = coordptr[0]; *stk::mesh::field_data( q_field.field_of_state(stk::mesh::StateN), node) = coordptr[0]; *stk::mesh::field_data( q_field.field_of_state(stk::mesh::StateNM1), node) = coordptr[0]; *stk::mesh::field_data(qtmp_field, node) = 0; *stk::mesh::field_data(alpha_field, node) = 1.0; *stk::mesh::field_data(lambda_field, node) = 1.0; } } } StkToTpetraMaps linsys; Tpetra::Export<> exporter; ConductionOffsetViews<order> offset_views; ConductionSolutionUpdate<order> field_update; LinearizedResidualFields<order> coefficient_fields; InteriorResidualFields<order> fields; static constexpr int nx = 32; static constexpr double scale = M_PI; }; TEST_F(ConductionSolutionUpdateFixture, solution_state_solver_construction) { ASSERT_EQ(field_update.solver().num_iterations(), 0); } namespace { void copy_tpetra_solution_vector_to_stk_field( const stk::mesh::NgpMesh& mesh, const stk::mesh::Selector& sel, Kokkos::View<const typename Tpetra::Map<>::local_ordinal_type*> elid, typename Tpetra::MultiVector<>::dual_view_type::t_dev_const_randomread delta_view, stk::mesh::NgpField<double>& field) { const int dim = delta_view.extent_int(1); stk::mesh::for_each_entity_run( mesh, stk::topology::NODE_RANK, sel, KOKKOS_LAMBDA(stk::mesh::FastMeshIndex mi) { const auto ent = mesh.get_entity(stk::topology::NODE_RANK, mi); const auto tpetra_lid = elid(ent.local_offset()); for (int d = 0; d < dim; ++d) { field(mi, d) = delta_view(tpetra_lid, d); } }); field.modify_on_device(); } } // namespace TEST_F(ConductionSolutionUpdateFixture, correct_behavior_for_linear_problem) { const auto conn = stk_connectivity_map<order>(mesh, meta.universal_part()); fields = gather_required_conduction_fields<order>(meta, conn); coefficient_fields.volume_metric = fields.volume_metric; coefficient_fields.diffusion_metric = fields.diffusion_metric; auto delta = stk::mesh::get_updated_ngp_field<double>(qtmp_field); field_update.compute_residual( test_solution_update::gammas, fields, BCDirichletFields{}, BCFluxFields<order>{}); auto& delta_mv = field_update.compute_delta( test_solution_update::gammas[0], coefficient_fields); copy_tpetra_solution_vector_to_stk_field( stk::mesh::get_updated_ngp_mesh(bulk), meta.universal_part(), linsys.stk_lid_to_tpetra_lid, delta_mv.getLocalViewDevice(Tpetra::Access::ReadOnly), delta); if (mesh.get_bulk_on_host().parallel_size() > 1) { stk::mesh::communicate_field_data<double>( mesh.get_bulk_on_host(), {&delta}); } delta.sync_to_host(); auto& coord_field = *meta.get_field<stk::mesh::Field<double, stk::mesh::Cartesian3d>>( stk::topology::NODE_RANK, "coordinates"); for (auto ib : bulk.get_buckets(stk::topology::NODE_RANK, meta.universal_part())) { for (auto node : *ib) { ASSERT_NEAR( *stk::mesh::field_data(qtmp_field, node), -stk::mesh::field_data(coord_field, node)[0], 1.0e-6); } } } } // namespace matrix_free } // namespace nalu } // namespace sierra

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extern zend_class_entry *stub_types_maybe_ce; ZEPHIR_INIT_CLASS(Stub_Types_MayBe); PHP_METHOD(Stub_Types_MayBe, gc); PHP_METHOD(Stub_Types_MayBe, gcFalse); #if PHP_VERSION_ID >= 80000 ZEND_BEGIN_ARG_WITH_RETURN_TYPE_MASK_EX(arginfo_stub_types_maybe_gc, 0, 1, MAY_BE_LONG|MAY_BE_FALSE) #else ZEND_BEGIN_ARG_WITH_RETURN_TYPE_INFO_EX(arginfo_stub_types_maybe_gc, 0, 1, IS_LONG, 0) #endif ZEND_ARG_TYPE_INFO(0, maxlifetime, IS_LONG, 0) ZEND_END_ARG_INFO() #if PHP_VERSION_ID >= 80000 ZEND_BEGIN_ARG_WITH_RETURN_TYPE_MASK_EX(arginfo_stub_types_maybe_gcfalse, 0, 0, MAY_BE_LONG|MAY_BE_FALSE) #else ZEND_BEGIN_ARG_WITH_RETURN_TYPE_INFO_EX(arginfo_stub_types_maybe_gcfalse, 0, 0, IS_LONG, 0) #endif ZEND_END_ARG_INFO() ZEPHIR_INIT_FUNCS(stub_types_maybe_method_entry) { PHP_ME(Stub_Types_MayBe, gc, arginfo_stub_types_maybe_gc, ZEND_ACC_PUBLIC) PHP_ME(Stub_Types_MayBe, gcFalse, arginfo_stub_types_maybe_gcfalse, ZEND_ACC_PUBLIC) PHP_FE_END };

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/* USB EHCI Host for Teensy 3.6 * Copyright 2017 Paul Stoffregen (paul@pjrc.com) * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * * information about the BlueTooth HCI comes from logic analyzer captures * plus... http://affon.narod.ru/BT/bluetooth_app_c10.pdf */ #ifndef __BT_DEFINES_H_ #define __BT_DEFINES_H_ /************************************************************/ // Define HCI Commands OGF HIgh byte OCF is low byte... // Actually shifted values... /************************************************************/ #define HCI_INQUIRY 0x0401 #define HCI_INQUIRY_CANCEL 0x0402 #define HCI_CREATE_CONNECTION 0x0405 #define HCI_OP_ACCEPT_CONN_REQ 0x0409 #define HCI_OP_REJECT_CONN_REQ 0x040A #define HCI_LINK_KEY_REQUEST_REPLY 0x040B #define HCI_LINK_KEY_NEG_REPLY 0x040C #define HCI_PIN_CODE_REPLY 0x040D #define HCI_AUTH_REQUESTED 0x0411 #define HCI_SET_CONN_ENCRYPTION 0x0413 #define HCI_OP_REMOTE_NAME_REQ 0x0419 #define HCI_OP_REMOTE_NAME_REQ_CANCEL 0x041a #define HCI_OP_READ_REMOTE_FEATURES 0x041b #define HCI_OP_READ_REMOTE_EXTENDED_FEATURE 0x041c #define HCI_OP_READ_REMOTE_VERSION_INFORMATION 0x041D #define HCI_IO_CAPABILITY_REQUEST_REPLY 0x042B #define HCI_USER_CONFIRMATION_REQUEST 0x042C #define HCI_OP_ROLE_DISCOVERY 0x0809 #define HCI_Write_Default_Link_Policy_Settings 0x080f #define HCI_Set_Event_Mask 0x0c01 #define HCI_RESET 0x0c03 #define HCI_SET_EVENT_FILTER 0x0c05 #define HCI_Read_Local_Name 0x0c14 #define HCI_READ_STORED_LINK_KEY 0x0c0d #define HCI_WRITE_STORED_LINK_KEY 0x0c11 #define HCI_DELETE_STORED_LINK_KEY 0x0c12 #define HCI_WRITE_LOCAL_NAME 0x0c13 #define Write_Connection_Accept_Timeout 0x0c16 #define HCI_WRITE_SCAN_ENABLE 0x0c1a #define HCI_Read_Page_Scan_Activity 0x0c1b #define HCI_READ_CLASS_OF_DEVICE 0x0c23 #define HCI_WRITE_CLASS_OF_DEV 0x0C24 #define HCI_Read_Voice_Setting 0x0c25 #define HCI_Read_Number_Of_Supported_IAC 0x0c38 #define HCI_Read_Current_IAC_LAP 0x0c39 #define HCI_WRITE_INQUIRY_MODE 0x0c45 #define HCI_Read_Page_Scan_Type 0x0c46 #define HCI_WRITE_EXTENDED_INQUIRY_RESPONSE 0x0c52 #define HCI_READ_SIMPLE_PAIRING_MODE 0x0c55 #define HCI_WRITE_SIMPLE_PAIRING_MODE 0x0c56 #define HCI_Read_Inquiry_Response_Transmit_Power_Level 0x0c58 #define HCI_WRITE_LE_HOST_SUPPORTED 0x0c6d #define HCI_Read_Local_Supported_Features 0x1003 #define HCI_Read_Local_Extended_Features 0x1004 #define HCI_Read_Buffer_Size 0x1005 #define HCI_Read_BD_ADDR 0x1009 #define HCI_Read_Local_Version_Information 0x1001 #define HCI_Read_Local_Supported_Commands 0x1002 #define HCI_READ_ENCRYPTION_KEY_SIZE 0x1408 #define HCI_LE_SET_EVENT_MASK 0x2001 #define HCI_LE_Read_Buffer_Size 0x2002 #define HCI_LE_Read_Local_supported_Features 0x2003 #define HCI_LE_READ_ADV_TX_POWER 0x2007 #define HCI_LE_SET_ADV_DATA 0x2008 #define HCI_LE_SET_SCAN_RSP_DATA 0x2009 #define HCI_LE_SET_SCAN_PARAMETERS 0x200B #define HCI_LE_SET_SCAN_ENABLE 0x200C #define HCI_LE_READ_WHITE_LIST_SIZE 0x200f #define HCI_LE_CLEAR_WHITE_LIST 0x2010 #define HCI_LE_Supported_States 0x201c /* Bluetooth L2CAP PSM - see http://www.bluetooth.org/Technical/AssignedNumbers/logical_link.htm */ #define SDP_PSM 0x01 // Service Discovery Protocol PSM Value #define HID_CTRL_PSM 0x11 // HID_Control PSM Value #define HID_INTR_PSM 0x13 // HID_Interrupt PSM Value // Used For Connection Response #define PENDING 0x01 #define SUCCESSFUL 0x00 #define SDP_SERVICE_SEARCH_REQUEST 0x02 #define SDP_SERVICE_SEARCH_RESPONSE 0x03 #define SDP_SERVICE_ATTRIBUTE_REQUEST 0x04 #define SDP_SERVICE_ATTRIBUTE_RESPONSE 0x05 #define SDP_SERVICE_SEARCH_ATTRIBUTE_REQUEST 0x06 // See the RFCOMM specs #define SDP_SERVICE_SEARCH_ATTRIBUTE_RESPONSE 0x07 // See the RFCOMM specs /* L2CAP signaling commands */ #define L2CAP_CMD_COMMAND_REJECT 0x01 #define L2CAP_CMD_CONNECTION_REQUEST 0x02 #define L2CAP_CMD_CONNECTION_RESPONSE 0x03 #define L2CAP_CMD_CONFIG_REQUEST 0x04 #define L2CAP_CMD_CONFIG_RESPONSE 0x05 #define L2CAP_CMD_DISCONNECT_REQUEST 0x06 #define L2CAP_CMD_DISCONNECT_RESPONSE 0x07 #define L2CAP_CMD_INFORMATION_REQUEST 0x0A #define L2CAP_CMD_INFORMATION_RESPONSE 0x0B #define HID_THDR_DATA_INPUT 0xa1 // HID stuff #define HID_BOOT_PROTOCOL 0x00 #define HID_RPT_PROTOCOL 0x01 /* HCI Events */ enum {EV_INQUIRY_COMPLETE = 0x01, EV_INQUIRY_RESULT = 0x02, EV_CONNECT_COMPLETE = 0x03, EV_INCOMING_CONNECT = 0x04, EV_DISCONNECT_COMPLETE = 0x05 , EV_AUTHENTICATION_COMPLETE = 0x06, EV_REMOTE_NAME_COMPLETE = 0x07, EV_ENCRYPTION_CHANGE = 0x08, EV_CHANGE_CONNECTION_LINK = 0x09, EV_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE=0x0B, EV_ROLE_CHANGED = 0x12 , EV_NUM_COMPLETE_PKT = 0x13, EV_MODE_CHANGE = 0x14, EV_PIN_CODE_REQUEST = 0x16, EV_LINK_KEY_REQUEST = 0x17, EV_LINK_KEY_NOTIFICATION = 0x18, EV_DATA_BUFFER_OVERFLOW = 0x1A , EV_MAX_SLOTS_CHANGE = 0x1B, EV_READ_REMOTE_VERSION_INFORMATION_COMPLETE = 0x0C, EV_QOS_SETUP_COMPLETE = 0x0D, EV_COMMAND_COMPLETE = 0x0E, EV_COMMAND_STATUS = 0x0F , EV_LOOPBACK_COMMAND = 0x19, EV_PAGE_SCAN_REP_MODE = 0x20, EV_INQUIRY_RESULTS_WITH_RSSI = 0x22,EV_READ_REMOTE_EXTENDED_FEATURES_COMPLETE = 0x23, EV_EXTENDED_INQUIRY_RESULT = 0x2F, EV_IO_CAPABILITY_REQUEST = 0x31, EV_IO_CAPABILITY_RESPONSE = 0x32, EV_USER_CONFIRMATION_REQUEST = 0x33, EV_SIMPLE_PAIRING_COMPLETE = 0x36, EV_RETURN_LINK_KEYS = 0x15, EV_LE_META_EVENT = 0x3E, }; enum { EV_LE_Connection_Complete = 0x01, EV_LE_ADVERTISING_REPORT = 0x02, EV_LE_CONNECTION_UPDATE_COMPLETE = 0x03, EV_LE_READ_REMOTE_FEATURES_COMPLETE = 0x04, EV_LE_LONG_TERM_KEY_REQUEST = 0x05, }; // Note: The states may be moved or splirt up. // different modes enum {PC_RESET = 1, PC_READ_LOCAL_SUPPORTED_COMMANDS, PC_READ_LOCAL_SUPPORTED_FEATURES, PC_SEND_SET_EVENT_MASK, PC_SET_LE_EVENT_MASK, PC_LE_READ_BUFFER_SIZE, PC_WRITE_CLASS_DEVICE, PC_MAYBE_WRITE_SIMPLE_PAIR, PC_MAYBE_READ_SIMPLE_PAIR, PC_READ_BDADDR, PC_READ_LOCAL_VERSION, // Pairing.mode PC_SEND_WRITE_SCAN_PAGE_0 = 0x20, // not sure if we will need a cancel before inquire... PC_SEND_WRITE_INQUIRE_MODE = 0x21, PC_SEND_INQUIRE, PC_INQUIRE_CANCEL = 100, PC_SEND_AUTHENTICATION_REQUEST = 110, PC_AUTHENTICATION_REQUESTED, PC_SEND_READ_REMOTE_EXTENDED_FEATURES = 115, PC_LINK_KEY_NEGATIVE = 120, PC_PIN_CODE_REPLY = 130, PC_CONNECT_AFTER_SDP_DISCONNECT = 140, PC_WRITE_SCAN_PAGE = 200, PC_SEND_REMOTE_SUPPORTED_FEATURES = 300, PC_SEND_REMOTE_EXTENDED_FEATURES = 310, PC_SEND_SET_SIMPLE_PAIRING = 320 }; ////////////// enum {CCON_INT = 0x01, CCON_CONT = 0x02, CCON_SDP = 0x04, CCON_ALL = 0x07}; ////////////// // Setup some states for the TX pipe where we need to chain messages enum {STATE_TX_SEND_CONNECT_INT = 200, STATE_TX_SEND_CONECT_RSP_SUCCESS, STATE_TX_SEND_CONFIG_REQ, STATE_TX_SEND_CONECT_ISR_RSP_SUCCESS, STATE_TX_SEND_CONFIG_ISR_REQ, STATE_TX_SEND_CONECT_SDP_RSP_SUCCESS, STATE_TX_SEND_CONFIG_SDP_REQ }; #endif

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sigsuspend.c

/*-*- mode:c;indent-tabs-mode:nil;c-basic-offset:2;tab-width:8;coding:utf-8 -*-│ │vi: set net ft=c ts=2 sts=2 sw=2 fenc=utf-8 :vi│ ╞══════════════════════════════════════════════════════════════════════════════╡ │ Copyright 2020 Justine Alexandra Roberts Tunney │ │ │ │ Permission to use, copy, modify, and/or distribute this software for │ │ any purpose with or without fee is hereby granted, provided that the │ │ above copyright notice and this permission notice appear in all copies. │ │ │ │ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL │ │ WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED │ │ WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE │ │ AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL │ │ DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR │ │ PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER │ │ TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR │ │ PERFORMANCE OF THIS SOFTWARE. │ ╚─────────────────────────────────────────────────────────────────────────────*/ #include "libc/calls/calls.h" #include "libc/calls/cp.internal.h" #include "libc/calls/internal.h" #include "libc/calls/sig.internal.h" #include "libc/calls/struct/sigset.h" #include "libc/calls/struct/sigset.internal.h" #include "libc/dce.h" #include "libc/intrin/asan.internal.h" #include "libc/intrin/describeflags.internal.h" #include "libc/intrin/strace.internal.h" #include "libc/log/backtrace.internal.h" #include "libc/nt/errors.h" #include "libc/nt/synchronization.h" #include "libc/sysv/consts/sig.h" #include "libc/sysv/errfuns.h" /** * Blocks until SIG ∉ MASK is delivered to thread. * * This temporarily replaces the signal mask until a signal that it * doesn't contain is delivered. * * @param ignore is a bitset of signals to block temporarily, which if * NULL is equivalent to passing an empty signal set * @return -1 w/ EINTR (or possibly EFAULT) * @cancellationpoint * @asyncsignalsafe * @norestart */ int sigsuspend(const sigset_t *ignore) { int rc; const sigset_t *arg; sigset_t save, mask = {0}; STRACE("sigsuspend(%s) → ...", DescribeSigset(0, ignore)); BEGIN_CANCELLATION_POINT; if (IsAsan() && ignore && !__asan_is_valid(ignore, sizeof(*ignore))) { rc = efault(); } else if (IsXnu() || IsOpenbsd()) { // openbsd and xnu only support 32 signals // they use a register calling convention for sigsuspend if (ignore) { arg = (sigset_t *)(uintptr_t)(*(uint32_t *)ignore); } else { arg = 0; } rc = sys_sigsuspend(arg, 8); } else if (IsLinux() || IsFreebsd() || IsNetbsd() || IsWindows()) { if (ignore) { arg = ignore; } else { arg = &mask; } if (!IsWindows()) { rc = sys_sigsuspend(arg, 8); } else { __sig_mask(SIG_SETMASK, arg, &save); #if defined(SYSDEBUG) && _POLLTRACE long ms = 0; long totoms = 0; #endif do { if ((rc = _check_interrupts(0))) { break; } if (SleepEx(__SIG_POLLING_INTERVAL_MS, true) == kNtWaitIoCompletion) { POLLTRACE("IOCP EINTR"); continue; } #if defined(SYSDEBUG) && _POLLTRACE ms += __SIG_POLLING_INTERVAL_MS; if (ms >= __SIG_LOGGING_INTERVAL_MS) { totoms += ms, ms = 0; POLLTRACE("... sigsuspending for %'lums...", totoms); } #endif } while (1); __sig_mask(SIG_SETMASK, &save, 0); } } else { // TODO(jart): sigsuspend metal support rc = enosys(); } END_CANCELLATION_POINT; STRACE("...sigsuspend → %d% m", rc); return rc; }

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/* DO NOT EDIT THIS FILE - it is machine generated */ #include <jni.h> /* Header for class javax_microedition_m3g_Light */ #ifndef _Included_javax_microedition_m3g_Light #define _Included_javax_microedition_m3g_Light #ifdef __cplusplus extern "C" { #endif #undef javax_microedition_m3g_Light_NONE #define javax_microedition_m3g_Light_NONE 144L #undef javax_microedition_m3g_Light_ORIGIN #define javax_microedition_m3g_Light_ORIGIN 145L #undef javax_microedition_m3g_Light_X_AXIS #define javax_microedition_m3g_Light_X_AXIS 146L #undef javax_microedition_m3g_Light_Y_AXIS #define javax_microedition_m3g_Light_Y_AXIS 147L #undef javax_microedition_m3g_Light_Z_AXIS #define javax_microedition_m3g_Light_Z_AXIS 148L #undef javax_microedition_m3g_Light_AMBIENT #define javax_microedition_m3g_Light_AMBIENT 128L #undef javax_microedition_m3g_Light_DIRECTIONAL #define javax_microedition_m3g_Light_DIRECTIONAL 129L #undef javax_microedition_m3g_Light_OMNI #define javax_microedition_m3g_Light_OMNI 130L #undef javax_microedition_m3g_Light_SPOT #define javax_microedition_m3g_Light_SPOT 131L /* * Class: javax_microedition_m3g_Light * Method: _ctor * Signature: (J)J */ JNIEXPORT jlong JNICALL Java_javax_microedition_m3g_Light__1ctor (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setIntensity * Signature: (JF)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setIntensity (JNIEnv *, jclass, jlong, jfloat); /* * Class: javax_microedition_m3g_Light * Method: _getIntensity * Signature: (J)F */ JNIEXPORT jfloat JNICALL Java_javax_microedition_m3g_Light__1getIntensity (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setColor * Signature: (JI)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setColor (JNIEnv *, jclass, jlong, jint); /* * Class: javax_microedition_m3g_Light * Method: _getColor * Signature: (J)I */ JNIEXPORT jint JNICALL Java_javax_microedition_m3g_Light__1getColor (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setMode * Signature: (JI)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setMode (JNIEnv *, jclass, jlong, jint); /* * Class: javax_microedition_m3g_Light * Method: _getMode * Signature: (J)I */ JNIEXPORT jint JNICALL Java_javax_microedition_m3g_Light__1getMode (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setSpotAngle * Signature: (JF)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setSpotAngle (JNIEnv *, jclass, jlong, jfloat); /* * Class: javax_microedition_m3g_Light * Method: _getSpotAngle * Signature: (J)F */ JNIEXPORT jfloat JNICALL Java_javax_microedition_m3g_Light__1getSpotAngle (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setSpotExponent * Signature: (JF)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setSpotExponent (JNIEnv *, jclass, jlong, jfloat); /* * Class: javax_microedition_m3g_Light * Method: _getSpotExponent * Signature: (J)F */ JNIEXPORT jfloat JNICALL Java_javax_microedition_m3g_Light__1getSpotExponent (JNIEnv *, jclass, jlong); /* * Class: javax_microedition_m3g_Light * Method: _setAttenuation * Signature: (JFFF)V */ JNIEXPORT void JNICALL Java_javax_microedition_m3g_Light__1setAttenuation (JNIEnv *, jclass, jlong, jfloat, jfloat, jfloat); /* * Class: javax_microedition_m3g_Light * Method: _getAttenuation * Signature: (JI)F */ JNIEXPORT jfloat JNICALL Java_javax_microedition_m3g_Light__1getAttenuation (JNIEnv *, jclass, jlong, jint); #ifdef __cplusplus } #endif #endif

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#ifndef __DOCUMENT_HEADER__ #define __DOCUMENT_HEADER__ #include "define.h" #include "execute.h" #include "typedef.h" #define init_documentation _n(init_documentation) #define build_documentation _n(build_documentation) void init_documentation(void); void build_documentation(Execute ptr); #endif

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#include "s9_map.h" #define S9M_VERSION 1 #define TS_WIDTH 16 #define FLAG_UPPERLAYER 0x01 #define FLAG_PLANA 0x02 #define FLAG_BYTETILES 0x04 // Helper macro to read a word out of a byte array #define BYTES_TO_WORD(x) (((x)[0] << 8) | ((x)[1])) u8 upperLayer, usePlanA, byteTiles; u8 *mapName; u16 mapWidth, mapHeight; const u8 *mapTiles; void SMAP_loadData(const u8 *data) { if(BYTES_TO_WORD(&data[0]) != S9M_VERSION) { char str[32]; sprintf(str, "Bad map version %hu", BYTES_TO_WORD(&data[0])); SYS_die(str); } u8 flags = data[2]; upperLayer = (flags & FLAG_UPPERLAYER) > 0; usePlanA = (flags & FLAG_PLANA) > 0; byteTiles = (flags & FLAG_BYTETILES) > 0; u8 nameLen = data[3]; // Move past the name data = &data[4 + nameLen]; // Width and height mapWidth = BYTES_TO_WORD(&data[0]); mapHeight = BYTES_TO_WORD(&data[2]); // Set tile pointer to location of tile data mapTiles = &data[4]; } void SMAP_drawArea(u16 x, u16 y, u16 w, u16 h) { u16 t, b, xx, yy; VDPPlane plan = usePlanA ? BG_A : BG_B; for(u8 layer = 0; layer <= upperLayer; layer++) { for(u16 by = y; by < y + h; by++) { for(u16 bx = x; bx < x + w; bx++) { t = (layer ? SMAP_getUpperTile(bx, by) : SMAP_getTile(bx, by)) * 2; b = TILE_USER_INDEX + (t / TS_WIDTH * TS_WIDTH * 2) + (t % TS_WIDTH); xx = (bx * 2) % 64; yy = (by * 2) % 32; VDP_setTileMapXY(plan, TILE_ATTR_FULL(PAL2,0,0,0,b), xx, yy); VDP_setTileMapXY(plan, TILE_ATTR_FULL(PAL2,0,0,0,b+1), xx+1, yy); VDP_setTileMapXY(plan, TILE_ATTR_FULL(PAL2,0,0,0,b+TS_WIDTH), xx, yy+1); VDP_setTileMapXY(plan, TILE_ATTR_FULL(PAL2,0,0,0,b+TS_WIDTH+1), xx+1, yy+1); } } plan = BG_A; } } u16 SMAP_getWidth() { return mapWidth; } u16 SMAP_getHeight() { return mapHeight; } u16 SMAP_getTile(u16 x, u16 y) { u16 index = (x % mapWidth) + (y % mapHeight) * mapWidth; if(byteTiles) { return mapTiles[index]; } else { return BYTES_TO_WORD(&mapTiles[index * 2]); } } u16 SMAP_getUpperTile(u16 x, u16 y) { if(!upperLayer) return 0; u16 index = mapWidth * mapHeight + (x % mapWidth) + (y % mapHeight) * mapWidth; if(byteTiles) { return mapTiles[index]; } else { return BYTES_TO_WORD(&mapTiles[index * 2]); } }

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qsieve.c

/* $NetBSD: qsieve.c,v 1.3 2011/09/04 20:55:43 joerg Exp $ */ /*- * Copyright 1994 Phil Karn <karn@qualcomm.com> * Copyright 1996-1998, 2003 William Allen Simpson <wsimpson@greendragon.com> * Copyright 2000 Niels Provos <provos@citi.umich.edu> * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Sieve candidates for "safe" primes, * suitable for use as Diffie-Hellman moduli; * that is, where q = (p-1)/2 is also prime. * * This is the first of two steps. * This step is memory intensive. * * 1996 May William Allen Simpson * extracted from earlier code by Phil Karn, April 1994. * save large primes list for later processing. * 1998 May William Allen Simpson * parameterized. * 2000 Dec Niels Provos * convert from GMP to openssl BN. * 2003 Jun William Allen Simpson * change outfile definition slightly to match openssh mistake. * move common file i/o to own file for better documentation. * redo memory again. */ #include <stdio.h> #include <stdlib.h> #include <time.h> #include <openssl/bn.h> #include <string.h> #include <err.h> #include "qfile.h" /* define DEBUG_LARGE 1 */ /* define DEBUG_SMALL 1 */ /* * Using virtual memory can cause thrashing. This should be the largest * number that is supported without a large amount of disk activity -- * that would increase the run time from hours to days or weeks! */ #define LARGE_MINIMUM (8UL) /* megabytes */ /* * Do not increase this number beyond the unsigned integer bit size. * Due to a multiple of 4, it must be LESS than 128 (yielding 2**30 bits). */ #define LARGE_MAXIMUM (127UL) /* megabytes */ /* * Constant: assuming 8 bit bytes and 32 bit words */ #define SHIFT_BIT (3) #define SHIFT_BYTE (2) #define SHIFT_WORD (SHIFT_BIT+SHIFT_BYTE) #define SHIFT_MEGABYTE (20) #define SHIFT_MEGAWORD (SHIFT_MEGABYTE-SHIFT_BYTE) /* * Constant: when used with 32-bit integers, the largest sieve prime * has to be less than 2**32. */ #define SMALL_MAXIMUM (0xffffffffUL) /* * Constant: can sieve all primes less than 2**32, as 65537**2 > 2**32-1. */ #define TINY_NUMBER (1UL<<16) /* * Ensure enough bit space for testing 2*q. */ #define TEST_MAXIMUM (1UL<<16) #define TEST_MINIMUM (QSIZE_MINIMUM + 1) /* real TEST_MINIMUM (1UL << (SHIFT_WORD - TEST_POWER)) */ #define TEST_POWER (3) /* 2**n, n < SHIFT_WORD */ /* * bit operations on 32-bit words */ #define BIT_CLEAR(a,n) ((a)[(n)>>SHIFT_WORD] &= ~(1U << ((n) & 31))) #define BIT_SET(a,n) ((a)[(n)>>SHIFT_WORD] |= (1U << ((n) & 31))) #define BIT_TEST(a,n) ((a)[(n)>>SHIFT_WORD] & (1U << ((n) & 31))) /* * sieve relative to the initial value */ static uint32_t *LargeSieve; static uint32_t largewords; static uint32_t largetries; static uint32_t largenumbers; static uint32_t largememory; /* megabytes */ static uint32_t largebits; static BIGNUM *largebase; /* * sieve 2**30 in 2**16 parts */ static uint32_t *SmallSieve; static uint32_t smallbits; static uint32_t smallbase; /* * sieve 2**16 */ static uint32_t *TinySieve; static uint32_t tinybits; __dead static void usage(void); static void sieve_large(uint32_t); /* * Sieve p's and q's with small factors */ static void sieve_large(uint32_t s) { BN_ULONG r; BN_ULONG u; #ifdef DEBUG_SMALL (void)fprintf(stderr, "%lu\n", s); #endif largetries++; /* r = largebase mod s */ r = BN_mod_word(largebase, (BN_ULONG) s); if (r == 0) { /* s divides into largebase exactly */ u = 0; } else { /* largebase+u is first entry divisible by s */ u = s - r; } if (u < largebits * 2) { /* * The sieve omits p's and q's divisible by 2, so ensure that * largebase+u is odd. Then, step through the sieve in * increments of 2*s */ if (u & 0x1) { /* Make largebase+u odd, and u even */ u += s; } /* Mark all multiples of 2*s */ for (u /= 2; u < largebits; u += s) { BIT_SET(LargeSieve, (uint32_t)u); } } /* r = p mod s */ r = (2 * r + 1) % s; if (r == 0) { /* s divides p exactly */ u = 0; } else { /* p+u is first entry divisible by s */ u = s - r; } if (u < largebits * 4) { /* * The sieve omits p's divisible by 4, so ensure that * largebase+u is not. Then, step through the sieve in * increments of 4*s */ while (u & 0x3) { if (SMALL_MAXIMUM - u < s) { return; } u += s; } /* Mark all multiples of 4*s */ for (u /= 4; u < largebits; u += s) { BIT_SET(LargeSieve, (uint32_t)u); } } } /* * list candidates for Sophie-Germaine primes * (where q = (p-1)/2) * to standard output. * The list is checked against small known primes * (less than 2**30). */ int main(int argc, char *argv[]) { BIGNUM *q; uint32_t j; int power; uint32_t r; uint32_t s; uint32_t smallwords = TINY_NUMBER >> 6; uint32_t t; time_t time_start; time_t time_stop; uint32_t tinywords = TINY_NUMBER >> 6; unsigned int i; setprogname(argv[0]); if (argc < 3) { usage(); } /* * Set power to the length in bits of the prime to be generated. * This is changed to 1 less than the desired safe prime moduli p. */ power = (int) strtoul(argv[2], NULL, 10); if ((unsigned)power > TEST_MAXIMUM) { errx(1, "Too many bits: %d > %lu.", power, (unsigned long)TEST_MAXIMUM); } else if (power < TEST_MINIMUM) { errx(1, "Too few bits: %d < %lu.", power, (unsigned long)TEST_MINIMUM); } power--; /* decrement before squaring */ /* * The density of ordinary primes is on the order of 1/bits, so the * density of safe primes should be about (1/bits)**2. Set test range * to something well above bits**2 to be reasonably sure (but not * guaranteed) of catching at least one safe prime. */ largewords = (uint32_t)((unsigned long) (power * power) >> (SHIFT_WORD - TEST_POWER)); /* * Need idea of how much memory is available. We don't have to use all * of it. */ largememory = (uint32_t)strtoul(argv[1], NULL, 10); if (largememory > LARGE_MAXIMUM) { warnx("Limited memory: %u MB; limit %lu MB.", largememory, LARGE_MAXIMUM); largememory = LARGE_MAXIMUM; } if (largewords <= (largememory << SHIFT_MEGAWORD)) { warnx("Increased memory: %u MB; need %u bytes.", largememory, (largewords << SHIFT_BYTE)); largewords = (largememory << SHIFT_MEGAWORD); } else if (largememory > 0) { warnx("Decreased memory: %u MB; want %u bytes.", largememory, (largewords << SHIFT_BYTE)); largewords = (largememory << SHIFT_MEGAWORD); } if ((TinySieve = (uint32_t *) calloc((size_t) tinywords, sizeof(uint32_t))) == NULL) { errx(1, "Insufficient memory for tiny sieve: need %u byts.", tinywords << SHIFT_BYTE); } tinybits = tinywords << SHIFT_WORD; if ((SmallSieve = (uint32_t *) calloc((size_t) smallwords, sizeof(uint32_t))) == NULL) { errx(1, "Insufficient memory for small sieve: need %u bytes.", smallwords << SHIFT_BYTE); } smallbits = smallwords << SHIFT_WORD; /* * dynamically determine available memory */ while ((LargeSieve = (uint32_t *)calloc((size_t)largewords, sizeof(uint32_t))) == NULL) { /* 1/4 MB chunks */ largewords -= (1L << (SHIFT_MEGAWORD - 2)); } largebits = largewords << SHIFT_WORD; largenumbers = largebits * 2; /* even numbers excluded */ /* validation check: count the number of primes tried */ largetries = 0; q = BN_new(); largebase = BN_new(); /* * Generate random starting point for subprime search, or use * specified parameter. */ if (argc < 4) { BN_rand(largebase, power, 1, 1); } else { BIGNUM *a; a = largebase; BN_hex2bn(&a, argv[2]); } /* ensure odd */ if (!BN_is_odd(largebase)) { BN_set_bit(largebase, 0); } time(&time_start); (void)fprintf(stderr, "%.24s Sieve next %u plus %d-bit start point:\n# ", ctime(&time_start), largenumbers, power); BN_print_fp(stderr, largebase); (void)fprintf(stderr, "\n"); /* * TinySieve */ for (i = 0; i < tinybits; i++) { if (BIT_TEST(TinySieve, i)) { /* 2*i+3 is composite */ continue; } /* The next tiny prime */ t = 2 * i + 3; /* Mark all multiples of t */ for (j = i + t; j < tinybits; j += t) { BIT_SET(TinySieve, j); } sieve_large(t); } /* * Start the small block search at the next possible prime. To avoid * fencepost errors, the last pass is skipped. */ for (smallbase = TINY_NUMBER + 3; smallbase < (SMALL_MAXIMUM - TINY_NUMBER); smallbase += TINY_NUMBER) { for (i = 0; i < tinybits; i++) { if (BIT_TEST(TinySieve, i)) { /* 2*i+3 is composite */ continue; } /* The next tiny prime */ t = 2 * i + 3; r = smallbase % t; if (r == 0) { /* t divides into smallbase exactly */ s = 0; } else { /* smallbase+s is first entry divisible by t */ s = t - r; } /* * The sieve omits even numbers, so ensure that * smallbase+s is odd. Then, step through the sieve in * increments of 2*t */ if (s & 1) { /* Make smallbase+s odd, and s even */ s += t; } /* Mark all multiples of 2*t */ for (s /= 2; s < smallbits; s += t) { BIT_SET(SmallSieve, s); } } /* * SmallSieve */ for (i = 0; i < smallbits; i++) { if (BIT_TEST(SmallSieve, i)) { /* 2*i+smallbase is composite */ continue; } /* The next small prime */ sieve_large((2 * i) + smallbase); } memset(SmallSieve, 0, (size_t)(smallwords << SHIFT_BYTE)); } time(&time_stop); (void)fprintf(stderr, "%.24s Sieved with %u small primes in %lu seconds\n", ctime(&time_stop), largetries, (long) (time_stop - time_start)); for (j = r = 0; j < largebits; j++) { if (BIT_TEST(LargeSieve, j)) { /* Definitely composite, skip */ continue; } #ifdef DEBUG_LARGE (void)fprintf(stderr, "test q = largebase+%lu\n", 2 * j); #endif BN_set_word(q, (unsigned long)(2 * j)); BN_add(q, q, largebase); if (0 > qfileout(stdout, (uint32_t) QTYPE_SOPHIE_GERMAINE, (uint32_t) QTEST_SIEVE, largetries, (uint32_t) (power - 1), /* MSB */ (uint32_t) (0), /* generator unknown */ q)) { break; } r++; /* count q */ } time(&time_stop); free(LargeSieve); free(SmallSieve); free(TinySieve); fflush(stdout); /* fclose(stdout); */ (void) fprintf(stderr, "%.24s Found %u candidates\n", ctime(&time_stop), r); return (0); } static void usage(void) { (void)fprintf(stderr, "Usage: %s <megabytes> <bits> [initial]\n" "Possible values for <megabytes>: 0, %lu to %lu\n" "Possible values for <bits>: %lu to %lu\n", getprogname(), LARGE_MINIMUM, LARGE_MAXIMUM, (unsigned long) TEST_MINIMUM, (unsigned long) TEST_MAXIMUM); exit(1); }

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/* -*- Mode: C; c-basic-offset:4 ; indent-tabs-mode:nil -*- */ /* * Copyright (c) 2021 Google, Inc. All rights reserved. * $COPYRIGHT$ * * Additional copyrights may follow * * $HEADER$ */ #include "opal_config.h" #include "opal/mca/smsc/base/base.h" #include "opal/mca/smsc/cma/smsc_cma_internal.h" #include <fcntl.h> #include <stdio.h> #include <sys/prctl.h> #include <sys/stat.h> #include <sys/types.h> #include <unistd.h> static int mca_smsc_cma_component_register(void); static int mca_smsc_cma_component_open(void); static int mca_smsc_cma_component_close(void); static int mca_smsc_cma_component_query(void); static mca_smsc_module_t *mca_smsc_cma_component_enable(void); #define MCA_SMSC_CMA_DEFAULT_PRIORITY 37 static const int mca_smsc_cma_default_priority = MCA_SMSC_CMA_DEFAULT_PRIORITY; mca_smsc_component_t mca_smsc_cma_component = { .smsc_version = { MCA_SMSC_DEFAULT_VERSION("cma"), .mca_open_component = mca_smsc_cma_component_open, .mca_close_component = mca_smsc_cma_component_close, .mca_register_component_params = mca_smsc_cma_component_register, }, .priority = MCA_SMSC_CMA_DEFAULT_PRIORITY, .query = mca_smsc_cma_component_query, .enable = mca_smsc_cma_component_enable, }; static int mca_smsc_cma_component_register(void) { mca_smsc_base_register_default_params(&mca_smsc_cma_component, mca_smsc_cma_default_priority); return OPAL_SUCCESS; } static int mca_smsc_cma_component_open(void) { /* nothing to do */ return OPAL_SUCCESS; } static int mca_smsc_cma_component_close(void) { /* nothing to do */ return OPAL_SUCCESS; } /* * mca_btl_sm_parse_proc_ns_user() tries to get the user namespace ID * of the current process. * Returns the ID of the user namespace. In the case of an error '0' is returned. */ ino_t mca_smsc_cma_get_user_ns_id(void) { struct stat buf; if (0 > stat("/proc/self/ns/user", &buf)) { /* * Something went wrong, probably an old kernel that does not support namespaces * simply assume all processes are in the same user namespace and return 0 */ return 0; } return buf.st_ino; } static int mca_smsc_cma_send_modex(void) { mca_smsc_cma_modex_t modex; modex.pid = getpid(); modex.user_ns_id = mca_smsc_cma_get_user_ns_id(); int rc; OPAL_MODEX_SEND(rc, PMIX_LOCAL, &mca_smsc_cma_component.smsc_version, &modex, sizeof(modex)); return rc; } static int mca_smsc_cma_component_query(void) { /* Check if we have the proper permissions for CMA */ char buffer = '0'; bool cma_happy = false; /* check system setting for current ptrace scope */ int fd = open("/proc/sys/kernel/yama/ptrace_scope", O_RDONLY); if (0 <= fd) { int ret = read(fd, &buffer, 1); if (ret < 0) { opal_output_verbose(MCA_BASE_VERBOSE_COMPONENT, opal_smsc_base_framework.framework_output, "mca_smsc_cma_component_query: could not read ptrace_scope. " "assuming ptrace scope is 0"); } close(fd); } /* ptrace scope 0 will allow an attach from any of the process owner's * processes. ptrace scope 1 limits attachers to the process tree * starting at the parent of this process. */ if ('0' != buffer) { #if defined PR_SET_PTRACER /* try setting the ptrace scope to allow attach */ int ret = prctl(PR_SET_PTRACER, PR_SET_PTRACER_ANY, 0, 0, 0); if (0 == ret) { cma_happy = true; } #endif } else { cma_happy = true; } if (!cma_happy) { opal_output_verbose(MCA_BASE_VERBOSE_COMPONENT, opal_smsc_base_framework.framework_output, "mca_smsc_cma_component_query: could not select for use. insufficient " "ptrace permissions."); mca_smsc_cma_component.priority = -1; return OPAL_ERR_NOT_AVAILABLE; } mca_smsc_cma_send_modex(); return OPAL_SUCCESS; } static mca_smsc_module_t *mca_smsc_cma_component_enable(void) { if (0 > mca_smsc_cma_component.priority) { return NULL; } return &mca_smsc_cma_module; }

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/* $NetBSD: mcount.c,v 1.14 2019/08/27 22:48:53 kamil Exp $ */ /* * Copyright (c) 2003, 2004 Wasabi Systems, Inc. * All rights reserved. * * Written by Nathan J. Williams for Wasabi Systems, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed for the NetBSD Project by * Wasabi Systems, Inc. * 4. The name of Wasabi Systems, Inc. may not be used to endorse * or promote products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 1983, 1992, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include <sys/types.h> #include <sys/gmon.h> #include <sys/interrupt.h> #include <sys/mutex.h> #include <sys/types.h> static SPIN_DEFINE(mcount_lock, 0); /* * * The function is updating an array of linked lists, which stores * how many times a function have been called by a second function. * * froms[X] - index X encodes a function (call site of the function, * there could be many for one function). * The value stored in froms[X] is an index of a tos entry, * which is a node from a linked list of called functions by X. * The list is sorted by most recently called functions. * * tos[Y] - a tos entry Y stores information about the called function: * selfpc - the address * count - how many times have it been called by the call site * link - index of the next function called by the same call site * (0 - end of the list) * * tos[0].link + 1 is the smallest index of an unused tos entry * * \warning This function while unlocking spinlock can turn on interrupts when * thread's td_idnest == 0, this problem occurs e.g. in mips_exc_handler, * this is why we do not profile user_mode_p. */ __no_profile void __cyg_profile_func_enter(void *self, void *from) { u_long frompc = (u_long)from, selfpc = (u_long)self; u_short *frompcindex; tostruct_t *top, *prevtop; gmonparam_t *p = &_gmonparam; long toindex; if (p->state != GMON_PROF_ON) return; WITH_SPIN_LOCK (&mcount_lock) { /* * To ensure consistent data in kgmon - this function can move * a node from the middle of the list to the beginning and * during this process we can omit it while accesing the structure. */ p->state = GMON_PROF_BUSY; /* * check that frompc is a reasonable pc value. * for example: signal catchers get called from the stack, * not from text space. too bad. */ frompc -= p->lowpc; if (frompc >= p->textsize) goto done; size_t index = (frompc / (HASHFRACTION * sizeof(*p->froms))); frompcindex = &p->froms[index]; toindex = *frompcindex; /* * First time profiling this calling function . */ if (toindex == 0) { /* * Getting an unused node (the smallest unused tos entry index). */ toindex = ++p->tos[0].link; if (toindex >= p->tolimit) { p->state = GMON_PROF_ERROR; goto done; } *frompcindex = (u_short)toindex; top = &p->tos[(size_t)toindex]; top->selfpc = selfpc; top->count = 1; top->link = 0; goto done; } top = &p->tos[(size_t)toindex]; /* * Node with our called function at front of chain; usual case. */ if (top->selfpc == selfpc) { top->count++; goto done; } /* * Traversing the list and looking for node with our called function. */ while (true) { /* * We reached the end of the list it does not contain a node with * the called function. Check if there are still available nodes to use, * if so get one and add it to the list. */ if (top->link == 0) { toindex = ++p->tos[0].link; if (toindex >= p->tolimit) { p->state = GMON_PROF_ERROR; goto done; } top = &p->tos[(size_t)toindex]; top->selfpc = selfpc; top->count = 1; top->link = *frompcindex; *frompcindex = (u_short)toindex; goto done; } /* * Move to the next node. */ prevtop = top; top = &p->tos[top->link]; /* * We found our node,remove it from our list * and add it at the beginning of the list. */ if (top->selfpc == selfpc) { top->count++; toindex = prevtop->link; prevtop->link = top->link; top->link = *frompcindex; *frompcindex = (u_short)toindex; goto done; } } done: if (p->state != GMON_PROF_ERROR) p->state = GMON_PROF_ON; } } __no_profile void __cyg_profile_func_exit(void *this_fn, void *call_site) { }

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/* * Copyright (c) 1993-1995 Argonaut Technologies Limited. All rights reserved. * * $Id: match.c 1.1 1997/12/10 16:47:17 jon Exp $ * $Locker: $ * * Functions that match a primitive against the renderers state */ #include "drv.h" #include "shortcut.h" #include "brassert.h" BR_RCS_ID("$Id: match.c 1.1 1997/12/10 16:47:17 jon Exp $"); /* * Invalid value for unknown pixelmap types */ #define PMT_NONE 255 #if 0 /* DEBUG */ int MatchCount = 0; #endif /* * Descriptions of all the available renderers * * These are not constant because the autoloader modifies the function pointer * */ static struct local_block primInfo_t8[] = { #if BASED_FLOAT #pragma message ("FLOAT") #include "prim_t8f.c" #endif #if BASED_FIXED #pragma message ("FIXED") #include "prim_t8x.c" #endif }; static struct local_block primInfo_l8[] = { #include "prim_l8.c" }; static struct local_block primInfo_p8[] = { #include "prim_p8.c" }; static struct local_block primInfo_t15[] = { #if BASED_FLOAT #pragma message ("FLOAT") #include "prm_t15f.c" #endif #if BASED_FIXED #pragma message ("FIXED") #include "prm_t15x.c" #endif }; static struct local_block primInfo_l15[] = { #include "prim_l15.c" }; static struct local_block primInfo_p15[] = { #include "prim_p15.c" }; static struct local_block primInfo_t16[] = { #if BASED_FLOAT #pragma message ("FLOAT") #include "prm_t16f.c" #endif #if BASED_FIXED #pragma message ("FIXED") #include "prm_t16x.c" #endif }; static struct local_block primInfo_l16[] = { #include "prim_l16.c" }; static struct local_block primInfo_p16[] = { #include "prim_p16.c" }; static struct local_block primInfo_t24[] = { #include "prim_t24.c" }; static struct local_block primInfo_l24[] = { #include "prim_l24.c" }; static struct local_block primInfo_p24[] = { #include "prim_p24.c" }; struct prim_info_table { struct local_block *blocks; int nblocks; }; static const struct prim_info_table primInfoTables[4][3] = { { { primInfo_p8, BR_ASIZE(primInfo_p8), }, { primInfo_l8, BR_ASIZE(primInfo_l8), }, { primInfo_t8, BR_ASIZE(primInfo_t8), }, },{ { primInfo_p15, BR_ASIZE(primInfo_p15), }, { primInfo_l15, BR_ASIZE(primInfo_l15), }, { primInfo_t15, BR_ASIZE(primInfo_t15), }, },{ { primInfo_p16, BR_ASIZE(primInfo_p16), }, { primInfo_l16, BR_ASIZE(primInfo_l16), }, { primInfo_t16, BR_ASIZE(primInfo_t16), }, },{ { primInfo_p24, BR_ASIZE(primInfo_p24), }, { primInfo_l24, BR_ASIZE(primInfo_l24), }, { primInfo_t24, BR_ASIZE(primInfo_t24), }, } }; /* * Block of priminfo to use if MMX is detected */ #if USE_MMX static struct local_block mmxInfo_t15[] = { #if BASED_FLOAT #include "mmx_t15f.c" #endif #if BASED_FIXED #include "mmx_t15x.c" #endif }; static struct local_block mmxInfo_t16[] = { #if BASED_FLOAT #include "mmx_t16f.c" #endif #if BASED_FIXED #include "mmx_t16x.c" #endif }; static const struct prim_info_table mmxInfoTables[4][3] = { { { primInfo_p8, BR_ASIZE(primInfo_p8), }, { primInfo_l8, BR_ASIZE(primInfo_l8), }, { primInfo_t8, BR_ASIZE(primInfo_t8), }, },{ { primInfo_p15, BR_ASIZE(primInfo_p15), }, { primInfo_l15, BR_ASIZE(primInfo_l15), }, { mmxInfo_t15, BR_ASIZE(mmxInfo_t15), }, },{ { primInfo_p16, BR_ASIZE(primInfo_p16), }, { primInfo_l16, BR_ASIZE(primInfo_l16), }, { mmxInfo_t16, BR_ASIZE(mmxInfo_t16), }, },{ { primInfo_p24, BR_ASIZE(primInfo_p24), }, { primInfo_l24, BR_ASIZE(primInfo_l24), }, { primInfo_t24, BR_ASIZE(primInfo_t24), }, } }; #endif /* * Transcribe buffer info into static paramater area for renderers */ /* * Output buffers */ static void updateWorkOut(struct prim_work *pw, struct br_primitive_state *self) { if(self->out.colour.pixelmap) SetupRenderBuffer(&pw->colour, self->out.colour.pixelmap); if(self->out.depth.pixelmap) SetupRenderBuffer(&pw->depth, self->out.depth.pixelmap); pw->timestamp_out = self->out.timestamp; } /* * Input buffers */ static void updateWorkPrim(struct prim_work *pw, struct br_primitive_state *self) { if(self->prim.colour_map.buffer) { pw->texture = self->prim.colour_map.buffer->buffer; /* * If texture does not have a palette - inherit one from screen */ if(pw->texture.palette == NULL) { pw->texture.palette = pw->colour.palette; pw->texture.palette_size = pw->colour.palette_size; } } if(self->prim.bump.buffer) pw->bump = self->prim.bump.buffer->buffer; if(self->prim.index_shade.buffer) { pw->shade_type = self->prim.index_shade.buffer->buffer.type; pw->shade_table = self->prim.index_shade.buffer->buffer.base; pw->index_base = self->prim.index_base; pw->index_range = self->prim.index_range; } if(self->prim.index_blend.buffer) { pw->blend_type = self->prim.index_blend.buffer->buffer.type; pw->blend_table = self->prim.index_blend.buffer->buffer.base; } if(self->prim.screendoor.buffer) { pw->screendoor_type = self->prim.screendoor.buffer->buffer.type; pw->blend_table = self->prim.screendoor.buffer->buffer.base; } if(self->prim.lighting.buffer) { pw->lighting_type = self->prim.lighting.buffer->buffer.type; pw->blend_table = self->prim.lighting.buffer->buffer.base; } if(self->prim.index_fog.buffer) { pw->fog_type = self->prim.index_fog.buffer->buffer.type; pw->fog_table = self->prim.index_fog.buffer->buffer.base; } if(self->prim.flags & PRIMF_DECAL) { pw->decal_index_base = self->prim.index_base; pw->decal_index_range = self->prim.index_range; pw->decal_shade_height = self->prim.index_shade.height; } pw->timestamp_prim = self->prim.timestamp; } static void updateRanges(struct br_primitive_state *self) { int i; br_uint_32 m; /* * XXX should make sure we have a valid block looked up */ if(self->cache.last_block == NULL) return; /* * Mask of required components */ m = self->cache.last_block->p.constant_components | self->cache.last_block->p.vertex_components; /* * Everything defaults to offset = 0, scale = 1 */ for(i=0; i < NUM_COMPONENTS; i++) { self->cache.comp_offsets[i] = BR_SCALAR(0.0); self->cache.comp_scales[i] = BR_SCALAR(1.0); } /* * SX,SY range are based on current colour_buffer */ if(self->cache.last_block->range_flags & RF_OFFSET_Y) { /* * Offset Y by one scanline so that FPU setup code never gets y == 0 (as it chokes) */ self->cache.comp_offsets[C_SX] = BR_CONST_DIV(BrIntToScalar(self->out.colour.width),2) - BR_SCALAR(0.5); self->cache.comp_scales[C_SX] = BR_CONST_DIV(BrIntToScalar(self->out.colour.width),2); self->cache.comp_offsets[C_SY] = BR_CONST_DIV(BrIntToScalar(self->out.colour.height),2) + BR_SCALAR(0.5); self->cache.comp_scales[C_SY] = -BR_CONST_DIV(BrIntToScalar(self->out.colour.height),2); } else{ self->cache.comp_offsets[C_SX] = BR_CONST_DIV(BrIntToScalar(self->out.colour.width),2) + BR_SCALAR(0.5); self->cache.comp_scales[C_SX] = BR_CONST_DIV(BrIntToScalar(self->out.colour.width),2); self->cache.comp_offsets[C_SY] = BR_CONST_DIV(BrIntToScalar(self->out.colour.height),2) + BR_SCALAR(0.5); self->cache.comp_scales[C_SY] = -BR_CONST_DIV(BrIntToScalar(self->out.colour.height),2); } /* * SZ is fixed - -1 to +1 (Setup code remaps to unsigned 16 bit) */ self->cache.comp_offsets[C_SZ] = BR_SCALAR(0); self->cache.comp_scales[C_SZ] = -BR_SCALAR(32767); /* * U,V range are based on current colour_map, if required */ if(m & (CM_U | CM_V)) { if(self->cache.last_block->texture_type != PMT_NONE) { if(self->cache.last_block->range_flags & RF_UNSCALED_TEXTURE_COORDS) { self->cache.comp_scales[C_U] = BR_SCALAR(1); self->cache.comp_scales[C_V] = BR_SCALAR(1); }else{ self->cache.comp_scales[C_U] = BrIntToScalar(self->prim.colour_map.width); self->cache.comp_scales[C_V] = BrIntToScalar(self->prim.colour_map.height); } } } /* * R,G,B are pulled from current prim. block, unless 'rgb_shade' is true, * when the scales are from the shade tbale height */ if(m & (CM_R | CM_G | CM_B)) { if(self->cache.last_block->range_flags & RF_RGB_SHADE) { self->cache.comp_scales[C_R] = BrIntToScalar(self->prim.index_shade.height-1); self->cache.comp_scales[C_G] = BrIntToScalar(self->prim.index_shade.height-1); self->cache.comp_scales[C_B] = BrIntToScalar(self->prim.index_shade.height-1); self->cache.comp_offsets[C_R] = BR_SCALAR(0.5); self->cache.comp_offsets[C_G] = BR_SCALAR(0.5); self->cache.comp_offsets[C_B] = BR_SCALAR(0.5); } else { self->cache.comp_scales[C_R] = self->cache.last_block->colour_scales[0]; self->cache.comp_scales[C_G] = self->cache.last_block->colour_scales[1]; self->cache.comp_scales[C_B] = self->cache.last_block->colour_scales[2]; self->cache.comp_offsets[C_R] = self->cache.last_block->colour_offsets[0]; self->cache.comp_offsets[C_G] = self->cache.last_block->colour_offsets[1]; self->cache.comp_offsets[C_B] = self->cache.last_block->colour_offsets[2]; } } /* * Alpha scaling is specified in block, unless a blend or screendoor table is used */ if(m & CM_A) { if(self->cache.last_block->blend_type != PMT_NONE) { self->cache.comp_scales[C_A] = BrIntToScalar(self->prim.index_blend.height-1); self->cache.comp_offsets[C_A] = BR_SCALAR(0.5); } else if(self->cache.last_block->screendoor_type != PMT_NONE) { self->cache.comp_scales[C_A] = BrIntToScalar(self->prim.screendoor.height-1); self->cache.comp_offsets[C_A] = BR_SCALAR(0.5); } else { self->cache.comp_scales[C_A] = self->cache.last_block->colour_scales[3]; self->cache.comp_offsets[C_A] = self->cache.last_block->colour_offsets[3]; } } /* * I - If a shade table is in use, comes from shade table, else use user base/range */ if(m & CM_I) { if(self->cache.last_block->range_flags & RF_DECAL) { self->cache.comp_offsets[C_I] = BR_SCALAR(0.5); self->cache.comp_scales[C_I] = BR_SCALAR(254.0); } else if(self->cache.last_block->shade_type != PMT_NONE) { self->cache.comp_scales[C_I] = BrIntToScalar(self->prim.index_shade.height-1); self->cache.comp_offsets[C_I] = BR_SCALAR(0.5); } else { self->cache.comp_scales[C_I] = BrIntToScalar(self->prim.index_range); self->cache.comp_offsets[C_I] = BrIntToScalar(self->prim.index_base) + BR_SCALAR(0.5); } } } /* * Reture true if argument is a power of 2 */ static br_boolean isPowerof2(br_int_32 x) { return !((x-1) & x); } br_error BR_CMETHOD_DECL(br_primitive_state_soft, renderBegin)( struct br_primitive_state *self, struct brp_block **rpb, br_boolean *block_changed, br_boolean *ranges_changed, br_boolean no_render, br_token prim_type) { int i,j,b,nb; struct local_block *pb; br_uint_32 flags; br_token input_colour_type; ASSERT(rpb); ASSERT(self); ASSERT(self->plib); /* * Lock destination pixelmap for rendering a new model or scene if * it is not already locked. * N.B. Pixelmap is unlocked by br_primitive_library_soft::flush. */ if (!no_render && self->plib->colour_buffer != self->out.colour.pixelmap) { /* * Unlock previous buffer */ if(self->plib->colour_buffer != NULL) DevicePixelmapDirectUnlock( self->plib->colour_buffer); /* * Lock new buffer */ self->plib->colour_buffer = self->out.colour.pixelmap ; DevicePixelmapDirectLock( self->plib->colour_buffer, BR_TRUE); } #if 1 /* * If previous match is still valid, return that */ if(self->cache.last_type == prim_type) { if(self->cache.timestamp_prim == self->prim.timestamp_major && self->cache.timestamp_out == self->out.timestamp_major) { *rpb = &self->cache.last_block->p; *block_changed = BR_FALSE; *ranges_changed = BR_FALSE; /* * Generate 'work' data */ if(self->cache.last_block->work->timestamp_prim != self->prim.timestamp) updateWorkPrim(self->cache.last_block->work, self); if(self->cache.last_block->work->timestamp_out != self->out.timestamp) updateWorkOut(self->cache.last_block->work, self); /* * Flush rasterise stack if necessary */ if(self->cache.last_block->range_flags & RF_FLUSH) RasteriseBufferFlush(); return BRE_OK; } } #endif /* * Assume the worst, that changes will have happened */ *block_changed = BR_TRUE; *ranges_changed = BR_TRUE; #if 0 /* DEBUG */ MatchCount++; #endif /* * XXX Validate the various buffers we are about to use */ #if 0 if(self->colour) { if(!ObjectIsA(self->colour,BRT_DEVICE_PIXELMAP)) return BRE_FAIL; if(self->colour->flags & BR_PMF_NO_DIRECT_ACCESS) return BRE_FAIL; if(!(self->colour->flags & BR_PMF_PIXELS_NEAR)) return BRE_FAIL; } #endif /* * Generate buffer info */ work.colour.type = PMT_NONE; work.depth.type = PMT_NONE; work.texture.type = PMT_NONE; work.bump.type = PMT_NONE; work.shade_type = PMT_NONE; work.blend_type = PMT_NONE; work.screendoor_type = PMT_NONE; work.lighting_type = PMT_NONE; work.fog_type = PMT_NONE; work.texture.width_p = 0; work.texture.height = 0; updateWorkOut(&work, self); updateWorkPrim(&work, self); if(self->prim.custom_block) { /* * If a custom block has been give, use that */ pb = self->prim.custom_block; } else { /* * Generate exrta match flag flags */ flags = self->prim.flags; if(work.index_range == 0) flags|=PRIMF_RANGE_ZERO; if(work.texture.type != PMT_NONE) { /* * See if the stride is the same as the width */ if(work.texture.width_b == work.texture.stride_b) flags |= PRIMF_NO_SKIP; if(work.texture.stride_b>0) flags |= PRIMF_STRIDE_POSITIVE; /* * See if texture size is ^2 which is .lt. 1024 */ if(isPowerof2(work.texture.width_p) && isPowerof2(work.texture.height) && work.texture.width_p <= 1024 && work.texture.height <= 1024) { flags |= PRIMF_POWER2; } /* * Does texture have a large enough palette attached? */ if(work.texture.palette) { int s; switch(work.texture.type) { case BR_PMT_INDEX_1: s = 2; break; case BR_PMT_INDEX_2: s = 4; break; case BR_PMT_INDEX_4: s = 16; break; case BR_PMT_INDEX_8: s = 256; break; } if(work.texture.palette_size >= s) flags |= PRIMF_PALETTE; } } /* * Look for perpective correct primitives if type is set (but not to subdivide) */ if(self->prim.perspective_type != BRT_NONE && self->prim.perspective_type != BRT_SUBDIVIDE) { flags |= PRIMF_PERSPECTIVE; } /* * Pick a primitives array based on colour buffer type and primitive */ switch(work.colour.type) { case BR_PMT_INDEX_8: i = 0; input_colour_type = BRT_INDEX; break; case BR_PMT_RGB_555: i = 1; input_colour_type = BRT_RGB; break; case BR_PMT_RGB_565: i = 2; input_colour_type = BRT_RGB; break; case BR_PMT_RGB_888: i = 3; input_colour_type = BRT_RGB; break; default: self->cache.last_block = NULL; return BRE_FAIL; } if(self->prim.colour_type != BRT_DEFAULT) input_colour_type = self->prim.colour_type; switch(prim_type) { case BRT_POINT: j = 0; break; case BRT_LINE: j = 1; break; case BRT_TRIANGLE: j = 2; break; default: self->cache.last_block = NULL; return BRE_FAIL; } /* * Match against selected primitives */ #if USE_MMX if(self->plib->use_mmx) { pb = mmxInfoTables[i][j].blocks; nb = mmxInfoTables[i][j].nblocks; } else { pb = primInfoTables[i][j].blocks; nb = primInfoTables[i][j].nblocks; } #else pb = primInfoTables[i][j].blocks; nb = primInfoTables[i][j].nblocks; #endif for(b=0; b < nb; b++,pb++) { /* * Do the flags match */ if((flags & pb->flags_mask) != pb->flags_cmp) continue; /* * Check buffer types */ if((pb->depth_type) != PMT_NONE && (work.depth.type != pb->depth_type)) continue; if((pb->texture_type) != PMT_NONE && (work.texture.type != pb->texture_type)) continue; if((pb->shade_type) != PMT_NONE && (work.shade_type != pb->shade_type)) continue; if((pb->bump_type) != PMT_NONE && (work.bump.type != pb->bump_type)) continue; if((pb->lighting_type) != PMT_NONE && (work.lighting_type != pb->lighting_type)) continue; if((pb->screendoor_type) != PMT_NONE && (work.screendoor_type != pb->screendoor_type)) continue; if((pb->blend_type) != PMT_NONE && (work.blend_type != pb->blend_type)) continue; if((pb->fog_type) != PMT_NONE && (work.fog_type != pb->fog_type)) continue; /* * See if input colour type matches */ if(pb->input_colour_type && (input_colour_type != pb->input_colour_type)) continue; /* * See if there are any size restrictions */ if(pb->map_width && (pb->map_width != work.texture.width_p)) continue; if(pb->map_height && (pb->map_height != work.texture.height)) continue; /* * Got one!! */ break; } /* * Default to last primitive in block */ if(b >= nb) { pb--; } } /* * Copy buffer info if neccesary */ if(pb->work && (pb->work != &work)) *pb->work = work; /* * If subdivision was requested, mark up the block * If rasteriser is perspective correct do not disturb subdivide flag */ if(self->prim.perspective_type == BRT_SUBDIVIDE || (pb->range_flags & RF_NEED_SUBDIVIDE)) { pb->p.flags |= BR_PRIMF_SUBDIVIDE; pb->p.subdivide_tolerance = self->prim.subdivide_tolerance; } else { pb->p.flags &= ~BR_PRIMF_SUBDIVIDE; } /* * return pointer to primitive, and set 'unchanged' if this * pointer is the same as previous match */ *rpb = &pb->p; if(pb == self->cache.last_block) { *block_changed = BR_FALSE; } else { self->cache.last_block = pb; } updateRanges(self); self->cache.last_type = prim_type; self->cache.timestamp_prim = self->prim.timestamp_major; self->cache.timestamp_out = self->out.timestamp_major; if(pb->range_flags & RF_FLUSH) RasteriseBufferFlush(); return BRE_OK; } br_error BR_CMETHOD_DECL(br_primitive_state_soft, renderEnd)( struct br_primitive_state *self, struct brp_block *pb) { return BRE_OK; } /* * Thunk that loads a renderer from a DLL * * pb->entry_info is a pointer to the name of the new render fn. */ void BR_ASM_CALL RenderAutoloadThunk(brp_block *block, brp_vertex *v0, brp_vertex *v1,brp_vertex *v2) { struct local_block *pb = (struct local_block *)block; br_image *image; brp_render_fn *render_fn; br_work_fn *work_fn; struct prim_work *old_work; ASSERT(pb->image_name); ASSERT(pb->entry_info); /* * Assume the worst - if no renderer is found - use dummy */ pb->p.render = (brp_render_fn *)TriangleRenderNull; /* * Try any load up referenced image */ image = BrImageReference(pb->image_name); ASSERT(image); /* * Don't do anything if it failed */ if(image == NULL) return; /* * Look up function name */ render_fn = BrImageLookupName(image,(char *)pb->entry_info,0); if(render_fn == NULL) { BrImageDereference(image); return; } /* * Look up work ptr function */ work_fn = BrImageLookupName(image,"_PrimLibWork",0); ASSERT(work_fn); if(work_fn == NULL) { BrImageDereference(image); return; } /* * Get work pointer */ old_work = pb->work; pb->work = work_fn(); /* * Copy work data into final destination */ *pb->work = *old_work; /* * Change block over to use loaded function */ pb->p.render = render_fn; /* * Hand over to new rendering function */ render_fn(block,v0,v1,v2); } /* * Thunk that loads generic setup rasterisers from a DLL * * pb->entry_info is the new render entry point * * Each of the setup.rasterise... function pointers is converted from * a pointer to a string to a pointer to a function looked up in the image */ void BR_ASM_CALL GenericAutoloadThunk(brp_block *block, brp_vertex *v0, brp_vertex *v1,brp_vertex *v2) { struct local_block *pb = (struct local_block *)block; br_image *image; ASSERT(pb->image_name); ASSERT(pb->entry_info); /* * Assume the worst - if no renderer is found - use dummy */ pb->p.render = (brp_render_fn *)TriangleRenderNull; /* * Try any load up referenced image */ image = BrImageReference(pb->image_name); ASSERT(image); /* * Don't do anything if it failed */ if(image == NULL) return; /* * Look up the rasteriser names */ pb->setup.rasterise_rl_l = BrImageLookupName(image,(char *)pb->setup.rasterise_rl_l,0); pb->setup.rasterise_lr_l = BrImageLookupName(image,(char *)pb->setup.rasterise_lr_l,0); pb->setup.rasterise_rl_s = BrImageLookupName(image,(char *)pb->setup.rasterise_rl_s,0); pb->setup.rasterise_lr_s = BrImageLookupName(image,(char *)pb->setup.rasterise_lr_s,0); if(pb->setup.rasterise_rl_l == NULL || pb->setup.rasterise_lr_l == NULL || pb->setup.rasterise_rl_s == NULL || pb->setup.rasterise_lr_s == NULL) { BrImageDereference(image); return; } /* * Change block over to use the generic setup function */ pb->p.render = pb->entry_info; /* * Hand over to setp function */ pb->p.render(block,v0,v1,v2); } br_error BR_CMETHOD_DECL(br_primitive_state_soft, rangesQueryF)( struct br_primitive_state *self, br_float *offset, br_float *scale, br_int_32 max_comp) { int i; /* * Fail if the current info is not valid */ if(self->cache.timestamp_prim != self->prim.timestamp_major || self->cache.timestamp_out != self->out.timestamp_major) return BRE_FAIL; for(i=0; i < max_comp; i++) { offset[i] = BrScalarToFloat(self->cache.comp_offsets[i]); scale[i] = BrScalarToFloat(self->cache.comp_scales[i]); } return BRE_OK; } br_error BR_CMETHOD_DECL(br_primitive_state_soft, rangesQueryX)( struct br_primitive_state *self, br_fixed_ls *offset, br_fixed_ls *scale, br_int_32 max_comp) { int i; /* * Fail if the current info is not valid */ if(self->cache.timestamp_prim != self->prim.timestamp_major || self->cache.timestamp_out != self->out.timestamp_major) return BRE_FAIL; for(i=0; i < max_comp; i++) { offset[i] = BrScalarToFixed(self->cache.comp_offsets[i]); scale[i] = BrScalarToFixed(self->cache.comp_scales[i]); } return BRE_OK; } /* * Dummy triangle renderer */ void BR_ASM_CALL TriangleRenderNull(brp_block *block, brp_vertex *v0, brp_vertex *v1, brp_vertex *v2) { }

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extern void exit (int); static inline int foo (void) { #ifdef __OPTIMIZE__ extern int undefined_reference; return undefined_reference; #else return 0; #endif } static inline int bar (void) { if (foo == foo) return 1; else return foo (); } int main (void) { exit (0); }

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/*=========================================================================== * * PUBLIC DOMAIN NOTICE * National Center for Biotechnology Information * * This software/database is a "United States Government Work" under the * terms of the United States Copyright Act. It was written as part of * the author's official duties as a United States Government employee and * thus cannot be copyrighted. This software/database is freely available * to the public for use. The National Library of Medicine and the U.S. * Government have not placed any restriction on its use or reproduction. * * Although all reasonable efforts have been taken to ensure the accuracy * and reliability of the software and data, the NLM and the U.S. * Government do not and cannot warrant the performance or results that * may be obtained by using this software or data. The NLM and the U.S. * Government disclaim all warranties, express or implied, including * warranties of performance, merchantability or fitness for any particular * purpose. * * Please cite the author in any work or product based on this material. * * =========================================================================== * */ #ifndef _h_matcher_input_ #define _h_matcher_input_ #ifdef __cplusplus extern "C" { #endif #ifndef _h_vdb_manager_ #include <vdb/manager.h> #endif #ifndef _h_klib_namelist_ #include <klib/namelist.h> #endif #ifndef _h_kfg_config_ #include <kfg/config.h> #endif #ifndef _h_kfs_directory_ #include <kfs/directory.h> #endif /* structure with all the matcher-inputs */ typedef struct matcher_input { VDBManager * manager; const VNamelist * add_schemas; KConfig * cfg; KDirectory * dir; const char * columns; const char * src_path; const char * dst_path; const char * legacy_schema; const char * dst_tabname; const char * excluded_columns; bool force_kcmInit; bool force_unlock; } matcher_input; typedef matcher_input* p_matcher_input; #ifdef __cplusplus } #endif #endif

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ltrharvest_fasta_out_visitor.c

/* Copyright (c) 2010 Sascha Steinbiss <steinbiss@zbh.uni-hamburg.de> Copyright (c) 2010 Center for Bioinformatics, University of Hamburg Permission to use, copy, modify, and distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include <string.h> #include "core/array_api.h" #include "core/class_alloc_lock.h" #include "core/cstr_api.h" #include "core/encseq_api.h" #include "core/fasta_api.h" #include "core/ma_api.h" #include "core/parseutils.h" #include "core/range_api.h" #include "core/str_api.h" #include "core/undef_api.h" #include "core/unused_api.h" #include "core/warning_api.h" #include "extended/node_visitor_api.h" #include "extended/feature_node.h" #include "extended/feature_node_iterator_api.h" #include "extended/feature_type_api.h" #include "ltr/ltrharvest_fasta_out_visitor.h" struct GtLTRharvestFastaOutVisitor { const GtNodeVisitor parent_instance; GtFile* outfp; GtUword width; bool inner; const GtEncseq *encseq; }; #define gt_ltrharvest_fasta_out_visitor_cast(GV)\ gt_node_visitor_cast(gt_ltrharvest_fasta_out_visitor_class(), GV) static int gt_ltrharvest_fasta_out_visitor_feature_node(GtNodeVisitor *nv, GtFeatureNode *fn, GT_UNUSED GtError *err) { GtLTRharvestFastaOutVisitor *lv; GtFeatureNodeIterator *fni; GtFeatureNode *curnode = NULL, *leftltr = NULL, *rightltr = NULL, *ltr_retrotrans = NULL; int had_err = 0, added_ltr = 0; GtRange rng, outrng; GtUword seqnum = GT_UNDEF_UWORD; const char *fnt; lv = gt_ltrharvest_fasta_out_visitor_cast(nv); gt_assert(lv); gt_error_check(err); /* traverse annotation subgraph and collect info */ fni = gt_feature_node_iterator_new(fn); while (!had_err && (curnode = gt_feature_node_iterator_next(fni))) { fnt = gt_feature_node_get_type(curnode); if (strcmp(fnt, gt_ft_LTR_retrotransposon) == 0) { const char *val; ltr_retrotrans = curnode; val = gt_feature_node_get_attribute(curnode, "seq_number"); if (val == NULL) { gt_error_set(err, "missing attribute \"seq_number\""); had_err = -1; } if (!had_err) { (void) gt_parse_uword(&seqnum, val); } } if (strcmp(fnt, gt_ft_long_terminal_repeat) == 0) { switch (added_ltr) { case 0: leftltr = curnode; break; case 1: rightltr = curnode; break; default: gt_error_set(err, "invalid number of LTR annotations: more than 2"); had_err = -1; } added_ltr++; } } gt_feature_node_iterator_delete(fni); /* check for invalid annotations */ if (!had_err && (!leftltr || !rightltr)) { gt_error_set(err, "missing LTR annotations"); had_err = -1; } /* determine sequence interval to output */ if (lv->inner) { gt_assert(leftltr && rightltr); rng = gt_genome_node_get_range((GtGenomeNode*) leftltr); outrng.start = rng.end + 1; rng = gt_genome_node_get_range((GtGenomeNode*) rightltr); outrng.end = rng.start - 1; } else { gt_assert(ltr_retrotrans); rng = gt_genome_node_get_range((GtGenomeNode*) ltr_retrotrans); outrng = rng; } /* output FASTA sequences */ if (!had_err && ltr_retrotrans != NULL) { if (outrng.start < outrng.end) { char *buf; const char *seqdesc; GtStr *desc; GtUword startpos, seqdesclen; gt_assert(seqnum != GT_UNDEF_UWORD && seqnum < gt_encseq_num_of_sequences(lv->encseq)); seqdesc = gt_encseq_description(lv->encseq, &seqdesclen, seqnum); desc = gt_str_new(); gt_str_append_cstr_nt(desc, seqdesc, seqdesclen); gt_str_append_cstr(desc, " (dbseq-nr "); gt_str_append_uword(desc, seqnum); gt_str_append_cstr(desc, ") ["); gt_str_append_uword(desc, outrng.start); gt_str_append_cstr(desc, ","); gt_str_append_uword(desc, outrng.end); gt_str_append_cstr(desc, "]"); buf = gt_calloc((size_t) gt_range_length(&outrng) + 1, sizeof (char)); startpos = gt_encseq_seqstartpos(lv->encseq, seqnum); gt_encseq_extract_decoded(lv->encseq, buf, startpos + outrng.start - 1, startpos + outrng.end - 1); gt_fasta_show_entry(gt_str_get(desc), buf, gt_range_length(&outrng), lv->width, lv->outfp); gt_free(buf); gt_str_delete(desc); } else { GtRange rootrng; rootrng = gt_genome_node_get_range((GtGenomeNode*) ltr_retrotrans); gt_warning("trying to output empty%s sequence for candidate at " ""GT_WU"-"GT_WU" on sequence "GT_WU"", (lv->inner ? " inner" : ""), rootrng.start, rootrng.end, seqnum); } } return had_err; } const GtNodeVisitorClass* gt_ltrharvest_fasta_out_visitor_class(void) { static const GtNodeVisitorClass *nvc = NULL; gt_class_alloc_lock_enter(); if (!nvc) { nvc = gt_node_visitor_class_new(sizeof (GtLTRharvestFastaOutVisitor), NULL, NULL, gt_ltrharvest_fasta_out_visitor_feature_node, NULL, NULL, NULL); } gt_class_alloc_lock_leave(); return nvc; } GtNodeVisitor* gt_ltrharvest_fasta_out_visitor_new(const GtEncseq *encseq, bool inner, GtUword width, GtFile *outfp) { GtNodeVisitor *nv; GtLTRharvestFastaOutVisitor *lv; gt_assert(encseq && outfp); nv = gt_node_visitor_create(gt_ltrharvest_fasta_out_visitor_class()); lv = gt_ltrharvest_fasta_out_visitor_cast(nv); gt_assert(lv); lv->inner = inner; lv->outfp = outfp; lv->width = width; lv->encseq = encseq; return nv; }

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// RUN: %clang -I../../../include -emit-llvm -g -c %s -o %t.bc // RUN: rm -rf %t.klee-out // RUN: %klee --output-dir=%t.klee-out --write-kqueries %t.bc > %t.log // RUN: cat %t.klee-out/test000001.kquery %t.klee-out/test000002.kquery %t.klee-out/test000003.kquery %t.klee-out/test000004.kquery > %t1 // RUN: grep "a\[1\]" %t1 | wc -l | grep 2 // RUN: grep "a\[100\]" %t1 | wc -l | grep 2 /* Tests that the Array factory correctly distinguishes between arrays created at the same location but with different sizes */ #include <stdio.h> #include <stdlib.h> char* mk_sym(int size) { char *a = malloc(size); klee_make_symbolic(a, size, "a"); return a; } int main() { int t; char *a, *b; klee_make_symbolic(&t, sizeof(t), "t"); if (t) { printf("Allocate obj of size 1\n"); a = mk_sym(1); if (a[0] > 'a') printf("Yes\n"); else printf("No\n"); } else { printf("Allocate obj of size 2\n"); b = mk_sym(100); if (b[99] > 'a') printf("Yes\n"); else printf("No\n"); } return 0; }

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#include <sys/quota.h> #include "syscall.h" int quotactl(int cmd, const char *special, int id, char *addr) { return syscall(SYS_quotactl, cmd, special, id, addr); }

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#ifndef Z_EN_ZOS_H #define Z_EN_ZOS_H #include "global.h" #include "objects/object_zos/object_zos.h" struct EnZos; typedef void (*EnZosActionFunc)(struct EnZos*, PlayState*); #define ENZOS_GET_F(thisx) ((thisx)->params & 0xF) typedef enum { /* 1 */ ENZOS_F_1 = 1, /* 2 */ ENZOS_F_2 } EnZosParam; typedef struct EnZos { /* 0x000 */ Actor actor; /* 0x144 */ Vec3s jointTable[EVAN_LIMB_MAX]; /* 0x1B0 */ Vec3s morphTable[EVAN_LIMB_MAX]; /* 0x21C */ SkelAnime skelAnime; /* 0x260 */ ColliderCylinder collider; /* 0x2AC */ s16 eyeIndex; /* 0x2AE */ s16 blinkTimer; /* 0x2B0 */ UNK_TYPE1 unk2B0[6]; /* 0x2B6 */ u16 unk_2B6; /* 0x2B8 */ s16 animIndex; /* 0x2BA */ s16 cueId; /* 0x2BC */ s16 unk_2BC; /* 0x2C0 */ EnZosActionFunc actionFunc; } EnZos; // size = 0x2C4 #endif // Z_EN_ZOS_H

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// Copyright (c) Lawrence Livermore National Security, LLC and other VisIt // Project developers. See the top-level LICENSE file for dates and other // details. No copyright assignment is required to contribute to VisIt. #include <CarpetHDF5PluginInfo.h> #include <avtCarpetHDF5FileFormat.h> #include <avtMTMDFileFormatInterface.h> #include <avtGenericDatabase.h> // **************************************************************************** // Method: CarpetHDF5CommonPluginInfo::GetDatabaseType // // Purpose: // Returns the type of a CarpetHDF5 database. // // Programmer: generated by xml2info // Creation: omitted // // **************************************************************************** DatabaseType CarpetHDF5CommonPluginInfo::GetDatabaseType() { return DB_TYPE_MTMD; } // **************************************************************************** // Method: CarpetHDF5CommonPluginInfo::SetupDatabase // // Purpose: // Sets up a CarpetHDF5 database. // // Arguments: // list A list of file names. // nList The number of timesteps in list. // nBlocks The number of blocks in the list. // // Returns: A CarpetHDF5 database from list. // // Programmer: generated by xml2info // Creation: omitted // // **************************************************************************** avtDatabase * CarpetHDF5CommonPluginInfo::SetupDatabase(const char *const *list, int nList, int nBlock) { // ignore any nBlocks past 1 // NOTE from Christian Reisswig: // Visit tries to be smart with grouping files together. // This feature is switched on by default in the file selector menu. // The effect is that Visit tries to open all bla.file_*.h5 files // and treats them as different timesteps! // To avoid this, we only open the first file by setting // nTimestepGroups = 1. int nTimestepGroups = 1; //nList / nBlock; avtMTMDFileFormat **ffl = new avtMTMDFileFormat*[nTimestepGroups]; for (int i = 0; i < nTimestepGroups; i++) { ffl[i] = new avtCarpetHDF5FileFormat(list[i*nBlock]); } avtMTMDFileFormatInterface *inter = new avtMTMDFileFormatInterface(ffl, nTimestepGroups); return new avtGenericDatabase(inter); }

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/buildroot/package/hifiberry-measurements/analyze/analyze.c

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analyze.c

// // analyze.c // // // Created by Joerg Schambacher on 6.11.2019 // i2Audio GmbH // #include <alsa/asoundlib.h> #include <stdio.h> #include <ctype.h> #include <string.h> #include <signal.h> #include <stdlib.h> #include <math.h> #include <limits.h> #include <fcntl.h> #include <sys/stat.h> #include <sys/types.h> #define NRM "\x1B[0m" #define RED "\x1B[31m" #define GRN "\x1B[32m" #define YEL "\x1B[33m" #define BLU "\x1B[34m" #define MAG "\x1B[35m" #define CYN "\x1B[36m" #define WHT "\x1B[37m" #define exp10(x) pow(10.0,x) #define sqr(x) ((x)*(x)) #define NOISEFLOOR (1e-15) #define dB(x) (20*log10((x)+NOISEFLOOR)) #define idB(x) (exp10(x/20.0)) #define printOK(...) do{printf(GRN); printf(__VA_ARGS__); printf(NRM);}while(0); #define printERR(...) do{printf(RED); printf(__VA_ARGS__); printf(NRM);}while(0); #define BIT_DEPTH 32 /* only 32 bit are supported for now */ #define MULTITONE 0 #define SWEEP 1 #define SINE 2 #define STEREO 0 #define LEFT 1 #define RIGHT 2 #define LOG_RESULTS(...) do {\ if(log_results) fprintf(LOGFILE, __VA_ARGS__); \ fflush(LOGFILE);\ } while (0) char filename[256] = "\0"; char logfilename[256] = "\0"; FILE *LOGFILE; unsigned int rate, channels, msecs, padding, mode; double *refmag, *refpha; /* reference FFT */ double *pcmmag, *pcmpha; /* single recording FFT */ double *resmag, *respha; /* summed FFT */ int *pcm; int vbw; unsigned fftsize; int numoptpts = 64; int verbose = 0; int log_results = 0; double fminswp = 20.0; double fmaxswp = 20000; void usage(char *name); int setoptions(int argc, char *argv[]); int fft_mono(int n,double *x,double *y); int read_ref_file(char *filename); int main(int argc, char *argv[]); void reduce_samples(void); int read_wave(char *filename, int *pcm); unsigned get_fftsize_of_wavfile(char *filename); void usage(char *name) { printf("usage:\n"); printf("%s [options] -r reference-file file1 file2 ...\n", name); printf("-n number of reduced FFT sample points \n"); printf("-r reference filename\n"); printf("-v verbosity level\n"); printf("\n"); exit(0); } int setoptions(int argc, char *argv[]) { int c; printf("HiFiBerry MultiFFT Tool V0.9 (c) 2019\n"); printf("=====================================\n"); if (argc == 1) usage(argv[0]); opterr = 0; while ((c = getopt (argc, argv, "n:r:hv:")) != -1) switch (c) { case 'v': verbose = atoi(optarg); break; case 'n': numoptpts = atoi(optarg); break; case 'r': strcpy(filename,optarg); break; case 'h': case '?': usage(argv[0]); return 1; default: usage(argv[0]); break; } if (optind < argc) return optind; return 0; } int fft_mono(int n,double *x,double *y) { unsigned m=log2(n),i,i1,j,k,i2,l,l1,l2; double c1,c2,tx,ty,t1,t2,u1,u2,z; i2 = n >> 1; j = 0; for (i=0;i<n-1;i++) { if (i < j) { tx = x[i]; ty = y[i]; x[i] = x[j]; y[i] = y[j]; x[j] = tx; y[j] = ty; } k = i2; while (k <= j) { j -= k; k >>= 1; } j += k; } c1 = -1.0; c2 = 0.0; l2 = 1; for (l=0;l<m;l++) { l1 = l2; l2 <<= 1; u1 = 1.0; u2 = 0.0; for (j=0;j<l1;j++) { for (i=j;i<n;i+=l2) { i1 = i + l1; t1 = u1 * x[i1] - u2 * y[i1]; t2 = u1 * y[i1] + u2 * x[i1]; x[i1] = x[i] - t1; y[i1] = y[i] - t2; x[i] += t1; y[i] += t2; } z = u1 * c1 - u2 * c2; u2 = u1 * c2 + u2 * c1; u1 = z; } c2 = sqrt((1.0 - c1) / 2.0); c2 = -c2; c1 = sqrt((1.0 + c1) / 2.0); } for (i=0;i<n;i++) { x[i] /= n>>1; y[i] /= n>>1; } return 0; } int read_ref_file(char *filename) { int i; read_wave(filename, pcm); /* do reference FFT */ double max = 0.0, tmp; for (i = 0; i < fftsize; i++){ refmag[i] = (double)pcm[i]; refpha[i] = 0; } fft_mono(fftsize, refmag, refpha); for (i = 0; i < fftsize/2; i++){ tmp = sqrt(sqr(refmag[i])+sqr(refpha[i])); refpha[i] = atan(refpha[i])/sqr(refmag[i]); refmag[i] = dB(tmp); if (refmag[i] > max) max = refmag[i]; } for (i = 0; i < fftsize/2; i++) refmag[i] -= max; #if 0 FILE *f; double freq = 0.0; f=fopen("fftdB.csv","w+"); for (i = 0; i < fftsize/2; i++){ freq = i*(double)rate/(double)fftsize; fprintf(f, "%.2f, %.1f, %f\n", freq, refmag[i], refpha[i]); } fclose(f); #endif return 0; } int process_wav_file(char *filename) { int i; static int notfirst; if (!notfirst) { /* first run */ if (verbose) printf("1st run: %s\n", filename); if (NULL==(pcmmag=malloc(fftsize*sizeof(double)))){ printERR("out of memory (pcmmag)\n"); exit(-1); } if (NULL==(pcmpha=malloc(fftsize*sizeof(double)))){ printERR("out of memory (pcmpha)\n"); exit(-1); } } else { if (verbose) printf("%i. run: %s\n", notfirst+1, filename); } /* do FFT */ read_wave(filename, pcm); double tmp; for (i = 0; i < fftsize; i++){ pcmmag[i] = (double)pcm[i]; pcmpha[i] = 0; } fft_mono(fftsize, pcmmag, pcmpha); for (i = 0; i < fftsize/2; i++){ tmp = sqrt(sqr(pcmmag[i])+sqr(pcmpha[i])); pcmpha[i] = atan(pcmpha[i])/sqr(pcmmag[i]); pcmmag[i] = tmp; } if (!notfirst) { /* first run */ for (i = 0; i < fftsize/2; i++) { resmag[i] = pcmmag[i]; respha[i] = pcmpha[i]; } } else { for (i = 0; i < fftsize/2; i++) { resmag[i] += pcmmag[i]; respha[i] += pcmpha[i]; resmag[i] /= 2; respha[i] /= 2; } } #if 0 FILE *f; double freq = 0.0; char buffer[32]; snprintf(buffer, 32, "fftdB_rec%i.csv", notfirst+1); f=fopen(buffer,"w+"); for (i = 0; i < fftsize/2; i++){ freq = i*(double)rate/(double)fftsize; fprintf(f, "%.2f, %.1f, %f\n", freq, dB(pcmmag[i]), pcmpha[i] * 180 / M_PI); } fclose(f); #endif notfirst++; return 0; } int main(int argc, char *argv[]) { int start, i; unsigned max; start = setoptions(argc, argv); if (!strlen(filename)) { printf("Error: reference file not given!\n"); usage(argv[0]); exit(0); } max = get_fftsize_of_wavfile(filename); /* reference file */ for (i = start; i < argc; i++) { /* test recordings */ fftsize = get_fftsize_of_wavfile(argv[i]); if (fftsize > max) max = fftsize; } fftsize = max; printf("allocating %i frames\n", fftsize); /* memory for reference FFT */ if (NULL == (refmag = malloc(fftsize * sizeof(double)))){ printERR("out of memory (refmag)\n"); exit(-1); } if (NULL == (refpha = malloc(fftsize * sizeof(double)))){ printERR("out of memory (refpha)\n"); exit(-1); } /* memory for reading files */ if(NULL == (pcm = malloc(fftsize * sizeof(int)))){ printERR("out of memory (pcmmag)!\n"); exit(-1); } /* memory for recording FFT(s) */ if(NULL == (pcmmag = malloc(fftsize * sizeof(double)))){ printERR("out of memory (pcmmag)!\n"); exit(-1); } if(NULL == (pcmpha = malloc(fftsize * sizeof(double)))){ printERR("out of memory (pcmpha)!\n"); exit(-1); } /* memory for summed FFT */ if(NULL == (resmag = malloc(fftsize * sizeof(double)))){ printERR("out of memory (resmag)!\n"); exit(-1); } bzero(resmag, fftsize); if(NULL == (respha = malloc(fftsize * sizeof(double)))){ printERR("out of memory (respha)!\n"); exit(-1); } bzero(respha, fftsize); read_ref_file(filename); while(0 == access(argv[start], 0)) { printf("processing %s\n", argv[start]); process_wav_file(argv[start]); start++; } reduce_samples(); printf("done.\n"); return 0; } void reduce_samples(void) { int i, j, cnt; double *res, *fr, *pha; if(NULL ==(res = malloc(numoptpts * sizeof(double)))){ printERR("out of memory!\n"); return; } if(NULL ==(pha = malloc(numoptpts * sizeof(double)))){ printERR("out of memory!\n"); return; } if(NULL ==(fr = malloc(numoptpts * sizeof(double)))){ printERR("out of memory!\n"); return; } double bit_scale = powf(2,31); for(i = 0; i < fftsize/2; i++) { resmag[i] = dB(resmag[i] / bit_scale); resmag[i] -= refmag[i]; respha[i] -= refpha[i]; } double fend; double x = pow(fmaxswp / fminswp, 1.0/(double)numoptpts); double vbw = (double)rate/((double)fftsize); // printf("fftsize %i, VBW %6.1f\n", fftsize, vbw); for(i = 0; i < numoptpts; i++){ fr[i] = fminswp * pow(x, i); fend = fminswp * pow(x, i+1); if (verbose > 0) printf("averaging from %f.2 to %.2f\n", fr[i], fend); res[i] = 0.0; pha[i] = 0.0; cnt = 0; j = (int) (fr[i]/vbw + 0.5); while (j * vbw < fend && j < fftsize / 2) { res[i] += resmag[j]; pha[i] += respha[j]; j++; cnt++; } res[i] /= cnt; pha[i] /= cnt / 180.0 * M_PI; fr[i] = (fend - fr[i]) / log( fend / fr[i]); /* take the log average */ } FILE *f; f=fopen("fftdB_vbw.csv","w+"); for (i = 0; i < numoptpts; i++){ fprintf(f, "%f, %.2f, %.5f\n", fr[i], res[i], pha[i]); } fclose(f); } int read_wave(char *filename, int *pcm) { int fd, tmp, len; struct struct_wavheader{ char riff[4]; unsigned filesize; char wave[4]; char fmt[4]; int fmtlen; short fmttype; short channels; int samplerate; int bytespersec; short framesize; short bitspersample; char data[4]; unsigned datasize; }wavheader; if (-1 == (fd=open(filename,O_RDONLY))) { printf("open error %s (%i)\n",filename,fd); exit(-1); } if ((tmp = read(fd, &wavheader, sizeof(wavheader))) != sizeof(wavheader)) { printERR("read error %s (%i bytes read)\n",filename,tmp); exit(-1); } if (verbose > 1) { printf("file info: riff %4s wave %4s\n", wavheader.riff, wavheader.wave); printf("file info: %i channels %ibit @ %isps\n", wavheader.channels, wavheader.bitspersample, wavheader.samplerate); printf("file info: %i bytes/sec %i framesize @ %i fmtlen\n", wavheader.bytespersec, wavheader.framesize, wavheader.fmtlen); printf("filesize %i bytes\n",wavheader.filesize); printf("datasize %i bytes\n",wavheader.datasize); } if (wavheader.channels != 1 || wavheader.bitspersample != 32) { printERR("WAV file has wrong format!\nOnly 1 channel 32bit supported.\n"); exit(-1); } rate = wavheader.samplerate; len = wavheader.filesize + 8 - 44; bzero(pcm, fftsize); if ((tmp = read(fd, pcm, len)) != len) { printERR("read error %i bytes read instead of %i\n",tmp,len); exit(-1); } if (verbose > 1) { printOK("%i bytes of data read.\n", tmp); printOK("%i frames = %usecs\n", tmp/4, tmp/(4*wavheader.samplerate)); } close(fd); return 0; } unsigned get_fftsize_of_wavfile(char *filename) { int fd, tmp, len; struct struct_wavheader{ char riff[4]; unsigned filesize; char wave[4]; char fmt[4]; int fmtlen; short fmttype; short channels; int samplerate; int bytespersec; short framesize; short bitspersample; char data[4]; unsigned datasize; }wavheader; if (access(filename, 0)) { printERR("file not found: %s\n",filename); return 0; } if (-1 == (fd=open(filename,O_RDONLY))) { printERR("open error %s (%i)\n",filename,fd); return 0; } if ((tmp = read(fd, &wavheader, sizeof(wavheader))) != sizeof(wavheader)) { printERR("read error %s (%i bytes read)\n",filename,tmp); return 0; } if (wavheader.channels != 1 || wavheader.bitspersample != 32) { printERR("WAV file has wrong format!\nOnly 1 channel 32bit supported.\n"); return 0; } len = wavheader.filesize + 8 - 44; if (verbose > 1) printf("%i frames in file %s\n", len / 4, filename); return (unsigned)exp2(ceil(log2(len / 4))); }

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/ext/phalcon/html/link/interfaces/evolvablelinkinterface.zep.c

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phalcon/cphalcon

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evolvablelinkinterface.zep.c

#ifdef HAVE_CONFIG_H #include "../../../../ext_config.h" #endif #include <php.h> #include "../../../../php_ext.h" #include "../../../../ext.h" #include <Zend/zend_exceptions.h> #include "kernel/main.h" /** * This file is part of the Phalcon Framework. * * (c) Phalcon Team <team@phalcon.io> * * For the full copyright and license information, please view the LICENSE.txt * file that was distributed with this source code. */ /** * An evolvable link value object. */ ZEPHIR_INIT_CLASS(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface) { ZEPHIR_REGISTER_INTERFACE(Phalcon\\Html\\Link\\Interfaces, EvolvableLinkInterface, phalcon, html_link_interfaces_evolvablelinkinterface, phalcon_html_link_interfaces_evolvablelinkinterface_method_entry); zend_class_implements(phalcon_html_link_interfaces_evolvablelinkinterface_ce, 1, phalcon_html_link_interfaces_linkinterface_ce); return SUCCESS; } /** * Returns an instance with the specified href. * * @param string $href * The href value to include. It must be one of: * - An absolute URI, as defined by RFC 5988. * - A relative URI, as defined by RFC 5988. The base of the relative * link is assumed to be known based on context by the client. * - A URI template as defined by RFC 6570. * - An object implementing __toString() that produces one of the * above values. * * An implementing library SHOULD evaluate a passed object to a string * immediately rather than waiting for it to be returned later. */ ZEPHIR_DOC_METHOD(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface, withHref); /** * Returns an instance with the specified relationship included. * * If the specified rel is already present, this method MUST return * normally without errors, but without adding the rel a second time. * * @param string $rel The relationship value to add. */ ZEPHIR_DOC_METHOD(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface, withRel); /** * Returns an instance with the specified relationship excluded. * * If the specified rel is already not present, this method MUST return * normally without errors. * * @param string $rel The relationship value to exclude. */ ZEPHIR_DOC_METHOD(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface, withoutRel); /** * Returns an instance with the specified attribute added. * * If the specified attribute is already present, it will be overwritten * with the new value. * * @param string $attribute The attribute to include. * @param string $value The value of the attribute to set. */ ZEPHIR_DOC_METHOD(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface, withAttribute); /** * Returns an instance with the specified attribute excluded. * * If the specified attribute is not present, this method MUST return * normally without errors. * * @param string $attribute The attribute to remove. */ ZEPHIR_DOC_METHOD(Phalcon_Html_Link_Interfaces_EvolvableLinkInterface, withoutAttribute);

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/lib-usb/src/h3/ft245rl.c

7959845d60b623e91b0369489121a4f94979ed66

[ "MIT" ]

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vanvught/rpidmx512

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ft245rl.c

/** * @file ft245rl.c * * @brief Interface for FT245RL * * Orange Pi * P1:H3 PIO_PA FT245RL * * 3:GPIO12 <---> D0 * 5:GPIO11 <---> D1 * 7:GPIO06 <---> D2 * 26:GPIO10 <---> D3 * 24:GPIO13 <---> D4 * 21:GPIO16 <---> D5 * 19:GPIO15 <---> D6 * 23:GPIO14 <---> D7 * * 15:GPIO03 ----> WR * 16:GPIO19 ----> RD# * * 18:GPIO18 <---- TXE# * 22:GPIO02 <---- RXF# * */ /* Copyright (C) 2018 by Arjan van Vught mailto:info@orangepi-dmx.nl * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdint.h> #include <stdbool.h> #include "h3_gpio.h" #include "h3.h" // PIO PA 6 10 11 12 13 14 15 16 #define D0 12 // CFG1 #define D1 11 // CFG1 #define D2 6 // CFG0 #define D3 10 // CFG1 #define D4 13 // CFG1 #define D5 16 // CFG2 #define D6 15 // CFG1 #define D7 14 // CFG1 #define WR 3 // CFG0 #define _RD 19 // CFG2 #define _TXE 18 // CFG2 #define _RXF 2 // CFG0 #define NOP_COUNT_READ 24 #define NOP_COUNT_WRITE 2 /** * Set the GPIOs for data to output */ static void data_gpio_fsel_output() { uint32_t value = H3_PIO_PORTA->CFG0; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA6_SELECT_CFG0_SHIFT); // D2 value |= (GPIO_FSEL_OUTPUT << PA6_SELECT_CFG0_SHIFT); H3_PIO_PORTA->CFG0 = value; value = H3_PIO_PORTA->CFG1; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA12_SELECT_CFG1_SHIFT); // D0 value |= (GPIO_FSEL_OUTPUT << PA12_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA11_SELECT_CFG1_SHIFT); // D1 value |= (GPIO_FSEL_OUTPUT << PA11_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA10_SELECT_CFG1_SHIFT); // D3 value |= (GPIO_FSEL_OUTPUT << PA10_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA13_SELECT_CFG1_SHIFT); // D4 value |= (GPIO_FSEL_OUTPUT << PA13_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA15_SELECT_CFG1_SHIFT); // D6 value |= (GPIO_FSEL_OUTPUT << PA15_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA14_SELECT_CFG1_SHIFT); // D7 value |= (GPIO_FSEL_OUTPUT << PA14_SELECT_CFG1_SHIFT); H3_PIO_PORTA->CFG1 = value; value = H3_PIO_PORTA->CFG2; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA16_SELECT_CFG2_SHIFT); // D5 value |= (GPIO_FSEL_OUTPUT << PA16_SELECT_CFG2_SHIFT); H3_PIO_PORTA->CFG2 = value; } /** * Set the GPIOs for data to input */ static void data_gpio_fsel_input() { uint32_t value = H3_PIO_PORTA->CFG0; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA6_SELECT_CFG0_SHIFT); // D2 value |= (GPIO_FSEL_INPUT << PA6_SELECT_CFG0_SHIFT); H3_PIO_PORTA->CFG0 = value; value = H3_PIO_PORTA->CFG1; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA12_SELECT_CFG1_SHIFT); // D0 value |= (GPIO_FSEL_INPUT << PA12_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA11_SELECT_CFG1_SHIFT); // D1 value |= (GPIO_FSEL_INPUT << PA11_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA10_SELECT_CFG1_SHIFT); // D3 value |= (GPIO_FSEL_INPUT << PA10_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA13_SELECT_CFG1_SHIFT); // D4 value |= (GPIO_FSEL_INPUT << PA13_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA15_SELECT_CFG1_SHIFT); // D6 value |= (GPIO_FSEL_INPUT << PA15_SELECT_CFG1_SHIFT); value &= (uint32_t) ~(GPIO_SELECT_MASK << PA14_SELECT_CFG1_SHIFT); // D7 value |= (GPIO_FSEL_INPUT << PA14_SELECT_CFG1_SHIFT); H3_PIO_PORTA->CFG1 = value; value = H3_PIO_PORTA->CFG2; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA16_SELECT_CFG2_SHIFT); // D5 value |= (GPIO_FSEL_INPUT << PA16_SELECT_CFG2_SHIFT); H3_PIO_PORTA->CFG2 = value; } /** * Set RD#, WR to output, TXE#, RXF# to input. * Set RD# to high, set WR to low */ void FT245RL_init(void) { // RD#, WR output uint32_t value = H3_PIO_PORTA->CFG0; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA3_SELECT_CFG0_SHIFT); // WR value |= (GPIO_FSEL_OUTPUT << PA3_SELECT_CFG0_SHIFT); H3_PIO_PORTA->CFG0 = value; value = H3_PIO_PORTA->CFG2; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA19_SELECT_CFG2_SHIFT); // RD# value |= (GPIO_FSEL_OUTPUT << PA19_SELECT_CFG2_SHIFT); H3_PIO_PORTA->CFG2 = value; // TXE#, RXF# input value = H3_PIO_PORTA->CFG0; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA2_SELECT_CFG0_SHIFT); // RXF# value |= (GPIO_FSEL_INPUT << PA2_SELECT_CFG0_SHIFT); H3_PIO_PORTA->CFG0 = value; value = H3_PIO_PORTA->CFG2; value &= (uint32_t) ~(GPIO_SELECT_MASK << PA18_SELECT_CFG2_SHIFT); // TXE# value |= (GPIO_FSEL_INPUT << PA18_SELECT_CFG2_SHIFT); H3_PIO_PORTA->CFG2 = value; // RD# high h3_gpio_set(_RD); // WR low h3_gpio_clr(WR); } /** * Write 8-bits to USB */ void FT245RL_write_data(uint8_t data) { uint8_t i; data_gpio_fsel_output(); // Raise WR to start the write. h3_gpio_set(WR); i = NOP_COUNT_WRITE; for (; i > 0; i--) { asm volatile("nop"::); } // Put the data on the bus. uint32_t out_gpio = H3_PIO_PORTA->DAT & (uint32_t)~( (1 << D0) | (1 << D1) | (1 << D2) | (1 << D3) | (1 << D4) | (1 << D5) | (1 << D6) | (1 << D7)); out_gpio |= (data & 1) ? (1 << D0) : 0; out_gpio |= (data & 2) ? (1 << D1) : 0; out_gpio |= (data & 4) ? (1 << D2) : 0; out_gpio |= (data & 8) ? (1 << D3) : 0; out_gpio |= (data & 16) ? (1 << D4) : 0; out_gpio |= (data & 32) ? (1 << D5) : 0; out_gpio |= (data & 64) ? (1 << D6) : 0; out_gpio |= (data & 128) ? (1 << D7) : 0; H3_PIO_PORTA->DAT = out_gpio; i = NOP_COUNT_WRITE; for (; i > 0; i--) { asm volatile("nop"::); } // Drop WR to tell the FT245 to read the data. h3_gpio_clr(WR); } /** * Read 8-bits from USB */ uint8_t FT245RL_read_data() { data_gpio_fsel_input(); h3_gpio_clr(_RD); // Wait for the FT245 to respond with data. uint8_t i = NOP_COUNT_READ; for (; i > 0; i--) { asm volatile("nop"::); } // Read the data from the data port. const uint32_t in_gpio = H3_PIO_PORTA->DAT; uint8_t data = (uint8_t)(((in_gpio & (1U << D0)) ? 1 : 0) | ((in_gpio & (1U << D1)) ? 2 : 0) | ((in_gpio & (1U << D2)) ? 4 : 0) | ((in_gpio & (1U << D3)) ? 8 : 0) | ((in_gpio & (1U << D4)) ? 16 : 0) | ((in_gpio & (1U << D5)) ? 32 : 0) | ((in_gpio & (1U << D6)) ? 64 : 0) | ((in_gpio & (1U << D7)) ? 128 : 0)); // Bring RD# back up so the FT245 can let go of the data. h3_gpio_set(_RD); return data; } /** * Read RXF# */ bool FT245RL_data_available(void) { return (!(H3_PIO_PORTA->DAT & (1 << _RXF))); } /** * Read TXE# */ bool FT245RL_can_write(void) { return (!(H3_PIO_PORTA->DAT & (1 << _TXE))); }

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/src/game/bossfile.c

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n64decomp/perfect_dark

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bossfile.c

#include <ultra64.h> #include "constants.h" #include "constants.h" #include "game/camdraw.h" #include "game/cheats.h" #include "game/lang.h" #include "game/player.h" #include "game/savebuffer.h" #include "game/bossfile.h" #include "game/bg.h" #include "game/challenge.h" #include "game/training.h" #include "game/gamefile.h" #include "game/mplayer/mplayer.h" #include "game/pak.h" #include "game/options.h" #include "game/utils.h" #include "bss.h" #include "lib/fault.h" #include "lib/snd.h" #include "data.h" #include "types.h" u8 var800a22d0[0x5b]; u8 g_AltTitleUnlocked; u8 g_AltTitleEnabled; void bossfileSetDefaults2(void) { bossfileSetDefaults(); } void bossfileSetAndSaveDefaults(void) { bossfileSetDefaults(); bossfileSave(); } bool bossfileLoadFull(void) { bossfileLoad(); #if VERSION >= VERSION_PAL_BETA langSetEuropean(g_Vars.language); #endif return true; } void func0f1106ec(void) { // empty } void func0f1106f4(u8 *dst) { bcopy(var800a22d0, dst, sizeof(var800a22d0)); } u32 bossfileFindFileId(void) { struct pakfileheader header; u32 fileids[513]; u32 candidate = 0; s32 i; if (pakGetFileIdsByType(SAVEDEVICE_GAMEPAK, PAKFILETYPE_BOSS, fileids) == 0) { for (i = 0; fileids[i] != 0; i++) { pakFindFile(SAVEDEVICE_GAMEPAK, fileids[i], &header); if (!header.occupied) { candidate = fileids[i]; break; } } for (i = 0; fileids[i] != 0; i++) { pakFindFile(SAVEDEVICE_GAMEPAK, fileids[i], &header); if (header.occupied) { candidate = fileids[i]; break; } } } return candidate; } void bossfileLoad(void) { bool failed = false; struct savebuffer buffer; s32 i; s32 fileid; struct fileguid guid; fileid = bossfileFindFileId(); if (fileid == 0) { failed = true; } else { savebufferClear(&buffer); if (pakReadBodyAtGuid(SAVEDEVICE_GAMEPAK, fileid, buffer.bytes, 0) != 0) { failed = true; } } if (!failed) { u8 tracknum; savebufferReadGuid(&buffer, &guid); g_Vars.bossfileid = guid.fileid; g_Vars.bossdeviceserial = guid.deviceserial; g_BossFile.unk89 = savebufferReadBits(&buffer, 1); g_Vars.language = savebufferReadBits(&buffer, 4); for (i = 0; i < ARRAYCOUNT(g_BossFile.teamnames); i++) { savebufferReadString(&buffer, g_BossFile.teamnames[i], 1); } tracknum = savebufferReadBits(&buffer, 8); if (tracknum == 0xff) { g_BossFile.tracknum = -1; } else { g_BossFile.tracknum = tracknum; } for (i = 0; i < ARRAYCOUNT(g_BossFile.multipletracknums); i++) { g_BossFile.multipletracknums[i] = savebufferReadBits(&buffer, 8); } g_BossFile.usingmultipletunes = savebufferReadBits(&buffer, 1); g_AltTitleUnlocked = savebufferReadBits(&buffer, 1); g_AltTitleEnabled = savebufferReadBits(&buffer, 1); func0f0d54c4(&buffer); } if (failed) { bossfileSetDefaults(); bossfileSave(); } } void bossfileSave(void) { volatile bool sp12c = false; struct savebuffer buffer; struct fileguid guid; u32 stack; s32 i; s32 fileid; savebufferClear(&buffer); guid.fileid = g_Vars.bossfileid; guid.deviceserial = g_Vars.bossdeviceserial; savebufferWriteGuid(&buffer, &guid); savebufferOr(&buffer, g_BossFile.unk89, 1); savebufferOr(&buffer, g_Vars.language, 4); for (i = 0; i < ARRAYCOUNT(g_BossFile.teamnames); i++) { func0f0d55a4(&buffer, g_BossFile.teamnames[i]); } if (g_BossFile.tracknum == -1) { savebufferOr(&buffer, 0xff, 8); } else { savebufferOr(&buffer, g_BossFile.tracknum, 8); } for (i = 0; i < ARRAYCOUNT(g_BossFile.multipletracknums); i++) { savebufferOr(&buffer, g_BossFile.multipletracknums[i], 8); } savebufferOr(&buffer, g_BossFile.usingmultipletunes, 1); savebufferOr(&buffer, g_AltTitleUnlocked, 1); savebufferOr(&buffer, g_AltTitleEnabled, 1); func0f0d54c4(&buffer); fileid = bossfileFindFileId(); if (fileid == 0) { faultAssert("fileGuid", "bossfile.c", VERSION >= VERSION_PAL_BETA ? 377 : 375); } if (pakSaveAtGuid(SAVEDEVICE_GAMEPAK, fileid, PAKFILETYPE_BOSS, buffer.bytes, NULL, 0) != 0) { sp12c = true; } } void bossfileSetDefaults(void) { g_BossFile.teamnames[0][0] = '\0'; g_BossFile.teamnames[1][0] = '\0'; g_BossFile.teamnames[2][0] = '\0'; g_BossFile.teamnames[3][0] = '\0'; g_BossFile.teamnames[4][0] = '\0'; g_BossFile.teamnames[5][0] = '\0'; g_BossFile.teamnames[6][0] = '\0'; g_BossFile.teamnames[7][0] = '\0'; g_BossFile.tracknum = -1; mpEnableAllMultiTracks(); g_BossFile.usingmultipletunes = false; g_BossFile.unk89 = 0; g_BossFile.locktype = MPLOCKTYPE_NONE; g_Vars.bossfileid = 0; g_Vars.bossdeviceserial = 0; g_Vars.language = (PAL ? 7 : 0); g_AltTitleUnlocked = 0; g_AltTitleEnabled = false; bossfileSave(); }

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/third_party/virtualbox/src/VBox/Devices/PC/ipxe/src/arch/i386/firmware/pcbios/pnpbios.c

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thalium/icebox

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pnpbios.c

/* * Copyright (C) 2007 Michael Brown <mbrown@fensystems.co.uk>. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ FILE_LICENCE ( GPL2_OR_LATER ); #include <stdint.h> #include <string.h> #include <errno.h> #include <realmode.h> #include <pnpbios.h> /** @file * * PnP BIOS * */ /** PnP BIOS structure */ struct pnp_bios { /** Signature * * Must be equal to @c PNP_BIOS_SIGNATURE */ uint32_t signature; /** Version as BCD (e.g. 1.0 is 0x10) */ uint8_t version; /** Length of this structure */ uint8_t length; /** System capabilities */ uint16_t control; /** Checksum */ uint8_t checksum; } __attribute__ (( packed )); /** Signature for a PnP BIOS structure */ #define PNP_BIOS_SIGNATURE \ ( ( '$' << 0 ) + ( 'P' << 8 ) + ( 'n' << 16 ) + ( 'P' << 24 ) ) /** * Test address for PnP BIOS structure * * @v offset Offset within BIOS segment to test * @ret rc Return status code */ static int is_pnp_bios ( unsigned int offset ) { union { struct pnp_bios pnp_bios; uint8_t bytes[256]; /* 256 is maximum length possible */ } u; size_t len; unsigned int i; uint8_t sum = 0; /* Read start of header and verify signature */ copy_from_real ( &u.pnp_bios, BIOS_SEG, offset, sizeof ( u.pnp_bios )); if ( u.pnp_bios.signature != PNP_BIOS_SIGNATURE ) return -EINVAL; /* Read whole header and verify checksum */ len = u.pnp_bios.length; copy_from_real ( &u.bytes, BIOS_SEG, offset, len ); for ( i = 0 ; i < len ; i++ ) { sum += u.bytes[i]; } if ( sum != 0 ) return -EINVAL; DBG ( "Found PnP BIOS at %04x:%04x\n", BIOS_SEG, offset ); return 0; } /** * Locate Plug-and-Play BIOS * * @ret pnp_offset Offset of PnP BIOS structure within BIOS segment * * The PnP BIOS structure will be at BIOS_SEG:pnp_offset. If no PnP * BIOS is found, -1 is returned. */ int find_pnp_bios ( void ) { static int pnp_offset = 0; if ( pnp_offset ) return pnp_offset; for ( pnp_offset = 0 ; pnp_offset < 0x10000 ; pnp_offset += 0x10 ) { if ( is_pnp_bios ( pnp_offset ) == 0 ) return pnp_offset; } pnp_offset = -1; return pnp_offset; }

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/CondTools/Ecal/interface/EcalIntercalibConstantsMCXMLTranslator.h

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/** Translates a EcalIntercalibConstantsMC record to XML and vice versa \author Stefano ARGIRO \version $Id: EcalIntercalibConstantsMCXMLTranslator.h,v 1.3 2009/06/30 16:15:16 argiro Exp $ \date 20 Jun 2008 */ #ifndef __EcalIntercalibConstantsMCXMLTranslator_h_ #define __EcalIntercalibConstantsMCXMLTranslator_h_ #include "CondTools/Ecal/interface/EcalFloatCondObjectContainerXMLTranslator.h" typedef EcalFloatCondObjectContainerXMLTranslator EcalIntercalibConstantsMCXMLTranslator; #endif // __EcalIntercalibConstantsMCXMLTranslator_h_

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/released_plugins/v3d_plugins/neurontracing_neutube/src_neutube/neurolabi/c/testscalarfield.c

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Vaa3D/vaa3d_tools

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/* testscalarfield.c * * 27-Apr-2008 Initial write: Ting Zhao */ #include <stdio.h> #include <image_lib.h> #include "tz_constant.h" #include "tz_stack_draw.h" #include "tz_local_neuroseg.h" #include "tz_bifold_neuroseg.h" #include "tz_stack_stat.h" #include "tz_farray.h" #include "tz_geo3d_point_array.h" #include "tz_geo3d_scalar_field.h" #include "tz_stack_bwmorph.h" #include "tz_darray.h" int main() { #if 0 /* Make a label stack */ Stack *stack = Make_Stack(FLOAT32, 100, 100, 50); Zero_Stack(stack); #endif #if 0 /* Make test neuron segment */ Local_Neuroseg *locseg = New_Local_Neuroseg(); Set_Local_Neuroseg(locseg, 1, 2, 24, 0, 0, NEUROSEG_MAX_CURVATURE, 50, 50, 25); Print_Local_Neuroseg(locseg); /* Generate field */ Geo3d_Scalar_Field *field = Local_Neuroseg_Field_S(locseg, 1.0, NULL); //Print_Geo3d_Scalar_Field(field); Delete_Local_Neuroseg(locseg); #endif #if 0 /* Make bifold neuron segment */ Bifold_Neuroseg *bn = New_Bifold_Neuroseg(); Set_Bifold_Neuroseg(bn, 2, 2, 2, 2, 24, 0.5, 1, 1, 1, 0); /* Generate field */ Geo3d_Scalar_Field *field = Bifold_Neuroseg_Field(bn, 1.0, NULL); Geo3d_Scalar_Field_Translate(field, 50, 50, 25); Delete_Bifold_Neuroseg(bn); #endif #if 0 //Print_Geo3d_Scalar_Field(field); /* Draw it in a stack */ double coef[] = {0.1, 1000.0}; double range[] = {0.0, 10000.0}; Geo3d_Scalar_Field_Draw_Stack(field, stack, coef, range); int idx; printf("%g\n", Stack_Max(stack, &idx, NULL)); /* Turn the stack to GREY type */ Translate_Stack(stack, GREY, 1); printf("%g\n", Stack_Max(stack, &idx, NULL)); /* Make canvas */ Stack *canvas = Make_Stack(COLOR, stack->width, stack->height, stack->depth); Zero_Stack(canvas); /* Label the canvas */ Stack_Label_Color(canvas, stack, 5.0, 1.0, stack); /* Save the stack */ Write_Stack("../data/test.tif", canvas); /* clean up */ Kill_Geo3d_Scalar_Field(field); Kill_Stack(stack); Kill_Stack(canvas); #endif #if 0 Geo3d_Scalar_Field *field = Read_Geo3d_Scalar_Field("../data/diadem_e3/seeds"); Print_Geo3d_Scalar_Field(field); Geo3d_Scalar_Field_Export_V3d_Marker(field, "../data/test.marker"); #endif #if 0 Stack_Fit_Score fs; fs.n = 2; fs.scores[0] = 0.5; fs.options[0] = 1; fs.scores[1] = 110.5; fs.options[1] = 0; Print_Stack_Fit_Score(&fs); /* FILE *fp = fopen("../data/test.bn", "w"); Stack_Fit_Score_Fwrite(&fs, fp); fclose(fp); */ Stack_Fit_Score fs2; FILE *fp2 = fopen("../data/test.bn", "r"); Stack_Fit_Score_Fread(&fs2, fp2); fclose(fp2); Print_Stack_Fit_Score(&fs2); #endif #if 0 Geo3d_Scalar_Field *field = Geo3d_Scalar_Field_Import_Apo("/Users/zhaot/Data/jinny/edswc_A copy/edswc_A0002.swc.apo"); Print_Geo3d_Scalar_Field(field); #endif #if 0 Geo3d_Ball *ball = New_Geo3d_Ball(); ball->r = 3.0; Stack *stack = Make_Stack(GREY, 100, 100, 100); One_Stack(stack); int i, j, k; int offset = 0; for (k = 0; k < stack->depth; k++) { for (j = 0; j < stack->height; j++) { for (i = 0; i < stack->width; i++) { if ((i == 0) || (j == 0) || (k == 0) || (i == stack->width-1) || (j == stack->height-1) || (k == stack->depth - 1)) { stack->array[offset] = 0; } offset++; } } } Stack *distmap = Stack_Bwdist_L_U16(stack, NULL, 0); tic(); Geo3d_Ball_Mean_Shift(ball, distmap, 1.0, 0.5); printf("%llu\n", toc()); Print_Geo3d_Ball(ball); #endif #if 0 Geo3d_Scalar_Field *field1 = Make_Geo3d_Scalar_Field(3); Set_Coordinate_3d(field1->points[0], 1, 1, 1); Set_Coordinate_3d(field1->points[1], 2, 2, 2); Set_Coordinate_3d(field1->points[2], 3, 3, 3); field1->values[0] = 1; field1->values[1] = 2; field1->values[2] = 3; Geo3d_Scalar_Field *field2 = Make_Geo3d_Scalar_Field(3); Set_Coordinate_3d(field2->points[0], 4, 4, 4); Set_Coordinate_3d(field2->points[1], 5, 5, 5); Set_Coordinate_3d(field2->points[2], 6, 6, 6); field2->values[0] = 4; field2->values[1] = 5; field2->values[2] = 6; Print_Geo3d_Scalar_Field(field1); Print_Geo3d_Scalar_Field(field2); Geo3d_Scalar_Field *field = Make_Geo3d_Scalar_Field(2); Geo3d_Scalar_Field_Merge(field1, field2, field); Print_Geo3d_Scalar_Field(field); #endif #if 1 Geo3d_Scalar_Field *field1 = Make_Geo3d_Scalar_Field(6); Set_Coordinate_3d(field1->points[0], 1, 1, 1); Set_Coordinate_3d(field1->points[1], 2, 4, 2); Set_Coordinate_3d(field1->points[2], 3, 3, 8); Set_Coordinate_3d(field1->points[3], 8, 4, 4); Set_Coordinate_3d(field1->points[4], 3, 5, 5); Set_Coordinate_3d(field1->points[5], 6, 7, 9); field1->values[0] = 1; field1->values[1] = 1; field1->values[2] = 1; field1->values[3] = 1; field1->values[4] = 1; field1->values[5] = 1; double vec[9]; double value[3]; Geo3d_Scalar_Field_Pca(field1, value, vec); darray_print2(vec, 3, 3); darray_print2(value, 3, 1); #endif return 0; }

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/Code_source/Compiled/signal/pulsediv~.c

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pulsediv~.c

// Porres 2017 #include "m_pd.h" #include <math.h> static t_class *pulsediv_class; typedef struct _pulsediv{ t_object x_obj; t_float x_div; t_float x_count; t_float x_start; t_float x_lastin; t_int x_mod; t_inlet *x_triglet; t_outlet *x_outlet_0; t_outlet *x_outlet_1; }t_pulsediv; static void pulsediv_div(t_pulsediv *x, t_floatarg f){ x->x_div = f < 1 ? 1 : f; } static void pulsediv_start(t_pulsediv *x, t_floatarg f){ x->x_start = f; } static t_int *pulsediv_perform(t_int *w){ t_pulsediv *x = (t_pulsediv *)(w[1]); int nblock = (t_int)(w[2]); t_float *in1 = (t_float *)(w[3]); t_float *in2 = (t_float *)(w[4]); t_float *out1 = (t_float *)(w[5]); t_float *out2 = (t_float *)(w[6]); t_float lastin = x->x_lastin; t_float start = x->x_start; t_float div = x->x_div; t_float count = x->x_count; while (nblock--){ t_float in = *in1++; t_float trig = *in2++; t_float pulse; if(trig > 0) count = start; count += (pulse = (in > 0 && lastin <= 0)); if (count >= 0) count = fmod(count, div); *out1++ = pulse && count == 0; *out2++ = pulse && count != 0; lastin = in; } x->x_lastin = lastin; x->x_count = count; return (w + 7); } static void pulsediv_dsp(t_pulsediv *x, t_signal **sp){ dsp_add(pulsediv_perform, 6, x, sp[0]->s_n, sp[0]->s_vec, sp[1]->s_vec, sp[2]->s_vec, sp[3]->s_vec); } static void *pulsediv_free(t_pulsediv *x){ inlet_free(x->x_triglet); outlet_free(x->x_outlet_0); outlet_free(x->x_outlet_1); return (void *)x; } static void *pulsediv_new(t_floatarg f1, t_floatarg f2){ t_pulsediv *x = (t_pulsediv *)pd_new(pulsediv_class); x->x_lastin = 1; x->x_div = f1 < 1 ? 1 : f1; x->x_start = x->x_count = f2 - 1; x->x_triglet = inlet_new((t_object *)x, (t_pd *)x, &s_signal, &s_signal); x->x_outlet_0 = outlet_new(&x->x_obj, &s_signal); x->x_outlet_1 = outlet_new(&x->x_obj, &s_signal); return (x); } void pulsediv_tilde_setup(void){ pulsediv_class = class_new(gensym("pulsediv~"), (t_newmethod)pulsediv_new, (t_method)pulsediv_free, sizeof(t_pulsediv), 0, A_DEFFLOAT, A_DEFFLOAT, 0); class_addmethod(pulsediv_class, nullfn, gensym("signal"), 0); class_addmethod(pulsediv_class, (t_method) pulsediv_dsp, gensym("dsp"), A_CANT, 0); class_addmethod(pulsediv_class, (t_method)pulsediv_div, gensym("div"), A_DEFFLOAT, 0); class_addmethod(pulsediv_class, (t_method)pulsediv_start, gensym("start"), A_DEFFLOAT, 0); }

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/SOFTWARE/A64-TERES/linux-a64/sound/pci/rme96.c

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/* * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio * interfaces * * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> * * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control * code. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #include <linux/delay.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/module.h> #include <sound/core.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/asoundef.h> #include <sound/initval.h> #include <asm/io.h> /* note, two last pcis should be equal, it is not a bug */ MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " "Digi96/8 PAD"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," "{RME,Digi96/8}," "{RME,Digi96/8 PRO}," "{RME,Digi96/8 PST}," "{RME,Digi96/8 PAD}}"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); /* * Defines for RME Digi96 series, from internal RME reference documents * dated 12.01.00 */ #define RME96_SPDIF_NCHANNELS 2 /* Playback and capture buffer size */ #define RME96_BUFFER_SIZE 0x10000 /* IO area size */ #define RME96_IO_SIZE 0x60000 /* IO area offsets */ #define RME96_IO_PLAY_BUFFER 0x0 #define RME96_IO_REC_BUFFER 0x10000 #define RME96_IO_CONTROL_REGISTER 0x20000 #define RME96_IO_ADDITIONAL_REG 0x20004 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C #define RME96_IO_SET_PLAY_POS 0x40000 #define RME96_IO_RESET_PLAY_POS 0x4FFFC #define RME96_IO_SET_REC_POS 0x50000 #define RME96_IO_RESET_REC_POS 0x5FFFC #define RME96_IO_GET_PLAY_POS 0x20000 #define RME96_IO_GET_REC_POS 0x30000 /* Write control register bits */ #define RME96_WCR_START (1 << 0) #define RME96_WCR_START_2 (1 << 1) #define RME96_WCR_GAIN_0 (1 << 2) #define RME96_WCR_GAIN_1 (1 << 3) #define RME96_WCR_MODE24 (1 << 4) #define RME96_WCR_MODE24_2 (1 << 5) #define RME96_WCR_BM (1 << 6) #define RME96_WCR_BM_2 (1 << 7) #define RME96_WCR_ADAT (1 << 8) #define RME96_WCR_FREQ_0 (1 << 9) #define RME96_WCR_FREQ_1 (1 << 10) #define RME96_WCR_DS (1 << 11) #define RME96_WCR_PRO (1 << 12) #define RME96_WCR_EMP (1 << 13) #define RME96_WCR_SEL (1 << 14) #define RME96_WCR_MASTER (1 << 15) #define RME96_WCR_PD (1 << 16) #define RME96_WCR_INP_0 (1 << 17) #define RME96_WCR_INP_1 (1 << 18) #define RME96_WCR_THRU_0 (1 << 19) #define RME96_WCR_THRU_1 (1 << 20) #define RME96_WCR_THRU_2 (1 << 21) #define RME96_WCR_THRU_3 (1 << 22) #define RME96_WCR_THRU_4 (1 << 23) #define RME96_WCR_THRU_5 (1 << 24) #define RME96_WCR_THRU_6 (1 << 25) #define RME96_WCR_THRU_7 (1 << 26) #define RME96_WCR_DOLBY (1 << 27) #define RME96_WCR_MONITOR_0 (1 << 28) #define RME96_WCR_MONITOR_1 (1 << 29) #define RME96_WCR_ISEL (1 << 30) #define RME96_WCR_IDIS (1 << 31) #define RME96_WCR_BITPOS_GAIN_0 2 #define RME96_WCR_BITPOS_GAIN_1 3 #define RME96_WCR_BITPOS_FREQ_0 9 #define RME96_WCR_BITPOS_FREQ_1 10 #define RME96_WCR_BITPOS_INP_0 17 #define RME96_WCR_BITPOS_INP_1 18 #define RME96_WCR_BITPOS_MONITOR_0 28 #define RME96_WCR_BITPOS_MONITOR_1 29 /* Read control register bits */ #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF #define RME96_RCR_IRQ_2 (1 << 16) #define RME96_RCR_T_OUT (1 << 17) #define RME96_RCR_DEV_ID_0 (1 << 21) #define RME96_RCR_DEV_ID_1 (1 << 22) #define RME96_RCR_LOCK (1 << 23) #define RME96_RCR_VERF (1 << 26) #define RME96_RCR_F0 (1 << 27) #define RME96_RCR_F1 (1 << 28) #define RME96_RCR_F2 (1 << 29) #define RME96_RCR_AUTOSYNC (1 << 30) #define RME96_RCR_IRQ (1 << 31) #define RME96_RCR_BITPOS_F0 27 #define RME96_RCR_BITPOS_F1 28 #define RME96_RCR_BITPOS_F2 29 /* Additional register bits */ #define RME96_AR_WSEL (1 << 0) #define RME96_AR_ANALOG (1 << 1) #define RME96_AR_FREQPAD_0 (1 << 2) #define RME96_AR_FREQPAD_1 (1 << 3) #define RME96_AR_FREQPAD_2 (1 << 4) #define RME96_AR_PD2 (1 << 5) #define RME96_AR_DAC_EN (1 << 6) #define RME96_AR_CLATCH (1 << 7) #define RME96_AR_CCLK (1 << 8) #define RME96_AR_CDATA (1 << 9) #define RME96_AR_BITPOS_F0 2 #define RME96_AR_BITPOS_F1 3 #define RME96_AR_BITPOS_F2 4 /* Monitor tracks */ #define RME96_MONITOR_TRACKS_1_2 0 #define RME96_MONITOR_TRACKS_3_4 1 #define RME96_MONITOR_TRACKS_5_6 2 #define RME96_MONITOR_TRACKS_7_8 3 /* Attenuation */ #define RME96_ATTENUATION_0 0 #define RME96_ATTENUATION_6 1 #define RME96_ATTENUATION_12 2 #define RME96_ATTENUATION_18 3 /* Input types */ #define RME96_INPUT_OPTICAL 0 #define RME96_INPUT_COAXIAL 1 #define RME96_INPUT_INTERNAL 2 #define RME96_INPUT_XLR 3 #define RME96_INPUT_ANALOG 4 /* Clock modes */ #define RME96_CLOCKMODE_SLAVE 0 #define RME96_CLOCKMODE_MASTER 1 #define RME96_CLOCKMODE_WORDCLOCK 2 /* Block sizes in bytes */ #define RME96_SMALL_BLOCK_SIZE 2048 #define RME96_LARGE_BLOCK_SIZE 8192 /* Volume control */ #define RME96_AD1852_VOL_BITS 14 #define RME96_AD1855_VOL_BITS 10 struct rme96 { spinlock_t lock; int irq; unsigned long port; void __iomem *iobase; u32 wcreg; /* cached write control register value */ u32 wcreg_spdif; /* S/PDIF setup */ u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ u32 rcreg; /* cached read control register value */ u32 areg; /* cached additional register value */ u16 vol[2]; /* cached volume of analog output */ u8 rev; /* card revision number */ struct snd_pcm_substream *playback_substream; struct snd_pcm_substream *capture_substream; int playback_frlog; /* log2 of framesize */ int capture_frlog; size_t playback_periodsize; /* in bytes, zero if not used */ size_t capture_periodsize; /* in bytes, zero if not used */ struct snd_card *card; struct snd_pcm *spdif_pcm; struct snd_pcm *adat_pcm; struct pci_dev *pci; struct snd_kcontrol *spdif_ctl; }; static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = { { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, { 0, } }; MODULE_DEVICE_TABLE(pci, snd_rme96_ids); #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) static int snd_rme96_playback_prepare(struct snd_pcm_substream *substream); static int snd_rme96_capture_prepare(struct snd_pcm_substream *substream); static int snd_rme96_playback_trigger(struct snd_pcm_substream *substream, int cmd); static int snd_rme96_capture_trigger(struct snd_pcm_substream *substream, int cmd); static snd_pcm_uframes_t snd_rme96_playback_pointer(struct snd_pcm_substream *substream); static snd_pcm_uframes_t snd_rme96_capture_pointer(struct snd_pcm_substream *substream); static void snd_rme96_proc_init(struct rme96 *rme96); static int snd_rme96_create_switches(struct snd_card *card, struct rme96 *rme96); static int snd_rme96_getinputtype(struct rme96 *rme96); static inline unsigned int snd_rme96_playback_ptr(struct rme96 *rme96) { return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; } static inline unsigned int snd_rme96_capture_ptr(struct rme96 *rme96) { return (readl(rme96->iobase + RME96_IO_GET_REC_POS) & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; } static int snd_rme96_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ snd_pcm_uframes_t pos, snd_pcm_uframes_t count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); count <<= rme96->playback_frlog; pos <<= rme96->playback_frlog; memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 0, count); return 0; } static int snd_rme96_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); count <<= rme96->playback_frlog; pos <<= rme96->playback_frlog; copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count); return 0; } static int snd_rme96_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */ snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); count <<= rme96->capture_frlog; pos <<= rme96->capture_frlog; copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count); return 0; } /* * Digital output capabilities (S/PDIF) */ static struct snd_pcm_hardware snd_rme96_playback_spdif_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000), .rate_min = 32000, .rate_max = 96000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital input capabilities (S/PDIF) */ static struct snd_pcm_hardware snd_rme96_capture_spdif_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000), .rate_min = 32000, .rate_max = 96000, .channels_min = 2, .channels_max = 2, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital output capabilities (ADAT) */ static struct snd_pcm_hardware snd_rme96_playback_adat_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * Digital input capabilities (ADAT) */ static struct snd_pcm_hardware snd_rme96_capture_adat_info = { .info = (SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_PAUSE), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE), .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000), .rate_min = 44100, .rate_max = 48000, .channels_min = 8, .channels_max = 8, .buffer_bytes_max = RME96_BUFFER_SIZE, .period_bytes_min = RME96_SMALL_BLOCK_SIZE, .period_bytes_max = RME96_LARGE_BLOCK_SIZE, .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, .fifo_size = 0, }; /* * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up * on the falling edge of CCLK and be stable on the rising edge. The rising * edge of CLATCH after the last data bit clocks in the whole data word. * A fast processor could probably drive the SPI interface faster than the * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) * limits the data rate to 500KHz and only causes a delay of 33 microsecs. * * NOTE: increased delay from 1 to 10, since there where problems setting * the volume. */ static void snd_rme96_write_SPI(struct rme96 *rme96, u16 val) { int i; for (i = 0; i < 16; i++) { if (val & 0x8000) { rme96->areg |= RME96_AR_CDATA; } else { rme96->areg &= ~RME96_AR_CDATA; } rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); rme96->areg |= RME96_AR_CCLK; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); val <<= 1; } rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); rme96->areg |= RME96_AR_CLATCH; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); udelay(10); rme96->areg &= ~RME96_AR_CLATCH; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); } static void snd_rme96_apply_dac_volume(struct rme96 *rme96) { if (RME96_DAC_IS_1852(rme96)) { snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); } else if (RME96_DAC_IS_1855(rme96)) { snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); } } static void snd_rme96_reset_dac(struct rme96 *rme96) { writel(rme96->wcreg | RME96_WCR_PD, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static int snd_rme96_getmontracks(struct rme96 *rme96) { return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); } static int snd_rme96_setmontracks(struct rme96 *rme96, int montracks) { if (montracks & 1) { rme96->wcreg |= RME96_WCR_MONITOR_0; } else { rme96->wcreg &= ~RME96_WCR_MONITOR_0; } if (montracks & 2) { rme96->wcreg |= RME96_WCR_MONITOR_1; } else { rme96->wcreg &= ~RME96_WCR_MONITOR_1; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_getattenuation(struct rme96 *rme96) { return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); } static int snd_rme96_setattenuation(struct rme96 *rme96, int attenuation) { switch (attenuation) { case 0: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & ~RME96_WCR_GAIN_1; break; case 1: rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & ~RME96_WCR_GAIN_1; break; case 2: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | RME96_WCR_GAIN_1; break; case 3: rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | RME96_WCR_GAIN_1; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_capture_getrate(struct rme96 *rme96, int *is_adat) { int n, rate; *is_adat = 0; if (rme96->areg & RME96_AR_ANALOG) { /* Analog input, overrides S/PDIF setting */ n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); switch (n) { case 1: rate = 32000; break; case 2: rate = 44100; break; case 3: rate = 48000; break; default: return -1; } return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; } rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_LOCK) { /* ADAT rate */ *is_adat = 1; if (rme96->rcreg & RME96_RCR_T_OUT) { return 48000; } return 44100; } if (rme96->rcreg & RME96_RCR_VERF) { return -1; } /* S/PDIF rate */ n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); switch (n) { case 0: if (rme96->rcreg & RME96_RCR_T_OUT) { return 64000; } return -1; case 3: return 96000; case 4: return 88200; case 5: return 48000; case 6: return 44100; case 7: return 32000; default: break; } return -1; } static int snd_rme96_playback_getrate(struct rme96 *rme96) { int rate, dummy; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) { /* slave clock */ return rate; } rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); switch (rate) { case 1: rate = 32000; break; case 2: rate = 44100; break; case 3: rate = 48000; break; default: return -1; } return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; } static int snd_rme96_playback_setrate(struct rme96 *rme96, int rate) { int ds; ds = rme96->wcreg & RME96_WCR_DS; switch (rate) { case 32000: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & ~RME96_WCR_FREQ_1; break; case 44100: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & ~RME96_WCR_FREQ_0; break; case 48000: rme96->wcreg &= ~RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | RME96_WCR_FREQ_1; break; case 64000: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & ~RME96_WCR_FREQ_1; break; case 88200: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & ~RME96_WCR_FREQ_0; break; case 96000: rme96->wcreg |= RME96_WCR_DS; rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | RME96_WCR_FREQ_1; break; default: return -EINVAL; } if ((!ds && rme96->wcreg & RME96_WCR_DS) || (ds && !(rme96->wcreg & RME96_WCR_DS))) { /* change to/from double-speed: reset the DAC (if available) */ snd_rme96_reset_dac(rme96); return 1; /* need to restore volume */ } else { writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } } static int snd_rme96_capture_analog_setrate(struct rme96 *rme96, int rate) { switch (rate) { case 32000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 44100: rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 48000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; break; case 64000: if (rme96->rev < 4) { return -EINVAL; } rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; case 88200: if (rme96->rev < 4) { return -EINVAL; } rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; case 96000: rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; break; default: return -EINVAL; } writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); return 0; } static int snd_rme96_setclockmode(struct rme96 *rme96, int mode) { switch (mode) { case RME96_CLOCKMODE_SLAVE: /* AutoSync */ rme96->wcreg &= ~RME96_WCR_MASTER; rme96->areg &= ~RME96_AR_WSEL; break; case RME96_CLOCKMODE_MASTER: /* Internal */ rme96->wcreg |= RME96_WCR_MASTER; rme96->areg &= ~RME96_AR_WSEL; break; case RME96_CLOCKMODE_WORDCLOCK: /* Word clock is a master mode */ rme96->wcreg |= RME96_WCR_MASTER; rme96->areg |= RME96_AR_WSEL; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); return 0; } static int snd_rme96_getclockmode(struct rme96 *rme96) { if (rme96->areg & RME96_AR_WSEL) { return RME96_CLOCKMODE_WORDCLOCK; } return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : RME96_CLOCKMODE_SLAVE; } static int snd_rme96_setinputtype(struct rme96 *rme96, int type) { int n; switch (type) { case RME96_INPUT_OPTICAL: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & ~RME96_WCR_INP_1; break; case RME96_INPUT_COAXIAL: rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & ~RME96_WCR_INP_1; break; case RME96_INPUT_INTERNAL: rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | RME96_WCR_INP_1; break; case RME96_INPUT_XLR: if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4)) { /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ return -EINVAL; } rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | RME96_WCR_INP_1; break; case RME96_INPUT_ANALOG: if (!RME96_HAS_ANALOG_IN(rme96)) { return -EINVAL; } rme96->areg |= RME96_AR_ANALOG; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); if (rme96->rev < 4) { /* * Revision less than 004 does not support 64 and * 88.2 kHz */ if (snd_rme96_capture_getrate(rme96, &n) == 88200) { snd_rme96_capture_analog_setrate(rme96, 44100); } if (snd_rme96_capture_getrate(rme96, &n) == 64000) { snd_rme96_capture_analog_setrate(rme96, 32000); } } return 0; default: return -EINVAL; } if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { rme96->areg &= ~RME96_AR_ANALOG; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_getinputtype(struct rme96 *rme96) { if (rme96->areg & RME96_AR_ANALOG) { return RME96_INPUT_ANALOG; } return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); } static void snd_rme96_setframelog(struct rme96 *rme96, int n_channels, int is_playback) { int frlog; if (n_channels == 2) { frlog = 1; } else { /* assume 8 channels */ frlog = 3; } if (is_playback) { frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; rme96->playback_frlog = frlog; } else { frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; rme96->capture_frlog = frlog; } } static int snd_rme96_playback_setformat(struct rme96 *rme96, int format) { switch (format) { case SNDRV_PCM_FORMAT_S16_LE: rme96->wcreg &= ~RME96_WCR_MODE24; break; case SNDRV_PCM_FORMAT_S32_LE: rme96->wcreg |= RME96_WCR_MODE24; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static int snd_rme96_capture_setformat(struct rme96 *rme96, int format) { switch (format) { case SNDRV_PCM_FORMAT_S16_LE: rme96->wcreg &= ~RME96_WCR_MODE24_2; break; case SNDRV_PCM_FORMAT_S32_LE: rme96->wcreg |= RME96_WCR_MODE24_2; break; default: return -EINVAL; } writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); return 0; } static void snd_rme96_set_period_properties(struct rme96 *rme96, size_t period_bytes) { switch (period_bytes) { case RME96_LARGE_BLOCK_SIZE: rme96->wcreg &= ~RME96_WCR_ISEL; break; case RME96_SMALL_BLOCK_SIZE: rme96->wcreg |= RME96_WCR_ISEL; break; default: snd_BUG(); break; } rme96->wcreg &= ~RME96_WCR_IDIS; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static int snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err, rate, dummy; bool apply_dac_volume = false; runtime->dma_area = (void __force *)(rme96->iobase + RME96_IO_PLAY_BUFFER); runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; runtime->dma_bytes = RME96_BUFFER_SIZE; spin_lock_irq(&rme96->lock); if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) { /* slave clock */ if ((int)params_rate(params) != rate) { err = -EIO; goto error; } } else { err = snd_rme96_playback_setrate(rme96, params_rate(params)); if (err < 0) goto error; apply_dac_volume = err > 0; /* need to restore volume later? */ } err = snd_rme96_playback_setformat(rme96, params_format(params)); if (err < 0) goto error; snd_rme96_setframelog(rme96, params_channels(params), 1); if (rme96->capture_periodsize != 0) { if (params_period_size(params) << rme96->playback_frlog != rme96->capture_periodsize) { err = -EBUSY; goto error; } } rme96->playback_periodsize = params_period_size(params) << rme96->playback_frlog; snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); /* S/PDIF setup */ if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); } err = 0; error: spin_unlock_irq(&rme96->lock); if (apply_dac_volume) { usleep_range(3000, 10000); snd_rme96_apply_dac_volume(rme96); } return err; } static int snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; int err, isadat, rate; runtime->dma_area = (void __force *)(rme96->iobase + RME96_IO_REC_BUFFER); runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; runtime->dma_bytes = RME96_BUFFER_SIZE; spin_lock_irq(&rme96->lock); if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { spin_unlock_irq(&rme96->lock); return err; } if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { if ((err = snd_rme96_capture_analog_setrate(rme96, params_rate(params))) < 0) { spin_unlock_irq(&rme96->lock); return err; } } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { if ((int)params_rate(params) != rate) { spin_unlock_irq(&rme96->lock); return -EIO; } if ((isadat && runtime->hw.channels_min == 2) || (!isadat && runtime->hw.channels_min == 8)) { spin_unlock_irq(&rme96->lock); return -EIO; } } snd_rme96_setframelog(rme96, params_channels(params), 0); if (rme96->playback_periodsize != 0) { if (params_period_size(params) << rme96->capture_frlog != rme96->playback_periodsize) { spin_unlock_irq(&rme96->lock); return -EBUSY; } } rme96->capture_periodsize = params_period_size(params) << rme96->capture_frlog; snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); spin_unlock_irq(&rme96->lock); return 0; } static void snd_rme96_playback_start(struct rme96 *rme96, int from_pause) { if (!from_pause) { writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); } rme96->wcreg |= RME96_WCR_START; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static void snd_rme96_capture_start(struct rme96 *rme96, int from_pause) { if (!from_pause) { writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); } rme96->wcreg |= RME96_WCR_START_2; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static void snd_rme96_playback_stop(struct rme96 *rme96) { /* * Check if there is an unconfirmed IRQ, if so confirm it, or else * the hardware will not stop generating interrupts */ rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_IRQ) { writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); } rme96->wcreg &= ~RME96_WCR_START; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static void snd_rme96_capture_stop(struct rme96 *rme96) { rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); if (rme96->rcreg & RME96_RCR_IRQ_2) { writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); } rme96->wcreg &= ~RME96_WCR_START_2; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); } static irqreturn_t snd_rme96_interrupt(int irq, void *dev_id) { struct rme96 *rme96 = (struct rme96 *)dev_id; rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); /* fastpath out, to ease interrupt sharing */ if (!((rme96->rcreg & RME96_RCR_IRQ) || (rme96->rcreg & RME96_RCR_IRQ_2))) { return IRQ_NONE; } if (rme96->rcreg & RME96_RCR_IRQ) { /* playback */ snd_pcm_period_elapsed(rme96->playback_substream); writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); } if (rme96->rcreg & RME96_RCR_IRQ_2) { /* capture */ snd_pcm_period_elapsed(rme96->capture_substream); writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); } return IRQ_HANDLED; } static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { .count = ARRAY_SIZE(period_bytes), .list = period_bytes, .mask = 0 }; static void rme96_set_buffer_size_constraint(struct rme96 *rme96, struct snd_pcm_runtime *runtime) { unsigned int size; snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); if ((size = rme96->playback_periodsize) != 0 || (size = rme96->capture_periodsize) != 0) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, size, size); else snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); } static int snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; spin_lock_irq(&rme96->lock); if (rme96->playback_substream != NULL) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->wcreg &= ~RME96_WCR_ADAT; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); rme96->playback_substream = substream; spin_unlock_irq(&rme96->lock); runtime->hw = snd_rme96_playback_spdif_info; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) { /* slave clock */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } rme96_set_buffer_size_constraint(rme96, runtime); rme96->wcreg_spdif_stream = rme96->wcreg_spdif; rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); return 0; } static int snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; runtime->hw = snd_rme96_capture_spdif_info; if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { if (isadat) { return -EIO; } runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } spin_lock_irq(&rme96->lock); if (rme96->capture_substream != NULL) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->capture_substream = substream; spin_unlock_irq(&rme96->lock); rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) { int rate, dummy; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; spin_lock_irq(&rme96->lock); if (rme96->playback_substream != NULL) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->wcreg |= RME96_WCR_ADAT; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); rme96->playback_substream = substream; spin_unlock_irq(&rme96->lock); runtime->hw = snd_rme96_playback_adat_info; if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) { /* slave clock */ runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) { int isadat, rate; struct rme96 *rme96 = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; runtime->hw = snd_rme96_capture_adat_info; if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { /* makes no sense to use analog input. Note that analog expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ return -EIO; } if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { if (!isadat) { return -EIO; } runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); runtime->hw.rate_min = rate; runtime->hw.rate_max = rate; } spin_lock_irq(&rme96->lock); if (rme96->capture_substream != NULL) { spin_unlock_irq(&rme96->lock); return -EBUSY; } rme96->capture_substream = substream; spin_unlock_irq(&rme96->lock); rme96_set_buffer_size_constraint(rme96, runtime); return 0; } static int snd_rme96_playback_close(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); int spdif = 0; spin_lock_irq(&rme96->lock); if (RME96_ISPLAYING(rme96)) { snd_rme96_playback_stop(rme96); } rme96->playback_substream = NULL; rme96->playback_periodsize = 0; spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; spin_unlock_irq(&rme96->lock); if (spdif) { rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); } return 0; } static int snd_rme96_capture_close(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISRECORDING(rme96)) { snd_rme96_capture_stop(rme96); } rme96->capture_substream = NULL; rme96->capture_periodsize = 0; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_playback_prepare(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISPLAYING(rme96)) { snd_rme96_playback_stop(rme96); } writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_capture_prepare(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); spin_lock_irq(&rme96->lock); if (RME96_ISRECORDING(rme96)) { snd_rme96_capture_stop(rme96); } writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_playback_trigger(struct snd_pcm_substream *substream, int cmd) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (!RME96_ISPLAYING(rme96)) { if (substream != rme96->playback_substream) { return -EBUSY; } snd_rme96_playback_start(rme96, 0); } break; case SNDRV_PCM_TRIGGER_STOP: if (RME96_ISPLAYING(rme96)) { if (substream != rme96->playback_substream) { return -EBUSY; } snd_rme96_playback_stop(rme96); } break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (RME96_ISPLAYING(rme96)) { snd_rme96_playback_stop(rme96); } break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!RME96_ISPLAYING(rme96)) { snd_rme96_playback_start(rme96, 1); } break; default: return -EINVAL; } return 0; } static int snd_rme96_capture_trigger(struct snd_pcm_substream *substream, int cmd) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (!RME96_ISRECORDING(rme96)) { if (substream != rme96->capture_substream) { return -EBUSY; } snd_rme96_capture_start(rme96, 0); } break; case SNDRV_PCM_TRIGGER_STOP: if (RME96_ISRECORDING(rme96)) { if (substream != rme96->capture_substream) { return -EBUSY; } snd_rme96_capture_stop(rme96); } break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (RME96_ISRECORDING(rme96)) { snd_rme96_capture_stop(rme96); } break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (!RME96_ISRECORDING(rme96)) { snd_rme96_capture_start(rme96, 1); } break; default: return -EINVAL; } return 0; } static snd_pcm_uframes_t snd_rme96_playback_pointer(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return snd_rme96_playback_ptr(rme96); } static snd_pcm_uframes_t snd_rme96_capture_pointer(struct snd_pcm_substream *substream) { struct rme96 *rme96 = snd_pcm_substream_chip(substream); return snd_rme96_capture_ptr(rme96); } static struct snd_pcm_ops snd_rme96_playback_spdif_ops = { .open = snd_rme96_playback_spdif_open, .close = snd_rme96_playback_close, .ioctl = snd_pcm_lib_ioctl, .hw_params = snd_rme96_playback_hw_params, .prepare = snd_rme96_playback_prepare, .trigger = snd_rme96_playback_trigger, .pointer = snd_rme96_playback_pointer, .copy = snd_rme96_playback_copy, .silence = snd_rme96_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static struct snd_pcm_ops snd_rme96_capture_spdif_ops = { .open = snd_rme96_capture_spdif_open, .close = snd_rme96_capture_close, .ioctl = snd_pcm_lib_ioctl, .hw_params = snd_rme96_capture_hw_params, .prepare = snd_rme96_capture_prepare, .trigger = snd_rme96_capture_trigger, .pointer = snd_rme96_capture_pointer, .copy = snd_rme96_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; static struct snd_pcm_ops snd_rme96_playback_adat_ops = { .open = snd_rme96_playback_adat_open, .close = snd_rme96_playback_close, .ioctl = snd_pcm_lib_ioctl, .hw_params = snd_rme96_playback_hw_params, .prepare = snd_rme96_playback_prepare, .trigger = snd_rme96_playback_trigger, .pointer = snd_rme96_playback_pointer, .copy = snd_rme96_playback_copy, .silence = snd_rme96_playback_silence, .mmap = snd_pcm_lib_mmap_iomem, }; static struct snd_pcm_ops snd_rme96_capture_adat_ops = { .open = snd_rme96_capture_adat_open, .close = snd_rme96_capture_close, .ioctl = snd_pcm_lib_ioctl, .hw_params = snd_rme96_capture_hw_params, .prepare = snd_rme96_capture_prepare, .trigger = snd_rme96_capture_trigger, .pointer = snd_rme96_capture_pointer, .copy = snd_rme96_capture_copy, .mmap = snd_pcm_lib_mmap_iomem, }; static void snd_rme96_free(void *private_data) { struct rme96 *rme96 = (struct rme96 *)private_data; if (rme96 == NULL) { return; } if (rme96->irq >= 0) { snd_rme96_playback_stop(rme96); snd_rme96_capture_stop(rme96); rme96->areg &= ~RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); free_irq(rme96->irq, (void *)rme96); rme96->irq = -1; } if (rme96->iobase) { iounmap(rme96->iobase); rme96->iobase = NULL; } if (rme96->port) { pci_release_regions(rme96->pci); rme96->port = 0; } pci_disable_device(rme96->pci); } static void snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) { struct rme96 *rme96 = pcm->private_data; rme96->spdif_pcm = NULL; } static void snd_rme96_free_adat_pcm(struct snd_pcm *pcm) { struct rme96 *rme96 = pcm->private_data; rme96->adat_pcm = NULL; } static int snd_rme96_create(struct rme96 *rme96) { struct pci_dev *pci = rme96->pci; int err; rme96->irq = -1; spin_lock_init(&rme96->lock); if ((err = pci_enable_device(pci)) < 0) return err; if ((err = pci_request_regions(pci, "RME96")) < 0) return err; rme96->port = pci_resource_start(rme96->pci, 0); rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE); if (!rme96->iobase) { snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1); return -ENOMEM; } if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, KBUILD_MODNAME, rme96)) { snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); return -EBUSY; } rme96->irq = pci->irq; /* read the card's revision number */ pci_read_config_byte(pci, 8, &rme96->rev); /* set up ALSA pcm device for S/PDIF */ if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1, 1, &rme96->spdif_pcm)) < 0) { return err; } rme96->spdif_pcm->private_data = rme96; rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); rme96->spdif_pcm->info_flags = 0; /* set up ALSA pcm device for ADAT */ if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { /* ADAT is not available on the base model */ rme96->adat_pcm = NULL; } else { if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1, 1, &rme96->adat_pcm)) < 0) { return err; } rme96->adat_pcm->private_data = rme96; rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); rme96->adat_pcm->info_flags = 0; } rme96->playback_periodsize = 0; rme96->capture_periodsize = 0; /* make sure playback/capture is stopped, if by some reason active */ snd_rme96_playback_stop(rme96); snd_rme96_capture_stop(rme96); /* set default values in registers */ rme96->wcreg = RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ RME96_WCR_SEL | /* normal playback */ RME96_WCR_MASTER | /* set to master clock mode */ RME96_WCR_INP_0; /* set coaxial input */ rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset the ADC */ writel(rme96->areg | RME96_AR_PD2, rme96->iobase + RME96_IO_ADDITIONAL_REG); writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset and enable the DAC (order is important). */ snd_rme96_reset_dac(rme96); rme96->areg |= RME96_AR_DAC_EN; writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); /* reset playback and record buffer pointers */ writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); /* reset volume */ rme96->vol[0] = rme96->vol[1] = 0; if (RME96_HAS_ANALOG_OUT(rme96)) { snd_rme96_apply_dac_volume(rme96); } /* init switch interface */ if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { return err; } /* init proc interface */ snd_rme96_proc_init(rme96); return 0; } /* * proc interface */ static void snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) { int n; struct rme96 *rme96 = entry->private_data; rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_iprintf(buffer, rme96->card->longname); snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); snd_iprintf(buffer, "\nGeneral settings\n"); if (rme96->wcreg & RME96_WCR_IDIS) { snd_iprintf(buffer, " period size: N/A (interrupts " "disabled)\n"); } else if (rme96->wcreg & RME96_WCR_ISEL) { snd_iprintf(buffer, " period size: 2048 bytes\n"); } else { snd_iprintf(buffer, " period size: 8192 bytes\n"); } snd_iprintf(buffer, "\nInput settings\n"); switch (snd_rme96_getinputtype(rme96)) { case RME96_INPUT_OPTICAL: snd_iprintf(buffer, " input: optical"); break; case RME96_INPUT_COAXIAL: snd_iprintf(buffer, " input: coaxial"); break; case RME96_INPUT_INTERNAL: snd_iprintf(buffer, " input: internal"); break; case RME96_INPUT_XLR: snd_iprintf(buffer, " input: XLR"); break; case RME96_INPUT_ANALOG: snd_iprintf(buffer, " input: analog"); break; } if (snd_rme96_capture_getrate(rme96, &n) < 0) { snd_iprintf(buffer, "\n sample rate: no valid signal\n"); } else { if (n) { snd_iprintf(buffer, " (8 channels)\n"); } else { snd_iprintf(buffer, " (2 channels)\n"); } snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme96_capture_getrate(rme96, &n)); } if (rme96->wcreg & RME96_WCR_MODE24_2) { snd_iprintf(buffer, " sample format: 24 bit\n"); } else { snd_iprintf(buffer, " sample format: 16 bit\n"); } snd_iprintf(buffer, "\nOutput settings\n"); if (rme96->wcreg & RME96_WCR_SEL) { snd_iprintf(buffer, " output signal: normal playback\n"); } else { snd_iprintf(buffer, " output signal: same as input\n"); } snd_iprintf(buffer, " sample rate: %d Hz\n", snd_rme96_playback_getrate(rme96)); if (rme96->wcreg & RME96_WCR_MODE24) { snd_iprintf(buffer, " sample format: 24 bit\n"); } else { snd_iprintf(buffer, " sample format: 16 bit\n"); } if (rme96->areg & RME96_AR_WSEL) { snd_iprintf(buffer, " sample clock source: word clock\n"); } else if (rme96->wcreg & RME96_WCR_MASTER) { snd_iprintf(buffer, " sample clock source: internal\n"); } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); } else { snd_iprintf(buffer, " sample clock source: autosync\n"); } if (rme96->wcreg & RME96_WCR_PRO) { snd_iprintf(buffer, " format: AES/EBU (professional)\n"); } else { snd_iprintf(buffer, " format: IEC958 (consumer)\n"); } if (rme96->wcreg & RME96_WCR_EMP) { snd_iprintf(buffer, " emphasis: on\n"); } else { snd_iprintf(buffer, " emphasis: off\n"); } if (rme96->wcreg & RME96_WCR_DOLBY) { snd_iprintf(buffer, " non-audio (dolby): on\n"); } else { snd_iprintf(buffer, " non-audio (dolby): off\n"); } if (RME96_HAS_ANALOG_IN(rme96)) { snd_iprintf(buffer, "\nAnalog output settings\n"); switch (snd_rme96_getmontracks(rme96)) { case RME96_MONITOR_TRACKS_1_2: snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); break; case RME96_MONITOR_TRACKS_3_4: snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); break; case RME96_MONITOR_TRACKS_5_6: snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); break; case RME96_MONITOR_TRACKS_7_8: snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); break; } switch (snd_rme96_getattenuation(rme96)) { case RME96_ATTENUATION_0: snd_iprintf(buffer, " attenuation: 0 dB\n"); break; case RME96_ATTENUATION_6: snd_iprintf(buffer, " attenuation: -6 dB\n"); break; case RME96_ATTENUATION_12: snd_iprintf(buffer, " attenuation: -12 dB\n"); break; case RME96_ATTENUATION_18: snd_iprintf(buffer, " attenuation: -18 dB\n"); break; } snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); } } static void snd_rme96_proc_init(struct rme96 *rme96) { struct snd_info_entry *entry; if (! snd_card_proc_new(rme96->card, "rme96", &entry)) snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read); } /* * control interface */ #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info static int snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; spin_lock_irq(&rme96->lock); val = (rme96->wcreg & ~RME96_WCR_SEL) | val; change = val != rme96->wcreg; rme96->wcreg = val; writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" }; struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] }; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: uinfo->value.enumerated.items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: uinfo->value.enumerated.items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { /* PST */ uinfo->value.enumerated.items = 4; texts[3] = _texts[4]; /* Analog instead of XLR */ } else { /* PAD */ uinfo->value.enumerated.items = 5; } break; default: snd_BUG(); break; } if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) { uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; } strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); return 0; } static int snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int items = 3; spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; } items = 4; } else { items = 5; } break; default: snd_BUG(); break; } if (ucontrol->value.enumerated.item[0] >= items) { ucontrol->value.enumerated.item[0] = items - 1; } spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change, items = 3; switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: case PCI_DEVICE_ID_RME_DIGI96_8: items = 3; break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: items = 4; break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: if (rme96->rev > 4) { items = 4; } else { items = 5; } break; default: snd_BUG(); break; } val = ucontrol->value.enumerated.item[0] % items; /* special case for PST */ if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { if (val == RME96_INPUT_XLR) { val = RME96_INPUT_ANALOG; } } spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getinputtype(rme96); snd_rme96_setinputtype(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static char *texts[3] = { "AutoSync", "Internal", "Word" }; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = 3; if (uinfo->value.enumerated.item > 2) { uinfo->value.enumerated.item = 2; } strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); return 0; } static int snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 3; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getclockmode(rme96); snd_rme96_setclockmode(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" }; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = 4; if (uinfo->value.enumerated.item > 3) { uinfo->value.enumerated.item = 3; } strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); return 0; } static int snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 4; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getattenuation(rme96); snd_rme96_setattenuation(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" }; uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; uinfo->count = 1; uinfo->value.enumerated.items = 4; if (uinfo->value.enumerated.item > 3) { uinfo->value.enumerated.item = 3; } strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); return 0; } static int snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); unsigned int val; int change; val = ucontrol->value.enumerated.item[0] % 4; spin_lock_irq(&rme96->lock); change = (int)val != snd_rme96_getmontracks(rme96); snd_rme96_setmontracks(rme96, val); spin_unlock_irq(&rme96->lock); return change; } static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) { u32 val = 0; val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; if (val & RME96_WCR_PRO) val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; else val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; return val; } static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) { aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); if (val & RME96_WCR_PRO) aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; else aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; } static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); return 0; } static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme96->lock); change = val != rme96->wcreg_spdif; rme96->wcreg_spdif = val; spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); return 0; } static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change; u32 val; val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); spin_lock_irq(&rme96->lock); change = val != rme96->wcreg_spdif_stream; rme96->wcreg_spdif_stream = val; rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); rme96->wcreg |= val; writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); spin_unlock_irq(&rme96->lock); return change; } static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; uinfo->count = 1; return 0; } static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { ucontrol->value.iec958.status[0] = kcontrol->private_value; return 0; } static int snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); return 0; } static int snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); spin_lock_irq(&rme96->lock); u->value.integer.value[0] = rme96->vol[0]; u->value.integer.value[1] = rme96->vol[1]; spin_unlock_irq(&rme96->lock); return 0; } static int snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) { struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); int change = 0; unsigned int vol, maxvol; if (!RME96_HAS_ANALOG_OUT(rme96)) return -EINVAL; maxvol = RME96_185X_MAX_OUT(rme96); spin_lock_irq(&rme96->lock); vol = u->value.integer.value[0]; if (vol != rme96->vol[0] && vol <= maxvol) { rme96->vol[0] = vol; change = 1; } vol = u->value.integer.value[1]; if (vol != rme96->vol[1] && vol <= maxvol) { rme96->vol[1] = vol; change = 1; } if (change) snd_rme96_apply_dac_volume(rme96); spin_unlock_irq(&rme96->lock); return change; } static struct snd_kcontrol_new snd_rme96_controls[] = { { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), .info = snd_rme96_control_spdif_info, .get = snd_rme96_control_spdif_get, .put = snd_rme96_control_spdif_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), .info = snd_rme96_control_spdif_stream_info, .get = snd_rme96_control_spdif_stream_get, .put = snd_rme96_control_spdif_stream_put }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), .info = snd_rme96_control_spdif_mask_info, .get = snd_rme96_control_spdif_mask_get, .private_value = IEC958_AES0_NONAUDIO | IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS }, { .access = SNDRV_CTL_ELEM_ACCESS_READ, .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), .info = snd_rme96_control_spdif_mask_info, .get = snd_rme96_control_spdif_mask_get, .private_value = IEC958_AES0_NONAUDIO | IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Input Connector", .info = snd_rme96_info_inputtype_control, .get = snd_rme96_get_inputtype_control, .put = snd_rme96_put_inputtype_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Loopback Input", .info = snd_rme96_info_loopback_control, .get = snd_rme96_get_loopback_control, .put = snd_rme96_put_loopback_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Sample Clock Source", .info = snd_rme96_info_clockmode_control, .get = snd_rme96_get_clockmode_control, .put = snd_rme96_put_clockmode_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Monitor Tracks", .info = snd_rme96_info_montracks_control, .get = snd_rme96_get_montracks_control, .put = snd_rme96_put_montracks_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Attenuation", .info = snd_rme96_info_attenuation_control, .get = snd_rme96_get_attenuation_control, .put = snd_rme96_put_attenuation_control }, { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "DAC Playback Volume", .info = snd_rme96_dac_volume_info, .get = snd_rme96_dac_volume_get, .put = snd_rme96_dac_volume_put } }; static int snd_rme96_create_switches(struct snd_card *card, struct rme96 *rme96) { int idx, err; struct snd_kcontrol *kctl; for (idx = 0; idx < 7; idx++) { if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) return err; if (idx == 1) /* IEC958 (S/PDIF) Stream */ rme96->spdif_ctl = kctl; } if (RME96_HAS_ANALOG_OUT(rme96)) { for (idx = 7; idx < 10; idx++) if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) return err; } return 0; } /* * Card initialisation */ static void snd_rme96_card_free(struct snd_card *card) { snd_rme96_free(card->private_data); } static int snd_rme96_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) { static int dev; struct rme96 *rme96; struct snd_card *card; int err; u8 val; if (dev >= SNDRV_CARDS) { return -ENODEV; } if (!enable[dev]) { dev++; return -ENOENT; } err = snd_card_create(index[dev], id[dev], THIS_MODULE, sizeof(struct rme96), &card); if (err < 0) return err; card->private_free = snd_rme96_card_free; rme96 = card->private_data; rme96->card = card; rme96->pci = pci; snd_card_set_dev(card, &pci->dev); if ((err = snd_rme96_create(rme96)) < 0) { snd_card_free(card); return err; } strcpy(card->driver, "Digi96"); switch (rme96->pci->device) { case PCI_DEVICE_ID_RME_DIGI96: strcpy(card->shortname, "RME Digi96"); break; case PCI_DEVICE_ID_RME_DIGI96_8: strcpy(card->shortname, "RME Digi96/8"); break; case PCI_DEVICE_ID_RME_DIGI96_8_PRO: strcpy(card->shortname, "RME Digi96/8 PRO"); break; case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: pci_read_config_byte(rme96->pci, 8, &val); if (val < 5) { strcpy(card->shortname, "RME Digi96/8 PAD"); } else { strcpy(card->shortname, "RME Digi96/8 PST"); } break; } sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, rme96->port, rme96->irq); if ((err = snd_card_register(card)) < 0) { snd_card_free(card); return err; } pci_set_drvdata(pci, card); dev++; return 0; } static void snd_rme96_remove(struct pci_dev *pci) { snd_card_free(pci_get_drvdata(pci)); pci_set_drvdata(pci, NULL); } static struct pci_driver rme96_driver = { .name = KBUILD_MODNAME, .id_table = snd_rme96_ids, .probe = snd_rme96_probe, .remove = snd_rme96_remove, }; module_pci_driver(rme96_driver);

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// SampSharp // Copyright 2022 Tim Potze // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. #pragma once #define PLUGIN_VERSION_MAJOR 0 #define PLUGIN_VERSION_MINOR 11 #define PLUGIN_VERSION_PATCH 0 #define PLUGIN_VERSION_ALPHA 0 #define __PLUGIN_STRINGIZE(x) #x #define __PLUGIN_STRINGIZEX(x) __PLUGIN_STRINGIZE(x) #define __PLUGIN_VERSION_STR \ __PLUGIN_STRINGIZEX(PLUGIN_VERSION_MAJOR) "." \ __PLUGIN_STRINGIZEX(PLUGIN_VERSION_MINOR) "." \ __PLUGIN_STRINGIZEX(PLUGIN_VERSION_PATCH) #if PLUGIN_VERSION_ALPHA > 0 # define PLUGIN_VERSION_STR __PLUGIN_VERSION_STR "-alpha" \ __PLUGIN_STRINGIZEX(PLUGIN_VERSION_ALPHA) #else # define PLUGIN_VERSION_STR __PLUGIN_VERSION_STR #endif #define PLUGIN_VERSION ( \ (PLUGIN_VERSION_MAJOR << 16) | \ (PLUGIN_VERSION_MINOR << 8) | \ (PLUGIN_VERSION_PATCH) | \ (PLUGIN_VERSION_ALPHA << 24))

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/unit_tests/UnitTestShmemAlignment.C

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UnitTestShmemAlignment.C

#include <gtest/gtest.h> #include <KokkosInterface.h> KOKKOS_FUNCTION inline bool is_aligned(const void* pointer, size_t byte_count) { return (uintptr_t)pointer % byte_count == 0; } void do_the_test() { unsigned N = 1; unsigned numScalars = 3; Kokkos::View<unsigned*, sierra::nalu::MemSpace> ngpResults("ngpResults", 1); Kokkos::View<unsigned*, sierra::nalu::MemSpace>::HostMirror hostResults = Kokkos::create_mirror_view(ngpResults); Kokkos::deep_copy(ngpResults, hostResults); unsigned bytes_per_team = 16; unsigned bytes_per_thread = 128; unsigned threads_per_team = 1; auto team_exec = sierra::nalu::get_device_team_policy( N, bytes_per_team, bytes_per_thread, threads_per_team); Kokkos::parallel_for( team_exec, KOKKOS_LAMBDA(const sierra::nalu::DeviceTeamHandleType& team) { unsigned one = 1; sierra::nalu::SharedMemView<double*, sierra::nalu::DeviceShmem> view1 = sierra::nalu::get_shmem_view_1D< double, sierra::nalu::DeviceTeamHandleType, sierra::nalu::DeviceShmem>(team, numScalars); if (view1.size() > 0 && is_aligned(view1.data(), 8)) { Kokkos::atomic_add(&ngpResults(0), one); } sierra::nalu::SharedMemView<double*, sierra::nalu::DeviceShmem> view2 = sierra::nalu::get_shmem_view_1D< double, sierra::nalu::DeviceTeamHandleType, sierra::nalu::DeviceShmem>(team, numScalars); if (view2.size() > 0 && is_aligned(view2.data(), 8)) { Kokkos::atomic_add(&ngpResults(0), one); } sierra::nalu::SharedMemView<double*, sierra::nalu::DeviceShmem> view3 = sierra::nalu::get_shmem_view_1D< double, sierra::nalu::DeviceTeamHandleType, sierra::nalu::DeviceShmem>(team, numScalars); if (view3.size() > 0 && is_aligned(view3.data(), 8)) { Kokkos::atomic_add(&ngpResults(0), one); } }); Kokkos::deep_copy(hostResults, ngpResults); EXPECT_EQ(3u, hostResults(0)); } TEST(Shmem, align) { do_the_test(); }

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2023-03-21T09:07:32

2015-06-16T01:22:12

C

UTF-8

C

false

11,162

h

BRGeneric.h

// // BRGeneric.h // Core // // Created by Ed Gamble on 6/19/19. // Copyright © 2019 Breadwinner AG. All rights reserved. // // See the LICENSE file at the project root for license information. // See the CONTRIBUTORS file at the project root for a list of contributors. #ifndef BRGeneric_h #define BRGeneric_h #include "support/BRInt.h" // UInt256 #include "support/BRSet.h" // BRSet #include "support/BRKey.h" // BRKey #include "support/BRArray.h" #include "BRGenericBase.h" #include "BRGenericClient.h" #ifdef __cplusplus extern "C" { #endif // MARK: - Network extern BRGenericNetwork genNetworkCreate (const char * type, int isMainnet); extern void genNetworkRelease (BRGenericNetwork network); extern const char * genNetworkGetType (BRGenericNetwork network); extern int genNetworkIsMainnet (BRGenericNetwork network); // MARK: - Account extern BRGenericAccount genAccountCreate (const char *type, UInt512 seed); extern BRGenericAccount genAccountCreateWithPublicKey (const char *type, BRKey publicKey); extern BRGenericAccount genAccountCreateWithSerialization (const char *type, uint8_t *bytes, size_t bytesCount); extern void genAccountRelease (BRGenericAccount account); extern const char * genAccountGetType (BRGenericAccount account); extern int genAccountHasType (BRGenericAccount account, const char *type); extern BRGenericAddress genAccountGetAddress (BRGenericAccount account); extern uint8_t * genAccountGetSerialization (BRGenericAccount account, size_t *bytesCount); extern void genAccountSignTransferWithSeed (BRGenericAccount account, BRGenericTransfer transfer, UInt512 seed); extern void genAccountSignTransferWithKey (BRGenericAccount account, BRGenericTransfer transfer, BRKey *key); // Address extern BRGenericAddress genAddressCreate (const char *type, const char *string); extern char * genAddressAsString (BRGenericAddress aid); extern int genAddressEqual (BRGenericAddress aid1, BRGenericAddress aid2); extern void genAddressRelease (BRGenericAddress address); // Transfer extern void genTransferRelease (BRGenericTransfer transfer); extern BRGenericAddress genTransferGetSourceAddress (BRGenericTransfer transfer); extern BRGenericAddress genTransferGetTargetAddress (BRGenericTransfer transfer); extern UInt256 genTransferGetAmount (BRGenericTransfer transfer); extern BRGenericFeeBasis genTransferGetFeeBasis (BRGenericTransfer transfer); extern BRGenericTransferDirection genTransferGetDirection (BRGenericTransfer transfer); extern BRGenericHash genTransferGetHash (BRGenericTransfer transfer); extern const char * genTransferGetUIDS (BRGenericTransfer transfer); extern void genTransferSetUIDS (BRGenericTransfer transfer, const char *uids); extern BRGenericTransferState genTransferGetState (BRGenericTransfer transfer); extern void genTransferSetState (BRGenericTransfer transfer, BRGenericTransferState state); extern OwnershipKept BRArrayOf(BRGenericTransferAttribute) genTransferGetAttributes (BRGenericTransfer transfer); extern void genTransferSetAttributes (BRGenericTransfer transfer, OwnershipKept BRArrayOf(BRGenericTransferAttribute) attributes); extern int genTransferEqual (BRGenericTransfer t1, BRGenericTransfer t2); extern BRGenericTransfer genTransferCopy (const BRGenericTransfer transfer); extern uint8_t * genTransferSerialize (BRGenericTransfer transfer, size_t *bytesCount); extern BRSetOf (BRGenericTransfer) genTransferSetCreate (size_t capacity); // MARK: - Generic Wallet /// Create the primary wallet. The `account` is provided because wallet's create transfers which /// requires addresses that are derived from account properties. /// /// @param account The account to use for addresses derived from public keys, tyically. /// extern BRGenericWallet genWalletCreate (BRGenericAccount account); extern void genWalletRelease (BRGenericWallet wallet); extern UInt256 genWalletGetBalance (BRGenericWallet wallet); extern UInt256 genWalletGetBalanceLimit (BRGenericWallet wallet, BRCryptoBoolean asMaximum, BRCryptoBoolean *hasLimit); extern BRGenericAddress genWalletGetAddress (BRGenericWallet wid); extern int genWalletHasAddress (BRGenericWallet wallet, BRGenericAddress address); extern BRGenericFeeBasis genWalletGetDefaultFeeBasis (BRGenericWallet wid); extern void genWalletSetDefaultFeeBasis (BRGenericWallet wid, BRGenericFeeBasis bid); extern int genWalletHasTransfer (BRGenericWallet wallet, BRGenericTransfer transfer); extern void genWalletAddTransfer (BRGenericWallet wallet, OwnershipKept BRGenericTransfer transfer); extern void genWalletRemTransfer (BRGenericWallet wallet, OwnershipKept BRGenericTransfer transfer); extern BRGenericTransfer genWalletCreateTransfer (BRGenericWallet wid, BRGenericAddress target, UInt256 amount, BRGenericFeeBasis estimatedFeeBasis); extern BRGenericTransfer genWalletCreateTransferWithAttributes (BRGenericWallet wid, BRGenericAddress target, UInt256 amount, BRGenericFeeBasis estimatedFeeBasis, OwnershipKept BRArrayOf(BRGenericTransferAttribute) attributes); extern BRGenericFeeBasis genWalletEstimateTransferFee (BRGenericWallet wid, BRGenericAddress target, UInt256 amount, UInt256 pricePerCostFactor); extern size_t genWalletGetTransferAttributeCount (BRGenericWallet wid, BRGenericAddress target); extern OwnershipGiven BRGenericTransferAttribute genWalletGetTransferAttributeAt (BRGenericWallet wid, BRGenericAddress target, size_t index); extern BRCryptoBoolean genWalletHasTransferAttributeForKey (BRGenericWallet wallet, BRGenericAddress target, const char *key, const char **keyFound, BRCryptoBoolean *isRequired); extern BRCryptoBoolean genWalletValidateTransferAttribute (BRGenericWallet wid, BRGenericTransferAttribute attribute); extern BRCryptoBoolean genWalletValidateTransferAttributes (BRGenericWallet wid, OwnershipKept BRArrayOf(BRGenericTransferAttribute) attributes); // MARK: Generic (Wallet) Manager extern BRGenericManager genManagerCreate (BRGenericClient client, const char *type, BRGenericNetwork network, BRGenericAccount account, uint64_t accountTimestamp, const char *storagePath, uint32_t syncPeriodInSeconds, uint64_t blockHeight); extern void genManagerRelease (BRGenericManager gwm); extern void genManagerStop (BRGenericManager gwm); extern void genManagerConnect (BRGenericManager gwm); extern void genManagerDisconnect (BRGenericManager gwm); extern void genManagerSync (BRGenericManager gwm); #if 0 extern BRArrayOf (BRGenericTransfer) // BRSetOf genManagerRestorePersistentTransfers (BRGenericManager gwm); extern void genManagerPersistTransfer (BRGenericManager gwm, BRGenericTransfer tid); #endif extern BRGenericAddress genManagerGetAccountAddress (BRGenericManager gwm); extern BRGenericWallet genManagerGetPrimaryWallet (BRGenericManager gwm); extern BRGenericAccount genManagerGetAccount (BRGenericManager gwm); extern BRGenericNetwork genManagerGetNetwork (BRGenericManager gwm); extern BRGenericClient genManagerGetClient (BRGenericManager gwm); extern BRGenericTransfer genManagerRecoverTransfer (BRGenericManager gwm, BRGenericWallet wallet, const char *hash, const char *uids, const char *from, const char *to, const char *amount, const char *currency, const char *fee, uint64_t timestamp, uint64_t blockHeight, int error); extern void genManagerWipe (BRGenericNetwork network, const char *storagePath); extern BRArrayOf(BRGenericTransfer) genManagerRecoverTransfersFromRawTransaction (BRGenericManager gwm, uint8_t *bytes, size_t bytesCount, uint64_t timestamp, uint64_t blockHeight); extern int genManagerSignTransfer (BRGenericManager gwm, BRGenericWallet wid, BRGenericTransfer transfer, UInt512 seed); extern int genManagerSignTransferWithKey (BRGenericManager gwm, BRGenericWallet wid, BRGenericTransfer transfer, BRKey *key); extern void genManagerSubmitTransfer (BRGenericManager gwm, BRGenericWallet wid, BRGenericTransfer transfer); extern BRArrayOf(BRGenericTransfer) genManagerLoadTransfers (BRGenericManager gwm); extern void genManagerSaveTransfer (BRGenericManager gwm, BRGenericTransfer transfer); #endif /* BRGeneric_h */

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/Engine/lib/curl/src/tool_formparse.c

927d3c1492854e836bca1b3f7a15e7341225226e

[ "MIT", "LicenseRef-scancode-unknown", "curl" ]

permissive

TorqueGameEngines/Torque3D

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a445a4364664e299196bd551d213844486080145

refs/heads/development

2023-09-03T12:40:40.658487

2023-08-24T14:44:43

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178

MIT

2023-09-13T14:28:16

2020-05-27T22:35:54

C++

UTF-8

C

false

25,895

c

tool_formparse.c

/*************************************************************************** * _ _ ____ _ * Project ___| | | | _ \| | * / __| | | | |_) | | * | (__| |_| | _ <| |___ * \___|\___/|_| \_\_____| * * Copyright (C) 1998 - 2022, Daniel Stenberg, <daniel@haxx.se>, et al. * * This software is licensed as described in the file COPYING, which * you should have received as part of this distribution. The terms * are also available at https://curl.se/docs/copyright.html. * * You may opt to use, copy, modify, merge, publish, distribute and/or sell * copies of the Software, and permit persons to whom the Software is * furnished to do so, under the terms of the COPYING file. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * * SPDX-License-Identifier: curl * ***************************************************************************/ #include "tool_setup.h" #include "strcase.h" #define ENABLE_CURLX_PRINTF /* use our own printf() functions */ #include "curlx.h" #include "tool_cfgable.h" #include "tool_msgs.h" #include "tool_binmode.h" #include "tool_getparam.h" #include "tool_paramhlp.h" #include "tool_formparse.h" #include "memdebug.h" /* keep this as LAST include */ /* Macros to free const pointers. */ #define CONST_FREE(x) free((void *) (x)) #define CONST_SAFEFREE(x) Curl_safefree(*((void **) &(x))) /* tool_mime functions. */ static struct tool_mime *tool_mime_new(struct tool_mime *parent, toolmimekind kind) { struct tool_mime *m = (struct tool_mime *) calloc(1, sizeof(*m)); if(m) { m->kind = kind; m->parent = parent; if(parent) { m->prev = parent->subparts; parent->subparts = m; } } return m; } static struct tool_mime *tool_mime_new_parts(struct tool_mime *parent) { return tool_mime_new(parent, TOOLMIME_PARTS); } static struct tool_mime *tool_mime_new_data(struct tool_mime *parent, const char *data) { struct tool_mime *m = NULL; data = strdup(data); if(data) { m = tool_mime_new(parent, TOOLMIME_DATA); if(!m) CONST_FREE(data); else m->data = data; } return m; } static struct tool_mime *tool_mime_new_filedata(struct tool_mime *parent, const char *filename, bool isremotefile, CURLcode *errcode) { CURLcode result = CURLE_OK; struct tool_mime *m = NULL; *errcode = CURLE_OUT_OF_MEMORY; if(strcmp(filename, "-")) { /* This is a normal file. */ filename = strdup(filename); if(filename) { m = tool_mime_new(parent, TOOLMIME_FILE); if(!m) CONST_FREE(filename); else { m->data = filename; if(!isremotefile) m->kind = TOOLMIME_FILEDATA; *errcode = CURLE_OK; } } } else { /* Standard input. */ int fd = fileno(stdin); char *data = NULL; curl_off_t size; curl_off_t origin; struct_stat sbuf; set_binmode(stdin); origin = ftell(stdin); /* If stdin is a regular file, do not buffer data but read it when needed. */ if(fd >= 0 && origin >= 0 && !fstat(fd, &sbuf) && #ifdef __VMS sbuf.st_fab_rfm != FAB$C_VAR && sbuf.st_fab_rfm != FAB$C_VFC && #endif S_ISREG(sbuf.st_mode)) { size = sbuf.st_size - origin; if(size < 0) size = 0; } else { /* Not suitable for direct use, buffer stdin data. */ size_t stdinsize = 0; switch(file2memory(&data, &stdinsize, stdin)) { case PARAM_NO_MEM: return m; case PARAM_READ_ERROR: result = CURLE_READ_ERROR; break; default: if(!stdinsize) { /* Zero-length data has been freed. Re-create it. */ data = strdup(""); if(!data) return m; } break; } size = curlx_uztoso(stdinsize); origin = 0; } m = tool_mime_new(parent, TOOLMIME_STDIN); if(!m) Curl_safefree(data); else { m->data = data; m->origin = origin; m->size = size; m->curpos = 0; if(!isremotefile) m->kind = TOOLMIME_STDINDATA; *errcode = result; } } return m; } void tool_mime_free(struct tool_mime *mime) { if(mime) { if(mime->subparts) tool_mime_free(mime->subparts); if(mime->prev) tool_mime_free(mime->prev); CONST_SAFEFREE(mime->name); CONST_SAFEFREE(mime->filename); CONST_SAFEFREE(mime->type); CONST_SAFEFREE(mime->encoder); CONST_SAFEFREE(mime->data); curl_slist_free_all(mime->headers); free(mime); } } /* Mime part callbacks for stdin. */ size_t tool_mime_stdin_read(char *buffer, size_t size, size_t nitems, void *arg) { struct tool_mime *sip = (struct tool_mime *) arg; curl_off_t bytesleft; (void) size; /* Always 1: ignored. */ if(sip->size >= 0) { if(sip->curpos >= sip->size) return 0; /* At eof. */ bytesleft = sip->size - sip->curpos; if(curlx_uztoso(nitems) > bytesleft) nitems = curlx_sotouz(bytesleft); } if(nitems) { if(sip->data) { /* Return data from memory. */ memcpy(buffer, sip->data + curlx_sotouz(sip->curpos), nitems); } else { /* Read from stdin. */ nitems = fread(buffer, 1, nitems, stdin); if(ferror(stdin)) { /* Show error only once. */ if(sip->config) { warnf(sip->config, "stdin: %s\n", strerror(errno)); sip->config = NULL; } return CURL_READFUNC_ABORT; } } sip->curpos += curlx_uztoso(nitems); } return nitems; } int tool_mime_stdin_seek(void *instream, curl_off_t offset, int whence) { struct tool_mime *sip = (struct tool_mime *) instream; switch(whence) { case SEEK_CUR: offset += sip->curpos; break; case SEEK_END: offset += sip->size; break; } if(offset < 0) return CURL_SEEKFUNC_CANTSEEK; if(!sip->data) { if(fseek(stdin, (long) (offset + sip->origin), SEEK_SET)) return CURL_SEEKFUNC_CANTSEEK; } sip->curpos = offset; return CURL_SEEKFUNC_OK; } /* Translate an internal mime tree into a libcurl mime tree. */ static CURLcode tool2curlparts(CURL *curl, struct tool_mime *m, curl_mime *mime) { CURLcode ret = CURLE_OK; curl_mimepart *part = NULL; curl_mime *submime = NULL; const char *filename = NULL; if(m) { ret = tool2curlparts(curl, m->prev, mime); if(!ret) { part = curl_mime_addpart(mime); if(!part) ret = CURLE_OUT_OF_MEMORY; } if(!ret) { filename = m->filename; switch(m->kind) { case TOOLMIME_PARTS: ret = tool2curlmime(curl, m, &submime); if(!ret) { ret = curl_mime_subparts(part, submime); if(ret) curl_mime_free(submime); } break; case TOOLMIME_DATA: ret = curl_mime_data(part, m->data, CURL_ZERO_TERMINATED); break; case TOOLMIME_FILE: case TOOLMIME_FILEDATA: ret = curl_mime_filedata(part, m->data); if(!ret && m->kind == TOOLMIME_FILEDATA && !filename) ret = curl_mime_filename(part, NULL); break; case TOOLMIME_STDIN: if(!filename) filename = "-"; /* FALLTHROUGH */ case TOOLMIME_STDINDATA: ret = curl_mime_data_cb(part, m->size, (curl_read_callback) tool_mime_stdin_read, (curl_seek_callback) tool_mime_stdin_seek, NULL, m); break; default: /* Other cases not possible in this context. */ break; } } if(!ret && filename) ret = curl_mime_filename(part, filename); if(!ret) ret = curl_mime_type(part, m->type); if(!ret) ret = curl_mime_headers(part, m->headers, 0); if(!ret) ret = curl_mime_encoder(part, m->encoder); if(!ret) ret = curl_mime_name(part, m->name); } return ret; } CURLcode tool2curlmime(CURL *curl, struct tool_mime *m, curl_mime **mime) { CURLcode ret = CURLE_OK; *mime = curl_mime_init(curl); if(!*mime) ret = CURLE_OUT_OF_MEMORY; else ret = tool2curlparts(curl, m->subparts, *mime); if(ret) { curl_mime_free(*mime); *mime = NULL; } return ret; } /* * helper function to get a word from form param * after call get_parm_word, str either point to string end * or point to any of end chars. */ static char *get_param_word(struct OperationConfig *config, char **str, char **end_pos, char endchar) { char *ptr = *str; /* the first non-space char is here */ char *word_begin = ptr; char *ptr2; char *escape = NULL; if(*ptr == '"') { ++ptr; while(*ptr) { if(*ptr == '\\') { if(ptr[1] == '\\' || ptr[1] == '"') { /* remember the first escape position */ if(!escape) escape = ptr; /* skip escape of back-slash or double-quote */ ptr += 2; continue; } } if(*ptr == '"') { bool trailing_data = FALSE; *end_pos = ptr; if(escape) { /* has escape, we restore the unescaped string here */ ptr = ptr2 = escape; do { if(*ptr == '\\' && (ptr[1] == '\\' || ptr[1] == '"')) ++ptr; *ptr2++ = *ptr++; } while(ptr < *end_pos); *end_pos = ptr2; } ++ptr; while(*ptr && *ptr != ';' && *ptr != endchar) { if(!ISSPACE(*ptr)) trailing_data = TRUE; ++ptr; } if(trailing_data) warnf(config->global, "Trailing data after quoted form parameter\n"); *str = ptr; return word_begin + 1; } ++ptr; } /* end quote is missing, treat it as non-quoted. */ ptr = word_begin; } while(*ptr && *ptr != ';' && *ptr != endchar) ++ptr; *str = *end_pos = ptr; return word_begin; } /* Append slist item and return -1 if failed. */ static int slist_append(struct curl_slist **plist, const char *data) { struct curl_slist *s = curl_slist_append(*plist, data); if(!s) return -1; *plist = s; return 0; } /* Read headers from a file and append to list. */ static int read_field_headers(struct OperationConfig *config, const char *filename, FILE *fp, struct curl_slist **pheaders) { size_t hdrlen = 0; size_t pos = 0; bool incomment = FALSE; int lineno = 1; char hdrbuf[999] = ""; /* Max. header length + 1. */ for(;;) { int c = getc(fp); if(c == EOF || (!pos && !ISSPACE(c))) { /* Strip and flush the current header. */ while(hdrlen && ISSPACE(hdrbuf[hdrlen - 1])) hdrlen--; if(hdrlen) { hdrbuf[hdrlen] = '\0'; if(slist_append(pheaders, hdrbuf)) { fprintf(config->global->errors, "Out of memory for field headers!\n"); return -1; } hdrlen = 0; } } switch(c) { case EOF: if(ferror(fp)) { fprintf(config->global->errors, "Header file %s read error: %s\n", filename, strerror(errno)); return -1; } return 0; /* Done. */ case '\r': continue; /* Ignore. */ case '\n': pos = 0; incomment = FALSE; lineno++; continue; case '#': if(!pos) incomment = TRUE; break; } pos++; if(!incomment) { if(hdrlen == sizeof(hdrbuf) - 1) { warnf(config->global, "File %s line %d: header too long (truncated)\n", filename, lineno); c = ' '; } if(hdrlen <= sizeof(hdrbuf) - 1) hdrbuf[hdrlen++] = (char) c; } } /* NOTREACHED */ } static int get_param_part(struct OperationConfig *config, char endchar, char **str, char **pdata, char **ptype, char **pfilename, char **pencoder, struct curl_slist **pheaders) { char *p = *str; char *type = NULL; char *filename = NULL; char *encoder = NULL; char *endpos; char *tp; char sep; char type_major[128] = ""; char type_minor[128] = ""; char *endct = NULL; struct curl_slist *headers = NULL; if(ptype) *ptype = NULL; if(pfilename) *pfilename = NULL; if(pheaders) *pheaders = NULL; if(pencoder) *pencoder = NULL; while(ISSPACE(*p)) p++; tp = p; *pdata = get_param_word(config, &p, &endpos, endchar); /* If not quoted, strip trailing spaces. */ if(*pdata == tp) while(endpos > *pdata && ISSPACE(endpos[-1])) endpos--; sep = *p; *endpos = '\0'; while(sep == ';') { while(ISSPACE(*++p)) ; if(!endct && checkprefix("type=", p)) { for(p += 5; ISSPACE(*p); p++) ; /* set type pointer */ type = p; /* verify that this is a fine type specifier */ if(2 != sscanf(type, "%127[^/ ]/%127[^;, \n]", type_major, type_minor)) { warnf(config->global, "Illegally formatted content-type field!\n"); curl_slist_free_all(headers); return -1; /* illegal content-type syntax! */ } /* now point beyond the content-type specifier */ p = type + strlen(type_major) + strlen(type_minor) + 1; for(endct = p; *p && *p != ';' && *p != endchar; p++) if(!ISSPACE(*p)) endct = p + 1; sep = *p; } else if(checkprefix("filename=", p)) { if(endct) { *endct = '\0'; endct = NULL; } for(p += 9; ISSPACE(*p); p++) ; tp = p; filename = get_param_word(config, &p, &endpos, endchar); /* If not quoted, strip trailing spaces. */ if(filename == tp) while(endpos > filename && ISSPACE(endpos[-1])) endpos--; sep = *p; *endpos = '\0'; } else if(checkprefix("headers=", p)) { if(endct) { *endct = '\0'; endct = NULL; } p += 8; if(*p == '@' || *p == '<') { char *hdrfile; FILE *fp; /* Read headers from a file. */ do { p++; } while(ISSPACE(*p)); tp = p; hdrfile = get_param_word(config, &p, &endpos, endchar); /* If not quoted, strip trailing spaces. */ if(hdrfile == tp) while(endpos > hdrfile && ISSPACE(endpos[-1])) endpos--; sep = *p; *endpos = '\0'; fp = fopen(hdrfile, FOPEN_READTEXT); if(!fp) warnf(config->global, "Cannot read from %s: %s\n", hdrfile, strerror(errno)); else { int i = read_field_headers(config, hdrfile, fp, &headers); fclose(fp); if(i) { curl_slist_free_all(headers); return -1; } } } else { char *hdr; while(ISSPACE(*p)) p++; tp = p; hdr = get_param_word(config, &p, &endpos, endchar); /* If not quoted, strip trailing spaces. */ if(hdr == tp) while(endpos > hdr && ISSPACE(endpos[-1])) endpos--; sep = *p; *endpos = '\0'; if(slist_append(&headers, hdr)) { fprintf(config->global->errors, "Out of memory for field header!\n"); curl_slist_free_all(headers); return -1; } } } else if(checkprefix("encoder=", p)) { if(endct) { *endct = '\0'; endct = NULL; } for(p += 8; ISSPACE(*p); p++) ; tp = p; encoder = get_param_word(config, &p, &endpos, endchar); /* If not quoted, strip trailing spaces. */ if(encoder == tp) while(endpos > encoder && ISSPACE(endpos[-1])) endpos--; sep = *p; *endpos = '\0'; } else if(endct) { /* This is part of content type. */ for(endct = p; *p && *p != ';' && *p != endchar; p++) if(!ISSPACE(*p)) endct = p + 1; sep = *p; } else { /* unknown prefix, skip to next block */ char *unknown = get_param_word(config, &p, &endpos, endchar); sep = *p; *endpos = '\0'; if(*unknown) warnf(config->global, "skip unknown form field: %s\n", unknown); } } /* Terminate content type. */ if(endct) *endct = '\0'; if(ptype) *ptype = type; else if(type) warnf(config->global, "Field content type not allowed here: %s\n", type); if(pfilename) *pfilename = filename; else if(filename) warnf(config->global, "Field file name not allowed here: %s\n", filename); if(pencoder) *pencoder = encoder; else if(encoder) warnf(config->global, "Field encoder not allowed here: %s\n", encoder); if(pheaders) *pheaders = headers; else if(headers) { warnf(config->global, "Field headers not allowed here: %s\n", headers->data); curl_slist_free_all(headers); } *str = p; return sep & 0xFF; } /*************************************************************************** * * formparse() * * Reads a 'name=value' parameter and builds the appropriate linked list. * * If the value is of the form '<filename', field data is read from the * given file. * Specify files to upload with 'name=@filename', or 'name=@"filename"' * in case the filename contain ',' or ';'. Supports specified * given Content-Type of the files. Such as ';type=<content-type>'. * * If literal_value is set, any initial '@' or '<' in the value string * loses its special meaning, as does any embedded ';type='. * * You may specify more than one file for a single name (field). Specify * multiple files by writing it like: * * 'name=@filename,filename2,filename3' * * or use double-quotes quote the filename: * * 'name=@"filename","filename2","filename3"' * * If you want content-types specified for each too, write them like: * * 'name=@filename;type=image/gif,filename2,filename3' * * If you want custom headers added for a single part, write them in a separate * file and do like this: * * 'name=foo;headers=@headerfile' or why not * 'name=@filemame;headers=@headerfile' * * To upload a file, but to fake the file name that will be included in the * formpost, do like this: * * 'name=@filename;filename=/dev/null' or quote the faked filename like: * 'name=@filename;filename="play, play, and play.txt"' * * If filename/path contains ',' or ';', it must be quoted by double-quotes, * else curl will fail to figure out the correct filename. if the filename * tobe quoted contains '"' or '\', '"' and '\' must be escaped by backslash. * ***************************************************************************/ /* Convenience macros for null pointer check. */ #define NULL_CHECK(ptr, init, retcode) \ do { \ (ptr) = (init); \ if(!(ptr)) { \ warnf(config->global, "out of memory!\n"); \ curl_slist_free_all(headers); \ Curl_safefree(contents); \ return retcode; \ } \ } while(0) #define SET_TOOL_MIME_PTR(m, field, retcode) \ do { \ if(field) \ NULL_CHECK((m)->field, strdup(field), retcode); \ } while(0) int formparse(struct OperationConfig *config, const char *input, struct tool_mime **mimeroot, struct tool_mime **mimecurrent, bool literal_value) { /* input MUST be a string in the format 'name=contents' and we'll build a linked list with the info */ char *name = NULL; char *contents = NULL; char *contp; char *data; char *type = NULL; char *filename = NULL; char *encoder = NULL; struct curl_slist *headers = NULL; struct tool_mime *part = NULL; CURLcode res; /* Allocate the main mime structure if needed. */ if(!*mimecurrent) { NULL_CHECK(*mimeroot, tool_mime_new_parts(NULL), 1); *mimecurrent = *mimeroot; } /* Make a copy we can overwrite. */ NULL_CHECK(contents, strdup(input), 2); /* Scan for the end of the name. */ contp = strchr(contents, '='); if(contp) { int sep = '\0'; if(contp > contents) name = contents; *contp++ = '\0'; if(*contp == '(' && !literal_value) { /* Starting a multipart. */ sep = get_param_part(config, '\0', &contp, &data, &type, NULL, NULL, &headers); if(sep < 0) { Curl_safefree(contents); return 3; } NULL_CHECK(part, tool_mime_new_parts(*mimecurrent), 4); *mimecurrent = part; part->headers = headers; headers = NULL; SET_TOOL_MIME_PTR(part, type, 5); } else if(!name && !strcmp(contp, ")") && !literal_value) { /* Ending a multipart. */ if(*mimecurrent == *mimeroot) { warnf(config->global, "no multipart to terminate!\n"); Curl_safefree(contents); return 6; } *mimecurrent = (*mimecurrent)->parent; } else if('@' == contp[0] && !literal_value) { /* we use the @-letter to indicate file name(s) */ struct tool_mime *subparts = NULL; do { /* since this was a file, it may have a content-type specifier at the end too, or a filename. Or both. */ ++contp; sep = get_param_part(config, ',', &contp, &data, &type, &filename, &encoder, &headers); if(sep < 0) { Curl_safefree(contents); return 7; } /* now contp point to comma or string end. If more files to come, make sure we have multiparts. */ if(!subparts) { if(sep != ',') /* If there is a single file. */ subparts = *mimecurrent; else NULL_CHECK(subparts, tool_mime_new_parts(*mimecurrent), 8); } /* Store that file in a part. */ NULL_CHECK(part, tool_mime_new_filedata(subparts, data, TRUE, &res), 9); part->headers = headers; headers = NULL; part->config = config->global; if(res == CURLE_READ_ERROR) { /* An error occurred while reading stdin: if read has started, issue the error now. Else, delay it until processed by libcurl. */ if(part->size > 0) { warnf(config->global, "error while reading standard input\n"); Curl_safefree(contents); return 10; } CONST_SAFEFREE(part->data); part->data = NULL; part->size = -1; res = CURLE_OK; } SET_TOOL_MIME_PTR(part, filename, 11); SET_TOOL_MIME_PTR(part, type, 12); SET_TOOL_MIME_PTR(part, encoder, 13); /* *contp could be '\0', so we just check with the delimiter */ } while(sep); /* loop if there's another file name */ part = (*mimecurrent)->subparts; /* Set name on group. */ } else { if(*contp == '<' && !literal_value) { ++contp; sep = get_param_part(config, '\0', &contp, &data, &type, NULL, &encoder, &headers); if(sep < 0) { Curl_safefree(contents); return 14; } NULL_CHECK(part, tool_mime_new_filedata(*mimecurrent, data, FALSE, &res), 15); part->headers = headers; headers = NULL; part->config = config->global; if(res == CURLE_READ_ERROR) { /* An error occurred while reading stdin: if read has started, issue the error now. Else, delay it until processed by libcurl. */ if(part->size > 0) { warnf(config->global, "error while reading standard input\n"); Curl_safefree(contents); return 16; } CONST_SAFEFREE(part->data); part->data = NULL; part->size = -1; res = CURLE_OK; } } else { if(literal_value) data = contp; else { sep = get_param_part(config, '\0', &contp, &data, &type, &filename, &encoder, &headers); if(sep < 0) { Curl_safefree(contents); return 17; } } NULL_CHECK(part, tool_mime_new_data(*mimecurrent, data), 18); part->headers = headers; headers = NULL; } SET_TOOL_MIME_PTR(part, filename, 19); SET_TOOL_MIME_PTR(part, type, 20); SET_TOOL_MIME_PTR(part, encoder, 21); if(sep) { *contp = (char) sep; warnf(config->global, "garbage at end of field specification: %s\n", contp); } } /* Set part name. */ SET_TOOL_MIME_PTR(part, name, 22); } else { warnf(config->global, "Illegally formatted input field!\n"); Curl_safefree(contents); return 23; } Curl_safefree(contents); return 0; }

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/bddisasm/include/instructions.h

8b810a929e722272908bd256c551e8b0abe58322

[ "Apache-2.0" ]

permissive

bitdefender/bddisasm

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refs/heads/master

2023-08-05T12:04:25.453259

2023-07-21T07:14:31

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817

117

Apache-2.0

2023-06-27T11:57:17

2020-07-09T12:30:49

C

UTF-8

C

false

1,900,040

h

instructions.h

/* * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ // // This file was auto-generated by generate_tables.py. DO NOT MODIFY! // #ifndef INSTRUCTIONS_H #define INSTRUCTIONS_H const ND_INSTRUCTION gInstructions[2780] = { // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" { ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" { ND_INS_AAD, ND_CAT_DECIMAL, ND_SET_I86, 1, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" { ND_INS_AADD, ND_CAT_RAOINT, ND_SET_RAOINT, 2, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:3 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" { ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 3, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:4 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR" { ND_INS_AAND, ND_CAT_RAOINT, ND_SET_RAOINT, 4, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:5 Instruction:"AAS" Encoding:"0x3F"/"" { ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 5, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:6 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:7 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:8 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:9 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:10 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:11 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:13 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:14 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:15 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" { ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:16 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" { ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 7, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, 0|NDR_RFLAG_CF, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:17 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:18 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:19 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:20 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:21 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:22 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:24 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:25 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:26 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" { ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:27 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" { ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 9, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:28 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" { ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 10, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:29 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" { ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 11, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:30 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" { ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 12, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:31 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" { ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 13, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:32 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" { ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 14, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:33 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" { ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 15, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, 0, 0|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:34 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" { ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 16, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:35 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" { ND_INS_AESDEC128KL, ND_CAT_AESKL, ND_SET_KL, 17, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:36 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" { ND_INS_AESDEC256KL, ND_CAT_AESKL, ND_SET_KL, 18, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:37 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" { ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 19, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:38 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" { ND_INS_AESDECWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 20, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:39 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" { ND_INS_AESDECWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 21, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:40 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" { ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 22, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:41 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" { ND_INS_AESENC128KL, ND_CAT_AESKL, ND_SET_KL, 23, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:42 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" { ND_INS_AESENC256KL, ND_CAT_AESKL, ND_SET_KL, 24, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:43 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" { ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 25, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:44 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" { ND_INS_AESENCWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 26, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:45 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" { ND_INS_AESENCWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 27, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:46 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" { ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 28, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:47 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" { ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 29, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:48 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" { ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 30, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:49 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:50 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:51 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:52 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:53 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:54 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:55 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:56 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:57 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:58 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" { ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:59 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" { ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 32, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:60 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" { ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 33, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:61 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" { ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 34, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:62 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" { ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 35, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:63 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" { ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 36, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:64 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" { ND_INS_AOR, ND_CAT_RAOINT, ND_SET_RAOINT, 37, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:65 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" { ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 38, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:66 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" { ND_INS_AXOR, ND_CAT_RAOINT, ND_SET_RAOINT, 39, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:67 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 40, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:68 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" { ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 40, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:69 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" { ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 41, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:70 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" { ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 42, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:71 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" { ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 43, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:72 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" { ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 44, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:73 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" { ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 45, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:74 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" { ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 46, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:75 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" { ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 47, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:76 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" { ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 48, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:77 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" { ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 49, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:78 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" { ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 50, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:79 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" { ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 51, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:80 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" { ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 52, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:81 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" { ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 53, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:82 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" { ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 54, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:83 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" { ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 55, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:84 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" { ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 56, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:85 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" { ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 57, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:86 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM" { ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 58, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_R, 0, 0), }, }, // Pos:87 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" { ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 59, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:88 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" { ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_R, 0, 0), }, }, // Pos:89 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" { ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), }, }, // Pos:90 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR" { ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 61, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), }, }, // Pos:91 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" { ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 62, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_a, 0, ND_OPA_R, 0, 0), }, }, // Pos:92 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" { ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 63, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:93 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" { ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 64, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:94 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:95 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:96 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:97 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:98 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:99 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:100 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:101 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" { ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:102 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" { ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:103 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" { ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:104 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" { ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 67, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:105 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" { ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 67, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:106 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" { ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:107 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" { ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:108 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" { ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:109 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" { ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:110 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" { ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 70, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:111 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" { ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 71, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:112 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" { ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 71, ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:113 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" { ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 72, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:114 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" { ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 72, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:115 Instruction:"CBW" Encoding:"ds16 0x98"/"" { ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 73, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:116 Instruction:"CDQ" Encoding:"ds32 0x99"/"" { ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 74, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:117 Instruction:"CDQE" Encoding:"ds64 0x98"/"" { ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 75, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:118 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" { ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 76, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 0, 0, 0, 0|NDR_RFLAG_AC, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:119 Instruction:"CLC" Encoding:"0xF8"/"" { ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 77, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:120 Instruction:"CLD" Encoding:"0xFC"/"" { ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 78, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:121 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" { ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 79, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:122 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" { ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 80, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), }, }, // Pos:123 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" { ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 81, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), }, }, // Pos:124 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" { ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 82, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:125 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" { ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 83, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:126 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" { ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 84, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:127 Instruction:"CLI" Encoding:"0xFA"/"" { ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 85, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:128 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" { ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 86, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:129 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" { ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 87, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:130 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" { ND_INS_CLUI, ND_CAT_UINTR, ND_SET_UINTR, 88, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 0, 0, 0, 0, { OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:131 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" { ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 89, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:132 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" { ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 90, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:133 Instruction:"CMC" Encoding:"0xF5"/"" { ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 91, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:134 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:135 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:136 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:137 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:138 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:139 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:140 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:141 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:142 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:143 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:144 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:145 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:146 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 104, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:147 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 105, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:148 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 106, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:149 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" { ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 107, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:150 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:151 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:152 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:153 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:154 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:155 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:156 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:157 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:158 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:159 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" { ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:160 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" { ND_INS_CMPBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:161 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" { ND_INS_CMPCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:162 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" { ND_INS_CMPLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:163 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" { ND_INS_CMPLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:164 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" { ND_INS_CMPNBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:165 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" { ND_INS_CMPNCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:166 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" { ND_INS_CMPNLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:167 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" { ND_INS_CMPNLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:168 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" { ND_INS_CMPNOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:169 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" { ND_INS_CMPNPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:170 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" { ND_INS_CMPNSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 119, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:171 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" { ND_INS_CMPNZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:172 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" { ND_INS_CMPOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:173 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 122, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:174 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 123, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:175 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" { ND_INS_CMPPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:176 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:177 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:178 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 126, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:179 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:180 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:181 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:182 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:183 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" { ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 128, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:184 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:185 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" { ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:186 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" { ND_INS_CMPSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:187 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" { ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:188 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" { ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:189 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" { ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 132, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:190 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" { ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 133, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:191 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" { ND_INS_CMPZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 134, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:192 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" { ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 135, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:193 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" { ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 136, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:194 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" { ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:195 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" { ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 138, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:196 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" { ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 139, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:197 Instruction:"CQO" Encoding:"ds64 0x99"/"" { ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 140, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:198 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:199 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:200 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:201 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" { ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:202 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" { ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 142, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:203 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" { ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 143, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:204 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" { ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 144, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:205 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" { ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 145, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:206 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" { ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 146, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:207 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" { ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 147, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:208 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" { ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 148, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:209 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" { ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 149, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:210 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" { ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 150, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:211 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" { ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 151, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:212 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" { ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 152, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:213 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" { ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 153, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:214 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" { ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 154, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:215 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" { ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 155, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:216 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" { ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 156, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:217 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" { ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 157, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:218 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" { ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 158, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:219 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" { ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 159, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:220 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" { ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 160, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:221 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" { ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 161, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:222 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" { ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 162, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:223 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" { ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 163, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:224 Instruction:"CWD" Encoding:"ds16 0x99"/"" { ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 164, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:225 Instruction:"CWDE" Encoding:"ds32 0x98"/"" { ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 165, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:226 Instruction:"DAA" Encoding:"0x27"/"" { ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, 0|NDR_RFLAG_OF, 0|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:227 Instruction:"DAS" Encoding:"0x2F"/"" { ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_OF, 0|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:228 Instruction:"DEC Zv" Encoding:"0x48"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:229 Instruction:"DEC Zv" Encoding:"0x49"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:230 Instruction:"DEC Zv" Encoding:"0x4A"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:231 Instruction:"DEC Zv" Encoding:"0x4B"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:232 Instruction:"DEC Zv" Encoding:"0x4C"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:233 Instruction:"DEC Zv" Encoding:"0x4D"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:234 Instruction:"DEC Zv" Encoding:"0x4E"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:235 Instruction:"DEC Zv" Encoding:"0x4F"/"O" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:236 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:237 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" { ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:238 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" { ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:239 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" { ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:240 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" { ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:241 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" { ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 171, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:242 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" { ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 172, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:243 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" { ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 173, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:244 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" { ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 174, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:245 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" { ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { 0 }, }, // Pos:246 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" { ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 176, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:247 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" { ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 177, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:248 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" { ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 178, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, 0, 0, 0, 0, { 0 }, }, // Pos:249 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" { ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 179, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), }, }, // Pos:250 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" { ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 180, 0, ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), }, }, // Pos:251 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" { ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 181, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), }, }, // Pos:252 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" { ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 182, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), OP(ND_OPT_SSE_XMM4, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:253 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" { ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 183, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 2), OP(ND_OPT_SSE_XMM2, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 5), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:254 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" { ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 184, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 0, 0, 0, 0, { 0 }, }, // Pos:255 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" { ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 185, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, 0, 0, 0, 0, { 0 }, }, // Pos:256 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 186, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:257 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 187, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:258 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" { ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 188, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:259 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" { ND_INS_ERETS, ND_CAT_RET, ND_SET_FRED, 189, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, 0, 0, 0, 0, { OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), }, }, // Pos:260 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" { ND_INS_ERETU, ND_CAT_RET, ND_SET_FRED, 190, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, 0, 0, 0, 0, { OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:261 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" { ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 191, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:262 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" { ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:263 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" { ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:264 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" { ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 193, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:265 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" { ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 194, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:266 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:267 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:268 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:269 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" { ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:270 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" { ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 196, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:271 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" { ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 197, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:272 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" { ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 198, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:273 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" { ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 199, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:274 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" { ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 200, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:275 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" { ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 201, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:276 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" { ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 202, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:277 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" { ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 203, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:278 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" { ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 204, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:279 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" { ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 205, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:280 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" { ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 206, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:281 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" { ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 207, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:282 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:283 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:284 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:285 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" { ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:286 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" { ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 209, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:287 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" { ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 210, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:288 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:289 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:290 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:291 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:292 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" { ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:293 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" { ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 212, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:294 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" { ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 213, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:295 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" { ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 214, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:296 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:297 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:298 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:299 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" { ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:300 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" { ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 216, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:301 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:302 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:303 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:304 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" { ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:305 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" { ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 218, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:306 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" { ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 219, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, 0, 0, 0, 0, { 0 }, }, // Pos:307 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" { ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 220, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:308 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" { ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 221, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:309 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" { ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:310 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" { ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:311 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" { ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:312 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" { ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:313 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" { ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:314 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" { ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:315 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" { ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:316 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" { ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:317 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" { ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:318 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" { ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:319 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:320 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:321 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" { ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:322 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" { ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:323 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" { ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:324 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" { ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 229, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:325 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" { ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:326 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" { ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:327 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:328 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:329 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" { ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:330 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:331 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:332 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" { ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:333 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" { ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:334 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" { ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:335 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" { ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:336 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" { ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:337 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:338 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:339 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:340 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" { ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:341 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" { ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 236, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:342 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" { ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 237, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:343 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" { ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 238, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:344 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" { ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 239, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:345 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" { ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 240, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:346 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" { ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 241, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:347 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" { ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 242, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:348 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" { ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 243, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:349 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" { ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 244, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:350 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:351 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:352 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:353 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" { ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:354 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" { ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 246, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:355 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" { ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 247, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:356 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" { ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 248, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:357 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" { ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 249, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:358 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:359 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:360 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" { ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:361 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" { ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 251, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:362 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" { ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 252, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:363 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" { ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 253, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:364 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" { ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:365 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" { ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:366 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" { ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 255, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:367 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" { ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 256, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:368 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" { ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 257, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:369 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" { ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 258, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:370 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" { ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 259, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:371 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" { ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 260, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:372 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" { ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 261, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:373 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" { ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 262, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:374 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" { ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 263, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:375 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" { ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 264, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:376 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" { ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 265, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:377 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:378 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:379 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" { ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:380 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" { ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), }, }, // Pos:381 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:382 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:383 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:384 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:385 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:386 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" { ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:387 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" { ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 269, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:388 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" { ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 270, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), }, }, // Pos:389 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:390 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:391 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:392 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" { ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:393 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" { ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 272, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:394 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:395 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:396 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:397 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" { ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:398 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" { ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 274, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:399 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" { ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 275, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:400 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" { ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 276, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:401 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" { ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 277, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:402 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" { ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 278, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_OF, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:403 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" { ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 279, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:404 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" { ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 280, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:405 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" { ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 281, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:406 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:407 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:408 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" { ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:409 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" { ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 283, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:410 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" { ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 284, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:411 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" { ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 285, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:412 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" { ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 286, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:413 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" { ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 287, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:414 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" { ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 288, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:415 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" { ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 289, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:416 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" { ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 290, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:417 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" { ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 291, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:418 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" { ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 292, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:419 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" { ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 293, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:420 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" { ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 294, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:421 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" { ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 295, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:422 Instruction:"HLT" Encoding:"0xF4"/"" { ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 296, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:423 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" { ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 297, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_HRESET, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:424 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" { ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 298, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:425 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" { ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 299, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:426 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" { ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:427 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" { ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:428 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:429 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:430 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:431 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:432 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" { ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:433 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:434 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:435 Instruction:"IN AL,DX" Encoding:"0xEC"/"" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:436 Instruction:"IN eAX,DX" Encoding:"0xED"/"" { ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:437 Instruction:"INC Zv" Encoding:"0x40"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:438 Instruction:"INC Zv" Encoding:"0x41"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:439 Instruction:"INC Zv" Encoding:"0x42"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:440 Instruction:"INC Zv" Encoding:"0x43"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:441 Instruction:"INC Zv" Encoding:"0x44"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:442 Instruction:"INC Zv" Encoding:"0x45"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:443 Instruction:"INC Zv" Encoding:"0x46"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:444 Instruction:"INC Zv" Encoding:"0x47"/"O" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:445 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:446 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" { ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:447 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" { ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 304, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:448 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" { ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 305, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:449 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:450 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:451 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:452 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:453 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" { ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:454 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" { ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:455 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" { ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, 0, ND_MOD_ANY, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:456 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" { ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:457 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:458 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" { ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:459 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" { ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:460 Instruction:"INT1" Encoding:"0xF1"/"" { ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:461 Instruction:"INT3" Encoding:"0xCC"/"" { ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:462 Instruction:"INTO" Encoding:"0xCE"/"" { ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_I64, 0, 0|NDR_RFLAG_VM, 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:463 Instruction:"INVD" Encoding:"0x0F 0x08"/"" { ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 315, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { 0 }, }, // Pos:464 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" { ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 316, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:465 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" { ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 317, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:466 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" { ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 318, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:467 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" { ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 319, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:468 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" { ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 320, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:469 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" { ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 321, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:470 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 322, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:471 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 323, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:472 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" { ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 324, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:473 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:474 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:475 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:476 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:477 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 327, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), }, }, // Pos:478 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 328, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), }, }, // Pos:479 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:480 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:481 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:482 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:483 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" { ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:484 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" { ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:485 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" { ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 331, ND_PREF_BND|ND_PREF_DNT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:486 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" { ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:487 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" { ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:488 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" { ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:489 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" { ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:490 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:491 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:492 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:493 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:494 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:495 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:496 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:497 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:498 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:499 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:500 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:501 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:502 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:503 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:504 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:505 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:506 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:507 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:508 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:509 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:510 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" { ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 344, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), }, }, // Pos:511 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:512 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:513 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:514 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" { ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, ND_PREF_BND|ND_PREF_BHINT, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:515 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:516 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:517 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:518 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" { ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:519 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:520 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:521 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:522 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:523 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:524 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" { ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:525 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:526 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" { ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:527 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" { ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:528 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" { ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:529 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:530 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:531 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:532 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:533 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:534 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:535 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:536 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:537 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:538 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:539 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:540 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:541 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:542 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:543 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:544 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:545 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:546 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:547 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:548 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" { ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:549 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:550 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:551 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:552 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" { ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:553 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:554 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:555 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:556 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:557 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:558 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:559 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" { ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:560 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" { ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:561 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:562 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:563 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:564 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" { ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:565 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:566 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:567 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:568 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" { ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:569 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:570 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:571 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:572 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" { ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:573 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:574 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:575 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" { ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:576 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:577 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:578 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:579 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" { ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:580 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:581 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:582 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:583 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" { ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:584 Instruction:"LAHF" Encoding:"0x9F"/"" { ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 400, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:585 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" { ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:586 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" { ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:587 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" { ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 402, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:588 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" { ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 403, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:589 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" { ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:590 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" { ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), }, }, // Pos:591 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" { ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 406, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_0, 0, ND_OPA_N, 0, 0), }, }, // Pos:592 Instruction:"LEAVE" Encoding:"0xC9"/"" { ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 407, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rBP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:593 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" { ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:594 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" { ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 409, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { 0 }, }, // Pos:595 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" { ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:596 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" { ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 411, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:597 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" { ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:598 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" { ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 413, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:599 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" { ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:600 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" { ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:601 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" { ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 415, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:602 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" { ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:603 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" { ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 417, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:604 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" { ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 418, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:605 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:606 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:607 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:608 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:609 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:610 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:611 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:612 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" { ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:613 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" { ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 423, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:614 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" { ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 424, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:615 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" { ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 425, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:616 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" { ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:617 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" { ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:618 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" { ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:619 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" { ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 428, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:620 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" { ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:621 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" { ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:622 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" { ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 431, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:623 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" { ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 432, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:624 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" { ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 433, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_rDI, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:625 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" { ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 434, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:626 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" { ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 435, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:627 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" { ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 436, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:628 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" { ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 437, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:629 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" { ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 438, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:630 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" { ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 439, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { 0 }, }, // Pos:631 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" { ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 440, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:632 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" { ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 441, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:633 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" { ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 442, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:634 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" { ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 443, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:635 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" { ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 444, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 0, 0, 0, 0, { OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:636 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" { ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 445, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:637 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" { ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 446, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:638 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" { ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:639 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" { ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:640 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" { ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:641 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" { ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:642 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" { ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:643 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" { ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:644 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:645 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:646 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:647 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:648 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:649 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:650 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:651 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:652 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:653 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:654 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:655 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:656 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:657 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:658 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:659 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:660 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:661 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:662 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:663 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:664 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:665 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:666 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:667 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:668 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:669 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:670 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:671 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:672 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:673 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" { ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), }, }, // Pos:674 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" { ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:675 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" { ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:676 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" { ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:677 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" { ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:678 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:679 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:680 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:681 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" { ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), }, }, // Pos:682 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:683 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:684 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_P, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:685 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" { ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:686 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" { ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 452, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:687 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" { ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 453, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, 0, 0, 0, 0, { OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), }, }, // Pos:688 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" { ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 454, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:689 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" { ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 455, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:690 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" { ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:691 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" { ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:692 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" { ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:693 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" { ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:694 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" { ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 458, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:695 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" { ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:696 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" { ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:697 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" { ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:698 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" { ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:699 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" { ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 461, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:700 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" { ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:701 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" { ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:702 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" { ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 463, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:703 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" { ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 464, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:704 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" { ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 465, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:705 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" { ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 466, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:706 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" { ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 467, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:707 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" { ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 468, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:708 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 469, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:709 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 470, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:710 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" { ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 471, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:711 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 472, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:712 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" { ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 473, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:713 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:714 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:715 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:716 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:717 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:718 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:719 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:720 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" { ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:721 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" { ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 475, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:722 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:723 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:724 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" { ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:725 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" { ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:726 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:727 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:728 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" { ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 478, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:729 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" { ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 479, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:730 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:731 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:732 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" { ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:733 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" { ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:734 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:735 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" { ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:736 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" { ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:737 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" { ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:738 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" { ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_z, 0, ND_OPA_R, 0, 0), }, }, // Pos:739 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" { ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:740 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" { ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:741 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" { ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:742 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" { ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:743 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" { ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:744 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" { ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:745 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" { ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 488, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:746 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" { ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:747 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" { ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:748 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" { ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 490, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:749 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" { ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 491, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:750 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" { ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 492, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:751 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" { ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 493, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:752 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" { ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:753 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" { ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 495, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:754 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" { ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 496, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:755 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" { ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:756 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" { ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" { ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:765 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:766 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:767 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:768 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:769 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:770 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:771 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:772 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:773 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:774 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:775 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:776 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:777 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:778 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:779 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:780 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:781 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:782 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:783 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:784 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:785 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:786 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:787 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:788 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:789 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:790 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:791 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:792 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:793 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:794 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:795 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:796 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:797 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:798 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:799 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:800 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:801 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:802 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:803 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:804 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:805 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:806 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:807 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:808 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:809 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:810 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:811 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:812 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:813 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:814 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:815 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:816 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:817 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:818 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:819 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:820 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" { ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), }, }, // Pos:821 Instruction:"NOP" Encoding:"0x90"/"" { ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 498, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:822 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" { ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), }, }, // Pos:823 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" { ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:824 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:825 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:826 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:827 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:828 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:829 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:830 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:831 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:832 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:833 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" { ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:834 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" { ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 501, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:835 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" { ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 502, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:836 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:837 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:838 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:839 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" { ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:840 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:841 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:842 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:843 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:844 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:845 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" { ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, ND_PREF_REP, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:846 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" { ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 507, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:847 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" { ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 507, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:848 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" { ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 508, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:849 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" { ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 508, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:850 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" { ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 509, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:851 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" { ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 509, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:852 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" { ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:853 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" { ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 510, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:854 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" { ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:855 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" { ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 511, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:856 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" { ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 512, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:857 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" { ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:858 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" { ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 513, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:859 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" { ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 514, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:860 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" { ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 514, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:861 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" { ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 515, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:862 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" { ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 515, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:863 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" { ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:864 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" { ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 516, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:865 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" { ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:866 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" { ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 517, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:867 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" { ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 518, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:868 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" { ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 518, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:869 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" { ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:870 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" { ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 519, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:871 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" { ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 520, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:872 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" { ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 520, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:873 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" { ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 521, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:874 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" { ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 521, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:875 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" { ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 522, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:876 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" { ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 522, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:877 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" { ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 523, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:878 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" { ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 523, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:879 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" { ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 524, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:880 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" { ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 524, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:881 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" { ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:882 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" { ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:883 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" { ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 526, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:884 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" { ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 527, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:885 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" { ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 528, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:886 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" { ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 528, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:887 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" { ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 529, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:888 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" { ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 530, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:889 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" { ND_INS_PBNDKB, ND_CAT_SYSTEM, ND_SET_TSE, 531, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_TSE, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:890 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" { ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 532, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:891 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" { ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 533, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:892 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" { ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 533, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:893 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" { ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 534, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:894 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" { ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 534, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:895 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" { ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 535, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:896 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" { ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 536, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:897 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" { ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 536, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:898 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" { ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 537, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:899 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" { ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 538, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:900 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" { ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 539, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:901 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" { ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 539, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:902 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" { ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 540, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:903 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" { ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 540, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:904 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" { ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 541, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:905 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" { ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 542, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:906 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" { ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 542, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:907 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" { ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 543, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:908 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" { ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 544, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:909 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" { ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 545, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:910 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" { ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:911 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" { ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:912 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" { ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:913 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" { ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:914 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:915 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:916 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" { ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:917 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" { ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:918 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" { ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:919 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:920 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:921 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" { ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:922 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" { ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 552, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:923 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" { ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 553, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:924 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" { ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 554, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:925 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" { ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 555, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:926 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" { ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 556, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:927 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" { ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 557, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:928 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" { ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 558, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:929 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" { ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 559, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:930 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" { ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 560, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:931 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" { ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 561, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:932 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" { ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 562, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:933 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" { ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 563, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:934 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" { ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 564, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:935 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" { ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 565, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:936 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" { ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 566, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:937 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" { ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:938 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" { ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 568, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:939 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" { ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 569, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:940 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" { ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:941 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" { ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 571, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:942 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" { ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 572, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:943 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" { ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:944 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" { ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 573, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:945 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" { ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:946 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" { ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 574, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:947 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" { ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:948 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" { ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 575, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:949 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" { ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 576, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:950 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" { ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:951 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" { ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 577, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:952 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" { ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:953 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" { ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 578, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:954 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" { ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 579, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:955 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" { ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 579, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:956 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" { ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 580, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:957 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" { ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 581, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:958 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" { ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:959 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" { ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:960 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 583, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:961 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" { ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 584, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:962 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" { ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:963 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" { ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:964 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" { ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:965 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" { ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:966 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" { ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:967 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" { ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 586, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:968 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" { ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 587, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:969 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" { ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 587, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:970 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" { ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 588, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:971 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" { ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 589, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:972 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" { ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 590, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:973 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" { ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 590, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:974 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" { ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 591, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:975 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" { ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 591, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:976 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" { ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 592, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:977 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" { ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 593, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:978 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" { ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 594, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:979 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" { ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 595, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:980 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" { ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 596, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:981 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" { ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 596, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:982 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" { ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 597, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:983 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" { ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 597, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:984 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" { ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 598, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:985 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" { ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 599, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:986 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" { ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 600, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:987 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" { ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 600, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:988 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" { ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 601, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:989 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" { ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 602, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:990 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" { ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 603, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:991 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" { ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 604, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:992 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" { ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 605, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:993 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" { ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 606, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:994 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" { ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 607, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:995 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" { ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 608, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:996 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" { ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 609, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:997 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" { ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 610, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:998 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" { ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 611, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:999 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" { ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 612, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1000 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" { ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 613, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1001 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" { ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 614, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1002 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" { ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 614, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1003 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" { ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 615, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1004 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" { ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1005 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" { ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 616, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1006 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" { ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 617, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1007 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" { ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 617, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1008 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" { ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 618, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1009 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" { ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 619, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1010 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" { ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 619, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1011 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" { ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1012 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" { ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 620, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1013 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_FS, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1014 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_GS, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1015 Instruction:"POP ES" Encoding:"0x07"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_ES, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1016 Instruction:"POP SS" Encoding:"0x17"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_SS, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1017 Instruction:"POP DS" Encoding:"0x1F"/"" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_DS, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1018 Instruction:"POP Zv" Encoding:"0x58"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1019 Instruction:"POP Zv" Encoding:"0x59"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1020 Instruction:"POP Zv" Encoding:"0x5A"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1021 Instruction:"POP Zv" Encoding:"0x5B"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1022 Instruction:"POP Zv" Encoding:"0x5C"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1023 Instruction:"POP Zv" Encoding:"0x5D"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1024 Instruction:"POP Zv" Encoding:"0x5E"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1025 Instruction:"POP Zv" Encoding:"0x5F"/"O" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1026 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" { ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1027 Instruction:"POPA" Encoding:"ds16 0x61"/"" { ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 622, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1028 Instruction:"POPAD" Encoding:"ds32 0x61"/"" { ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 623, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1029 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" { ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 624, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1030 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 625, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1031 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 626, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1032 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" { ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 627, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1033 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" { ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1034 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" { ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 628, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1035 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1036 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1037 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1038 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" { ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1039 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" { ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 630, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1040 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" { ND_INS_PREFETCHIT0, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 631, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), }, }, // Pos:1041 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" { ND_INS_PREFETCHIT1, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 632, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), }, }, // Pos:1042 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" { ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 633, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1043 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" { ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1044 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" { ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1045 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" { ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1046 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" { ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1047 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" { ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1048 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" { ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1049 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" { ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1050 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" { ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1051 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" { ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 638, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1052 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" { ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 639, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), }, }, // Pos:1053 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" { ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1054 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" { ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 640, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1055 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" { ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 641, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1056 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" { ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 641, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1057 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 642, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1058 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 643, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1059 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 644, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1060 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" { ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 645, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1061 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" { ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 646, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1062 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" { ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 646, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1063 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" { ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1064 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" { ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 647, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1065 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" { ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1066 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" { ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 648, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1067 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" { ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1068 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" { ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1069 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" { ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1070 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" { ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1071 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" { ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1072 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" { ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1073 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" { ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1074 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" { ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1075 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" { ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1076 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" { ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1077 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" { ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1078 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" { ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1079 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" { ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1080 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" { ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 653, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1081 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" { ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1082 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" { ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1083 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" { ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1084 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" { ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1085 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" { ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1086 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" { ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1087 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" { ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1088 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" { ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1089 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" { ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1090 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" { ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1091 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" { ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1092 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" { ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1093 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" { ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 657, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1094 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" { ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1095 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" { ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1096 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" { ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1097 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" { ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1098 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" { ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1099 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" { ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1100 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" { ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1101 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" { ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1102 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" { ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 660, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1103 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" { ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 660, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1104 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" { ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 661, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1105 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" { ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 661, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1106 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" { ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1107 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" { ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 662, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1108 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" { ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1109 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" { ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 663, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1110 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" { ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 664, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1111 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" { ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 664, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1112 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" { ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 665, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1113 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" { ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 665, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1114 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" { ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1115 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" { ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 666, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1116 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" { ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 667, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1117 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" { ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 667, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1118 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" { ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 668, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1119 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" { ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 669, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1120 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" { ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 670, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1121 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" { ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 671, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1122 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" { ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 671, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1123 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" { ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 672, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1124 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" { ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 672, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1125 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" { ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 673, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1126 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" { ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1127 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" { ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 674, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1128 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" { ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1129 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" { ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 675, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1130 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" { ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 676, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1131 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" { ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 676, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1132 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" { ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 677, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1133 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" { ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1134 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" { ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 678, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1135 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_FS, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1136 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_GS, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1137 Instruction:"PUSH ES" Encoding:"0x06"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_ES, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1138 Instruction:"PUSH CS" Encoding:"0x0E"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1139 Instruction:"PUSH SS" Encoding:"0x16"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_SS, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1140 Instruction:"PUSH DS" Encoding:"0x1E"/"" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_DS, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1141 Instruction:"PUSH Zv" Encoding:"0x50"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1142 Instruction:"PUSH Zv" Encoding:"0x51"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1143 Instruction:"PUSH Zv" Encoding:"0x52"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1144 Instruction:"PUSH Zv" Encoding:"0x53"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1145 Instruction:"PUSH Zv" Encoding:"0x54"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1146 Instruction:"PUSH Zv" Encoding:"0x55"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1147 Instruction:"PUSH Zv" Encoding:"0x56"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1148 Instruction:"PUSH Zv" Encoding:"0x57"/"O" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1149 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_DWS, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1150 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_DWS, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1151 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" { ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1152 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" { ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1153 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" { ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1154 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 682, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1155 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 683, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1156 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" { ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 684, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, 0, 0, 0, 0, { OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1157 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" { ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 685, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1158 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" { ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, 0, 0, 0, 0, { OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1159 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" { ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 686, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1160 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1161 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1162 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1163 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1164 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1165 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" { ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1166 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" { ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 688, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1167 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" { ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 689, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1168 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1169 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1170 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1171 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1172 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1173 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" { ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1174 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" { ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 691, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1175 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" { ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 692, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1176 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" { ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 693, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1177 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" { ND_INS_RDMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 694, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, 0, 0, 0, 0, { OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1178 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" { ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 695, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_yf, 0, ND_OPA_W, 0, 0), OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1179 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" { ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 696, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 0, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1180 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" { ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 697, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1181 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" { ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 698, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1182 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" { ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1183 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" { ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1184 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" { ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1185 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" { ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1186 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" { ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 701, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1187 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" { ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 702, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1188 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" { ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1189 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" { ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 704, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1190 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" { ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 705, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1191 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" { ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1192 Instruction:"RETF" Encoding:"0xCB"/"" { ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1193 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" { ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1194 Instruction:"RETN" Encoding:"0xC3"/"" { ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, ND_PREF_BND, ND_MOD_ANY, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, 0, 0, 0, 0, { OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1195 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" { ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 708, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1196 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" { ND_INS_RMPQUERY, ND_CAT_SYSTEM, ND_SET_SNP, 709, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RMPQUERY, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1197 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" { ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 710, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MEM_rCX, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1198 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1199 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1200 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1201 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1202 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1203 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" { ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1204 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1205 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1206 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1207 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1208 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1209 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" { ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1210 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" { ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 713, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1211 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" { ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1212 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" { ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 715, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1213 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" { ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 716, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1214 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" { ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1215 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" { ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 718, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), }, }, // Pos:1216 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" { ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 719, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), }, }, // Pos:1217 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" { ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 720, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1218 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" { ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 721, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1219 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" { ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 722, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1220 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" { ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 723, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1221 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" { ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 724, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), }, }, // Pos:1222 Instruction:"SAHF" Encoding:"0x9E"/"" { ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 725, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0, 0, { OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1223 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1224 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1225 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1226 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1227 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1228 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" { ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1229 Instruction:"SALC" Encoding:"0xD6"/"" { ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1230 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1231 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1232 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1233 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1234 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1235 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" { ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1236 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 729, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1237 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" { ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_MEM_SHS, ND_OPS_12, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1238 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1239 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1240 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1241 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1242 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1243 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1244 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1245 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1246 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1247 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" { ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1248 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1249 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1250 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1251 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1252 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1253 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1254 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1255 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" { ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, ND_PREF_REPC, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1256 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" { ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 736, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1257 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" { ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 737, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rR8, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rR9, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1258 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" { ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 738, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { 0 }, }, // Pos:1259 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" { ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 739, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1260 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" { ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 740, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, 0, 0, 0, 0, { 0 }, }, // Pos:1261 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1262 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1263 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1264 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1265 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1266 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_CF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1267 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1268 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1269 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1270 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1271 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1272 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1273 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_OF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1274 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 754, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_PF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1275 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 755, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_SF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1276 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" { ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 756, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_MEM_SHS0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1277 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" { ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 757, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, 0|NDR_RFLAG_ZF, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1278 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" { ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 758, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, 0, 0, 0, 0, { 0 }, }, // Pos:1279 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" { ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 759, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1280 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" { ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 760, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1281 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" { ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 761, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1282 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" { ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 762, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1283 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" { ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 763, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1284 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" { ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 764, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1285 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" { ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 765, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1286 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" { ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 766, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1287 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1288 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1289 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1290 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1291 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1292 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" { ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1293 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" { ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1294 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" { ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1295 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 769, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1296 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1297 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1298 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1299 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1300 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1301 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" { ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1302 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" { ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1303 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" { ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1304 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" { ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 772, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1305 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" { ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 773, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1306 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" { ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 774, 0, ND_MOD_ANY, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1307 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" { ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 775, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1308 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" { ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 776, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1309 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" { ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1310 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" { ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1311 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" { ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 778, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1312 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" { ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:1313 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" { ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1314 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" { ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1315 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" { ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 781, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1316 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" { ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 782, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1317 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" { ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 783, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1318 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" { ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 784, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1319 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" { ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 785, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1320 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" { ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 786, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, 0, 0, 0|NDR_RFLAG_AC, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1321 Instruction:"STC" Encoding:"0xF9"/"" { ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 787, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1322 Instruction:"STD" Encoding:"0xFD"/"" { ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 788, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1323 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" { ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 789, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:1324 Instruction:"STI" Encoding:"0xFB"/"" { ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 790, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_IF, 0, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1325 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" { ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 791, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1326 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1327 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1328 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1329 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1330 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1331 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1332 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1333 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" { ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_DF, 0, 0, 0, { OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1334 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" { ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1335 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" { ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1336 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" { ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 797, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0), }, }, // Pos:1337 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" { ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 798, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 0, 0, 0, 0, { OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1338 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1339 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1340 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1341 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1342 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1343 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1344 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1345 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1346 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1347 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" { ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1348 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" { ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 800, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1349 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" { ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 801, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1350 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" { ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 802, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1351 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" { ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 803, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1352 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" { ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:1353 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" { ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 805, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), }, }, // Pos:1354 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" { ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 806, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), }, }, // Pos:1355 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" { ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 807, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, 0, 0, 0, 0, { OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1356 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" { ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 808, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT, ND_CFF_FSC, 0, 0, 0, 0, { OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_LSTAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_FMASK, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1357 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" { ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 809, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, ND_CFF_SEP, 0, 0, 0, 0|NDR_RFLAG_IF, { OP(ND_OPT_MSR_SCS, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_SESP, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_SEIP, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:1358 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" { ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 810, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, 0, 0, 0, 0, { OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1359 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" { ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 811, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, 0, 0, 0, 0, { OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1360 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" { ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 812, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1361 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" { ND_INS_TCMMIMFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 813, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1362 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" { ND_INS_TCMMRLFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 814, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1363 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" { ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 815, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:1364 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" { ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 816, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1365 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" { ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 817, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1366 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" { ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 818, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1367 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" { ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 819, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1368 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" { ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 820, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1369 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" { ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 821, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXFP16, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1370 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1371 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1372 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1373 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1374 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1375 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1376 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1377 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" { ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1378 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" { ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 823, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1379 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" { ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 824, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1380 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" { ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 825, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1381 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" { ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 826, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { 0 }, }, // Pos:1382 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" { ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 827, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0), OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0), }, }, // Pos:1383 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" { ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 828, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, 0, 0, 0, 0, { OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), }, }, // Pos:1384 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" { ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 829, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, 0, 0, 0, 0, { 0 }, }, // Pos:1385 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" { ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 830, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1386 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" { ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 831, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1387 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" { ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 832, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, 0, 0, 0, 0, { OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1388 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" { ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 833, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1389 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" { ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 834, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1390 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" { ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 835, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1391 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" { ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 836, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1392 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" { ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 837, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:1393 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" { ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 838, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, 0, 0, 0, 0, { OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1394 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" { ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 839, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1395 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" { ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 840, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1396 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" { ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 841, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1397 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" { ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 842, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1398 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" { ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 843, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1399 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" { ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 844, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1400 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" { ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 845, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1401 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" { ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 846, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1402 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" { ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 847, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1403 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" { ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 848, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1404 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" { ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1405 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" { ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 849, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1406 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" { ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 850, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1407 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" { ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1408 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" { ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 851, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1409 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" { ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 852, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1410 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" { ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 852, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1411 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" { ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 853, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1412 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" { ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1413 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" { ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 854, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1414 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" { ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 855, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1415 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" { ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 856, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1416 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1417 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" { ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 857, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1418 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1419 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" { ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 858, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1420 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1421 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" { ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 859, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1422 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1423 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" { ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 860, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1424 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" { ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 861, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1425 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" { ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 862, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1426 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" { ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 863, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1427 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" { ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 864, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1428 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" { ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 865, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:1429 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" { ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 865, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1430 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" { ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1431 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" { ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 866, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1432 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" { ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:1433 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" { ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 867, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1434 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" { ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 868, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1435 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" { ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 868, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1436 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" { ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 869, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:1437 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" { ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 870, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:1438 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" { ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 871, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:1439 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" { ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 872, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1440 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" { ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 873, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1441 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" { ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 874, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1442 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" { ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 875, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1443 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" { ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 876, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1444 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" { ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 877, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1445 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" { ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 878, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1446 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" { ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 879, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1447 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" { ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1448 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" { ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 881, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1449 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" { ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 882, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1450 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" { ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 883, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1451 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" { ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 884, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1452 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" { ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1453 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" { ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 886, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1454 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" { ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 887, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1455 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" { ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 888, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1456 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" { ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1457 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" { ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 889, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1458 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" { ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1459 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" { ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 890, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1460 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1461 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" { ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 891, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1462 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 892, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1463 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1464 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" { ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 893, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1465 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1466 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" { ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 894, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1467 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 895, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1468 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" { ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1469 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" { ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 896, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1470 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" { ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 897, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1471 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" { ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 897, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1472 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" { ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 898, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1473 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" { ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1474 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" { ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 899, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1475 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" { ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 900, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1476 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" { ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 901, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1477 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" { ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1478 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" { ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1479 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" { ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1480 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 903, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1481 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 904, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1482 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" { ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 904, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1483 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" { ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 905, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1484 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" { ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1485 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" { ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 907, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1486 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" { ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 908, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1487 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" { ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 909, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1488 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" { ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1489 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" { ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 910, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1490 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" { ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1491 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" { ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 911, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1492 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" { ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 912, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1493 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" { ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1494 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" { ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1495 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" { ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1496 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" { ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 914, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1497 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" { ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 915, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1498 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" { ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 916, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1499 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1500 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" { ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1501 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" { ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1502 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" { ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1503 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" { ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1504 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" { ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1505 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" { ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1506 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" { ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1507 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" { ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 923, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1508 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" { ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 924, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1509 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" { ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1510 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 926, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1511 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" { ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 926, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1512 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" { ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1513 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" { ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1514 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" { ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1515 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" { ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1516 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" { ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1517 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" { ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1518 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" { ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 929, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1519 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" { ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 930, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1520 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" { ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 931, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1521 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" { ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 932, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1522 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" { ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 933, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1523 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" { ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 934, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1524 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" { ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 935, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1525 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" { ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 936, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1526 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" { ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 937, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1527 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" { ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 937, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1528 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" { ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 938, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1529 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" { ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 938, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1530 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" { ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 939, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1531 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" { ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 940, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1532 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" { ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1533 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" { ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 942, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1534 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" { ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 943, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1535 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" { ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1536 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" { ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1537 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" { ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 944, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1538 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" { ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 945, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1539 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1540 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" { ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 946, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1541 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" { ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1542 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" { ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 947, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1543 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" { ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 948, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1544 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" { ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1545 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" { ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 949, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1546 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" { ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 950, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1547 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" { ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1548 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" { ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 951, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1549 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" { ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 952, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1550 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" { ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 953, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1551 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" { ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 954, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1552 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1553 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" { ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1554 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" { ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 957, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1555 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" { ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 958, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1556 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" { ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 959, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1557 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" { ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 960, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1558 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" { ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1559 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" { ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 961, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1560 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" { ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 962, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1561 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" { ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 963, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1562 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" { ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 964, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1563 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" { ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1564 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" { ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 965, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1565 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" { ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1566 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" { ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 967, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1567 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" { ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 968, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1568 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" { ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1569 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" { ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 969, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1570 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" { ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 970, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1571 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" { ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 971, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1572 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" { ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 972, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1573 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" { ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 973, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1574 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" { ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 974, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1575 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" { ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 975, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1576 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" { ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 976, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1577 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" { ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1578 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" { ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1579 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" { ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 978, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1580 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" { ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 979, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1581 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" { ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1582 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" { ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 981, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1583 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" { ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 982, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1584 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" { ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1585 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" { ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 983, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1586 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" { ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 984, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1587 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" { ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1588 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" { ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 985, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1589 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" { ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1590 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" { ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 986, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1591 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" { ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 987, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1592 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" { ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1593 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" { ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 988, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1594 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" { ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 989, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:1595 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" { ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 990, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1596 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" { ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 991, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1597 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" { ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 992, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1598 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" { ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 993, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1599 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" { ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 994, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1600 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" { ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 995, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1601 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" { ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 996, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1602 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" { ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 997, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1603 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" { ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 998, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1604 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" { ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 999, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1605 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" { ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1000, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1606 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" { ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1607 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" { ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1002, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1608 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" { ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 1003, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1609 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" { ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1004, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1610 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" { ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1005, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1611 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" { ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1006, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1612 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" { ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1007, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1613 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1614 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1615 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" { ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1616 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" { ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1617 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" { ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1009, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1618 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" { ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1010, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1619 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" { ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1011, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1620 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" { ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1012, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1621 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" { ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1013, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1622 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" { ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1014, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1623 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" { ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1015, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1624 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" { ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1016, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1625 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" { ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1626 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" { ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1017, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1627 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" { ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1018, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1628 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" { ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1629 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" { ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1019, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1630 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" { ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1631 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" { ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1020, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1632 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" { ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1021, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1633 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" { ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1634 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" { ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1022, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1635 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" { ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1636 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" { ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1023, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1637 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" { ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1024, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1638 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" { ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1639 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" { ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1025, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1640 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" { ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1641 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" { ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1026, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1642 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" { ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1027, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1643 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" { ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1644 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" { ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1028, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1645 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" { ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1646 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" { ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1029, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1647 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" { ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1030, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1648 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" { ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1649 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" { ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1031, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1650 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" { ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1032, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1651 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" { ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1032, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1652 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" { ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1033, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1653 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" { ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1654 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" { ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1034, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1655 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" { ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1035, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1656 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" { ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1036, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1657 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" { ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1658 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" { ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1659 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" { ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1660 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" { ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1661 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" { ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1662 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" { ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1663 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" { ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1664 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" { ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1665 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" { ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1666 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" { ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1041, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1667 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" { ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1042, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1668 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" { ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1669 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" { ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1043, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1670 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" { ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1671 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" { ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1044, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1672 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" { ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1045, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1673 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" { ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1674 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" { ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1046, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1675 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" { ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1676 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" { ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1047, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1677 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" { ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1048, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1678 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" { ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1679 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" { ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1049, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1680 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" { ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1681 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" { ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1682 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" { ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1683 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" { ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1684 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" { ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1685 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" { ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1052, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1686 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" { ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1053, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1687 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" { ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1688 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" { ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1054, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1689 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" { ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1690 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" { ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1055, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1691 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" { ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1056, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1692 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" { ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1693 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" { ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1057, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1694 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" { ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1695 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" { ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1058, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1696 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" { ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1059, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1697 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" { ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1698 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" { ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1060, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1699 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" { ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1700 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" { ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1061, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1701 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" { ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1062, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1702 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" { ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1703 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" { ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1063, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1704 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" { ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1705 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" { ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1064, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1706 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" { ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1065, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1707 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" { ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1708 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" { ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1066, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1709 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" { ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1710 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" { ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1067, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1711 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" { ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1068, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1712 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" { ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1713 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" { ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1069, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1714 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" { ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1715 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" { ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1070, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1716 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" { ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1071, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1717 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" { ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1718 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" { ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1072, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1719 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" { ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1720 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" { ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1073, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1721 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" { ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1074, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1722 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" { ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1723 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" { ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1075, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1724 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" { ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1725 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" { ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1076, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1726 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" { ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1077, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1727 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" { ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1728 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" { ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1078, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1729 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" { ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1730 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" { ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1731 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" { ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1732 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" { ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1733 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" { ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1734 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" { ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1735 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" { ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1736 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" { ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1737 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" { ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1738 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" { ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1739 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" { ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1740 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" { ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1741 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" { ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1742 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" { ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1086, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1743 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" { ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1744 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" { ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1087, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1745 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" { ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1088, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1746 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" { ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1747 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" { ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1089, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1748 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" { ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1749 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" { ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1090, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1750 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" { ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1091, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1751 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" { ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1752 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" { ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1092, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1753 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" { ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1754 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" { ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1093, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1755 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" { ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1094, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1756 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" { ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1757 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" { ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1095, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1758 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" { ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1759 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" { ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1096, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1760 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" { ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1097, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1761 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" { ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1762 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" { ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1098, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1763 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" { ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1764 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" { ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1099, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1765 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" { ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1100, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1766 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" { ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1767 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" { ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1101, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1768 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" { ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1769 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" { ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1102, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1770 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" { ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1103, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1771 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" { ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1772 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" { ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1104, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1773 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" { ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1774 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" { ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1775 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" { ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1776 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" { ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1777 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" { ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1778 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" { ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1779 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" { ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1780 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" { ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1781 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" { ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1782 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" { ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1109, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1783 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" { ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1110, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1784 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" { ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1785 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" { ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1111, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1786 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" { ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1787 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" { ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1112, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1788 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" { ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1113, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1789 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" { ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1790 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" { ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1114, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1791 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" { ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1792 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" { ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1115, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1793 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" { ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1116, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1794 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" { ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1795 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" { ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1117, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1796 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" { ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1797 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" { ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1118, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1798 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" { ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1119, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1799 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" { ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1800 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" { ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1120, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1801 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" { ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:1802 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" { ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1121, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1803 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" { ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1122, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:1804 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" { ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:1805 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" { ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1123, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1806 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" { ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1807 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" { ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1124, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1808 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" { ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1125, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1809 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" { ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:1810 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" { ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1126, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1811 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" { ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1812 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" { ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1813 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" { ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1814 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" { ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1815 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" { ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1816 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" { ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1817 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" { ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1818 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" { ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1819 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" { ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1131, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1820 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" { ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1132, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1821 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" { ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1133, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1822 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" { ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1134, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1823 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" { ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1135, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1824 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" { ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1136, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1825 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" { ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1137, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1826 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" { ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1138, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1827 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" { ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1139, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1828 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" { ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1140, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1829 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" { ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1830 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" { ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1141, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1831 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" { ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1832 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" { ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1142, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1833 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" { ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1834 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" { ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1835 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" { ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1836 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" { ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1837 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" { ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1147, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1838 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" { ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1148, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1839 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" { ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1149, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1840 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" { ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1150, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1841 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" { ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1842 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" { ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1151, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1843 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" { ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1844 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" { ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1152, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), }, }, // Pos:1845 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" { ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1153, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1846 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" { ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1154, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1847 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" { ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1155, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1848 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" { ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1156, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1849 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" { ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1157, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1850 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" { ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1158, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1851 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" { ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1159, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1852 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" { ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1160, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1853 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" { ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1161, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1854 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" { ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1162, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1855 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" { ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1163, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1856 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" { ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1164, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1857 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" { ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1858 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" { ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1859 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" { ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1860 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" { ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1861 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" { ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1862 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" { ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1863 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" { ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1168, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1864 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" { ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1169, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1865 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" { ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1170, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1866 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" { ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1171, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1867 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" { ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1172, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1868 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" { ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1173, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1869 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" { ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1174, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1870 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" { ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1175, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1871 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" { ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1176, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1872 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" { ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1177, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1873 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" { ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1178, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1874 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" { ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1179, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1875 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" { ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1180, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1876 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" { ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1181, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1877 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1878 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1879 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" { ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1880 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" { ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:1881 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" { ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1183, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1882 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" { ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1184, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1883 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" { ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1185, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1884 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" { ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1885 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" { ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1886 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" { ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1887 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" { ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1888 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" { ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1889 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" { ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1188, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1890 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" { ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1189, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1891 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" { ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1892 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" { ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1190, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1893 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" { ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1191, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1894 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" { ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1191, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1895 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" { ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1192, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1896 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" { ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1897 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" { ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1193, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1898 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" { ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1194, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0, 0, 0, { 0 }, }, // Pos:1899 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" { ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1195, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1900 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" { ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1196, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0, 0, 0, { 0 }, }, // Pos:1901 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" { ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:1902 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" { ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:1903 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" { ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:1904 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" { ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1198, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1905 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" { ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:1906 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" { ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:1907 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" { ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1200, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:1908 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" { ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1201, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1909 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" { ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1201, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1910 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" { ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1202, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1911 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" { ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:1912 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" { ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1203, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:1913 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" { ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1204, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:1914 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" { ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1205, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:1915 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" { ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:1916 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" { ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:1917 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" { ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1918 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" { ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1919 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" { ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1920 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" { ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1921 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" { ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1922 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" { ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1923 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" { ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1924 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" { ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1925 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1926 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1927 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" { ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1928 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" { ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:1929 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" { ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1930 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" { ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1931 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" { ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1932 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" { ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1933 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" { ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1934 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" { ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1935 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" { ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1936 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" { ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1937 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" { ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1938 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" { ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1939 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" { ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1940 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" { ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1941 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" { ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1942 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" { ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1943 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" { ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1944 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" { ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1945 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" { ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1946 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" { ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1947 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" { ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1948 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" { ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1949 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" { ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1950 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" { ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1951 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" { ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1219, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1952 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" { ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1953 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" { ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1954 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" { ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1955 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" { ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1956 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" { ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1957 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" { ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1958 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" { ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1959 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" { ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1960 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" { ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1222, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1961 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" { ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1222, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1962 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" { ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1963 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" { ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1964 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" { ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1965 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" { ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1966 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" { ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1967 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" { ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1968 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" { ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1969 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" { ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1970 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" { ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1225, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1971 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" { ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1226, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1972 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" { ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1973 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" { ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1227, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1974 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" { ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1975 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" { ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1228, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1976 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" { ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1977 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" { ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1229, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1978 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" { ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:1979 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" { ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1230, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:1980 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1981 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1982 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1983 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1984 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:1985 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1986 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1987 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" { ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1988 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1989 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1990 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1991 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1992 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1993 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:1994 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1995 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" { ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:1996 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" { ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), }, }, // Pos:1997 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), }, }, // Pos:1998 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" { ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:1999 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2000 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" { ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2001 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" { ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1234, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2002 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" { ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2003 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" { ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1235, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2004 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2005 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2006 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2007 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2008 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2009 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2010 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2011 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" { ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2012 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" { ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2013 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" { ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2014 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" { ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2015 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" { ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2016 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" { ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2017 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" { ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2018 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" { ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2019 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" { ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2020 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" { ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2021 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" { ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2022 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" { ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2023 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" { ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2024 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" { ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1240, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2025 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" { ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1241, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2026 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" { ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1242, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2027 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" { ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1243, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2028 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" { ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1244, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2029 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" { ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1245, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2030 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" { ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1246, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, 0, 0, 0, 0, { 0 }, }, // Pos:2031 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" { ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:2032 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" { ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1247, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2033 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" { ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1248, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:2034 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" { ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:2035 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" { ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1249, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2036 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" { ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1250, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2037 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" { ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1250, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2038 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" { ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1251, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2039 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" { ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1252, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2040 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" { ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1252, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2041 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" { ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1253, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2042 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" { ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1254, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2043 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" { ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1255, 0, ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2044 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" { ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1256, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2045 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" { ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1256, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2046 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" { ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1257, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2047 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" { ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1257, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2048 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" { ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1258, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2049 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" { ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1259, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2050 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" { ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1260, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2051 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" { ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1261, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2052 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" { ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2053 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" { ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1262, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2054 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" { ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2055 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" { ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1263, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2056 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" { ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1264, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2057 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" { ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2058 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" { ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1265, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2059 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" { ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2060 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" { ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1266, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2061 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" { ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2062 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" { ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1267, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2063 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" { ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2064 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" { ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1268, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2065 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" { ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2066 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" { ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1269, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2067 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" { ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2068 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" { ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1270, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2069 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" { ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2070 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" { ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1271, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2071 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" { ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2072 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" { ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1272, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2073 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" { ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2074 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" { ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1273, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2075 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" { ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2076 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" { ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1274, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2077 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" { ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2078 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" { ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1275, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2079 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" { ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2080 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" { ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1276, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2081 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" { ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1277, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2082 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" { ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1277, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2083 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" { ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2084 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" { ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1278, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2085 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" { ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1279, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2086 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" { ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2087 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" { ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1281, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2088 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" { ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1282, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2089 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" { ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1283, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2090 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" { ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1284, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2091 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" { ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1285, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2092 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" { ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1285, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2093 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" { ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2094 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" { ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1286, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2095 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" { ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1287, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2096 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" { ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1288, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2097 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" { ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1289, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2098 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" { ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1290, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2099 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" { ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1291, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2100 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" { ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1292, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2101 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" { ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1293, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2102 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" { ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2103 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" { ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2104 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" { ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2105 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" { ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2106 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" { ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2107 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" { ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2108 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" { ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1296, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2109 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" { ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1297, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2110 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" { ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2111 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" { ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2112 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" { ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1298, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2113 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" { ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2114 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" { ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2115 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" { ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1299, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2116 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2117 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" { ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2118 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" { ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2119 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" { ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2120 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" { ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2121 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" { ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2122 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" { ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2123 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" { ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1304, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2124 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" { ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2125 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" { ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1305, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2126 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" { ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2127 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" { ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1306, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2128 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" { ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2129 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" { ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1307, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2130 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" { ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1308, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2131 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" { ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1309, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2132 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" { ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2133 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" { ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1310, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2134 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" { ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2135 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" { ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1311, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2136 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" { ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2137 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" { ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1312, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2138 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" { ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2139 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" { ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1313, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2140 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" { ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1314, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2141 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" { ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1315, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2142 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" { ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1316, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2143 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" { ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2144 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" { ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1318, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2145 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" { ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1319, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2146 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" { ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1320, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2147 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" { ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1321, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2148 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" { ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1322, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2149 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" { ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1323, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2150 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" { ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1324, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2151 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" { ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1325, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2152 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" { ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1326, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2153 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" { ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1327, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2154 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" { ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1328, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2155 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" { ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1329, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2156 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" { ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1330, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2157 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" { ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1331, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2158 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" { ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1332, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2159 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" { ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1333, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2160 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" { ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1334, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2161 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" { ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1335, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2162 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" { ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1336, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2163 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" { ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1337, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2164 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" { ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2165 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" { ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2166 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" { ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2167 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" { ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2168 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" { ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2169 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" { ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2170 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" { ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1342, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2171 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" { ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1343, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2172 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" { ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2173 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" { ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1344, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2174 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" { ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2175 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" { ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1345, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2176 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" { ND_INS_VPDPWSUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1346, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2177 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" { ND_INS_VPDPWSUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1347, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2178 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" { ND_INS_VPDPWUSD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1348, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2179 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" { ND_INS_VPDPWUSDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1349, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2180 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" { ND_INS_VPDPWUUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1350, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2181 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" { ND_INS_VPDPWUUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1351, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2182 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" { ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1352, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2183 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" { ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1353, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2184 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" { ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1354, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2185 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" { ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2186 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" { ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1355, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2187 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" { ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1356, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2188 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" { ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1357, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2189 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" { ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1358, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2190 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" { ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1359, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2191 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" { ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1360, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2192 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" { ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1361, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2193 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" { ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2194 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" { ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2195 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" { ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2196 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" { ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2197 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" { ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2198 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" { ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2199 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" { ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2200 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" { ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2201 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" { ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2202 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" { ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2203 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" { ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2204 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" { ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2205 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" { ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2206 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" { ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2207 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" { ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2208 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" { ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1366, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2209 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" { ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2210 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" { ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2211 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" { ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1367, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2212 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" { ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2213 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" { ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2214 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" { ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1368, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2215 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" { ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1369, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2216 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" { ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1370, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2217 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" { ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1371, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2218 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" { ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1372, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2219 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" { ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1373, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2220 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" { ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2221 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" { ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1375, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2222 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" { ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2223 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" { ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1377, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2224 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" { ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1378, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2225 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" { ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1379, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2226 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2227 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2228 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" { ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2229 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" { ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2230 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2231 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2232 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" { ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2233 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" { ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2234 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2235 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2236 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" { ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2237 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" { ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2238 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2239 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2240 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2241 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" { ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2242 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" { ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2243 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" { ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2244 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" { ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2245 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" { ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1384, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2246 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" { ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2247 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" { ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1385, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2248 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" { ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2249 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" { ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1386, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2250 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" { ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2251 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" { ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1387, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2252 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" { ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1388, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2253 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" { ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1389, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2254 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" { ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1390, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2255 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" { ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1391, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2256 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" { ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1392, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2257 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" { ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1393, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2258 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" { ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1394, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2259 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" { ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1395, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2260 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" { ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1396, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2261 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" { ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1397, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2262 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" { ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1398, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2263 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" { ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1399, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2264 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" { ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1400, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2265 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" { ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1401, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2266 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" { ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1402, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2267 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" { ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1403, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2268 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" { ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1404, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2269 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" { ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1405, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2270 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" { ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1406, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2271 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" { ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1407, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2272 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" { ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1408, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2273 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" { ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1409, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2274 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2275 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2276 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" { ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2277 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" { ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2278 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1411, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2279 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" { ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1411, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2280 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2281 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" { ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1412, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2282 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2283 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2284 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" { ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2285 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" { ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2286 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" { ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1414, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2287 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" { ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1415, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2288 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" { ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1416, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2289 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" { ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1417, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2290 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" { ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1418, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2291 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" { ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1419, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2292 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" { ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1420, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2293 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" { ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1421, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2294 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" { ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1422, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2295 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" { ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1423, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2296 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" { ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1424, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2297 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" { ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1425, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2298 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" { ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1426, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2299 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" { ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1427, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2300 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" { ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2301 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" { ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1428, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2302 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" { ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2303 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" { ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1429, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2304 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" { ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2305 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" { ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1430, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2306 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" { ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2307 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" { ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1431, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2308 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" { ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2309 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" { ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2310 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" { ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2311 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" { ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2312 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" { ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2313 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" { ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1434, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2314 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" { ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2315 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" { ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1435, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2316 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" { ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2317 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" { ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2318 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" { ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1437, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2319 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" { ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2320 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" { ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1438, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2321 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" { ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2322 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" { ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1439, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2323 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" { ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1440, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2324 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" { ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1441, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2325 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" { ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1441, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2326 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" { ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1442, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2327 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" { ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1442, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2328 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" { ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1443, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2329 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" { ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1443, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2330 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" { ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1444, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2331 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" { ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1445, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2332 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" { ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1445, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2333 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" { ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2334 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" { ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1446, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2335 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" { ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1447, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2336 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" { ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1447, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2337 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" { ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1448, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2338 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" { ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2339 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" { ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1449, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2340 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" { ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1450, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2341 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" { ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1451, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2342 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" { ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2343 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" { ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2344 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" { ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1454, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2345 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" { ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1455, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2346 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" { ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1456, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2347 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" { ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1457, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2348 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" { ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1458, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2349 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" { ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1459, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2350 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" { ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2351 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" { ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1461, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2352 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" { ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2353 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" { ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2354 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" { ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2355 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" { ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2356 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" { ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2357 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" { ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2358 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" { ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1468, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2359 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" { ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2360 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" { ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2361 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" { ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1469, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2362 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" { ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), }, }, // Pos:2363 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" { ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2364 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" { ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1470, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2365 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" { ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2366 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" { ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2367 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" { ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1471, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2368 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" { ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2369 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" { ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2370 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" { ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1472, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2371 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" { ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2372 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" { ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2373 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" { ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1473, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2374 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" { ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2375 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" { ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2376 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" { ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1474, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2377 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" { ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1475, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2378 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" { ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2379 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" { ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2380 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" { ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2381 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" { ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1479, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2382 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" { ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1480, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2383 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" { ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1481, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2384 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" { ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1482, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2385 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" { ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2386 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" { ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2387 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" { ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1483, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2388 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" { ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), }, }, // Pos:2389 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" { ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), }, }, // Pos:2390 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" { ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1484, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2391 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" { ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2392 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" { ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2393 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" { ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1485, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2394 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" { ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2395 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" { ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2396 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" { ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1486, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2397 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" { ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2398 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" { ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2399 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" { ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1487, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2400 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" { ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2401 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" { ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), }, }, // Pos:2402 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" { ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1488, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2403 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" { ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1489, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2404 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" { ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1489, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2405 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" { ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1490, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2406 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" { ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1490, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2407 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" { ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1491, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2408 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" { ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1491, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2409 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" { ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1492, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2410 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" { ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1492, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2411 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" { ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1493, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2412 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" { ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1493, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2413 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" { ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1494, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2414 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" { ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2415 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" { ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1495, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2416 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" { ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1496, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2417 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" { ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1497, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2418 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" { ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1497, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2419 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" { ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1498, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2420 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" { ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1499, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2421 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" { ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1500, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2422 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" { ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1501, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2423 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" { ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1502, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2424 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" { ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1503, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2425 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" { ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1504, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2426 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" { ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2427 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" { ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2428 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" { ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1506, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2429 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" { ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1507, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2430 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" { ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1508, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2431 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" { ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1509, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2432 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" { ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1510, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2433 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" { ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1511, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2434 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" { ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1512, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2435 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" { ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1513, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2436 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" { ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2437 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" { ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2438 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" { ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2439 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" { ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2440 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" { ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2441 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" { ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2442 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" { ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2443 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" { ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2444 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" { ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2445 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" { ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2446 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" { ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2447 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" { ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2448 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2449 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" { ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1518, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2450 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" { ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1519, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2451 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" { ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1520, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2452 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" { ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1521, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2453 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" { ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1522, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2454 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" { ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2455 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" { ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2456 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" { ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2457 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" { ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2458 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" { ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2459 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" { ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2460 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" { ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2461 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" { ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2462 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" { ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2463 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" { ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2464 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" { ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2465 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" { ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2466 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" { ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1528, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2467 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" { ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2468 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" { ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2469 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" { ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2470 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" { ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2471 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" { ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1533, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2472 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" { ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1534, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2473 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" { ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2474 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" { ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2475 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" { ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1536, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2476 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" { ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1537, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2477 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" { ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1538, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2478 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" { ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1539, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2479 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" { ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1540, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2480 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" { ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1541, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2481 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" { ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1542, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2482 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" { ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2483 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" { ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1543, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2484 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" { ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1544, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2485 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" { ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2486 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" { ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1545, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2487 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" { ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2488 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" { ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1546, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2489 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" { ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2490 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" { ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1547, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2491 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" { ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1548, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2492 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" { ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1549, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2493 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" { ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1550, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2494 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" { ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2495 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" { ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2496 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" { ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2497 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" { ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2498 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" { ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1552, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2499 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" { ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1552, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2500 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" { ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2501 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" { ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2502 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" { ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2503 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" { ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2504 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" { ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2505 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" { ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1554, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2506 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" { ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2507 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" { ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1555, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2508 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" { ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2509 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" { ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2510 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" { ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2511 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" { ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2512 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" { ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2513 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" { ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2514 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" { ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2515 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" { ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2516 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" { ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2517 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" { ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2518 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" { ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2519 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" { ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2520 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" { ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1560, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2521 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" { ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1561, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2522 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" { ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1562, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2523 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" { ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2524 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" { ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2525 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" { ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2526 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" { ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2527 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" { ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2528 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" { ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2529 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" { ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2530 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" { ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2531 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" { ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2532 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" { ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1565, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2533 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" { ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2534 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" { ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2535 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" { ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2536 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" { ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2537 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" { ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2538 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" { ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1567, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2539 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" { ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2540 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" { ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1568, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2541 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" { ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1569, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2542 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" { ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2543 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" { ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2544 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" { ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2545 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" { ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2546 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" { ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1571, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2547 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" { ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1571, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2548 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" { ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1572, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2549 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" { ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1572, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2550 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" { ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1573, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2551 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" { ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1573, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2552 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" { ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1574, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2553 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" { ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1574, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2554 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" { ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1575, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2555 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" { ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1575, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2556 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" { ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1576, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2557 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" { ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1576, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2558 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" { ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1577, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2559 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" { ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1577, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2560 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" { ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1578, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2561 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" { ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1578, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2562 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" { ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1579, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2563 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" { ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1580, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2564 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" { ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1581, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2565 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" { ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1582, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2566 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" { ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1583, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2567 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" { ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1584, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2568 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" { ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1585, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2569 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" { ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1586, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2570 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" { ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1587, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2571 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" { ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1588, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2572 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" { ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1589, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2573 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" { ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1590, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2574 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" { ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1590, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2575 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" { ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1591, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2576 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" { ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1591, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2577 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" { ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1592, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2578 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" { ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1592, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2579 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" { ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1593, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2580 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" { ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1593, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2581 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" { ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1594, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2582 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" { ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1594, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2583 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" { ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1595, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2584 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" { ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1595, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2585 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" { ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1596, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2586 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" { ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1596, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2587 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" { ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1597, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), }, }, // Pos:2588 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" { ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1597, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2589 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" { ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1598, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2590 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" { ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1599, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2591 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" { ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1600, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2592 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" { ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1601, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2593 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" { ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1602, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2594 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" { ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1603, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2595 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" { ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1604, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2596 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" { ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1605, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2597 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" { ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1606, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2598 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" { ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1607, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2599 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" { ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1608, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2600 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" { ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1609, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:2601 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" { ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1610, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:2602 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" { ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1611, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:2603 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" { ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1612, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:2604 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" { ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1613, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), }, }, // Pos:2605 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" { ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1614, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2606 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" { ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1615, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), }, }, // Pos:2607 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" { ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1616, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2608 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" { ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1617, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2609 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" { ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1618, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2610 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" { ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1619, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2611 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" { ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1620, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2612 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" { ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1621, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2613 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" { ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1622, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2614 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" { ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2615 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" { ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1624, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2616 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" { ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1625, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2617 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" { ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2618 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" { ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1627, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2619 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" { ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1628, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2620 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" { ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1629, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2621 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" { ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1630, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2622 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" { ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1631, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2623 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" { ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1632, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2624 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" { ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1633, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2625 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" { ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1634, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2626 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" { ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1635, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2627 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" { ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1636, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2628 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" { ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1637, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), }, }, // Pos:2629 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" { ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1638, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), }, }, // Pos:2630 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" { ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1639, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:2631 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" { ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1640, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:2632 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" { ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1641, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), }, }, // Pos:2633 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" { ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1642, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2634 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" { ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1643, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), }, }, // Pos:2635 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" { ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1644, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2636 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" { ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1645, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:2637 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" { ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1646, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:2638 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" { ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1647, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:2639 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" { ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1648, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2640 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" { ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1649, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2641 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" { ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1650, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2642 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" { ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1651, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2643 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" { ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2644 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" { ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1653, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2645 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" { ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1654, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2646 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" { ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1655, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2647 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" { ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1656, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2648 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" { ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1657, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2649 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" { ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1658, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2650 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" { ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1659, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2651 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" { ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1660, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), }, }, // Pos:2652 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" { ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1661, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2653 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" { ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1662, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2654 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" { ND_INS_VSHA512MSG1, ND_CAT_SHA512, ND_SET_SHA512, 1663, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2655 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" { ND_INS_VSHA512MSG2, ND_CAT_SHA512, ND_SET_SHA512, 1664, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2656 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" { ND_INS_VSHA512RNDS2, ND_CAT_SHA512, ND_SET_SHA512, 1665, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2657 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" { ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1666, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2658 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" { ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1667, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2659 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" { ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1668, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2660 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" { ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1669, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2661 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" { ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1670, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2662 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" { ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1670, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2663 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" { ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2664 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" { ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1671, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2665 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" { ND_INS_VSM3MSG1, ND_CAT_SM3, ND_SET_SM3, 1672, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2666 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" { ND_INS_VSM3MSG2, ND_CAT_SM3, ND_SET_SM3, 1673, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), }, }, // Pos:2667 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" { ND_INS_VSM3RNDS2, ND_CAT_SM3, ND_SET_SM3, 1674, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), }, }, // Pos:2668 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" { ND_INS_VSM4KEY4, ND_CAT_SM4, ND_SET_SM4, 1675, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2669 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" { ND_INS_VSM4RNDS4, ND_CAT_SM4, ND_SET_SM4, 1676, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2670 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" { ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:2671 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" { ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1677, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2672 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" { ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1678, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), }, }, // Pos:2673 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" { ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:2674 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" { ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1679, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2675 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" { ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2676 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" { ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1680, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2677 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" { ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1681, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2678 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" { ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2679 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" { ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1682, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2680 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" { ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1683, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2681 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" { ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1684, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), }, }, // Pos:2682 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" { ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1684, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2683 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" { ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1685, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), }, }, // Pos:2684 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" { ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1686, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), }, }, // Pos:2685 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" { ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1686, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2686 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" { ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1687, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2687 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" { ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1687, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2688 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" { ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1688, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), }, }, // Pos:2689 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" { ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1689, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), }, }, // Pos:2690 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" { ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1689, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), }, }, // Pos:2691 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" { ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1690, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2692 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" { ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1691, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2693 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" { ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1692, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2694 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" { ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1692, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2695 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" { ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1693, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, 0, 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, 0, 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2696 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" { ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1694, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2697 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" { ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1694, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, 0, 0, { OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2698 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" { ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1695, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2699 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" { ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1695, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2700 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" { ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1696, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2701 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" { ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1696, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2702 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" { ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1697, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2703 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" { ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1697, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2704 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" { ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1698, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2705 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" { ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1698, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), }, }, // Pos:2706 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" { ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1699, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), }, }, // Pos:2707 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" { ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1699, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2708 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" { ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1700, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), }, }, // Pos:2709 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" { ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1700, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2710 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" { ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1701, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2711 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" { ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1702, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, 0, 0, 0, 0, { OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2712 Instruction:"WAIT" Encoding:"0x9B"/"" { ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1703, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2713 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" { ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1704, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2714 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" { ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1705, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, 0, 0, 0, 0, { 0 }, }, // Pos:2715 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" { ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1706, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2716 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" { ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1707, 0, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, 0, 0, 0, 0, { OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2717 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" { ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1708, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2718 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" { ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1709, 0, ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, 0, 0, 0, 0, { OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), }, }, // Pos:2719 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" { ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1710, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WRMSRNS, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2720 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" { ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1711, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, 0, 0, 0, 0, { OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2721 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" { ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1712, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), }, }, // Pos:2722 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" { ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1713, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:2723 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" { ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1714, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:2724 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1715, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:2725 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" { ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1716, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), }, }, // Pos:2726 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" { ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1717, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 0, 0, 0, 0, { OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), }, }, // Pos:2727 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" { ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2728 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" { ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, ND_PREF_LOCK|ND_PREF_HLE, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2729 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" { ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1719, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 0, 0, 0, 0, { OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), }, }, // Pos:2730 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2731 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2732 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2733 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2734 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2735 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2736 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2737 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2738 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2739 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" { ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), }, }, // Pos:2740 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" { ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1721, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2741 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" { ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1722, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2742 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" { ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1723, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2743 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" { ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1724, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2744 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" { ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1725, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2745 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" { ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1726, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 0, 0, 0, 0, { OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), }, }, // Pos:2746 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" { ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2747 Instruction:"XLATB" Encoding:"0xD7"/"" { ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1728, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), OP(ND_OPT_MEM_rBX_AL, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2748 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2749 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2750 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2751 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2752 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2753 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2754 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2755 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2756 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2757 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" { ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, ND_PREF_HLE|ND_PREF_LOCK, ND_MOD_ANY, 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, 0|NDR_RFLAG_AF, 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, { OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2758 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" { ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1730, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), }, }, // Pos:2759 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" { ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1731, 0, ND_MOD_ANY, 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, 0, 0, 0, 0, { OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), }, }, // Pos:2760 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" { ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1732, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 0, 0, 0, 0, { 0 }, }, // Pos:2761 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" { ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1733, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2762 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" { ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1734, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2763 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" { ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1735, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2764 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" { ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1736, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2765 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" { ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1737, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2766 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" { ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1738, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2767 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" { ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1739, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2768 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" { ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1740, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2769 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" { ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1741, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2770 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" { ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1742, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2771 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" { ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1743, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2772 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" { ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1744, 0, ND_MOD_ANY, 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, 0, 0, 0, 0, { OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), }, }, // Pos:2773 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" { ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1745, 0, ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, 0, 0, 0, 0, { OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, // Pos:2774 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" { ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1746, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2775 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" { ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1747, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2776 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" { ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2777 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" { ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, ND_PREF_REP, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, 0, 0, 0, 0, { 0 }, }, // Pos:2778 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" { ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1749, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, 0, 0, 0, 0, { 0 }, }, // Pos:2779 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" { ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1750, 0, ND_MOD_ANY, 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, 0, 0|NDR_RFLAG_ZF, 0, 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, { OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), }, }, }; #endif

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/** @file Include file for the WinNt Library Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef __WIN_NT_INCLUDE_H__ #define __WIN_NT_INCLUDE_H__ #define GUID _WINNT_DUP_GUID_____ #define _LIST_ENTRY _WINNT_DUP_LIST_ENTRY_FORWARD #define LIST_ENTRY _WINNT_DUP_LIST_ENTRY #if (_MSC_VER < 1800) #define InterlockedIncrement _WINNT_DUP_InterlockedIncrement #define InterlockedDecrement _WINNT_DUP_InterlockedDecrement #define InterlockedCompareExchange64 _WINNT_DUP_InterlockedCompareExchange64 #endif #undef UNALIGNED #undef CONST #undef VOID #ifndef __GNUC__ #include "windows.h" // // Win32 include files do not compile clean with /W4, so we use the warning // pragma to suppress the warnings for Win32 only. This way our code can still // compile at /W4 (highest warning level) with /WX (warnings cause build // errors). // #pragma warning(disable : 4115) #pragma warning(disable : 4201) #pragma warning(disable : 4214) #pragma warning(disable : 4028) #pragma warning(disable : 4133) // // Set the warnings back on as the EFI code must be /W4. // #pragma warning(default : 4115) #pragma warning(default : 4201) #pragma warning(default : 4214) #endif #undef GUID #undef _LIST_ENTRY #undef LIST_ENTRY #undef InterlockedIncrement #undef InterlockedDecrement #undef InterlockedCompareExchange64 #undef InterlockedCompareExchangePointer #define VOID void // // Prevent collisions with Windows API name macros that deal with Unicode/Not issues // #undef LoadImage #undef CreateEvent #endif

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// RUN: %sea pf -O0 --devirt-functions "%s" 2>&1 | OutputCheck %s // CHECK: ^unsat$ #include "seahorn/seahorn.h" int a (void); int b (void); int c (void); int d (void); int main(int argc, char** argv) { int (*p) (void); int (*q) (void); if (argc == 1) { p = a; q = c; } else { p = b; q = d; } int x = p(); int y = q(); sassert(x>= 5); sassert(y>= 5); // If we resolve based only on types then we cannot prove this one. // Using aliasing we should be able to prove it. //sassert(y>= 15); return 0; } int a() {return 10;} int b() {return 5;} int c() {return 15;} int d() {return 20;}

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#include <sys/wait.h> pid_t waitpid(pid_t pid, int *status, int options) { return wait4(pid, status, options, NULL); }

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icmp.h

/**************************************************************************** * include/nuttx/net/icmp.h * Header file for the NuttX ICMP stack. * * Copyright (C) 2007-2009, 2012, 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt <gnutt@nuttx.org> * * This logic was leveraged from uIP which also has a BSD-style license: * * Author Adam Dunkels <adam@dunkels.com> * Copyright (c) 2001-2003, Adam Dunkels. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote * products derived from this software without specific prior * written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ #ifndef __INCLUDE_NUTTX_NET_ICMP_H #define __INCLUDE_NUTTX_NET_ICMP_H /**************************************************************************** * Included Files ****************************************************************************/ #include <nuttx/config.h> #include <stdint.h> #include <nuttx/net/netconfig.h> #include <nuttx/net/ip.h> /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ /* ICMP definitions */ /* ICMP Message Types */ #define ICMP_ECHO_REPLY 0 /* RFC 792 */ #define ICMP_DEST_UNREACHABLE 3 /* RFC 792 */ #define ICMP_SRC_QUENCH 4 /* RFC 792 */ #define ICMP_REDIRECT 5 /* RFC 792 */ #define ICMP_ALT_HOST_ADDRESS 6 #define ICMP_ECHO_REQUEST 8 /* RFC 792 */ #define ICMP_ROUTER_ADVERTISEMENT 9 /* RFC 1256 */ #define ICMP_ROUTER_SOLICITATION 10 /* RFC 1256 */ #define ICMP_TIME_EXCEEDED 11 /* RFC 792 */ #define ICMP_PARAMETER_PROBLEM 12 #define ICMP_TIMESTAMP_REQUEST 13 #define ICMP_TIMESTAMP_REPLY 14 #define ICMP_INFORMATION_REQUEST 15 #define ICMP_INFORMATION_REPLY 16 #define ICMP_ADDRESS_MASK_REQUEST 17 #define ICMP_ADDRESS_MASK_REPLY 18 #define ICMP_TRACEROUTE 30 #define ICMP_CONVERSION_ERROR 31 #define ICMP_MOBILE_HOST_REDIRECT 32 #define ICMP_IPV6_WHEREAREYOU 33 #define ICMP_IPV6_IAMHERE 34 #define ICMP_MOBILE_REGIS_REQUEST 35 #define ICMP_MOBILE_REGIS_REPLY 36 #define ICMP_DOMAIN_NAME_REQUEST 37 #define ICMP_DOMAIN_NAME_REPLY 38 #define ICMP_SKIP_DISCOVERY_PROTO 39 #define ICMP_PHOTURIS_SECURITY_FAIL 40 #define ICMP_EXP_MOBILE_PROTO 41 /* RFC 4065 */ /* Header sizes */ #define ICMP_HDRLEN 8 /* Size of ICMP header */ #define IPICMP_HDRLEN (ICMP_HDRLEN + IPv4_HDRLEN) /* Size of IPv4 + ICMP header */ /* Codes for UNREACH. */ #define ICMP_NET_UNREACH 0 /* Network Unreachable */ #define ICMP_HOST_UNREACH 1 /* Host Unreachable */ #define ICMP_PROT_UNREACH 2 /* Protocol Unreachable */ #define ICMP_PORT_UNREACH 3 /* Port Unreachable */ #define ICMP_FRAG_NEEDED 4 /* Fragmentation Needed/DF set */ #define ICMP_SR_FAILED 5 /* Source Route failed */ #define ICMP_NET_UNKNOWN 6 #define ICMP_HOST_UNKNOWN 7 #define ICMP_HOST_ISOLATED 8 #define ICMP_NET_ANO 9 #define ICMP_HOST_ANO 10 #define ICMP_NET_UNR_TOS 11 #define ICMP_HOST_UNR_TOS 12 #define ICMP_PKT_FILTERED 13 /* Packet filtered */ #define ICMP_PREC_VIOLATION 14 /* Precedence violation */ #define ICMP_PREC_CUTOFF 15 /* Precedence cut off */ #define NR_ICMP_UNREACH 15 /* instead of hardcoding immediate value */ /* Codes for TIME_EXCEEDED. */ #define ICMP_EXC_TTL 0 /* TTL count exceeded */ #define ICMP_EXC_FRAGTIME 1 /* Fragment Reassembly time exceeded */ #define ICMP_FILTER 1 /**************************************************************************** * Public Type Definitions ****************************************************************************/ struct icmp_hdr_s { /* ICMP header */ uint8_t type; /* Defines the format of the ICMP message */ uint8_t icode; /* Further qualifies the ICMP message */ uint16_t icmpchksum; /* Checksum of ICMP header and data */ /* All ICMP packets have an 8-byte header and variable-sized data section. * The first 4 bytes of the header have fixed format, while the last * 4 bytes depend on the type/code of that ICMP packet. */ /* ICMP_ECHO_REQUEST and ICMP_ECHO_REPLY data */ union { struct { uint16_t id; /* Used to match requests with replies */ uint16_t seqno; /* " " "" " " " " " " " " */ }; uint16_t data[2]; }; }; /* The structure holding the ICMP statistics that are gathered if * CONFIG_NET_STATISTICS is defined. */ #ifdef CONFIG_NET_STATISTICS struct icmp_stats_s { net_stats_t drop; /* Number of dropped ICMP packets */ net_stats_t recv; /* Number of received ICMP packets */ net_stats_t sent; /* Number of sent ICMP packets */ net_stats_t typeerr; /* Number of ICMP packets with a wrong type */ }; #endif /**************************************************************************** * Public Data ****************************************************************************/ #ifdef __cplusplus #define EXTERN extern "C" extern "C" { #else #define EXTERN extern #endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ #undef EXTERN #ifdef __cplusplus } #endif #endif /* __INCLUDE_NUTTX_NET_ICMP_H */

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qu8-dwconv-25p16c-minmax-fp32-wasmsimd-mul16.c

// Auto-generated file. Do not edit! // Template: src/qs8-dwconv/unipass-wasmsimd-mul16.c.in // Generator: tools/xngen // // Copyright 2020 Google LLC // // This source code is licensed under the BSD-style license found in the // LICENSE file in the root directory of this source tree. #include <assert.h> #include <wasm_simd128.h> #include <xnnpack/dwconv.h> void xnn_qu8_dwconv_minmax_fp32_ukernel_25p16c__wasmsimd_mul16( size_t channels, size_t output_width, const uint8_t** input, const void* weights, uint8_t* output, intptr_t input_stride, size_t output_increment, size_t input_offset, const uint8_t* zero, const union xnn_qu8_conv_minmax_params params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS { assert(channels != 0); assert(output_width != 0); const v128_t vkernel_zero_point = wasm_u32x4_load16x4(params->fp32_wasmsimd.kernel_zero_point); do { const uint8_t* i0 = input[0]; assert(i0 != NULL); if XNN_UNPREDICTABLE(i0 != zero) { i0 = (const uint8_t*) ((uintptr_t) i0 + input_offset); } const uint8_t* i1 = input[1]; assert(i1 != NULL); if XNN_UNPREDICTABLE(i1 != zero) { i1 = (const uint8_t*) ((uintptr_t) i1 + input_offset); } const uint8_t* i2 = input[2]; assert(i2 != NULL); if XNN_UNPREDICTABLE(i2 != zero) { i2 = (const uint8_t*) ((uintptr_t) i2 + input_offset); } const uint8_t* i3 = input[3]; assert(i3 != NULL); if XNN_UNPREDICTABLE(i3 != zero) { i3 = (const uint8_t*) ((uintptr_t) i3 + input_offset); } const uint8_t* i4 = input[4]; assert(i4 != NULL); if XNN_UNPREDICTABLE(i4 != zero) { i4 = (const uint8_t*) ((uintptr_t) i4 + input_offset); } const uint8_t* i5 = input[5]; assert(i5 != NULL); if XNN_UNPREDICTABLE(i5 != zero) { i5 = (const uint8_t*) ((uintptr_t) i5 + input_offset); } const uint8_t* i6 = input[6]; assert(i6 != NULL); if XNN_UNPREDICTABLE(i6 != zero) { i6 = (const uint8_t*) ((uintptr_t) i6 + input_offset); } const uint8_t* i7 = input[7]; assert(i7 != NULL); if XNN_UNPREDICTABLE(i7 != zero) { i7 = (const uint8_t*) ((uintptr_t) i7 + input_offset); } const uint8_t* i8 = input[8]; assert(i8 != NULL); if XNN_UNPREDICTABLE(i8 != zero) { i8 = (const uint8_t*) ((uintptr_t) i8 + input_offset); } const uint8_t* i9 = input[9]; assert(i9 != NULL); if XNN_UNPREDICTABLE(i9 != zero) { i9 = (const uint8_t*) ((uintptr_t) i9 + input_offset); } const uint8_t* i10 = input[10]; assert(i10 != NULL); if XNN_UNPREDICTABLE(i10 != zero) { i10 = (const uint8_t*) ((uintptr_t) i10 + input_offset); } const uint8_t* i11 = input[11]; assert(i11 != NULL); if XNN_UNPREDICTABLE(i11 != zero) { i11 = (const uint8_t*) ((uintptr_t) i11 + input_offset); } const uint8_t* i12 = input[12]; assert(i12 != NULL); if XNN_UNPREDICTABLE(i12 != zero) { i12 = (const uint8_t*) ((uintptr_t) i12 + input_offset); } const uint8_t* i13 = input[13]; assert(i13 != NULL); if XNN_UNPREDICTABLE(i13 != zero) { i13 = (const uint8_t*) ((uintptr_t) i13 + input_offset); } const uint8_t* i14 = input[14]; assert(i14 != NULL); if XNN_UNPREDICTABLE(i14 != zero) { i14 = (const uint8_t*) ((uintptr_t) i14 + input_offset); } const uint8_t* i15 = input[15]; assert(i15 != NULL); if XNN_UNPREDICTABLE(i15 != zero) { i15 = (const uint8_t*) ((uintptr_t) i15 + input_offset); } const uint8_t* i16 = input[16]; assert(i16 != NULL); if XNN_UNPREDICTABLE(i16 != zero) { i16 = (const uint8_t*) ((uintptr_t) i16 + input_offset); } const uint8_t* i17 = input[17]; assert(i17 != NULL); if XNN_UNPREDICTABLE(i17 != zero) { i17 = (const uint8_t*) ((uintptr_t) i17 + input_offset); } const uint8_t* i18 = input[18]; assert(i18 != NULL); if XNN_UNPREDICTABLE(i18 != zero) { i18 = (const uint8_t*) ((uintptr_t) i18 + input_offset); } const uint8_t* i19 = input[19]; assert(i19 != NULL); if XNN_UNPREDICTABLE(i19 != zero) { i19 = (const uint8_t*) ((uintptr_t) i19 + input_offset); } const uint8_t* i20 = input[20]; assert(i20 != NULL); if XNN_UNPREDICTABLE(i20 != zero) { i20 = (const uint8_t*) ((uintptr_t) i20 + input_offset); } const uint8_t* i21 = input[21]; assert(i21 != NULL); if XNN_UNPREDICTABLE(i21 != zero) { i21 = (const uint8_t*) ((uintptr_t) i21 + input_offset); } const uint8_t* i22 = input[22]; assert(i22 != NULL); if XNN_UNPREDICTABLE(i22 != zero) { i22 = (const uint8_t*) ((uintptr_t) i22 + input_offset); } const uint8_t* i23 = input[23]; assert(i23 != NULL); if XNN_UNPREDICTABLE(i23 != zero) { i23 = (const uint8_t*) ((uintptr_t) i23 + input_offset); } const uint8_t* i24 = input[24]; assert(i24 != NULL); if XNN_UNPREDICTABLE(i24 != zero) { i24 = (const uint8_t*) ((uintptr_t) i24 + input_offset); } input = (const uint8_t**) ((uintptr_t) input + input_stride); size_t c = channels; const void* w = weights; for (; c >= 16; c -= 16) { v128_t vacc0123 = wasm_v128_load(w); v128_t vacc4567 = wasm_v128_load((const void*) ((uintptr_t) w + 4 * sizeof(int32_t))); v128_t vacc89AB = wasm_v128_load((const void*) ((uintptr_t) w + 8 * sizeof(int32_t))); v128_t vaccCDEF = wasm_v128_load((const void*) ((uintptr_t) w + 12 * sizeof(int32_t))); const v128_t vi0x01234567 = wasm_u16x8_load8x8(i0); const v128_t vk0x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 0 * sizeof(uint8_t))); const v128_t vi0x89ABCDEF = wasm_u16x8_load8x8(i0 + 8); const v128_t vk0x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 8 * sizeof(uint8_t))); i0 += 16; v128_t vprod01234567 = wasm_i16x8_mul(vi0x01234567, vk0x01234567); v128_t vprod89ABCDEF = wasm_i16x8_mul(vi0x89ABCDEF, vk0x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi1x01234567 = wasm_u16x8_load8x8(i1); const v128_t vk1x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 16 * sizeof(uint8_t))); const v128_t vi1x89ABCDEF = wasm_u16x8_load8x8(i1 + 8); const v128_t vk1x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 24 * sizeof(uint8_t))); v128_t vsumx01234567 = wasm_i16x8_add(vi0x01234567, vi1x01234567); v128_t vsumx89ABCDEF = wasm_i16x8_add(vi0x89ABCDEF, vi1x89ABCDEF); i1 += 16; vprod01234567 = wasm_i16x8_mul(vi1x01234567, vk1x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi1x89ABCDEF, vk1x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi2x01234567 = wasm_u16x8_load8x8(i2); const v128_t vk2x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 32 * sizeof(uint8_t))); const v128_t vi2x89ABCDEF = wasm_u16x8_load8x8(i2 + 8); const v128_t vk2x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 40 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi2x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi2x89ABCDEF); i2 += 16; vprod01234567 = wasm_i16x8_mul(vi2x01234567, vk2x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi2x89ABCDEF, vk2x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi3x01234567 = wasm_u16x8_load8x8(i3); const v128_t vk3x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 48 * sizeof(uint8_t))); const v128_t vi3x89ABCDEF = wasm_u16x8_load8x8(i3 + 8); const v128_t vk3x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 56 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi3x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi3x89ABCDEF); i3 += 16; vprod01234567 = wasm_i16x8_mul(vi3x01234567, vk3x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi3x89ABCDEF, vk3x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi4x01234567 = wasm_u16x8_load8x8(i4); const v128_t vk4x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 64 * sizeof(uint8_t))); const v128_t vi4x89ABCDEF = wasm_u16x8_load8x8(i4 + 8); const v128_t vk4x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 72 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi4x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi4x89ABCDEF); i4 += 16; vprod01234567 = wasm_i16x8_mul(vi4x01234567, vk4x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi4x89ABCDEF, vk4x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi5x01234567 = wasm_u16x8_load8x8(i5); const v128_t vk5x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 80 * sizeof(uint8_t))); const v128_t vi5x89ABCDEF = wasm_u16x8_load8x8(i5 + 8); const v128_t vk5x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 88 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi5x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi5x89ABCDEF); i5 += 16; vprod01234567 = wasm_i16x8_mul(vi5x01234567, vk5x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi5x89ABCDEF, vk5x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi6x01234567 = wasm_u16x8_load8x8(i6); const v128_t vk6x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 96 * sizeof(uint8_t))); const v128_t vi6x89ABCDEF = wasm_u16x8_load8x8(i6 + 8); const v128_t vk6x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 104 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi6x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi6x89ABCDEF); i6 += 16; vprod01234567 = wasm_i16x8_mul(vi6x01234567, vk6x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi6x89ABCDEF, vk6x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi7x01234567 = wasm_u16x8_load8x8(i7); const v128_t vk7x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 112 * sizeof(uint8_t))); const v128_t vi7x89ABCDEF = wasm_u16x8_load8x8(i7 + 8); const v128_t vk7x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 120 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi7x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi7x89ABCDEF); i7 += 16; vprod01234567 = wasm_i16x8_mul(vi7x01234567, vk7x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi7x89ABCDEF, vk7x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi8x01234567 = wasm_u16x8_load8x8(i8); const v128_t vk8x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 128 * sizeof(uint8_t))); const v128_t vi8x89ABCDEF = wasm_u16x8_load8x8(i8 + 8); const v128_t vk8x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 136 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi8x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi8x89ABCDEF); i8 += 16; vprod01234567 = wasm_i16x8_mul(vi8x01234567, vk8x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi8x89ABCDEF, vk8x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi9x01234567 = wasm_u16x8_load8x8(i9); const v128_t vk9x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 144 * sizeof(uint8_t))); const v128_t vi9x89ABCDEF = wasm_u16x8_load8x8(i9 + 8); const v128_t vk9x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 152 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi9x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi9x89ABCDEF); i9 += 16; vprod01234567 = wasm_i16x8_mul(vi9x01234567, vk9x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi9x89ABCDEF, vk9x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi10x01234567 = wasm_u16x8_load8x8(i10); const v128_t vk10x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 160 * sizeof(uint8_t))); const v128_t vi10x89ABCDEF = wasm_u16x8_load8x8(i10 + 8); const v128_t vk10x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 168 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi10x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi10x89ABCDEF); i10 += 16; vprod01234567 = wasm_i16x8_mul(vi10x01234567, vk10x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi10x89ABCDEF, vk10x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi11x01234567 = wasm_u16x8_load8x8(i11); const v128_t vk11x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 176 * sizeof(uint8_t))); const v128_t vi11x89ABCDEF = wasm_u16x8_load8x8(i11 + 8); const v128_t vk11x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 184 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi11x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi11x89ABCDEF); i11 += 16; vprod01234567 = wasm_i16x8_mul(vi11x01234567, vk11x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi11x89ABCDEF, vk11x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi12x01234567 = wasm_u16x8_load8x8(i12); const v128_t vk12x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 192 * sizeof(uint8_t))); const v128_t vi12x89ABCDEF = wasm_u16x8_load8x8(i12 + 8); const v128_t vk12x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 200 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi12x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi12x89ABCDEF); i12 += 16; vprod01234567 = wasm_i16x8_mul(vi12x01234567, vk12x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi12x89ABCDEF, vk12x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi13x01234567 = wasm_u16x8_load8x8(i13); const v128_t vk13x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 208 * sizeof(uint8_t))); const v128_t vi13x89ABCDEF = wasm_u16x8_load8x8(i13 + 8); const v128_t vk13x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 216 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi13x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi13x89ABCDEF); i13 += 16; vprod01234567 = wasm_i16x8_mul(vi13x01234567, vk13x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi13x89ABCDEF, vk13x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi14x01234567 = wasm_u16x8_load8x8(i14); const v128_t vk14x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 224 * sizeof(uint8_t))); const v128_t vi14x89ABCDEF = wasm_u16x8_load8x8(i14 + 8); const v128_t vk14x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 232 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi14x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi14x89ABCDEF); i14 += 16; vprod01234567 = wasm_i16x8_mul(vi14x01234567, vk14x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi14x89ABCDEF, vk14x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi15x01234567 = wasm_u16x8_load8x8(i15); const v128_t vk15x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 240 * sizeof(uint8_t))); const v128_t vi15x89ABCDEF = wasm_u16x8_load8x8(i15 + 8); const v128_t vk15x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 248 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi15x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi15x89ABCDEF); i15 += 16; vprod01234567 = wasm_i16x8_mul(vi15x01234567, vk15x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi15x89ABCDEF, vk15x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi16x01234567 = wasm_u16x8_load8x8(i16); const v128_t vk16x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 256 * sizeof(uint8_t))); const v128_t vi16x89ABCDEF = wasm_u16x8_load8x8(i16 + 8); const v128_t vk16x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 264 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi16x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi16x89ABCDEF); i16 += 16; vprod01234567 = wasm_i16x8_mul(vi16x01234567, vk16x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi16x89ABCDEF, vk16x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi17x01234567 = wasm_u16x8_load8x8(i17); const v128_t vk17x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 272 * sizeof(uint8_t))); const v128_t vi17x89ABCDEF = wasm_u16x8_load8x8(i17 + 8); const v128_t vk17x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 280 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi17x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi17x89ABCDEF); i17 += 16; vprod01234567 = wasm_i16x8_mul(vi17x01234567, vk17x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi17x89ABCDEF, vk17x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi18x01234567 = wasm_u16x8_load8x8(i18); const v128_t vk18x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 288 * sizeof(uint8_t))); const v128_t vi18x89ABCDEF = wasm_u16x8_load8x8(i18 + 8); const v128_t vk18x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 296 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi18x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi18x89ABCDEF); i18 += 16; vprod01234567 = wasm_i16x8_mul(vi18x01234567, vk18x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi18x89ABCDEF, vk18x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi19x01234567 = wasm_u16x8_load8x8(i19); const v128_t vk19x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 304 * sizeof(uint8_t))); const v128_t vi19x89ABCDEF = wasm_u16x8_load8x8(i19 + 8); const v128_t vk19x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 312 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi19x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi19x89ABCDEF); i19 += 16; vprod01234567 = wasm_i16x8_mul(vi19x01234567, vk19x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi19x89ABCDEF, vk19x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi20x01234567 = wasm_u16x8_load8x8(i20); const v128_t vk20x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 320 * sizeof(uint8_t))); const v128_t vi20x89ABCDEF = wasm_u16x8_load8x8(i20 + 8); const v128_t vk20x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 328 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi20x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi20x89ABCDEF); i20 += 16; vprod01234567 = wasm_i16x8_mul(vi20x01234567, vk20x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi20x89ABCDEF, vk20x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi21x01234567 = wasm_u16x8_load8x8(i21); const v128_t vk21x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 336 * sizeof(uint8_t))); const v128_t vi21x89ABCDEF = wasm_u16x8_load8x8(i21 + 8); const v128_t vk21x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 344 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi21x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi21x89ABCDEF); i21 += 16; vprod01234567 = wasm_i16x8_mul(vi21x01234567, vk21x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi21x89ABCDEF, vk21x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi22x01234567 = wasm_u16x8_load8x8(i22); const v128_t vk22x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 352 * sizeof(uint8_t))); const v128_t vi22x89ABCDEF = wasm_u16x8_load8x8(i22 + 8); const v128_t vk22x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 360 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi22x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi22x89ABCDEF); i22 += 16; vprod01234567 = wasm_i16x8_mul(vi22x01234567, vk22x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi22x89ABCDEF, vk22x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi23x01234567 = wasm_u16x8_load8x8(i23); const v128_t vk23x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 368 * sizeof(uint8_t))); const v128_t vi23x89ABCDEF = wasm_u16x8_load8x8(i23 + 8); const v128_t vk23x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 376 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi23x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi23x89ABCDEF); i23 += 16; vprod01234567 = wasm_i16x8_mul(vi23x01234567, vk23x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi23x89ABCDEF, vk23x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); const v128_t vi24x01234567 = wasm_u16x8_load8x8(i24); const v128_t vk24x01234567 = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 384 * sizeof(uint8_t))); const v128_t vi24x89ABCDEF = wasm_u16x8_load8x8(i24 + 8); const v128_t vk24x89ABCDEF = wasm_u16x8_load8x8((const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 392 * sizeof(uint8_t))); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi24x01234567); vsumx89ABCDEF = wasm_i16x8_add(vsumx89ABCDEF, vi24x89ABCDEF); i24 += 16; vprod01234567 = wasm_i16x8_mul(vi24x01234567, vk24x01234567); vprod89ABCDEF = wasm_i16x8_mul(vi24x89ABCDEF, vk24x89ABCDEF); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); vacc89AB = wasm_i32x4_add(vacc89AB, wasm_u32x4_extend_low_u16x8(vprod89ABCDEF)); vaccCDEF = wasm_i32x4_add(vaccCDEF, wasm_u32x4_extend_high_u16x8(vprod89ABCDEF)); vacc0123 = wasm_i32x4_sub(vacc0123, wasm_i32x4_mul(wasm_u32x4_extend_low_u16x8(vsumx01234567), vkernel_zero_point)); vacc4567 = wasm_i32x4_sub(vacc4567, wasm_i32x4_mul(wasm_u32x4_extend_high_u16x8(vsumx01234567), vkernel_zero_point)); vacc89AB = wasm_i32x4_sub(vacc89AB, wasm_i32x4_mul(wasm_u32x4_extend_low_u16x8(vsumx89ABCDEF), vkernel_zero_point)); vaccCDEF = wasm_i32x4_sub(vaccCDEF, wasm_i32x4_mul(wasm_u32x4_extend_high_u16x8(vsumx89ABCDEF), vkernel_zero_point)); w = (const void*) ((uintptr_t) w + 16 * sizeof(int32_t) + 400 * sizeof(uint8_t)); vacc0123 = wasm_f32x4_convert_i32x4(vacc0123); vacc4567 = wasm_f32x4_convert_i32x4(vacc4567); vacc89AB = wasm_f32x4_convert_i32x4(vacc89AB); vaccCDEF = wasm_f32x4_convert_i32x4(vaccCDEF); const v128_t vscale = wasm_v128_load64_splat(params->fp32_wasmsimd.scale); vacc0123 = wasm_f32x4_mul(vacc0123, vscale); vacc4567 = wasm_f32x4_mul(vacc4567, vscale); vacc89AB = wasm_f32x4_mul(vacc89AB, vscale); vaccCDEF = wasm_f32x4_mul(vaccCDEF, vscale); const v128_t vmagic_bias = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_bias); vacc0123 = wasm_f32x4_add(vacc0123, vmagic_bias); vacc4567 = wasm_f32x4_add(vacc4567, vmagic_bias); vacc89AB = wasm_f32x4_add(vacc89AB, vmagic_bias); vaccCDEF = wasm_f32x4_add(vaccCDEF, vmagic_bias); const v128_t vmagic_min = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_min); vacc0123 = wasm_i32x4_max(vacc0123, vmagic_min); vacc4567 = wasm_i32x4_max(vacc4567, vmagic_min); vacc89AB = wasm_i32x4_max(vacc89AB, vmagic_min); vaccCDEF = wasm_i32x4_max(vaccCDEF, vmagic_min); const v128_t vmagic_bias_less_output_zero_point = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_bias_less_output_zero_point); vacc0123 = wasm_i32x4_sub(vacc0123, vmagic_bias_less_output_zero_point); vacc4567 = wasm_i32x4_sub(vacc4567, vmagic_bias_less_output_zero_point); vacc89AB = wasm_i32x4_sub(vacc89AB, vmagic_bias_less_output_zero_point); vaccCDEF = wasm_i32x4_sub(vaccCDEF, vmagic_bias_less_output_zero_point); v128_t vout01234567 = wasm_i16x8_narrow_i32x4(vacc0123, vacc4567); v128_t vout89ABCDEF = wasm_i16x8_narrow_i32x4(vacc89AB, vaccCDEF); v128_t vout0123456789ABCDEF = wasm_u8x16_narrow_i16x8(vout01234567, vout89ABCDEF); const v128_t voutput_max = wasm_v128_load64_splat(params->fp32_wasmsimd.output_max); vout0123456789ABCDEF = wasm_u8x16_min(vout0123456789ABCDEF, voutput_max); wasm_v128_store(output, vout0123456789ABCDEF); output += 16; } if XNN_UNLIKELY(c != 0) { const uint8_t* k = (const uint8_t*) ((uintptr_t) w + 16 * sizeof(int32_t)); do { v128_t vacc0123 = wasm_v128_load(w); v128_t vacc4567 = wasm_v128_load((const void*) ((uintptr_t) w + 4 * sizeof(int32_t))); const v128_t vi0x01234567 = wasm_u16x8_load8x8(i0); const v128_t vk0x01234567 = wasm_u16x8_load8x8(k); i0 += 8; v128_t vprod01234567 = wasm_i16x8_mul(vi0x01234567, vk0x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi1x01234567 = wasm_u16x8_load8x8(i1); const v128_t vk1x01234567 = wasm_u16x8_load8x8((const void*) (k + 16)); v128_t vsumx01234567 = wasm_i16x8_add(vi0x01234567, vi1x01234567); i1 += 8; vprod01234567 = wasm_i16x8_mul(vi1x01234567, vk1x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi2x01234567 = wasm_u16x8_load8x8(i2); const v128_t vk2x01234567 = wasm_u16x8_load8x8((const void*) (k + 32)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi2x01234567); i2 += 8; vprod01234567 = wasm_i16x8_mul(vi2x01234567, vk2x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi3x01234567 = wasm_u16x8_load8x8(i3); const v128_t vk3x01234567 = wasm_u16x8_load8x8((const void*) (k + 48)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi3x01234567); i3 += 8; vprod01234567 = wasm_i16x8_mul(vi3x01234567, vk3x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi4x01234567 = wasm_u16x8_load8x8(i4); const v128_t vk4x01234567 = wasm_u16x8_load8x8((const void*) (k + 64)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi4x01234567); i4 += 8; vprod01234567 = wasm_i16x8_mul(vi4x01234567, vk4x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi5x01234567 = wasm_u16x8_load8x8(i5); const v128_t vk5x01234567 = wasm_u16x8_load8x8((const void*) (k + 80)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi5x01234567); i5 += 8; vprod01234567 = wasm_i16x8_mul(vi5x01234567, vk5x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi6x01234567 = wasm_u16x8_load8x8(i6); const v128_t vk6x01234567 = wasm_u16x8_load8x8((const void*) (k + 96)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi6x01234567); i6 += 8; vprod01234567 = wasm_i16x8_mul(vi6x01234567, vk6x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi7x01234567 = wasm_u16x8_load8x8(i7); const v128_t vk7x01234567 = wasm_u16x8_load8x8((const void*) (k + 112)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi7x01234567); i7 += 8; vprod01234567 = wasm_i16x8_mul(vi7x01234567, vk7x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi8x01234567 = wasm_u16x8_load8x8(i8); const v128_t vk8x01234567 = wasm_u16x8_load8x8((const void*) (k + 128)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi8x01234567); i8 += 8; vprod01234567 = wasm_i16x8_mul(vi8x01234567, vk8x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi9x01234567 = wasm_u16x8_load8x8(i9); const v128_t vk9x01234567 = wasm_u16x8_load8x8((const void*) (k + 144)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi9x01234567); i9 += 8; vprod01234567 = wasm_i16x8_mul(vi9x01234567, vk9x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi10x01234567 = wasm_u16x8_load8x8(i10); const v128_t vk10x01234567 = wasm_u16x8_load8x8((const void*) (k + 160)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi10x01234567); i10 += 8; vprod01234567 = wasm_i16x8_mul(vi10x01234567, vk10x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi11x01234567 = wasm_u16x8_load8x8(i11); const v128_t vk11x01234567 = wasm_u16x8_load8x8((const void*) (k + 176)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi11x01234567); i11 += 8; vprod01234567 = wasm_i16x8_mul(vi11x01234567, vk11x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi12x01234567 = wasm_u16x8_load8x8(i12); const v128_t vk12x01234567 = wasm_u16x8_load8x8((const void*) (k + 192)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi12x01234567); i12 += 8; vprod01234567 = wasm_i16x8_mul(vi12x01234567, vk12x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi13x01234567 = wasm_u16x8_load8x8(i13); const v128_t vk13x01234567 = wasm_u16x8_load8x8((const void*) (k + 208)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi13x01234567); i13 += 8; vprod01234567 = wasm_i16x8_mul(vi13x01234567, vk13x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi14x01234567 = wasm_u16x8_load8x8(i14); const v128_t vk14x01234567 = wasm_u16x8_load8x8((const void*) (k + 224)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi14x01234567); i14 += 8; vprod01234567 = wasm_i16x8_mul(vi14x01234567, vk14x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi15x01234567 = wasm_u16x8_load8x8(i15); const v128_t vk15x01234567 = wasm_u16x8_load8x8((const void*) (k + 240)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi15x01234567); i15 += 8; vprod01234567 = wasm_i16x8_mul(vi15x01234567, vk15x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi16x01234567 = wasm_u16x8_load8x8(i16); const v128_t vk16x01234567 = wasm_u16x8_load8x8((const void*) (k + 256)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi16x01234567); i16 += 8; vprod01234567 = wasm_i16x8_mul(vi16x01234567, vk16x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi17x01234567 = wasm_u16x8_load8x8(i17); const v128_t vk17x01234567 = wasm_u16x8_load8x8((const void*) (k + 272)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi17x01234567); i17 += 8; vprod01234567 = wasm_i16x8_mul(vi17x01234567, vk17x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi18x01234567 = wasm_u16x8_load8x8(i18); const v128_t vk18x01234567 = wasm_u16x8_load8x8((const void*) (k + 288)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi18x01234567); i18 += 8; vprod01234567 = wasm_i16x8_mul(vi18x01234567, vk18x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi19x01234567 = wasm_u16x8_load8x8(i19); const v128_t vk19x01234567 = wasm_u16x8_load8x8((const void*) (k + 304)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi19x01234567); i19 += 8; vprod01234567 = wasm_i16x8_mul(vi19x01234567, vk19x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi20x01234567 = wasm_u16x8_load8x8(i20); const v128_t vk20x01234567 = wasm_u16x8_load8x8((const void*) (k + 320)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi20x01234567); i20 += 8; vprod01234567 = wasm_i16x8_mul(vi20x01234567, vk20x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi21x01234567 = wasm_u16x8_load8x8(i21); const v128_t vk21x01234567 = wasm_u16x8_load8x8((const void*) (k + 336)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi21x01234567); i21 += 8; vprod01234567 = wasm_i16x8_mul(vi21x01234567, vk21x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi22x01234567 = wasm_u16x8_load8x8(i22); const v128_t vk22x01234567 = wasm_u16x8_load8x8((const void*) (k + 352)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi22x01234567); i22 += 8; vprod01234567 = wasm_i16x8_mul(vi22x01234567, vk22x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi23x01234567 = wasm_u16x8_load8x8(i23); const v128_t vk23x01234567 = wasm_u16x8_load8x8((const void*) (k + 368)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi23x01234567); i23 += 8; vprod01234567 = wasm_i16x8_mul(vi23x01234567, vk23x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); const v128_t vi24x01234567 = wasm_u16x8_load8x8(i24); const v128_t vk24x01234567 = wasm_u16x8_load8x8((const void*) (k + 384)); vsumx01234567 = wasm_i16x8_add(vsumx01234567, vi24x01234567); i24 += 8; vprod01234567 = wasm_i16x8_mul(vi24x01234567, vk24x01234567); vacc0123 = wasm_i32x4_add(vacc0123, wasm_u32x4_extend_low_u16x8(vprod01234567)); vacc4567 = wasm_i32x4_add(vacc4567, wasm_u32x4_extend_high_u16x8(vprod01234567)); k += 8; vacc0123 = wasm_i32x4_sub(vacc0123, wasm_i32x4_mul(wasm_u32x4_extend_low_u16x8(vsumx01234567), vkernel_zero_point)); vacc4567 = wasm_i32x4_sub(vacc4567, wasm_i32x4_mul(wasm_u32x4_extend_high_u16x8(vsumx01234567), vkernel_zero_point)); vacc0123 = wasm_f32x4_convert_i32x4(vacc0123); vacc4567 = wasm_f32x4_convert_i32x4(vacc4567); const v128_t vscale = wasm_v128_load64_splat(params->fp32_wasmsimd.scale); vacc0123 = wasm_f32x4_mul(vacc0123, vscale); vacc4567 = wasm_f32x4_mul(vacc4567, vscale); const v128_t vmagic_bias = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_bias); vacc0123 = wasm_f32x4_add(vacc0123, vmagic_bias); vacc4567 = wasm_f32x4_add(vacc4567, vmagic_bias); const v128_t vmagic_min = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_min); vacc0123 = wasm_i32x4_max(vacc0123, vmagic_min); vacc4567 = wasm_i32x4_max(vacc4567, vmagic_min); const v128_t vmagic_bias_less_output_zero_point = wasm_v128_load64_splat(params->fp32_wasmsimd.magic_bias_less_output_zero_point); vacc0123 = wasm_i32x4_sub(vacc0123, vmagic_bias_less_output_zero_point); vacc4567 = wasm_i32x4_sub(vacc4567, vmagic_bias_less_output_zero_point); v128_t vout01234567 = wasm_i16x8_narrow_i32x4(vacc0123, vacc4567); v128_t vout0123456701234567 = wasm_u8x16_narrow_i16x8(vout01234567, vout01234567); const v128_t voutput_max = wasm_v128_load64_splat(params->fp32_wasmsimd.output_max); vout0123456701234567 = wasm_u8x16_min(vout0123456701234567, voutput_max); w = (const void*) ((uintptr_t) w + 8 * sizeof(int32_t)); if XNN_LIKELY(c >= 8) { wasm_v128_store64_lane(output, vout0123456701234567, 0); output += 8; c -= 8; } else { if (c & 4) { wasm_v128_store32_lane(output, vout0123456701234567, 0); vout0123456701234567 = wasm_u64x2_shr(vout0123456701234567, 32); output += 4; } if (c & 2) { wasm_v128_store16_lane(output, vout0123456701234567, 0); vout0123456701234567 = wasm_u32x4_shr(vout0123456701234567, 16); output += 2; } if (c & 1) { wasm_v128_store8_lane(output, vout0123456701234567, 0); output += 1; } c = 0; } } while (c != 0); } output = (uint8_t*) ((uintptr_t) output + output_increment); } while (--output_width != 0); }

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/AKWF-c/AKWF_linear/AKWF_linear_0020.h

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[ "CC0-1.0" ]

permissive

KristofferKarlAxelEkstrand/AKWF-FREE

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2023-07-23T18:22:36.939705

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CC0-1.0

2023-07-10T17:14:41

2018-08-23T07:26:56

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UTF-8

C

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4,686

h

AKWF_linear_0020.h

/* Adventure Kid Waveforms (AKWF) converted for use with Teensy Audio Library * * Adventure Kid Waveforms(AKWF) Open waveforms library * https://www.adventurekid.se/akrt/waveforms/adventure-kid-waveforms/ * * This code is in the public domain, CC0 1.0 Universal (CC0 1.0) * https://creativecommons.org/publicdomain/zero/1.0/ * * Converted by Brad Roy, https://github.com/prosper00 */ /* AKWF_linear_0020 256 samples +-----------------------------------------------------------------------------------------------------------------+ | ****** **** | | ***** **** | | **** ** | | **** ** | | ****** ** | | ***** ** | | ******* ** | |**** ** ***| | ** ******* | | ** **** | | ** **** | | ** ***** | | ** **** | | ** **** | | ***** ****** | +-----------------------------------------------------------------------------------------------------------------+ */ const uint16_t AKWF_linear_0020 [] = { 32821, 33043, 33276, 33504, 33766, 34070, 34372, 34675, 34977, 35278, 35581, 35882, 36185, 36486, 36789, 37088, 37390, 37691, 37995, 38293, 38597, 38893, 39218, 39612, 40014, 40413, 40814, 41212, 41613, 42011, 42412, 42810, 43210, 43608, 44009, 44406, 44805, 45204, 45604, 46001, 46403, 46860, 47338, 47809, 48283, 48754, 49227, 49698, 50171, 50644, 51115, 51586, 52058, 52530, 53001, 53473, 53944, 54416, 54888, 55339, 55771, 56207, 56640, 57076, 57510, 57944, 58378, 58812, 59246, 59679, 60114, 60545, 60980, 61410, 61850, 62274, 62722, 63061, 63199, 63341, 63481, 63619, 63764, 63899, 64043, 64179, 64322, 64457, 64603, 64734, 64883, 65012, 65163, 65290, 65448, 65496, 65042, 64473, 63941, 63383, 62847, 62291, 61755, 61200, 60661, 60108, 59568, 59018, 58473, 57926, 57379, 56841, 56285, 55738, 54496, 52863, 51310, 49708, 48143, 46553, 44980, 43393, 41819, 40235, 38660, 37078, 35502, 33921, 32347, 30764, 29197, 27602, 26186, 24988, 23768, 22563, 21351, 20145, 18935, 17726, 16519, 15306, 14106, 12889, 11693, 10474, 9282, 8058, 6879, 5628, 4638, 4380, 4184, 3974, 3776, 3565, 3371, 3160, 2965, 2753, 2560, 2349, 2154, 1945, 1750, 1544, 1346, 1139, 956, 1065, 1285, 1470, 1679, 1868, 2075, 2269, 2472, 2667, 2868, 3065, 3264, 3464, 3662, 3862, 4057, 4262, 4448, 4791, 5266, 5716, 6179, 6634, 7096, 7552, 8011, 8469, 8927, 9386, 9843, 10301, 10758, 11216, 11673, 12132, 12590, 13045, 13492, 13942, 14390, 14839, 15288, 15737, 16185, 16633, 17081, 17530, 17977, 18426, 18873, 19320, 19768, 20215, 20663, 21110, 21564, 22018, 22473, 22926, 23380, 23833, 24288, 24741, 25196, 25647, 26101, 26553, 27007, 27460, 27911, 28365, 28814, 29269, 29576, 29797, 30034, 30263, 30496, 30726, 30959, 31191, 31421, 31654, 31881, 32117, 32342, 32582, };

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/third_party/grpc/src/third_party/upb/upb/util/required_fields.h

874914bd67698b54a129d34a710d7624b492b465

[ "BSD-3-Clause", "MPL-2.0", "Apache-2.0", "LGPL-2.0-or-later", "MIT", "GPL-1.0-or-later" ]

permissive

iridium-browser/iridium-browser

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h

required_fields.h

/* * Copyright (c) 2009-2021, Google LLC * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Google LLC nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Google LLC BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef UPB_UTIL_REQUIRED_FIELDS_H_ #define UPB_UTIL_REQUIRED_FIELDS_H_ #include "upb/def.h" #include "upb/reflection.h" /* Must be last. */ #include "upb/port_def.inc" #ifdef __cplusplus extern "C" { #endif // A FieldPath can be encoded as an array of upb_FieldPathEntry, in the // following format: // { {.field = f1}, {.field = f2} } # f1.f2 // { {.field = f1}, {.index = 5}, {.field = f2} } # f1[5].f2 // { {.field = f1}, {.key = "abc"}, {.field = f2} } # f1["abc"].f2 // // Users must look at the type of `field` to know if an index or map key // follows. // // A field path may be NULL-terminated, in which case a NULL field indicates // the end of the field path. typedef union { const upb_FieldDef* field; size_t array_index; upb_MessageValue map_key; } upb_FieldPathEntry; // Writes a string representing `*path` to `buf` in the following textual // format: // foo.bar # Regular fields // repeated_baz[2].bar # Repeated field // int32_msg_map[5].bar # Integer-keyed map // string_msg_map["abc"] # String-keyed map // bool_msg_map[true] # Bool-keyed map // // The input array `*path` must be NULL-terminated. The pointer `*path` will be // updated to point to one past the terminating NULL pointer of the input array. // // The output buffer `buf` will always be NULL-terminated. If the output data // (including NULL terminator) exceeds `size`, the result will be truncated. // Returns the string length of the data we attempted to write, excluding the // terminating NULL. size_t upb_FieldPath_ToText(upb_FieldPathEntry** path, char* buf, size_t size); // Checks whether `msg` or any of its children has unset required fields, // returning `true` if any are found. `msg` may be NULL, in which case the // message will be treated as empty. // // When this function returns true, `fields` is updated (if non-NULL) to point // to a heap-allocated array encoding the field paths of the required fields // that are missing. Each path is terminated with {.field = NULL}, and a final // {.field = NULL} terminates the list of paths. The caller is responsible for // freeing this array. bool upb_util_HasUnsetRequired(const upb_Message* msg, const upb_MessageDef* m, const upb_DefPool* ext_pool, upb_FieldPathEntry** fields); #ifdef __cplusplus } /* extern "C" */ #endif #include "upb/port_undef.inc" #endif /* UPB_UTIL_REQUIRED_FIELDS_H_ */

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gstgvainference.h

/******************************************************************************* * Copyright (C) 2018-2021 Intel Corporation * * SPDX-License-Identifier: MIT ******************************************************************************/ #ifndef _GST_GVA_INFERENCE_H_ #define _GST_GVA_INFERENCE_H_ #include <gst/base/gstbasetransform.h> #include "gva_base_inference.h" G_BEGIN_DECLS #define GST_TYPE_GVA_INFERENCE (gst_gva_inference_get_type()) #define GST_GVA_INFERENCE(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), GST_TYPE_GVA_INFERENCE, GstGvaInference)) #define GST_GVA_INFERENCE_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), GST_TYPE_GVA_INFERENCE, GstGvaInferenceClass)) #define GST_IS_GVA_INFERENCE(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), GST_TYPE_GVA_INFERENCE)) #define GST_IS_GVA_INFERENCE_CLASS(obj) (G_TYPE_CHECK_CLASS_TYPE((klass), GST_TYPE_GVA_INFERENCE)) typedef struct _GstGvaInference { GvaBaseInference base_inference; } GstGvaInference; typedef struct _GstGvaInferenceClass { GvaBaseInferenceClass base_class; } GstGvaInferenceClass; GType gst_gva_inference_get_type(void); G_END_DECLS #endif

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/rtos/pmsis/bsp/include/bsp/bootloader_utility.h

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/* * Copyright (C) 2020 GreenWaves Technologies * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /* * Created by Mathieu Barbe <mathieu.barbe@greenwaves-technologies.com>. * on 1/6/2020. */ #ifndef SSBL_BOOTLOADER_UTILITY_H #define SSBL_BOOTLOADER_UTILITY_H #include "stdbool.h" #include "stdint.h" #include "pmsis.h" #include "bsp/flash_partition.h" #include "bsp/partition.h" #define MAX_NB_SEGMENT 16 #define L2_BUFFER_SIZE 4096 typedef struct { uint32_t start; uint32_t ptr; uint32_t size; } bin_segment_t; typedef struct { uint32_t nb_segments; uint32_t entry; } bin_header_t; #define APP_BIN_MAGIC_CODE "GApp" typedef struct { char magic_code[4]; uint8_t md5[16]; bin_header_t header; bin_segment_t segments[MAX_NB_SEGMENT]; } bin_desc_t; typedef struct { flash_partition_pos_t ota_info; flash_partition_pos_t factory; flash_partition_pos_t test; flash_partition_pos_t ota[2]; flash_partition_pos_t updater[2]; uint32_t app_count; uint32_t selected_subtype; } bootloader_state_t; bool bootloader_utility_binary_is_valid(pi_device_t *flash, uint32_t flash_offset); pi_err_t bootloader_utility_fill_state(const flash_partition_table_t *table, bootloader_state_t *bs); pi_err_t bootloader_utility_boot_from_partition(pi_device_t *flash, const uint32_t partition_offset); pi_partition_subtype_t bootloader_utility_get_boot_partition(const flash_partition_table_t *table, const bootloader_state_t *bs); static inline void __attribute__((noreturn)) jump_to_address(unsigned int address) { void (*entry)() = (void (*)())(address); entry(); while (1); } #endif //SSBL_BOOTLOADER_UTILITY_H

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halide_runtime.c

// Copyright 2021 ETH Zurich and University of Bologna. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // Author: Samuel Riedel, ETH Zurich #include "halide_runtime.h" #include "printf.h" #include "runtime.h" #include "synchronization.h" #include <stdbool.h> #include <stdint.h> #include <stdio.h> #include <string.h> #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" void *halide_malloc(void *user_context, size_t x) { return (void *)0x0000b000; } void halide_free(void *user_context, void *ptr) {} char *getenv(const char *name) { return NULL; }; void halide_error(void *user_context, const char *msg) { halide_print(user_context, msg); } size_t write(int fd, const void *buf, size_t count) { const char *msg = buf; printf("Write is not implemented! fd: %d\n", fd); for (unsigned i = 0; i < count; ++i) { printf("%c", msg[count]); } printf("\n"); return 1; } FILE *fopen(const char *pathname, const char *mode) { printf("fopen not implemented!\n"); return (FILE *)NULL; } size_t fwrite(const void *ptr, size_t size, size_t count, FILE *stream) { printf("fwrite not implemented!\n"); return 0; } int fclose(FILE *stream) { printf("fclose not implemented!\n"); return -1; } int fileno(FILE *stream) { printf("fileno not implemented!\n"); return -1; } int atoi(const char *str) { printf("atoi not implemented!\n"); return 0; } void halide_print(void *user_context, const char *msg) { printf("%s\n", msg); } ////////////// // Parallel // ////////////// // Halide calls this function int halide_do_par_for(void *user_context, halide_task_t task, int min, int size, uint8_t *closure) { for (uint32_t core_id = mempool_get_core_id(); core_id < (uint32_t)size; core_id += mempool_get_core_count()) { task(user_context, (int32_t)core_id, closure); } return 0; } #pragma GCC diagnostic pop

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repack.c

#include <u.h> #include <libc.h> #include "git.h" #define TMPPATH(suff) (".git/objects/pack/repack."suff) int cleanup(Hash h) { char newpfx[42], dpath[256], fpath[256]; int i, j, nd; Dir *d; snprint(newpfx, sizeof(newpfx), "%H.", h); for(i = 0; i < 256; i++){ snprint(dpath, sizeof(dpath), ".git/objects/%02x", i); if((nd = slurpdir(dpath, &d)) == -1) continue; for(j = 0; j < nd; j++){ snprint(fpath, sizeof(fpath), ".git/objects/%02x/%s", i, d[j].name); remove(fpath); } remove(dpath); free(d); } snprint(dpath, sizeof(dpath), ".git/objects/pack"); if((nd = slurpdir(dpath, &d)) == -1) return -1; for(i = 0; i < nd; i++){ if(strncmp(d[i].name, newpfx, strlen(newpfx)) == 0) continue; snprint(fpath, sizeof(fpath), ".git/objects/pack/%s", d[i].name); remove(fpath); } return 0; } void usage(void) { fprint(2, "usage: %s [-d]\n", argv0); exits("usage"); } void main(int argc, char **argv) { char path[128], **names; int fd, nrefs; Hash *refs, h; Dir rn; ARGBEGIN{ case 'd': chattygit++; break; default: usage(); }ARGEND; gitinit(); refs = nil; if((nrefs = listrefs(&refs, &names)) == -1) sysfatal("load refs: %r"); if((fd = create(TMPPATH("pack.tmp"), OWRITE, 0644)) == -1) sysfatal("open %s: %r", TMPPATH("pack.tmp")); if(writepack(fd, refs, nrefs, nil, 0, &h) == -1) sysfatal("writepack: %r"); if(indexpack(TMPPATH("pack.tmp"), TMPPATH("idx.tmp"), h) == -1) sysfatal("indexpack: %r"); close(fd); nulldir(&rn); rn.name = path; snprint(path, sizeof(path), "%H.pack", h); if(dirwstat(TMPPATH("pack.tmp"), &rn) == -1) sysfatal("rename pack: %r"); snprint(path, sizeof(path), "%H.idx", h); if(dirwstat(TMPPATH("idx.tmp"), &rn) == -1) sysfatal("rename pack: %r"); if(cleanup(h) == -1) sysfatal("cleanup: %r"); exits(nil); }

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NetBSD/src

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iconv.c

/* $NetBSD: iconv.c,v 1.14 2019/10/24 18:17:59 kamil Exp $ */ /*- * Copyright (c)2003 Citrus Project, * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include <sys/cdefs.h> #if defined(LIBC_SCCS) && !defined(lint) __RCSID("$NetBSD: iconv.c,v 1.14 2019/10/24 18:17:59 kamil Exp $"); #endif /* LIBC_SCCS and not lint */ #include "namespace.h" #include <assert.h> #include <errno.h> #include <paths.h> #include <sys/queue.h> #include <iconv.h> #ifdef __weak_alias __weak_alias(iconv, _iconv) __weak_alias(iconv_open, _iconv_open) __weak_alias(iconv_close, _iconv_close) #endif #include <sys/types.h> #include "citrus_types.h" #include "citrus_module.h" #include "citrus_esdb.h" #include "citrus_hash.h" #include "citrus_iconv.h" #define ISBADF(_h_) (!(_h_) || (_h_) == (iconv_t)-1) iconv_t iconv_open(const char *out, const char *in) { int ret; struct _citrus_iconv *handle; ret = _citrus_iconv_open(&handle, _PATH_ICONV, in, out); if (ret) { errno = ret == ENOENT? EINVAL : ret; return ((iconv_t)-1); } return ((iconv_t)(void *)handle); } int iconv_close(iconv_t handle) { if (ISBADF(handle)) { errno = EBADF; return (-1); } _citrus_iconv_close((struct _citrus_iconv *)(void *)handle); return (0); } size_t iconv(iconv_t handle, char **in, size_t *szin, char **out, size_t *szout) { int err; size_t ret; if (ISBADF(handle)) { errno = EBADF; return ((size_t)-1); } err = _citrus_iconv_convert( (struct _citrus_iconv *)(void *)handle, (const char **)(void *)in, szin, out, szout, 0, &ret); if (err) { errno = err; ret = (size_t)-1; } return (ret); } size_t __iconv(iconv_t handle, char **in, size_t *szin, char **out, size_t *szout, u_int32_t flags, size_t *invalids) { int err; size_t ret; if (ISBADF(handle)) { errno = EBADF; return ((size_t)-1); } err = _citrus_iconv_convert( (struct _citrus_iconv *)(void *)handle, (const char **)(void *)in, szin, out, szout, flags, &ret); if (invalids) *invalids = ret; if (err) { errno = err; ret = (size_t)-1; } return (ret); } int __iconv_get_list(char ***rlist, size_t *rsz) { int ret; ret = _citrus_esdb_get_list(rlist, rsz); if (ret) { errno = ret; return -1; } return 0; } void __iconv_free_list(char **list, size_t sz) { _citrus_esdb_free_list(list, sz); }

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course_data.inc.c

// todo: Replace addresses with variables #include <ultra64.h> #include <macros.h> #include <PR/gbi.h> #include <actor_types.h> #include <waypoints.h> #include <course.h> #include <courses/star_cup/bowsers_castle/packed.inc.h> Gfx d_course_bowsers_castle_dl_0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_110[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_230[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_398[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_428[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4F0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_640[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_7A0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_860[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_8E8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_9F8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_AE0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_B88[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5A78), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_C08[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_D20[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5A78), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_E00[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_EA8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_F08[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1040[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1138[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5A78), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_11F0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5BC8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1248[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1290[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5BC8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_12D0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5BC8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1330[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_5850), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1350[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1370[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6580), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5850), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_338), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_13A0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_3578), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5BC8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_13C0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6580), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_13E0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5850), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1448[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5850), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1488[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6580), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5850), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3930), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_14B0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1520[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1590[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1608[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_63D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1690[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_63D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_17E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1700), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1618), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1530), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_18D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1710[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_64A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1788[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_D38), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1360), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1D58), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_17D0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_64A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1818[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1860[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_18C0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_64A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_48A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4BB0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4EB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_41A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1928[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1960[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_19A8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_19F8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1A40[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPSetGeometryMode(G_CULL_BACK), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1A90[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1AD8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1B10[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6200), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1B58[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6BC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_66E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1BB0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6BC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_66E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_B80), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1B88), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPDisplayList(d_course_bowsers_castle_packed_dl_280), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1C10[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6BC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_66E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1C38[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_19B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1C60[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_6BC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_66E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1AA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2A48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1C98[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3308), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1EA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1CD0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3308), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1EA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1DF8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3308), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1EA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1EB0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3308), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1EA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_470), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_1FA0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2008[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2130[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_21F0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_22E8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2398[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_24B8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2578[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2688[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2760[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2880[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2958[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_82D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2A60[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2B80[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2C48[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2D08[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2DF8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2F30[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_2FB0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3050[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3158[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3230[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_32C0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3338[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3480[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3508[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_35D0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3678[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7CC0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8348), gsSPDisplayList(d_course_bowsers_castle_packed_dl_80E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_37D8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_38F8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_39E0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3B00[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_54E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5778), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_70D0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3C08[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3D78[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3EA8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_28B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5300), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6E48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7998), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7DB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_3FF0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7730), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_40F0[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4278[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4358[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6F08), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7E28), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4488[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5678), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_45D8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4748[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4820[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2770), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4998[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2128), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7908), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4A98[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_23E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2450), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2310), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2858), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8218), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4C00[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4CE8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9328), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9438), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6A90), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_87E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8BE0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8C78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_24B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_20B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2188), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2228), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2598), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2698), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5270), gsSPDisplayList(d_course_bowsers_castle_packed_dl_56F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6D78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6CB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7520), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7418), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7340), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7B50), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7BB8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7C30), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7650), gsSPDisplayList(d_course_bowsers_castle_packed_dl_76C0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_77A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7820), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7898), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_81B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7EA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F20), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8078), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_4EA8[] = { gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9290), gsSPDisplayList(d_course_bowsers_castle_packed_dl_93A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_30C8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94D8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_84A8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8D10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8DA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2378), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2528), gsSPDisplayList(d_course_bowsers_castle_packed_dl_27E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2610), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2708), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5448), gsSPDisplayList(d_course_bowsers_castle_packed_dl_53E0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_55E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_5560), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7038), gsSPDisplayList(d_course_bowsers_castle_packed_dl_6FA0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7288), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7180), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A10), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7A78), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7AD8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7D48), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8148), gsSPDisplayList(d_course_bowsers_castle_packed_dl_7F98), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8008), gsSPEndDisplayList(), }; // 0x4F90 struct TrackWayPoint d_course_bowsers_castle_unknown_waypoints[] = { {2, 0, -172, 0}, {2, 0, -197, 0}, {-2, 0, -691, 0}, {-1, 0, -1087, 0}, {4, 0, -1519, 0}, {88, 0, -1645, 0}, {228, 0, -1743, 0}, {571, 0, -1749, 0}, {999, 0, -1749, 0}, {1201, 0, -1747, 0}, {1262, 0, -1759, 0}, {1274, 0, -1797, 0}, {1277, 0, -2193, 0}, {1272, 0, -2487, 0}, {1281, 0, -2631, 0}, {1351, 0, -2653, 0}, {1752, 0, -2642, 0}, {2350, 0, -2640, 0}, {2470, 0, -2621, 0}, {2490, 0, -2580, 0}, {2491, 0, -2372, 0}, {2491, 0, -1970, 0}, {2491, 0, -1759, 0}, {2471, 0, -1705, 0}, {2407, 0, -1681, 0}, {2115, 0, -1680, 0}, {1814, 0, -1681, 0}, {1752, 0, -1678, 0}, {1718, 0, -1661, 0}, {1704, 0, -1599, 0}, {1705, 0, -1403, 0}, {1704, 0, -1250, 0}, {1704, 0, -1099, 0}, {1706, 0, -904, 0}, {1701, 0, -850, 0}, {1679, 0, -811, 0}, {1480, 0, -799, 0}, {1133, 0, -802, 0}, {945, 0, -752, 0}, {907, 0, -637, 0}, {957, 0, -493, 0}, {1080, 0, -445, 0}, {1481, 0, -445, 0}, {1871, 0, -437, 0}, {1914, 0, -391, 0}, {1920, 0, -351, 0}, {1925, 0, -102, 0}, {1919, 0, 203, 0}, {1919, 0, 557, 0}, {1919, 0, 644, 0}, {1962, 0, 716, 0}, {2028, 0, 761, 0}, {2112, 0, 757, 0}, {2184, 0, 720, 0}, {2227, 0, 649, 0}, {2227, 0, 567, 0}, {2191, 0, 490, 0}, {2117, 0, 449, 0}, {2020, 0, 454, 0}, {1828, 0, 456, 0}, {1351, 0, 456, 0}, {949, 0, 447, 0}, {749, 0, 486, 0}, {525, 0, 554, 0}, {353, 0, 556, 0}, {159, 0, 555, 0}, {23, 0, 488, 0}, {-18, 0, 377, 0}, {-6, 0, 209, 0}, {4, 0, -95, 0}, {3, 0, -144, 0}, {-32768, 0, 0, 0}, }; struct TrackWayPoint d_course_bowsers_castle_track_waypoints[] = { {2, 0, -184, 1}, {1, 0, -204, 2}, {1, 0, -224, 2}, {1, 0, -244, 2}, {1, 0, -264, 2}, {1, 0, -284, 2}, {1, 0, -304, 2}, {0, 0, -324, 2}, {0, 0, -344, 2}, {0, 0, -364, 2}, {0, 0, -384, 2}, {0, 0, -404, 2}, {0, 0, -424, 2}, {0, 0, -444, 2}, {0, 0, -464, 2}, {0, 0, -484, 2}, {0, 0, -504, 2}, {0, 0, -524, 2}, {0, 0, -544, 2}, {0, 0, -564, 2}, {0, 0, -584, 2}, {-1, 0, -604, 3}, {-1, 0, -624, 3}, {-1, 0, -644, 3}, {-1, 0, -664, 3}, {-1, 0, -684, 3}, {-1, 0, -704, 3}, {-1, 0, -724, 3}, {-1, 0, -744, 3}, {-1, 0, -764, 3}, {-1, 0, -784, 3}, {-1, 0, -804, 4}, {-1, 0, -824, 4}, {-1, 0, -844, 4}, {-1, 0, -864, 4}, {-1, 0, -884, 4}, {-1, 0, -904, 4}, {-1, 0, -924, 4}, {-1, 0, -944, 4}, {-1, 0, -964, 4}, {-1, 0, -985, 4}, {-1, 0, -1005, 5}, {0, 0, -1025, 5}, {0, 0, -1045, 5}, {0, 0, -1065, 5}, {0, 0, -1085, 5}, {0, 0, -1105, 5}, {0, 0, -1125, 5}, {0, 0, -1145, 5}, {0, 0, -1165, 5}, {0, 0, -1185, 5}, {0, 0, -1205, 5}, {0, 0, -1225, 5}, {0, 0, -1245, 5}, {1, 0, -1265, 5}, {1, 0, -1285, 5}, {1, 0, -1305, 5}, {1, 0, -1325, 5}, {2, 0, -1345, 5}, {3, 0, -1365, 5}, {4, 0, -1385, 5}, {5, 0, -1405, 5}, {7, 0, -1425, 5}, {9, 0, -1445, 5}, {11, 0, -1464, 5}, {14, 0, -1484, 5}, {18, 0, -1504, 5}, {22, 0, -1523, 5}, {28, 0, -1543, 5}, {35, 0, -1561, 5}, {44, 0, -1579, 5}, {55, 0, -1596, 5}, {68, 0, -1611, 5}, {81, 0, -1626, 5}, {94, 0, -1641, 5}, {109, 0, -1655, 5}, {124, 0, -1668, 5}, {140, 0, -1680, 5}, {156, 0, -1692, 5}, {173, 0, -1703, 5}, {191, 0, -1712, 5}, {209, 0, -1719, 5}, {228, 0, -1725, 5}, {248, 0, -1730, 5}, {267, 0, -1734, 5}, {287, 0, -1737, 5}, {307, 0, -1740, 5}, {327, 0, -1742, 5}, {347, 0, -1743, 5}, {367, 0, -1744, 5}, {387, 0, -1745, 5}, {407, 0, -1746, 5}, {427, 0, -1746, 5}, {447, 0, -1746, 5}, {467, 0, -1747, 5}, {487, 0, -1747, 5}, {507, 0, -1747, 5}, {527, 0, -1747, 5}, {547, 0, -1747, 5}, {567, 0, -1748, 5}, {587, 0, -1748, 5}, {607, 0, -1748, 6}, {627, 0, -1748, 6}, {647, 0, -1748, 6}, {667, 0, -1748, 6}, {687, 0, -1748, 6}, {707, 0, -1748, 6}, {727, 0, -1748, 6}, {747, 0, -1748, 6}, {767, 0, -1748, 6}, {787, 0, -1749, 6}, {807, 0, -1748, 6}, {827, 0, -1748, 6}, {847, 0, -1748, 6}, {867, 0, -1748, 6}, {887, 0, -1748, 6}, {907, 0, -1748, 6}, {927, 0, -1748, 6}, {947, 0, -1748, 6}, {967, 0, -1748, 6}, {987, 0, -1748, 6}, {1007, 0, -1748, 6}, {1027, 0, -1748, 6}, {1047, 0, -1748, 6}, {1067, 0, -1748, 6}, {1087, 0, -1748, 6}, {1107, 0, -1747, 6}, {1127, 0, -1747, 6}, {1147, 0, -1747, 6}, {1167, 0, -1748, 6}, {1187, 0, -1748, 6}, {1207, 0, -1750, 6}, {1227, 0, -1752, 6}, {1246, 0, -1757, 6}, {1263, 0, -1768, 6}, {1269, 0, -1787, 6}, {1271, 0, -1807, 6}, {1272, 0, -1827, 6}, {1273, 0, -1847, 6}, {1273, 0, -1867, 6}, {1274, 0, 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70, -1723, 9}, {2464, 70, -1708, 9}, {2448, 70, -1696, 9}, {2429, 70, -1690, 9}, {2409, 70, -1686, 10}, {2389, 70, -1684, 10}, {2369, 70, -1683, 10}, {2349, 70, -1682, 10}, {2329, 70, -1681, 10}, {2309, 70, -1681, 10}, {2289, 70, -1680, 10}, {2269, 70, -1680, 10}, {2249, 70, -1680, 10}, {2229, 70, -1680, 10}, {2209, 70, -1680, 10}, {2189, 70, -1680, 10}, {2169, 70, -1680, 10}, {2149, 70, -1680, 10}, {2129, 70, -1680, 10}, {2109, 70, -1680, 10}, {2089, 70, -1680, 10}, {2069, 70, -1680, 10}, {2049, 70, -1680, 10}, {2029, 70, -1680, 10}, {2009, 70, -1680, 10}, {1989, 70, -1680, 10}, {1969, 70, -1680, 10}, {1949, 70, -1680, 10}, {1929, 70, -1680, 10}, {1909, 70, -1680, 10}, {1889, 70, -1680, 10}, {1869, 70, -1680, 10}, {1849, 70, -1680, 10}, {1829, 70, -1680, 10}, {1809, 70, -1680, 10}, {1789, 70, -1679, 10}, {1769, 70, -1678, 10}, {1749, 70, -1674, 11}, {1731, 70, -1667, 11}, {1718, 70, -1652, 11}, {1711, 70, -1633, 11}, {1708, 70, -1613, 11}, {1706, 70, -1593, 11}, {1705, 70, -1573, 11}, {1704, 70, -1553, 11}, {1704, 70, -1533, 11}, {1704, 70, -1513, 11}, {1704, 70, -1493, 11}, {1704, 70, -1473, 11}, {1704, 70, -1453, 11}, {1704, 70, -1433, 11}, {1704, 70, -1413, 11}, {1704, 68, -1393, 12}, {1704, 66, -1373, 12}, {1704, 64, -1353, 12}, {1704, 62, -1333, 12}, {1704, 61, -1313, 12}, {1704, 61, -1293, 12}, {1704, 60, -1273, 12}, {1704, 60, -1253, 12}, {1704, 60, -1233, 12}, {1704, 61, -1213, 12}, {1704, 61, -1193, 12}, {1704, 62, -1173, 12}, {1704, 63, -1153, 12}, {1704, 65, -1133, 12}, {1704, 68, -1113, 12}, {1704, 70, -1093, 13}, {1704, 70, -1073, 13}, {1704, 70, -1053, 13}, {1704, 70, -1033, 13}, {1704, 70, -1013, 13}, {1705, 70, -993, 13}, {1705, 70, -973, 13}, {1705, 70, -953, 13}, {1705, 70, -933, 13}, {1705, 70, -913, 13}, {1704, 70, -893, 14}, {1703, 70, -873, 14}, {1699, 70, -853, 14}, {1692, 70, -835, 14}, {1678, 70, -821, 14}, {1659, 70, -815, 14}, {1640, 70, -811, 14}, {1620, 60, -808, 14}, {1600, 60, -806, 14}, {1580, 60, -805, 14}, {1560, 50, -803, 14}, {1540, 50, -803, 14}, {1520, 40, -802, 14}, {1500, 40, -801, 14}, {1480, 40, -801, 14}, {1460, 30, -800, 14}, {1440, 30, -800, 14}, {1420, 20, -800, 14}, {1400, 20, -800, 14}, {1380, 20, -800, 14}, {1360, 10, -800, 14}, {1340, 10, -800, 14}, {1320, 0, -800, 14}, {1300, 0, -800, 14}, {1280, 0, -800, 14}, {1260, 0, -800, 14}, {1240, 0, -800, 14}, {1220, 0, -799, 14}, {1200, 0, -798, 14}, {1180, 0, -797, 14}, {1160, 0, -796, 14}, {1140, 0, -794, 14}, {1120, 0, -791, 14}, {1100, 0, -789, 14}, {1080, 0, -786, 14}, {1061, 0, -782, 15}, {1041, 0, -777, 15}, {1022, 0, -772, 15}, {1003, 0, -765, 15}, {985, 0, -757, 15}, {968, 0, -747, 15}, {952, 0, -734, 15}, {939, 0, -719, 15}, {929, 0, -702, 15}, {922, 0, -683, 15}, {919, 0, -663, 15}, {917, 0, -643, 15}, {918, 0, -624, 15}, {921, 0, -604, 15}, {925, 0, -584, 15}, {931, 0, -565, 15}, {939, 0, -546, 15}, {948, 0, -529, 15}, {959, 0, -512, 15}, {973, 0, -497, 15}, {988, 0, -485, 15}, {1005, 0, -474, 15}, {1023, 0, -467, 15}, {1043, 0, -461, 15}, {1062, 0, -457, 15}, {1082, 0, -454, 15}, {1102, 0, -452, 15}, {1122, 0, -450, 15}, {1142, 0, -448, 15}, {1162, 0, -447, 15}, {1182, 0, -446, 15}, {1202, 0, -446, 15}, {1222, 0, -445, 15}, {1242, 0, -445, 15}, {1262, 0, -445, 15}, {1282, 0, -444, 15}, {1302, 0, -444, 15}, {1322, 0, -444, 15}, {1342, 0, -444, 15}, {1362, 0, -444, 15}, {1382, 0, -444, 15}, {1402, 0, -444, 15}, {1422, 0, -444, 15}, {1442, 0, -444, 15}, {1462, 0, -444, 15}, {1482, 0, -443, 15}, {1502, 0, -443, 15}, {1522, 0, -443, 15}, {1542, 0, -443, 15}, {1562, 0, -442, 15}, {1582, 0, -442, 15}, {1602, 0, -442, 15}, {1622, 0, -442, 15}, {1642, 0, -441, 15}, {1662, 0, -441, 15}, {1682, 0, -440, 15}, {1702, 0, -440, 15}, {1722, 0, -439, 15}, {1742, 0, -438, 15}, {1762, 0, -437, 15}, {1782, 0, -436, 15}, {1802, 0, -434, 15}, {1822, 0, -432, 15}, {1842, 0, -430, 15}, {1861, 0, -426, 15}, {1881, 0, -420, 15}, {1896, 0, -409, 15}, {1908, 0, -392, 15}, {1916, 0, -374, 15}, {1918, 0, -354, 15}, {1919, 0, -334, 15}, {1920, 0, -314, 15}, {1920, 0, -294, 15}, {1921, 0, -274, 15}, {1921, 0, -254, 15}, {1922, 0, -234, 15}, {1922, 0, -214, 16}, {1923, 0, -194, 16}, {1923, 0, -174, 16}, {1923, 0, -154, 16}, {1923, 0, -134, 16}, {1923, 0, -114, 16}, {1923, 0, -94, 16}, {1923, 0, -74, 16}, {1923, 0, -54, 17}, {1923, 0, -34, 17}, {1923, 0, -14, 17}, {1922, 0, 5, 17}, {1922, 0, 25, 17}, {1922, 0, 45, 17}, {1921, 0, 65, 17}, {1921, 0, 85, 17}, {1921, 0, 105, 18}, {1920, 0, 125, 18}, {1920, 0, 145, 18}, {1920, 0, 165, 18}, {1919, 0, 185, 18}, {1919, 0, 205, 18}, {1919, 0, 225, 18}, {1919, 0, 245, 18}, {1919, 0, 265, 18}, {1919, 0, 285, 18}, {1919, 0, 305, 18}, {1919, 0, 325, 18}, {1919, 0, 345, 18}, {1919, 0, 365, 18}, {1919, 0, 385, 18}, {1919, 0, 405, 19}, {1918, 1, 425, 19}, {1918, 2, 445, 19}, {1919, 3, 465, 19}, {1919, 4, 485, 19}, {1918, 5, 505, 19}, {1919, 7, 525, 19}, {1919, 8, 545, 19}, {1919, 10, 565, 19}, {1919, 11, 585, 19}, {1919, 13, 605, 19}, {1920, 15, 625, 19}, {1925, 17, 645, 19}, {1932, 20, 664, 19}, {1941, 22, 681, 20}, {1952, 24, 698, 20}, {1965, 26, 713, 20}, {1980, 28, 727, 20}, {1996, 30, 739, 20}, {2013, 32, 748, 20}, {2032, 34, 755, 20}, {2052, 36, 758, 20}, {2072, 37, 758, 20}, {2092, 40, 756, 20}, {2111, 41, 752, 20}, {2130, 44, 746, 20}, {2148, 45, 738, 20}, {2165, 48, 727, 20}, {2181, 49, 714, 21}, {2194, 51, 699, 21}, {2206, 53, 683, 21}, {2215, 55, 665, 21}, {2221, 57, 646, 21}, {2225, 60, 627, 21}, {2226, 61, 607, 21}, {2225, 63, 587, 21}, {2222, 64, 567, 21}, {2217, 67, 548, 21}, {2209, 69, 529, 21}, {2200, 71, 512, 21}, {2187, 72, 496, 21}, {2173, 74, 482, 22}, {2156, 75, 471, 22}, {2138, 78, 462, 22}, {2119, 79, 456, 22}, {2100, 81, 452, 22}, {2080, 82, 451, 22}, {2060, 83, 451, 22}, {2040, 85, 452, 22}, {2020, 86, 453, 22}, {2000, 87, 453, 22}, {1980, 89, 454, 22}, {1960, 90, 454, 23}, {1940, 91, 454, 23}, {1920, 93, 455, 23}, {1900, 93, 455, 23}, {1880, 94, 455, 23}, {1860, 95, 455, 23}, {1840, 96, 455, 23}, {1820, 97, 455, 23}, {1800, 97, 455, 23}, {1780, 98, 455, 23}, {1760, 98, 455, 23}, {1740, 98, 455, 23}, {1720, 98, 455, 23}, {1700, 98, 455, 23}, {1680, 98, 455, 23}, {1660, 98, 455, 23}, {1640, 98, 455, 23}, {1620, 98, 455, 23}, {1600, 98, 455, 23}, {1580, 98, 455, 23}, {1560, 98, 455, 23}, {1540, 88, 455, 24}, {1520, 78, 455, 24}, {1500, 68, 455, 24}, {1479, 58, 455, 24}, {1459, 48, 455, 24}, {1439, 38, 455, 24}, {1419, 33, 455, 24}, {1399, 29, 455, 24}, {1379, 25, 455, 24}, {1359, 21, 454, 24}, {1339, 18, 454, 24}, {1319, 16, 454, 24}, {1299, 14, 454, 24}, {1279, 12, 453, 24}, {1259, 10, 453, 24}, {1239, 9, 453, 24}, {1219, 8, 452, 24}, {1199, 7, 452, 24}, {1179, 6, 452, 24}, {1159, 5, 451, 24}, {1139, 4, 451, 24}, {1119, 3, 450, 24}, {1099, 2, 450, 24}, {1079, 1, 450, 24}, {1059, 0, 450, 24}, {1039, 0, 450, 25}, {1019, 0, 451, 25}, {999, 0, 451, 25}, {979, 0, 452, 25}, {959, 0, 453, 25}, {939, 0, 455, 25}, {919, 1, 456, 25}, {899, 2, 458, 25}, {880, 3, 461, 25}, {860, 4, 464, 25}, {840, 5, 468, 25}, {821, 7, 472, 25}, {801, 9, 476, 25}, {781, 11, 480, 25}, {762, 13, 485, 25}, {743, 15, 490, 25}, {723, 17, 495, 25}, {704, 19, 500, 25}, {685, 21, 505, 25}, {665, 23, 511, 25}, {646, 23, 517, 25}, {627, 23, 522, 25}, {608, 23, 528, 25}, {588, 23, 533, 25}, {569, 13, 538, 26}, {549, 3, 542, 26}, {530, 0, 545, 26}, {510, 0, 549, 26}, {490, 0, 551, 26}, {470, 0, 553, 26}, {450, 0, 554, 26}, {430, 0, 555, 26}, {410, 0, 555, 26}, {390, 0, 555, 26}, {370, 0, 555, 26}, {350, 0, 555, 26}, {330, 0, 555, 26}, {310, 0, 555, 26}, {290, 0, 555, 26}, {270, 0, 555, 26}, {250, 0, 555, 26}, {230, 0, 554, 27}, {210, 0, 553, 27}, {190, 0, 550, 27}, {171, 0, 547, 27}, {151, 0, 543, 27}, {132, 0, 537, 27}, {113, 0, 531, 27}, {94, 0, 523, 27}, {77, 0, 514, 27}, {60, 0, 503, 27}, {44, 0, 491, 27}, {30, 0, 477, 27}, {17, 0, 461, 27}, {7, 0, 444, 27}, {0, 0, 425, 27}, {-5, 0, 406, 27}, {-9, 0, 387, 27}, {-11, 0, 367, 27}, {-12, 0, 347, 27}, {-13, 0, 327, 27}, {-12, 0, 307, 27}, {-11, 0, 287, 27}, {-10, 0, 267, 27}, {-9, 0, 247, 27}, {-8, 0, 227, 27}, {-6, 0, 207, 27}, {-6, 0, 187, 1}, {-5, 0, 167, 1}, {-4, 0, 147, 1}, {-3, 0, 127, 1}, {-2, 0, 107, 1}, {-2, 0, 87, 1}, {-1, 0, 67, 1}, {0, 0, 47, 1}, {0, 0, 27, 1}, {0, 0, 7, 1}, {1, 0, -12, 1}, {1, 0, -32, 1}, {2, 0, -52, 1}, {2, 0, -72, 1}, {2, 0, -92, 1}, {3, 0, -112, 1}, {3, 0, -132, 1}, {2, 0, -152, 1}, {2, 0, -172, 1}, {-32768, -32768, -32768, 0}, }; // 82DF40_06738 u8 d_course_bowsers_castle_thwomp_side[] = { #include "assets/courses/bowsers_castle/gTextureThwompSide.inc.c" }; // 0x6F38 u8 d_course_bowsers_castle_thwomp_tlut[] = { #include "assets/courses/bowsers_castle/gTLUTThwomp.inc.c" }; // 0x7138 u8 d_course_bowsers_castle_thwomp_faces[][1024] = { { #include "assets/courses/bowsers_castle/gTextureThwompFace1.inc.c" }, { #include "assets/courses/bowsers_castle/gTextureThwompFace2.inc.c" }, { #include "assets/courses/bowsers_castle/gTextureThwompFace3.inc.c" }, { #include "assets/courses/bowsers_castle/gTextureThwompFace4.inc.c" }, { #include "assets/courses/bowsers_castle/gTextureThwompFace5.inc.c" }, { #include "assets/courses/bowsers_castle/gTextureThwompFace6.inc.c" }, }; // 0x8938 Vtx d_course_bowsers_castle_thwomp_model1[] = { {{{ -8, 19, 13 }, 0, { 0, 0 }, {0xD5, 0x2C, 0x66, 0xFF }}}, {{{ -8, 5, 13 }, 0, { 0, 2048 }, {0xD5, 0xD3, 0x65, 0xFF }}}, {{{ 8, 5, 13 }, 0, { 1024, 2048 }, {0x2C, 0xD3, 0x65, 0xFF }}}, {{{ 8, 19, 13 }, 0, { 1024, 0 }, {0x2C, 0x2C, 0x66, 0xFF }}}, }; Vtx d_course_bowsers_castle_thwomp_model2[] = { {{{ 13, 5, 8 }, 0, { -320, 1244 }, {0x66, 0xD3, 0x2B, 0xFF }}}, {{{ 8, 5, 13 }, 0, { -30, 1244 }, {0x2C, 0xD3, 0x65, 0xFF }}}, {{{ 8, 0, 8 }, 0, { -175, 1019 }, {0x2A, 0x99, 0x29, 0xFF }}}, {{{ 8, 5, -13 }, 0, { -320, 1244 }, {0x2C, 0xD3, 0x9A, 0xFF }}}, {{{ 13, 5, -8 }, 0, { -30, 1244 }, {0x66, 0xD3, 0xD4, 0xFF }}}, {{{ 8, 0, -8 }, 0, { -175, 1019 }, {0x2A, 0x99, 0xD6, 0xFF }}}, {{{ -13, 5, -8 }, 0, { -320, 1244 }, {0x9B, 0xD3, 0xD4, 0xFF }}}, {{{ -8, 5, -13 }, 0, { -30, 1244 }, {0xD5, 0xD3, 0x9A, 0xFF }}}, {{{ -8, 0, -8 }, 0, { -175, 1019 }, {0xD7, 0x99, 0xD6, 0xFF }}}, {{{ -8, 5, 13 }, 0, { -320, 1244 }, {0xD5, 0xD3, 0x65, 0xFF }}}, {{{ -13, 5, 8 }, 0, { -30, 1244 }, {0x9B, 0xD3, 0x2B, 0xFF }}}, {{{ -8, 0, 8 }, 0, { -175, 1019 }, {0xD7, 0x99, 0x29, 0xFF }}}, {{{ 13, 19, 8 }, 0, { 819, 2877 }, {0x67, 0x2C, 0x2B, 0xFF }}}, {{{ 8, 24, 8 }, 0, { 599, 3043 }, {0x2C, 0x67, 0x2B, 0xFF }}}, {{{ 8, 19, 13 }, 0, { 846, 3165 }, {0x2C, 0x2C, 0x66, 0xFF }}}, {{{ 8, 19, -13 }, 0, { 832, 2010 }, {0x2C, 0x2C, 0x99, 0xFF }}}, {{{ 8, 24, -8 }, 0, { 589, 2142 }, {0x2C, 0x67, 0xD4, 0xFF }}}, {{{ 13, 19, -8 }, 0, { 816, 2299 }, {0x67, 0x2C, 0xD4, 0xFF }}}, {{{ -13, 19, -8 }, 0, { 464, 1239 }, {0x9A, 0x2C, 0xD4, 0xFF }}}, {{{ -8, 24, -8 }, 0, { 408, 1509 }, {0xD5, 0x67, 0xD4, 0xFF }}}, {{{ -8, 19, -13 }, 0, { 675, 1438 }, {0xD5, 0x2C, 0x99, 0xFF }}}, {{{ -8, 19, 13 }, 0, { -362, 1024 }, {0xD5, 0x2C, 0x66, 0xFF }}}, {{{ -8, 24, 8 }, 0, { -191, 1240 }, {0xD5, 0x67, 0x2B, 0xFF }}}, {{{ -13, 19, 8 }, 0, { -74, 991 }, {0x9A, 0x2C, 0x2B, 0xFF }}}, {{{ -8, 24, -8 }, 0, { 315, 1420 }, {0xD5, 0x67, 0xD4, 0xFF }}}, {{{ -13, 19, -8 }, 0, { 491, 1632 }, {0x9A, 0x2C, 0xD4, 0xFF }}}, {{{ -13, 19, 8 }, 0, { 975, 1255 }, {0x9A, 0x2C, 0x2B, 0xFF }}}, {{{ -8, 24, 8 }, 0, { 812, 1032 }, {0xD5, 0x67, 0x2B, 0xFF }}}, {{{ 8, 24, -8 }, 0, { 598, 2012 }, {0x2C, 0x67, 0xD4, 0xFF }}}, {{{ 8, 19, -13 }, 0, { 874, 2015 }, {0x2C, 0x2C, 0x99, 0xFF }}}, {{{ -8, 19, -13 }, 0, { 898, 1401 }, {0xD5, 0x2C, 0x99, 0xFF }}}, {{{ -8, 24, -8 }, 0, { 623, 1383 }, {0xD5, 0x67, 0xD4, 0xFF }}}, }; Vtx d_course_bowsers_castle_thwomp_model3[] = { {{{ 8, 24, 8 }, 0, { 588, 2839 }, {0x2C, 0x67, 0x2B, 0xFF }}}, {{{ 13, 19, 8 }, 0, { 860, 2883 }, {0x67, 0x2C, 0x2B, 0xFF }}}, {{{ 13, 19, -8 }, 0, { 976, 2280 }, {0x67, 0x2C, 0xD4, 0xFF }}}, {{{ 8, 24, -8 }, 0, { 707, 2220 }, {0x2C, 0x67, 0xD4, 0xFF }}}, {{{ -8, 24, 8 }, 0, { -59, 1821 }, {0xD5, 0x67, 0x2B, 0xFF }}}, {{{ -8, 19, 13 }, 0, { 10, 2088 }, {0xD5, 0x2C, 0x66, 0xFF }}}, {{{ 8, 19, 13 }, 0, { 609, 1950 }, {0x2C, 0x2C, 0x66, 0xFF }}}, {{{ 8, 24, 8 }, 0, { 554, 1679 }, {0x2C, 0x67, 0x2B, 0xFF }}}, {{{ -8, 19, 13 }, 0, { 0, 1595 }, {0xD5, 0x2C, 0x66, 0xFF }}}, {{{ -13, 19, 8 }, 0, { 289, 1595 }, {0x9A, 0x2C, 0x2B, 0xFF }}}, {{{ -13, 5, 8 }, 0, { 289, 1024 }, {0x9B, 0xD3, 0x2B, 0xFF }}}, {{{ -8, 5, 13 }, 0, { 0, 1024 }, {0xD5, 0xD3, 0x65, 0xFF }}}, {{{ -13, 19, -8 }, 0, { 0, 1595 }, {0x9A, 0x2C, 0xD4, 0xFF }}}, {{{ -13, 5, -8 }, 0, { 0, 2166 }, {0x9B, 0xD3, 0xD4, 0xFF }}}, {{{ -13, 5, 8 }, 0, { 614, 2166 }, {0x9B, 0xD3, 0x2B, 0xFF }}}, {{{ -13, 19, 8 }, 0, { 614, 1595 }, {0x9A, 0x2C, 0x2B, 0xFF }}}, {{{ -13, 19, -8 }, 0, { -362, 1595 }, {0x9A, 0x2C, 0xD4, 0xFF }}}, {{{ -8, 19, -13 }, 0, { -72, 1595 }, {0xD5, 0x2C, 0x99, 0xFF }}}, {{{ -8, 5, -13 }, 0, { -72, 1024 }, {0xD5, 0xD3, 0x9A, 0xFF }}}, {{{ -13, 5, -8 }, 0, { -362, 1024 }, {0x9B, 0xD3, 0xD4, 0xFF }}}, {{{ 8, 19, -13 }, 0, { 0, 1595 }, {0x2C, 0x2C, 0x99, 0xFF }}}, {{{ 8, 5, -13 }, 0, { 0, 2166 }, {0x2C, 0xD3, 0x9A, 0xFF }}}, {{{ -8, 5, -13 }, 0, { 614, 2166 }, {0xD5, 0xD3, 0x9A, 0xFF }}}, {{{ -8, 19, -13 }, 0, { 614, 1595 }, {0xD5, 0x2C, 0x99, 0xFF }}}, {{{ 8, 19, -13 }, 0, { -362, 1595 }, {0x2C, 0x2C, 0x99, 0xFF }}}, {{{ 13, 19, -8 }, 0, { -72, 1595 }, {0x67, 0x2C, 0xD4, 0xFF }}}, {{{ 13, 5, -8 }, 0, { -72, 1024 }, {0x66, 0xD3, 0xD4, 0xFF }}}, {{{ 8, 5, -13 }, 0, { -362, 1024 }, {0x2C, 0xD3, 0x9A, 0xFF }}}, {{{ 13, 19, 8 }, 0, { 0, 1595 }, {0x67, 0x2C, 0x2B, 0xFF }}}, {{{ 13, 5, 8 }, 0, { 0, 2166 }, {0x66, 0xD3, 0x2B, 0xFF }}}, {{{ 13, 5, -8 }, 0, { 614, 2166 }, {0x66, 0xD3, 0xD4, 0xFF }}}, {{{ 13, 19, -8 }, 0, { 614, 1595 }, {0x67, 0x2C, 0xD4, 0xFF }}}, }; Vtx d_course_bowsers_castle_thwomp_model4[] = { {{{ 13, 19, 8 }, 0, { -149, 1595 }, {0x67, 0x2C, 0x2B, 0xFF }}}, {{{ 8, 19, 13 }, 0, { -439, 1595 }, {0x2C, 0x2C, 0x66, 0xFF }}}, {{{ 8, 5, 13 }, 0, { -439, 2166 }, {0x2C, 0xD3, 0x65, 0xFF }}}, {{{ 13, 5, 8 }, 0, { -149, 2166 }, {0x66, 0xD3, 0x2B, 0xFF }}}, {{{ -13, 5, -8 }, 0, { 59, 1240 }, {0x9B, 0xD3, 0xD4, 0xFF }}}, {{{ -8, 0, -8 }, 0, { -11, 1498 }, {0xD7, 0x99, 0xD6, 0xFF }}}, {{{ -8, 0, 8 }, 0, { 601, 1646 }, {0xD7, 0x99, 0x29, 0xFF }}}, {{{ -13, 5, 8 }, 0, { 656, 1384 }, {0x9B, 0xD3, 0x2B, 0xFF }}}, {{{ 8, 5, -13 }, 0, { 59, 1240 }, {0x2C, 0xD3, 0x9A, 0xFF }}}, {{{ 8, 0, -8 }, 0, { -11, 1498 }, {0x2A, 0x99, 0xD6, 0xFF }}}, {{{ -8, 0, -8 }, 0, { 601, 1646 }, {0xD7, 0x99, 0xD6, 0xFF }}}, {{{ -8, 5, -13 }, 0, { 656, 1384 }, {0xD5, 0xD3, 0x9A, 0xFF }}}, {{{ 13, 5, 8 }, 0, { 59, 1240 }, {0x66, 0xD3, 0x2B, 0xFF }}}, {{{ 8, 0, 8 }, 0, { -11, 1498 }, {0x2A, 0x99, 0x29, 0xFF }}}, {{{ 8, 0, -8 }, 0, { 601, 1646 }, {0x2A, 0x99, 0xD6, 0xFF }}}, {{{ 13, 5, -8 }, 0, { 656, 1384 }, {0x66, 0xD3, 0xD4, 0xFF }}}, {{{ -8, 5, 13 }, 0, { 0, 1023 }, {0xD5, 0xD3, 0x65, 0xFF }}}, {{{ -8, 0, 8 }, 0, { -70, 1282 }, {0xD7, 0x99, 0x29, 0xFF }}}, {{{ 8, 0, 8 }, 0, { 541, 1430 }, {0x2A, 0x99, 0x29, 0xFF }}}, {{{ 8, 5, 13 }, 0, { 597, 1168 }, {0x2C, 0xD3, 0x65, 0xFF }}}, {{{ 8, 24, 8 }, 0, { 0, 1024 }, {0x2C, 0x67, 0x2B, 0xFF }}}, {{{ 8, 24, -8 }, 0, { 0, 1654 }, {0x2C, 0x67, 0xD4, 0xFF }}}, {{{ -8, 24, -8 }, 0, { 630, 1654 }, {0xD5, 0x67, 0xD4, 0xFF }}}, {{{ -8, 24, 8 }, 0, { 630, 1024 }, {0xD5, 0x67, 0x2B, 0xFF }}}, {{{ 8, 0, -8 }, 0, { 0, 1024 }, {0x2A, 0x99, 0xD6, 0xFF }}}, {{{ 8, 0, 8 }, 0, { 0, 1654 }, {0x2A, 0x99, 0x29, 0xFF }}}, {{{ -8, 0, 8 }, 0, { 630, 1654 }, {0xD7, 0x99, 0x29, 0xFF }}}, {{{ -8, 0, -8 }, 0, { 630, 1024 }, {0xD7, 0x99, 0xD6, 0xFF }}}, }; Gfx d_course_bowsers_castle_dl_8F38[] = { gsSPNumLights(1), gsSPTexture(0xFFFF, 0xFFFF, 0, G_TX_RENDERTILE, G_ON), gsDPPipeSync(), gsDPSetCombineMode(G_CC_MODULATEIA, G_CC_MODULATEIA), gsDPSetRenderMode(G_RM_AA_ZB_OPA_SURF, G_RM_AA_ZB_OPA_SURF2), gsSPVertex(d_course_bowsers_castle_thwomp_model1, 4, 0), gsSP1Quadrangle(0, 1, 2, 3, 0), gsDPTileSync(), gsDPSetTile(G_IM_FMT_RGBA, G_IM_SIZ_16b, 8, 0x0000, G_TX_RENDERTILE, 0, G_TX_NOMIRROR | G_TX_WRAP, 5, G_TX_NOLOD, G_TX_NOMIRROR | G_TX_WRAP, 5, G_TX_NOLOD), gsDPSetTileSize(G_TX_RENDERTILE, 0, 0, 0x007C, 0x007C), gsDPSetTextureImage(G_IM_FMT_RGBA, G_IM_SIZ_16b, 1, d_course_bowsers_castle_thwomp_side), gsDPTileSync(), gsDPSetTile(G_IM_FMT_RGBA, G_IM_SIZ_16b, 0, 0x0000, G_TX_LOADTILE, 0, G_TX_NOMIRROR | G_TX_WRAP, G_TX_NOMASK, G_TX_NOLOD, G_TX_NOMIRROR | G_TX_WRAP, G_TX_NOMASK, G_TX_NOLOD), gsDPLoadSync(), gsDPLoadBlock(G_TX_LOADTILE, 0, 0, 1023, 256), gsSPVertex(d_course_bowsers_castle_thwomp_model2, 32, 0), gsSP2Triangles(0, 1, 2, 0, 3, 4, 5, 0), gsSP2Triangles(6, 7, 8, 0, 9, 10, 11, 0), gsSP2Triangles(12, 13, 14, 0, 15, 16, 17, 0), gsSP2Triangles(18, 19, 20, 0, 21, 22, 23, 0), gsSP1Quadrangle(24, 25, 26, 27, 0), gsSP1Quadrangle(28, 29, 30, 31, 0), gsSPVertex(d_course_bowsers_castle_thwomp_model3, 32, 0), gsSP1Quadrangle(0, 1, 2, 3, 0), gsSP1Quadrangle(4, 5, 6, 7, 0), gsSP1Quadrangle(8, 9, 10, 11, 0), gsSP1Quadrangle(12, 13, 14, 15, 0), gsSP1Quadrangle(16, 17, 18, 19, 0), gsSP1Quadrangle(20, 21, 22, 23, 0), gsSP1Quadrangle(24, 25, 26, 27, 0), gsSP1Quadrangle(28, 29, 30, 31, 0), gsSPVertex(d_course_bowsers_castle_thwomp_model4, 28, 0), gsSP1Quadrangle(0, 1, 2, 3, 0), gsSP1Quadrangle(4, 5, 6, 7, 0), gsSP1Quadrangle(8, 9, 10, 11, 0), gsSP1Quadrangle(12, 13, 14, 15, 0), gsSP1Quadrangle(16, 17, 18, 19, 0), gsSP1Quadrangle(20, 21, 22, 23, 0), gsSP1Quadrangle(24, 25, 26, 27, 0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_9078[] = { gsSPDisplayList(d_course_bowsers_castle_dl_8F38), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_thwomp[] = { gsSPDisplayList(d_course_bowsers_castle_dl_9078), gsSPEndDisplayList(), }; Vtx d_course_bowsers_castle_unknown_model[] = { {{{ 25, 0, 0 }, 0, { 1365, 1024 }, {0xFF, 0xFE, 0xFE, 0xFF}}}, {{{ 0, 40, 0 }, 0, { 512, -614 }, {0xFF, 0xFE, 0xFE, 0xFF}}}, {{{ -25, 0, 0 }, 0, { -341, 1024 }, {0xFF, 0xFE, 0xFE, 0xFF}}}, }; Gfx d_course_bowsers_castle_dl_bush[] = { gsSPTexture(0xFFFF, 0xFFFF, 0, G_TX_RENDERTILE, G_ON), gsDPPipeSync(), gsSPClearGeometryMode(G_LIGHTING), gsDPSetCombineMode(G_CC_MODULATEIDECALA, G_CC_MODULATEIDECALA), gsDPSetRenderMode(G_RM_AA_ZB_TEX_EDGE, G_RM_AA_ZB_TEX_EDGE2), gsDPTileSync(), gsDPSetTile(G_IM_FMT_RGBA, G_IM_SIZ_16b, 8, 0x0000, G_TX_RENDERTILE, 0, G_TX_NOMIRROR | G_TX_CLAMP, 5, G_TX_NOLOD, G_TX_NOMIRROR | G_TX_CLAMP, 5, G_TX_NOLOD), gsDPSetTileSize(G_TX_RENDERTILE, 0, 0, 0x007C, 0x007C), gsDPSetTextureImage(G_IM_FMT_RGBA, G_IM_SIZ_16b, 1, 0x03009000), gsDPTileSync(), gsDPSetTile(G_IM_FMT_RGBA, G_IM_SIZ_16b, 0, 0x0000, G_TX_LOADTILE, 0, G_TX_NOMIRROR | G_TX_WRAP, G_TX_NOMASK, G_TX_NOLOD, G_TX_NOMIRROR | G_TX_WRAP, G_TX_NOMASK, G_TX_NOLOD), gsDPLoadSync(), gsDPLoadBlock(G_TX_LOADTILE, 0, 0, 1023, 256), gsSPVertex(d_course_bowsers_castle_unknown_model, 3, 0), gsSP1Triangle(0, 1, 2, 0), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_9148[] = { gsDPSetCombineMode(G_CC_MODULATEIDECALA, G_CC_MODULATEIDECALA), gsDPSetRenderMode(G_RM_AA_ZB_TEX_EDGE, G_RM_AA_ZB_TEX_EDGE2), gsSPClearGeometryMode(G_CULL_BACK), gsSPDisplayList(d_course_bowsers_castle_packed_dl_428), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_328), gsSPSetGeometryMode(G_CULL_BACK), gsDPSetCombineMode(G_CC_MODULATEIA, G_CC_MODULATEIA), gsDPSetRenderMode(G_RM_AA_ZB_OPA_SURF, G_RM_AA_ZB_OPA_SURF2), gsSPDisplayList(d_course_bowsers_castle_packed_dl_94B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_9278), gsSPDisplayList(d_course_bowsers_castle_packed_dl_8E40), gsSPDisplayList(d_course_bowsers_castle_packed_dl_83B0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_75E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_57E8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_51B8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_4198), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3C70), gsSPDisplayList(d_course_bowsers_castle_packed_dl_3920), gsSPDisplayList(d_course_bowsers_castle_packed_dl_32F0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2BA8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_29A0), gsSPDisplayList(d_course_bowsers_castle_packed_dl_2098), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1E40), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1350), gsSPDisplayList(d_course_bowsers_castle_packed_dl_11F8), gsSPDisplayList(d_course_bowsers_castle_packed_dl_A10), gsSPEndDisplayList(), }; Gfx d_course_bowsers_castle_dl_9228[] = { gsDPPipeSync(), gsSPTexture(0xFFFF, 0xFFFF, 0, G_TX_RENDERTILE, G_ON), gsSPClearGeometryMode(G_LIGHTING), gsDPNoOp(), gsDPSetCombineMode(G_CC_MODULATEIA, G_CC_MODULATEIA), gsDPPipeSync(), gsDPSetRenderMode(G_RM_AA_ZB_XLU_INTER, G_RM_NOOP2), gsDPSetCombineMode(G_CC_MODULATEIA, G_CC_MODULATEIA), gsSPDisplayList(d_course_bowsers_castle_packed_dl_1350), gsSPSetGeometryMode(G_CULL_BACK), gsDPSetAlphaCompare(G_AC_NONE), gsDPPipeSync(), gsSPEndDisplayList(), }; // 0x9290 Spawn locations for item boxes and trees struct ActorSpawnData d_course_bowsers_castle_tree_spawn[] = { {{ -150, 0, -1350 }, {7}}, {{ -150, 0, -1450 }, {7}}, {{ -150, 0, -1550 }, {7}}, {{ -150, 0, -1650 }, {7}}, {{ 400, 0, -1900 }, {7}}, {{ 300, 0, -1900 }, {7}}, {{ 200, 0, -1900 }, {7}}, {{ 100, 0, -1900 }, {7}}, {{ 150, 0, -1350 }, {7}}, {{ 150, 0, -1450 }, {7}}, {{ 400, 0, -1600 }, {7}}, {{ 300, 0, -1600 }, {7}}, {{ 225, 0, -1525 }, {7}}, {{ 829, 0, -752 }, {7}}, {{ 829, 0, -652 }, {7}}, {{ 829, 0, -552 }, {7}}, {{ 829, 0, -452 }, {7}}, {{ 1129, 0, -527 }, {7}}, {{ 1129, 0, -377 }, {7}}, {{ 1204, 0, -527 }, {7}}, {{ 1204, 0, -377 }, {7}}, {{ 1279, 0, -377 }, {7}}, {{ 1279, 0, -527 }, {7}}, {{ 1354, 0, -527 }, {7}}, {{ 1354, 0, -377 }, {7}}, {{ 1429, 0, -377 }, {7}}, {{ 1429, 0, -527 }, {7}}, {{ -32768, 0, 0 }, {0}}, }; struct ActorSpawnData d_course_bowsers_castle_item_box_spawns[] = { {{ 64, 0, -1592 }, {0}}, {{ 78, 0, -1649 }, {0}}, {{ 132, 0, -1669 }, {0}}, {{ 123, 0, -1598 }, {0}}, {{ 1156, 0, -771 }, {1}}, {{ 1192, 0, -827 }, {1}}, {{ 1141, 0, -815 }, {1}}, {{ 1198, 0, -798 }, {1}}, {{ 1190, 7, 420 }, {2}}, {{ 1160, 5, 480 }, {2}}, {{ 1100, 2, 434 }, {2}}, {{ 1103, 3, 372 }, {2}}, {{ -32768, 0, 0 }, {0}}, }; // 0x93D8 TrackSections d_course_bowsers_castle_addr[] = { { d_course_bowsers_castle_packed_dl_5448, 4, 1, 0x0000 }, { d_course_bowsers_castle_packed_dl_53E0, 4, 2, 0x0000 }, { d_course_bowsers_castle_packed_dl_93A0, 17, 3, 0x0000 }, { d_course_bowsers_castle_packed_dl_9290, 17, 4, 0x0000 }, { d_course_bowsers_castle_packed_dl_30C8, 4, 5, 0x0000 }, { d_course_bowsers_castle_packed_dl_1FA0, 8, 5, 0x0000 }, { d_course_bowsers_castle_packed_dl_3578, 4, 6, 0x0000 }, { d_course_bowsers_castle_packed_dl_3930, 4, 7, 0x0000 }, { d_course_bowsers_castle_packed_dl_3C80, 4, 8, 0x0000 }, { d_course_bowsers_castle_packed_dl_D38, 4, 9, 0x0000 }, { d_course_bowsers_castle_packed_dl_41A8, 4, 10, 0x0000 }, { d_course_bowsers_castle_packed_dl_B80, 4, 11, 0x0000 }, { d_course_bowsers_castle_packed_dl_280, 16, 12, 0x0000 }, { d_course_bowsers_castle_packed_dl_2A48, 4, 12, 0x0000 }, { d_course_bowsers_castle_packed_dl_A20, 4, 13, 0x0000 }, { d_course_bowsers_castle_packed_dl_470, 4, 14, 0x0000 }, { d_course_bowsers_castle_packed_dl_3308, 4, 15, 0x0000 }, { d_course_bowsers_castle_packed_dl_1EA8, 8, 15, 0x0000 }, { d_course_bowsers_castle_packed_dl_9328, 17, 16, 0x0000 }, { d_course_bowsers_castle_packed_dl_9438, 17, 17, 0x0000 }, { d_course_bowsers_castle_packed_dl_5378, 4, 18, 0x0000 }, { d_course_bowsers_castle_packed_dl_5300, 4, 19, 0x0000 }, { d_course_bowsers_castle_packed_dl_5270, 4, 20, 0x0000 }, { d_course_bowsers_castle_packed_dl_51E8, 4, 21, 0x0000 }, { d_course_bowsers_castle_packed_dl_54E8, 4, 22, 0x0000 }, { d_course_bowsers_castle_packed_dl_5778, 4, 23, 0x0000 }, { d_course_bowsers_castle_packed_dl_56F0, 4, 24, 0x0000 }, { d_course_bowsers_castle_packed_dl_5678, 4, 25, 0x0000 }, { d_course_bowsers_castle_packed_dl_55E8, 4, 26, 0x0000 }, { d_course_bowsers_castle_packed_dl_5560, 4, 27, 0x0000 }, { d_course_bowsers_castle_packed_dl_8E40, 4, 255, 0x0000 }, { d_course_bowsers_castle_packed_dl_2BB8, 4, 255, 0x0000 }, { d_course_bowsers_castle_packed_dl_75E8, 255, 255, 0x0000 }, { d_course_bowsers_castle_packed_dl_9278, 255, 255, 0x0000 }, { d_course_bowsers_castle_packed_dl_3B0, 255, 255, 0x0000 }, { d_course_bowsers_castle_packed_dl_83B0, 255, 255, 0x0000 }, { 0x00000000, 0, 0, 0x0000 }, };

32fd765bf0d02695db9c5fd81bfeafe770e93a19

e65a4dbfbfb0e54e59787ba7741efee12f7687f3

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patch-lib_gibber_gibber-muc-connection.c

--- lib/gibber/gibber-muc-connection.c.orig 2012-11-12 14:13:18 UTC +++ lib/gibber/gibber-muc-connection.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <netinet/in.h> #include <stdio.h> #include <stdlib.h>

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loadlibPWGJEEMCAL.C

void loadlibPWGJEEMCAL() { // this macro should load PWGJE with all dependencies from ROOT // (it should not require to be run with AliRoot) // // please use the macro before a commit to check // that the PWGJE libraries not only compile but can also be loaded // with the known dependencies // // if you have to add dependendencies make sure that people get informed // (especially the operators of trains should know what to change) gSystem->Load("libCore"); gSystem->Load("libPhysics"); gSystem->Load("libMinuit"); gSystem->Load("libVMC"); gSystem->Load("libNet"); gSystem->Load("libTree"); gSystem->Load("libSTEERBase"); gSystem->Load("libESD"); gSystem->Load("libAOD"); gSystem->Load("libANALYSIS"); gSystem->Load("libANALYSISalice"); gSystem->Load("libOADB"); gSystem->Load("libCDB"); gSystem->Load("libTender"); gSystem->Load("libCORRFW"); gSystem->Load("libPWGTools"); gSystem->Load("libPWGEMCAL"); gSystem->Load("libCGAL"); gSystem->Load("libfastjet"); gSystem->Load("libsiscone"); gSystem->Load("libsiscone_spherical"); gSystem->Load("libfastjetplugins"); gSystem->Load("libfastjettools"); gSystem->Load("libfastjetcontribfragile"); gSystem->Load("libPWGJEEMCALJetTasks"); }

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#include "common.h" #include <ctype.h> #include <plumb.h> #include <libsec.h> #include <thread.h> #include "dat.h" extern char* dirtab[]; /* jpc */ typedef struct Header Header; struct Header { char *type; void (*f)(Message*, Header*, char*); int len; }; /* headers */ static void ctype(Message*, Header*, char*); static void cencoding(Message*, Header*, char*); static void cdisposition(Message*, Header*, char*); static void date822(Message*, Header*, char*); static void from822(Message*, Header*, char*); static void to822(Message*, Header*, char*); static void sender822(Message*, Header*, char*); static void replyto822(Message*, Header*, char*); static void subject822(Message*, Header*, char*); static void inreplyto822(Message*, Header*, char*); static void cc822(Message*, Header*, char*); static void bcc822(Message*, Header*, char*); static void messageid822(Message*, Header*, char*); static void mimeversion(Message*, Header*, char*); static void nullsqueeze(Message*); enum { Mhead= 11, /* offset of first mime header */ }; Header head[] = { { "date:", date822, }, { "from:", from822, }, { "to:", to822, }, { "sender:", sender822, }, { "reply-to:", replyto822, }, { "subject:", subject822, }, { "cc:", cc822, }, { "bcc:", bcc822, }, { "in-reply-to:", inreplyto822, }, { "mime-version:", mimeversion, }, { "message-id:", messageid822, }, [Mhead] { "content-type:", ctype, }, { "content-transfer-encoding:", cencoding, }, { "content-disposition:", cdisposition, }, { 0, } }; /* static void fatal(char *fmt, ...); jpc */ static void initquoted(void); /* static void startheader(Message*); static void startbody(Message*); jpc */ static char* skipwhite(char*); static char* skiptosemi(char*); static char* getstring(char*, String*, int); static void setfilename(Message*, char*); /* static char* lowercase(char*); jpc */ static int is8bit(Message*); static int headerline(char**, String*); static void initheaders(void); static void parseattachments(Message*, Mailbox*); int debug; char *Enotme = "path not served by this file server"; enum { Chunksize = 1024 }; Mailboxinit *boxinit[] = { imap4mbox, pop3mbox, plan9mbox }; char* syncmbox(Mailbox *mb, int doplumb) { return (*mb->sync)(mb, doplumb); } /* create a new mailbox */ char* newmbox(char *path, char *name, int std) { Mailbox *mb, **l; char *p, *rv; int i; initheaders(); mb = emalloc(sizeof(*mb)); strncpy(mb->path, path, sizeof(mb->path)-1); if(name == nil){ p = strrchr(path, '/'); if(p == nil) p = path; else p++; if(*p == 0){ free(mb); return "bad mbox name"; } strncpy(mb->name, p, sizeof(mb->name)-1); } else { strncpy(mb->name, name, sizeof(mb->name)-1); } rv = nil; /* check for a mailbox type */ for(i=0; i<nelem(boxinit); i++) if((rv = (*boxinit[i])(mb, path)) != Enotme) break; if(i == nelem(boxinit)){ free(mb); return "bad path"; } /* on error, give up */ if(rv){ free(mb); return rv; } /* make sure name isn't taken */ qlock(&mbllock); for(l = &mbl; *l != nil; l = &(*l)->next){ if(strcmp((*l)->name, mb->name) == 0){ if(strcmp(path, (*l)->path) == 0) rv = nil; else rv = "mbox name in use"; if(mb->close) (*mb->close)(mb); free(mb); qunlock(&mbllock); return rv; } } /* always try locking */ mb->dolock = 1; mb->refs = 1; mb->next = nil; mb->id = newid(); mb->root = newmessage(nil); mb->std = std; *l = mb; qunlock(&mbllock); qlock(&mb->ql); if(mb->ctl){ henter(PATH(mb->id, Qmbox), "ctl", (Qid){PATH(mb->id, Qmboxctl), 0, QTFILE}, nil, mb); } rv = syncmbox(mb, 0); qunlock(&mb->ql); return rv; } /* close the named mailbox */ void freembox(char *name) { Mailbox **l, *mb; qlock(&mbllock); for(l=&mbl; *l != nil; l=&(*l)->next){ if(strcmp(name, (*l)->name) == 0){ mb = *l; *l = mb->next; mboxdecref(mb); break; } } hfree(PATH(0, Qtop), name); qunlock(&mbllock); } static void initheaders(void) { Header *h; static int already; if(already) return; already = 1; for(h = head; h->type != nil; h++) h->len = strlen(h->type); } /* * parse a Unix style header */ void parseunix(Message *m) { char *p; String *h; h = s_new(); for(p = m->start + 5; *p && *p != '\r' && *p != '\n'; p++) s_putc(h, *p); s_terminate(h); s_restart(h); m->unixfrom = s_parse(h, s_reset(m->unixfrom)); m->unixdate = s_append(s_reset(m->unixdate), h->ptr); s_free(h); } /* * parse a message */ void parseheaders(Message *m, int justmime, Mailbox *mb, int addfrom) { String *hl; Header *h; char *p, *q; int i; if(m->whole == m->whole->whole){ henter(PATH(mb->id, Qmbox), m->name, (Qid){PATH(m->id, Qdir), 0, QTDIR}, m, mb); } else { henter(PATH(m->whole->id, Qdir), m->name, (Qid){PATH(m->id, Qdir), 0, QTDIR}, m, mb); } for(i = 0; i < Qmax; i++) henter(PATH(m->id, Qdir), dirtab[i], (Qid){PATH(m->id, i), 0, QTFILE}, m, mb); /* parse mime headers */ p = m->header; hl = s_new(); while(headerline(&p, hl)){ if(justmime) h = &head[Mhead]; else h = head; for(; h->type; h++){ if(cistrncmp(s_to_c(hl), h->type, h->len) == 0){ (*h->f)(m, h, s_to_c(hl)); break; } } s_reset(hl); } s_free(hl); /* the blank line isn't really part of the body or header */ if(justmime){ m->mhend = p; m->hend = m->header; } else { m->hend = p; } if(*p == '\n') p++; m->rbody = m->body = p; /* if type is text, get any nulls out of the body. This is */ /* for the two seans and imap clients that get confused. */ if(strncmp(s_to_c(m->type), "text/", 5) == 0) nullsqueeze(m); /* */ /* cobble together Unix-style from line */ /* for local mailbox messages, we end up recreating the */ /* original header. */ /* for pop3 messages, the best we can do is */ /* use the From: information and the RFC822 date. */ /* */ if(m->unixdate == nil || strcmp(s_to_c(m->unixdate), "???") == 0 || strcmp(s_to_c(m->unixdate), "Thu Jan 1 00:00:00 GMT 1970") == 0){ if(m->unixdate){ s_free(m->unixdate); m->unixdate = nil; } /* look for the date in the first Received: line. */ /* it's likely to be the right time zone (it's */ /* the local system) and in a convenient format. */ if(cistrncmp(m->header, "received:", 9)==0){ if((q = strchr(m->header, ';')) != nil){ p = q; while((p = strchr(p, '\n')) != nil){ if(p[1] != ' ' && p[1] != '\t' && p[1] != '\n') break; p++; } if(p){ *p = '\0'; m->unixdate = date822tounix(q+1); *p = '\n'; } } } /* fall back on the rfc822 date */ if(m->unixdate==nil && m->date822) m->unixdate = date822tounix(s_to_c(m->date822)); } if(m->unixheader != nil) s_free(m->unixheader); /* only fake header for top-level messages for pop3 and imap4 */ /* clients (those protocols don't include the unix header). */ /* adding the unix header all the time screws up mime-attached */ /* rfc822 messages. */ if(!addfrom && !m->unixfrom){ m->unixheader = nil; return; } m->unixheader = s_copy("From "); if(m->unixfrom && strcmp(s_to_c(m->unixfrom), "???") != 0) s_append(m->unixheader, s_to_c(m->unixfrom)); else if(m->from822) s_append(m->unixheader, s_to_c(m->from822)); else s_append(m->unixheader, "???"); s_append(m->unixheader, " "); if(m->unixdate) s_append(m->unixheader, s_to_c(m->unixdate)); else s_append(m->unixheader, "Thu Jan 1 00:00:00 GMT 1970"); s_append(m->unixheader, "\n"); } String* promote(String **sp) { String *s; if(*sp != nil) s = s_clone(*sp); else s = nil; return s; } void parsebody(Message *m, Mailbox *mb) { Message *nm; /* recurse */ if(strncmp(s_to_c(m->type), "multipart/", 10) == 0){ parseattachments(m, mb); } else if(strcmp(s_to_c(m->type), "message/rfc822") == 0){ decode(m); parseattachments(m, mb); nm = m->part; /* promote headers */ if(m->replyto822 == nil && m->from822 == nil && m->sender822 == nil){ m->from822 = promote(&nm->from822); m->to822 = promote(&nm->to822); m->date822 = promote(&nm->date822); m->sender822 = promote(&nm->sender822); m->replyto822 = promote(&nm->replyto822); m->subject822 = promote(&nm->subject822); m->unixdate = promote(&nm->unixdate); } } } void parse(Message *m, int justmime, Mailbox *mb, int addfrom) { parseheaders(m, justmime, mb, addfrom); parsebody(m, mb); } static void parseattachments(Message *m, Mailbox *mb) { Message *nm, **l; char *p, *x; /* if there's a boundary, recurse... */ if(m->boundary != nil){ p = m->body; nm = nil; l = &m->part; for(;;){ x = strstr(p, s_to_c(m->boundary)); /* no boundary, we're done */ if(x == nil){ if(nm != nil) nm->rbend = nm->bend = nm->end = m->bend; break; } /* boundary must be at the start of a line */ if(x != m->body && *(x-1) != '\n'){ p = x+1; continue; } if(nm != nil) nm->rbend = nm->bend = nm->end = x; x += strlen(s_to_c(m->boundary)); /* is this the last part? ignore anything after it */ if(strncmp(x, "--", 2) == 0) break; p = strchr(x, '\n'); if(p == nil) break; nm = newmessage(m); nm->start = nm->header = nm->body = nm->rbody = ++p; nm->mheader = nm->header; *l = nm; l = &nm->next; } for(nm = m->part; nm != nil; nm = nm->next) parse(nm, 1, mb, 0); return; } /* if we've got an rfc822 message, recurse... */ if(strcmp(s_to_c(m->type), "message/rfc822") == 0){ nm = newmessage(m); m->part = nm; nm->start = nm->header = nm->body = nm->rbody = m->body; nm->end = nm->bend = nm->rbend = m->bend; parse(nm, 0, mb, 0); } } /* * pick up a header line */ static int headerline(char **pp, String *hl) { char *p, *x; s_reset(hl); p = *pp; x = strpbrk(p, ":\n"); if(x == nil || *x == '\n') return 0; for(;;){ x = strchr(p, '\n'); if(x == nil) x = p + strlen(p); s_nappend(hl, p, x-p); p = x; if(*p != '\n' || *++p != ' ' && *p != '\t') break; while(*p == ' ' || *p == '\t') p++; s_putc(hl, ' '); } *pp = p; return 1; } static String* addr822(char *p) { String *s, *list; int incomment, addrdone, inanticomment, quoted; int n; int c; list = s_new(); s = s_new(); quoted = incomment = addrdone = inanticomment = 0; n = 0; for(; *p; p++){ c = *p; /* whitespace is ignored */ if(!quoted && isspace(c) || c == '\r') continue; /* strings are always treated as atoms */ if(!quoted && c == '"'){ if(!addrdone && !incomment) s_putc(s, c); for(p++; *p; p++){ if(!addrdone && !incomment) s_putc(s, *p); if(!quoted && *p == '"') break; if(*p == '\\') quoted = 1; else quoted = 0; } if(*p == 0) break; quoted = 0; continue; } /* ignore everything in an expicit comment */ if(!quoted && c == '('){ incomment = 1; continue; } if(incomment){ if(!quoted && c == ')') incomment = 0; quoted = 0; continue; } /* anticomments makes everything outside of them comments */ if(!quoted && c == '<' && !inanticomment){ inanticomment = 1; s = s_reset(s); continue; } if(!quoted && c == '>' && inanticomment){ addrdone = 1; inanticomment = 0; continue; } /* commas separate addresses */ if(!quoted && c == ',' && !inanticomment){ s_terminate(s); addrdone = 0; if(n++ != 0) s_append(list, " "); s_append(list, s_to_c(s)); s = s_reset(s); continue; } /* what's left is part of the address */ s_putc(s, c); /* quoted characters are recognized only as characters */ if(c == '\\') quoted = 1; else quoted = 0; } if(*s_to_c(s) != 0){ s_terminate(s); if(n++ != 0) s_append(list, " "); s_append(list, s_to_c(s)); } s_free(s); if(n == 0){ s_free(list); return nil; } return list; } static void to822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->to822); m->to822 = addr822(p); } static void cc822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->cc822); m->cc822 = addr822(p); } static void bcc822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->bcc822); m->bcc822 = addr822(p); } static void from822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->from822); m->from822 = addr822(p); } static void sender822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->sender822); m->sender822 = addr822(p); } static void replyto822(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->replyto822); m->replyto822 = addr822(p); } static void mimeversion(Message *m, Header *h, char *p) { p += strlen(h->type); s_free(m->mimeversion); m->mimeversion = addr822(p); } static void killtrailingwhite(char *p) { char *e; e = p + strlen(p) - 1; while(e > p && isspace(*e)) *e-- = 0; } static void date822(Message *m, Header *h, char *p) { p += strlen(h->type); p = skipwhite(p); s_free(m->date822); m->date822 = s_copy(p); p = s_to_c(m->date822); killtrailingwhite(p); } static void subject822(Message *m, Header *h, char *p) { p += strlen(h->type); p = skipwhite(p); s_free(m->subject822); m->subject822 = s_copy(p); p = s_to_c(m->subject822); killtrailingwhite(p); } static void inreplyto822(Message *m, Header *h, char *p) { p += strlen(h->type); p = skipwhite(p); s_free(m->inreplyto822); m->inreplyto822 = s_copy(p); p = s_to_c(m->inreplyto822); killtrailingwhite(p); } static void messageid822(Message *m, Header *h, char *p) { p += strlen(h->type); p = skipwhite(p); s_free(m->messageid822); m->messageid822 = s_copy(p); p = s_to_c(m->messageid822); killtrailingwhite(p); } static int isattribute(char **pp, char *attr) { char *p; int n; n = strlen(attr); p = *pp; if(cistrncmp(p, attr, n) != 0) return 0; p += n; while(*p == ' ') p++; if(*p++ != '=') return 0; while(*p == ' ') p++; *pp = p; return 1; } static void ctype(Message *m, Header *h, char *p) { String *s; p += h->len; p = skipwhite(p); p = getstring(p, m->type, 1); while(*p){ if(isattribute(&p, "boundary")){ s = s_new(); p = getstring(p, s, 0); m->boundary = s_reset(m->boundary); s_append(m->boundary, "--"); s_append(m->boundary, s_to_c(s)); s_free(s); } else if(cistrncmp(p, "multipart", 9) == 0){ /* * the first unbounded part of a multipart message, * the preamble, is not displayed or saved */ } else if(isattribute(&p, "name")){ if(m->filename == nil) setfilename(m, p); } else if(isattribute(&p, "charset")){ p = getstring(p, s_reset(m->charset), 0); } p = skiptosemi(p); } } static void cencoding(Message *m, Header *h, char *p) { p += h->len; p = skipwhite(p); if(cistrncmp(p, "base64", 6) == 0) m->encoding = Ebase64; else if(cistrncmp(p, "quoted-printable", 16) == 0) m->encoding = Equoted; } static void cdisposition(Message *m, Header *h, char *p) { p += h->len; p = skipwhite(p); while(*p){ if(cistrncmp(p, "inline", 6) == 0){ m->disposition = Dinline; } else if(cistrncmp(p, "attachment", 10) == 0){ m->disposition = Dfile; } else if(cistrncmp(p, "filename=", 9) == 0){ p += 9; setfilename(m, p); } p = skiptosemi(p); } } ulong msgallocd, msgfreed; Message* newmessage(Message *parent) { /* static int id; jpc */ Message *m; msgallocd++; m = emalloc(sizeof(*m)); memset(m, 0, sizeof(*m)); m->disposition = Dnone; m->type = s_copy("text/plain"); m->charset = s_copy("iso-8859-1"); m->id = newid(); if(parent) sprint(m->name, "%d", ++(parent->subname)); if(parent == nil) parent = m; m->whole = parent; m->hlen = -1; return m; } /* delete a message from a mailbox */ void delmessage(Mailbox *mb, Message *m) { Message **l; int i; mb->vers++; msgfreed++; if(m->whole != m){ /* unchain from parent */ for(l = &m->whole->part; *l && *l != m; l = &(*l)->next) ; if(*l != nil) *l = m->next; /* clear out of name lookup hash table */ if(m->whole->whole == m->whole) hfree(PATH(mb->id, Qmbox), m->name); else hfree(PATH(m->whole->id, Qdir), m->name); for(i = 0; i < Qmax; i++) hfree(PATH(m->id, Qdir), dirtab[i]); } /* recurse through sub-parts */ while(m->part) delmessage(mb, m->part); /* free memory */ if(m->mallocd) free(m->start); if(m->hallocd) free(m->header); if(m->ballocd) free(m->body); s_free(m->unixfrom); s_free(m->unixdate); s_free(m->unixheader); s_free(m->from822); s_free(m->sender822); s_free(m->to822); s_free(m->bcc822); s_free(m->cc822); s_free(m->replyto822); s_free(m->date822); s_free(m->inreplyto822); s_free(m->subject822); s_free(m->messageid822); s_free(m->addrs); s_free(m->mimeversion); s_free(m->sdigest); s_free(m->boundary); s_free(m->type); s_free(m->charset); s_free(m->filename); free(m); } /* mark messages (identified by path) for deletion */ void delmessages(int ac, char **av) { Mailbox *mb; Message *m; int i, needwrite; qlock(&mbllock); for(mb = mbl; mb != nil; mb = mb->next) if(strcmp(av[0], mb->name) == 0){ qlock(&mb->ql); break; } qunlock(&mbllock); if(mb == nil) return; needwrite = 0; for(i = 1; i < ac; i++){ for(m = mb->root->part; m != nil; m = m->next) if(strcmp(m->name, av[i]) == 0){ if(!m->deleted){ mailplumb(mb, m, 1); needwrite = 1; m->deleted = 1; logmsg("deleting", m); } break; } } if(needwrite) syncmbox(mb, 1); qunlock(&mb->ql); } /* * the following are called with the mailbox qlocked */ void msgincref(Message *m) { m->refs++; } void msgdecref(Mailbox *mb, Message *m) { m->refs--; if(m->refs == 0 && m->deleted) syncmbox(mb, 1); } /* * the following are called with mbllock'd */ void mboxincref(Mailbox *mb) { assert(mb->refs > 0); mb->refs++; } void mboxdecref(Mailbox *mb) { assert(mb->refs > 0); qlock(&mb->ql); mb->refs--; if(mb->refs == 0){ delmessage(mb, mb->root); if(mb->ctl) hfree(PATH(mb->id, Qmbox), "ctl"); if(mb->close) (*mb->close)(mb); free(mb); } else qunlock(&mb->ql); } int cistrncmp(char *a, char *b, int n) { while(n-- > 0){ if(tolower(*a++) != tolower(*b++)) return -1; } return 0; } int cistrcmp(char *a, char *b) { for(;;){ if(tolower(*a) != tolower(*b++)) return -1; if(*a++ == 0) break; } return 0; } static char* skipwhite(char *p) { while(isspace(*p)) p++; return p; } static char* skiptosemi(char *p) { while(*p && *p != ';') p++; while(*p == ';' || isspace(*p)) p++; return p; } static char* getstring(char *p, String *s, int dolower) { s = s_reset(s); p = skipwhite(p); if(*p == '"'){ p++; for(;*p && *p != '"'; p++) if(dolower) s_putc(s, tolower(*p)); else s_putc(s, *p); if(*p == '"') p++; s_terminate(s); return p; } for(; *p && !isspace(*p) && *p != ';'; p++) if(dolower) s_putc(s, tolower(*p)); else s_putc(s, *p); s_terminate(s); return p; } static void setfilename(Message *m, char *p) { m->filename = s_reset(m->filename); getstring(p, m->filename, 0); for(p = s_to_c(m->filename); *p; p++) if(*p == ' ' || *p == '\t' || *p == ';') *p = '_'; } /* */ /* undecode message body */ /* */ void decode(Message *m) { int i, len; char *x; if(m->decoded) return; switch(m->encoding){ case Ebase64: len = m->bend - m->body; i = (len*3)/4+1; /* room for max chars + null */ x = emalloc(i); len = dec64((uchar*)x, i, m->body, len); if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; break; case Equoted: len = m->bend - m->body; x = emalloc(len+2); /* room for null and possible extra nl */ len = decquoted(x, m->body, m->bend); if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; break; default: break; } m->decoded = 1; } /* convert latin1 to utf */ void convert(Message *m) { int len; char *x; /* don't convert if we're not a leaf, not text, or already converted */ if(m->converted) return; if(m->part != nil) return; if(cistrncmp(s_to_c(m->type), "text", 4) != 0) return; if(cistrcmp(s_to_c(m->charset), "us-ascii") == 0 || cistrcmp(s_to_c(m->charset), "iso-8859-1") == 0){ len = is8bit(m); if(len > 0){ len = 2*len + m->bend - m->body + 1; x = emalloc(len); len = latin1toutf(x, m->body, m->bend); if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "iso-8859-2") == 0){ len = xtoutf("8859-2", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "iso-8859-15") == 0){ len = xtoutf("8859-15", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "big5") == 0){ len = xtoutf("big5", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "iso-2022-jp") == 0){ len = xtoutf("jis", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "windows-1257") == 0 || cistrcmp(s_to_c(m->charset), "windows-1252") == 0){ len = is8bit(m); if(len > 0){ len = 2*len + m->bend - m->body + 1; x = emalloc(len); len = windows1257toutf(x, m->body, m->bend); if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "windows-1251") == 0){ len = xtoutf("cp1251", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } else if(cistrcmp(s_to_c(m->charset), "koi8-r") == 0){ len = xtoutf("koi8", &x, m->body, m->bend); if(len != 0){ if(m->ballocd) free(m->body); m->body = x; m->bend = x + len; m->ballocd = 1; } } m->converted = 1; } enum { Self= 1, Hex= 2 }; uchar tableqp[256]; static void initquoted(void) { int c; memset(tableqp, 0, 256); for(c = ' '; c <= '<'; c++) tableqp[c] = Self; for(c = '>'; c <= '~'; c++) tableqp[c] = Self; tableqp['\t'] = Self; tableqp['='] = Hex; } static int hex2int(int x) { if(x >= '0' && x <= '9') return x - '0'; if(x >= 'A' && x <= 'F') return (x - 'A') + 10; if(x >= 'a' && x <= 'f') return (x - 'a') + 10; return 0; } static char* decquotedline(char *out, char *in, char *e) { int c, soft; /* dump trailing white space */ while(e >= in && (*e == ' ' || *e == '\t' || *e == '\r' || *e == '\n')) e--; /* trailing '=' means no newline */ if(*e == '='){ soft = 1; e--; } else soft = 0; while(in <= e){ c = (*in++) & 0xff; switch(tableqp[c]){ case Self: *out++ = c; break; case Hex: c = hex2int(*in++)<<4; c |= hex2int(*in++); *out++ = c; break; } } if(!soft) *out++ = '\n'; *out = 0; return out; } int decquoted(char *out, char *in, char *e) { char *p, *nl; if(tableqp[' '] == 0) initquoted(); p = out; while((nl = strchr(in, '\n')) != nil && nl < e){ p = decquotedline(p, in, nl); in = nl + 1; } if(in < e) p = decquotedline(p, in, e-1); /* make sure we end with a new line */ if(*(p-1) != '\n'){ *p++ = '\n'; *p = 0; } return p - out; } #if 0 /* jpc */ static char* lowercase(char *p) { char *op; int c; for(op = p; c = *p; p++) if(isupper(c)) *p = tolower(c); return op; } #endif /* * return number of 8 bit characters */ static int is8bit(Message *m) { int count = 0; char *p; for(p = m->body; p < m->bend; p++) if(*p & 0x80) count++; return count; } /* translate latin1 directly since it fits neatly in utf */ int latin1toutf(char *out, char *in, char *e) { Rune r; char *p; p = out; for(; in < e; in++){ r = (*in) & 0xff; p += runetochar(p, &r); } *p = 0; return p - out; } /* translate any thing else using the tcs program */ int xtoutf(char *charset, char **out, char *in, char *e) { char *av[4]; int totcs[2]; int fromtcs[2]; int n, len, sofar; char *p; len = e-in+1; sofar = 0; *out = p = malloc(len+1); if(p == nil) return 0; av[0] = charset; av[1] = "-f"; av[2] = charset; av[3] = 0; if(pipe(totcs) < 0) return 0; if(pipe(fromtcs) < 0){ close(totcs[0]); close(totcs[1]); return 0; } switch(rfork(RFPROC|RFFDG|RFNOWAIT)){ case -1: close(fromtcs[0]); close(fromtcs[1]); close(totcs[0]); close(totcs[1]); return 0; case 0: close(fromtcs[0]); close(totcs[1]); dup(fromtcs[1], 1); dup(totcs[0], 0); close(fromtcs[1]); close(totcs[0]); dup(open("/dev/null", OWRITE), 2); /*jpc exec("/bin/tcs", av); */ exec(unsharp("#9/bin/tcs"), av); /* _exits(0); */ threadexits(nil); default: close(fromtcs[1]); close(totcs[0]); switch(rfork(RFPROC|RFFDG|RFNOWAIT)){ case -1: close(fromtcs[0]); close(totcs[1]); return 0; case 0: close(fromtcs[0]); while(in < e){ n = write(totcs[1], in, e-in); if(n <= 0) break; in += n; } close(totcs[1]); /* _exits(0); */ threadexits(nil); default: close(totcs[1]); for(;;){ n = read(fromtcs[0], &p[sofar], len-sofar); if(n <= 0) break; sofar += n; p[sofar] = 0; if(sofar == len){ len += 1024; *out = p = realloc(p, len+1); if(p == nil) return 0; } } close(fromtcs[0]); break; } break; } return sofar; } enum { Winstart= 0x7f, Winend= 0x9f }; Rune winchars[] = { L'•', L'•', L'•', L'‚', L'ƒ', L'„', L'…', L'†', L'‡', L'ˆ', L'‰', L'Š', L'‹', L'Œ', L'•', L'•', L'•', L'•', L'‘', L'’', L'“', L'”', L'•', L'–', L'—', L'˜', L'™', L'š', L'›', L'œ', L'•', L'•', L'Ÿ' }; int windows1257toutf(char *out, char *in, char *e) { Rune r; char *p; p = out; for(; in < e; in++){ r = (*in) & 0xff; if(r >= 0x7f && r <= 0x9f) r = winchars[r-0x7f]; p += runetochar(p, &r); } *p = 0; return p - out; } void * emalloc(ulong n) { void *p; p = mallocz(n, 1); if(!p){ fprint(2, "%s: out of memory alloc %lud\n", argv0, n); threadexits("out of memory"); } setmalloctag(p, getcallerpc(&n)); return p; } void * erealloc(void *p, ulong n) { if(n == 0) n = 1; p = realloc(p, n); if(!p){ fprint(2, "%s: out of memory realloc %lud\n", argv0, n); threadexits("out of memory"); } setrealloctag(p, getcallerpc(&p)); return p; } void mailplumb(Mailbox *mb, Message *m, int delete) { Plumbmsg p; Plumbattr a[7]; char buf[256]; int ai; char lenstr[10], *from, *subject, *date; static int fd = -1; if(m->subject822 == nil) subject = ""; else subject = s_to_c(m->subject822); if(m->from822 != nil) from = s_to_c(m->from822); else if(m->unixfrom != nil) from = s_to_c(m->unixfrom); else from = ""; if(m->unixdate != nil) date = s_to_c(m->unixdate); else date = ""; sprint(lenstr, "%ld", m->end-m->start); if(biffing && !delete) print("[ %s / %s / %s ]\n", from, subject, lenstr); if(!plumbing) return; if(fd < 0) fd = plumbopen("send", OWRITE); if(fd < 0) return; p.src = "mailfs"; p.dst = "seemail"; p.wdir = "/mail/fs"; p.type = "text"; ai = 0; a[ai].name = "filetype"; a[ai].value = "mail"; a[++ai].name = "sender"; a[ai].value = from; a[ai-1].next = &a[ai]; a[++ai].name = "length"; a[ai].value = lenstr; a[ai-1].next = &a[ai]; a[++ai].name = "mailtype"; a[ai].value = delete?"delete":"new"; a[ai-1].next = &a[ai]; a[++ai].name = "date"; a[ai].value = date; a[ai-1].next = &a[ai]; if(m->sdigest){ a[++ai].name = "digest"; a[ai].value = s_to_c(m->sdigest); a[ai-1].next = &a[ai]; } a[ai].next = nil; p.attr = a; snprint(buf, sizeof(buf), "%s/%s/%s", mntpt, mb->name, m->name); p.ndata = strlen(buf); p.data = buf; plumbsend(fd, &p); } /* */ /* count the number of lines in the body (for imap4) */ /* */ void countlines(Message *m) { int i; char *p; i = 0; for(p = strchr(m->rbody, '\n'); p != nil && p < m->rbend; p = strchr(p+1, '\n')) i++; sprint(m->lines, "%d", i); } char *LOG = "fs"; void logmsg(char *s, Message *m) { int pid; if(!logging) return; pid = getpid(); if(m == nil) syslog(0, LOG, "%s.%d: %s", user, pid, s); else syslog(0, LOG, "%s.%d: %s msg from %s digest %s", user, pid, s, m->from822 ? s_to_c(m->from822) : "?", s_to_c(m->sdigest)); } /* * squeeze nulls out of the body */ static void nullsqueeze(Message *m) { char *p, *q; q = memchr(m->body, 0, m->end-m->body); if(q == nil) return; for(p = m->body; q < m->end; q++){ if(*q == 0) continue; *p++ = *q; } m->bend = m->rbend = m->end = p; } /* */ /* convert an RFC822 date into a Unix style date */ /* for when the Unix From line isn't there (e.g. POP3). */ /* enough client programs depend on having a Unix date */ /* that it's easiest to write this conversion code once, right here. */ /* */ /* people don't follow RFC822 particularly closely, */ /* so we use strtotm, which is a bunch of heuristics. */ /* */ extern int strtotm(char*, Tm*); String* date822tounix(char *s) { char *p, *q; Tm tm; if(strtotm(s, &tm) < 0) return nil; p = asctime(&tm); if(q = strchr(p, '\n')) *q = '\0'; return s_copy(p); }

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/src/amd/lib-src/vect_lib.c

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vect_lib.c

/***************************************************************************** * * Copyright (c) 1996-1999 ADVANCED MICRO DEVICES, INC. All Rights reserved. * * This software is unpublished and contains the trade secrets and * confidential proprietary information of AMD. Unless otherwise * provided in the Software Agreement associated herewith, it is * licensed in confidence "AS IS" and is not to be reproduced in * whole or part by any means except for backup. Use, duplication, * or disclosure by the Government is subject to the restrictions * in paragraph(b)(3)(B)of the Rights in Technical Data and * Computer Software clause in DFAR 52.227-7013(a)(Oct 1988). * Software owned by Advanced Micro Devices Inc., One AMD Place * P.O. Box 3453, Sunnyvale, CA 94088-3453. * ***************************************************************************** * * VECT_LIB.C * * AMD3D 3D library code: Vector math * The majority of these routines are in vect.asm - this file only * provides a C wrapper for functions needing to return a float value. * * BETA RELEASE * *****************************************************************************/ #include <amd3dx.h> #include <avector.h> #ifdef _MSC_VER #pragma warning(disable:4799) #endif /* _mag_vect - find the magnitude of a vector * a - input vector * return - the magnitude of 'a' */ float _mag_vect(float *a) { float r; __asm { femms mov eax, a movq mm0, [eax] movd mm1, [eax+8] pfmul(mm0, mm0) pfmul(mm1, mm1) pfacc(mm0, mm0) pfadd(mm0, mm1) pfrsqrt(mm1, mm0) movq mm2, mm1 pfmul(mm1, mm1) pfrsqit1(mm1, mm0) pfrcpit2(mm1, mm2) pfmul(mm0, mm1) movd r, mm0 femms } return r; } /* _dot_vect - compute the dot product of two vectors * a - input vector 1 * b - input vector 2 * return - the dot product */ float _dot_vect(float *a, float *b) { float r; __asm { femms mov eax, a mov edx, b movq mm0, [eax] movd mm1, [eax+8] pfmul(mm0, edx) pfacc(mm0, mm0) pfmulm(mm1, edx, 0x8) pfadd(mm0, mm1) movd r, mm0 femms } return r; } // eof