source large_stringclasses 2
values | subject large_stringclasses 112
values | code large_stringclasses 112
values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
|---|---|---|---|---|
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The new hash-based module integrity checking will also be able to
satisfy the requirements of lockdown.
Such an alternative is not representable with "select", so use
"depends on" instead.
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
---
security/lockdown/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 de... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:58 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The upcoming CONFIG_MODULE_HASHES will introduce a signature type.
This needs to be handled by callers differently than PKCS7 signatures.
Report the signature type to the caller and let them verify it.
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
---
include/linux/module_signature.h | 2 +-
kernel/modu... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:57 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | CONFIG_MODULE_HASHES needs to process the modules at build time in the
exact form they will be loaded at runtime. If the modules are stripped
afterwards they will not be loadable anymore.
Also evaluate INSTALL_MOD_STRIP at build time and build the hashes based
on modules stripped this way.
If users specify inconsiste... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:29:01 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The logic to extract the signature bits from a module file are
duplicated between the module core and IMA modsig appraisal.
Unify the implementation.
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
---
include/linux/module_signature.h | 4 +--
kernel/module/signing.c | 52 +++++++--------------... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:52 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | To allow CONFIG_MODULE_HASHES in combination with INSTALL_MOD_STRIP,
this logc will also be used by Makefile.modfinal.
Move it to a shared location to enable reuse.
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
---
scripts/Makefile.lib | 32 ++++++++++++++++++++++++++++++++
scripts/Makefile.modinst | 37... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:29:00 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The signature splitting will also be used by CONFIG_MODULE_HASHES.
Move it up the callchain, so the result can be reused.
Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
---
kernel/module/internal.h | 2 +-
kernel/module/main.c | 13 ++++++++++++-
kernel/module/signing.c | 21 +++++++--------------
3 fi... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:56 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The upcoming module hashes functionality will build the modules in
between the generation of the BTF data and the final link of vmlinux.
Having a dependency from the modules on vmlinux would make this
impossible as it would mean having a cyclic dependency.
Break this cyclic dependency by introducing a new target.
Sign... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:50 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | {
"author": "=?utf-8?q?Thomas_Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Tue, 13 Jan 2026 13:28:59 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On 2026-01-13 13:28:59 [+0100], Thomas Weißschuh wrote:
…
This and a few other instances below could be optimized to avoid
hashing. I probably forgot to let you know.
-> https://git.kernel.org/pub/scm/linux/kernel/git/bigeasy/mtree-hashed-mods.git/commit/?id=10b565c123c731da37befe862de13678b7c54877
Sebastian | {
"author": "Sebastian Andrzej Siewior <bigeasy@linutronix.de>",
"date": "Tue, 13 Jan 2026 15:56:35 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On 1/13/26 1:28 PM, Thomas Weißschuh wrote:
The patch looks to modify the behavior when mangled_module is true.
Previously, module_sig_check() didn't attempt to extract the signature
in such a case and treated the module as unsigned. The err remained set
to -ENODATA and the function subsequently consulted module_sig_... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Tue, 27 Jan 2026 16:20:15 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On 1/13/26 1:28 PM, Thomas Weißschuh wrote:
I suggest moving the IS_ENABLED(CONFIG_MODULE_SIG) block under the
new IS_ENABLED(CONFIG_MODULE_SIG_POLICY) section. I realize that
CONFIG_MODULE_SIG implies CONFIG_MODULE_SIG_POLICY, but I believe this
change makes it more apparent that this it the case. Otherwise, one
migh... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Thu, 29 Jan 2026 15:41:43 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On 1/13/26 1:28 PM, Thomas Weißschuh wrote:
The new else branch means that if the user chooses not to configure any
module integrity policy, they will no longer be able to load any
modules. I think this entire if-else part should be moved under the
IS_ENABLED(CONFIG_MODULE_SIG_POLICY) block above, as I'm mentioning on... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Thu, 29 Jan 2026 15:44:31 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On 1/13/26 1:28 PM, Thomas Weißschuh wrote:
I wonder if this dependency cycle could be resolved by utilizing the
split into vmlinux.unstripped and vmlinux that occurred last year.
The idea is to create the following ordering: vmlinux.unstripped ->
modules -> vmlinux, and to patch in .module_hashes only when building
... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Fri, 30 Jan 2026 18:06:20 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Tue, Jan 13, 2026 at 01:28:46PM +0100, Thomas Weißschuh wrote:
Reviewed-by: Aaron Tomlin <atomlin@atomlin.com>
--
Aaron Tomlin | {
"author": "Aaron Tomlin <atomlin@atomlin.com>",
"date": "Fri, 30 Jan 2026 15:43:09 -0500",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Tue, Jan 13, 2026 at 01:28:47PM +0100, Thomas Weißschuh wrote:
Reviewed-by: Aaron Tomlin <atomlin@atomlin.com>
--
Aaron Tomlin | {
"author": "Aaron Tomlin <atomlin@atomlin.com>",
"date": "Fri, 30 Jan 2026 15:49:16 -0500",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Tue, Jan 13, 2026 at 01:28:48PM +0100, Thomas Weißschuh wrote:
Reviewed-by: Aaron Tomlin <atomlin@atomlin.com>
--
Aaron Tomlin | {
"author": "Aaron Tomlin <atomlin@atomlin.com>",
"date": "Fri, 30 Jan 2026 15:53:50 -0500",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packaging process much more complicated.
I think there is a middle ground whe... | {
"author": "=?UTF-8?q?Mihai-Drosi=20C=C3=A2ju?= <mcaju95@gmail.com>",
"date": "Sat, 31 Jan 2026 09:36:36 +0200",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | Hi Mihai-Drosi,
thanks for taking an interest into these patches!
On 2026-01-31 09:36:36+0200, Mihai-Drosi Câju wrote:
The goal is to make the distro kernel packages rebuildable by the
general public. Any involvement of secret values will break this goal.
I am not familiar with NixOS and its secret management.
Thi... | {
"author": "Thomas =?utf-8?Q?Wei=C3=9Fschuh?= <linux@weissschuh.net>",
"date": "Sun, 1 Feb 2026 17:22:12 +0100",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | Mihai-Drosi Câju <mcaju95@gmail.com> wrote:
There is another issue too: If you have a static private key that you use to
sign modules (and probably other things), someone will likely give you a GPL
request to get it.
One advantage of using a transient key every build and deleting it after is
that no one has the key.... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Sun, 01 Feb 2026 17:09:48 +0000",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Sun, Feb 01, 2026 at 05:09:48PM +0000, David Howells wrote:
It sounds like hash-based module authentication is just better, then.
If the full set of authentic modules is known at kernel build time, then
signatures are unnecessary to verify their authenticity: a list of
hashes built into the kernel image is perfectl... | {
"author": "Eric Biggers <ebiggers@kernel.org>",
"date": "Sun, 1 Feb 2026 12:12:18 -0800",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | Eric Biggers <ebiggers@kernel.org> wrote:
Because it's not just signing of modules and it's not just modules built with
the kernel. Also a hash table just of module hashes built into the core
kernel image will increase the size of the kernel by around a third of a meg
(on Fedora 43 and assuming SHA512) with uncompre... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 02 Feb 2026 09:21:19 +0000",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Mon, Feb 02, 2026 at 09:21:19AM +0000, David Howells wrote:
Module signing is indeed about the signing of modules.
Could you give more details on this use case and why it needs
signatures, as opposed to e.g. loading an additional Merkle tree root
into the kernel to add to the set of allowed modules?
This patchs... | {
"author": "Eric Biggers <ebiggers@kernel.org>",
"date": "Mon, 2 Feb 2026 10:30:55 -0800",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | Eric Biggers <ebiggers@kernel.org> wrote:
The signature verification stuff in the kernel isn't just used for modules.
kexec, for instance; wifi restriction database for another.
Because we don't want to, for example, include all the nvidia drivers in our
kernel SRPM.
David | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 02 Feb 2026 18:38:51 +0000",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 00/17] module: Introduce hash-based integrity checking | The current signature-based module integrity checking has some drawbacks
in combination with reproducible builds. Either the module signing key
is generated at build time, which makes the build unreproducible, or a
static signing key is used, which precludes rebuilds by third parties
and makes the whole build and packa... | On Mon, Feb 02, 2026 at 06:38:51PM +0000, David Howells wrote:
That doesn't answer my question. Are you trying to say these modules
need to be built later *and* signed using the original signing key?
- Eric | {
"author": "Eric Biggers <ebiggers@kernel.org>",
"date": "Mon, 2 Feb 2026 10:47:25 -0800",
"thread_id": "20260202184725.GC2036@quark.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Extend kvm_riscv_gstage_mode_detect() to probe all HGATP.MODE values
supported by the host and record them in a bitmask. Keep tracking the
maximum supported G-stage page table level for existing internal users.
Also provide lightweight helpers to retrieve the supported-mo... | {
"author": "fangyu.yu@linux.alibaba.com",
"date": "Mon, 2 Feb 2026 22:07:14 +0800",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Add a VM capability that allows userspace to select the G-stage page table
format by setting HGATP.MODE on a per-VM basis.
Userspace enables the capability via KVM_ENABLE_CAP, passing the requested
HGATP.MODE in args[0]. The request is rejected with -EINVAL if the mode is... | {
"author": "fangyu.yu@linux.alibaba.com",
"date": "Mon, 2 Feb 2026 22:07:15 +0800",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Define UAPI bit positions for the supported-mode bitmask returned by
KVM_CHECK_EXTENSION(KVM_CAP_RISCV_SET_HGATP_MODE).
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
arch/riscv/include/uapi/asm/kvm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arc... | {
"author": "fangyu.yu@linux.alibaba.com",
"date": "Mon, 2 Feb 2026 22:07:16 +0800",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Introduces one per-VM architecture-specific fields to support runtime
configuration of the G-stage page table format:
- kvm->arch.kvm_riscv_gstage_pgd_levels: the corresponding number of page
table levels for the selected mode.
These fields replace the previous global ... | {
"author": "fangyu.yu@linux.alibaba.com",
"date": "Mon, 2 Feb 2026 22:07:13 +0800",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | On Mon, Feb 02, 2026 at 10:07:14PM +0800, fangyu.yu@linux.alibaba.com wrote:
These should be defined in the UAPI, as I see the last patch of the series
does. No need to define them twice.
It seems like we're going out of our way to only provide the capability
for rv64. While the cap isn't useful for rv32, having #if... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 12:45:31 -0600",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH v4 0/4] Support runtime configuration for per-VM's HGATP mode | From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Currently, RISC-V KVM hardcodes the G-stage page table format (HGATP mode)
to the maximum mode detected at boot time (e.g., SV57x4 if supported). but
often such a wide GPA is unnecessary, just as a host sometimes doesn't need
sv57.
This patch introduces per-VM configurabi... | On Mon, Feb 02, 2026 at 10:07:15PM +0800, fangyu.yu@linux.alibaba.com wrote:
If we only want this to work for rv64, then we should write riscv64 here,
but, as I said in the last patch, I think we can just support rv32 too
by supporting its one and only mode.
We should write what happens if the capability (setting th... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 12:49:41 -0600",
"thread_id": "ftdnjnfvmybiskej3txd23mqn3jpjdewmgjxjbap3y4ekj4h4m@d74ihtpclyps.mbox.gz"
} |
lkml | [PATCH bpf-next] ftrace: Fix direct_functions leak in update_ftrace_direct_del | Alexei reported memory leak in update_ftrace_direct_del.
We miss cleanup of the replaced direct_functions in the
success path in update_ftrace_direct_del, adding that.
Fixes: 8d2c1233f371 ("ftrace: Add update_ftrace_direct_del function")
Reported-by: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Closes: https://lo... | On Mon, 2 Feb 2026 08:58:49 +0100
Jiri Olsa <jolsa@kernel.org> wrote:
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
-- Steve | {
"author": "Steven Rostedt <rostedt@kernel.org>",
"date": "Mon, 2 Feb 2026 09:55:15 -0500",
"thread_id": "202602030237.Ze7K6UoS-lkp@intel.com.mbox.gz"
} |
lkml | [PATCH bpf-next] ftrace: Fix direct_functions leak in update_ftrace_direct_del | Alexei reported memory leak in update_ftrace_direct_del.
We miss cleanup of the replaced direct_functions in the
success path in update_ftrace_direct_del, adding that.
Fixes: 8d2c1233f371 ("ftrace: Add update_ftrace_direct_del function")
Reported-by: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Closes: https://lo... | Hello:
This patch was applied to bpf/bpf-next.git (master)
by Alexei Starovoitov <ast@kernel.org>:
On Mon, 2 Feb 2026 08:58:49 +0100 you wrote:
Here is the summary with links:
- [bpf-next] ftrace: Fix direct_functions leak in update_ftrace_direct_del
https://git.kernel.org/bpf/bpf-next/c/6b95cc562de2
You are... | {
"author": "patchwork-bot+netdevbpf@kernel.org",
"date": "Mon, 02 Feb 2026 16:00:04 +0000",
"thread_id": "202602030237.Ze7K6UoS-lkp@intel.com.mbox.gz"
} |
lkml | [PATCH bpf-next] ftrace: Fix direct_functions leak in update_ftrace_direct_del | Alexei reported memory leak in update_ftrace_direct_del.
We miss cleanup of the replaced direct_functions in the
success path in update_ftrace_direct_del, adding that.
Fixes: 8d2c1233f371 ("ftrace: Add update_ftrace_direct_del function")
Reported-by: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Closes: https://lo... | Hi Jiri,
kernel test robot noticed the following build warnings:
[auto build test WARNING on bpf-next/master]
url: https://github.com/intel-lab-lkp/linux/commits/Jiri-Olsa/ftrace-Fix-direct_functions-leak-in-update_ftrace_direct_del/20260202-160850
base: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-n... | {
"author": "kernel test robot <lkp@intel.com>",
"date": "Tue, 3 Feb 2026 02:51:37 +0800",
"thread_id": "202602030237.Ze7K6UoS-lkp@intel.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common().
Reuse the already available local node pointer when mapping the ICU
register space.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-ren... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:32 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Make use of dev_err_probe() to simplify rzv2h_icu_probe_common().
Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for
allocation failures, ensuring they remain visible in logs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:34 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Use a local struct device pointer in rzv2h_icu_probe_common() to avoid
repeated dereferencing of pdev->dev.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++--------------
... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:33 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
that allows software to explicitly assert interrupts toward individual
CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
interrupt.
Introduce a debug mechanism to tr... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:35 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
ECC RAM, and CA55/IP error conditions during bring-up and debugging.
When debug support is enabled, register the error IRQ handler and
provide a debugfs write interface to trigger pseudo e... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:36 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Document the debugfs interface exported by the Renesas RZ/V2H ICU
driver to aid bring-up and debugging.
Describe the write-only swint and swpe files used to trigger software
and pseudo error interrupts.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:37 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
Just a question,
If the irq handler is meant for debugging/bring-up, can this irq handler activated only for debug session
instead of unconditionally enabling it?
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Thu, 22 Jan 2026 08:20:30 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Biju,
On Thu, Jan 22, 2026 at 8:20 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
The IRQ handler is registered only when `irq_renesas_rzv2h.debug=1` is
present in the bootargs.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Thu, 22 Jan 2026 09:18:52 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
Thanks for clarification.
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Thu, 22 Jan 2026 09:26:00 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
On Wed, 21 Jan 2026 at 16:01, Prabhakar <prabhakar.csengg@gmail.com> wrote:
Thanks for your patch!
[...]
drivers/irqchip/irq-renesas-rzv2h.c:730:23: error: implicit
declaration of function ‘devm_request_irq’; did you mean
‘can_request_irq’? [-Werror=implicit-function-declaration]
How does this buil... | {
"author": "Geert Uytterhoeven <geert@linux-m68k.org>",
"date": "Fri, 23 Jan 2026 11:45:19 +0100",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Geert,
Thank you for the review.
On Fri, Jan 23, 2026 at 10:45 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
While posting the patches, I had rebased them on next-20260119 (and
used defconfig), but I didn't see any build issues. Below is the
snippet from irq-renesas-rzv2h.i:
struct ns_common;
int open_relat... | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Fri, 23 Jan 2026 11:24:08 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
Can't you reuse/extend the existing mechanism provided by
CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
instead of implementing yet another ad hoc debugfs magic?
Thanks,
tglx | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Mon, 26 Jan 2026 17:03:49 +0100",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
Why is that only relevant to bring-up and debugging? Those errors
can't happen in production, right?
Thanks,
tglx | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Mon, 26 Jan 2026 17:11:47 +0100",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
Thank you for the feedback.
On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
Can you please point me to a driver which makes use of it? In my case
the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
ICU_SWINT.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Thu, 29 Jan 2026 21:24:02 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
Care to look what irq_inject_interrupt() does?
It tries first to inject the interrupt via irq_set_irqchip_state(),
which only works when a chip in the hierarchy implements the
chip::irq_set_irqchip_state() callback.
If that fails, it uses the resend mechanism, which... | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Thu, 29 Jan 2026 22:59:05 +0100",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
On Thu, Jan 29, 2026 at 9:59 PM Thomas Gleixner <tglx@kernel.org> wrote:
I did implement irq_set_irqchip_state but it doesn't land in the
rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed
something.
#Trigger int-ca55-0
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14
#The trace... | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Fri, 30 Jan 2026 11:17:08 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Fri, Jan 30 2026 at 11:17, Lad, Prabhakar wrote:
...
Correct. That's how the hierarchy works. | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Fri, 30 Jan 2026 15:52:38 +0100",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
On Mon, Jan 26, 2026 at 4:11 PM Thomas Gleixner <tglx@kernel.org> wrote:
The error conditions can happen in production too. So I'll enable them
by default and drop the debug module param.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Mon, 2 Feb 2026 19:02:33 +0000",
"thread_id": "20260121150137.3364865-1-prabhakar.mahadev-lad.rj@bp.renesas.com.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | From: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
Rename mshv_synic_init() to mshv_synic_cpu_init() and
mshv_synic_cleanup() to mshv_synic_cpu_exit() to better reflect that
these functions handle per-cpu synic setup and teardown.
Use mshv_synic_init/cleanup() to perform init/cleanup that is not per-cpu.
Mo... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Mon, 2 Feb 2026 18:27:05 +0000",
"thread_id": "aYD15RxUIoGDJCv5@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | From: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hypervi... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Mon, 2 Feb 2026 18:27:06 +0000",
"thread_id": "aYD15RxUIoGDJCv5@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | On Mon, Feb 02, 2026 at 06:27:05PM +0000, Anirudh Rayabharam wrote:
Unrelated to the change, but it would be great to get rid of this
notifier altogether and just do the cleanup in the device shutdown hook.
This is a cleaner approach as this is a device driver and we do have the
device in hands.
Do you think you could... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 2 Feb 2026 11:07:17 -0800",
"thread_id": "aYD15RxUIoGDJCv5@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Fri, Jan 23, 2026 at 04:03:53PM +0000, James Clark wrote:
Makes sense.
The isb() in the interrupt handler is useful and should not be removed.
See the sequence in the interrupt handler:
arm_spe_perf_aux_output_begin() {
write_sysreg_s(base, SYS_PMBPTR_EL1);
// Ensure the write pointer is or... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Fri, 30 Jan 2026 20:24:37 +0000",
"thread_id": "aYD08d42SewAAQCB@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Fri, Jan 30, 2026 at 08:24:37PM +0000, Leo Yan wrote:
Oh nice, since when was it ok to relax the architecture and break
existing drivers that were perfectly fine before? The SPE spec's not
worth the paper it's written on...
Anyway, we're not changing the driver without a comment next to the new
isb() explaining th... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 16:53:57 +0000",
"thread_id": "aYD08d42SewAAQCB@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Mon, Feb 02, 2026 at 04:53:57PM +0000, Will Deacon wrote:
[...]
I think the ISB after arm_spe_perf_aux_output_begin() in the irq
handler is required for both the failure and success cases.
For a normal maintenance interrupt, an ISB is inserted between writing
PMBLIMITR_EL1 and PMBSR_EL1 to ensure that a valid li... | {
"author": "Leo Yan <leo.yan@arm.com>",
"date": "Mon, 2 Feb 2026 18:42:34 +0000",
"thread_id": "aYD08d42SewAAQCB@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Mon, Feb 02, 2026 at 06:42:34PM +0000, Leo Yan wrote:
Hmm, so let's say we've executed the first ISB. At that point, the
Profiling Buffer is disabled (PMBLIMITR_EL1.E = 0) and profiling is
stopped (PMBSR_EL1.S = 1). If we *don't* have the second ISB then either
PMBLIMITR_EL1 is written first or PMBSR_EL1 is written... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 18:57:11 +0000",
"thread_id": "aYD08d42SewAAQCB@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] perf: arm_spe: Add barrier before enabling profiling
buffer | The Arm ARM known issues document [1] states that the architecture will
be relaxed so that the profiling buffer must be correctly configured
when ProfilingBufferEnabled() && !SPEProfilingStopped() &&
PMBLIMITR_EL1.FM != DISCARD:
R24557
While the Profiling Buffer is enabled, profiling is not stopped, and
Discard... | On Fri, Jan 23, 2026 at 04:03:53PM +0000, James Clark wrote:
Thinking about this some more, does that mean that the direct write to
PMBPTR_EL1 performs an indirect read of PMBLIMITR_EL1 so that it can
determine the write-ignore semantics? If so, doesn't that mean that
we'll get order against a subsequent direct write ... | {
"author": "Will Deacon <will@kernel.org>",
"date": "Mon, 2 Feb 2026 19:03:13 +0000",
"thread_id": "aYD08d42SewAAQCB@willie-the-truck.mbox.gz"
} |
lkml | [PATCH] rtmutex: Introduce __cleanup() based infrastructure | Commit 54da6a092431 ("locking: Introduce __cleanup() based
infrastructure") introduced lock guards for mutexes in
include/linux/mutex.h, but, presumably as PREEMPT_RT wasn't merged at
the time, the guard for rt_mutex was never created. Do this now so this
infrastructure exists for rt_mutex as well.
Signed-off-by: Thom... | On 2026-02-02 18:04:43 [+0100], Thomas Böhler wrote:
Wait, what? rt_mutex can be used independently of PREEMPT_RT.
I suggest you focus on what this patch does in its description and
repost it with the locking maintainer in Cc.
Do you plan to have any users of this?
Sebastian | {
"author": "Sebastian Andrzej Siewior <bigeasy@linutronix.de>",
"date": "Mon, 2 Feb 2026 18:58:40 +0100",
"thread_id": "DG4PGZN9OM5B.301RXEQEIVB7@wiredspace.de.mbox.gz"
} |
lkml | [PATCH] rtmutex: Introduce __cleanup() based infrastructure | Commit 54da6a092431 ("locking: Introduce __cleanup() based
infrastructure") introduced lock guards for mutexes in
include/linux/mutex.h, but, presumably as PREEMPT_RT wasn't merged at
the time, the guard for rt_mutex was never created. Do this now so this
infrastructure exists for rt_mutex as well.
Signed-off-by: Thom... | On Mon Feb 2, 2026 at 6:58 PM CET, Sebastian Andrzej Siewior wrote:
I wasn't aware of that, sorry for the confusion. I'm still pretty
new to the Linux Kernel; my assumption was wrong here.
Thanks, I'll do that for a potential v2!
No. I discovered this was "missing" while developing out-of-tree. I'm
aware that an i... | {
"author": "=?utf-8?q?Thomas_B=C3=B6hler?= <witcher@wiredspace.de>",
"date": "Mon, 02 Feb 2026 19:59:43 +0100",
"thread_id": "DG4PGZN9OM5B.301RXEQEIVB7@wiredspace.de.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Avoid dereferencing pdev->dev.of_node again in rzv2h_icu_probe_common().
Reuse the already available local node pointer when mapping the ICU
register space.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-ren... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:32 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Make use of dev_err_probe() to simplify rzv2h_icu_probe_common().
Keep dev_err() for -ENOMEM paths, as dev_err_probe() does not print for
allocation failures, ensuring they remain visible in logs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:34 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Use a local struct device pointer in rzv2h_icu_probe_common() to avoid
repeated dereferencing of pdev->dev.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/irqchip/irq-renesas-rzv2h.c | 29 +++++++++++++++--------------
... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:33 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
that allows software to explicitly assert interrupts toward individual
CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
interrupt.
Introduce a debug mechanism to tr... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:35 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Handle the RZ/V2H ICU error interrupt to help diagnose latched bus,
ECC RAM, and CA55/IP error conditions during bring-up and debugging.
When debug support is enabled, register the error IRQ handler and
provide a debugfs write interface to trigger pseudo e... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:36 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Document the debugfs interface exported by the Renesas RZ/V2H ICU
driver to aid bring-up and debugging.
Describe the write-only swint and swpe files used to trigger software
and pseudo error interrupts.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.... | {
"author": "Prabhakar <prabhakar.csengg@gmail.com>",
"date": "Wed, 21 Jan 2026 15:01:37 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
Just a question,
If the irq handler is meant for debugging/bring-up, can this irq handler activated only for debug session
instead of unconditionally enabling it?
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Thu, 22 Jan 2026 08:20:30 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Biju,
On Thu, Jan 22, 2026 at 8:20 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
The IRQ handler is registered only when `irq_renesas_rzv2h.debug=1` is
present in the bootargs.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Thu, 22 Jan 2026 09:18:52 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
Thanks for clarification.
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Thu, 22 Jan 2026 09:26:00 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Prabhakar,
On Wed, 21 Jan 2026 at 16:01, Prabhakar <prabhakar.csengg@gmail.com> wrote:
Thanks for your patch!
[...]
drivers/irqchip/irq-renesas-rzv2h.c:730:23: error: implicit
declaration of function ‘devm_request_irq’; did you mean
‘can_request_irq’? [-Werror=implicit-function-declaration]
How does this buil... | {
"author": "Geert Uytterhoeven <geert@linux-m68k.org>",
"date": "Fri, 23 Jan 2026 11:45:19 +0100",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Geert,
Thank you for the review.
On Fri, Jan 23, 2026 at 10:45 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
While posting the patches, I had rebased them on next-20260119 (and
used defconfig), but I didn't see any build issues. Below is the
snippet from irq-renesas-rzv2h.i:
struct ns_common;
int open_relat... | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Fri, 23 Jan 2026 11:24:08 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
Can't you reuse/extend the existing mechanism provided by
CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
instead of implementing yet another ad hoc debugfs magic?
Thanks,
tglx | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Mon, 26 Jan 2026 17:03:49 +0100",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
Why is that only relevant to bring-up and debugging? Those errors
can't happen in production, right?
Thanks,
tglx | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Mon, 26 Jan 2026 17:11:47 +0100",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
Thank you for the feedback.
On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@kernel.org> wrote:
Can you please point me to a driver which makes use of it? In my case
the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
ICU_SWINT.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Thu, 29 Jan 2026 21:24:02 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Thu, Jan 29 2026 at 21:24, Prabhakar Lad wrote:
Care to look what irq_inject_interrupt() does?
It tries first to inject the interrupt via irq_set_irqchip_state(),
which only works when a chip in the hierarchy implements the
chip::irq_set_irqchip_state() callback.
If that fails, it uses the resend mechanism, which... | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Thu, 29 Jan 2026 22:59:05 +0100",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
On Thu, Jan 29, 2026 at 9:59 PM Thomas Gleixner <tglx@kernel.org> wrote:
I did implement irq_set_irqchip_state but it doesn't land in the
rzv2h_icu_irq_set_irqchip_state(). So I was wondering if I missed
something.
#Trigger int-ca55-0
root@rzv2h-evk:/sys/kernel/debug/irq/irqs# echo trigger > 14
#The trace... | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Fri, 30 Jan 2026 11:17:08 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | On Fri, Jan 30 2026 at 11:17, Lad, Prabhakar wrote:
...
Correct. That's how the hierarchy works. | {
"author": "Thomas Gleixner <tglx@kernel.org>",
"date": "Fri, 30 Jan 2026 15:52:38 +0100",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/6] irqchip/renesas-rzv2h: Add support to handle ICU error IRQ and add SWPE trigger | From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This patch series aims to enhance the Renesas RZ/V2H ICU irqchip driver by
adding support to handle ICU error IRQs and introducing a
software-generated interrupt (SWPE) trigger. The series includes the
following changes:
- Use local pointers for de... | Hi Thomas,
On Mon, Jan 26, 2026 at 4:11 PM Thomas Gleixner <tglx@kernel.org> wrote:
The error conditions can happen in production too. So I'll enable them
by default and drop the debug module param.
Cheers,
Prabhakar | {
"author": "\"Lad, Prabhakar\" <prabhakar.csengg@gmail.com>",
"date": "Mon, 2 Feb 2026 19:02:33 +0000",
"thread_id": "CA+V-a8s+wqRainda_J2uBbaoYO99OSgOp+LcpMe+5G+JLV8C_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH] gfs2: fix memory leaks in gfs2_fill_super error path | Fix two memory leaks in the gfs2_fill_super() error handling path when
transitioning a filesystem to read-write mode fails.
First leak: kthread objects (thread_struct, task_struct, etc.)
When gfs2_freeze_lock_shared() fails after init_threads() succeeds,
the created kernel threads (logd and quotad) are never destroyed... | Hello Deepanshu,
thanks for this patch; see below.
On Sat, Jan 31, 2026 at 7:25 AM Deepanshu Kartikey
<kartikey406@gmail.com> wrote:
This isn't pretty. Can it be replaced by the following?
--- a/fs/gfs2/super.c
+++ b/fs/gfs2/super.c
@@ -147,8 +147,10 @@ int gfs2_make_fs_rw(struct gfs2_sbd *sdp)
}
e... | {
"author": "Andreas Gruenbacher <agruenba@redhat.com>",
"date": "Mon, 2 Feb 2026 19:57:06 +0100",
"thread_id": "CAHc6FU5=rG-GaSnHsU2aUO83i8zNpsYDyryuenJzRov64BsQ_g@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH net-next v2] net: bridge: use sysfs_emit instead of sprintf | Replace sprintf with sysfs_emit in sysfs show() methods as outlined in
Documentation/filesystems/sysfs.rst.
sysfs_emit is preferred to sprintf in sysfs show() methods as it is safer
with buffer handling.
Signed-off-by: David Corvaglia <david@corvaglia.dev>
---
v2: Fix alignment of sysfs_emit arguments.
v1: https://lo... | On Mon, Feb 02, 2026 at 07:07:12AM +0000, David Corvaglia wrote:
I get:
$ b4 shazam -k 0100019c1d2d46e0-a083f912-ac82-47e8-8cbb-ac9d70355ed3-000000@email.amazonses.com
[...]
● checkpatch.pl: 392: ERROR: code indent should use tabs where possible
[...]
$ scripts/checkpatch.pl -g HEAD
ERROR: code indent should use... | {
"author": "Ido Schimmel <idosch@nvidia.com>",
"date": "Mon, 2 Feb 2026 19:44:09 +0200",
"thread_id": "0100019c1fbca989-a2726974-1033-4468-bd63-a5c306949e37-000000@email.amazonses.com.mbox.gz"
} |
lkml | [PATCH net-next v2] net: bridge: use sysfs_emit instead of sprintf | Replace sprintf with sysfs_emit in sysfs show() methods as outlined in
Documentation/filesystems/sysfs.rst.
sysfs_emit is preferred to sprintf in sysfs show() methods as it is safer
with buffer handling.
Signed-off-by: David Corvaglia <david@corvaglia.dev>
---
v2: Fix alignment of sysfs_emit arguments.
v1: https://lo... | Hi Ido,
Will fix the whitespace issue and send v3 soon. Thanks for the review, sorry about that.
Best,
David Corvaglia | {
"author": "David Corvaglia <david@corvaglia.dev>",
"date": "Mon, 2 Feb 2026 19:03:03 +0000",
"thread_id": "0100019c1fbca989-a2726974-1033-4468-bd63-a5c306949e37-000000@email.amazonses.com.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Am Freitag, 30. Januar 2026, 09:41:31 CET schrieb ming.qian@oss.nxp.com:
If I read the Datasheet correctly 600 MHz is only supported by overdrive
mode (also depending on the VDD_VPU).
Is this frequency really correct?
Best regards,
Alexander | {
"author": "Alexander Stein <alexander.stein@ew.tq-group.com>",
"date": "Fri, 30 Jan 2026 10:09:46 +0100",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Hi,
Le vendredi 30 janvier 2026 à 16:41 +0800, ming.qian@oss.nxp.com a écrit :
Tested on EVK, with the downstream DCSS driver, and this change triggers DCSS
underrun (which is related to the DRAM QoS erratas on this SoC). It also
sometimes trigger the "not all macroblock decoded" warning I added recently, and
we can ... | {
"author": "Nicolas Dufresne <nicolas@ndufresne.ca>",
"date": "Fri, 30 Jan 2026 09:47:34 -0500",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | On Fri, Jan 30, 2026 at 10:09:46AM +0100, Alexander Stein wrote:
G1 and BUS clk were already set as Overdrive frequency.
This change is to only upgrading G2 from 300M to 600M.
So if your question is should we downgrade all to Nominal mode, I think
no. The freq could be override in board dts, or adding a new dts
as a... | {
"author": "Peng Fan <peng.fan@oss.nxp.com>",
"date": "Mon, 2 Feb 2026 10:41:49 +0800",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Hi Alexander，
On 2/2/2026 10:41 AM, Peng Fan wrote:
Yes, you are right, 600MHz is the Overdriver frequency.
However, to achieve the 4K 60fps target, we set the VPU to run in
overdrive mode by default, just as Peng said.
Regards,
Ming | {
"author": "\"Ming Qian(OSS)\" <ming.qian@oss.nxp.com>",
"date": "Mon, 2 Feb 2026 13:56:47 +0800",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Hi Nicolas,
On 1/30/2026 10:47 PM, Nicolas Dufresne wrote:
This doesn't sound like just a VPU issue; it's related to the display or
DDR.
If not displayed, do the fluster test cases yield different results at
600MHz and 300MHz?
My display is hdmi, I'll try the DCSS.
And the DDR bandwidth results measured by perf a... | {
"author": "\"Ming Qian(OSS)\" <ming.qian@oss.nxp.com>",
"date": "Mon, 2 Feb 2026 15:44:37 +0800",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Le lundi 02 février 2026 à 15:44 +0800, Ming Qian(OSS) a écrit :
Didn't you run these tests before sending ? I can try again, but in my internal
notes, I wrote:
> Tested that, and everything becomes unstable
That was before I figure-out the IRQ handler didn't handle exception bits that
didn't stop the decoder (or ... | {
"author": "Nicolas Dufresne <nicolas@ndufresne.ca>",
"date": "Mon, 02 Feb 2026 13:44:28 -0500",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for 4K60fps decoding | From: Ming Qian <ming.qian@oss.nxp.com>
The VPU G2 clock was reduced from 600MHz to 300MHz in commit
b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
pixel errors with high-resolution HEVC postprocessor output.
However, testing shows the 300MHz clock rate is insufficient for
4K60fps decoding and th... | Hi,
Le lundi 02 février 2026 à 13:44 -0500, Nicolas Dufresne a écrit :
Ran some fluster tests now. With this patch the results is not consistent
anymore. Then I ran it with weston being started, and in the middle of the test
the display turned black. Matches my past observation. We did reproduce this on
BSP kernel to... | {
"author": "Nicolas Dufresne <nicolas@ndufresne.ca>",
"date": "Mon, 02 Feb 2026 14:12:54 -0500",
"thread_id": "5e3431c69da07557edb20a252c4759be8c857f08.camel@ndufresne.ca.mbox.gz"
} |
lkml | [GIT PULL] ASPEED clk updates for v6.20 | Hi Stephen,
Please pull the following ASPEED clock driver updates for v6.20.
The series includes:
- Reorganization of ASPEED clock drivers under drivers/clk/aspeed/
- MAINTAINERS updates for ASPEED clock drivers
- New ASPEED clock driver support
The branch is based on v6.19-rc1 as requested.
Thanks,
Billy
-------... | Quoting Billy Tsai (2026-01-28 19:36:24)
Thanks. Pulled into clk-next | {
"author": "Stephen Boyd <sboyd@kernel.org>",
"date": "Mon, 02 Feb 2026 12:13:27 -0700",
"thread_id": "177005960797.4027.14390177024032129085@lazor.mbox.gz"
} |
lkml | [PATCH 1/2] dt-bindings: arm: fsl: Add Gateworks GW7906 board | Add support for the Gateworks GW7906 board based on the
i.MX8M Mini SoC.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.y... | The GW7906 is based on the i.MX8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- software selectable RS232/RS485/RS422 serial transceiver
- PMIC
- 1x isolated RS232 UART
- 1x off-board bi-direction... | {
"author": "Tim Harvey <tharvey@gateworks.com>",
"date": "Mon, 2 Feb 2026 10:10:29 -0800",
"thread_id": "aYD4BwB3McK45vCk@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 1/2] dt-bindings: arm: fsl: Add Gateworks GW7906 board | Add support for the Gateworks GW7906 board based on the
i.MX8M Mini SoC.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.y... | On Mon, Feb 02, 2026 at 10:10:29AM -0800, Tim Harvey wrote:
Any difference with gateworks,imx8mm-gw7904? Can reuse existed file?
Please run https://github.com/lznuaa/dt-format for new dts to keep nice
node order,
If output result is not good enough, let know
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Mon, 2 Feb 2026 14:16:23 -0500",
"thread_id": "aYD4BwB3McK45vCk@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | From: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
Rename mshv_synic_init() to mshv_synic_cpu_init() and
mshv_synic_cleanup() to mshv_synic_cpu_exit() to better reflect that
these functions handle per-cpu synic setup and teardown.
Use mshv_synic_init/cleanup() to perform init/cleanup that is not per-cpu.
Mo... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Mon, 2 Feb 2026 18:27:05 +0000",
"thread_id": "aYD3XvbrOhH3NNP_@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | From: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hypervi... | {
"author": "Anirudh Rayabharam <anirudh@anirudhrb.com>",
"date": "Mon, 2 Feb 2026 18:27:06 +0000",
"thread_id": "aYD3XvbrOhH3NNP_@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | On Mon, Feb 02, 2026 at 06:27:05PM +0000, Anirudh Rayabharam wrote:
Unrelated to the change, but it would be great to get rid of this
notifier altogether and just do the cleanup in the device shutdown hook.
This is a cleaner approach as this is a device driver and we do have the
device in hands.
Do you think you could... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 2 Feb 2026 11:07:17 -0800",
"thread_id": "aYD3XvbrOhH3NNP_@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v2 0/2] ARM64 support for doorbell and intercept SINTs | From: "Anirudh Rayabharam (Microsoft)" <anirudh@anirudhrb.com>
On x86, the HYPERVISOR_CALLBACK_VECTOR is used to receive synthetic
interrupts (SINTs) from the hypervisor for doorbells and intercepts.
There is no such vector reserved for arm64.
On arm64, the INTID for SINTs should be in the SGI or PPI range. The
hyper... | On Mon, Feb 02, 2026 at 06:27:06PM +0000, Anirudh Rayabharam wrote:
You have introduced 4 ifdef branches (one aroung the variable and three
in mshv_synic_cpu_init) and then you still have a big ifdef branch here.
Why is it better than simply introducing two different
mshv_synic_cpu_init functions and have a single bi... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 2 Feb 2026 11:13:34 -0800",
"thread_id": "aYD3XvbrOhH3NNP_@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH bpf] bpf, sockmap: Fix af_unix null-ptr-deref in proto
update | BPF_MAP_UPDATE_ELEM races unix_stream_connect(): when
sock_map_sk_state_allowed() passes (sk_state == TCP_ESTABLISHED),
unix_peer(sk) in unix_stream_bpf_update_proto() may still return NULL.
T0 bpf T1 connect
------ ----------
WRITE_ONCE(sk->sk_state, TCP_ESTABLISHED)
sock_map_sk_state_allowed(sk)
...
sk_... | On 1/29/26 8:47 AM, Michal Luczaj wrote:
It is a long thread to dig. Please summarize the discussion in the
commit message.
From looking at this commit message, if the existing lock_sock held by
update_elem is not useful for af_unix, it is not clear why a new test
"!sk_pair" on top of the existing WRITE_ONCE(sk->... | {
"author": "Martin KaFai Lau <martin.lau@linux.dev>",
"date": "Thu, 29 Jan 2026 11:41:17 -0800",
"thread_id": "7603c0e6-cd5b-452b-b710-73b64bd9de26@linux.dev.mbox.gz"
} |
lkml | [PATCH bpf] bpf, sockmap: Fix af_unix null-ptr-deref in proto
update | BPF_MAP_UPDATE_ELEM races unix_stream_connect(): when
sock_map_sk_state_allowed() passes (sk_state == TCP_ESTABLISHED),
unix_peer(sk) in unix_stream_bpf_update_proto() may still return NULL.
T0 bpf T1 connect
------ ----------
WRITE_ONCE(sk->sk_state, TCP_ESTABLISHED)
sock_map_sk_state_allowed(sk)
...
sk_... | On 1/29/26 20:41, Martin KaFai Lau wrote:
OK, there we go:
The root cause of the null-ptr-deref is that unix_stream_connect() sets
sk_state (`WRITE_ONCE(sk->sk_state, TCP_ESTABLISHED)`) _before_ it assigns
a peer (`unix_peer(sk) = newsk`). sk_state == TCP_ESTABLISHED makes
sock_map_sk_state_allowed() believe that soc... | {
"author": "Michal Luczaj <mhal@rbox.co>",
"date": "Fri, 30 Jan 2026 12:00:09 +0100",
"thread_id": "7603c0e6-cd5b-452b-b710-73b64bd9de26@linux.dev.mbox.gz"
} |
lkml | [PATCH bpf] bpf, sockmap: Fix af_unix null-ptr-deref in proto
update | BPF_MAP_UPDATE_ELEM races unix_stream_connect(): when
sock_map_sk_state_allowed() passes (sk_state == TCP_ESTABLISHED),
unix_peer(sk) in unix_stream_bpf_update_proto() may still return NULL.
T0 bpf T1 connect
------ ----------
WRITE_ONCE(sk->sk_state, TCP_ESTABLISHED)
sock_map_sk_state_allowed(sk)
...
sk_... | On 1/30/26 3:00 AM, Michal Luczaj wrote:
It sounds like lock_sock is the incorrect lock to hold for af_unix. Is
taking lock_sock in sock_map doing anything useful for af_unix? Should
sock_map hold the unix_state_lock instead of lock_sock?
Other than update_elem, do other lock_sock() usages in sock_map have a
simil... | {
"author": "Martin KaFai Lau <martin.lau@linux.dev>",
"date": "Fri, 30 Jan 2026 13:29:44 -0800",
"thread_id": "7603c0e6-cd5b-452b-b710-73b64bd9de26@linux.dev.mbox.gz"
} |
lkml | [PATCH bpf] bpf, sockmap: Fix af_unix null-ptr-deref in proto
update | BPF_MAP_UPDATE_ELEM races unix_stream_connect(): when
sock_map_sk_state_allowed() passes (sk_state == TCP_ESTABLISHED),
unix_peer(sk) in unix_stream_bpf_update_proto() may still return NULL.
T0 bpf T1 connect
------ ----------
WRITE_ONCE(sk->sk_state, TCP_ESTABLISHED)
sock_map_sk_state_allowed(sk)
...
sk_... | On Fri, Jan 30, 2026 at 1:30 PM Martin KaFai Lau <martin.lau@linux.dev> wrote:
Yes, we already have a memory barrier for unix_peer(sk) there
(to save sock_hold()/sock_put() in sendmsg(), see 830a1e5c212fb)
and another one just for sk->sk_state is not worth the unlikely
case in sockmap by a buggy user.
If a user hit... | {
"author": "Kuniyuki Iwashima <kuniyu@google.com>",
"date": "Sat, 31 Jan 2026 02:06:04 -0800",
"thread_id": "7603c0e6-cd5b-452b-b710-73b64bd9de26@linux.dev.mbox.gz"
} |
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