source large_stringclasses 2
values | subject large_stringclasses 112
values | code large_stringclasses 112
values | critique large_stringlengths 61 3.04M ⌀ | metadata dict |
|---|---|---|---|---|
lkml | [PATCH v0 00/15] PCI passthru on Hyper-V (Part I) | From: Mukesh Rathor <mrathor@linux.microsoft.com>
Implement passthru of PCI devices to unprivileged virtual machines
(VMs) when Linux is running as a privileged VM on Microsoft Hyper-V
hypervisor. This support is made to fit within the workings of VFIO
framework, and any VMM needing to use it must use the VFIO subsyst... | On Fri, Jan 30, 2026 at 02:17:24PM -0800, Mukesh R wrote:
So, are you saying that the hypervisor does not use these pages and only
tracks them? That would make things easier.
However, if we later try to map a GPA that is already mapped, will the
hypervisor return an error?
Thanks,
Stanislav | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 2 Feb 2026 08:30:49 -0800",
"thread_id": "aYDO1S3DdUSHNkEY@skinsburskii.localdomain.mbox.gz"
} |
lkml | [PATCH v5] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, and the shared memory size
to be at least 64 bytes.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ext_sta_set_re... | On Mon, Feb 02, 2026 at 12:38:57AM +0000, Jiakai Xu wrote:
Any reason not to add these tests to
tools/testing/selftests/kvm/steal_time.c in the linux repo?
Sorry I missed this on my first review, but new_shmem should be
initialized to INVALID_GPA, since zero is a valid gpa.
And then here check 'new_shmem != INVALI... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 10:25:08 -0600",
"thread_id": "h5ywmsqp2eysyslvh7zmuiw3mzthkiilgqv4gvjvpl6nejxs7m@ahjmnsz2c2x3.mbox.gz"
} |
lkml | [PATCH v5] RISC-V: KVM: Validate SBI STA shmem alignment in kvm_sbi_ext_sta_set_reg() | The RISC-V SBI Steal-Time Accounting (STA) extension requires the shared
memory physical address to be 64-byte aligned, and the shared memory size
to be at least 64 bytes.
KVM exposes the SBI STA shared memory configuration to userspace via
KVM_SET_ONE_REG. However, the current implementation of
kvm_sbi_ext_sta_set_re... | On Mon, Feb 02, 2026 at 12:38:57AM +0000, Jiakai Xu wrote:
...
A procedure comment is that you don't need to send a new revision for each
change as comments come in or as you think of them yourself. You should
leave a revision on the list long enough to collect comments from multiple
reviewers (including yourself) and... | {
"author": "Andrew Jones <andrew.jones@oss.qualcomm.com>",
"date": "Mon, 2 Feb 2026 10:31:29 -0600",
"thread_id": "h5ywmsqp2eysyslvh7zmuiw3mzthkiilgqv4gvjvpl6nejxs7m@ahjmnsz2c2x3.mbox.gz"
} |
lkml | [GIT PULL] lsm/lsm-pr-20260202 | Hi Linus,
A small LSM patch to address a regression found in the v6.19-rcX releases
where the /proc/sys/vm/mmap_min_addr tunable disappeared when
CONFIG_SECURITY was not selected. Long term we plan to work with the MM
folks to get the core parts of this moved over to the MM subsystem, but
in the meantime we need to f... | On Mon, Feb 2, 2026 at 12:37 PM Paul Moore <paul@paul-moore.com> wrote:
I forgot to add, you'll notice a forced push on that branch, but that
was simply to add some additional reviewed-by/tested-by tags this
morning that I thought were worthwhile given we are currently at -rc8.
--
paul-moore.com | {
"author": "Paul Moore <paul@paul-moore.com>",
"date": "Mon, 2 Feb 2026 12:39:08 -0500",
"thread_id": "CAHC9VhR80ZipmG8PGTdfvY-GpUsvX_UzND-XV6s844hbmO3BTw@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add verify-only public key crypto support for ML-DSA so that the
X.509/PKCS#7 signature verification code, as used by module signing,
amongst other things, can make use of it through the common crypto_sig API.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Eric ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:06 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Calculate the SHA256 hash for blacklisting purposes independently of the
signature hash (which may be something other than SHA256).
This is necessary because when ML-DSA is used, no digest is calculated.
Note that this represents a change of behaviour in that the hash used for
the blacklist check would previously hav... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:07 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Rename ->digest and ->digest_len to ->m and ->m_size to represent the input
to the signature verification algorithm, reflecting that ->digest may no
longer actually *be* a digest.
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org>
cc: Lukas Wunner <lukas@wunner.de>
cc: ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:08 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the data to be verified in a PKCS#7 or CMS message to be passed
directly to an asymmetric cipher algorithm (e.g. ML-DSA) if it wants to do
whatever passes for hashing/digestion itself. The normal digestion of the
data is then skipped as that would be ignored unless another signed info in
the message has some oth... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:09 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Add support for ML-DSA keys and signatures to the CMS/PKCS#7 and X.509
implementations. ML-DSA-44, -65 and -87 are all supported. For X.509
certificates, the TBSCertificate is required to be signed directly; for
CMS, direct signing of the data is preferred, though use of SHA512 (and
only that) as an intermediate hash... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:10 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow ML-DSA module signing to be enabled.
Note that OpenSSL's CMS_*() function suite does not, as of OpenSSL-3.6,
support the use of CMS_NOATTR with ML-DSA, so the prohibition against using
signedAttrs with module signing has to be removed. The selected digest
then applies only to the algorithm used to calculate the... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:11 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v16 0/7] x509, pkcs7, crypto: Add ML-DSA signing | Hi Lukas, Ignat,
[Note this is based on Eric Bigger's libcrypto-next branch].
These patches add ML-DSA module signing signing:
(1) Add a crypto_sig interface for ML-DSA, verification only.
(2) Generate a SHA256 hash of the X.509 TBSCertificate and check that in
the blacklist. Direct-sign ML-DSA doesn't gene... | Allow the rejection of authenticatedAttributes in PKCS#7 (signedAttrs in
CMS) to be waived in the kernel config for ML-DSA when used for module
signing. This reflects the issue that openssl < 4.0 cannot do this and
openssl-4 has not yet been released.
This does not permit RSA, ECDSA or ECRDSA to be so waived (behavio... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 2 Feb 2026 17:02:12 +0000",
"thread_id": "20260202170216.2467036-1-dhowells@redhat.com.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Replace direct comparisons of hv_result(status) against
HV_STATUS_INSUFFICIENT_MEMORY with a new hv_result_needs_memory() helper
function.
This improves code readability and provides a consistent and extendable
interface for checking out-of-memory conditions in hypercall results.
No functional changes intended.
Signe... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:58:57 +0000",
"thread_id": "177005515446.120041.8169777750859263202.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | Introduce hv_deposit_memory_node() and hv_deposit_memory() helper
functions to handle memory deposition with proper error handling.
The new hv_deposit_memory_node() function takes the hypervisor status
as a parameter and validates it before depositing pages. It checks for
HV_STATUS_INSUFFICIENT_MEMORY specifically and... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:03 +0000",
"thread_id": "177005515446.120041.8169777750859263202.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | The HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY status indicates that the
hypervisor lacks sufficient contiguous memory for its internal allocations.
When this status is encountered, allocate and deposit
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES contiguous pages to the hypervisor.
HV_MAX_CONTIGUOUS_ALLOCATION_PAGES is defined i... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:09 +0000",
"thread_id": "177005515446.120041.8169777750859263202.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH v2 0/4] Improve Hyper-V memory deposit error handling | This series extends the MSHV driver to properly handle additional
memory-related error codes from the Microsoft Hypervisor by depositing
memory pages when needed.
Currently, when the hypervisor returns HV_STATUS_INSUFFICIENT_MEMORY
during partition creation, the driver calls hv_call_deposit_pages() to
provide the nece... | When creating guest partition objects, the hypervisor may fail to
allocate root partition pages and return an insufficient memory status.
In this case, deposit memory using the root partition ID instead.
Note: This error should never occur in a guest of L1VH partition context.
Signed-off-by: Stanislav Kinsburskii <sk... | {
"author": "Stanislav Kinsburskii <skinsburskii@linux.microsoft.com>",
"date": "Mon, 02 Feb 2026 17:59:14 +0000",
"thread_id": "177005515446.120041.8169777750859263202.stgit@skinsburskii-cloud-desktop.internal.cloudapp.net.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in commit f3b93547b91a ("module: sign with sha512
instead of sha1 by defa... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Tue, 11 Nov 2025 16:48:31 +0100",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | The PKCS#7 code in sign-file allows for signing only with SHA-1. Since
SHA-1 support for module signing has been removed, drop PKCS#7 support in
favor of using only CMS.
The use of the PKCS#7 code is selected by the following:
#if defined(LIBRESSL_VERSION_NUMBER) || \
OPENSSL_VERSION_NUMBER < 0x10000000L || \
de... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Tue, 11 Nov 2025 16:48:32 +0100",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | Hi Petr,
On Tue, Nov 11, 2025 at 7:49 AM Petr Pavlu <petr.pavlu@suse.com> wrote:
It looks like GKI just uses the defaults here. Overall, Android
doesn't rely on module signing for security, it's only used to
differentiate between module types. Dropping SHA-1 support sounds like
a good idea to me.
For the series:
R... | {
"author": "Sami Tolvanen <samitolvanen@google.com>",
"date": "Tue, 11 Nov 2025 08:22:34 -0800",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Tue, 2025-11-11 at 16:48 +0100, Petr Pavlu wrote:
The change log is a bit alarmist. CMS really *is* PKCS7 and most
literature will refer to CMS as PKCS7. What you're really deprecating
is the use of the PKCS7_sign() API which can only produce SHA-1
Signatures ... openssl is fully capable of producing any hash PKC... | {
"author": "James Bottomley <James.Bottomley@HansenPartnership.com>",
"date": "Tue, 11 Nov 2025 11:53:34 -0500",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Tue, Nov 11, 2025 at 04:48:31PM +0100, Petr Pavlu wrote:
Agreed.
Reviewed-by: Aaron Tomlin <atomlin@atomlin.com>
--
Aaron Tomlin | {
"author": "Aaron Tomlin <atomlin@atomlin.com>",
"date": "Tue, 11 Nov 2025 17:37:28 -0500",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On 11/11/25 5:53 PM, James Bottomley wrote:
Ok, I plan to update the description to the following in v2:
sign-file: Use only the OpenSSL CMS API for signing
The USE_PKCS7 code in sign-file utilizes PKCS7_sign(), which allows signing
only with SHA-1. Since SHA-1 support for module signing has been removed,
drop the u... | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Wed, 12 Nov 2025 14:51:24 +0100",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Wed, 2025-11-12 at 14:51 +0100, Petr Pavlu wrote:
Much better, thanks!
Regards,
James | {
"author": "James Bottomley <James.Bottomley@HansenPartnership.com>",
"date": "Wed, 12 Nov 2025 10:05:57 -0500",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | Petr Pavlu <petr.pavlu@suse.com> wrote:
We're looking at moving to ML-DSA, and the CMS support there is slightly dodgy
at the moment, so we need to hold off a bit on this change.
Patch 1, removing the option to sign with SHA-1 from the kernel is fine, but
doesn't stop things that are signed with SHA-1 from being ver... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Wed, 12 Nov 2025 15:36:57 +0000",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Wed, 2025-11-12 at 15:36 +0000, David Howells wrote:
How will removing PKCS7_sign, which can only do sha1 signatures affect
that? Is the dodginess that the PKCS7_... API is better than CMS_...
for PQS at the moment? In which case we could pretty much do a rip and
replace of the CMS_ API if necessary, but that woul... | {
"author": "James Bottomley <James.Bottomley@HansenPartnership.com>",
"date": "Wed, 12 Nov 2025 10:47:23 -0500",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | James Bottomley <James.Bottomley@HansenPartnership.com> wrote:
OpenSSL-3.5.1's ML-DSA support isn't completely right - in particular
CMS_NOATTR is not currently supported. I believe there is a fix in the works
there, but I doubt it has made it to all the distributions yet. I'm only
asking that we hold off a cycle; ... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Wed, 12 Nov 2025 15:52:40 +0000",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Wed, 2025-11-12 at 15:52 +0000, David Howells wrote:
I get that PQC in openssl-3.5 is highly experimental, but that merely
means we tell people not to use it for a while. However, what I don't
see is how this impacts PKCS7_sign removal. The CMS API can do a sha1
signature if that's what people want and keeping th... | {
"author": "James Bottomley <James.Bottomley@HansenPartnership.com>",
"date": "Wed, 12 Nov 2025 10:58:31 -0500",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Tue, 11 Nov 2025 16:48:30 +0100, Petr Pavlu wrote:
Applied to modules-next, thanks!
[1/2] module: Remove SHA-1 support for module signing
commit: 148519a06304af4e6fbb82f20e1a4480e2c1b126
[2/2] sign-file: Use only the OpenSSL CMS API for signing
commit: d7afd65b4acc775df872af30948dd7c196587169
Best reg... | {
"author": "Sami Tolvanen <samitolvanen@google.com>",
"date": "Mon, 22 Dec 2025 20:24:17 +0000",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | Here's an alternative patch that will allow PKCS#7 with the hash specified on
the command line, removing the SHA1 restriction.
David
---
sign-file, pkcs7: Honour the hash parameter to sign-file
Currently, the sign-file program rejects anything other than "sha1" as the
hash parameter if it is going to produce a PKCS#7... | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 02 Feb 2026 11:24:22 +0000",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | David Howells <dhowells@redhat.com> wrote:
Apologies, that line was so I could debug it and should've been removed.
David | {
"author": "David Howells <dhowells@redhat.com>",
"date": "Mon, 02 Feb 2026 11:27:39 +0000",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On 2/2/26 12:24 PM, David Howells wrote:
Is it worth keeping this sign-file code that uses the OpenSSL PKCS7 API
instead of having only one variant that uses the newer CMS API?
--
Thanks,
Petr | {
"author": "Petr Pavlu <petr.pavlu@suse.com>",
"date": "Mon, 2 Feb 2026 13:25:06 +0100",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 0/2] module: Remove SHA-1 support for module signing | SHA-1 is considered deprecated and insecure due to vulnerabilities that can
lead to hash collisions. Most distributions have already been using SHA-2
for module signing because of this. The default was also changed last year
from SHA-1 to SHA-512 in f3b93547b91a ("module: sign with sha512 instead of
sha1 by default"). ... | On Mon, Feb 2, 2026 at 4:25 AM Petr Pavlu <petr.pavlu@suse.com> wrote:
I agree that keeping only the CMS variant makes more sense. However,
David, please let me know if you'd prefer that I drop the patch
removing PKCS7 support from sign-file for now. I assumed you had no
further objections since the discussion in the ... | {
"author": "Sami Tolvanen <samitolvanen@google.com>",
"date": "Mon, 2 Feb 2026 09:01:19 -0800",
"thread_id": "CABCJKucAkZa10TYRQ+NxPPw3KaTq4QVk5+XZWyCPpSrpMR_GEg@mail.gmail.com.mbox.gz"
} |
lkml | [PATCH 5.15.y 1/3] wifi: cfg80211: add a work abstraction with special semantics | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit a3ee4dc84c4e9d14cb34dad095fd678127aca5b6 ]
Add a work abstraction at the cfg80211 level that will always
hold the wiphy_lock() for any work executed and therefore also
can be canceled safely (without waiting) while holding that.
This improves on what we ... | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit 16114496d684a3df4ce09f7c6b7557a8b2922795 ]
We'll need this later to convert other works that might
be cancelled from here, so convert this one first.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Hanne-Lotta Mäenpää <hannelotta@g... | {
"author": "=?UTF-8?q?Hanne-Lotta=20M=C3=A4enp=C3=A4=C3=A4?= <hannelotta@gmail.com>",
"date": "Mon, 2 Feb 2026 18:50:37 +0200",
"thread_id": "20260202165038.215693-1-hannelotta@gmail.com.mbox.gz"
} |
lkml | [PATCH 5.15.y 1/3] wifi: cfg80211: add a work abstraction with special semantics | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit a3ee4dc84c4e9d14cb34dad095fd678127aca5b6 ]
Add a work abstraction at the cfg80211 level that will always
hold the wiphy_lock() for any work executed and therefore also
can be canceled safely (without waiting) while holding that.
This improves on what we ... | From: Johannes Berg <johannes.berg@intel.com>
[ Upstream commit 777b26002b73127e81643d9286fadf3d41e0e477 ]
Again, to have the wiphy locked for it.
Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
[ Summary of conflict resolutions:
- In mlme.c, move... | {
"author": "=?UTF-8?q?Hanne-Lotta=20M=C3=A4enp=C3=A4=C3=A4?= <hannelotta@gmail.com>",
"date": "Mon, 2 Feb 2026 18:50:38 +0200",
"thread_id": "20260202165038.215693-1-hannelotta@gmail.com.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Currently hrtimer_interrupt() runs expired timers, which can re-arm
themselves, after which it computes the next expiration time and
re-programs the hardware.
However, things like HRTICK, a highres timer driving preemption,
cannot re-arm itself at the point of running, since the next task has
not been determined yet. ... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:15 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Hi!
At long last a new version of the hrtick rework! The previous version had a
mysterious deadlock which has been resolved. So far (weeks) the 0-day robot has
not found more issues with these patches.
These patches aim to reduce the hrtick overhead to such an extent that it can
be default enabled. Decoupling the pre... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:10 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Upon schedule() HRTICK will cancel the current timer, pick the next
task and reprogram the timer. When schedule() consistently triggers
due to blocking conditions instead of the timer, this leads to endless
reprogramming without ever firing.
Mitigate this with a new hrtimer mode: fuzzy (not really happy with
that name... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:13 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Rework hrtimer_interrupt() such that reprogramming is split out into
an independent function at the end of the interrupt.
This prepares for reprogramming getting delayed beyond the end of
hrtimer_interrupt().
Notably, this changes the hang handling to always wait 100ms instead
of trying to keep it proportional to the... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:14 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | The nominal duration for an EEVDF task to run is until its deadline.
At which point the deadline is moved ahead and a new task selection is
done.
Try and predict the time 'lost' to higher scheduling classes. Since
this is an estimate, the timer can be both early or late. In case it
is early task_tick_fair() will take ... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:11 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | ... for generic entry architectures. This decouples preemption from
CONFIG_HZ, leaving only the periodic load-balancer and various
accounting things relying on the tick.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/sched/features.h | 5 +++++
1 file changed, 5 insertions(+)
--- a/kernel... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Wed, 21 Jan 2026 17:20:16 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Hi Peter,
On Wed, Jan 21, 2026 at 05:20:16PM +0100 Peter Zijlstra wrote:
I maybe be missing something. But the title of this patch
and the above code do not seem to match.
Cheers,
Phil
-- | {
"author": "Phil Auld <pauld@redhat.com>",
"date": "Wed, 21 Jan 2026 17:24:44 -0500",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Hello,
On 21/01/26 17:20, Peter Zijlstra wrote:
...
Nit.. guess we don't fear overflow since vdelta should be bounded
anyway.
Reviewed-by: Juri Lelli <juri.lelli@redhat.com>
Thanks,
Juri | {
"author": "Juri Lelli <juri.lelli@redhat.com>",
"date": "Thu, 22 Jan 2026 11:53:34 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Hello,
On 21/01/26 17:20, Peter Zijlstra wrote:
Reviewed-by: Juri Lelli <juri.lelli@redhat.com>
Thanks,
Juri | {
"author": "Juri Lelli <juri.lelli@redhat.com>",
"date": "Thu, 22 Jan 2026 12:00:14 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, Jan 21, 2026 at 05:24:44PM -0500, Phil Auld wrote:
Arguably this should be CONFIG_GENERIC_ENTRY I suppose
You mean it only default enables it for a subset of architectures? | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Thu, 22 Jan 2026 12:40:54 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Thu, Jan 22, 2026 at 12:40:54PM +0100 Peter Zijlstra wrote:
Nope, I mean I can't read... nevermind.
Cheers,
Phil
-- | {
"author": "Phil Auld <pauld@redhat.com>",
"date": "Thu, 22 Jan 2026 07:31:17 -0500",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | Hello,
On 21/01/26 17:20, Peter Zijlstra wrote:
Does the more common (lazier :) 'lazy' work better?
...
Not sure either, but since it's improving things for local already,
maybe it's an acceptable first step?
Reviewed-by: Juri Lelli <juri.lelli@redhat.com>
Thanks,
Juri | {
"author": "Juri Lelli <juri.lelli@redhat.com>",
"date": "Thu, 22 Jan 2026 14:12:28 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Thu, 22 Jan 2026 14:12:28 +0100
Juri Lelli <juri.lelli@redhat.com> wrote:
I don't like either fuzzy or lazy.
Fuzzy makes me think of just random entries (for fuzz testing and such).
Lazy is to postpone things to do things less often.
What about "speculative"? Like branch prediction and such. Where a timer
is e... | {
"author": "Steven Rostedt <rostedt@goodmis.org>",
"date": "Fri, 23 Jan 2026 15:04:50 -0500",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, 21 Jan 2026 17:20:15 +0100
Peter Zijlstra <peterz@infradead.org> wrote:
I'm curious to why you decided to use scoped_guard() here and not just
guard() and not add the extra indentation? The function is small enough
where everything is expected to be protected by the spinlock.
-- Steve | {
"author": "Steven Rostedt <rostedt@goodmis.org>",
"date": "Fri, 23 Jan 2026 15:08:43 -0500",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Fri, Jan 23, 2026 at 03:08:43PM -0500, Steven Rostedt wrote:
Yeah, I'm not entirely sure... its been over 6 months since I wrote this
code :-/ | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Fri, 23 Jan 2026 22:04:33 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, Jan 21 2026 at 17:20, Peter Zijlstra wrote:
Reviewed-by: Thomas Gleixner <tglx@kernel.org> | {
"author": "Thomas Gleixner <tglx@linutronix.de>",
"date": "Mon, 02 Feb 2026 13:28:12 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, Jan 21 2026 at 17:20, Peter Zijlstra wrote:
SHouldn't this be HRTIMER_MODE_REL_PINNED_HARD? I know it's set when
starting the timer, but I had to double check it.
I'd rather say:
Fuzzy requires pinned as the lazy reprogramming only works
for CPU local timers.
Other than that:
Review... | {
"author": "Thomas Gleixner <tglx@linutronix.de>",
"date": "Mon, 02 Feb 2026 15:02:26 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, Jan 21 2026 at 17:20, Peter Zijlstra wrote:
Indeed.
in_hrtirq
Reviewed-by: Thomas Gleixner <tglx@kernel.org> | {
"author": "Thomas Gleixner <tglx@linutronix.de>",
"date": "Mon, 02 Feb 2026 15:05:14 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Wed, Jan 21 2026 at 17:20, Peter Zijlstra wrote:
Two things I'm not convinced that they are handled correctly:
1) Interrupts
After reenabling interrupts and before reaching schedule() an
interrupt comes in and runs soft interrupt processing for a while
on the way back, which delays the up... | {
"author": "Thomas Gleixner <tglx@linutronix.de>",
"date": "Mon, 02 Feb 2026 15:37:13 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH v2 2/6] hrtimer: Optimize __hrtimer_start_range_ns() | Much like hrtimer_reprogram(), skip programming if the cpu_base is
running the hrtimer interrupt.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
kernel/time/hrtimer.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/kernel/time/hrtimer.c
+++ b/kernel/time/hrtimer.c
@@ -1261,6 +1261,14 @@ stat... | On Mon, Feb 02, 2026 at 03:37:13PM +0100, Thomas Gleixner wrote:
So the basic thing looks like:
<USER-MODE>
irqentry_enter()
run_irq_on_irqstack_cond()
if (user_mode() || hardirq_stack_inuse)
irq_enter_rcu();
func_c();
irq_exit_rcu()
__irq_exit_rcu()
invoke_softirq()
irqentr... | {
"author": "Peter Zijlstra <peterz@infradead.org>",
"date": "Mon, 2 Feb 2026 17:33:55 +0100",
"thread_id": "20260202163355.GI1395266@noisy.programming.kicks-ass.net.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | From: Arnd Bergmann <arnd@arndb.de>
The deeply nested loop in rkvdec_init_v4l2_vp9_count_tbl() needs a lot
of registers, so when the clang register allocator runs out, it ends up
spilling countless temporaries to the stack:
drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c:966:12: error: stack frame size (1472) exc... | {
"author": "Arnd Bergmann <arnd@kernel.org>",
"date": "Mon, 2 Feb 2026 10:47:51 +0100",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | Hi Arnd,
Le lundi 02 février 2026 à 10:47 +0100, Arnd Bergmann a écrit :
We had already addressed and validated that on clang-21, which indicates me that
we likely are missing an architecture (or a config) in our CI. Can you document
which architecture, configuration and flags was affected so we can add it on our
sid... | {
"author": "Nicolas Dufresne <nicolas.dufresne@collabora.com>",
"date": "Mon, 02 Feb 2026 08:42:41 -0500",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | On Mon, Feb 2, 2026, at 14:42, Nicolas Dufresne wrote:
The configuration that hit this for me was an ARMv7-M NOMMU build. I'm
doing 'randconfig' builds here, so I inevitably hit some corner cases
that all deterministic CI systems miss. I don't think that you should
add ARMv7-M here, since that would take up useful bui... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Mon, 02 Feb 2026 15:09:14 +0100",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | Hi Arnd,
Le lundi 02 février 2026 à 15:09 +0100, Arnd Bergmann a écrit :
All fair comments. I plan to take this into fixes (no changes needed), hopefully
for rc-2.
Performance wise, this code is to replace read/mask/write into hardware
registers which was significantly slower for this amount of registers (~200
32bit... | {
"author": "Nicolas Dufresne <nicolas.dufresne@collabora.com>",
"date": "Mon, 02 Feb 2026 10:12:53 -0500",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | On Mon, Feb 2, 2026, at 16:12, Nicolas Dufresne wrote:
I think there are multiple things going on here, some of which are
more relevant than others:
- The problem I'm addressing with my patch is purely a clang issue
for CPU architectures with high register pressure when assembling
the structure in memory. As ... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Mon, 02 Feb 2026 16:59:05 +0100",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | Hi,
Le lundi 02 février 2026 à 16:59 +0100, Arnd Bergmann a écrit :
Ok, got it, clearly the registers bitfield (which is a set of 32bit bitfield) is
fine (appart from endian, but this is deliberatly ignored). These are the one I
had mind, and are optimized with copy_toio.
For the SPS/PPS bistream, which is shared me... | {
"author": "Nicolas Dufresne <nicolas.dufresne@collabora.com>",
"date": "Mon, 02 Feb 2026 11:31:40 -0500",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 1/2] media: rkvdec: reduce excessive stack usage in assemble_hw_pps() | From: Arnd Bergmann <arnd@arndb.de>
The rkvdec_pps had a large set of bitfields, all of which
as misaligned. This causes clang-21 and likely other versions to
produce absolutely awful object code and a warning about very
large stack usage, on targets without unaligned access:
drivers/media/platform/rockchip/rkvdec/rk... | Le lundi 02 février 2026 à 10:47 +0100, Arnd Bergmann a écrit :
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> | {
"author": "Nicolas Dufresne <nicolas.dufresne@collabora.com>",
"date": "Mon, 02 Feb 2026 11:32:16 -0500",
"thread_id": "ca81b8b03651cdb4f997c89fffd489407be59b8b.camel@collabora.com.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Set d3hot_delay to 0 for Intel controllers because a delay is not needed.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i3c/master/mipi-i3c-h... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:35 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Some I3C controller drivers need runtime PM to operate on a device other
than the parent device. To support that, add an rpm_dev pointer to
struct i3c_master_controller so drivers can specify which device should
be used for runtime power management.
If a driver does not set rpm_dev explicitly, default to using the pa... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:36 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | When an IBI can be received after the controller is
pm_runtime_put_autosuspend()'ed, the interrupt may occur just before the
device is auto‑suspended. In such cases, the runtime PM core may not see
any recent activity and may suspend the device earlier than intended.
Mark the controller as last busy whenever an IBI i... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:37 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Some I3C controllers can be automatically runtime-resumed in order to
handle in-band interrupts (IBIs), meaning that runtime suspend does not
need to be blocked when IBIs are enabled.
For example, a PCI-attached controller in a low-power state may generate
a Power Management Event (PME) when the SDA line is pulled low... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:38 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability,
where a single parent device hosts multiple I3C controller instances. In
such designs, the parent - not the individual child instances - may need to
coordinate runtime PM so that all controllers enter low-power states
together, and all runtime su... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:39 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs), and they also implement the MIPI I3C HCI
Multi-Bus Instance capability. When multiple I3C bus instances share the
same PCI wakeup, the PCI parent must coordinate runtime PM so that all
instances suspend together and their mi... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:41 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability,
where a single parent device hosts multiple I3C controller instances. In
such designs, the parent - not the individual child instances - may need to
coordinate runtime PM so that all controllers enter low-power states
together, and all runtime su... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 20:18:40 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Thu, Jan 29, 2026 at 08:18:35PM +0200, Adrian Hunter wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 14:43:45 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Thu, Jan 29, 2026 at 08:18:37PM +0200, Adrian Hunter wrote:
look like this can't resolve problem. pm_runtime_mark_last_busy() just
change dev->power.last_busy. If suspend before it, nothing happen.
irq use thread irq, in irq thread call pm_runtime_resume() if needs.
And this function call by irq handle, just put ... | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 14:56:01 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Thu, Jan 29, 2026 at 08:18:39PM +0200, Adrian Hunter wrote:
Does your hardware support recieve IBI when runtime suspend?
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 15:00:14 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On 29/01/2026 22:00, Frank Li wrote:
When runtime suspended (in D3), the hardware first triggers a Power Management
Event (PME) when the SDA line is pulled low to signal the START condition of an IBI.
The PCI subsystem will then runtime-resume the device. When the bus is enabled,
the clock is started and the IBI is r... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 22:28:14 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On 29/01/2026 21:56, Frank Li wrote:
It should be effective.
rpm_suspend() recalculates the autosuspend expiry time based on
last_busy (see pm_runtime_autosuspend_expiration()) and restarts
the timer is it is in the future.
Just premature runtime suspension inconsistent with autosuspend_delay. | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Thu, 29 Jan 2026 22:42:32 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Thu, Jan 29, 2026 at 10:42:32PM +0200, Adrian Hunter wrote:
CPU 0 CPU 1
1. rpm_suspend() 2. pm_runtime_mark_last_busy(master->rpm_dev)
if 2 happen before 1, it can extend suspend. 2 happen after 1, it should
do nothing.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 15:55:40 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Thu, Jan 29, 2026 at 10:28:14PM +0200, Adrian Hunter wrote:
It align my assumption, why need complex solution.
SDA->PME->IRQ should handle by hardware, so irq handle queue IBI to working
queue.
IBI work will try do transfer, which will call runtime resume(), then
transfer data.
What's issue?
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 29 Jan 2026 16:00:20 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On 29/01/2026 23:00, Frank Li wrote:
The PME indicates I3C START (SDA line pulled low). The controller is
in a low power state unable to operate the bus. At this point it is not
known what I3C device has pulled down the SDA line, or even if it is an
IBI since it is indistinguishable from hot-join at this point.
The... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Fri, 30 Jan 2026 09:00:33 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On 29/01/2026 22:55, Frank Li wrote:
2 happening after 1 is a separate issue. It will never happen
in the wakeup case because the wakeup does a runtime resume:
pm_runtime_put_autosuspend()
IBI -> pm_runtime_mark_last_busy()
another IBI -> pm_runtime_mark_last_busy() and so on
<autosuspend_delay finally elapses>
... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Fri, 30 Jan 2026 09:48:07 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Fri, Jan 30, 2026 at 09:00:33AM +0200, Adrian Hunter wrote:
One instance 1 suspend, instance 2 running, PME is inactive, what's happen
if instance 1 request IBI?
IBI will be missed?
Does PME active auto by hardware or need software config?
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Fri, 30 Jan 2026 10:04:24 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On 30/01/2026 17:04, Frank Li wrote:
Nothing will happen. Instance 1 I3C bus is not operational and there can
be no PME when the PCI device is not in a low power state (D3hot)
Possibly not if instance 1 is eventually resumed and the I3C device
requesting the IBI has not yet given up.
PCI devices (hardware) advert... | {
"author": "Adrian Hunter <adrian.hunter@intel.com>",
"date": "Fri, 30 Jan 2026 18:34:37 +0200",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Fri, Jan 30, 2026 at 06:34:37PM +0200, Adrian Hunter wrote:
Okay, I think I understand your situation, let me check patch again.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Fri, 30 Jan 2026 12:11:19 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers | Hi
Here are patches related to enabling IBI while runtime suspended for Intel
controllers.
Intel LPSS I3C controllers can wake from runtime suspend to receive
in-band interrupts (IBIs).
It is non-trivial to implement because the parent PCI device has 2 I3C bus
instances (MIPI I3C HCI Multi-Bus Instance capability) r... | On Fri, Jan 30, 2026 at 06:34:37PM +0200, Adrian Hunter wrote:
Does your device Hierarchy look like
PCI device
|
-----------------
HCI1 HCI2
| |
I3C M1 I3C M2
You want HCI1 and HCI2 suspened only when both HCI1 and HCI2 can enter R... | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Mon, 2 Feb 2026 11:25:23 -0500",
"thread_id": "aYDP847mgleQBF5Y@lizhi-Precision-Tower-5810.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | The SEV-SNP IBPB-on-Entry feature does not require a guest-side
implementation. The feature was added in Zen5 h/w, after the first
SNP Zen implementation, and thus was not accounted for when the
initial set of SNP features were added to the kernel.
In its abundant precaution, commit 8c29f0165405 ("x86/sev: Add SEV-SNP... | {
"author": "Kim Phillips <kim.phillips@amd.com>",
"date": "Mon, 26 Jan 2026 16:42:04 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
SNP guests may choose to enable IBPB-on-Entry by setting
SEV_FEATURES... | {
"author": "Kim Phillips <kim.phillips@amd.com>",
"date": "Mon, 26 Jan 2026 16:42:05 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/27/2026 4:12 AM, Kim Phillips wrote:
The subject line should have the prefix "x86/sev" instead
of "KVM: SEV". The below subject line would be more appropriate:
x86/sev: Allow IBPB-on-Entry feature for SNP guests
Apart from the above comments:
Reviewed-by: Nikunj A Dadhania <nikunj@amd.com> | {
"author": "\"Nikunj A. Dadhania\" <nikunj@amd.com>",
"date": "Tue, 27 Jan 2026 11:49:07 +0530",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/27/2026 4:12 AM, Kim Phillips wrote:
The early return seems to split up the SNP features unnecessarily.
Keeping everything under `if (sev_snp_enabled)` is cleaner IMO -
it's clear that these features belong together. Plus, when
someone adds the next SNP feature, they won't have to think about
whether it goes be... | {
"author": "\"Nikunj A. Dadhania\" <nikunj@amd.com>",
"date": "Tue, 27 Jan 2026 12:08:27 +0530",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/27/26 12:38 AM, Nikunj A. Dadhania wrote:
Hi Nikunj,
The SNP 'togetherness' semantics are maintained whether under an
'if (sev_snp_enabled)' body, or after an 'if (!sev_snp_enabled) return;'.
Only SNP-specific things are being done in the trailing part of the function,
so it naturally lends itself to do the ear... | {
"author": "Kim Phillips <kim.phillips@amd.com>",
"date": "Tue, 27 Jan 2026 14:56:02 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/26/26 16:42, Kim Phillips wrote:
With the change to the subject line...
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> | {
"author": "Tom Lendacky <thomas.lendacky@amd.com>",
"date": "Wed, 28 Jan 2026 13:02:37 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/26/26 16:42, Kim Phillips wrote:
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> | {
"author": "Tom Lendacky <thomas.lendacky@amd.com>",
"date": "Wed, 28 Jan 2026 13:08:49 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Mon, Jan 26, 2026 at 04:42:04PM -0600, Kim Phillips wrote:
Do not explain what the patch does.
I guess...
Why isn't this part of SNP_FEATURES_PRESENT?
If this feature doesn't require guest-side support, then it is trivially
present, no?
I guess this is a fix of sorts and I could take it in now once all revie... | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Wed, 28 Jan 2026 20:23:12 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | Hi Boris,
On 1/28/26 1:23 PM, Borislav Petkov wrote:
For that last paragraph, how about:
"Allow guests to make use of IBPB-on-Entry when supported by the
hypervisor, as the bit is now architecturally defined and safe to
expose."
?
Hopefully a bitfield will be carved out for these
no-explicit-guest-implementation-... | {
"author": "Kim Phillips <kim.phillips@amd.com>",
"date": "Wed, 28 Jan 2026 18:38:29 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Wed, Jan 28, 2026 at 06:38:29PM -0600, Kim Phillips wrote:
Better.
Yes, and I'm asking why can't SNP_FEATURES_PRESENT contain *all* SNP features?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Thu, 29 Jan 2026 11:51:16 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/29/26 4:51 AM, Borislav Petkov wrote:
Not *all* SNP features are implemented in all guest kernel versions, and,
well, for those that don't require explicit guest code support, perhaps it's
because they aren't necessarily well defined and validated in all hardware
versions...
Kim | {
"author": "Kim Phillips <kim.phillips@amd.com>",
"date": "Thu, 29 Jan 2026 16:32:49 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Thu, Jan 29, 2026 at 04:32:49PM -0600, Kim Phillips wrote:
Ok, can you add *this* feature to SNP_FEATURES_PRESENT? If not, why not?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Fri, 30 Jan 2026 13:32:52 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/30/26 06:32, Borislav Petkov wrote:
It can be added. Any of the features added to SNP_FEATURES_PRESENT that
aren't set in the SNP_FEATURES_IMPL_REQ bitmap are really a no-op. The
SNP_FEATURES_PRESENT bitmap is meant to contain whatever bits are set in
SNP_FEATURES_IMPL_REQ when an implementation has been implemen... | {
"author": "Tom Lendacky <thomas.lendacky@amd.com>",
"date": "Fri, 30 Jan 2026 08:56:07 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Fri, Jan 30, 2026 at 08:56:07AM -0600, Tom Lendacky wrote:
Right, that's the question. SNP_FEATURES_PRESENT is used in the masking
operation to get the unsupported features.
But when we say a SNP feature is present, then, even if it doesn't need guest
implementation, that feature is still present nonetheless.
So ... | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Fri, 30 Jan 2026 16:45:34 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 1/30/26 09:45, Borislav Petkov wrote:
I guess it really depends on the persons point of view. I agree that
renaming the SNP_FEATURES_PRESENT to SNP_FEATURES_IMPL(EMENTED) would
match up nicely with SNP_FEATURES_IMPL_REQ. Maybe that's all that is
needed...
Thanks,
Tom | {
"author": "Tom Lendacky <thomas.lendacky@amd.com>",
"date": "Mon, 2 Feb 2026 09:38:50 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Mon, Feb 02, 2026 at 09:38:50AM -0600, Tom Lendacky wrote:
I guess...
I still think it would be useful to have a common place that says which things
in SEV_STATUS are supported and present in a guest, no?
Or are we going to dump that MSR like Joerg's patch from a while ago and
that'll tell us what the guest suppo... | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Mon, 2 Feb 2026 16:49:36 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On 2/2/26 09:49, Borislav Petkov wrote:
But I can see that getting stale because it isn't required to be updated
for features that don't require an implementation in order for the guest
to boot successfully. Whereas the SNP_FEATURES_IMPL_REQ is set with
known values that require an implementation and all the reserved ... | {
"author": "Tom Lendacky <thomas.lendacky@amd.com>",
"date": "Mon, 2 Feb 2026 10:09:19 -0600",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH 0/2] KVM: SEV: Add support for IBPB-on-Entry | AMD EPYC 5th generation and above processors support IBPB-on-Entry
for SNP guests. By invoking an Indirect Branch Prediction Barrier
(IBPB) on VMRUN, old indirect branch predictions are prevented
from influencing indirect branches within the guest.
The first patch is guest-side support which unmasks the Zen5+ feature... | On Mon, Feb 02, 2026 at 10:09:19AM -0600, Tom Lendacky wrote:
Ok, I guess we can rename that define SNP_FEATURES_IMPL to denote is the
counterpart of SNP_FEATURES_IMPL_REQ, so to speak.
@Kim, you can send a new version with the define renamed.
Due to it being too close to the merge window, it'll wait for after and t... | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Mon, 2 Feb 2026 18:12:23 +0100",
"thread_id": "20260202171223.GBaYDa9z7sKO9q3Q9a@fat_crate.local.mbox.gz"
} |
lkml | [PATCH] Cleanup ipu3 driver | Clean up warnings generated by ./scripts/checkpatch.pl regarding the ipu3 driver at /drivers/staging/media/ipu3
More specifically, the following files have been affected: ipu3-css.c, ipu3-mmu.c, ipu3-mmu.h, ipu3-v4l2.c, ipu3.c, ipu3.h
Signed-off-by: Bogdan Sandu <bogdanelsandu2011@gmail.com>
---
drivers/staging/medi... | On Mon, Feb 02, 2026 at 12:03:11PM +0200, Bogdan Sandu wrote:
Was this an AI generated patch?
Either way, it needs to be properly broken up into "one logical change
per patch" like all others.
thanks,
greg k-h | {
"author": "Greg KH <gregkh@linuxfoundation.org>",
"date": "Mon, 2 Feb 2026 11:14:26 +0100",
"thread_id": "2026020258-very-numbly-b36b@gregkh.mbox.gz"
} |
lkml | [PATCH] Cleanup ipu3 driver | Clean up warnings generated by ./scripts/checkpatch.pl regarding the ipu3 driver at /drivers/staging/media/ipu3
More specifically, the following files have been affected: ipu3-css.c, ipu3-mmu.c, ipu3-mmu.h, ipu3-v4l2.c, ipu3.c, ipu3.h
Signed-off-by: Bogdan Sandu <bogdanelsandu2011@gmail.com>
---
drivers/staging/medi... | I can assure you, it is not AI-generated.
per patch" like all others.
Understood. I'll resend it afterwards.
Thank you for your patience. | {
"author": "Bogdan Sandu <bogdanelsandu2011@gmail.com>",
"date": "Mon, 2 Feb 2026 12:18:43 +0200",
"thread_id": "2026020258-very-numbly-b36b@gregkh.mbox.gz"
} |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.