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source	linux	================ STiH407 Overview ================ Introduction ------------ The STiH407 is the new generation of SoC for Multi-HD, AVC set-top boxes and server/connected client application for satellite, cable, terrestrial and IP-STB markets. Features - ARM Cortex-A9 1.5 GHz dual core CPU (28nm)...	Documentation/arch/arm/sti/stih407-overview.rst	null	null	null	null	null
source	linux	================ STiH418 Overview ================ Introduction ------------ The STiH418 is the new generation of SoC for UHDp60 set-top boxes and server/connected client application for satellite, cable, terrestrial and IP-STB markets. Features - ARM Cortex-A9 1.5 GHz quad core CPU (28nm) - ...	Documentation/arch/arm/sti/stih418-overview.rst	null	null	null	null	null
source	linux	======================== STM32 ARM Linux Overview ======================== Introduction ------------ The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of ARM Linux. Configuration ------------- For MCUs, use the provided ...	Documentation/arch/arm/stm32/overview.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ======================= STM32 DMA-MDMA chaining ======================= Introduction ------------ This document describes the STM32 DMA-MDMA chaining feature. But before going further, let's introduce the peripherals involved. To offload data transfers from the CPU, STM32 ...	Documentation/arch/arm/stm32/stm32-dma-mdma-chaining.rst	null	null	null	null	null
source	linux	================== STM32F429 Overview ================== Introduction ------------ The STM32F429 is a Cortex-M4 MCU aimed at various applications. It features: - ARM Cortex-M4 up to 180MHz with FPU - 2MB internal Flash Memory - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND) - I2C, SPI, SAI,...	Documentation/arch/arm/stm32/stm32f429-overview.rst	null	null	null	null	null
source	linux	================== STM32F746 Overview ================== Introduction ------------ The STM32F746 is a Cortex-M7 MCU aimed at various applications. It features: - Cortex-M7 core running up to @216MHz - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM) - FMC controller to connect SDRAM, NOR and NAND mem...	Documentation/arch/arm/stm32/stm32f746-overview.rst	null	null	null	null	null
source	linux	================== STM32F769 Overview ================== Introduction ------------ The STM32F769 is a Cortex-M7 MCU aimed at various applications. It features: - Cortex-M7 core running up to @216MHz - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM) - FMC controller to connect SDRAM, NOR and NAND mem...	Documentation/arch/arm/stm32/stm32f769-overview.rst	null	null	null	null	null
source	linux	================== STM32H743 Overview ================== Introduction ------------ The STM32H743 is a Cortex-M7 MCU aimed at various applications. It features: - Cortex-M7 core running up to @400MHz - 2MB internal flash, 1MBytes internal RAM - FMC controller to connect SDRAM, NOR and NAND memories - Dual mode QSPI -...	Documentation/arch/arm/stm32/stm32h743-overview.rst	null	null	null	null	null
source	linux	================== STM32H750 Overview ================== Introduction ------------ The STM32H750 is a Cortex-M7 MCU aimed at various applications. It features: - Cortex-M7 core running up to @480MHz - 128K internal flash, 1MBytes internal RAM - FMC controller to connect SDRAM, NOR and NAND memories - Dual mode QSPI ...	Documentation/arch/arm/stm32/stm32h750-overview.rst	null	null	null	null	null
source	linux	=================== STM32MP13 Overview =================== Introduction ------------ The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications. They feature: - One Cortex-A7 application core - Standard memories interface support - Standard connectivity, widely inherited from the STM32 MCU f...	Documentation/arch/arm/stm32/stm32mp13-overview.rst	null	null	null	null	null
source	linux	=================== STM32MP151 Overview =================== Introduction ------------ The STM32MP151 is a Cortex-A MPU aimed at various applications. It features: - Single Cortex-A7 application core - Standard memories interface support - Standard connectivity, widely inherited from the STM32 MCU family - Comprehens...	Documentation/arch/arm/stm32/stm32mp151-overview.rst	null	null	null	null	null
source	linux	=================== STM32MP157 Overview =================== Introduction ------------ The STM32MP157 is a Cortex-A MPU aimed at various applications. It features: - Dual core Cortex-A7 application core - 2D/3D image composition with GPU - Standard memories interface support - Standard connectivity, widely inherited ...	Documentation/arch/arm/stm32/stm32mp157-overview.rst	null	null	null	null	null
source	linux	======================================================= Frequently asked questions about the sunxi clock system ======================================================= This document contains useful bits of information that people tend to ask about the sunxi clock system, as well as accompanying ASCII art when adequate...	Documentation/arch/arm/sunxi/clocks.rst	null	null	null	null	null
source	linux	=============================================== Release notes for Linux Kernel VFP support code =============================================== Date: 20 May 2004 Author: Russell King This is the first release of the Linux Kernel VFP support code. It provides support for the exceptions bounced from VFP hardware fou...	Documentation/arch/arm/vfp/release-notes.rst	null	null	null	null	null
source	linux	=========== ACPI Tables =========== The expectations of individual ACPI tables are discussed in the list that follows. If a section number is used, it refers to a section number in the ACPI specification where the object is defined. If "Signature Reserved" is used, the table signature (the first four bytes of the ta...	Documentation/arch/arm64/acpi_object_usage.rst	null	null	null	null	null
source	linux	.. _amu_index: ======================================================= Activity Monitors Unit (AMU) extension in AArch64 Linux ======================================================= Author: Ionela Voinescu <ionela.voinescu@arm.com> Date: 2019-09-10 This document briefly describes the provision of Activity Monitors...	Documentation/arch/arm64/amu.rst	null	null	null	null	null
source	linux	=================== ACPI on Arm systems =================== ACPI can be used for Armv8 and Armv9 systems designed to follow the BSA (Arm Base System Architecture) [0] and BBR (Arm Base Boot Requirements) [1] specifications. Both BSA and BBR are publicly accessible documents. Arm Servers, in addition to being BSA comp...	Documentation/arch/arm64/arm-acpi.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ===================================== Arm Confidential Compute Architecture ===================================== Arm systems that support the Realm Management Extension (RME) contain hardware to allow a VM guest to be run in a way which protects the code and data of the guest from...	Documentation/arch/arm64/arm-cca.rst	null	null	null	null	null
source	linux	====================== Asymmetric 32-bit SoCs ====================== Author: Will Deacon <will@kernel.org> This document describes the impact of asymmetric 32-bit SoCs on the execution of 32-bit (``AArch32``) applications. Date: 2021-05-17 Introduction ============ Some Armv9 SoCs suffer from a big.LITTLE misfeatu...	Documentation/arch/arm64/asymmetric-32bit.rst	null	null	null	null	null
source	linux	===================== Booting AArch64 Linux ===================== Author: Will Deacon <will.deacon@arm.com> Date : 07 September 2012 This document is based on the ARM booting document by Russell King and is relevant to all public releases of the AArch64 Linux kernel. The AArch64 exception model is made up of a num...	Documentation/arch/arm64/booting.rst	null	null	null	null	null
source	linux	=========================== ARM64 CPU Feature Registers =========================== Author: Suzuki K Poulose <suzuki.poulose@arm.com> This file describes the ABI for exporting the AArch64 CPU ID/feature registers to userspace. The availability of this ABI is advertised via the HWCAP_CPUID in HWCAPs. 1. Motivation -...	Documentation/arch/arm64/cpu-feature-registers.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _cpuhp_index: ==================== CPU Hotplug and ACPI ==================== CPU hotplug in the arm64 world is commonly used to describe the kernel taking CPUs online/offline using PSCI. This document is about ACPI firmware allowing CPUs that were not available during boot to be...	Documentation/arch/arm64/cpu-hotplug.rst	null	null	null	null	null
source	linux	.. _elf_hwcaps_index: ================ ARM64 ELF hwcaps ================ This document describes the usage and semantics of the arm64 ELF hwcaps. 1. Introduction --------------- Some hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, but have no...	Documentation/arch/arm64/elf_hwcaps.rst	null	null	null	null	null
source	linux	=============================================== Guarded Control Stack support for AArch64 Linux =============================================== This document outlines briefly the interface provided to userspace by Linux in order to support use of the ARM Guarded Control Stack (GCS) feature. This is an outline of the ...	Documentation/arch/arm64/gcs.rst	null	null	null	null	null
source	linux	.. _hugetlbpage_index: ==================== HugeTLBpage on ARM64 ==================== Hugepage relies on making efficient use of TLBs to improve performance of address translations. The benefit depends on both - - the size of hugepages - size of entries supported by the TLBs The ARM64 port supports two flavours...	Documentation/arch/arm64/hugetlbpage.rst	null	null	null	null	null
source	linux	.. _arm64_index: ================== ARM64 Architecture ================== .. toctree:: :maxdepth: 1 acpi_object_usage amu arm-acpi arm-cca asymmetric-32bit booting cpu-feature-registers cpu-hotplug elf_hwcaps gcs hugetlbpage kdump legacy_instructions memory...	Documentation/arch/arm64/index.rst	null	null	null	null	null
source	linux	======================================= crashkernel memory reservation on arm64 ======================================= Author: Baoquan He <bhe@redhat.com> Kdump mechanism is used to capture a corrupted kernel vmcore so that it can be subsequently analyzed. In order to do this, a preliminarily reserved memory is need...	Documentation/arch/arm64/kdump.rst	null	null	null	null	null
source	linux	=================== Legacy instructions =================== The arm64 port of the Linux kernel provides infrastructure to support emulation of instructions which have been deprecated, or obsoleted in the architecture. The infrastructure code uses undefined instruction hooks to support emulation. Where available it als...	Documentation/arch/arm64/legacy_instructions.rst	null	null	null	null	null
source	linux	=============================================== Memory Tagging Extension (MTE) in AArch64 Linux =============================================== Authors: Vincenzo Frascino <vincenzo.frascino@arm.com> Catalin Marinas <catalin.marinas@arm.com> Date: 2020-02-25 This document describes the provision of the Memor...	Documentation/arch/arm64/memory-tagging-extension.rst	null	null	null	null	null
source	linux	============================== Memory Layout on AArch64 Linux ============================== Author: Catalin Marinas <catalin.marinas@arm.com> This document describes the virtual memory layout used by the AArch64 Linux kernel. The architecture allows up to 4 levels of translation tables with a 4KB page size and up to...	Documentation/arch/arm64/memory.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =================================== Memory copy/set instructions (MOPS) =================================== A MOPS memory copy/set operation consists of three consecutive CPY* or SET* instructions: a prologue, main and epilogue (for example: CPYP, CPYM, CPYE). A main or epilogue i...	Documentation/arch/arm64/mops.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _perf_index: ==== Perf ==== Perf Event Attributes ===================== :Author: Andrew Murray <andrew.murray@arm.com> :Date: 2019-03-06 exclude_user ------------ This attribute excludes userspace. Userspace always runs at EL0 and thus this attribute will exclude EL0. exc...	Documentation/arch/arm64/perf.rst	null	null	null	null	null
source	linux	======================================= Pointer authentication in AArch64 Linux ======================================= Author: Mark Rutland <mark.rutland@arm.com> Date: 2017-07-19 This document briefly describes the provision of pointer authentication functionality in AArch64 Linux. Architecture overview --------...	Documentation/arch/arm64/pointer-authentication.rst	null	null	null	null	null
source	linux	====================== Kernel page table dump ====================== ptdump is a debugfs interface that provides a detailed dump of the kernel page tables. It offers a comprehensive overview of the kernel virtual memory layout as well as the attributes associated with the various regions in a human-readable format. It...	Documentation/arch/arm64/ptdump.rst	null	null	null	null	null
source	linux	======================================= Silicon Errata and Software Workarounds ======================================= Author: Will Deacon <will.deacon@arm.com> Date : 27 November 2015 It is an unfortunate fact of life that hardware is often produced with so-called "errata", which can cause it to deviate from the ...	Documentation/arch/arm64/silicon-errata.rst	null	null	null	null	null
source	linux	=================================================== Scalable Matrix Extension support for AArch64 Linux =================================================== This document outlines briefly the interface provided to userspace by Linux in order to support use of the ARM Scalable Matrix Extension (SME). This is an outline...	Documentation/arch/arm64/sme.rst	null	null	null	null	null
source	linux	=================================================== Scalable Vector Extension support for AArch64 Linux =================================================== Author: Dave Martin <Dave.Martin@arm.com> Date: 4 August 2017 This document outlines briefly the interface provided to userspace by Linux in order to support u...	Documentation/arch/arm64/sve.rst	null	null	null	null	null
source	linux	========================== AArch64 TAGGED ADDRESS ABI ========================== Authors: Vincenzo Frascino <vincenzo.frascino@arm.com> Catalin Marinas <catalin.marinas@arm.com> Date: 21 August 2019 This document describes the usage and semantics of the Tagged Address ABI on AArch64 Linux. 1. Introduction ...	Documentation/arch/arm64/tagged-address-abi.rst	null	null	null	null	null
source	linux	========================================= Tagged virtual addresses in AArch64 Linux ========================================= Author: Will Deacon <will.deacon@arm.com> Date : 12 June 2013 This document briefly describes the provision of tagged virtual addresses in the AArch64 translation system and their potential ...	Documentation/arch/arm64/tagged-pointers.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ======================= Booting Linux/LoongArch ======================= :Author: Yanteng Si <siyanteng@loongson.cn> :Date: 18 Nov 2022 Information passed from BootLoader to kernel ============================================ LoongArch supports ACPI and FDT. The information that...	Documentation/arch/loongarch/booting.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ====================== LoongArch Architecture ====================== .. toctree:: :maxdepth: 2 :numbered: introduction booting irq-chip-model features	Documentation/arch/loongarch/index.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ========================= Introduction to LoongArch ========================= LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). There are ...	Documentation/arch/loongarch/introduction.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ======================================= IRQ chip model (hierarchy) of LoongArch ======================================= Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU ...	Documentation/arch/loongarch/irq-chip-model.rst	null	null	null	null	null
source	linux	===================================== Amiga Buddha and Catweasel IDE Driver ===================================== The Amiga Buddha and Catweasel IDE Driver (part of ide.c) was written by Geert Uytterhoeven based on the following specifications: ------------------------------------------------------------------------ ...	Documentation/arch/m68k/buddha-driver.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ================= m68k Architecture ================= .. toctree:: :maxdepth: 2 kernel-options buddha-driver features	Documentation/arch/m68k/index.rst	null	null	null	null	null
source	linux	=================================== Command Line Options for Linux/m68k =================================== Last Update: 2 May 1999 Linux/m68k version: 2.2.6 Author: Roman.Hodek@informatik.uni-erlangen.de (Roman Hodek) Update: jds@kom.auc.dk (Jes Sorensen) and faq@linux-m68k.org (Chris Lawrence) 0) Introduction ==...	Documentation/arch/m68k/kernel-options.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 BMIPS DeviceTree Booting ------------------------ Some bootloaders only support a single entry point, at the start of the kernel image. Other bootloaders will jump to the ELF start address. Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y, so the f...	Documentation/arch/mips/booting.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =========================== MIPS-specific Documentation =========================== .. toctree:: :maxdepth: 2 :numbered: booting ingenic-tcu features	Documentation/arch/mips/index.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =============================================== Ingenic JZ47xx SoCs Timer/Counter Unit hardware =============================================== The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to eight channels, that can be used...	Documentation/arch/mips/ingenic-tcu.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ============================== Nios II Specific Documentation ============================== .. toctree:: :maxdepth: 2 :numbered: nios2 features	Documentation/arch/nios2/index.rst	null	null	null	null	null
source	linux	================================= Linux on the Nios II architecture ================================= This is a port of Linux to Nios II (nios2) processor. In order to compile for Nios II, you need a version of GCC with support for the generic system call ABI. Please see this link for more information on how compilin...	Documentation/arch/nios2/nios2.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ===================== OpenRISC Architecture ===================== .. toctree:: :maxdepth: 2 openrisc_port todo features	Documentation/arch/openrisc/index.rst	null	null	null	null	null
source	linux	============== OpenRISC Linux ============== This is a port of Linux to the OpenRISC class of microprocessors; the initial target architecture, specifically, is the 32-bit OpenRISC 1000 family (or1k). For information about OpenRISC processors and ongoing development: ======= ============================== website...	Documentation/arch/openrisc/openrisc_port.rst	null	null	null	null	null
source	linux	==== TODO ==== The OpenRISC Linux port is fully functional and has been tracking upstream since 2.6.35. There are, however, remaining items to be completed within the coming months. Here's a list of known-to-be-less-than-stellar items that are due for investigation shortly, i.e. our TODO list: - Implement the rest...	Documentation/arch/openrisc/todo.rst	null	null	null	null	null
source	linux	================= PA-RISC Debugging ================= okay, here are some hints for debugging the lower-level parts of linux/parisc. 1. Absolute addresses ===================== A lot of the assembly code currently runs in real mode, which means absolute addresses are used instead of virtual addresses as in the rest...	Documentation/arch/parisc/debugging.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ==================== PA-RISC Architecture ==================== .. toctree:: :maxdepth: 2 debugging registers features	Documentation/arch/parisc/index.rst	null	null	null	null	null
source	linux	================================ Register Usage for Linux/PA-RISC ================================ [ an asterisk is used for planned usage which is currently unimplemented ] General Registers as specified by ABI ===================================== Control Registers ----------------- ==============================...	Documentation/arch/parisc/registers.rst	null	null	null	null	null
source	linux	============================ NUMA resource associativity ============================ Associativity represents the groupings of the various platform resources into domains of substantially similar mean performance relative to resources outside of that domain. Resources subsets of a given domain that exhibit better per...	Documentation/arch/powerpc/associativity.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 DeviceTree Booting ------------------ During the development of the Linux/ppc64 kernel, and more specifically, the addition of new platform types outside of the old IBM pSeries/iSeries pair, it was decided to enforce some strict rules regarding the kernel entry and bootloader <-> k...	Documentation/arch/powerpc/booting.rst	null	null	null	null	null
source	linux	======================== The PowerPC boot wrapper ======================== Copyright (C) Secret Lab Technologies Ltd. PowerPC image targets compresses and wraps the kernel image (vmlinux) with a boot wrapper to make it usable by the system firmware. There is no standard PowerPC firmware interface, so the boot wrappe...	Documentation/arch/powerpc/bootwrapper.rst	null	null	null	null	null
source	linux	============ CPU Families ============ This document tries to summarise some of the different cpu families that exist and are supported by arch/powerpc. Book3S (aka sPAPR) ------------------ - Hash MMU (except 603 and e300) - Radix MMU (POWER9 and later) - Software loaded TLB (603 and e300) - Selectable Software lo...	Documentation/arch/powerpc/cpu_families.rst	null	null	null	null	null
source	linux	============ CPU Features ============ Hollis Blanchard <hollis@austin.ibm.com> 5 Jun 2002 This document describes the system (including self-modifying code) used in the PPC Linux kernel to support a variety of PowerPC CPUs without requiring compile-time selection. Early in the boot process the ppc32 kernel detects ...	Documentation/arch/powerpc/cpu_features.rst	null	null	null	null	null
source	linux	===================== DAWR issues on POWER9 ===================== On older POWER9 processors, the Data Address Watchpoint Register (DAWR) can cause a checkstop if it points to cache inhibited (CI) memory. Currently Linux has no way to distinguish CI memory when configuring the DAWR, so on affected systems, the DAWR is...	Documentation/arch/powerpc/dawr-power9.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0-or-later ========================================== DEXCR (Dynamic Execution Control Register) ========================================== Overview ======== The DEXCR is a privileged special purpose register (SPR) introduced in PowerPC ISA 3.1B (Power10) that allows per-cpu control...	Documentation/arch/powerpc/dexcr.rst	null	null	null	null	null
source	linux	=================================== DSCR (Data Stream Control Register) =================================== DSCR register in powerpc allows user to have some control of prefetch of data stream in the processor. Please refer to the ISA documents or related manual for more detailed information regarding how to use this ...	Documentation/arch/powerpc/dscr.rst	null	null	null	null	null
source	linux	========================== PCI Bus EEH Error Recovery ========================== Linas Vepstas <linas@austin.ibm.com> 12 January 2005 Overview: --------- The IBM POWER-based pSeries and iSeries computers include PCI bus controller chips that have extended capabilities for detecting and reporting a large variety of ...	Documentation/arch/powerpc/eeh-pci-error-recovery.rst	null	null	null	null	null
source	linux	.. _elf_hwcaps_powerpc: ================== POWERPC ELF HWCAPs ================== This document describes the usage and semantics of the powerpc ELF HWCAPs. 1. Introduction --------------- Some hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, b...	Documentation/arch/powerpc/elf_hwcaps.rst	null	null	null	null	null
source	linux	========================== ELF Note PowerPC Namespace ========================== The PowerPC namespace in an ELF Note of the kernel binary is used to store capabilities and information which can be used by a bootloader or userland. Types and Descriptors --------------------- The types to be used with the "PowerPC" n...	Documentation/arch/powerpc/elfnote.rst	null	null	null	null	null
source	linux	====================== Firmware-Assisted Dump ====================== July 2011 The goal of firmware-assisted dump is to enable the dump of a crashed system, and to do so from a fully-reset system, and to minimize the total elapsed time until the system is back in production use. - Firmware-Assisted Dump (FADump) inf...	Documentation/arch/powerpc/firmware-assisted-dump.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _htm: =================================== HTM (Hardware Trace Macro) =================================== Athira Rajeev, 2 Mar 2025 .. contents:: :depth: 3 Basic overview ============== H_HTM is used as an interface for executing Hardware Trace Macro (HTM) functions, incl...	Documentation/arch/powerpc/htm.rst	null	null	null	null	null
source	linux	=============================================================== HVCS IBM "Hypervisor Virtual Console Server" Installation Guide =============================================================== for Linux Kernel 2.6.4+ Copyright (C) 2004 IBM Corporation .. ===============================================================...	Documentation/arch/powerpc/hvcs.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _imc: =================================== IMC (In-Memory Collection Counters) =================================== Anju T Sudhakar, 10 May 2019 .. contents:: :depth: 3 Basic overview ============== IMC (In-Memory collection counters) is a hardware monitoring facility that...	Documentation/arch/powerpc/imc.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ======= powerpc ======= .. toctree:: :maxdepth: 1 associativity booting bootwrapper cpu_families cpu_features dawr-power9 dexcr dscr eeh-pci-error-recovery elf_hwcaps elfnote firmware-assisted-dump htm hvcs imc is...	Documentation/arch/powerpc/index.rst	null	null	null	null	null
source	linux	========================== CPU to ISA Version Mapping ========================== Mapping of some CPU versions to relevant ISA versions. Note Power4 and Power4+ are not supported. ========= ==================================================================== CPU Architecture version ========= ==================...	Documentation/arch/powerpc/isa-versions.rst	null	null	null	null	null
source	linux	KASAN is supported on powerpc on 32-bit and Radix 64-bit only. 32 bit support ============== KASAN is supported on both hash and nohash MMUs on 32-bit. The shadow area sits at the top of the kernel virtual memory space above the fixmap area and occupies one eighth of the total kernel virtual memory space. Instrumen...	Documentation/arch/powerpc/kasan.txt	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =========================== KASLR for Freescale BookE32 =========================== The word KASLR stands for Kernel Address Space Layout Randomization. This document tries to explain the implementation of the KASLR for Freescale BookE32. KASLR is a security feature that deters ex...	Documentation/arch/powerpc/kaslr-booke32.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ==================================== Nested KVM on POWER ==================================== Introduction ============ This document explains how a guest operating system can act as a hypervisor and run nested guests through the use of hypercalls, if the hypervisor has implemente...	Documentation/arch/powerpc/kvm-nested.rst	null	null	null	null	null
source	linux	============================= Linux 2.6.x on MPC52xx family ============================= For the latest info, go to https://www.246tNt.com/mpc52xx/ To compile/use : - U-Boot:: # <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION if you wish to ). # make lite5200_defconfig ...	Documentation/arch/powerpc/mpc52xx.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =========================== Hypercall Op-codes (hcalls) =========================== Overview ========= Virtualization on 64-bit Power Book3S Platforms is based on the PAPR specification [1]_ which describes the run-time environment for a guest operating system and how it should in...	Documentation/arch/powerpc/papr_hcalls.rst	null	null	null	null	null
source	linux	=================================================== PCI Express I/O Virtualization Resource on Powerenv =================================================== Wei Yang <weiyang@linux.vnet.ibm.com> Benjamin Herrenschmidt <benh@au1.ibm.com> Bjorn Helgaas <bhelgaas@google.com> 26 Aug 2014 This document describes the req...	Documentation/arch/powerpc/pci_iov_resource_on_powernv.rst	null	null	null	null	null
source	linux	======================== PMU Event Based Branches ======================== Event Based Branches (EBBs) are a feature which allows the hardware to branch directly to a specified user space address when certain events occur. The full specification is available in Power ISA v2.07: https://www.power.org/documentation/...	Documentation/arch/powerpc/pmu-ebb.rst	null	null	null	null	null
source	linux	====== Ptrace ====== GDB intends to support the following hardware debug features of BookE processors: 4 hardware breakpoints (IAC) 2 hardware watchpoints (read, write and read-write) (DAC) 2 value conditions for the hardware watchpoints (DVC) For that, we need to extend ptrace so that GDB can query and set these re...	Documentation/arch/powerpc/ptrace.rst	null	null	null	null	null
source	linux	========================================= Freescale QUICC Engine Firmware Uploading ========================================= (c) 2007 Timur Tabi <timur at freescale.com>, Freescale Semiconductor .. Table of Contents I - Software License for Firmware II - Microcode Availability III - Description and T...	Documentation/arch/powerpc/qe_firmware.rst	null	null	null	null	null
source	linux	=============================================== Power Architecture 64-bit Linux system call ABI =============================================== syscall ======= Invocation ---------- The syscall is made with the sc instruction, and returns with execution continuing at the instruction following the sc instruction. If ...	Documentation/arch/powerpc/syscall64-abi.rst	null	null	null	null	null
source	linux	============================ Transactional Memory support ============================ POWER kernel support for this feature is currently limited to supporting its use by user programs. It is not currently used by the kernel itself. This file aims to sum up how it is supported by Linux and what behaviour you can exp...	Documentation/arch/powerpc/transactional_memory.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _ultravisor: ============================ Protected Execution Facility ============================ .. contents:: :depth: 3 Introduction ############ Protected Execution Facility (PEF) is an architectural change for POWER 9 that enables Secure Virtual Machines (SVM...	Documentation/arch/powerpc/ultravisor.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _VAS-API: =================================================== Virtual Accelerator Switchboard (VAS) userspace API =================================================== Introduction ============ Power9 processor introduced Virtual Accelerator Switchboard (VAS) which allows both us...	Documentation/arch/powerpc/vas-api.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ======================== VCPU Dispatch Statistics ======================== For Shared Processor LPARs, the POWER Hypervisor maintains a relatively static mapping of the LPAR processors (vcpus) to physical processor chips (representing the "home" node) and tries to always dispatch v...	Documentation/arch/powerpc/vcpudispatch_stats.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ========== Device DAX ========== The device-dax interface uses the tail deduplication technique explained in Documentation/mm/vmemmap_dedup.rst On powerpc, vmemmap deduplication is only used with radix MMU translation. Also with a 64K page size, only the devdax namespace with 1G a...	Documentation/arch/powerpc/vmemmap_dedup.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 .. _vpa-dtl: =================================== DTL (Dispatch Trace Log) =================================== Athira Rajeev, 19 April 2025 .. contents:: :depth: 3 Basic overview ============== The pseries Shared Processor Logical Partition(SPLPAR) machines can retrieve a lo...	Documentation/arch/powerpc/vpa-dtl.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ============== ACPI on RISC-V ============== The ISA string parsing rules for ACPI are defined by `Version ASCIIDOC Conversion, 12/2022 of the RISC-V specifications, as defined by tag "riscv-isa-release-1239329-2023-05-23" (commit 1239329 ) <https://github.com/riscv/riscv-isa-manua...	Documentation/arch/riscv/acpi.rst	null	null	null	null	null
source	linux	================================= Boot image header in RISC-V Linux ================================= :Author: Atish Patra <atish.patra@wdc.com> :Date: 20 May 2019 This document only describes the boot image header details for RISC-V Linux. The following 64-byte header is present in decompressed Linux kernel image...	Documentation/arch/riscv/boot-image-header.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 =============================================== RISC-V Kernel Boot Requirements and Constraints =============================================== :Author: Alexandre Ghiti <alexghiti@rivosinc.com> :Date: 23 May 2023 This document describes what the RISC-V kernel expects from bootload...	Documentation/arch/riscv/boot.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ============================================================================== Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux ============================================================================== CMODX is a programming technique where a prog...	Documentation/arch/riscv/cmodx.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 RISC-V Hardware Probing Interface --------------------------------- The RISC-V hardware probing interface is based around a single syscall, which is defined in <asm/hwprobe.h>:: struct riscv_hwprobe { __s64 key; __u64 value; }; long sys_riscv_hwprobe(s...	Documentation/arch/riscv/hwprobe.rst	null	null	null	null	null
source	linux	=================== RISC-V architecture =================== .. toctree:: :maxdepth: 1 acpi boot boot-image-header vm-layout hwprobe patch-acceptance uabi vector cmodx zicfilp zicfiss features	Documentation/arch/riscv/index.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 arch/riscv maintenance guidelines for developers ================================================ Overview -------- The RISC-V instruction set architecture is developed in the open: in-progress drafts are available for all to review and to experiment with implementations. New modu...	Documentation/arch/riscv/patch-acceptance.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 RISC-V Linux User ABI ===================== ISA string ordering in /proc/cpuinfo ------------------------------------ The canonical order of ISA extension names in the ISA string is defined in Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA (Document Vers...	Documentation/arch/riscv/uabi.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ========================================= Vector Extension Support for RISC-V Linux ========================================= This document briefly outlines the interface provided to userspace by Linux in order to support the use of the RISC-V Vector Extension. 1. prctl() Interfa...	Documentation/arch/riscv/vector.rst	null	null	null	null	null
source	linux	.. SPDX-License-Identifier: GPL-2.0 ===================================== Virtual Memory Layout on RISC-V Linux ===================================== :Author: Alexandre Ghiti <alex@ghiti.fr> :Date: 12 February 2021 This document describes the virtual memory layout used by the RISC-V Linux Kernel. RISC-V Linux Kerne...	Documentation/arch/riscv/vm-layout.rst	null	null	null	null	null

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