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source | linux | .. SPDX-License-Identifier: GPL-2.0
=================================
Devicetree Dynamic Resolver Notes
=================================
This document describes the implementation of the in-kernel
DeviceTree resolver, residing in drivers/of/resolver.c
How the resolver works
----------------------
The resolver is g... | Documentation/devicetree/dynamic-resolution-notes.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
=============================
Open Firmware and Devicetree
=============================
Kernel Devicetree Usage
=======================
.. toctree::
:maxdepth: 1
usage-model
of_unittest
kernel-api
Devicetree Overlays
===================
.. toctree::
:maxdepth: 1
... | Documentation/devicetree/index.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
.. _devicetree:
======================================
DeviceTree Kernel API
======================================
Core functions
--------------
.. kernel-doc:: drivers/of/base.c
:export:
.. kernel-doc:: include/linux/of.h
:internal:
.. kernel-doc:: drivers/of/property.c
... | Documentation/devicetree/kernel-api.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
=================================
Open Firmware Devicetree Unittest
=================================
Author: Gaurav Minocha <gaurav.minocha.os@gmail.com>
1. Introduction
===============
This document explains how the test data required for executing OF unittest
is attached to th... | Documentation/devicetree/of_unittest.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
========================
Devicetree Overlay Notes
========================
This document describes the implementation of the in-kernel
device tree overlay functionality residing in drivers/of/overlay.c and is a
companion document to Documentation/devicetree/dynamic-resolution-notes... | Documentation/devicetree/overlay-notes.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
========================
Linux and the Devicetree
========================
The Linux usage model for device tree data
:Author: Grant Likely <grant.likely@secretlab.ca>
This article describes how Linux uses the device tree. An overview of
the device tree data format can be found ... | Documentation/devicetree/usage-model.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
===================
Devicetree (DT) ABI
===================
I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit
summary document:
"That still leaves the question of, what does a stable binding look
like? Certainly a stable binding means that a ne... | Documentation/devicetree/bindings/ABI.rst | null | null | null | null | null |
source | linux | Common properties
=================
Endianness
----------
The Devicetree Specification does not define any properties related to hardware
byte swapping, but endianness issues show up frequently in porting drivers to
different machine types. This document attempts to provide a consistent
way of handling byte swapping... | Documentation/devicetree/bindings/common-properties.txt | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
=====================================
Devicetree Sources (DTS) Coding Style
=====================================
When writing Devicetree Sources (DTS) please observe below guidelines. They
should be considered complementary to any rules expressed already in
the Devicetree Specifi... | Documentation/devicetree/bindings/dts-coding-style.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
.. toctree::
:maxdepth: 1
ABI
dts-coding-style
writing-bindings
writing-schema
submitting-patches | Documentation/devicetree/bindings/index.rst | null | null | null | null | null |
source | linux | Jailhouse non-root cell device tree bindings
--------------------------------------------
When running in a non-root Jailhouse cell (partition), the device tree of this
platform shall have a top-level "hypervisor" node with the following
properties:
- compatible = "jailhouse,cell" | Documentation/devicetree/bindings/jailhouse.txt | null | null | null | null | null |
source | linux | Some properties contain an ordered list of 1 or more datum which are
normally accessed by index. However, some devices will have multiple
values which are more naturally accessed by name. Device nodes can
include a supplemental property for assigning names to each of the list
items. The names property consists of a ... | Documentation/devicetree/bindings/resource-names.txt | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
==========================================
Submitting Devicetree (DT) binding patches
==========================================
I. For patch submitters
=======================
0) Normal patch submission rules from
Documentation/process/submitting-patches.rst applies.
1)... | Documentation/devicetree/bindings/submitting-patches.rst | null | null | null | null | null |
source | linux | 1) OF unittest platform device
** unittest
Required properties:
- compatible: must be "unittest"
All other properties are optional.
Example:
unittest {
compatible = "unittest";
};
2) OF unittest i2c adapter platform device
** platform device unittest adapter
Required properties:
- compatible: must be unittes... | Documentation/devicetree/bindings/unittest.txt | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
============================================================
DOs and DON'Ts for designing and writing Devicetree bindings
============================================================
This is a list of common review feedback items focused on binding design. With
every rule, there ar... | Documentation/devicetree/bindings/writing-bindings.rst | null | null | null | null | null |
source | linux | .. SPDX-License-Identifier: GPL-2.0
Writing Devicetree Bindings in json-schema
==========================================
Devicetree bindings are written using json-schema vocabulary. Schema files are
written in a JSON-compatible subset of YAML. YAML is used instead of JSON as it
is considered more human readable and... | Documentation/devicetree/bindings/writing-schema.rst | null | null | null | null | null |
source | linux | d) Xilinx IP cores
The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
of standard device types (network, serial, etc.) and miscellaneous
devices (gpio, LCD, spi, etc). Also, since these devices are
implemented w... | Documentation/devicetree/bindings/xilinx.txt | null | null | null | null | null |
source | linux | Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
---------------------------------------------------------------------------
SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
Required root node properties:
- compatible = "snps,axs101", "snps,arc-sdp"; | Documentation/devicetree/bindings/arc/axs101.txt | null | null | null | null | null |
source | linux | Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
---------------------------------------------------------------------------
SDP Main Board with an AXC003 FPGA Card which can contain various flavours of
HS38x cores.
Required root node properties:
- compatible = "snps,axs103", "snps,arc-... | Documentation/devicetree/bindings/arc/axs103.txt | null | null | null | null | null |
source | linux | EZchip NPS Network Processor Platforms Device Tree Bindings
---------------------------------------------------------------------------
Appliance main board with NPS400 ASIC.
Required root node properties:
- compatible = "ezchip,arc-nps"; | Documentation/devicetree/bindings/arc/eznps.txt | null | null | null | null | null |
source | linux | Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
---------------------------------------------------------------------------
ARC HSDK Board with quad-core ARC HS38x4 in silicon.
Required root node properties:
- compatible = "snps,hsdk"; | Documentation/devicetree/bindings/arc/hsdk.txt | null | null | null | null | null |
source | linux | * ARC Performance Counters
The ARC700 can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
are 100+ hardware conditions dynamically mapped to up to 32 counters
Note that:
* The ARC 700 PCT does not support interrupts; although... | Documentation/devicetree/bindings/arc/pct.txt | null | null | null | null | null |
source | linux | Atmel system registers
Chipid required properties:
- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
"microchip,sama7d65-chipid"
- reg : Should contain registers location and length
PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain regis... | Documentation/devicetree/bindings/arm/atmel-sysregs.txt | null | null | null | null | null |
source | linux | * ARM Secure world bindings
ARM CPUs with TrustZone support have two distinct address spaces,
"Normal" and "Secure". Most devicetree consumers (including the Linux
kernel) are not TrustZone aware and run entirely in either the Normal
world or the Secure world. However some devicetree consumers are
TrustZone aware and ... | Documentation/devicetree/bindings/arm/secure.txt | null | null | null | null | null |
source | linux | ST-Ericsson Nomadik Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs.
Required root node property: src
- Nomadik System and reset controller used for basic chip control, clock
and reset line control.
- compati... | Documentation/devicetree/bindings/arm/ste-nomadik.txt | null | null | null | null | null |
source | linux | ARM Versatile Express Serial Configuration Controller
-----------------------------------------------------
Test chips for ARM Versatile Express platform implement SCC (Serial
Configuration Controller) interface, used to set initial conditions
for the test chip.
In some cases its registers are also mapped in normal a... | Documentation/devicetree/bindings/arm/vexpress-scc.txt | null | null | null | null | null |
source | linux | * Xen hypervisor device tree bindings
Xen ARM virtual platforms shall have a top-level "hypervisor" node with
the following properties:
- compatible:
compatible = "xen,xen-<version>", "xen,xen";
where <version> is the version of the Xen ABI of the platform.
- reg: specifies the base physical address and size of t... | Documentation/devicetree/bindings/arm/xen.txt | null | null | null | null | null |
source | linux | Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
-----------------------------------------------------------
Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
following properties:
Required root node property:
compatible: should be "brcm,bcm63138"
An optional Boot lookup table Devi... | Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt | null | null | null | null | null |
source | linux | ARM Broadcom STB platforms Device Tree Bindings
-----------------------------------------------
Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
SoC shall have the following DT organization:
Required root node properties:
- compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
example:
/ {
... | Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | null | null | null | null | null |
source | linux | * Software Delegated Exception Interface (SDEI)
Firmware implementing the SDEI functions described in ARM document number
ARM DEN 0054A ("Software Delegated Exception Interface") can be used by
Linux to receive notification of events such as those generated by
firmware-first error handling, or from an IRQ that has bee... | Documentation/devicetree/bindings/arm/firmware/sdei.txt | null | null | null | null | null |
source | linux | Resume Control
--------------
Available on Marvell SOCs: 98DX3336 and 98DX4251
Required properties:
- compatible: must be "marvell,98dx3336-resume-ctrl"
- reg: Should contain resume control registers location and length
Example:
resume@20980 {
compatible = "marvell,98dx3336-resume-ctrl";
reg = <0x20980 0x10>;
}; | Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt | null | null | null | null | null |
source | linux | Power Management Service Unit(PMSU)
-----------------------------------
Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
Required properties:
- compatible: should be one of:
- "marvell,armada-370-pmsu" for Armada 370 or Armada XP
- "marvell,armada-380-pmsu" for Armada 38x
- "marvell,armada-370-xp... | Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt | null | null | null | null | null |
source | linux | Marvell Armada 38x CA9 MPcore SoC Controller
============================================
Required properties:
- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
- reg: should be the register base and length as documented in the
datasheet for the CA9 MPcore SoC Control registers
mpcore-soc-ctrl@20d20 {... | Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt | null | null | null | null | null |
source | linux | Marvell Armada CPU reset controller
===================================
Required properties:
- compatible: Should be "marvell,armada-370-cpu-reset".
- reg: should be register base and length as documented in the
datasheet for the CPU reset registers
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-c... | Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt | null | null | null | null | null |
source | linux | Coherency fabric
----------------
Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP
Required properties:
- compatible: the possible values are:
* "marvell,coherency-fabric", to be used for the coherency fabric of
the Armada 370 and Armada XP.
* "marvell,armada-375-coherency-fabric", f... | Documentation/devicetree/bindings/arm/marvell/coherency-fabric.txt | null | null | null | null | null |
source | linux | MVEBU CPU Config registers
--------------------------
MVEBU (Marvell SOCs: Armada 370/XP)
Required properties:
- compatible: one of:
- "marvell,armada-370-cpu-config"
- "marvell,armada-xp-cpu-config"
- reg: Should contain CPU config registers location and length, in
their per-CPU variant
Example:
cpu-config@... | Documentation/devicetree/bindings/arm/marvell/mvebu-cpu-config.txt | null | null | null | null | null |
source | linux | MVEBU System Controller
-----------------------
MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
Required properties:
- compatible: one of:
- "marvell,orion-system-controller"
- "marvell,armada-370-xp-system-controller"
- "marvell,armada-375-system-controller"
- reg: Should contain system ... | Documentation/devicetree/bindings/arm/marvell/mvebu-system-controller.txt | null | null | null | null | null |
source | linux | MediaTek g3dsys controller
============================
The MediaTek g3dsys controller provides various clocks and reset controller to
the GPU.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-g3dsys", "syscon":
for MT2701 SoC
- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
for ... | Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt | null | null | null | null | null |
source | linux | OMAP Counter-32K bindings
Required properties:
- compatible: Must be "ti,omap-counter32k" for OMAP controllers
- reg: Contains timer register address range (base address and length)
- ti,hwmods: Name of the hwmod associated to the counter, which is typically
"counter_32k"
Example:
counter32k: counter@4a304000 {
... | Documentation/devicetree/bindings/arm/omap/counter.txt | null | null | null | null | null |
source | linux | Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSB... | Documentation/devicetree/bindings/arm/omap/crossbar.txt | null | null | null | null | null |
source | linux | OMAP Control Module bindings
Control Module contains miscellaneous features under it based on SoC type.
Pincontrol is one common feature, and it has a specialized support
described in [1]. Typically some clock nodes are also under control module.
Syscon is used to share register level access to drivers external to
con... | Documentation/devicetree/bindings/arm/omap/ctrl.txt | null | null | null | null | null |
source | linux | OMAP Dynamic Memory Manager (DMM) bindings
The dynamic memory manager (DMM) is a module located immediately in front of the
SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
accesses such as priority generation amongst initiators, configuration of SDRAM
interleaving, optimizing transfer o... | Documentation/devicetree/bindings/arm/omap/dmm.txt | null | null | null | null | null |
source | linux | * TI - DSP (Digital Signal Processor)
TI DSP included in OMAP SoC
Required properties:
- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
- ti,hwmods: "dsp"
Examples:
dsp {
compatible = "ti,omap3-c64";
ti,hwmods = "dsp";
}; | Documentation/devicetree/bindings/arm/omap/dsp.txt | null | null | null | null | null |
source | linux | * TI - IVA (Imaging and Video Accelerator) subsystem
The IVA contain various audio, video or imaging HW accelerator
depending of the version.
Required properties:
- compatible : Should be:
- "ti,ivahd" for OMAP4
- "ti,iva2.2" for OMAP3
- "ti,iva2.1" for OMAP2430
- "ti,iva1" for OMAP2420
- ti,hwmods: "iva"
Ex... | Documentation/devicetree/bindings/arm/omap/iva.txt | null | null | null | null | null |
source | linux | * TI - L3 Network On Chip (NoC)
This version is an implementation of the generic NoC IP
provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
Should be "ti,omap5-l3-noc" for OMAP5 family
... | Documentation/devicetree/bindings/arm/omap/l3-noc.txt | null | null | null | null | null |
source | linux | L4 interconnect bindings
These bindings describe the OMAP SoCs L4 interconnect bus.
Required properties:
- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Shoul... | Documentation/devicetree/bindings/arm/omap/l4.txt | null | null | null | null | null |
source | linux | * TI - MPU (Main Processor Unit) subsystem
The MPU subsystem contain one or several ARM cores
depending of the version.
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
Required properties:
- compatible : Should be "ti,omap3-mpu" for OMAP3
Should be "ti,omap4-mpu" for OMAP4
Should be "ti,o... | Documentation/devicetree/bindings/arm/omap/mpu.txt | null | null | null | null | null |
source | linux | * Texas Instruments OMAP
OMAP is currently using a static file per SoC family to describe the
IPs present in the SoC.
On top of that an omap_device is created to extend the platform_device
capabilities and to allow binding with one or several hwmods.
The hwmods will contain all the information to build the device:
add... | Documentation/devicetree/bindings/arm/omap/omap.txt | null | null | null | null | null |
source | linux | OMAP PRCM bindings
Power Reset and Clock Manager lists the device clocks and clockdomains under
a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
each describing one module and the clock hierarchy under it. see [1] for
documentation about the individual clock/clockdomain nodes.
[1] Documentat... | Documentation/devicetree/bindings/arm/omap/prcm.txt | null | null | null | null | null |
source | linux | ST-Ericsson Ux500 boards
------------------------
Required properties (in root node) one of these:
compatible = "st-ericsson,mop500" (legacy)
compatible = "st-ericsson,u8500"
Required node (under root node):
soc: represents the system-on-chip and contains the chip
peripherals
Required property of soc node, one of... | Documentation/devicetree/bindings/arm/ux500/boards.txt | null | null | null | null | null |
source | linux | * ST-Ericsson UX500 PM Domains
UX500 supports multiple PM domains which are used to gate power to one or
more peripherals on the SOC.
The implementation of PM domains for UX500 are based upon the generic PM domain
and use the corresponding DT bindings.
==PM domain providers==
Required properties:
- compatible: Mus... | Documentation/devicetree/bindings/arm/ux500/power_domain.txt | null | null | null | null | null |
source | linux | VIA/Wondermedia VT8500 Power Management Controller
-----------------------------------------------------
Required properties:
- compatible : "via,vt8500-pmc"
- reg : Should contain 1 register ranges(address and length)
Example:
pmc@d8130000 {
compatible = "via,vt8500-pmc";
reg = <0xd8130000 0x1000>;
}; | Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt | null | null | null | null | null |
source | linux | Driver for ARM AXI Bus with Broadcom Plugins (bcma)
Required properties:
- compatible : brcm,bus-axi
- reg : iomem address range of chipcommon core
The cores on the AXI bus are automatically detected by bcma with the
memory ranges they are using and they get registered afterwards.
Automatic detection of the IRQ num... | Documentation/devicetree/bindings/bus/brcm,bus-axi.txt | null | null | null | null | null |
source | linux | * Marvell MBus
Required properties:
- compatible: Should be set to one of the following:
marvell,armada370-mbus
marvell,armadaxp-mbus
marvell,armada375-mbus
marvell,armada380-mbus
marvell,kirkwood-mbus
marvell,dove-mbus
marvell,orion5x-88f5281-mbus
marvell,orion5x-88f5182-mbus
marvell,orio... | Documentation/devicetree/bindings/bus/mvebu-mbus.txt | null | null | null | null | null |
source | linux | Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
The Generic Memory Interface bus enables memory transfers between internal and
external memory. Can be used to attach various high speed devices such as
synchronous/asynchronous NOR, FPGA, UARTS and more.
The actual devices are instantiated from the c... | Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt | null | null | null | null | null |
source | linux | * OMAP OCP2SCP - ocp interface to scp interface
properties:
- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
Should be "ti,omap-ocp2scp" for all others
- reg : Address and length of the register set for the device
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ra... | Documentation/devicetree/bindings/bus/omap-ocp2scp.txt | null | null | null | null | null |
source | linux | * Device tree bindings for Texas Instruments da8xx master peripheral
priority driver
DA8XX SoCs feature a set of registers allowing to change the priority of all
peripherals classified as masters.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
Required properties:
- compatible: ... | Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt | null | null | null | null | null |
source | linux | Technologic Systems NBUS
The NBUS is a bus used to interface with peripherals in the Technologic
Systems FPGA on the TS-4600 SoM.
Required properties :
- compatible : "technologic,ts-nbus"
- #address-cells : must be 1
- #size-cells : must be 0
- pwms : The PWM bound to the FPGA
- ts,data-gpios : The 8 GPIO p... | Documentation/devicetree/bindings/bus/ts-nbus.txt | null | null | null | null | null |
source | linux | Freescale L2 Cache Controller
L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
The cache bindings explained below are Devicetree Specification compliant
Required Properties:
- compatible : Should include one of the following:
"fsl,b4420-l2-cache-controller"
"fsl,b4860-l2-cache-controlle... | Documentation/devicetree/bindings/cache/freescale-l2cache.txt | null | null | null | null | null |
source | linux | Binding for the AXS10X I2S PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: shall be "snps,axs10x-i2s-pll-clock"
- reg : address and length of the I2S PLL register set.
- clocks: shall be the input parent clock ... | Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt | null | null | null | null | null |
source | linux | * Palmas 32KHz clocks *
Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
This binding uses the common clock binding ./clock-bindings.txt.
Required properties:
- compatible : "ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock
- #clock-cells : shall be set to 0.
... | Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt | null | null | null | null | null |
source | linux | This file has moved to the clock binding schema:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml | Documentation/devicetree/bindings/clock/clock-bindings.txt | null | null | null | null | null |
source | linux | * Hisilicon Hi3660 Clock Controller
The Hi3660 clock controller generates and supplies clock to various
controllers within the Hi3660 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3660-crgctrl"
- "hisil... | Documentation/devicetree/bindings/clock/hi3660-clock.txt | null | null | null | null | null |
source | linux | * Hisilicon Hi3670 Clock Controller
The Hi3670 clock controller generates and supplies clock to various
controllers within the Hi3670 SoC.
Required Properties:
- compatible: the compatible should be one of the following strings to
indicate the clock controller functionality.
- "hisilicon,hi3670-crgctrl"
- "hisil... | Documentation/devicetree/bindings/clock/hi3670-clock.txt | null | null | null | null | null |
source | linux | * Hisilicon Hi6220 Clock Controller
Clock control registers reside in different Hi6220 system controllers,
please refer the following document to know more about the binding rules
for these system controllers:
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
Required Properties:
- compatible: the comp... | Documentation/devicetree/bindings/clock/hi6220-clock.txt | null | null | null | null | null |
source | linux | * HiSilicon Clock and Reset Generator(CRG)
The CRG module provides clock and reset signals to various
modules within the SoC.
This binding uses the following bindings:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Documentation/devicetree/bindings/reset/reset.txt
Required Properties:
- compatib... | Documentation/devicetree/bindings/clock/hisi-crg.txt | null | null | null | null | null |
source | linux | Binding for Imagination Technologies MIPS Boston clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
The device node must be a child node of the syscon node corresponding to the
Boston system's platform registers.
Required properties:
- compat... | Documentation/devicetree/bindings/clock/img,boston-clock.txt | null | null | null | null | null |
source | linux | Binding for Keystone gate control driver which uses PSC controller IP.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,keystone,psc-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- c... | Documentation/devicetree/bindings/clock/keystone-gate.txt | null | null | null | null | null |
source | linux | Binding for keystone PLLs. The main PLL IP typically has a multiplier,
a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
and PAPLL are controlled by the memory mapped register where as the Main
PLL is controlled by a PLL controller registers along with memory mapped
registers.
This binding uses ... | Documentation/devicetree/bindings/clock/keystone-pll.txt | null | null | null | null | null |
source | linux | * Marvell PXA168 Clock Controller
The PXA168 clock subsystem generates and supplies clock to various
controllers within the PXA168 SoC.
Required Properties:
- compatible: should be one of the following.
- "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
- reg: physical base address of the clock sub... | Documentation/devicetree/bindings/clock/marvell,pxa168.txt | null | null | null | null | null |
source | linux | * Marvell PXA1928 Clock Controllers
The PXA1928 clock subsystem generates and supplies clock to various
controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
blocks called APMU, MPMU, and APBC roughly corresponding to internal buses.
Required Properties:
- compatible: should be one of the follo... | Documentation/devicetree/bindings/clock/marvell,pxa1928.txt | null | null | null | null | null |
source | linux | * Marvell PXA910 Clock Controller
The PXA910 clock subsystem generates and supplies clock to various
controllers within the PXA910 SoC.
Required Properties:
- compatible: should be one of the following.
- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
- reg: physical base address of the clock sub... | Documentation/devicetree/bindings/clock/marvell,pxa910.txt | null | null | null | null | null |
source | linux | NVIDIA Tegra124 DFLL FCPU clocksource
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU vol... | Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | null | null | null | null | null |
source | linux | * Clock bindings for Marvell PXA chips
Required properties:
- compatible: Should be "marvell,pxa-clocks"
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell (see include/.../pxa-clock.h).
Examples:
pxa2xx_clks: pxa2xx_clks@41300004 {
... | Documentation/devicetree/bindings/clock/pxa-clock.txt | null | null | null | null | null |
source | linux | Binding for the HSDK Generic PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: should be "snps,hsdk-<name>-pll-clock"
"snps,hsdk-core-pll-clock"
"snps,hsdk-gp-pll-clock"
"snps,hsdk-hdmi-pll-clock"
- reg : s... | Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt | null | null | null | null | null |
source | linux | Binding for the AXS10X Generic PLL clock
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: should be "snps,axs10x-<name>-pll-clock"
"snps,axs10x-arc-pll-clock"
"snps,axs10x-pgu-pll-clock"
- reg: should always contain 2... | Documentation/devicetree/bindings/clock/snps,pll-clock.txt | null | null | null | null | null |
source | linux | ST Microelectronics Nomadik SRC System Reset and Control
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The Nomadik SRC controller is responsible of controlling chrystals,
PLLs and clock gates.
Required properties for the SRC node:
- compatible: must be "steric... | Documentation/devicetree/bindings/clock/st,nomadik.txt | null | null | null | null | null |
source | linux | Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
synthesizer/multiplier/divider.
Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf
I2C device node required properties:
- compatible: shall be "ti,cdce706".
- reg: i2c device address, shall be in range [0x68...0x6b].
- #clock-cells: from common clo... | Documentation/devicetree/bindings/clock/ti,cdce706.txt | null | null | null | null | null |
source | linux | Device Tree Clock bindings for arch-vt8500
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
"wm,wm8650-pll-clock" - for a WM8650 PLL... | Documentation/devicetree/bindings/clock/vt8500.txt | null | null | null | null | null |
source | linux | Device Tree Clock bindings for the Zynq 7000 EPP
The Zynq EPP has several different clk providers, each with there own bindings.
The purpose of this document is to document their usage.
See clock_bindings.txt for more information on the generic clock bindings.
See Chapter 25 of Zynq TRM for more information about Zyn... | Documentation/devicetree/bindings/clock/zynq-7000.txt | null | null | null | null | null |
source | linux | Binding for a ST multiplexed clock driver.
This binding supports only simple indexed multiplexers, it does not
support table based parent index to hardware value translations.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compat... | Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt | null | null | null | null | null |
source | linux | Binding for a ST pll clock driver.
This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
Required properties:
- compatible : shall be:... | Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | null | null | null | null | null |
source | linux | Binding for a Clockgen hardware block found on
certain STMicroelectronics consumer electronics SoC devices.
A Clockgen node can contain pll, diviser or multiplexer nodes.
We will find only the base address of the Clockgen, this base
address is common of all subnode.
clockgen_node {
reg = <>;
pll_node {
...
... | Documentation/devicetree/bindings/clock/st/st,clkgen.txt | null | null | null | null | null |
source | linux | Binding for a type of flexgen structure found on certain
STMicroelectronics consumer electronics SoC devices
This structure includes:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Flexgen structure is a part of Clockgen[1].
Please find an e... | Documentation/devicetree/bindings/clock/st/st,flexgen.txt | null | null | null | null | null |
source | linux | Binding for a type of quad channel digital frequency synthesizer found on
certain STMicroelectronics consumer electronics SoC devices.
This version contains a programmable PLL which can generate up to 216, 432
or 660MHz (from a 30MHz oscillator input) as the input to the digital
synthesizers.
This binding uses the co... | Documentation/devicetree/bindings/clock/st/st,quadfs.txt | null | null | null | null | null |
source | linux | Binding for Texas Instruments ADPLL clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped ADPLL with two to three selectable input clocks
and three to four children.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of "ti,dm8... | Documentation/devicetree/bindings/clock/ti/adpll.txt | null | null | null | null | null |
source | linux | Binding for Texas Instruments APLL clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typical... | Documentation/devicetree/bindings/clock/ti/apll.txt | null | null | null | null | null |
source | linux | Binding for Texas Instruments clockdomain.
This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
their parent clockdomain to be controlled when the clock is
enabled/disabled. This bind... | Documentation/devicetree/bindings/clock/ti/clockdomain.txt | null | null | null | null | null |
source | linux | Binding for Texas Instruments DPLL clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped DPLL with usually two selectable input clocks
(reference clock and bypass clock), with digital phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typica... | Documentation/devicetree/bindings/clock/ti/dpll.txt | null | null | null | null | null |
source | linux | Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
The ATL IP is used to generate clock to be used to synchronize baseband and
audio codec. A single ATL IP provides four ATL clock instances sharing the same
functional clock but can be configured to provide different clocks.
ATL can maintain a clock... | Documentation/devicetree/bindings/clock/ti/dra7-atl.txt | null | null | null | null | null |
source | linux | Binding for Texas Instruments FAPLL clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped FAPLL with usually two selectable input clocks
(reference clock and bypass clock), and one or more child
syntesizers.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properti... | Documentation/devicetree/bindings/clock/ti/fapll.txt | null | null | null | null | null |
source | linux | Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
registers call CFGCHIPn. Some of these registers function as clock
gates. This document describes the bindings for those clocks.
All of the clock nodes described below must be child nodes... | Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip.txt | null | null | null | null | null |
source | linux | Binding for TI DaVinci PLL Controllers
The PLL provides clocks to most of the components on the SoC. In addition
to the PLL itself, this controller also contains bypasses, gates, dividers,
an multiplexers for various clock signals.
Required properties:
- compatible: shall be one of:
- "ti,da850-pll0" for PLL0 on DA8... | Documentation/devicetree/bindings/clock/ti/davinci/pll.txt | null | null | null | null | null |
source | linux | Binding for TI DaVinci Power Sleep Controller (PSC)
The PSC provides power management, clock gating and reset functionality. It is
primarily used for clocking.
Required properties:
- compatible: shall be one of:
- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18X... | Documentation/devicetree/bindings/clock/ti/davinci/psc.txt | null | null | null | null | null |
source | linux | ==========================================
CPU capacity bindings
==========================================
==========================================
1 - Introduction
==========================================
Some systems may be configured to have cpus with different power/performance
characteristics within the sam... | Documentation/devicetree/bindings/cpu/cpu-capacity.txt | null | null | null | null | null |
source | linux | Broadcom AVS mail box and interrupt register bindings
=====================================================
A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
references the mailbox register used to communicate with the AVS CPU[1]. The
second node (brcm,avs-cpu-l2-intr) is required to trigger an ... | Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt | null | null | null | null | null |
source | linux | SPEAr cpufreq driver
-------------------
SPEAr SoC cpufreq driver for CPU frequency scaling.
It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems
which share clock across all CPUs.
Required properties:
- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
increasing ord... | Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt | null | null | null | null | null |
source | linux | Binding for ST's CPUFreq driver
===============================
ST's CPUFreq driver attempts to read 'process' and 'version' attributes
from the SoC, then supplies the OPP framework with 'prop' and 'supported
hardware' information respectively. The framework is then able to read
the DT and operate in the usual way.
... | Documentation/devicetree/bindings/cpufreq/cpufreq-st.txt | null | null | null | null | null |
source | linux | i.MX CPUFreq-DT OPP bindings
================================
Certain i.MX SoCs support different OPPs depending on the "market segment" and
"speed grading" value which are written in fuses. These bits are combined with
the opp-supported-hw values for each OPP to check if the OPP is allowed.
Required properties:
----... | Documentation/devicetree/bindings/cpufreq/imx-cpufreq-dt.txt | null | null | null | null | null |
source | linux | Tegra124 CPU frequency scaling driver bindings
----------------------------------------------
Both required and optional properties listed below must be defined
under node /cpus/cpu@0.
Required properties:
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
-... | Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | null | null | null | null | null |
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