repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
mi2bjss/Pressel-site | 34,239 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/sha256-armv8-linux64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__ELF__)
// Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under ... |
mi2bjss/Pressel-site | 26,206 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/vpaes-armv8-linux64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__ELF__)
.section .rodata
.type _vpaes_consts,%object
.align 7 // totally strategic alignment
_vpaes_c... |
mi2bjss/Pressel-site | 28,780 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/chacha-armv4-linux32.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__)
@ Silence ARMv8 deprecated IT instruction warnings. This file is used by both
@ ARMv7 and ARMv8 pr... |
mi2bjss/Pressel-site | 68,707 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/p256-x86_64-asm-macosx.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && defined(__APPLE__)
.text
.section __DATA,__const
.p2align 6
L$poly:
.quad 0xffffffffffffffff, 0x00000000fffff... |
mi2bjss/Pressel-site | 23,124 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/vpaes-armv7-linux32.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__)
.syntax unified
.arch armv7-a
.fpu neon
#if defined(__thumb2__)
.thumb
#else
.code 32
#endif
.t... |
mi2bjss/Pressel-site | 7,650 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/aesv8-armx-ios64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__APPLE__)
#if __ARM_MAX_ARCH__>=7
.text
.section __TEXT,__const
.align 5
Lrcon:
.long 0x01,0x01,0x01,... |
mi2bjss/Pressel-site | 36,746 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/p256-armv8-asm-linux64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__ELF__)
.section .rodata
.align 5
.Lpoly:
.quad 0xffffffffffffffff,0x00000000ffffffff,0x00000000000000... |
mi2bjss/Pressel-site | 9,958 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/vpaes-x86-elf.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
#ifdef BORINGSSL_DISPATCH_TEST
#endif
.align 64
.L_vpaes_consts:
.long 218628480,235210255,1... |
mi2bjss/Pressel-site | 82,152 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/aesv8-gcm-armv8-ios64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__APPLE__)
#if __ARM_MAX_ARCH__ >= 8
.text
.globl _aes_gcm_enc_kernel
.private_extern _aes_gcm_enc_ke... |
mi2bjss/Pressel-site | 49,024 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/sha512-armv8-ios64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(__APPLE__)
// Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed unde... |
mi2bjss/Pressel-site | 7,660 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/pregenerated/aesv8-armx-win64.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#if __ARM_MAX_ARCH__>=7
.text
.arch armv8-a+crypto
.section .rodata
.align 5
Lrcon:
.long 0x01,... |
mi2bjss/Pressel-site | 2,659 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/third_party/fiat/asm/fiat_curve25519_adx_square.S | #include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \
(defined(__APPLE__) || defined(__ELF__))
.intel_syntax noprefix
.text
#if defined(__APPLE__)
.private_extern _fiat_curve25519_adx_square
.global _fiat_curve25519_adx_square
_fiat_curve25519_adx_square:
#else
.type fiat_cu... |
mi2bjss/Pressel-site | 3,464 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/third_party/fiat/asm/fiat_curve25519_adx_mul.S | #include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64) && \
(defined(__APPLE__) || defined(__ELF__))
.intel_syntax noprefix
.text
#if defined(__APPLE__)
.private_extern _fiat_curve25519_adx_mul
.global _fiat_curve25519_adx_mul
_fiat_curve25519_adx_mul:
#else
.type fiat_curve25519_... |
mi2bjss/Pressel-site | 62,534 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/crypto/poly1305/poly1305_arm_asm.S | #include <ring-core/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__)
#pragma GCC diagnostic ignored "-Wlanguage-extension-token"
# This implementation was taken from the public domain, neon2 version in
# SUPERCOP by D. J. Bernstein and Peter Schwabe.
# qhasm: int32 input_0
# qha... |
mi2bjss/Pressel-site | 41,448 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/ring-0.17.13/crypto/curve25519/asm/x25519-asm-arm.S | // Copyright 2015 The BoringSSL Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or ag... |
mi2bjss/Pressel-site | 6,761 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/lzma-sys-0.1.20/xz-5.2/src/liblzma/check/crc64_x86.S | /*
* Speed-optimized CRC64 using slicing-by-four algorithm
*
* This uses only i386 instructions, but it is optimized for i686 and later
* (including e.g. Pentium II/III/IV, Athlon XP, and Core 2).
*
* Authors: Igor Pavlov (original CRC32 assembly code)
* Lasse Collin (CRC64 adaptation of the modified CR... |
mi2bjss/Pressel-site | 7,228 | .cargo/registry/src/index.crates.io-6f17d22bba15001f/lzma-sys-0.1.20/xz-5.2/src/liblzma/check/crc32_x86.S | /*
* Speed-optimized CRC32 using slicing-by-eight algorithm
*
* This uses only i386 instructions, but it is optimized for i686 and later
* (including e.g. Pentium II/III/IV, Athlon XP, and Core 2). For i586
* (e.g. Pentium), slicing-by-four would be better, and even the C version
* of slicing-by-eight built with ... |
MikelB03/TFM_Mikel_Barrena | 4,085 | RISC-V/R9A02G021_c/src/smc_gen/r_bsp/mcu/all/start.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
MikelB03/TFM_Mikel_Barrena | 2,545 | RISC-V/R9A02G021_c/src/smc_gen/r_bsp/mcu/all/r_bsp_common_llvm.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
MikelB03/TFM_Mikel_Barrena | 2,451 | RISC-V/R9A02G021_c/src/smc_gen/r_bsp/mcu/all/exit.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
MikelB03/TFM_Mikel_Barrena | 4,085 | RISC-V/R9A02G021_fromScilab/src/smc_gen/r_bsp/mcu/all/start.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
MikelB03/TFM_Mikel_Barrena | 2,545 | RISC-V/R9A02G021_fromScilab/src/smc_gen/r_bsp/mcu/all/r_bsp_common_llvm.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
MikelB03/TFM_Mikel_Barrena | 2,451 | RISC-V/R9A02G021_fromScilab/src/smc_gen/r_bsp/mcu/all/exit.s | ;;/***********************************************************************************************************************
;;* DISCLAIMER
;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
;;* other uses are authorized. This software is owned by Rene... |
mikotopku/os | 4,414 | src/link_app.S |
.align 3
.section .data
.global _num_app
_num_app:
.quad 19
.quad app_0_start
.quad app_1_start
.quad app_2_start
.quad app_3_start
.quad app_4_start
.quad app_5_start
.quad app_6_start
.quad app_7_start
.quad app_8_start
.quad app_9_start
.quad app_10_start
... |
mikotopku/os | 1,640 | src/trap/trap.S | .altmacro
.macro SAVE_GP n
sd x\n, \n*8(sp)
.endm
.macro LOAD_GP n
ld x\n, \n*8(sp)
.endm
.section .text.trampoline
.globl __alltraps
.globl __restore
.align 2
__alltraps:
csrrw sp, sscratch, sp
# now sp->*TrapContext in user space, sscratch->user stack
# save other general purpose r... |
minhcly95/riscv_sim | 7,563 | asm/src/int_test.s | .global _start
.text
_start:
# Load the base addr of the trace array
li x31, 0x00001000
# Load 2 random 32-bit numbers
li x1, 0xbcfec832
li x2, 0x51290ce3
# ---------------- OP-IMM -----------------
# ADDI
addi x3, x1, 0xfffff89b # Should be 0xbcfec0cd
sw x3, 0(x31)
... |
minhcly95/riscv_sim | 3,170 | asm/src/mul_test.s | .global _start
.text
_start:
# Load the base addr of the trace array
li x31, 0x00001000
# Load 2 random 32-bit numbers
li x1, 0xbcfec832
li x2, 0x51290ce3
# ----------------- MUL -------------------
# MUL x1 * x2
mul x3, x1, x2 # Should be 0x694fdc56
sw x3, ... |
minhcly95/riscv_sim | 1,044 | asm/src/csr_test.s | .global _start
.text
_start:
# Load the base addr of the trace array
li x31, 0x00001000
# Load some random 32-bit numbers
li x1, 0xbcfec832
li x2, 0x51290ce3
li x4, 0x0e27d515
# ----------------- MUL -------------------
# CSRRW
csrw mscratch, x4
csrrw x3, mscr... |
minhcly95/riscv_sim | 3,416 | asm/src/amo_test.s | .global _start
.text
_start:
# Load the base addr of the trace array
li x31, 0x00001000
# Load 2 random 32-bit numbers
li x1, 0xbcfec832
li x2, 0x51290ce3
# ----------------- AMO -------------------
# AMOSWAP
sw x1, (x31)
amoswap.w x3, x2, (x31) # Should ... |
minhcly95/riscv_sim | 3,361 | asm/src/lrsc_test.s | .global _start
.text
_start:
# Load the base addr of the trace array
li x31, 0x00001000
# Addr to test lr/sc
li x30, 0x00000ffc # Main addr
li x29, 0x00000ff8 # Other addr
# Load 2 random 32-bit numbers
li x1, 0xbcfec832
li x2, 0x51290ce3
# --------------- LR -... |
mintair-xyz/succinct-sp1 | 11,855 | crates/zkvm/entrypoint/src/memcpy.s | // This is musl-libc commit 37e18b7bf307fa4a8c745feebfcba54a0ba74f30:
//
// src/string/memcpy.c
//
// This was compiled into assembly with:
//
// clang-14 -target riscv32 -march=rv32im -O3 -S memcpy.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a whole is ... |
mintair-xyz/succinct-sp1 | 8,450 | crates/zkvm/entrypoint/src/memset.s | // This is musl-libc memset commit 37e18b7bf307fa4a8c745feebfcba54a0ba74f30:
//
// src/string/memset.c
//
// This was compiled into assembly with:
//
// clang-14 -target riscv32 -march=rv32im -O3 -S memset.c -nostdlib -fno-builtin -funroll-loops
//
// and labels manually updated to not conflict.
//
// musl as a wh... |
MissBiwott25/comprehensive-rust. | 4,676 | src/bare-metal/aps/examples/src/exceptions.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
MissBiwott25/comprehensive-rust. | 1,445 | src/bare-metal/aps/examples/src/idmap.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
MissBiwott25/comprehensive-rust. | 4,768 | src/bare-metal/aps/examples/src/entry.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
mit-enclaves/argos-monitor | 1,088 | crates/bricks/src/x86_64/entry.S | .text
// Take a capa_index_t* and a void**, expected to be in rdi, rsi.
.globl asm_call_gate
asm_call_gate:
pushq %rbp
pushq %rbx
pushq %rcx
pushq %rdx
pushq %r10
pushq %r11
pushq %r12
pushq %r13
pushq %r14
pushq %r15
pushfq
// Now do the call, arguments are in the right... |
mit-enclaves/argos-monitor | 3,305 | monitor/first-stage/src/smp/trampoline.S | # Upon receiving a SIPI from BSP, the AP starts in real mode with CS:IP set to XY00:0000.
# The assembly here tries to enter long mode directly from real mode (skipping protected mode)
#
# Useful links:
# - https://wiki.osdev.org/Symmetric_Multiprocessing#AP_Initialization_Code
# - https://wiki.osdev.org/Entering_Long_... |
mit-enclaves/argos-monitor | 1,061 | C/libraries/sdktyche/runtime/asm.S | #if defined CONFIG_X86 || defined(__x86_64__)
.text
// Take a capa_index_t* and a void**, expected to be in rdi, rsi.
.globl asm_call_gate
asm_call_gate:
pushq %rbp
pushq %rbx
pushq %rcx
pushq %rdx
pushq %r10
pushq %r11
pushq %r12
pushq %r13
pushq %r14
pushq %r15
pushfq
... |
mit-enclaves/argos-monitor | 161,672 | C/libraries/sdktyche/loader/blake3_avx512_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx5... |
mit-enclaves/argos-monitor | 66,050 | C/libraries/sdktyche/loader/blake3_avx2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx2... |
mit-enclaves/argos-monitor | 61,143 | C/libraries/sdktyche/loader/blake3_sse41_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse41... |
mit-enclaves/argos-monitor | 68,858 | C/libraries/sdktyche/loader/blake3_sse2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse2
... |
Misakait/charlotteos | 1,355 | src/entry.S | # size of each hart's stack is 1024 bytes
# 为每个核心的栈定义大小，这里是 1024 字节
.equ STACK_SIZE, 1024
# 将 _start 符号声明为全局可见，作为程序入口
.global _start
.text
_start:
# park harts with id != 0
# 让非 0 号核心“待命”
csrr t0, mhartid # 读 CSR 寄存器 mhartid，获取当前核心的ID，存入 t0 寄存器
mv tp, t0 # 将核心ID从 t0 移到 tp 寄存器中备份，以便后续使用
bnez t0, park # ... |
MissBiwott25/comprehensive-rust. | 4,676 | src/bare-metal/aps/examples/src/exceptions.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
MissBiwott25/comprehensive-rust. | 1,445 | src/bare-metal/aps/examples/src/idmap.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
MissBiwott25/comprehensive-rust. | 4,768 | src/bare-metal/aps/examples/src/entry.S | /*
* Copyright 2023 Google LLC
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to ... |
mit-enclaves/argos-monitor | 1,088 | crates/bricks/src/x86_64/entry.S | .text
// Take a capa_index_t* and a void**, expected to be in rdi, rsi.
.globl asm_call_gate
asm_call_gate:
pushq %rbp
pushq %rbx
pushq %rcx
pushq %rdx
pushq %r10
pushq %r11
pushq %r12
pushq %r13
pushq %r14
pushq %r15
pushfq
// Now do the call, arguments are in the right... |
mit-enclaves/argos-monitor | 3,305 | monitor/first-stage/src/smp/trampoline.S | # Upon receiving a SIPI from BSP, the AP starts in real mode with CS:IP set to XY00:0000.
# The assembly here tries to enter long mode directly from real mode (skipping protected mode)
#
# Useful links:
# - https://wiki.osdev.org/Symmetric_Multiprocessing#AP_Initialization_Code
# - https://wiki.osdev.org/Entering_Long_... |
mit-enclaves/argos-monitor | 1,061 | C/libraries/sdktyche/runtime/asm.S | #if defined CONFIG_X86 || defined(__x86_64__)
.text
// Take a capa_index_t* and a void**, expected to be in rdi, rsi.
.globl asm_call_gate
asm_call_gate:
pushq %rbp
pushq %rbx
pushq %rcx
pushq %rdx
pushq %r10
pushq %r11
pushq %r12
pushq %r13
pushq %r14
pushq %r15
pushfq
... |
mit-enclaves/argos-monitor | 161,672 | C/libraries/sdktyche/loader/blake3_avx512_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx5... |
mit-enclaves/argos-monitor | 66,050 | C/libraries/sdktyche/loader/blake3_avx2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global _blake3_hash_many_avx2... |
mit-enclaves/argos-monitor | 61,143 | C/libraries/sdktyche/loader/blake3_sse41_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse41... |
mit-enclaves/argos-monitor | 68,858 | C/libraries/sdktyche/loader/blake3_sse2_x86-64_unix.S | #if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
#endif
#if defined(__ELF__) && defined(__CET__) && defined(__has_include)
#if __has_include(<cet.h>)
#include <cet.h>
#endif
#endif
#if !defined(_CET_ENDBR)
#define _CET_ENDBR
#endif
.intel_syntax noprefix
.global blake3_hash_many_sse2
... |
mm-zk/eravm_risc | 3,344 | asm/asm_reduced.S | /*
Entry point of all programs (_start).
It initializes DWARF call frame information, the stack pointer, the
frame pointer (needed for closures to work in start_rust) and the global
pointer. Then it calls _start_rust.
*/
.section .init, "ax"
.global _start
_start:
/* Jump to the absolute address ... |
moehr1z/loader | 5,267 | src/arch/x86_64/entry_fc.s | # This is the kernel's entry point, if Hermit is running with
# FireCracker. FireCracker assumes a 64 bit Linux kernel.
.code32
.set BOOT_STACK_SIZE, 4096
.extern loader_start # defined in linker script
.extern loader_end
.section .mboot, "a"
.align 8
.align 4
# we need already a valid GDT to switch in the 64bit ... |
moehr1z/loader | 6,171 | src/arch/x86_64/entry.s | # This is the kernel's entry point. We could either call main here,
# or we can use this to setup the stack or other nice stuff, like
# perhaps setting up the GDT and segments. Please note that interrupts
# are disabled at this point: More on interrupts later!
.code32
.set BOOT_STACK_SIZE, 4096
.extern loader_start ... |
moehr1z/loader | 1,619 | src/arch/aarch64/entry.s | // Adapted from https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials/blob/master/02_runtime_init/src/_arch/aarch64/cpu/boot.s
.equ _core_id_mask, 0xff
.section .text._start
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, mpidr_el1
and x1, x1, _core_id_mask
mov x2, xzr // Assume CP... |
mm-zk/eravm_risc | 3,344 | asm/asm_reduced.S | /*
Entry point of all programs (_start).
It initializes DWARF call frame information, the stack pointer, the
frame pointer (needed for closures to work in start_rust) and the global
pointer. Then it calls _start_rust.
*/
.section .init, "ax"
.global _start
_start:
/* Jump to the absolute address ... |
moehr1z/loader | 5,267 | src/arch/x86_64/entry_fc.s | # This is the kernel's entry point, if Hermit is running with
# FireCracker. FireCracker assumes a 64 bit Linux kernel.
.code32
.set BOOT_STACK_SIZE, 4096
.extern loader_start # defined in linker script
.extern loader_end
.section .mboot, "a"
.align 8
.align 4
# we need already a valid GDT to switch in the 64bit ... |
moehr1z/loader | 6,171 | src/arch/x86_64/entry.s | # This is the kernel's entry point. We could either call main here,
# or we can use this to setup the stack or other nice stuff, like
# perhaps setting up the GDT and segments. Please note that interrupts
# are disabled at this point: More on interrupts later!
.code32
.set BOOT_STACK_SIZE, 4096
.extern loader_start ... |
moehr1z/loader | 1,619 | src/arch/aarch64/entry.s | // Adapted from https://github.com/rust-embedded/rust-raspberrypi-OS-tutorials/blob/master/02_runtime_init/src/_arch/aarch64/cpu/boot.s
.equ _core_id_mask, 0xff
.section .text._start
_start:
// Only proceed on the boot core. Park it otherwise.
mrs x1, mpidr_el1
and x1, x1, _core_id_mask
mov x2, xzr // Assume CP... |
moehr1z/hermit-rs | 3,451 | kernel/src/arch/riscv64/kernel/switch.s | .section .text
.global switch_to_task
.global task_start
.extern task_entry
// .extern set_current_kernel_stack
.align 16
// This function should only be called if the fp registers are clean
switch_to_task:
// a0 = old_stack => the address to store the old rsp
// a1 = new_stack => stack pointer of the new task
a... |
moehr1z/hermit-rs | 4,619 | kernel/src/arch/x86_64/kernel/boot.s | # This is the entry point for the application processors.
# It is loaded at 0x8000 by Hermit and filled with parameters.
# It does the switch from Real Mode -> Protected Mode -> Long Mode,
# sets up CR3 for this CPU, and then calls into _start.
#
# In contrast to this self-contained entry point, _start is linked
# to t... |
moehr1z/hermit-rs | 6,784 | kernel/src/arch/aarch64/kernel/start.s | .section .text
.extern do_bad_mode
.extern do_irq
.extern do_fiq
.extern do_sync
.extern do_error
.extern get_last_stack_pointer
.macro trap_entry spsel
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x1... |
MohannedAhmed67/Edits | 1,766 | tests/tests_data/preprocessing/standardize_test_input_1.s |
datasets/formatted/output/ADD_1_TO_A_GIVEN_NUMBER_1.o: file format elf64-x86-64
Disassembly of section .text:
0000000000000000 <f_gold(int)>:
f_gold(int):
0: endbr64
4: pushq %rbp
5: movq %rsp,%rbp
8: movl %edi,-0x4(%rbp)
b: movl -0x4(%rbp),%eax
e: addl $0x1,%eax
11: popq %rbp
... |
Molorius/ulp-speed-test | 3,790 | main/main.S |
#define HIGH() reg_wr 257, 26, 26, 1;
#define LOW() reg_wr 258, 26, 26, 1;
#define LOOPS 1024
// this does not affect any flags
#define TEST(code...) \
HIGH() \
code; \
LOW()
#define ALU_REG_TEST(ins) TEST(ins r0, r0, r0)
#define ALU_IMM_TEST(ins) TEST(ins r0, r0, 0)
#define JUMP_0F_TEST(code...) \
... |
mp3/ccsnes | 2,932 | tests/hello_world.s | ; Simple SNES Hello World Test ROM
; This creates a minimal ROM that displays "HELLO" on screen
.include "snes.inc"
.segment "HEADER"
.byte "HELLO WORLD TEST " ; Title (21 bytes)
.byte $30 ; LoROM, FastROM
.byte $00 ; No chips
.byte $08 ... |
mpeco/rust-os | 8,452 | bootloader/src/asm/stage2.s | .section .second_stage, "awx"
.code16
stage2_start:
mov si, offset second_stage_string
call bios_println
a20_line_enable:
call check_a20_line
test ax, ax
jnz a20_line_enabled
call a20_line_kcontroller_enable
call check_a20_line
test ax, ax
jnz a20_line_enabled
call a20_line_... |
mpeco/rust-os | 3,381 | bootloader/src/asm/stage1.s | .section .first_stage, "awx"
.global stage1_start
.code16
stage1_start:
cld # clear direction flag
# initialize segment registers
xor ax, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ds, ax
mov ss, ax
mov sp, 0x7C00 # initialize the stack
mov [drive_code], dl # stores drive code
... |
mpeco/rust-os | 2,185 | kernel/src/x86_64/cpu/smp/asm/trampoline.s | # will be loaded on address 0x8000
.code16
trampoline_start:
cli
cld
xor ax, ax
mov ds, ax
# load gloal descriptor table
mov byte ptr [0x8034], 0xCF
lgdt [0x8020]
# enter protected mode
mov eax, cr0
or al, 1
mov cr0, eax
# jump to protected mode
ljmp 0x8, 0x8040
... |
mrkayaalp/ad7708 | 24,397 | Core/Startup/startup_stm32f446retx.s | /**
******************************************************************************
* @file startup_stm32f446xx.s
* @author MCD Application Team
* @brief STM32F446xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* ... |
MrSnickersRUS/NSTUlab2 | 1,423 | lab2_task3/main.s | section .data
array dd 1, 2, 3, 5, 2
array_len equ ($ - array) / 4
result_msg db "Количество неубывающих серий: ", 0
result_msg_len equ $ - result_msg
newline db 10, 0
newline_len equ $ - newline
buffer times 11 db 0
section .text
global _start
_start:
mov ecx, array_len
cmp e... |
MukioXun/OSKernel_test | 2,386 | AstrancE/modules/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
_srodata = .;
.rodata : ALIGN(4K) {
*(.rodata... |
MukioXun/OSKernel_test | 4,325 | AstrancE/modules/axhal/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.bal... |
MukioXun/OSKernel_test | 1,965 | AstrancE/modules/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STAR... |
MukioXun/OSKernel_test | 1,791 | AstrancE/modules/axhal/src/arch/loongarch64/trap.S | .macro SAVE_REGS, from_user
move $t0, $sp
.if \from_user == 1
csrrd $sp, KSAVE_KSP // restore kernel sp
addi.d $sp, $sp, -{trapframe_size}
STD $tp, $sp, 2
STD $r21, $sp, 21
csrrd $tp, KSAVE_TP
csrrd $r21, KSAVE_R21
.else
addi.d $sp, $sp, -{trap... |
MukioXun/OSKernel_test | 2,358 | AstrancE/modules/axhal/src/arch/riscv/trap.S | .macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR... |
MukioXun/OSKernel_test | 1,397 | AstrancE/modules/axhal/src/arch/x86_64/syscall.S | .section .text
.code64
syscall_entry:
swapgs // switch to kernel gs
mov gs:[offset __PERCPU_USER_RSP_OFFSET], rsp // save user rsp
mov rsp, gs:[offset __PERCPU_TSS + {tss_rsp0_offset}] // switch to kernel stack
sub rsp, 8 ... |
MukioXun/OSKernel_test | 1,627 | AstrancE/modules/axhal/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt ... |
MukioXun/OSKernel_test | 2,989 | AstrancE/modules/axhal/src/arch/aarch64/trap.S | .macro SAVE_REGS
sub sp, sp, {trapframe_size}
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp ... |
MusicalArtist12/basic-os-rust | 2,287 | src/kernel/boot/init.s | .global start
.section .init, "ax", @progbits
.code32
.extern stack_top
start:
cli
mov %ebx, %edi // pass multiboot address information to _start
movl $stack_top, %esp
call check_multiboot
call check_cpuid
call check_longmode
call setup_page_tables
call enable_paging
... |
MukioXun/OSKernel_test | 2,386 | AstrancE/modules/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
_srodata = .;
.rodata : ALIGN(4K) {
*(.rodata... |
MukioXun/OSKernel_test | 4,325 | AstrancE/modules/axhal/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.bal... |
MukioXun/OSKernel_test | 1,965 | AstrancE/modules/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STAR... |
MukioXun/OSKernel_test | 1,791 | AstrancE/modules/axhal/src/arch/loongarch64/trap.S | .macro SAVE_REGS, from_user
move $t0, $sp
.if \from_user == 1
csrrd $sp, KSAVE_KSP // restore kernel sp
addi.d $sp, $sp, -{trapframe_size}
STD $tp, $sp, 2
STD $r21, $sp, 21
csrrd $tp, KSAVE_TP
csrrd $r21, KSAVE_R21
.else
addi.d $sp, $sp, -{trap... |
MukioXun/OSKernel_test | 2,358 | AstrancE/modules/axhal/src/arch/riscv/trap.S | .macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR... |
MukioXun/OSKernel_test | 1,397 | AstrancE/modules/axhal/src/arch/x86_64/syscall.S | .section .text
.code64
syscall_entry:
swapgs // switch to kernel gs
mov gs:[offset __PERCPU_USER_RSP_OFFSET], rsp // save user rsp
mov rsp, gs:[offset __PERCPU_TSS + {tss_rsp0_offset}] // switch to kernel stack
sub rsp, 8 ... |
MukioXun/OSKernel_test | 1,627 | AstrancE/modules/axhal/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt ... |
MukioXun/OSKernel_test | 2,989 | AstrancE/modules/axhal/src/arch/aarch64/trap.S | .macro SAVE_REGS
sub sp, sp, {trapframe_size}
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
stp x10, x11, [sp, 10 * 8]
stp x12, x13, [sp, 12 * 8]
stp x14, x15, [sp, 14 * 8]
stp ... |
MusicalArtist12/basic-os-rust | 2,287 | src/kernel/boot/init.s | .global start
.section .init, "ax", @progbits
.code32
.extern stack_top
start:
cli
mov %ebx, %edi // pass multiboot address information to _start
movl $stack_top, %esp
call check_multiboot
call check_cpuid
call check_longmode
call setup_page_tables
call enable_paging
... |
Mwneees/New | 4,165 | crates/fiber/src/unix/s390x.S | // A WORD OF CAUTION
//
// This entire file basically needs to be kept in sync with itself. It's not
// really possible to modify just one bit of this file without understanding
// all the other bits. Documentation tries to reference various bits here and
// there but try to make sure to read over everything before twe... |
Mwneees/New | 4,052 | crates/wasmtime/src/runtime/vm/arch/s390x.S | // Currently `global_asm!` isn't stable on s390x, so this is an external
// assembler file built with the `build.rs`.
.machine z13
.text
.hidden host_to_wasm_trampoline
.globl host_to_wasm_trampoline
.type host_to_wasm_trampoline,@function
.p2align 2
#define CONCAT2(a,... |
n1z19/ipwndfu | 2,237 | src/checkm8_armv7.S | .text
.pool
.set PAYLOAD_OFFSET, 0xBAD00006
.set PAYLOAD_SIZE, 0xBAD00007
.set PAYLOAD_DEST, 0xBAD00005
.set PAYLOAD_PTR, 0xBAD00008
.set gUSBSerialNumber, 0xBAD00002
.set gUSBSRNMStringDescriptor, 0xBAD00004
.set gUSBDescriptors, ... |
n1z19/ipwndfu | 7,690 | src/limera1n-shellcode.S | @ limera1n-shellcode.S
@ Author: axi0mX
@ Shellcode for limera1n exploit with minor improvements:
@ * supports 'exec' magic for code execution over USB
@ * reports PWND:[limera1n] in USB serial number string
.text
.pool
.set free, 0xBAD0000d
.set memz_create, 0xBAD0000f
.se... |
n1z19/ipwndfu | 8,764 | src/alloc8-shellcode.S | @ alloc8-shellcode.S
@ Author: axi0mX
@ Shellcode for alloc8 exploit with minor improvements:
@ * supports 'exec' magic for code execution over USB
@ * reports PWND:[alloc8] in USB serial number string
@ * enters pwned DFU on boot if home and power buttons are being held and cable is connected
.text
.pool
.set free,... |
n1z19/ipwndfu | 8,151 | src/steaks4uce-shellcode.S | @ steaks4uce-shellcode.S
@ Author: axi0mX
@ Shellcode for steaks4uce exploit with minor improvements:
@ * reports PWND:[steaks4uce] in USB serial number string
.text
.pool
.set clean_data_cache, 0xBAD0000a
.set invalidate_instruction_cache, 0xBAD00006
.set usb_shutdown, 0xBAD00005
.set ... |
n1z19/ipwndfu | 3,423 | src/usb_0xA1_2_arm64.S | .text
.pool
.set USB_CORE_DO_IO, 0xBAD00006
.set LOAD_ADDRESS, 0xBAD00001
.set EXEC_MAGIC, 0xBAD00002
.set MEMC_MAGIC, 0xBAD00004
.set MEMS_MAGIC, 0xBAD00005
.set DONE_MAGIC, 0xBAD00003
.global _main
_main:
jump_back:
BRK #1
BRK #1
LDRH W2, [X0]
CMP W2, #0x2A1
BNE jump_back
STP X2... |
n1z19/ipwndfu | 2,701 | src/ibss-flash-nor-shellcode.S | @ ibss-flash-nor-shellcode.S
@ Author: axi0mX
@ Flashes parts of payload to NOR using iPhone2,1 4.3.5 iBSS
@ Parts flashed: 0x0-0x200, 0x8000-0xF3000
.text
.pool
.set reboot_cmd, 0x84000cdd
.set set_bgcolor, 0x8400c6ed
.set apply_bgcolor, 0x8400c789
.set get_block_device, 0x84012c61
... |
n1z19/ipwndfu | 1,771 | src/checkm8_arm64.S | .text
.pool
.set PAYLOAD_OFFSET, 0xBAD00006
.set PAYLOAD_SIZE, 0xBAD00007
.set PAYLOAD_DEST, 0xBAD00005
.set PAYLOAD_PTR, 0xBAD00008
.set gUSBSerialNumber, 0xBAD00002
.set gUSBSRNMStringDescriptor, 0xBAD00004
.set gUSBDescriptors, ... |
n1z19/ipwndfu | 2,444 | src/usb_0xA1_2_armv7.S | .text
.pool
.set USB_CORE_DO_IO, 0xBAD00006
.set LOAD_ADDRESS, 0xBAD00001
.set EXEC_MAGIC, 0xBAD00002
.set MEMC_MAGIC, 0xBAD00004
.set MEMS_MAGIC, 0xBAD00005
.set DONE_MAGIC, 0xBAD00003
.code 16
.global _main
_main:
jump_back:
BKPT #1
BKPT #1
BKPT #1
BKPT #1
LDRH R2, [R0]
MOVW R3, #0x2A... |
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