repo_id string | size int64 | file_path string | content string |
|---|---|---|---|
tactcomplabs/xbgas-binutils-gdb | 1,702 | gas/testsuite/gas/visium/allinsn_def.s | begin:
write.l (r2),r1
write.l 0(r2),r1
write.w 1(r1),r2
write.b 31(r3),r7
write.b (r4),r7
eamwrite 0,r4,r5
eamwrite 31,r7,r10
writemd r14,r15
writemdc r9
divs r5
divu r6
divds r10
divdu r11
asrd r12
lsrd r13
asld r14
dsi
mults r7,r8
multu r9,r10
eni
dsi
rfi
nsrel:
brr fa,nsrel
rflag r... |
tactcomplabs/xbgas-binutils-gdb | 1,446 | gas/testsuite/gas/mmix/comment-1.s | # Check that "naked" comments are accepted and ignored on all different
# mnemonic types and pseudos. The goal is to use all combinations of
# operands where varying number of operands are allowed. If any
# combinations are missing, for simplicity, add them to another file.
Main TRAP 123 ignore; x y z
TRAP 1,23 all;... |
tactcomplabs/xbgas-binutils-gdb | 1,784 | gas/testsuite/gas/mmix/regt-op.s | # All-registers, 'T'-type operands; optional third operand is
# register or constant.
Main LDA X,Y,Z
LDT $32,Y,Z
LDBU Y,$32,Z
LDTU $232,$133,Z
LDO X,Y,$73
LDOU $31,Y,$233
LDW X,$38,$212
LDWU $4,$175,$181
LDB X,Y,Z0
LDSF $32,Y,Z0
LDVTS Y,$32,Z0
LDUNC $232,$133,Z0
STHT X,Y,203
LDHT $31,Y,213
CSWAP X,$38,21... |
tactcomplabs/xbgas-binutils-gdb | 5,977 | gas/testsuite/gas/mmix/pr25331.s | # 1 "pr25331.c"
! mmixal:= 8H LOC Data_Section
.text ! mmixal:= 9H LOC 8B
.global f
.data ! mmixal:= 8H LOC 9B
.p2align 3
LOC @+(8-@)&7
f IS @
LOC @+8
.global g
.p2align 2
LOC @+(4-@)&3
g IS @
LOC @+4
.global h
.p2align 3
LOC @+(8-@)&7
h IS @
LOC @+8
.section .rodata
.p2align 2
LOC @+(4-@)&3
LC:0 IS @
... |
tactcomplabs/xbgas-binutils-gdb | 1,122 | gas/testsuite/gas/mmix/pushgo-op.s | # PUSHGO. Like T, but $X can be expressed as a constant.
# Using regt-op as a template caused this to go out of control.
Main PUSHGO X,Y,Z
PUSHGO XC,Y,Z
PUSHGO $32,Y,Z
PUSHGO 32,Y,Z
PUSHGO X,$32,Z
PUSHGO XC,$32,Z
PUSHGO $232,$133,Z
PUSHGO 232,$133,Z
PUSHGO X,Y,$73
PUSHGO XC,Y,$73
PUSHGO $31,Y,$233
PUSHGO 31... |
tactcomplabs/xbgas-binutils-gdb | 4,890 | gas/testsuite/gas/mmix/list-insns.s | #
# Somewhat complete instruction set and operand type check. No
# relocations or deferred register definitions here.
#
#
#
Main TETRA 3
TRAP 3,4,5
FCMP $12,$23,$241
FLOT $112,ROUND_OFF,$41
FLOT $112,ROUND_NEAR,141
FLOT $191,$242
FLOT $195,42
FUN $122,$203,$4
FEQL $102,$30,$40
FLOTU $102,$14
FLOTU $132,ROUN... |
tactcomplabs/xbgas-binutils-gdb | 1,027 | gas/testsuite/gas/mmix/relax2.s | # PUSHJ stub border-cases: two with either or both stubs unreachable,
# local symbols, ditto non-local labels, similar with three PUSHJs.
# Note the absence of ":" on labels: because it's a symbol-character,
# it's concatenated with the parameter macro name and parsed as "\x:".
# This happens before gas deals with ":" ... |
tactcomplabs/xbgas-binutils-gdb | 1,152 | gas/testsuite/gas/mmix/relax1.s | # Relaxation border-cases: just-within reach, just-out-of-reach, forward
# and backward. Have a few variable-length thingies in-between so it
# doesn't get too easy.
Main JMP l6
l0 JMP l6
l1 JMP l6
l01 JMP l6
GETA $7,nearfar1 % Within reach.
PUSHJ $191,nearfar2 % Within reach.
l2 JMP nearfar2 % Dummy.
.space 65530... |
tactcomplabs/xbgas-binutils-gdb | 1,872 | gas/testsuite/gas/arm/sp-pc-usage-t.s | .arch armv7-r
.syntax unified
.text
.thumb
.global foo
foo:
.align 4
@ Section A6.1.3 "Use of 0b1101 as a register specifier".
@ R13 as the source or destination register of a mov instruction.
@ only register to register transfers without shifts are supported,
@ with no flag setting
mov sp,r0
mov r0,sp
@ Using the... |
tactcomplabs/xbgas-binutils-gdb | 4,433 | gas/testsuite/gas/arm/vfp1.s | @ VFP Instructions for D variants (Double precision)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fcmped d0, d0
fcmpezd d0
fcmpd d0, d0
fcmpzd d0
@ ... |
tactcomplabs/xbgas-binutils-gdb | 1,311 | gas/testsuite/gas/arm/armv8_3-a-simd.s | .text
A1:
.arm
vcadd.f32 q1,q2,q3,#90
vcadd.f32 q1,q2,q3,#270
vcadd.f16 d21,d22,d23,#90
vcadd.f16 q1,q2,q3,#90
vcadd.f32 d21,d22,d23,#90
vcmla.f32 q1,q2,q3,#0
vcmla.f32 q1,q2,q3,#90
vcmla.f32 q1,q2,q3,#180
vcmla.f32 q1,q2,q3,#270
vcmla.f16 d21,d22,d23,#90
vcmla.f16 q1,q2,q3,#90
vcmla.f32 d21,d22,d23,#9... |
tactcomplabs/xbgas-binutils-gdb | 1,917 | gas/testsuite/gas/arm/mve-vstrldr-2.s | .syntax unified
.thumb
.macro all_vstr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
.endr
.endr
.endm
.irp data, .32, .u32, .s32, .f32
.irp imm, 0, 4, 8, 16, 32, 64, 128, 256, 508, 340, 168, 60, 48... |
tactcomplabs/xbgas-binutils-gdb | 1,276 | gas/testsuite/gas/arm/group-reloc-ldrs.s | @ Tests for LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym o... |
tactcomplabs/xbgas-binutils-gdb | 2,618 | gas/testsuite/gas/arm/archv8m_1m-cmse-main.s | .thumb
.syntax unified
T:
clrm {r0, r2} @ Accepts list without APSR
clrm {APSR} @ Accepts APSR alone
clrm {r3, APSR} @ Accepts core register and APSR together
clrmeq {r4} @ Accepts conditional execution
vscclrm {VPR} @ Accepts list with only VPR
vscclrm {s30, VPR} @ Accept single-precision VFP register and VPR toget... |
tactcomplabs/xbgas-binutils-gdb | 1,112 | gas/testsuite/gas/arm/group-reloc-ldr.s | @ Tests for LDR group relocations.
.text
.macro ldrtest load store sym offset
\load r0, [r0, #:pc_g0:(\sym \offset)]
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset... |
tactcomplabs/xbgas-binutils-gdb | 3,847 | gas/testsuite/gas/arm/unpredictable.s | .text
.global upredictable
unpredictable:
.word 0x004f00b1 @ strheq r0, [pc], #-1
.word 0x005fffff @ ldrsheq pc, [pc], #-255
.word 0x007fffff @ ldrsheq pc, [pc, #-255]!
.word 0x00cf00b0 @ strheq r0, [pc], #0
.word 0x00df00b0 @ ldrhe... |
tactcomplabs/xbgas-binutils-gdb | 1,975 | gas/testsuite/gas/arm/armv8-ar-bad.s | .syntax unified
.text
// SWP
.arm
swp r0, r1, [r2]
// deprecated MCRs
mcr p15, 0, r0, c7, c5, 4
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r2, c7, c10, 5
mrc p14, 6, r1, c0, c0, 0
mrc p14, 6, r0, c1, c0, 0
// deprecated SETEND
setend be
.thumb
setend le
// HLT A32
.arm
hlt 0x10000
hltne 0x1
// HLT... |
tactcomplabs/xbgas-binutils-gdb | 7,483 | gas/testsuite/gas/arm/neon-const.s | @ test floating-point constant parsing.
.arm
.text
.syntax unified
vmov.f32 q0, 0.0
vmov.f32 q0, 2.0
vmov.f32 q0, 4.0
vmov.f32 q0, 8.0
vmov.f32 q0, 16.0
vmov.f32 q0, 0.125
vmov.f32 q0, 0.25
vmov.f32 q0, 0.5
vmov.f32 q0, 1.0
vmov.f32 q0, 2.1... |
tactcomplabs/xbgas-binutils-gdb | 2,786 | gas/testsuite/gas/arm/bfloat16-bad.s | .syntax unified
// Test warnings about type specifier being incorrect.
vdot.b16 d0, d0, d0
vmmla q0.b16, q0, q0
vdot.bf32 d0, d0, d0[1]
vdot d0.bf32, d0, d0
vdot d0.bf32, d0.bf16, d0.bf16
// Test conditions are not allowed in ARM.
vdotne d0, d0, d0
vdotne d0, d0, d0[1]
vmmlane q0, q0, q0
vfmatne.bf16 q0, d0, d0
vfm... |
tactcomplabs/xbgas-binutils-gdb | 2,628 | gas/testsuite/gas/arm/thumb.s | .text
.code 16
.foo:
lsl r2, r1, #3
lsr r3, r4, #31
wibble/data:
asr r7, r0, #5
lsl r1, r2, #0
lsr r3, r4, #0
asr r4, r5, #0
lsr r6, r7, #32
asr r0, r1, #32
add r1, r2, r3
add r2, r4, #2
sub r3, r5, r7
sub r2, r4, #7
mov r4, #255
cmp r3, #250
add r6, #123
sub r5, #128
and r3, r5
eor r4, r6
l... |
tactcomplabs/xbgas-binutils-gdb | 2,844 | gas/testsuite/gas/arm/arch7em.s | # Instructions included in v7E-M architecture over v7-M.
.text
.thumb
.syntax unified
pkh:
pkhbt r0, r0, r0
pkhbt r9, r0, r0
pkhbt r0, r9, r0
pkhbt r0, r0, r9
pkhbt r0, r0, r0, lsl #0x14
pkhbt r0, r0, r0, lsl #3
pkhtb r1, r2, r3
pkhtb r1, r2, r3, asr #0x11
qadd:
qadd r1, r2, r3
qadd16 r1, r2, r3
qadd... |
tactcomplabs/xbgas-binutils-gdb | 5,464 | gas/testsuite/gas/arm/mve-vstld-bad.s | .syntax unified
.thumb
vst20.8 {q0, q2}, [r0]
vst20.8 {q0, q1, q2}, [r0]
vst20.8 {q0}, [r0]
vst20.8 {q0, q1}, [pc]
vst20.8 {q0, q1}, [pc]!
vst20.8 {q0, q1}, [sp]!
vst20.8 {q3, q2}, [r0]
vst20.64 {q0, q1}, [r0]
vst21.8 {q0, q2}, [r0]
vst21.8 {q0, q1, q2}, [r0]
vst21.8 {q0}, [r0]
vst21.8 {q0, q1}, [pc]
vst21.8 {q0, q1}, ... |
tactcomplabs/xbgas-binutils-gdb | 1,985 | gas/testsuite/gas/arm/cde-mve-or-neon.s | .syntax unified
vcx1 p0, s0, #0
vcx1 p0, s0, #1920
vcx1 p0, s0, #64
vcx1 p0, s0, #63
vcx1 p7, s0, #0
vcx1 p0, s1, #0
vcx1 p0, s30, #0
vcx1 p0, d0, #0
vcx1 p0, d0, #1920
vcx1 p0, d0, #64
vcx1 p0, d0, #63
vcx1 p7, d0, #0
vcx1 p0, d15, #0
vcx1a p0, s0, #0
vcx1a p0, s0, #1920
vcx1a p0, s0, #64
vcx1a p0, s0, #63
vcx1a p7, s... |
tactcomplabs/xbgas-binutils-gdb | 1,723 | gas/testsuite/gas/arm/mve-vqdmlsdh.s | .syntax unified
.thumb
.irp data, s8, s16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
vqdmlsdh.\data \op1, \op2, \op3
vqdmlsdhx.\data \op1, \op2, \op3
vqrdmlsdh.\data \op1, \op2, \op3
vqrdmlsdhx.\data \op1, \op2, \op3
.endr
.endr
.endr
.endr
.irp op2, q1, q2, q4, q7
.irp op3,... |
tactcomplabs/xbgas-binutils-gdb | 6,275 | gas/testsuite/gas/arm/sp-pc-validations-bad.s | .syntax unified
@ Loads, ARM ================================================================
.arm
@ LDR (immediate, ARM)
@ LDR (literal)
@No unpredictable or undefined combinations.
@ LDR (register)
ldr r0,[r1,pc, LSL #2] @ Unpredictable
ldr r0,[r1,pc, LSL #2]! @ ditto
ldr r0,[r1],pc, LSL #2 @ ditto
ldr r0,[p... |
tactcomplabs/xbgas-binutils-gdb | 2,896 | gas/testsuite/gas/arm/mve-vmov-1.s | .syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vm... |
tactcomplabs/xbgas-binutils-gdb | 1,105 | gas/testsuite/gas/arm/mve-vqdmull-bad.s | .macro cond op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vqdmullt.s8 q0, q1, q2
vqdmullt.u8 q0, q1, q2
vqdmullt.i16 q0, q1, q2
vqdmullt.s64 q0, q1, q2
vqdmullb.s8 q0, q1, q2
vqdmullb.u8 q0, q1, q2
vqdmullb.i16 q0, q1, q2
vqdmullb.s64 q0, q1, q2
v... |
tactcomplabs/xbgas-binutils-gdb | 2,306 | gas/testsuite/gas/arm/armv7-a+virt.s | .text
.syntax unified
.arm
foo:
hvc 0x0000
hvc 0xffff
eret
mrs r1, R8_usr
mrs r1, R9_usr
mrs r1, R10_usr
mrs r1, R11_usr
mrs r1, R12_usr
mrs r1, SP_usr
mrs r1, LR_usr
mrs r1, R8_fiq
mrs r1, R9_fiq
mrs r1, R10_fiq
mrs r1, R11_fiq
mrs r1, R12_fiq
mrs r1, SP_fiq
mrs r1, LR_fiq
mrs r1, SPSR_fiq
mrs r1... |
tactcomplabs/xbgas-binutils-gdb | 2,846 | gas/testsuite/gas/arm/mve-vstr-bad-3.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vstrb.8 q0, [r0, #128]
vstrb.8 q0, [r0, #-128]
vstrb.16 q0, [r0, #128]
vstrb.16 q0, [r0, #-128]
vstrb.32 q0, [r0, #128]
vstrb.32 q0, [r0, #-128]
vstrb.8 q0, [r0, #128]!
vstrb.8 q0, [r0, #-128]!
vstrb.16 ... |
tactcomplabs/xbgas-binutils-gdb | 1,190 | gas/testsuite/gas/arm/cde.s | .syntax unified
.include "cde-scalar.s"
# vcx1{a} encoding has the following form
# 111a110i0d10iiiidddd0pppi1iiiiii (vector form)
# 111a110s0d10iiiidddd0pppi0iiiiii (S/D register form)
#
# Variants to test:
# - immediates that set each set of `i` to ones in turn.
# - each register set to something non-zero
# (whe... |
tactcomplabs/xbgas-binutils-gdb | 1,394 | gas/testsuite/gas/arm/mve-vqrshrn-bad.s | .macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q0, #1
.endr
.endm
.syntax unified
.thumb
vqrshrnt.s8 q0, q1, #1
vqrshrnt.s64 q0, q1, #1
vqrshrnt.s16 q0, q1, #0
vqrshrnt.s16 q0, q1, #9
vqrshrnt.s32 q0, q1, #0
vqrshrnt.s32 q0, q1, #17
vqrshrnb.s8 q0, q1, #1
vqrshrnb.s64 q0, q1, #1
vqrshrnb.s16 ... |
tactcomplabs/xbgas-binutils-gdb | 3,936 | gas/testsuite/gas/arm/iwmmxt.s | .text
.global iwmmxt
iwmmxt:
tandcb r15
TANDCHLE r15
TANDCWge r15
TBCSTBlt wr0, r1
tbcsth wr1, r2
TBCSTWGT wr2, r3
textrcb r15, #7
textrcheq r15, #2
TEXTRCW r15, #0
TEXTRMUB r14, wr3, #6
textrmsbne r13, wr4, #5
textrmUH r12, wr5, #2
textrmSh r11, wr6, #0
TEXTRMUWcs r10, wr7, #1
textrmswhs r9, ... |
tactcomplabs/xbgas-binutils-gdb | 4,160 | gas/testsuite/gas/arm/mve-vmov-3.s | vmov r0, r1, q1[2], q1[0]
vmov r0, r1, q2[2], q2[0]
vmov r0, r1, q3[2], q3[0]
vmov r0, r1, q4[2], q4[0]
vmov r0, r1, q5[2], q5[0]
vmov r0, r1, q6[2], q6[0]
vmov r0, r1, q7[2], q7[0]
vmov r1, r0, q0[2], q0[0]
vmov r2, r0, q0[2], q0[0]
vmov r3, r0, q0[2], q0[0]
vmov r4, r0, q0[2], q0[0]
vmov r5, r0, q0[2], q0[0]
vmov r6,... |
tactcomplabs/xbgas-binutils-gdb | 13,442 | gas/testsuite/gas/arm/neon-cov.s | @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
@ possible, but without causing instructions to be badly-formed.
.arm
.syntax unified
.text
.macro regs3_1 op opq vtype
\op\vtype q0,q0,q0
\opq\vtype q0,q0,q0
\op\vtype d0,d0,d0
.endm
.macro dregs3_1 op vtype
\op\vtype d0,d0,d0
... |
tactcomplabs/xbgas-binutils-gdb | 2,093 | gas/testsuite/gas/arm/mve-vldr-bad-1.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vldrb.16 q0, [r0, q1]
vldrb.p16 q0, [r0, q1]
vldrb.f16 q0, [r0, q1]
vldrb.32 q0, [r0, q1]
vldrb.f32 q0, [r0, q1]
vldrb.64 q0, [r0, q1]
vldrb.u64 q0, [r0, q1]
vldrb.s64 q0, [r0, q1]
vldrb.u32 q0, [pc... |
tactcomplabs/xbgas-binutils-gdb | 1,716 | gas/testsuite/gas/arm/armv8-ar.s | .syntax unified
.text
.arch armv8-a
.arm
foo:
sevl
hlt 0x0
hlt 0xf
hlt 0xfff0
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh... |
tactcomplabs/xbgas-binutils-gdb | 1,917 | gas/testsuite/gas/arm/armv8-2-fp16-scalar.s | .macro f16_sss_arithmetic reg0, reg1, reg2
.irp op, vdiv.f16, vfma.f16, vfms.f16, vfnma.f16, vfnms.f16, vmaxnm.f16, vminnm.f16, vmla.f16, vmls.f16, vmul.f16, vnmla.f16, vnmls.f16, vnmul.f16, vsub.f16
\op s\reg0, s\reg1, s\reg2
.endr
.endm
.macro f16_ss_arithmetic reg0, reg1
.irp op, vabs.f16, vadd.f16, vsqrt.f... |
tactcomplabs/xbgas-binutils-gdb | 2,081 | gas/testsuite/gas/arm/float.s | .text
.align 0
l:
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0
mvfs f4, f7
mvfsp f0, f1
mvfdm f3, f4
mvfez f7, f7
adfe f0, f1, #2.0
adfeqe f1, f2, #0.5
adfsm f3, f4, f5
sufd f0, f0, #2.0
sufs f1, f2, #10.0
sufneez f3, f4, f5
rsfs f1, f1, #0.0
rsfdp f3, f0, #5.0
rsfled f7, f6, f0
mufd f0, f0, f0
mu... |
tactcomplabs/xbgas-binutils-gdb | 1,334 | gas/testsuite/gas/arm/mve-vmlsldav-bad.s | .macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlsldav.s16 r0, sp, q1, q2
vmlsldav.u16 r0, r1, q1, q2
cond vmlsldav
cond vmlsldava
cond vmlsldavx
cond vmlsldavax
vmlsldav.s64 r0, r1, q1, q2
vmlsldav.f32 r0, r1, q1, q2
vmlsldav.s8 r0, r1, q1, q2
... |
tactcomplabs/xbgas-binutils-gdb | 2,675 | gas/testsuite/gas/arm/fpa-monadic.s | .text
.globl F
F:
mvfs f0, f0
mvfsp f0, f0
mvfsm f0, f0
mvfsz f0, f0
mvfd f0, f0
mvfdp f0, f0
mvfdm f0, f0
mvfdz f0, f0
mvfe f0, f0
mvfep f0, f0
mvfem f0, f0
mvfez f0, f0
mnfs f0, f0
mnfsp f0, f0
mnfsm f0, f0
mnfsz f0, f0
mnfd f0, f0
mnfdp f0, f0
mnfdm f0, f0
mnfdz f0, f0
mnfe f0, f0
mnfep f0, ... |
tactcomplabs/xbgas-binutils-gdb | 2,975 | gas/testsuite/gas/arm/vfp-neon-syntax-inc.s | @ VFP with Neon-style syntax
.syntax unified
.arch armv7-a
.include "itblock.s"
func:
.macro testvmov cond="" f32=".f32" f64=".f64"
itblock 4 \cond
vmov\cond\f32 s0,s1
vmov\cond\f64 d0,d1
vmov\cond\f32 s0,#0.25
vmov\cond\f64 d0,#1.0
itblock 4 \cond
vmov\cond r0,s1
... |
tactcomplabs/xbgas-binutils-gdb | 2,460 | gas/testsuite/gas/arm/armv8-a+crypto.s | .syntax unified
.arch armv8-a
.arch_extension crypto
.arm
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
ae... |
tactcomplabs/xbgas-binutils-gdb | 3,072 | gas/testsuite/gas/arm/mve-vmov-2.s | .syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vm... |
tactcomplabs/xbgas-binutils-gdb | 5,726 | gas/testsuite/gas/arm/vfp1xD_t2.s | @ VFP Instructions for v1xD variants (Single precision only)
@ Same as vfp1xD.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison... |
tactcomplabs/xbgas-binutils-gdb | 1,240 | gas/testsuite/gas/arm/archv6t2-bad.s | @ We do not bother testing simple cases, e.g. immediates where
@ registers belong, trailing junk at end of line.
.text
x:
@ pc not allowed
bfc pc,#0,#1
bfi pc,r0,#0,#1
movw pc,#0
movt pc,#0
@ bitfield range limits
bfc r0,#0,#0
bfc r0,#32,#0
bfc r0,#0,#33
bfc r0,#33,#1
bfc r0,#32,#1
bfc r0,#28,#10
bfi ... |
tactcomplabs/xbgas-binutils-gdb | 5,939 | gas/testsuite/gas/arm/cde-scalar.s | .syntax unified
# Extra tests everywhere:
# Ensure that setting the register to something in r[1-12] works.
# cx1{a} Has arguments in the following form
# 111a111000iiiiiidddd0pppi0iiiiii
#
# Variants to test:
# - Base (everything we can set to zero)
# - immediates that set each set of `i` to ones in turn.
# (imm = ... |
tactcomplabs/xbgas-binutils-gdb | 1,830 | gas/testsuite/gas/arm/thumb2_vpool.s | .text
.fpu neon
.thumb
.syntax unified
.thumb_func
thumb2_ldr:
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
# Thumb-2 support vldr literal pool also.
vlxr s "=0"
vlxr s "=0xff000000"
vlxr s "=-1"
vlxr s "=0x0fff0000"
.pool
vlxr s "=0"
vlxr s "=0x0... |
tactcomplabs/xbgas-binutils-gdb | 2,689 | gas/testsuite/gas/arm/mve-vstrldr-3.s | .syntax unified
.thumb
.macro n_vstr_w_vldr op, imm
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7
\op \op1, [\op2, #\imm]
\op \op1, [\op2, #-\imm]
\op \op1, [\op2, #\imm]!
\op \op1, [\op2, #-\imm]!
\op \op1, [\op2], #\imm
\op \op1, [\op2], #-\imm
.endr
.endr
.endm
.irp mnem, vstrb.16, vstrb.32
.irp imm, 0... |
tactcomplabs/xbgas-binutils-gdb | 1,983 | gas/testsuite/gas/arm/neon-ldst-es.s | @ test element and structure loads and stores.
.text
.arm
.syntax unified
vst2.8 {d2,d3},[r6,:128]
vld3.8 {d1,d2,d3},[r7]!
vst3.16 {d1,d3,d5},[r9:64],r3
vld4.32 {d2,d3,d4,d5},[r10]
vst4.16 {d1,d3,d5,d7},[r10]
vld1.16 {d1[],d2[]},[r10]
vld1.16 {d1[]},[r10,:16]
vld2.32 {d1[],d3[]},[r10:64]
vld3.s8 {d3[],d4[... |
tactcomplabs/xbgas-binutils-gdb | 2,872 | gas/testsuite/gas/arm/iwmmxt2.s | .text
.global iwmmxt2
iwmmxt2:
waddhc wr4, wr5, wr6
waddwc wr7, wr8, wr9
wmadduxgt wr4, wr5, wr6
wmadduneq wr7, wr8, wr9
wmaddsxne wr4, wr5, wr6
wmaddsnge wr7, wr8, wr9
wmulumr wr1, wr2, wr3
wmulsmr wr1, wr2, wr3
torvscbgt r15
torvschne r15
torvscweq r15
wabsb wr1, wr2
wabsh wr3, wr4
wabsw w... |
tactcomplabs/xbgas-binutils-gdb | 4,601 | gas/testsuite/gas/arm/vfp1_t2.s | @ VFP Instructions for D variants (Double precision)
@ Same as vfp1.s, but for Thumb-2
.syntax unified
.thumb
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operation... |
tactcomplabs/xbgas-binutils-gdb | 1,975 | gas/testsuite/gas/arm/mve-vpt.s | .syntax unified
.thumb
.macro ins_2 cond2
vaddt.i32 q0, q1, q2
vadd\cond2\().i32 q0, q1, q2
.endm
.macro ins_3 cond2, cond3
ins_2 \cond2
vadd\cond3\().i32 q0, q1, q2
.endm
.macro ins_4 cond2, cond3, cond4
ins_3 \cond2, \cond3
vadd\cond4\().i32 q0, q1, q2
.endm
.macro vpt_1 data, cond, op1, op2
vpt\data \cond, \op1, \... |
tactcomplabs/xbgas-binutils-gdb | 3,155 | gas/testsuite/gas/arm/mve-vldr-bad-3.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0]
.endr
.endm
.syntax unified
.thumb
vldrb.8 q0, [r0, #128]
vldrb.8 q0, [r0, #-128]
vldrb.u16 q0, [r0, #128]
vldrb.u16 q0, [r0, #-128]
vldrb.u32 q0, [r0, #128]
vldrb.u32 q0, [r0, #-128]
vldrb.8 q0, [r0, #128]!
vldrb.8 q0, [r0, #-128]!
vldr... |
tactcomplabs/xbgas-binutils-gdb | 4,535 | gas/testsuite/gas/arm/archv6.s | .text
.align 0
label:
cps #15
cpsid if
cpsie if
ldrex r2, [r4]
ldrexne r4, [r8]
mcrr2 p0, 12, r7, r5, c3
mrrc2 p0, 12, r7, r5, c3
pkhbt r2, r5, r8
pkhbt r2, r5, r8, LSL #3
pkhbtal r2, r5, r8, LSL #3
pkhbteq r2, r5, r8, LSL #3
pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5.
pkhtb r2, r5, r8, ASR #3
pk... |
tactcomplabs/xbgas-binutils-gdb | 1,332 | gas/testsuite/gas/arm/arm7t.s | .text
.align 0
loadhalfwords:
ldrh r0, [r1]
ldrh r0, [r1]!
ldrh r0, [r1, r2]
ldrh r0, [r1, r2]!
ldrh r0, [r1,#0x0C]
ldrh r0, [r1,#0x0C]!
ldrh r0, [r1,#-0x0C]
ldrh r0, [r1], r2
ldrh r0, =0xFF00
ldrh r0, =0xC0DE
ldrh r0, .L2
storehalfwords:
strh r0, [r1]
strh r0, [r1]!
strh r0, [r1, r2]
strh r0, [r1, r... |
tactcomplabs/xbgas-binutils-gdb | 1,166 | gas/testsuite/gas/arm/vfpv3-32drs.s | .arm
.syntax unified
fcpyd d3,d22
fcpyd d22,d3
fcvtds d22,s22
fcvtsd s22,d22
fmdhr d21,r4
fmdlr d27,r5
fmrdh r6,d23
fmrdl r7,d25
fsitod d22,s22
fuitod d21,s21
ftosid s20,d20
ftosizd s20,d20
ftouid s19,d19
ftouizd s19,d19
fldd d19,[r10,#4]
fstd d21,[r10,#4]
fldmiad r10!,{d5,d6}
fldmiad r10!,{d18,d19,d2... |
tactcomplabs/xbgas-binutils-gdb | 1,602 | gas/testsuite/gas/arm/half-prec-vfpv3.s | .text
vcvtt.f32.f16 s0, s1
vcvtteq.f32.f16 s2, s3
vcvttne.f32.f16 s2, s3
vcvttcs.f32.f16 s2, s3
vcvttcc.f32.f16 s2, s3
vcvttmi.f32.f16 s2, s3
vcvttpl.f32.f16 s2, s3
vcvttvs.f32.f16 s2, s3
vcvttvc.f32.f16 s2, s3
vcvtthi.f32.f16 s2, s3
vcvttls.f32.f16 s2, s3
vcvttge.f32.f16 s2, s3
vcvttlt.f32.f1... |
tactcomplabs/xbgas-binutils-gdb | 9,347 | gas/testsuite/gas/arm/sp-pc-validations-bad-t.s | .syntax unified
@ Enable Thumb mode
.thumb
.macro it_test opcode operands:vararg
itt eq
\opcode\()eq r15, \operands
moveq r0, r0
.endm
.macro it_testw opcode operands:vararg
itt eq
\opcode\()eq.w r15, \operands
moveq r0, r0
.endm
.macro LOAD operands:vararg
it_test ldr, \operands
.endm
.macro LOADw operands:vararg
i... |
tactcomplabs/xbgas-binutils-gdb | 4,202 | gas/testsuite/gas/arm/msr-imm.s | @ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from Immediate
@ Write to application status register
msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0... |
tactcomplabs/xbgas-binutils-gdb | 2,724 | gas/testsuite/gas/arm/mve-vstrldr-1.s | .syntax unified
.thumb
.macro all_vstr op, size, ext
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q0, q1, q2, q4, q7
\op\()\size \op1, [\op2, \op3]
\op\()\size \op1, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endr
.endm
.irp size, .8, .16, .32
all_vstr vstrb, \size, 0
.endr
... |
tactcomplabs/xbgas-binutils-gdb | 1,135 | gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s | @ Tests for LDC group relocations that are meant to fail during parsing.
.macro ldctest insn reg
\insn 0, \reg, [r0, #:pc_g0_nc:(sym)]
\insn 0, \reg, [r0, #:pc_g1_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g0_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g1_nc:(sym)]
\insn 0, \reg, [r0, #:foo:(sym)]
.endm
.macro ldctest2 ins... |
tactcomplabs/xbgas-binutils-gdb | 1,461 | gas/testsuite/gas/arm/mve-vstld.s | .syntax unified
.thumb
.macro all_vstld2 op
.irp part, 0, 1
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1}, [\op2]
\op\()\part\()\size {q1, q2}, [\op2]
\op\()\part\()\size {q2, q3}, [\op2]
\op\()\part\()\size {q3, q4}, [\op2]
\op\()\part\()\size {q4, q5}, [\op... |
tactcomplabs/xbgas-binutils-gdb | 1,173 | gas/testsuite/gas/arm/thumb2_ldmstm_bad.s | .syntax unified
.thumb
ldmstm_bad:
@ UNPREDICTABLE Thumb-2 encodings of LDM/LDMIA/LDMFD as specified
@ by section A8.6.53 of the ARMARM.
ldmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE
ldmia r1, {r14, r15} @ Encoding T2, UNPREDICTABLE
ldmia r0!, {r0-r3} @ Encoding ... |
tactcomplabs/xbgas-binutils-gdb | 1,138 | gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s | .macro cond, op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s8 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vhadd.i8 q0, q1, q2
vhadd.s64 q0, q1, q2
vhadd.i8 q0, q1, r2
vhadd.s64 q0, q1, r2
vhsub.i16 q0, q1, q2
vhsub.u64 q0, q1, q2
vhsub.i16 q0, q1, r2
vhsub.u64 q0, q1, r2
vrhadd.i32 q0, q1, q2
v... |
tactcomplabs/xbgas-binutils-gdb | 1,055 | gas/testsuite/gas/arm/arch7.s | # ARMV7 instructions
.text
.arch armv7r
label1:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
pli [r5, #4095]
pli [r5, #-4095]
dbg #0
dbg #15
dmb
dmb sy
dsb
dsb sy
dsb un
dsb st
dsb unst
isb
isb sy
.thumb
.thumb_func
label2:
pli [r6, r8]
pli [r9, r7]
pli [r0, r1, lsl #2]
pli [r5]
p... |
tactcomplabs/xbgas-binutils-gdb | 1,206 | gas/testsuite/gas/arm/archv6t2.s | .text
x:
bfi r0, r0, #0, #1
bfine r0, r0, #0, #1
bfi r9, r0, #0, #1
bfi r0, r9, #0, #1
bfi r0, r0, #0, #18
bfi r0, r0, #17, #1
bfi r0, #0, #0, #1
bfc r0, #0, #1
bfcne r0, #0, #1
bfc r9, #0, #1
bfc r0, #0, #18
bfc r0, #17, #1
sbfx r0, r0, #0, #1
sbfxne r0, r0, #0, #1
ubfx r0, r0, #0, #1
sbfx r9, r0, ... |
tactcomplabs/xbgas-binutils-gdb | 1,265 | gas/testsuite/gas/arm/neon-cond-bad-inc.s | # Check for illegal conditional Neon instructions in ARM mode. The instructions
# which overlap with VFP are the tricky cases, so test those.
.include "itblock.s"
.syntax unified
.arch armv7-a
.fpu neon
.text
func:
itblock 4 eq
vmoveq q0,q1
vmoveq d0,d1
vmoveq.i32 q0,#0
vmoveq.i32 d0,#0
... |
tactcomplabs/xbgas-binutils-gdb | 1,317 | gas/testsuite/gas/arm/ldr-t.s | .syntax unified
.arch armv7-a
.thumb
.global foo
foo:
.align 4
@ldr-immediate
@!wback && (n == t)
ldr r1, [r1, #5]
@wback && !(n == t)
ldr r1, [r2, #5]!
@!(rt == r15) && rn == r15
@ && bits<0..1> (immediate) != 00
ldr r1, [r15, #5]
@rt == r15 && !(rn == r15)
@ && bits<0..1> (immediate) != 00
ldr r15,... |
tactcomplabs/xbgas-binutils-gdb | 1,129 | gas/testsuite/gas/arm/neon-psyn.s | .arm
.syntax unified
fish .qn q2
cow .dn d2[1]
chips .dn d2
banana .dn d3
vmul fish.s16, fish.s16, fish.s16
vmul banana, banana, cow.s32
vmul d3.s32, d3.s32, d2.s32
vadd d2.s32, d3.s32
vmull fish.u32, chips.u16, chips.u16[1]
X .dn D0.S16
Y .dn D1.S16
Z .dn Y[2]
VMLA X, Y, Z
VMLA X, Y, Y[2]
foo .dn d5
ba... |
tactcomplabs/xbgas-binutils-gdb | 1,284 | gas/testsuite/gas/arm/r15-bad.s | .text
.align 0
label:
mul r15, r1, r2
mul r1, r15, r2
mla r15, r2, r3, r4
mla r1, r15, r3, r4
mla r1, r2, r15, r4
mla r1, r2, r3, r15
smlabb r15, r2, r3, r4
smlabb r1, r15, r3, r4
smlabb r1, r2, r15, r4
smlabb r1, r2, r3, r15
smlalbb r15, r2, r3, r4
smlalbb r1, r15, r3, r4
smlalbb r1, r2, r15, r4
smlalbb... |
tactcomplabs/xbgas-binutils-gdb | 1,314 | gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s | @ Tests that are meant to fail during encoding of LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.... |
tactcomplabs/xbgas-binutils-gdb | 1,392 | gas/testsuite/gas/arm/bundle.s | .syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
.macro offset_insn insn_name, offset, size
.p2align 4
\insn_name\()_offset_\offset\():
.rept \offset / \size
bkpt
.endr
\insn_name
.endm
.macro test_offsets_arm insn_... |
tactcomplabs/xbgas-binutils-gdb | 2,802 | gas/testsuite/gas/arm/fpa-dyadic.s | .text
.globl F
F:
adfs f0, f0, f0
adfsp f0, f0, f0
adfsm f0, f0, f0
adfsz f0, f0, f0
adfd f0, f0, f0
adfdp f0, f0, f0
adfdm f0, f0, f0
adfdz f0, f0, f0
adfe f0, f0, f0
adfep f0, f0, f0
adfem f0, f0, f0
adfez f0, f0, f0
sufs f0, f0, f0
sufsp f0, f0, f0
sufsm f0, f0, f0
sufsz f0, f0, f0
sufd f0, f0, f... |
tactcomplabs/xbgas-binutils-gdb | 6,271 | gas/testsuite/gas/arm/vfp1xD.s | @ VFP Instructions for v1xD variants (Single precision only)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fmstat
fcmpes s0, s0
fcmpezs s0
fcmps s0, s... |
tactcomplabs/xbgas-binutils-gdb | 3,870 | gas/testsuite/gas/arm/mve-vrmlaldavh-bad.s | .macro cond op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s32 r0, r1, q2, q3
.endr
.endm
.syntax unified
.thumb
vrmlaldavh.s16 r0, r1, q2, q3
vrmlaldavh.i32 r0, r1, q2, q3
vrmlaldavha.s16 r0, r1, q2, q3
vrmlaldavha.i32 r0, r1, q2, q3
vrmlalvh.s16 r0, r1, q2, q3
vrmlalvh.i32 r0, r1, q2, q3
vrmlalvha.s16 r0, r1, ... |
tactcomplabs/xbgas-binutils-gdb | 1,520 | gas/testsuite/gas/arm/arm-it-auto.s | .syntax unified
.arch armv7
.thumb
main:
@These branches are to see the labels in the generated file
bl .L888
bl .L111
bl .L777
@No IT block here:
bne .L4
@The following groups should be an IT block each.
@it ne
addne.n pc, r0
@it ne
tbbne [r0, r1]
@it eq
tbheq [r1, r0]
@The following group should be ... |
tactcomplabs/xbgas-binutils-gdb | 1,561 | gas/testsuite/gas/arm/archv8m-cmse-msr.s | T:
## MRS ##
# MSP
mrs r0, MSP
mrs r0, MSP_NS
mrs r0, msp
mrs r0, msp_ns
# PSP
mrs r1, PSP
mrs r1, PSP_NS
mrs r1, psp
mrs r1, psp_ns
# MSPLIM
mrs r2, MSPLIM
mrs r2, MSPLIM_NS
mrs r2, msplim
mrs r2, msplim_ns
# PSPLIM
mrs r3, PSPLIM
mrs r3, PSPLIM_NS
mrs r3, psplim
mrs r3, psplim_ns
... |
tactcomplabs/xbgas-binutils-gdb | 1,822 | gas/testsuite/gas/arm/thumb2_ldmstm.s | .syntax unified
.thumb
ldmstm:
ldmia sp!, {r0}
ldmia sp!, {r8}
ldmia r1, {r9}
ldmia r2!, {ip}
ldmdb sp!, {r2}
ldmdb sp!, {r8}
ldmdb r6, {r4}
ldmdb r6, {r8}
ldmdb r2!, {r4}
ldmdb r2!, {ip}
stmia sp!, {r3}
stmia sp!, {r9}
stmia r3, {ip}
stmia r4!, {ip}
stmdb sp!, {r3}
stmdb sp!, {r9}
stmdb r7, {r5}
stmd... |
tactcomplabs/xbgas-binutils-gdb | 13,220 | gas/testsuite/gas/arm/thumb32.s | .text
.thumb
.syntax unified
encode_thumb32_immediate:
orr r0, r1, #0x00000000
orr r0, r1, #0x000000a5
orr r0, r1, #0x00a500a5
orr r0, r1, #0xa500a500
orr r0, r1, #0xa5a5a5a5
orr r0, r1, #0xa5 << 31
orr r0, r1, #0xa5 << 30
orr r0, r1, #0xa5 << 29
orr r0, r1, #0xa5 << 28
orr r0, r1, #0xa5 << 27
orr r0, r... |
tactcomplabs/xbgas-binutils-gdb | 1,091 | gas/testsuite/gas/arm/armv1.s | .global entry
.text
entry:
and r0, r0, r0
ands r0, r0, r0
eor r0, r0, r0
eors r0, r0, r0
sub r0, r0, r0
subs r0, r0, r0
rsb r0, r0, r0
rsbs r0, r0, r0
add r0, r0, r0
adds r0, r0, r0
adc r0, r0, r0
adcs r0, r0, r0
sbc r0, r0, r0
sbcs r0, r0, r0
rsc r0, r0, r0
rscs r0, r0, r0
orr r0, r0, r0
orrs r0, r... |
tactcomplabs/xbgas-binutils-gdb | 18,592 | gas/testsuite/gas/arm/thumb2_bad_reg.s | .syntax unified
.text
.align 2
.thumb
.thumb_func
test:
@ ADC (immediate)
adc r13, r0, #1
adc r15, r0, #1
adc r0, r13, #1
adc r0, r15, #1
@ ADC (register)
adc.w r13, r0, r1
adc.w r15, r0, r1
adc.w r0, r13, r1
adc.w r0, r15, r1
adc.w r0, r1, r13
adc.w r0, r1, r15
@ ADD (immediate)
add.... |
tactcomplabs/xbgas-binutils-gdb | 1,305 | gas/testsuite/gas/arm/mve-vmlaldav-bad.s | .macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlaldav.s16 r0, sp, q1, q2
cond vmlaldav
cond vmlaldava
cond vmlaldavx
cond vmlaldavax
vmlaldav.s64 r0, r1, q1, q2
vmlaldav.f32 r0, r1, q1, q2
vmlaldav.s8 r0, r1, q1, q2
vmlaldav.s16 r0, q1, q2
vmla... |
tactcomplabs/xbgas-binutils-gdb | 1,225 | gas/testsuite/gas/arm/bundle-lock.s | .syntax unified
.bundle_align_mode 4
# We use these macros to test each pattern at every offset from
# bundle alignment, i.e. [0,16) by 2 or 4.
size_arm = 4
size_thumb = 2
.macro offset_sequence which, size, offset
.p2align 4
\which\()_sequence_\size\()_offset_\offset\():
.rept \offset / size_\which
bkpt
.en... |
tactcomplabs/xbgas-binutils-gdb | 12,605 | gas/testsuite/gas/arm/maverick.s | .text
.align
load_store:
cfldrseq mvf5, [sp, #1020]
cfldrsmi mvf14, [r11, #292]
cfldrsvc mvf2, [r12, #-956]
cfldrslt mvf0, [sl, #-1020]
cfldrscc mvf12, [r1, #-156]
cfldrs mvf13, [r9, #416]!
cfldrscs mvf9, [r0, #-1020]!
cfldrsls mvf4, [r1, #-156]!
cfldrsle mvf7, [r9, #416]!
cfldrsvs mvf11, [r0, #-1020]!
cfl... |
tactcomplabs/xbgas-binutils-gdb | 1,052 | gas/testsuite/gas/arm/mve-vcvt-bad-4.s | .macro cond
.irp round, a, n, p, m
.irp cond, eq, ne, gt, ge, lt, le
.irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
it \cond
vcvt\round\size q0, q1
.endr
.endr
.endr
.endm
.syntax unified
.thumb
cond
vcvta.s64.f64 q0, q1
vcvta.u64.f64 q0, q1
vcvta.f64.s64 q0, q1
vcvta.f64.u64 q0, q1
vcvtn.s64.f64 q0, q1
vcvtn.u64.f... |
tactcomplabs/xbgas-binutils-gdb | 3,574 | gas/testsuite/gas/arm/group-reloc-ldc.s | @ LDC group relocation tests.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store
\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
\load 0,... |
tactcomplabs/xbgas-binutils-gdb | 2,214 | gas/testsuite/gas/arm/mve-vstr-bad-1.s | .macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vstrb.s8 q0, [r0, q1]
vstrb.u8 q0, [r0, q1]
vstrb.s16 q0, [r0, q1]
vstrb.u16 q0, [r0, q1]
vstrb.f16 q0, [r0, q1]
vstrb.u32 q0, [r0, q1]
vstrb.s32 q0, [r0, q1]
vstrb.f32 q0, [r0, q1]
vstrb.64 q0, [r... |
tactcomplabs/xbgas-binutils-gdb | 1,067 | gas/testsuite/gas/arm/unwind.s | # Test generation of unwind tables
.text
foo: @ Simple function
.fnstart
.save {r4, lr}
mov r0, #0
.fnend
foo1: @ Typical frame pointer prologue
.fnstart
.movsp ip
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #4
@sub fp, ip, #4
mov r0, #1
.fnend
foo2: @ Custom person... |
tactcomplabs/xbgas-binutils-gdb | 2,681 | gas/testsuite/gas/arm/armv8-ar+fp.s | .syntax unified
.text
.arch_extension fp
.arm
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s3... |
tactcomplabs/xbgas-binutils-gdb | 1,461 | gas/testsuite/gas/arm/mve-vcadd.s | .syntax unified
.thumb
.irp data, i8, i16, f16
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, q0, q1, q2, q4, q7
.irp op4, #90, #270
vcadd.\data \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
.endr
.macro vcadd_q0 data, op2, op4
.irp op3, q1, q2, q4, q7
vcadd.\data q0, \op2, \op3, \op4
.endr
.endm... |
tactcomplabs/xbgas-binutils-gdb | 2,164 | gas/testsuite/gas/arm/t16-bad.s | @ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macr... |
tactcomplabs/xbgas-binutils-gdb | 2,779 | gas/testsuite/gas/arm/vldconst.s | @ Test file for ARM/GAS -- vldr reg, =... expressions.
.fpu neon
.text
.align
foo:
# test both low and high index of the
# Advanced SIMD and Floating-point reg.
.macro vlxr regtype const
.irp regindex, 0, 14, 28, 31
vldr \regtype\regindex, \const
.endr
.endm
.macro vlxreq regtype const
.irp regindex, 0... |
tactcomplabs/xbgas-binutils-gdb | 1,101 | gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s | @ Tests that are supposed to fail during parsing of LDRS group relocations.
.text
@ No NC variants exist for the LDRS relocations.
ldrd r0, [r0, #:pc_g0_nc:(f)]
ldrd r0, [r0, #:pc_g1_nc:(f)]
ldrd r0, [r0, #:sb_g0_nc:(f)]
ldrd r0, [r0, #:sb_g1_nc:(f)]
strd r0, [r0, #:pc_g0_nc:(f)]
strd r0, [r0, #:pc_g1_nc:(f)... |
tactcomplabs/xbgas-binutils-gdb | 2,935 | gas/testsuite/gas/arm/msr-reg.s | @ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from register
msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
@ Write to CPSR flags
msr CPSR,r9
msr CPSR_s... |
tactcomplabs/xbgas-binutils-gdb | 1,699 | gas/testsuite/gas/arm/bfloat16-neon.s | .syntax unified
// Check argument encoding by having different arguments.
// We use 20 and 11 since their binary encoding is 10100 and 01011
// respectively which ensures that we distinguish between the D/M/N bit
// encoding the first or last bit of the argument.
// q registers are encoded as double their actual number... |
tactcomplabs/xbgas-binutils-gdb | 1,295 | gas/testsuite/gas/arm/fpv5-d16.s | .syntax unified
.text
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s3... |
tactcomplabs/xbgas-binutils-gdb | 1,326 | gas/testsuite/gas/arm/armv7e-m+fpv5-d16.s | .syntax unified
.text
.arch armv7e-m
.fpu fpv5-d16
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d8, d8, d8
vselge.f64 d15, d15, d15
vselgt.f64 d10, d10, d10
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s3... |
tactcomplabs/xbgas-binutils-gdb | 1,038 | gas/testsuite/gas/arm/archv8m.s | .thumb
.syntax unified
T:
blx r4
blx r9
bx r4
bx r9
tt r0, r1
tt r8, r9
ttt r0, r1
ttt r8, r9
movw r0, #0xF123
@ mov accept all immediate formats, including T3. It's also the suggested
@ assembly to use.
mov r8, #0xF123
@ .w means wide, specifies that the assembler must select a 32-bit encoding for
@ t... |
tactcomplabs/xbgas-binutils-gdb | 1,694 | gas/testsuite/gas/arm/attr-names.s | .eabi_attribute Tag_CPU_raw_name, "random-cpu"
.eabi_attribute Tag_CPU_name, "cpu"
.eabi_attribute Tag_CPU_arch, 1
.eabi_attribute Tag_CPU_arch_profile, 'S'
.eabi_attribute Tag_ARM_ISA_use, 1
.eabi_attribute Tag_THUMB_ISA_use, 1
.eabi_attribute Tag_FP_arch, 1
.eabi_attribute Tag_VFP_arch, 1
.eabi_attribute Tag_WMMX_arc... |
tactcomplabs/xbgas-binutils-gdb | 1,341 | gas/testsuite/gas/arm/mve-vmullbt.s | .syntax unified
.thumb
.macro helper_q0 op
.irp op2, q1, q2, q4, q7
.irp op3, q1, q2, q4, q7
\op q0, \op2, \op3
.endr
.endr
.endm
.macro helper_q1 op
.irp op2, q0, q2, q4, q7
.irp op3, q0, q2, q4, q7
\op q1, \op2, \op3
.endr
.endr
.endm
.macro helper_q2 op
.irp op2, q0, q1, q4, q7
.irp op3, q0, q1, q4, q7
\op q2, \o... |
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