id string | difficulty string | is_agentic string | instruction string | targets list | dut_module_name string | dut_instance_name string | rtl_files list | spec_files list |
|---|---|---|---|---|---|---|---|---|
cvdp_agentic_byte_enable_ram_0004 | medium | Agentic | I have a specification of a custom_byte_enable_ram module in the docs directory. Write a SystemVerilog testbench `tb_custom_byte_enable_ram.sv` in the verif directory to apply stimulus and achieve maximum coverage for the `custom_byte_enable_ram` module.
Include the following in the generated testbench:
**Module Instance**:
Instantiate the `custom_byte_enable_ram` module as `uut`, ensuring that all input and output ports (covering both port A and port B) are properly connected.
**Clock Generation**:
Implement a clock generator with a 10ns period.
**Stimulus Scenarios**:
In the testbench’s initial block, apply a series of stimulus sequences with delays and $display statements (without using tasks) that cover the following 13 test cases:
- **Test 1**: Full write via port A at address 0 followed by a read-back.
- **Test 2**: Partial write via port B at address 1 followed by a read-back.
- **Test 3**: Dual-port simultaneous write at address 2 with port A writing lower bytes and port B writing upper bytes, then reading back from both ports.
- **Test 4**: Sequential partial writes on port A at address 3, with an initial write using one byte-enable pattern and a subsequent write using a complementary pattern, then reading back.
- **Test 5**: Independent full writes on port A (at address 5) and port B (at address 6) with subsequent reads.
- **Test 6**: Dual-port full write at the same address (address 4) by both ports, then reading the final value (noting that port A’s bytes have priority).
- **Test 7**: Dual-port overlapping partial write at address 7 with interleaved byte enables, then reading back.
- **Test 8**: Dual-port write at address 9 where port A has no active byte enables and port B performs a full write, followed by a read-back.
- **Test 9**: Sequential writes at address 10 with an initial full write via port A and a subsequent partial update via port B, then reading back.
- **Test 10**: A no-update scenario at address 11 where an initial full write is not altered by a cycle with both ports enabled but with zero byte enables, then reading back.
- **Test 11**: Write at address 25 with only port B enabled, then reading back from both ports.
- **Test 12**: Read at addresses 100 and 101 with both ports disabled to verify unchanged memory.
- **Test 13**: Separate partial writes at different addresses (address 12 via port A and address 13 via port B) with subsequent reads.
The testbench should structure these stimulus sequences directly within an initial block using appropriate delays and $display calls for traceability and debugging. Do not include checker logic or internal state validation—this testbench is solely for generating stimulus. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | custom_byte_enable_ram | uut | [
{
"name": "custom_byte_enable_ram.sv",
"content": "module custom_byte_enable_ram \n #(\n parameter XLEN = 32,\n parameter LINES = 8192\n )\n (\n input logic clk,\n input logic[$clog2(LINES)-1:0] addr_a,\n input logic en_a,\n input logic[XLEN... | [
{
"name": "specs.md",
"content": "# Custom Byte-Enable RAM Module\n\nThis module implements a dual-port RAM with byte-enable support and pipelining, designed for efficient memory operations in systems such as processors or embedded controllers. It features separate interfaces for two independent ports (Port... |
cvdp_copilot_hamming_code_tx_and_rx_0031 | easy | Non-Agentic | Create a testbench to only supply stimulus to a `hamming_code_receiver` module. This module decodes an 8-bit input signal and detects single-bit errors using Hamming code principles. The receiver performs "even parity checks" to identify single-bit errors in `data_in` and provides corrected 4-bit data through the output port `data_out[3:0]`.
---
### **RTL Specification**
#### 1. **Module Interface**
**Inputs:**
- `data_in[7:0]` – An 8-bit input signal containing 4 data bits, 3 parity bits, and 1 redundant bit.
**Output:**
- `data_out[3:0]` – A 4-bit output signal containing the corrected data if an error is detected. If no error is detected, the output mirrors the data bits in the input (`data_in`).
#### 2. **Module Functionality**
The module uses Hamming code principles to detect and correct single-bit errors in the 8-bit input (`data_in`). The organization of bits in the input is as follows:
- **Parity Bits:** Placed at positions that are powers of 2 in `data_in`:
- `data_in[1]` (2<sup>0</sup> = 1),
- `data_in[2]` (2<sup>1</sup> = 2),
- `data_in[4]` (2<sup>2</sup> = 4).
- **Data Bits:** Placed sequentially in positions that are not powers of 2:
- `data_in[3]`, `data_in[5]`, `data_in[6]`, and `data_in[7]`.
#### 2.1. **Error Detection and Correction**
- The module calculates three syndrome bits (`c1`, `c2`, `c3`) using XOR operations on specific data and parity bits from `data_in`. These syndrome bits indicate the position of any error within the 7 most significant bits (`data_in[7:1]`).
- If an error is detected, the incorrect bit is corrected.
#### 2.2. **Output Assignment**
- After error correction, the module retrieves the 4 data bits from the corrected input and assigns them to the output port `data_out[3:0]`.
- The positions of the data bits in the input correspond to:
- `data_in[3]`, `data_in[5]`, `data_in[6]`, and `data_in[7]`.
#### 3. **Timing and Synchronization**
- The design is purely combinational, meaning the output is updated immediately after any change in the input.
---
### **Testbench Requirements**
- **Module Instance:** The `hamming_code_receiver` module should be instantiated as **`uut_receiver`**, with input and output signals connected for testing.
---
### **Input Generation and Validation**
1. **Input Generation:**
- The testbench should generate all possible 4-bit binary values for input data (ranging from the minimum value (0) to the maximum value (2<sup>4</sup> - 1)) and extend it to include encoding bits before supplying the stimulus to the design, ensuring coverage of both typical cases and edge cases.
3. **Golden Encoder Logic:**
- Inputs provided to the module should follow a specific pattern similar to data generated from a transmitter following hamming code principles. It should also ensure that erroneous input data is supplied with only single-bit errors (as the RTL is capable of correcting only single-bit errors)
- The testbench should encode the generated 4-bit data into an 8-bit data (golden encoded data) using Hamming code principles for error detection.
- The encoding process based on Hamming code principles is as follows: (Assume the 4-bit data generated internally is `data_in` and it is extended to `golden_data_out`)
1. **`golden_data_out[0]`**: A redundant bit, fixed at 0.
2. **`golden_data_out[1]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[0]`, `data_in[1]`, and `data_in[3]`.
3. **`golden_data_out[2]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[0]`, `data_in[2]`, and `data_in[3]`.
4. **`golden_data_out[4]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[1]`, `data_in[2]`, and `data_in[3]`.
5. **`golden_data_out[3]`, `golden_data_out[5]`, `golden_data_out[6]`, `golden_data_out[7]`**: These are the data bits `data[0]`, `data[1]`, `data[2]`, and `data[3]` respectively, in the same order.
- To simulate errors, a single bit in the **golden encoded data** must be randomly modified. This modified data should then be assigned to the input of the design under test (**`uut_receiver`**).
4. **Stabilization Period:**
- After assigning each input value, the testbench must wait for 10 time units to ensure that the outputs have stabilized before asserting new values.
--- | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 100
}
] | hamming_code_receiver | uut_receiver | [
{
"name": "hamming_code_receiver.sv",
"content": "module hamming_code_receiver (\n input[7:0] data_in,\n output [3:0] data_out\n);\n \n wire c1,c2,c3,error;\n reg[7:0] correct_data;\n \n \n assign c3 = data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[7];\n assign c2 = data_in[2] ^ data_in[3] ^ data_in... | [] |
cvdp_copilot_simple_spi_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `spi_fsm`. The module handles data transmission in a serial format from a 16-bit input vector (`i_data_in`) using an SPI protocol. The design includes proper state transitions, signal handling, and timing synchronization to ensure accurate data transmission. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
### Inputs
1. **`i_clk`** (1-bit, Input):
- System clock signal for synchronous operations.
2. **`i_rst_b`** (1-bit, Input):
- Active-low asynchronous reset. Upon activation, the system must reset all internal states and outputs.
3. **`i_data_in`** (16-bit, Input):
- Input data vector to be serialized and transmitted through the SPI bus.
4. **`i_enable`** (1-bit, Input):
- Control signal to enable or disable the block.
- High (`1`): The block operates normally, and data transmission occurs.
- Low (`0`): The block resets to the idle state, disabling transmission.
5. **`i_fault`** (1-bit, Input):
- Indicates a fault condition. If asserted, the FSM transitions to an error state, halts all activity, and drives outputs to safe defaults.
6. **`i_clear`** (1-bit, Input):
- Forces the FSM to immediately clear the current transaction, clear counters, and transition to the idle state.
---
### Outputs
1. **`o_spi_cs_b`** (1-bit, Output):
- Active-low SPI chip select signal to indicate the start and end of a transmission. Default is logic high when idle.
2. **`o_spi_clk`** (1-bit, Output):
- SPI clock signal for synchronizing data transfers. The clock signal toggles during transmission. Default is logic low when idle or disabled.
3. **`o_spi_data`** (1-bit, Output):
- Serialized SPI data output derived from the `i_data_in` input vector. Default is logic low when idle or disabled.
4. **`o_bits_left`** (5-bit, Output):
- Tracks the number of bits remaining to be transmitted during the SPI session. Default is `0x10` (all bits remaining).
5. **`o_done`** (1-bit, Output):
- Pulses high for exactly one clock cycle when a transaction is successfully completed or the FSM transitions to an error state.
6. **`o_fsm_state`** (2-bit, Output):
- Reflects the internal FSM state for external monitoring:
- `00` = Idle
- `01` = Transmit
- `10` = Clock Toggle
- `11` = Error
---
### Behavioral Requirements
1. **FSM States**:
- **Idle** (`00`): Initialize SPI signals (`o_spi_cs_b = 1`, `o_spi_clk = 0`) and wait for `i_enable = 1` to begin transmission.
- **Transmit** (`01`): Activate SPI signals (`o_spi_cs_b = 0`), load the MSB of `i_data_in` into `o_spi_data`, and start shifting the bits out sequentially.
- **Clock Toggle** (`10`): Toggle `o_spi_clk` to latch `o_spi_data` externally, decrement `o_bits_left`, and determine if more bits remain to be transmitted. If all bits are sent, assert `o_done` and transition to Idle.
- **Error** (`11`): Entered upon assertion of `i_fault`. All SPI outputs are driven to safe values (`o_spi_cs_b = 1`, `o_spi_clk = 0`, `o_spi_data = 0`,`o_done`=0,`o_bits_left=10`), and the FSM remains here until cleared or reset.
2. **Control Signals**:
- **Enable (`i_enable`)**:
- If asserted (`1`): FSM proceeds through normal transmission states (`Transmit` and `Clock Toggle`).
- If deasserted (`0`): FSM immediately transitions to Idle and resets all active outputs.
- **Clear (`i_clear`)**:
- When asserted, FSM immediately transitions to Idle, resetting all counters and outputs regardless of the current state.
3. **Done Signal (`o_done`)**:
- Asserted (high) for one clock cycle upon successful completion of transmission.
4. **FSM State Output (`o_fsm_state`)**:
- Reflects the current FSM state in real-time for external monitoring.
## Test Bench Requirements
### Stimulus Generation
**1. Reset and Initialization**
- Apply the reset is applied.
**2. Normal SPI Transmission**
- Enable the FSM and provide a valid data input to initiate a transmission.
- Introduce multiple consecutive transmissions without disabling the FSM to check if data is continuously processed as expected.
- Attempt to modify the input data while transmission is ongoing to ensure that changes do not interfere with the current operation.
**3. Control Signal Handling**
- Disable the FSM while a transmission is in progress.
- Force the FSM to clear its current operation while actively transmitting to confirm that it returns to idle without completing the remaining shifts.
**4. Error Handling**
- Introduce an error condition during transmission.
- Attempt to recover from the error by applying a reset-like condition.
**5. Clock and Edge Case Behavior**
- Make the FSM to properly toggle the SPI clock signal during transmission, synchronizing data shifts.
- Test the handling of extreme data values, including cases where only a single bit is set.
- Execute back-to-back transmissions with varying data patterns. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 94
}
] | spi_fsm | dut | [
{
"name": "spi_fsm.v",
"content": "module spi_fsm (\n input wire i_clk, // System clock\n input wire i_rst_b, // Active-low async reset\n input wire [15:0] i_data_in, // Parallel 16-bit data to transmit\n input wire i_enable, // Enable block\n input... | [] |
cvdp_copilot_word_reducer_0012 | easy | Non-Agentic | Create a testbench named `tb_Bit_Difference_Counter` using SystemVerilog to generate stimulus for the `Bit_Difference_Counter` module, which calculates the hamming distance (bitwise difference) between two inputs of equal bit width. The testbench should apply edge-case scenarios and random input patterns to thoroughly exercise the module. The testbench should only contain stimulus generator.
## Module: `Bit_Difference_Counter`
### Parameters:
- **BIT_WIDTH**: Defines the width of the input vectors, with a default value of 3. This parameter must be a positive integer greater than or equal to 1.
- **COUNT_WIDTH**: The expression calculates $clog2(BIT_WIDTH + 1), which is the width required to represent the maximum possible number of differing bits.
### Inputs
1. **`[BIT_WIDTH-1:0] input_A`**: A binary input signal.
2. **`[BIT_WIDTH-1:0] input_B`**: A binary input signal of the same width as `input_A`.
### Output
1. **`[COUNT_WIDTH-1:0] bit_difference_count`**: The output indicates the Hamming distance between `input_A` and `input_B`. The Hamming distance is the number of differing bits between the two inputs.
## Testbench Design
### Instantiation
The `Bit_Difference_Counter` module is instantiated as `dut`, with the following connections:
- **Inputs**: `input_A` and `input_B`
- **Output**: `bit_difference_count`
## Input Generation
### Edge Case Testing
1. **All Zero Inputs**: Generate a test case where both inputs are composed entirely of zeros (0).
2. **All One Inputs**: Generate a test case where both inputs are composed entirely of ones (1).
3. **Completely Different Inputs**: Generate a test case where one input is all zeros and the other is all ones.
4. **Single Bit Differences**: For each bit position in the input, generate test cases where the inputs differ by only that single bit.
### Randomized Testing
- Randomly generates 100 test cases for `input_A` and `input_B`, covering various combinations of differing bits. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | Bit_Difference_Counter | dut | [
{
"name": "Data_Reduction.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Bit_Difference_Counter\n#(\n parameter BIT_WIDTH = 3, // Defines the width of the input vectors.\n localparam COUNT_WIDTH = $clog2(BIT_WIDTH + 1) // Calculates the width required to represent th... | [] |
cvdp_agentic_ttc_lite_0007 | hard | Agentic | I have a specification of a `ttc_counter_lite` module in the `docs` directory. Write a SystemVerilog TB `ttc_counter_lite_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `ttc_counter_lite` module.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the `ttc_counter_lite` module as `dut`, appropriately connecting all input and output signals.
- **Clock Generation**: Use a 100 MHz clock with a 10ns period (`clk_in`).
- **Reset Procedure**: Create an apply_reset task that
- Asserts reset for 10 clock cycles.
- Desserts it before the stimulus begin
- Reapplies reset mid-operation to test FSM recovery behavior.
- **Basic Register Access Tasks**
Implement the following tasks to drive valid AXI-style register-level operations:
- axi_write: Drives write transactions using `axi_addr`, `axi_wdata`, and `axi_write_en`.
- axi_read: Performs read transactions and prints `axi_rdata` for traceability and debug visibility.
- axi_read_force_toggle_full: Forces and releases upper toggle bits in `axi_rdata` to stimulate data bus transitions.
- drive_counter_to_upper_bits: Configures the control, match, and reload registers to run the counter long enough to
toggle the upper counter bits.
- toggle_prescaler_bits: Writes and clears the prescaler register to trigger bit toggles and verify prescaler logic.
- **Stress and Coverage Stimulus**:
Apply diverse stimuli to activate all reachable RTL states, signal transitions, and FSM paths:
- Read all defined address registers after reset to cover initial state logic.
- Write to `MATCH` and `RELOAD` registers using:
- Minimum value: `0x00000000`
- Maximum value: `0x0000FFFF`
- Drive various `CONTROL` register modes including:
- Enable / Disable
- Reload mode
- Interval mode
- Cover counter wrap-around and overflow behavior using small reload and match values.
- Perform writes/reads to invalid or unused addresses(e.g., `0xF`, `0x1000`) to trigger decoder edge cases.
- Toggle enable modes during ongoing counting to test runtime configurability.
- Apply **1-cycle read/write pulses** to target glitchy signal paths or edge-sensitive conditions.
- Perform **reset mid-operation** and after multiple transactions to test FSM recovery behavior.
- Write known upper-bit patterns to all writable registers and read them back to observe **toggle logic** in `axi_rdata`.
- Repeat read/write sequences to:
- `CONTROL`
- `MATCH`
- `RELOAD`
- `PRESCALER`
- **Stress and Sequence Coverage**
Run repeated sequences and edge cases to validate internal behavior:
- Enable timer → wait → read counter
- Enable → Disable → Enable transitions
- Write **invalid configuration values** to test FSM error handling
- Perform `Write → Read` transitions with:
- Short delays
- Long idle intervals
- Issue high-speed, back-to-back register accesses with minimal spacing
- Vary `axi_addr` to cover:
- All address bits
- Edge and boundary cases
Do not include checkers, assertions, or internal state comparisons. The testbench should be structured strictly for applying input stimulus to the DUT and exercising its logic comprehensively. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | ttc_counter_lite | dut | [
{
"name": "ttc_counter_lite.sv",
"content": "`timescale 1ns / 1ps\nmodule ttc_counter_lite (\n input wire clk, // Clock signal\n input wire reset, // Reset signal\n input wire [3:0] axi_addr, // AXI address for read/write\n input wire [3... | [
{
"name": "specification.md",
"content": "# ttc_counter_lite Specification Document\n\n## Introduction\n\nThe **ttc_counter_lite** module implements a lightweight, programmable timer with support for **interval and single-shot counting modes**. It includes a 16-bit up-counter, configurable match and reload ... |
cvdp_copilot_bcd_adder_0007 | easy | Non-Agentic | Create a testbench to generate stimulus for the `bcd_adder` module, which performs Binary Coded Decimal (BCD) addition on two 4-bit inputs, a and b.
## Testbench Description
### Inputs
- Registers: a and b are 4-bit registers that provide the two BCD numbers to be added.
### Outputs
- The outputs from the BCD adder include a 4-bit sum (`sum`) and a carry-out signal (`cout`).
### Instantiation
- The bcd_adder module is instantiated as uut, with the input and output signals connected for testing.
## Input Generation
- Input Data Generation: The testbench generates all possible combinations of a and b in the range from 0 to 9 (since the inputs are BCD digits).
---
Follows the specification for building the RTL of the module, use it as a reference for the verification environment too:
### Inputs
- [3:0] a: 4-bit input representing a BCD value.
- [3:0] b: 4-bit input representing another BCD value.
### Outputs
- [3:0] sum: 4-bit output representing the BCD-corrected sum of `a` and `b`.
- cout: Single-bit output indicating if a carry is generated during the BCD addition.
---
### Design Description
The `bcd_adder` module performs Binary Coded Decimal (BCD) addition. It consists of three primary blocks:
1. **Binary Adder:** A 4-bit binary adder calculates the intermediate sum (`binary_sum`) and carry (`binary_cout`).
2. **Logic Block:** Detects whether BCD correction is needed based on the upper bits of the intermediate binary sum.
3. **BCD Correction:** If correction is required, adds 6 to the intermediate sum to produce the final BCD-corrected output. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | bcd_adder | uut | [
{
"name": "bcd_adder.sv",
"content": "module bcd_adder( \n input [3:0] a, // 4-bit BCD input\n input [3:0] b, // 4-bit BCD input\n output [3:0] sum, // The corrected 4-bit BCD result of the addition\n ... | [] |
cvdp_copilot_apb_history_shift_register_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `APBGlobalHistoryRegister`. The register updates synchronously on every gated rising edge of the `history_shift_valid` clock, shifting in predicted outcomes or restoring history on mispredictions. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
---
### 1. Interface
#### 1.1 Clock & Reset Signals
- **`pclk`** (input): APB clock input used for all synchronous operations.
- **`presetn`** (input, active-low): Asynchronous reset for system initialization.
#### 1.2 APB Signals
- **`paddr`** (input, 10 bits): Address bus for accessing internal CSR registers.
- **`pselx`** (input): APB select signal, indicates CSR/memory selection.
- **`penable`** (input): APB enable signal, marks transaction progression.
- **`pwrite`** (input): Write-enable signal. High for writes, low for reads.
- **`pwdata`** (input, 8 bits): Write data bus for sending data to CSR registers or memory.
- **`pready`** (output, reg): Ready signal, driven high to indicate the end of a transaction.
- **`prdata`** (output, reg, 8 bits): Read data bus for retrieving data from the module.
- **`pslverr`** (output, reg): Error signal, asserted on invalid addresses.
#### 1.3 History Shift Interface
- **`history_shift_valid`** (input): On the rising edge of this signal, the values in `control_register` and `train_history` are considered valid and will trigger an update of the predict_history register.
#### 1.4 Clock Gating Enable
- **`clk_gate_en`** (input): Signal in domain of `pclk`, which will be toggle only on negative edge of `pclk` to avoid glitches. Assertion of this signal will gate the `pclk` internally to minimize switching power.
#### 1.4 Status & Interrupt Signals
- **`history_full`** (output): Indicates if the 8-bit shift register is full (all bits set to 1).
- **`history_empty`** (output): Indicates if the 8-bit shift register is empty (all bits cleared to 0).
- **`error_flag`** (output): Indicates detected errors for invalid address.
- **`interrupt_full`** (output): Asserted high to signal an interrupt when history_full is set.
- **`interrupt_error`** (output): Asserted high to signal an interrupt when error_flag is set.
---
### 2. Register Descriptions
1. **`control_register`**
- **Address:** `0x0`
- Bit fields (from LSB to MSB):
- `predict_valid` (control_register[0]): Indicates a valid branch prediction.
- `predict_taken` (control_register[1]): Predicted direction of the branch (1 = taken, 0 = not taken).
- `train_mispredicted` (control_register[2]): Indicates a branch misprediction occurred.
- `train_taken` (control_register[3]): Actual direction of the mispredicted branch (1 = taken, 0 = not taken).
- control_register[7:4]: Reserved and will be read 0.
- Read and write register.
2. **`train_history`**
- **Address:** `0x1`
- 7 bits (`train_history[6:0]`) representing the recorded branch history prior to the mispredicted branch.
- train_history[7]: Reserved and will be read 0.
- Read and write register.
3. **`predict_history`**
- **Address:** `0x2`
- 8-bit register representing the current state of the branch history shift register.
- Updated only on the rising edge of `history_shift_valid`.
- Can be read via the APB interface (using `prdata`).
- Can't be written via APB interface.
---
### 3. Functional Description
#### 3.1 APB Protocol
1. **Read Operations**
- In the **READ_STATE**:
- Drive `prdata` with the register value corresponding to `paddr`.
- After the read completes, return to **IDLE**.
2. **Write Operations**
- In the **WRITE_STATE**:
- Update the register selected by `paddr` with `pwdata`.
- After the write completes, return to **IDLE**.
3. **Reset Behavior**
- When `presetn` is deasserted (active-low):
- Reset `pready` and `pslverr` to 0.
- Clear `prdata`.
- Initialize `control_register` and `train_history` to 0.
- Reset the shift register to zero (`predict_history = 8'b0`).
#### 3.2 APB Interface Control
1. **Basics**
- Registers are accessed via the APB interface using `paddr`.
- To read the computed prediction history, use address **0x2**; the data is returned on `prdata`.
2. **Error Handling**
- If `paddr` does not correspond to a valid register, assert `pslverr` (`1'b1`).
3. **Wait States**
- This design does not support wait states. All read/write operations complete in two clock cycles, and `pready` is always driven high (`1'b1`).
---
### 4. Prediction Update Logic
1. **Normal Update**
- If `predict_valid = 1` and no misprediction occurs (`train_mispredicted = 0`), the shift register updates by shifting in `predict_taken` from the least significant bit (LSB). The youngest branch direction is stored in `predict_history[0]`.
2. **Misprediction Handling**
- If `train_mispredicted = 1`, the shift register is updated synchronously with `history_shift_valid` to load the concatenation of `train_history` (7 bits) with `train_taken` (1 bit). This restores the history state before the mispredicted branch while incorporating the actual outcome of the mispredicted branch.
3. **Priority**
- If both `predict_valid` and `train_mispredicted` are asserted simultaneously, `train_mispredicted` takes precedence. The misprediction state overrides any prediction to ensure correct recovery of the pipeline state.
4. **Output Behavior**
- `predict_history` (the shift register) is updated only on the rising edge of `history_shift_valid`.
- `history_full` is asserted if predict_history contains all ones (8'hFF) else it will be deasserted.
- `history_empty` is asserted if predict_history contains all zeros (8'h00) else it will be deasserted.
- `interrupt_full` is directly driven by history_full.
- `interrupt_error` is directly driven by error_flag.
Note: Need not to worry about mixing synchronous (pclk) and asynchronous (history_shift_valid) control which can lead to metastability and timing issues. The history_shift_valid will trigger only in absense of pclk.
## Test Bench Requirements
### Stimulus Generation
## 1. **Reset & Initialization Stimuli**
- **Apply and Release Reset**
1. Deassert the active-low reset (`presetn`) after a certain period while the clock toggles, ensuring all internal registers begin at default states.
2. Keep clock transitions valid during reset deassertion.
---
## 2. **APB Interface Stimuli**
### 2.1 **Valid Register Accesses**
- **Write to Control Register**
1. Present the address corresponding to `control_register` on `paddr`.
2. Drive APB signals (`pselx`, `penable`, `pwrite`) for a valid write transaction.
3. Provide varied data patterns on `pwdata` that affect bits `[3:0]` of `control_register`.
- **Write to Train History Register**
1. Present the address corresponding to `train_history` on `paddr`.
2. Drive valid APB write signals.
3. Send multiple data patterns that affect bits `[6:0]`.
- **Read from Control/Register/Train History/Predict History**
1. Present each valid address in turn (`0x0`, `0x1`, `0x2`).
2. Drive APB signals for read transactions.
### 2.2 **Invalid Register Access**
- **Access Addresses Beyond Valid Range**
1. Set `paddr` to a value beyond the defined valid set (greater than `0x2`).
2. Drive an APB read or write cycle.
---
## 3. **Clock Gating Stimuli**
- **Toggle `clk_gate_en`**
1. Drive `clk_gate_en` active and inactive at different moments, including while issuing valid APB transactions.
2. Ensure transitions occur on safe clock edges, demonstrating partial or no internal updates under gating.
---
## 4. **Shift Register Update Stimuli**
### 4.1 **No Update Condition**
- **Drive Control Bits for No-Action**
1. Set `predict_valid` and `train_mispredicted` to inactive states.
2. Pulse the `history_shift_valid` signal.
### 4.2 **Normal Prediction Updates**
- **Drive Valid Prediction**
1. Set `predict_valid` active in `control_register`.
2. Alternate the predicted direction bit (`predict_taken`) across multiple pulses of `history_shift_valid`.
3. Repeat for various patterns of taken/not-taken.
### 4.3 **Misprediction Handling**
- **Restore from Train History**
1. Write desired values into `train_history`.
2. Set `train_mispredicted` active, along with a chosen `train_taken` bit.
3. Drive `history_shift_valid` to force the restore path.
- **Simultaneous Valid Prediction & Misprediction**
1. Set both `predict_valid` and `train_mispredicted` active in the same cycle.
2. Pulse `history_shift_valid`.
---
## 5. **Edge Conditions for the Shift Register**
- **All-Zero to All-One Transitions**
1. Repeatedly provide inputs (via normal prediction or misprediction) so that the shift register transitions from all zeros to all ones.
2. Similarly, drive it back from all ones to all zeros with a series of stimuli.
---
## 6. **Error & Interrupt Stimuli**
- **Trigger Invalid APB Transactions**
1. Provide out-of-range addresses and drive write or read cycles.
- **Generate Interrupt Conditions**
1. Fill the shift register to all ones (to drive any “full” interrupt).
2. Cause invalid address access (to drive error interrupt).
---
## 7. **Combined Complex Sequences**
- **Integrated Flow**
1. Begin with reset cycling.
2. Perform valid reads and writes to internal registers.
3. Toggle `clk_gate_en`.
4. Issue valid predictions and a series of mispredictions.
5. Drive the shift register from empty to full.
6. Include at least one invalid address access mid-sequence.
## 8. **Additional Test Scenarios**
- **Reset During Operation** – Ensures the system can reinitialize correctly when reset is asserted dynamically, not just at startup.
- **Reserved Bit Handling** – Toggles unused register fields to confirm they remain stable and do not interfere with functionality.
- **Expanded Address Access** – Interacts with a broader address range to verify correct handling of both valid and invalid accesses.
- **Repeated Prediction History Reads** – Ensures the stored history updates correctly and all bits are exercised across different states.
- **Response Signal Validation** – Checks readiness and status transitions across reset, transactions, and different operating conditions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | APBGlobalHistoryRegister | dut | [
{
"name": "APBGlobalHistoryRegister.v",
"content": "module APBGlobalHistoryRegister (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire ... | [] |
cvdp_copilot_ring_token_0004 | easy | Non-Agentic | Create a SystemVerilog testbench module named **`tb_token_ring_fsm`** that instantiates the `token_ring_fsm` module as the Unit Under Test (UUT). The testbench must include a **stimulus generator** that systematically drives various input conditions to achieve **100% code and functional coverage** for the `token_ring_fsm`. The `token_ring_fsm` implements a **Finite State Machine (FSM)-based token-passing mechanism** in a four-node ring network, ensuring controlled data transmission between nodes. The stimulus should cover **all state transitions, token passing, data transmission scenarios, and asynchronous reset conditions** while logging outputs for debugging and verification.
---
## **Description**
### **Inputs**
- **Clock Signal**:
- `clk`: Positive edge-triggered clock signal driving the FSM.
- **Reset Signal**:
- `rst`: Asynchronous active-high reset signal that initializes the FSM.
- **Data and Control Inputs**:
- `data_in [3:0]`: A 4-bit input representing binary data for transmission by the current node.
- `has_data_to_send`: A 1-bit signal indicating whether the current node has data to send.
### **Outputs**
- **Data and Token Outputs**:
- `data_out [3:0]`: A 4-bit output representing the data transmitted by the current node.
- `token_received [3:0]`: A 4-bit one-hot encoded signal indicating which node currently holds the token.
- `token [3:0]`: A 4-bit one-hot encoded signal representing the token being passed to the next node.
---
## **Input Generation**
### **State Transitions and Token Passing**
- Drive the FSM through all four states:
- `NODE0 to NODE1 to NODE2 to NODE3 to NODE0` in a cyclic manner.
- Ensure that `token_received` correctly identifies the node holding the token.
- Simulate token passing by shifting the `token` signal across nodes and verifying correct cycling.
### **Data Transmission Stimulus**
- Generate various patterns for `data_in` and toggle `has_data_to_send` to simulate:
- Nodes transmitting data when they hold the token.
- Nodes idling when `has_data_to_send` is LOW.
- Different data values being sent across nodes.
### **Edge Case Testing**
- **Reset Behavior**:
- Apply `rst` at different states to ensure FSM returns to `NODE0`.
- Verify that `token_received` is set to `4'b0001` and `data_out`, `token` are cleared.
- **Token Handling**:
- Simulate idle conditions where no node is ready to send data.
- Inject forced token values using `force` and `release` commands to verify FSM recovery.
- **Overlapping Data Transmission**:
- Test scenarios where multiple nodes attempt to send data consecutively.
- Ensure only the node holding the token transmits data.
---
## **Instantiation**
- The instance of the RTL should be named **`uut`**.
---
## **Module Interface**
### **Inputs**
- `clk`: Clock signal.
- `rst`: Asynchronous active-high reset signal.
- `data_in [3:0]`: Data input for transmission.
- `has_data_to_send`: Indicates whether the node has data to send.
### **Outputs**
- `data_out [3:0]`: Transmitted data output.
- `token_received [3:0]`: Indicates the node currently holding the token.
- `token [3:0]`: Indicates the token being passed to the next node.
---
## **Module Functionality**
1. **Token Passing Mechanism**:
- The FSM cycles through the four nodes, passing the token sequentially.
- The node with the token is allowed to transmit data if `has_data_to_send` is HIGH.
2. **Data Transmission**:
- When a node holds the token and `has_data_to_send` is HIGH, `data_out` reflects `data_in`.
- If no node is ready to send, `data_out` remains `4'b0000`.
3. **Reset Behavior**:
- When `rst` is asserted HIGH, the FSM resets to `NODE0`, `token_received` is set to `4'b0001`, and other outputs are cleared.
4. **Edge Cases**:
- Idle conditions where no node transmits data.
- Forced invalid states and token values to test FSM recovery.
- Multiple data transmissions in consecutive cycles.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | token_ring_fsm | uut | [
{
"name": "token_ring_fsm.sv",
"content": "module token_ring_fsm (\n input logic clk, // Clock input\n input logic rst, // Reset input\n input logic [3:0] data_in, // Data input from node\n output reg [3:0] data_out, // Data output to node\n input logic has_dat... | [] |
cvdp_copilot_morse_code_0027 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `morse_encoder_tb`. The testbench must instantiate the `morse_encoder` **RTL** module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `morse_encoder` module converts an **8-bit ASCII input** into a **6-bit Morse code output** along with the **length** of the Morse representation.
---
## **Description:**
### **Inputs**:
Registers:
- `ascii_in` (8-bit, `[7:0]`): ASCII character input supplied to the **DUT**.
### **Outputs**:
Registers:
- `morse_out` (6-bit, `[5:0]`): Encoded Morse representation received from the **DUT**.
- `morse_length` (4-bit, `[3:0]`): Length of the Morse code sequence for the given input character.
---
## **Instantiation:**
The testbench instantiates the `morse_encoder` module as **dut** and connects the signals between the module and the testbench.
Each input and output from the **DUT** is connected to its corresponding signal in the testbench.
---
## **Input Generation and Validation:**
### **Stimulus Generation:**
Multiple test cases are applied to verify Morse encoding for different ASCII characters. The output from the **DUT** is monitored using `$display`.
### **Test Cases:**
- **Alphabet (Uppercase)**
- `ascii_in = 8'h41;` // 'A'
- `ascii_in = 8'h42;` // 'B'
- `ascii_in = 8'h43;` // 'C'
- `ascii_in = 8'h44;` // 'D'
- `ascii_in = 8'h45;` // 'E'
- `ascii_in = 8'h46;` // 'F'
- `ascii_in = 8'h47;` // 'G'
- `ascii_in = 8'h48;` // 'H'
- `ascii_in = 8'h49;` // 'I'
- `ascii_in = 8'h4A;` // 'J'
- `ascii_in = 8'h4B;` // 'K'
- `ascii_in = 8'h4C;` // 'L'
- `ascii_in = 8'h4D;` // 'M'
- `ascii_in = 8'h4E;` // 'N'
- `ascii_in = 8'h4F;` // 'O'
- `ascii_in = 8'h50;` // 'P'
- `ascii_in = 8'h51;` // 'Q'
- `ascii_in = 8'h52;` // 'R'
- `ascii_in = 8'h53;` // 'S'
- `ascii_in = 8'h54;` // 'T'
- `ascii_in = 8'h55;` // 'U'
- `ascii_in = 8'h56;` // 'V'
- `ascii_in = 8'h57;` // 'W'
- `ascii_in = 8'h58;` // 'X'
- `ascii_in = 8'h59;` // 'Y'
- `ascii_in = 8'h5A;` // 'Z'
- **Numbers (0-9)**
- `ascii_in = 8'h30;` // '0'
- `ascii_in = 8'h31;` // '1'
- `ascii_in = 8'h32;` // '2'
- `ascii_in = 8'h33;` // '3'
- `ascii_in = 8'h34;` // '4'
- `ascii_in = 8'h35;` // '5'
- `ascii_in = 8'h36;` // '6'
- `ascii_in = 8'h37;` // '7'
- `ascii_in = 8'h38;` // '8'
- `ascii_in = 8'h39;` // '9'
- **Punctuation and Special Characters**
- `ascii_in = 8'h2E;` // '.'
- `ascii_in = 8'h2C;` // ','
- `ascii_in = 8'h3F;` // '?'
- `ascii_in = 8'h27;` // "'"
- `ascii_in = 8'h21;` // '!'
- `ascii_in = 8'h2F;` // '/'
- `ascii_in = 8'h28;` // '('
- `ascii_in = 8'h29;` // ')'
- `ascii_in = 8'h26;` // '&'
- `ascii_in = 8'h3A;` // ':'
- `ascii_in = 8'h3B;` // ';'
- `ascii_in = 8'h3D;` // '='
- `ascii_in = 8'h2B;` // '+'
- `ascii_in = 8'h2D;` // '-'
- `ascii_in = 8'h22;` // '"'
- `ascii_in = 8'h40;` // '@'
- **Edge Cases and Invalid Inputs**
- `ascii_in = 8'h00;` // NULL
- `ascii_in = 8'hFF;` // Maximum 8-bit value
- `ascii_in = 8'h7B;` // '{'
- `ascii_in = 8'h7F;` // DEL
- `ascii_in = 8'h5D;` // ']'
- `ascii_in = 8'h5B;` // '['
- `ascii_in = 8'h7A;` // 'z' (Lowercase)
- `ascii_in = 8'h7C;` // '|'
---
## **Reset Handling:**
At the beginning of the test, an **initial condition** is set to ensure the **DUT** starts in a known state. The testbench then applies each test case sequentially.
---
```verilog
module morse_encoder_tb;
reg [7:0] ascii_in;
wire [5:0] morse_out;
wire [3:0] morse_length;
morse_encoder dut (
.ascii_in(ascii_in),
.morse_out(morse_out),
.morse_length(morse_length)
);
initial begin
$display("Starting Testbench...");
// Insert code here for Test bench
endmodule
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | morse_encoder | dut | [
{
"name": "morse_encoder.sv",
"content": "module morse_encoder (\n input wire [7:0] ascii_in, // ASCII input character\n output reg [5:0] morse_out, // Morse code output \n output reg [3:0] morse_length // Length of the Morse code sequence\n);\n\n always @(*) begin\n case (a... | [] |
cvdp_copilot_restoring_division_0006 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module generates the output `quotient`, `remainder`, and `valid` once the computation is completed for the given `dividend` and `divisor` when the `start` signal is asserted.
## **Design Details**
### **Parameterization**
- **WIDTH**: Specifies the bit-width of the dividend and divisor.
- **Default**: 6 bits
### **Functionality**
The **restoring_division** module implements division using a shift-subtract approach:
- The division process must finish within WIDTH clock cycles if WIDTH is a power of 2 (2^n) to ensure all data is processed; otherwise (if WIDTH is not a power of 2), it will take WIDTH+1 clock cycles.
- The FSM governs the state transitions and ensures proper computation.
- The division process begins when `start` is asserted and completes when `valid` is high.
## **Signal Behavior**
### Inputs:
- **`clk`**: 1-bit clock signal, toggles every 5 time units.
- **`rst`**: Active-low reset signal to initialize the module.
- **`start`**: Start signal to begin the division process.
- **`dividend`**: `WIDTH`-bit input representing the dividend.
- **`divisor`**: `WIDTH`-bit input representing the divisor.
### Outputs:
- **`quotient`**: `WIDTH`-bit result of the division operation.
- **`remainder`**: `WIDTH`-bit remainder of the division operation.
- **`valid`**: 1-bit signal indicating completion of division.
---
## **Testbench Requirements**
### **Instantiation**
- **Module Instance**: The **restoring_division** module should be instantiated as `uut`, with all inputs and outputs properly connected.
### **Input Generation and Validation**
1. **Clock Generation**:
- The testbench must generate a clock signal with a 10 ns period.
- The clock should toggle every **5 time units**.
2. **Reset Behavior**:
- The reset signal should be asserted low initially.
- After 10 ns, reset should be de-asserted (set high) to allow normal operation.
3. **Division Test Cases**:
- A **task** named `run_test` should be used to apply test cases dynamically.
- The testbench should generate **random** values for `dividend` and `divisor`.
- The **divisor should never be zero** (handled by ensuring divisor ≥ 1).
- The division process should be started by asserting `start` high for one cycle.
- The testbench must **wait for `valid`** to be asserted before capturing the results.
- The computed **quotient and remainder** should be displayed for debugging.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\n\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start signal to b... | [] |
cvdp_copilot_restoring_division_0034 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module produces the `quotient`, `remainder`, and asserts the `valid` signal upon computation completion. Additionally, it sets the `divisor_valid_result` flag to indicate whether the divisor was valid (nonzero) when the `start` signal is asserted with the `dividend` and `divisor` inputs.
---
## **Design Details**
### **Parameterization**
- **WIDTH**: Specifies the bit-width of the dividend and divisor.
- **Default**: 6
### **Functionality**
The **restoring_division** module performs unsigned integer division using a sequential **restoring division algorithm**. The quotient and remainder are computed iteratively over multiple clock cycles.
#### **Division Process and Output Behavior**
- The computation is **iterative** and progresses bit-by-bit over **WIDTH** clock cycles.
- The division process must finish within WIDTH clock cycles if WIDTH is a power of 2 (2^n) to ensuring all data is processed; otherwise (if WIDTH is not a power of 2), it will take WIDTH+1 clock cycles.
- Once the computation is complete, the **valid** signal is asserted high to indicate that the **quotient** and **remainder** outputs are stable and valid.
- The **divisor_valid_result** signal ensures that valid results are only produced when the divisor is nonzero.
### **Inputs:**
- `clk` (1-bit): Clock signal, toggles every 5 time units (**100MHz operation**).
- `rst` (1-bit): **Active-low** reset signal to initialize the module.
- `start` (1-bit): Start signal to begin the division process.
- `dividend` (6-bit): Dividend input value.
- `divisor` (6-bit): Divisor input value.
### **Outputs:**
- `quotient` (6-bit): Computed quotient output.
- `remainder` (6-bit): Computed remainder output.
- `valid` (1-bit): Signal indicating division completion.
- `divisor_valid_result` (1-bit): Signal indicating if divisor was valid (not zero).
---
## **Testbench Requirements**
### **Instantiation**
- The **restoring_division** module should be instantiated as **uut** (Unit Under Test), with all input and output signals connected.
### **Input Generation and Validation**
- **Randomized Inputs**: The testbench must generate multiple test cases, covering:
- **Random dividend & random nonzero divisor**
- **Dividend = 0** (Edge case)
- **Divisor = 0** (Edge case, division by zero)
- **Dividend < Divisor** (Ensuring the quotient is 0 and remainder = dividend)
- **Stabilization Period**: After applying inputs, the testbench must wait until the **valid** signal is asserted before checking outputs.
### **Control Signal Behavior**
- The **start** signal should be asserted high for **one clock cycle** before being de-asserted.
- The testbench must ensure that **valid** is asserted only after the computation is complete.
---
This testbench will verify the **correctness, stability, and edge-case behavior** of the **restoring_division** module. It ensures that the division process adheres to the restoring division algorithm and produces accurate results across all test scenarios. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start s... | [] |
cvdp_copilot_microcode_sequencer_0028 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_microcode_sequencer`.The testbench must instantiate the `microcode_sequencer` RTL module and provide input stimulus for it, apply various input combinations representing different instructions and conditions such as resetting, fetching instructions, loading data, pushing/popping from the stack, jumping, conditional holds, and program suspensions and edge cases with invalid instructions and test conditional failures rather than building a full testbench.
The module interface is given below :
## **Module Interface** :
### Inputs:
- `clk`(1-bit): The positive edge-triggered clock signal required for the sequential components.
- `c_n_in`(1-bit): Carry-in signal for the ripple carry adder.
- `c_inc_in`(1-bit): Carry-in for the program counter incrementer.
- `r_en`(1-bit): ACTIVE LOW auxiliary register enable signal.
- `cc`(1-bit): ACTIVE LOW condition code input for instruction decoding.
- `ien`(1-bit): ACTIVE LOW instruction enable signal.
- `d_in`(4-bit , [3:0]): A 4-bit data input bus.
- `instr_in`(5-bit, [4:0]): A 5-bit opcode representing the instruction.
- `oen`(1-bit): ACTIVE LOW output enable for the data output path.
### Outputs:
- `d_out`(4-bit,[3:0]): A 4-bit address output bus.
- `c_n_out`(1-bit): Carry-out signal from the ripple carry adder. LOGIC HIGH in this signal indicates the presence of carry.
- `c_inc_out`(1-bit): Carry-out signal from the program counter incremented. LOGIC HIGH in this signal indicates the presence of carry.
- `full`(1-bit): ACTIVE HIGH signal indicates if the Last In First Out (LIFO) stack is full.
- `empty`(1-bit): ACTIVE HIGH signal indicates if the LIFO stack is empty.
- `g_n_out`: Group generate signal from the arithmetic unit.
- `p_n_out`: Group propagate signal from the arithmetic unit.
- `g_inc_out`: Group generate signal from the program counter incrementer.
- `p_inc_out`: Group propagate signal from the program counter incrementer.
## Instantiation :
The testbench instantiates the `microcode_sequencer` module as **uut** and connects the signals between the module and the testbench. Each input and output from the **uut** is connected to its corresponding signal in the testbench.
## Input Generation and Validation:
**Stimulus**:
Several test cases are applied to simulate various operations of the microcode_sequencer. These test cases cover a wide range of scenarios such as different types of instructions (reset, fetch, load, push, pop, jump, etc.), as well as conditional and unconditional instruction executions. For each test case, the relevant outputs (`d_out`, `c_n_out`, `c_inc_out`, `full`, `empty`, `g_n_out`, `p_n_out`, `g_inc_out`, `p_inc_out`) are monitored immediately after the application of inputs to validate the functionality.
**Test Case 1: Instruction Disable** :
- Description: This test case disables the instruction input (`5'bxxxxx`). With no valid instruction provided, the microcode sequencer should remain idle and output default values, reflecting no operation being performed. The outputs should show that the sequencer is in a non-operational state with the `uut.pc_out_w` value remaining at 0000.
**Test Case 2: Reset Instruction** :
- The test applies a reset instruction (`5'b00000`), which should clear all registers and reset the state of the sequencer. The outputs should reflect the sequencer being reset, with `d_out`, `c_n_out`, `c_inc_out`, and `uut.pc_out_w` values showing their initial conditions (`0000` for `d_out`, `0000` for `uut.pc_out_w`, and `full` set to `0`, `empty` set to `1`).
**Test Case 3: Fetch PC Instruction** :
- This test case applies a fetch PC instruction (`5'b00001`), where the program counter (PC) is fetched. The sequencer should output the program counter incremented by 1. In this case, the expected output for uut.pc_out_w is `0001`, with `d_out` reflecting the fetched value.
**Test Case 4: Fetch R Instruction** :
- The sequencer applies a fetch R instruction (`5'b00010`), which fetches the value from register R. The expected outcome is that the value in `d_out` should be the value of register R (`101` in this case) with `uut.pc_out_w` incrementing accordingly (`0010`).
**Test Case 5: Fetch D Instruction** :
- This test case applies a fetch D instruction (`5'b00011`). The sequencer fetches the value from the D input(`d_in`), with `d_out` reflecting the value of D (`110`) and `uut.pc_out_w` incrementing as expected (`0011`).
**Test Case 6: Fetch R + D Instruction** :
- A fetch R + D instruction (`5'b00100`) is applied, where the sequencer fetches and combines data from both the auxiliary register and `d_in`. The expected result is `d_out` showing the combined data (111), and `uut.pc_out_w` reflecting the expected increment (`0100`).
**Test Case 7: Fetch PC + D Instruction** :
- This test case applies a fetch PC + D instruction (`5'b00101`), which combines the values of the program counter (PC) and the `d_in`. The d_out value should reflect the combination (`1100`), and `uut.pc_out` should increment to `0101`.
**Test Case 8: Fetch PC + R Instruction** :
- The test applies a fetch PC + R instruction (`5'b00110`), where the sequencer fetches both the program counter (PC) and the Auxiliary register. The expected output for `d_out` should be a combination of the content of the PC and auxiliary register (`1101`), and `pc_out `increments accordingly to `0110`.
**Test Case 9: Fetch PC to R Instruction** :
- A fetch PC to R instruction (`5'b01000`) is applied, where the program counter (`PC`) is transferred to the auxiliary register. The expected output should show `d_out` reflecting the PC value (`111`), and `pc_out` incrementing as expected (`0111`).
**Test Case 10: Fetch R+D to R Instruction** :
- This case applies a fetch R + D to R instruction (`5'b01001`), where the data from both the auxiliary register and `d_in` are fetched, added, and transferred to the auxiliary register. The expected output should reflect this combination (`11` for `d_out`), and the program counter should increment (`1000` for `uut.pc_out_w`).
**Test Case 11: Load R Instruction** :
- A load R instruction (`5'b01010`) is applied, where data from an`d_in` is loaded into the auxiliary register. The output should reflect the `uut.pc_out_w` value (`1001` for `d_out`), and the program counter (`uut.pc_out_w`) should be incremented accordingly (`1001`).
**Test Case 12: Push PC Instruction** :
- A push PC instruction (`5'b01011`) is tested, where the program counter (`PC`) is pushed onto the stack. The output shows the updated stack (`d_out` as `1010`) and empty flag reflecting the stack status (`0`).
**Test Case 13: Pop PC Instruction** :
- A pop PC instruction (`5'b01110`) is applied, where the program counter (PC) is popped from the stack. The expected output shows the popped value (`1011`) in d_out and the updated program counter (`uut.pc_out_w` as `1101`).
**Test Case 14: Push D Instruction** :
- A push D instruction (`5'b01100`) is tested, where data from the `d_in` is pushed onto the stack. The expected output is that `d_out` reflects the pushed value and 1uut.pc_out_w1 should increment appropriately.
**Test Case 15: Pop Stack Instruction** :
- A pop stack instruction (`5'b01101`) tests the sequencer's ability to pop data from the stack. The expected outputs should show the data being popped correctly (`d_out` reflects the popped value) and the stack's status with empty being checked.
**Test Case 16: HOLD** :
- A hold instruction (`5'b01111`) is applied to check that the sequencer halts its operation. The expected behavior is that the sequencer should not move to the next instruction and `uut.pc_out_w` stays in the current state.
**Test Case 17: Fail Conditional Instruction** :
- This test applies an invalid instruction (`5'b1xxxx`) with conditional failure (`cc` = `1`). The sequencer should fail to process the instruction and output appropriate values (`d_out` reflecting updated `uut.pc_out_w` value).
**Test Case 18: Jump R Instruction** :
- A jump R instruction (`5'b10000`) is applied, where the sequencer performs a jump using the auxiliary register value. The expected output shows a jump action with `d_out` reflecting the jump address.
**Test Case 19: Jump D Instruction** :
- A jump D instruction (`5'b10001`) tests the sequencer’s ability to jump based on the `d_in` value. The expected outcome is that `d_out` reflects the jump address based on the value of `d_in`.
**Test Case 20: Jump 0 Instruction** :
- A jump 0 instruction (`5'b10010`) applies a jump to address `0`. The output should reflect this jump, with `uut.pc_out_w` updated to `0000`.
**Test Case 21: Jump R+D Instruction** :
- A jump R+D instruction (`5'b10011`) applies a jump based on the sum of the auxiliary register and `d_in`. The expected output should reflect the sum.
**Test Case 22: Jump PC+D Instruction** :
- A jump PC+D instruction (`5'b10100`) applies a jump based on the sum of PC and `d_in`. The expected behavior is that `d_out `reflects the result of PC and `d_in` combined.
**Test Case 23: Jump PC+R Instruction** :
- A jump PC+R instruction (`5'b10101`) applies a jump based on the sum of PC and auxiliary register. The expected output should reflect this combination in `d_out`.
**Test Case 24: JSB R Instruction** :
- A JSB R instruction (`5'b10110`) applies a jump to a subroutine based on the auxiliary register. The output should show the subroutine jump address in `d_out`.
**Test Case 25: JSB D Instruction** :
- A JSB D instruction (`5'b10111`) applies a jump to the subroutine address based on the `d_in`. The sequencer should handle the jump correctly by appropriately updating `d_out`.
**Test Case 26: JSB 0 Instruction** :
- A JSB 0 instruction (`5'b11000`) applies a jump to a subroutine at address 0. The expected output should reflect the jump to address 0.
**Test Case 27: JSB R+D Instruction** :
- A JSB R+D instruction (5'b11001) applies a jump to the subroutine address based on the sum of the auxiliary register and `d_in`. The sequencer should perform the jump correctly.
**Test Case 28: JSB PC+D Instruction** :
- A JSB PC+D instruction (`5'b11010`) applies a jump to the subroutine address based on the sum of PC and `d_in`. The expected outcome should reflect the subroutine jump at `d_out`.
**Test Case 29: Fetch S+D Instruction** :
- This test applies a fetch S+D instruction (`5'b00111`), where the sequencer fetches and adds values of popped stack value (S) with `d_in`. The expected output should reflect the appropriate address at `d_out`.
**Test Case 30: Return S Instruction** :
- The return S instruction (`5'b11100`) tests the sequencer’s ability to return from a subroutine. The expected outcome should show the return address at `d_out`.
**Test Case 31: Return S+D Instruction** :
- The return S+D instruction (`5'b11101`) checks the sequencer’s ability to return from a subroutine with the sum of popped value from the stack and `d_in`. The expected output should be reflected at `d_out`.
**Test Case 32: Conditional Hold** :
- The conditional hold instruction (`5'b11110`) tests the sequencer’s ability to hold execution based on a condition. The expected outcome should show that the sequencer halts.
**Test Case 33: Program Suspend** :
- The program suspend instruction (`5'b11111`) checks the sequencer’s ability to suspend its program flow. The expected behavior is that the sequencer stops and no further instructions are executed.
## Module Functionality :
**Microcode Sequencer Module (microcode_sequencer)** :
Purpose: This module controls the operation of a microprocessor by sequencing operations based on the instructions it receives. It interacts with other modules (like stack, program counter, arithmetic operations, and instruction decoder) to control the flow of data.
It contains the following components :
**LIFO Stack Module (lifo_stack)** :
**Purpose**: Implements a stack with push and pop functionality, allowing data to be stored and retrieved in a last-in-first-out
order.
**Components**:
- **Stack Pointer**: Tracks the current position in the stack and controls whether the stack is full or empty.
- **Stack RAM**: Stores the actual stack data.
- **Stack Data Mux**: Selects which data (either from the program counter or data input) should be pushed onto the stack.
**Program Counter Module (program_counter)** :
**Purpose**: Handles the program counter (PC), which keeps track of the next instruction to execute. It can increment
based on different conditions.
**Components**:
- **PC Mux**: Selects the input for the program counter (either from the adder or program counter).
- **PC Incrementer**: Performs the actual increment of the program counter based on carry and increment signals.
- **PC Register**: Stores the current value of the program counter.
**Instruction Decoder (instruction_decoder)** :
**Purpose**: Decodes the incoming instruction (instr_in) and generates control signals for various operations like
increment, push, pop, stack operations, etc.
**Microcode Arithmetic Module (microcode_arithmetic)**
**Purpose**: Performs arithmetic operations like addition using a carry lookahead adder. It uses data from various inputs
(program counter, stack, data input) and processes it based on the instruction.
**Components**:
**Auxiliary Register**: Stores data that can be modified based on the control signals (rsel, rce).
**MUXes**: Control the selection of data from different sources (registers, stack, program counter) to be used in arithmetic
operations.
**Full Adder**: Performs the actual arithmetic operations and generates the result, carry, group, generate, and propagate
signals. It is implemented using 4-bit carry-lookahead logic.
**Partial Test Stimulus Generator Code** :
```verilog
module tb_microcode_sequencer;
// Inputs to the DUT
logic clk;
logic c_n_in;
logic c_inc_in;
logic r_en;
logic cc;
logic ien;
logic [3:0] d_in;
logic [4:0] instr_in;
logic oen;
// Outputs from the DUT
logic [3:0] d_out;
logic c_n_out;
logic c_inc_out;
logic full;
logic empty;
logic g_n_out;
logic p_n_out;
logic g_inc_out;
logic p_inc_out;
microcode_sequencer uut (
.clk(clk),
.c_n_in(c_n_in),
.c_inc_in(c_inc_in),
.r_en(r_en),
.cc(cc),
.ien(ien),
.d_in(d_in),
.instr_in(instr_in),
.oen(oen),
.d_out(d_out),
.c_n_out(c_n_out),
.c_inc_out(c_inc_out),
.full(full),
.empty(empty),
.g_n_out(g_n_out),
.p_n_out(p_n_out),
.g_inc_out(g_inc_out),
.p_inc_out(p_inc_out)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Task to test specific cases
task run_test_case(
input logic [4:0] test_instr, // Instruction input
input logic test_carry_in, // Carry input
input logic test_carry_inc, // Carry increment input
input logic test_reg_en, // Register enable
input logic test_cond_code, // Condition code
input logic test_instr_en, // Instruction enable
input logic [3:0] test_data_in, // Data input
input logic test_output_en, // Output enable
input string case_name // Name of the test case
);
begin
// Apply inputs
instr_in = test_instr;
c_n_in = test_carry_in;
c_inc_in = test_carry_inc;
r_en = test_reg_en;
cc = test_cond_code;
ien = test_instr_en;
d_in = test_data_in;
oen = test_output_en;
#20;
$display("Running test case: %s", case_name);
$display("time = %0t , Inputs: instr_in = %0b, c_n_in = %b, c_inc_in = %b, r_en = %b, cc = %b, ien = %b, d_in = %0b, oen = %b",
$time,test_instr, test_carry_in, test_carry_inc, test_reg_en, test_cond_code, test_instr_en, test_data_in, test_output_en);
$display("time = %0t , d_out = %0b, c_n_out = %b, c_inc_out = %b, full = %b, empty = %b, g_n_out = %b, p_n_out = %b, g_inc_out = %b, p_inc_out = %b , pc_out = %b",
$time,d_out, c_n_out, c_inc_out, full, empty, g_n_out, p_n_out, g_inc_out, p_inc_out,uut.pc_data_w);
end
endtask
initial begin
$dumpfile("microcode_sequencer.vcd");
$dumpvars(0, tb_microcode_sequencer);
$display("Starting testbench for microcode_sequencer...");
run_test_case(5'bxxxxx, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 4'bxxxx, 1'b0, "Instruction Disable");
run_test_case(5'b00000, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 4'bxxxx, 1'b0, "Reset Instruction");
run_test_case(5'b00001, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'bxxxx, 1'b0, "Fetch PC Instruction");
run_test_case(5'b00010, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0101, 1'b0, "Fetch R Instruction");
run_test_case(5'b00010, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0110, 1'b0, "Fetch R Instruction");
run_test_case(5'b00011, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0110, 1'b0, "Fetch D Instruction");
run_test_case(5'b00011, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 4'b0110, 1'b0, "Fetch D Instruction");
run_test_case(5'b00011, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0111, 1'b0, "Fetch D Instruction");
// Insert the code for remaining test cases here
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | microcode_sequencer | uut | [
{
"name": "microcode_sequencer.sv",
"content": "module microcode_sequencer (\n // Inputs\n input logic clk, // Input Clock\n input logic c_n_in, // Input Carry for Carry Lookahead Adder\n input logic c_inc_in, // Input Carry for Carry Lookahead Program Counter Incrementer\n input logic r_en, // A... | [] |
cvdp_agentic_async_fifo_compute_ram_application_0004 | medium | Agentic | Create a test bench in SystemVerilog for a Verilog module named `async_fifo`. The **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory and Gray-coded pointers for reliable synchronization. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
# Stimulus Generation
Below are all test cases designed to maximize coverage of the `async_fifo` module.
**Setup:**
- `p_data_width = 8`
- `p_addr_width = 4`
- Write clk = 10 ns, Read clk = 12 ns
---
## Test Case 1: Basic Write-Read
**Description:**
Write a sequence of data and read it back with asynchronous clocks.
**Sequence:**
1. Deassert resets.
2. Write 8 sequential values.
3. Read back all values.
---
## Test Case 2: Fill-and-Drain (Full/Empty Flag Test)
**Description:**
Completely fill and then completely drain the FIFO.
**Sequence:**
1. Write 16 items to FIFO.
2. Observe `o_fifo_full = 1`.
3. Read all data.
4. Observe `o_fifo_empty = 1`.
---
## Test Case 3: Pointer Wrap-Around
**Description:**
Test pointer wrap-around logic at FIFO depth boundaries.
**Sequence:**
1. Continuously write 20 items.
2. Slowly read back data.
---
## Test Case 4: Write Domain Reset
**Description:**
Test behavior when only the write side is reset.
**Sequence:**
1. Write till Fifo is full.
2. Reset `i_wr_rst_n`.
3. Read Back.
---
## Test Case 5: Read Domain Reset
**Description:**
Test behavior when only the read side is reset.
**Sequence:**
1. Continuously write data.
2. Reset `i_rd_rst_n`.
3. Read Back.
---
## Test Case 6: Simultaneous Reset
**Description:**
Reset both domains simultaneously.
**Sequence:**
1. Write and read some data.
2. Assert both resets.
3. Resume operation.
--- | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Assertion",
"target_percentage": 100
},
{
"inst_name": "dut",
"metric": "Toggle",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Block",... | async_fifo | dut | [
{
"name": "async_fifo.sv",
"content": "module async_fifo\n #(\n parameter p_data_width = 32, // Parameter to define the width of the data\n parameter p_addr_width = 16 // Parameter to define the width of the address\n )(\n input wire i_wr_clk, // Write ... | [
{
"name": "fifo.md",
"content": "# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory... |
cvdp_copilot_gaussian_rounding_div_0014 | easy | Non-Agentic | Write a testbench to only generate stimulus for a `divider` that performs non-restoring division for two unsigned positive integer inputs, and generates the output `quotient`, `remainder` and `valid` when computation is completed for the inputs `dividend` and `divisor` when `start` is asserted. In this design, the outputs are generated after WIDTH + 2 clock cycles and the output is considered valid when `valid` is asserted.
The non-restoring division is a division technique for unsigned binary values that simplifies the procedure by eliminating the restoring phase.
## Design Details
### Parameters
- **`WIDTH`**
- *Default*: 32
- *Constraint*: Must be greater than 1
- *Description*: Bit-width of the `dividend` and `divisor`, and thus of the `quotient` and `remainder`.
---
### Port List
| **Port Name** | **Direction** | **Width** | **Description and Constraints** |
|----------------|---------------|-----------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| **`clk`** | input | 1 bit | Main clock input. All operations occur on the rising edge of this signal. |
| **`rst_n`** | input | 1 bit | Active-low asynchronous reset. When asserted (0), resets the internal state machine, outputs and registers to their initial states. |
| **`start`** | input | 1 bit | When asserted high, it indicates that valid inputs (`dividend` and `divisor`) are available and a new division operation should begin on the next rising clock edge. |
| **`dividend`** | input | `WIDTH` bits | Dividend (the numerator) for the division operation. Must be greater than or equal to 0 and Less than 2<sup>(WIDTH)</sup>-1 |
| **`divisor`** | input | `WIDTH` bits | Divisor (the denominator) for the division operation. Must be greater than 0 and Less than 2<sup>(WIDTH-1)</sup>-1. |
| **`quotient`** | output | `WIDTH` bits | The integer division result, valid once the module completes the division and `valid` is asserted. The output value is held till the computation of the next set of inputs is completed. |
| **`remainder`**| output | `WIDTH` bits | The remainder from the division, valid once the module completes the division and `valid` is asserted. The output value is held till the computation of the next set of inputs is completed.|
| **`valid`** | output | 1 bit | Asserted high when the output (`quotient` and `remainder`) is valid. Remains asserted after the calculation is completed till the `start` input is driven low. |
---
## The design follows the following Finite-State Machine (FSM) for division
1. **IDLE**
- **Default/Reset state**.
- Waits for `start` to be asserted.
- On `start`, loads the `dividend` and `divisor` into internal registers, resets the `quotient` and `remainder` registers, and transitions to **BUSY**.
2. **BUSY**
- Performs the **non-restoring** algorithm for `WIDTH` clock cycles.
3. **DONE**
- Asserts `valid` to indicate outputs are ready.
- Stays in **DONE** until `start` is de-asserted, then returns to **IDLE**.
---
### Latency Considerations of the DUT
Total Latency = WIDTH + 2 cycles
### Notes:
- Division by 0 is not handled in this design
- When `start` signal is is asserted, the design latches the input `dividend` and `divisor` at the next clock edge.
- Inputs `dividend` and `divisor` will remain stable until the calculation is complete.
## Testbench requirements:
### Instantiation
- Module Instance: The `divider` module is instantiated as `dut`, with the input and output signals connected for testing.
---
### Input Generation
- Input Generation: The testbench must generate inputs of WIDTH-bit binary values for `dividend` and `divisor` and 1-bit `start` to cover all possibilities, including the corner cases.
- Computation Period: After setting each pair of inputs, the testbench waits till assertion of `valid` to ensure the outputs have stabilized, before asserting new values. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | divider | dut | [
{
"name": "divider.sv",
"content": "`timescale 1ns/1ps\nmodule divider #\n(\n parameter WIDTH = 32\n)\n(\n input wire clk,\n input wire rst_n, // Active-low asynchronous reset\n input wire start, // Start signal for new operation\n ... | [] |
cvdp_copilot_prim_max_0005 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `prim_max_find` module. This module implements a **binary tree-based maximum value finder** that determines the highest value from multiple input sources and provides the corresponding index. The testbench must apply a range of test cases to validate correct maximum value selection, index resolution, and handling of various input conditions.
---
### **Inputs:**
- `clk_i`: **Clock signal with a 10ns period.**
- `rst_ni`: **Active-low reset signal.**
- `values_i`: **Flattened `NumSrc * Width`-bit wide input containing all values.**
- `valid_i`: **`NumSrc`-bit wide signal indicating which inputs are valid.**
### **Outputs:**
- `max_value_o`: **`Width`-bit output representing the maximum value among valid inputs.**
- `max_idx_o`: **`SrcWidth`-bit output indicating the index of the maximum value.**
- `max_valid_o`: **Indicates whether any valid inputs were provided.**
---
### **Instantiation**
The testbench must instantiate a single instance of the `prim_max_find` module:
- **Maximum Finder Module (`dut`)**: Instantiated with `NumSrc=8` and `Width=8` to test typical input conditions.
---
### **Testbench Requirements**
The testbench must apply a **wide range of test patterns** to ensure correct operation under all input conditions:
1. **Clock Generation:**
- `clk_i` must toggle every **5 time units**, ensuring a **10 ns clock period**.
2. **Reset Handling:**
- `rst_ni` must be **asserted for multiple cycles** before deasserting.
- The module must correctly initialize outputs when `rst_ni` is released.
3. **Stimulus Generation Strategy:**
- The testbench **must not verify outputs** (only generate inputs).
- The following test sequences must be executed:
- **All Invalid Inputs**: Assign `valid_i = 0` for all inputs.
- **Single Valid Input**: One valid source with all others invalid.
- **Multiple Valid Inputs (Distinct Values)**: Various active sources with different values.
- **Multiple Valid Inputs (Duplicate Maximums)**: Multiple sources with the same highest value.
- **Maximum Value at First and Last Index**: Ensures correct tie-breaking at input boundaries.
- **Sequentially Increasing and Decreasing Values**: Tests proper priority handling.
- **Alternating Valid Input Patterns**: Exercises irregular valid signal transitions.
- **Extended Randomized Testing**: Generates **20 iterations** of randomized valid inputs and values.
4. **Handling Continuous and Edge Cases:**
- The testbench must ensure **robust performance** under all valid/invalid input conditions.
- **Pipeline behavior** must be properly exercised through random valid signal transitions.
- **Valid input bursts and sporadic input toggling** must be tested.
5. **Waveform Generation:**
- The testbench must generate a `.vcd` waveform file to allow waveform analysis.
---
### **Coverage and Compliance**
- The testbench must ensure **high coverage** across all possible input combinations.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
---
### **Test Plan Overview**
The testbench must ensure **96%+ input stimulus coverage** by applying:
- **Valid data selection** across different test cases.
- **Edge case handling** for minimum, maximum, and undefined values.
- **Randomized input variations** to ensure robustness.
- **Pipeline behavior verification** to confirm proper propagation of results.
- **Handling of multiple maximum values** to ensure correct index selection.
This testbench will provide a **comprehensive input stimulus environment** for `prim_max_find`, ensuring correct operation under various test conditions.
---
### **Note:**
- The testbench **must only generate stimulus** without verifying outputs.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
- **Ensure the maximum possible input coverage** without adding assertions or comparisons.
Can you implement a **SystemVerilog testbench** with the above stimulus requirements? | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | prim_max_find | dut | [
{
"name": "prim_max_find.sv",
"content": "module prim_max_find #(\n parameter int NumSrc = 8,\n parameter int Width = 8,\n // Derived parameters\n localparam int SrcWidth = $clog2(NumSrc),\n localparam int NumLevels = $clog2(NumSrc),\n localparam int NumNodes = 2**(NumLevels+1)-1\n) (\n input ... | [] |
cvdp_copilot_manchester_enc_0009 | easy | Non-Agentic | Complete the given SystemVerilog testbench for the `top_manchester` module. The testbench currently instantiates the UUT and should include stimulus generation logic that dynamically produces a wide range of test scenarios to ensure 100% functional and code coverage. The stimulus generation logic should drive the design under various conditions, including the module functionality below.
---
## Description
### Parameter
- **`N`**: Input Parameter Value, Default value is 8.
### Inputs
- **`clk_in`**: Clock signal driving the design (positive edge triggered).
- **`rst_in`**: Asynchronous reset signal (active high) to reset the encoder and decoder.
- **`enc_valid_in`**: 1-bit Input valid signal for the encoder.
- **`enc_data_in[N-1:0]`**: N-bit input data for the encoder.
- **`dec_valid_in`**: 1-bit Input valid signal for the decoder.
- **`dec_data_in[2*N-1:0]`**: 2N-bit input data for the decoder.
### Outputs
- **`enc_valid_out`**: 1-bit Output valid signal for the encoder.
- **`enc_data_out[2*N-1:0]`**: 2N-bit Manchester-encoded output data from the encoder.
- **`dec_valid_out`**: 1-bit Output valid signal for the decoder.
- **`dec_data_out[N-1:0]`**: N-bit decoded output data from the decoder.
---
## Input Generation
### Input Generation
- **Clock and Reset**:
- Generate a clock signal (`clk_in`) with a configurable period.
- Apply reset (`rst_in`) at the beginning and during random intervals to test reset behavior.
- **Encoder Inputs**:
- Generate diverse patterns for `enc_data_in`, such as:
- Incremental data (e.g., 0, 1, 2, ...).
- Random data patterns.
- Edge cases (e.g., all zeros, all ones, alternating patterns).
- Toggle `enc_valid_in` to test valid and invalid input scenarios.
- **Decoder Inputs**:
- Generate diverse patterns for `dec_data_in`, such as:
- Valid Manchester-encoded data (e.g., 0x5AA5, 0xC33C).
- Invalid Manchester-encoded data (e.g., 0xFFFF, 0x0000).
- Incremental data (e.g., 0, 1, 2, ...).
- Random data patterns.
- Toggle `dec_valid_in` to test valid and invalid input scenarios.
## **Instantiation**
- The instance of the RTL should be named **`uut`**.
---
Follows the specification for building the RTL of the module, use it as a reference for the verification environment too:
## Module Functionality
1. **Encoder Functionality**:
- The encoder converts N-bit input data (`enc_data_in`) into 2N-bit Manchester-encoded data (`enc_data_out`).
- The encoding logic follows the Manchester encoding scheme:
- `1` is encoded as `01`.
- `0` is encoded as `10`.
2. **Decoder Functionality**:
- The decoder converts 2N-bit Manchester-encoded data (`dec_data_in`) into N-bit decoded data (`dec_data_out`).
- The decoding logic follows the Manchester decoding scheme:
- `01` is decoded as `1`.
- `10` is decoded as `0`.
- Invalid patterns (e.g., `00` or `11`) are decoded as `0`.
3. **Reset Behavior**:
- When `rst_in` is asserted, all outputs (`enc_data_out`, `enc_valid_out`, `dec_data_out`, `dec_valid_out`) are cleared to zero.
---
```verilog
module tb_top_manchester;
parameter N = 8; // Width of input and output data
parameter CLK_PERIOD = 10; // Clock period in ns
// Testbench signals
logic clk_in;
logic rst_in;
logic enc_valid_in;
logic [N-1:0] enc_data_in;
logic dec_valid_out;
logic dec_valid_in;
logic [N-1:0] dec_data_out;
logic [2*N-1:0] enc_data_out; // 2N-bit Manchester encoded data
logic [2*N-1:0] dec_data_in; // 2N-bit Manchester encoded data
logic enc_valid_out; // Encoded data valid signal
// Instantiate the top module
top_manchester #(
.N(N)
) uut (
.clk_in(clk_in),
.rst_in(rst_in),
.enc_valid_in(enc_valid_in),
.enc_data_in(enc_data_in),
.enc_valid_out(enc_valid_out),
.enc_data_out(enc_data_out),
.dec_valid_in(dec_valid_in),
.dec_data_in(dec_data_in),
.dec_valid_out(dec_valid_out),
.dec_data_out(dec_data_out)
);
// Insert the code here to generate stimulus generation logic
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | top_manchester | uut | [
{
"name": "top_manchester.sv",
"content": "module top_manchester #(\n parameter N = 8 // Default width of input and output data\n) (\n input logic clk_in, // Clock input\n input logic rst_in, // Active high reset input\n \n // Encoder Signals\n inpu... | [] |
cvdp_agentic_nbit_swizzling_0005 | easy | Agentic | I have a specification of a `nbit_swizzling` module in the `docs` directory. Write a system verilog testbench `nbit_swizzling_tb.sv` in the verif directory to only generate stimulus and achieve maximum coverage for the `nbit_swizzling` module.
Include the following in the generated testbench:
1. **Module instance:**
- Instantiate the `nbit_swizzling` module as `dut`.
- Connect all input and output signals for testing, as described in the specification.
2. **Input generation:**
- Generate the inputs `data_in` in the range of 0 to 2<sup>`DATA_WIDTH`</sup>-1 and `sel` in the range of 0 to 3.
3. **Additional Requirements:**
- Use the Parameter `DATA_WIDTH` = 16 to generate input stimulus.
- Test edge cases such as:
- Random data inputs.
- unknown value of input sel. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | nbit_swizzling | dut | [
{
"name": "nbit_swizzling.sv",
"content": "`timescale 1ns/1ps\nmodule nbit_swizzling #(parameter DATA_WIDTH = 64)(\n input [DATA_WIDTH-1:0] data_in, // Input data of size DATA_WIDTH \n input [1:0] sel, \t // 2-b... | [
{
"name": "nbit_swizzling_spec.md",
"content": "The `nbit_swizzling` module performs bit rearrangement **(swizzling)** and **Gray code** conversion on an input data bus of variable width. The module offers four swizzling patterns controlled by a **2-bit selection signal**. After the swizzling operation, an ... |
cvdp_copilot_gf_multiplier_0047 | medium | Non-Agentic | Create a testbench to generate stimuli for the `gf_mac` module, which computes a byte-wide Galois Field (2<sup>8</sup>) multiply-accumulate function over two `WIDTH`-bit inputs (`a` and `b`). The module also supports a passthrough mode and provides status signals for validity, readiness, and error indication.
---
## Description
The `gf_mac` module processes two input values by breaking them into 8-bit segments and multiplies each corresponding segment in GF(2<sup>8</sup>). The partial products are then XORed together to form an 8-bit accumulation result (`result`). A passthrough mode is included, allowing direct output of `a[7:0]` instead of the GF multiply-accumulate result. The module provides the `valid_result` and `ready` signals to indicate when the output can be sampled, and sets `error_flag` if the specified `WIDTH` is not a multiple of 8.
---
## Inputs
### **1. Parameters**
- **`WIDTH`**
- **Type**: Integer parameter
- **Default / Typical**: 32
- **Purpose**: Defines the bit width of inputs `a` and `b`. Must be a multiple of 8 for proper GF(2<sup>8</sup>) segmentation.
- **Impact**: If `WIDTH` is not divisible by 8, the module asserts `error_flag` and forces the result output to `8'b0`.
### **2. Registers / Signals for Stimulus**
- **`reset`**
- **Bit Width**: 1
- **Purpose**: Asynchronous reset signal. When asserted, internal registers and outputs are forced to their default state.
- **Usage**: Drives the module to initialize or clear state before applying new inputs.
- **`enable`**
- **Bit Width**: 1
- **Purpose**: Activation signal to start the multiply-accumulate process. When low, the outputs remain at default values.
- **Usage**: Driven high for normal operation or low to hold outputs in an inactive state.
- **`pass_through`**
- **Bit Width**: 1
- **Purpose**: Mode selector. When set, the module outputs `a[7:0]` directly, bypassing the GF multiply-accumulate logic.
- **Usage**: Driven high or low to test both normal GF MAC operation and pass-through behavior.
- **`a [WIDTH-1:0]`**
- **Bit Width**: `WIDTH` (e.g., 32 bits by default)
- **Purpose**: First input operand for the GF MAC calculation or direct source (when `pass_through` is set).
- **Usage**: Driven with a variety of patterns (random, edge, corner cases) to exercise the internal GF segments.
- **`b [WIDTH-1:0]`**
- **Bit Width**: `WIDTH` (e.g., 32 bits by default)
- **Purpose**: Second input operand for the GF MAC calculation, partitioned into 8-bit segments for multiplication.
- **Usage**: Driven alongside `a` to cover different multiply-accumulate scenarios in GF(2<sup>8</sup>).
---
## Outputs
- **`result [7:0]`**
- **Bit Width**: 8
- **Purpose**: Final 8-bit accumulation of GF(2<sup>8</sup>) partial products or direct pass-through from `a[7:0]` when `pass_through` is set.
- **Usage**: Observed after applying stimulus to determine the outcome of the GF MAC or pass-through operation.
- **`valid_result`**
- **Bit Width**: 1
- **Purpose**: Indicates that `result` is valid when `enable` is asserted and `WIDTH` is a multiple of 8.
- **Usage**: Sampled to confirm that the output is ready and valid in the current cycle.
- **`ready`**
- **Bit Width**: 1
- **Purpose**: Mirrors `valid_result` in this design. Signals the environment that the module has produced the final output.
- **Usage**: Observed to coordinate data flow, especially if additional handshake logic is applied.
- **`error_flag`**
- **Bit Width**: 1
- **Purpose**: Asserts high when `WIDTH` is not divisible by 8. Remains low if `WIDTH` is valid.
- **Usage**: Checked to detect or log configuration errors or unsupported widths during stimulus application.
---
## Instantiation
A single instance of the `gf_mac` module can be created, supplying `reset`, `enable`, `pass_through`, `a`, and `b` as stimulus inputs and capturing `result`, `valid_result`, `ready`, and `error_flag` as outputs. The parameter `WIDTH` can be set to 32 or other multiples of 8 to explore different valid configurations, or to a non-multiple of 8 to observe the `error_flag` behavior.
---
## Input Generation and Observations
1. **Deterministic Stimuli**
- **Zero Inputs**: Apply `a=0`, `b=0` with `enable=1`, checking if the module outputs `0x00`.
- **Simple Patterns**: Use known 8-bit segments repeated across `a` and `b` (e.g., `0x00000001`, `0xFFFFFFFF`) to observe repeated partial multiplications.
- **Pass-Through Mode**: Set `pass_through=1` and apply different values to `a` to confirm that `result` matches `a[7:0]`.
2. **Toggle Reset**
- Assert `reset` for a period before releasing it, ensuring the module clears its outputs to default and deasserts `error_flag` unless `WIDTH` is invalid.
3. **Valid and Invalid `WIDTH` Tests**
- Use a `WIDTH` multiple of 8 (e.g., 32) to keep `error_flag` low and observe proper GF MAC operation.
- Optionally modify `WIDTH` to a non-multiple of 8 in a separate simulation run to observe `error_flag` assertion and forced zero output.
4. **Random Stimuli**
- Generate random patterns for `a` and `b` to stress the partial products across the 8-bit segments.
- Randomly switch `enable` and `pass_through` to exercise state transitions while capturing the resultant behavior.
5. **Timing Intervals**
- Change inputs at defined or random time steps (e.g., 5–10 time units) to capture the module’s combinational output.
- Log and compare results after each stimulus to observe the correlation with input patterns.
---
## Module Interface
### **Inputs**
- **`reset` (1 bit)**: Active-high reset for the internal state.
- **`enable` (1 bit)**: Activates the GF MAC operation when high.
- **`pass_through` (1 bit)**: Selects direct pass of `a[7:0]` vs. GF MAC accumulation.
- **`a [WIDTH-1:0]`**: First operand for the GF(2<sup>8</sup>) accumulate or pass-through data.
- **`b [WIDTH-1:0]`**: Second operand for the GF(2<sup>8</sup>) accumulate.
### **Outputs**
- **`result [7:0]`**: 8-bit GF MAC output or direct pass of `a[7:0]`.
- **`valid_result` (1 bit)**: Indicates a valid `result` when `enable` is high and `WIDTH` is valid.
- **`ready` (1 bit)**: Mirrors the `valid_result` signal.
- **`error_flag` (1 bit)**: High if `WIDTH` is invalid (not multiple of 8), otherwise low.
---
## Module Functionality
- **GF MAC Calculation**
- When `enable` is high and `pass_through` is low, the module slices `a` and `b` into 8-bit segments and multiplies each pair using a GF(2<sup>8</sup>) multiplier. The partial products are XORed to produce `result`.
- **Pass-Through Mode**
- When `pass_through` is high and `enable` is high, the 8-bit portion `a[7:0]` is directly mapped to `result`.
- **Readiness & Validity**
- The signals `valid_result` and `ready` both indicate that the output is finalized and stable under valid conditions (`WIDTH % 8 == 0`).
- **Error Indication**
- The signal `error_flag` is asserted if `WIDTH` is not divisible by 8. In that case, `result` is forced to `8'b0`, and `valid_result` remains low.
---
## Additional Notes
- **GF Multiplier Usage**: Internally, the module instantiates multiple `gf_multiplier` blocks (one per 8-bit segment of `a` and `b`) to compute partial products.
- **Coverage of Corner Cases**: Stimuli can include values with alternating bits, large or small decimal representations, and identical inputs for both `a` and `b` to exercise the reduction logic in the GF multipliers.
- **Scalability**: The parameterizable `WIDTH` allows the environment to explore larger or smaller inputs, provided the requirement (`WIDTH % 8 == 0`) is satisfied. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | gf_mac | uut | [
{
"name": "gf_mac.sv",
"content": "`timescale 1ns/1ps\nmodule gf_mac#(parameter WIDTH=32)(\n input reset,\n input enable,\n input pass_through,\n input [WIDTH-1:0] a,\n input [WIDTH-1:0] b,\n output [7:0] result,\n output valid_result,\n output ready,\n output error_flag\n);\n ... | [] |
cvdp_copilot_encoder_8b10b_0026 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_encoder_8b10b` that instantiates the `encoder_8b10b` module as the Unit Under test (UUT). This testbench module must include the `stimulus generation` logic only, which systematically drives different input conditions to the `encoder_8b10b` module to achieve **100% functional and code coverage**. The `encoder_8b10b` module supports encoding of control and data symbols as given in the below functionality.
---
## **Input Stimulus Generation**
### **Encoder Inputs**
- Generate diverse patterns for `encoder_in`, including:
- Standard **control symbols** (`8'h1C`, `8'h3C`, `8'h5C`, `8'h7C`, etc.).
- Random **valid data symbols** (`8'h00` to `8'hFF`).
- Repeated control symbols.
- Invalid control inputs.
- **Imbalanced** control symbols to check running disparity handling.
- **Continuous data symbols** covering the entire range.
- **Sequential and random data symbols**.
### **Edge Case Testing**
- Drive encoder inputs with:
- **Repeated** control symbol sequences.
- **Back-to-back** transitions between control and data symbols.
- **Random invalid 8-bit values** fed into the encoder.
### **Stabilization Period**
- **Wait 1 clock cycle** after each input change before checking `encoder_out` and `disparity_out` to ensure stable results.
---
## **Instantiation**
- The instance of the **RTL module** should be named **`uut`**.
Following the RTL specification for building the RTL of the module, and using it as a reference for the testbench environment too:
---
## **Module Interface**
### **Inputs**
- `clk_in`: **Rising-edge triggered clock** signal with a 50% duty cycle.
- `reset_in`: **Active-HIGH asynchronous reset**.
- `control_in`: **1-bit input**, HIGH for control symbols, LOW for data symbols.
- `encoder_in[7:0]`: **8-bit input symbol** to be encoded.
- `disparity_data_in`: **1-bit input**, representing the current running disparity.
### **Outputs**
- `encoder_out[9:0]`: **10-bit encoded output**.
- `disparity_out`: **1-bit output**, representing the running disparity after encoding.
---
## **Module Functionality**
An 8b10b encoder is a digital circuit that converts an 8-bit word into a 10-bit encoded codeword, used in telecommunications to maintain Digital Control (DC) balance (equal number of 1s and 0s) and provide error detection capabilities. The encoder is extended to support **data symbols**, which are standard data inputs distinct from control symbols.
1. **Control and Data Symbol Encoding**:
- When `control_in` is HIGH: Encode `encoder_in` as a control character based on predefined control symbols and update the running disparity for control encoding.
- When `control_in` is LOW: Encode `encoder_in` as a data symbol based on the 8b/10b data encoding scheme. Use `disparity_data_in` to run disparity tracking and generate a valid 10-bit encoded data symbol while updating the running disparity.
2. **Latency**:
- Ensure the module introduces a single clock cycle latency for control or data symbol encoding.
3. **Control Encoding Compatibility**:
- Maintain compatibility with existing control symbol encoding implementation.
- Use modular components to handle control and data symbol encoding separately for maintainability.
Below are the 5b/6b and 3b/4b encoding tables used for encoding data symbols in the design.
### **5b/6b Encoding Table**
The lower 5 bits of the 8-bit input are mapped to 6 bits based on the current running disparity (`RD`).
| Input 5-bit(LSB) | RD = 0 | RD = 1 |
|------------------|--------|---------|
| 00000 | 100111 | 011000 |
| 00001 | 011101 | 100010 |
| 00010 | 101101 | 010010 |
| 00011 | 110001 | 110001 |
| 00100 | 110101 | 001010 |
| 00101 | 101001 | 101001 |
| 00110 | 011001 | 011001 |
| 00111 | 111000 | 000111 |
| 01000 | 111001 | 000110 |
| 01001 | 100101 | 100101 |
| 01010 | 010101 | 010101 |
| 01011 | 110100 | 110100 |
| 01100 | 001101 | 001101 |
| 01101 | 101100 | 101100 |
| 01110 | 011100 | 011100 |
| 01111 | 010111 | 101000 |
| 10000 | 011011 | 100100 |
| 10001 | 100011 | 100011 |
| 10010 | 010011 | 010011 |
| 10011 | 110010 | 110010 |
| 10100 | 001011 | 001011 |
| 10101 | 101010 | 101010 |
| 10110 | 011010 | 011010 |
| 10111 | 111010 | 000101 |
| 11000 | 110011 | 001100 |
| 11001 | 100110 | 100110 |
| 11010 | 010110 | 010110 |
| 11011 | 110110 | 001001 |
| 11100 | 001110 | 001110 |
| 11101 | 101110 | 010001 |
| 11110 | 011110 | 100001 |
| 11111 | 101011 | 010100 |
### **3b/4b Encoding Table**
The upper 3 bits of the 8-bit input are mapped to 4 bits based on the current running disparity (`RD`).
| Input (MSB) | RD = 0 | RD = 1 |
|-------------|---------|---------|
| 000 | 0100 | 1011 |
| 001 | 1001 | 1001 |
| 010 | 0101 | 0101 |
| 011 | 0011 | 1100 |
| 100 | 0010 | 1101 |
| 101 | 1010 | 1010 |
| 110 | 0110 | 0110 |
| 111 | 1110 | 0001 | | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | encoder_8b10b | uut | [
{
"name": "encoder_8b10b.sv",
"content": "module encoder_8b10b (\n input logic clk_in, // Trigger on rising edge\n input logic reset_in, // Reset, assert HI\n input logic control_in, // Control character, assert HI for control words\n input logic ... | [] |
cvdp_copilot_traffic_light_controller_0007 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `traffic_controller_fsm`. Based on sensor inputs and timing signals, the FSM manages the traffic lights for both a main road and a side road. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameter Inputs - Outputs and Functional behaviour**
---
### Inputs and Outputs
| Signal | Direction | Bit Width | Active Level | Description |
|------------------------------|-----------|-----------|--------------|-----------------------------------------------------------------------------------------|
| **`i_clk`** | Input | 1 | — | System clock signal, with FSM transitions occurring on the rising edge. |
| **`i_rst_b`** | Input | 1 | Active-low | Asynchronous reset signal. When asserted (`0`), FSM resets to its initial state. |
| **`i_vehicle_sensor_input`** | Input | 1 | Active-high | Detects vehicle presence on the side road. High (`1`) when a vehicle is detected. |
| **`i_short_timer`** | Input | 1 | Active-high | Indicates the expiration of the short timer. High (`1`) when the short timer expires. |
| **`i_long_timer`** | Input | 1 | Active-high | Indicates the expiration of the long timer. High (`1`) when the long timer expires. |
| **`o_short_trigger`** | Output | 1 | Active-high | Initiates the short timer. Set to high (`1`) to start the short timer. |
| **`o_long_trigger`** | Output | 1 | Active-high | Initiates the long timer. Set to high (`1`) to start the long timer. |
| **`o_main[2:0]`** | Output | 3 | — | Controls main road traffic lights: Red (`3'b100`), Yellow (`3'b010`), Green (`3'b001`). |
| **`o_side[2:0]`** | Output | 3 | — | Controls side road traffic lights: Red (`3'b100`), Yellow (`3'b010`), Green (`3'b001`). |
### FSM Output Table
| State | Description | `o_main` | `o_side` | `o_short_trigger` | `o_long_trigger` |
|-------|---------------------------------------|-------------------|-------------------|-------------------|------------------|
| **S1** | Main road green, side road red | `3'b001` (Green) | `3'b100` (Red) | 0 | 1 |
| **S2** | Main road yellow, side road red | `3'b010` (Yellow) | `3'b100` (Red) | 1 | 0 |
| **S3** | Main road red, side road green | `3'b100` (Red) | `3'b001` (Green) | 0 | 1 |
| **S4** | Main road red, side road yellow | `3'b100` (Red) | `3'b010` (Yellow) | 1 | 0 |
### FSM Transition Logic
- **S1 → S2**: Transition when a vehicle is detected (`i_vehicle_sensor_input = 1`) and the long timer expires (`i_long_timer = 1`).
- **S2 → S3**: Transition upon short timer expiration (`i_short_timer = 1`).
- **S3 → S4**: Transition when either vehicle is detected (`i_vehicle_sensor_input = 1`) or the long timer expires (`i_long_timer = 1`).
- **S4 → S1**: Transition upon short timer expiration (`i_short_timer = 1`).
### Requirements
1. **Reset Behavior**: When the reset signal is active (`i_rst_b = 0`), the FSM should reset to **State S1** with the following initial values:
- **`o_main`** set to `3'b000` (main road lights off).
- **`o_side`** set to `3'b000` (side road lights off).
- **`o_long_trigger`** set to `1'b0` (long timer trigger reset).
- **`o_short_trigger`** set to `1'b0` (short timer trigger reset).
2. **Clocked Transitions**: The FSM should transition between states on the rising edge of the clock (`i_clk`).
3. **Synchronized Outputs**: Ensure the traffic light outputs (`o_main` and `o_side`) and the timer triggers (`o_long_trigger`, `o_short_trigger`) are properly synchronized with state transitions.
## 4. Test Bench Requirements
### 4.1 Stimulus Generation
1. **Reset and Initialization Stimulus**
1.1. Assert the asynchronous reset by driving the active-low reset signal to its active state for several clock cycles while keeping all other inputs inactive.
1.2. Deassert the reset by returning the active-low reset signal to its inactive state and wait one clock cycle for system initialization.
2. **Stimulus for the State with Main Road Green and Side Road Red (S1)**
2.1. **No Transition Conditions:**
2.1.1. Apply stimulus with the sensor input inactive and the long timer signal inactive for several clock cycles.
2.1.2. Apply stimulus with the sensor input active and the long timer signal inactive for several clock cycles.
2.1.3. Apply stimulus with the sensor input inactive and the long timer signal active for several clock cycles.
2.2. **Transition Condition:**
2.2.1. Apply stimulus with both the sensor input and the long timer signal active for one clock cycle.
3. **Stimulus for the State with Main Road Yellow and Side Road Red (S2)**
3.1. **No Transition Condition:**
3.1.1. Maintain the short timer signal inactive for several clock cycles.
3.2. **Transition Condition:**
3.2.1. Provide a one-clock-cycle pulse on the short timer signal.
4. **Stimulus for the State with Main Road Red and Side Road Green (S3)**
4.1. **No Transition Condition:**
4.1.1. Apply stimulus with the sensor input active and the long timer signal inactive for several clock cycles.
4.2. **Transition Conditions:**
4.2.1. Transition Branch A: Apply stimulus with the sensor input inactive (with the long timer signal inactive) for one clock cycle.
4.2.2. Transition Branch B: Alternatively, apply stimulus with the sensor input active and the long timer signal active for one clock cycle.
5. **Stimulus for the State with Main Road Red and Side Road Yellow (S4)**
5.1. **No Transition Condition:**
5.1.1. Maintain the short timer signal inactive for several clock cycles.
5.2. **Transition Condition:**
5.2.1. Provide a one-clock-cycle pulse on the short timer signal.
6. **Clock and Synchronization Stimulus**
6.1. Generate a continuous clock signal.
6.2. Ensure that any changes to the input signals are applied between clock edges so that state transitions occur on the rising edge of the clock.
7. **Timer Pulse Width Stimulus**
7.1. Apply one-clock-cycle pulses to the short timer and long timer signals to simulate timer expiration events.
7.2. In separate scenarios, hold the short timer and long timer signals active for multiple clock cycles.
8. **Comprehensive Sequence Stimulus**
8.1. Start with the reset sequence as described in section 1.
8.2. Progress through the full state cycle by sequentially applying stimulus to:
8.2.1. The state with main road green and side road red (S1), including both no transition and transition conditions.
8.2.2. The state with main road yellow and side road red (S2), including both no transition and transition conditions.
8.2.3. The state with main road red and side road green (S3), including both no transition and transition conditions using both branches.
8.2.4. The state with main road red and side road yellow (S4), including both no transition and transition conditions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | traffic_controller_fsm | dut | [
{
"name": "traffic_light_controller.sv",
"content": "module traffic_controller_fsm ( \n input i_clk, // System clock input\n input i_rst_b, // Active-low reset signal\n input i_vehicle_sensor_input, // High when a vehicle is present on the side road\n in... | [] |
cvdp_copilot_thermostat_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `thermostat`. It automatically switches between heating and cooling based on temperature feedback. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameter Inputs - Outputs and Functional behaviour**
### Inputs
1. **6-bit**: `i_temp_feedback[5:0]`
Each bit represents a distinct temperature condition :
- `i_temp_feedback[5]` : `i_full_cold` (1 = too cold)
- `i_temp_feedback[4]` : `i_medium_cold` (1 = medium cold)
- `i_temp_feedback[3]` : `i_low_cold` (1 = low cold)
- `i_temp_feedback[2]` : `i_low_hot` (1 = low hot)
- `i_temp_feedback[1]` : `i_medium_hot` (1 = medium hot)
- `i_temp_feedback[0]` : `i_full_hot` (1 = too hot)
2. **1-bit**: `i_fan_on`
- User control to turn the fan on manually (`1` = fan on, `0` = fan off).
3. **1-bit**: `i_enable`
- Enables or disables the thermostat.
- When `i_enable = 0`, all thermostat outputs must be forced to `0` regardless of temperature feedback.
4. **1-bit**: `i_fault`
- Signals a fault/error condition.
- When `i_fault = 1`, all outputs must be forced to `0` (overridden), ignoring normal FSM logic.
5. **1-bit**: `i_clr`
- Clears the error state set by `i_fault`. Upon assertion, the thermostat should return to `AMBIENT`.
6. **Clock/Reset**
- `i_clk`: Clock for sequential logic.
- `i_rst`: Asynchronous active-low reset.
---
### Outputs
1. **Heating Control (1-bit each)**
- `o_heater_full`
- `o_heater_medium`
- `o_heater_low`
2. **Cooling Control (1-bit each)**
- `o_aircon_full`
- `o_aircon_medium`
- `o_aircon_low`
3. **Fan Control (1-bit)**
- `o_fan`
4. **FSM Output State (3-bit)**
- `o_state[2:0]`: Indicates the current FSM state among the seven valid states:
- `3'b000` = `HEAT_LOW`
- `3'b001` = `HEAT_MED`
- `3'b010` = `HEAT_FULL`
- `3'b011` = `AMBIENT`
- `3'b100` = `COOL_LOW`
- `3'b101` = `COOL_MED`
- `3'b110` = `COOL_FULL`
---
### Reset/Idle Behavior
- **Asynchronous Reset (`i_rst` active low)**
- When `i_rst` is asserted (`0`), force the FSM to `AMBIENT` and all outputs to `0`.
- **Idle/Default State**
- `AMBIENT` state when no heating or cooling is required.
- When `i_clr` is asserted (to clear a fault), the FSM should go back to `AMBIENT` on the next rising clock edge if `i_rst` is not active.
---
### Fault Handling
- If `i_fault = 1`, **all outputs** (`o_heater_full`, `o_heater_medium`, `o_heater_low`, `o_aircon_full` , `o_aircon_medium`, `o_aircon_low`, `o_fan`) must be forced to `0`, overriding any state-based or feedback logic.
- Once a fault is signaled, the thermostat remains forced off until `i_clr` is asserted to clear the fault.
- After clearing the fault (`i_clr = 1`), the controller returns to `AMBIENT` state on the next rising clock edge.
---
### Enable Control
- If `i_enable = 0`, the thermostat is turned off.
- Force **all outputs** to `0` (similar to a disable override).
- Internally, the FSM move to `AMBIENT`.
---
## FSM State Transition Logic
On each rising edge of `i_clk` (while `i_rst = 1` and no fault override), the FSM evaluates the temperature feedback bits to determine the next state:
1. **Cold Conditions** (highest priority first)
- If `i_full_cold = 1`: transition to `HEAT_FULL`.
- Else if `i_medium_cold = 1`: transition to `HEAT_MED`.
- Else if `i_low_cold = 1`: transition to `HEAT_LOW`.
2. **Hot Conditions** (highest priority first)
- If `i_full_hot = 1`: transition to `COOL_FULL`.
- Else if `i_medium_hot = 1`: transition to `COOL_MED`.
- Else if `i_low_hot = 1`: transition to `COOL_LOW`.
3. **Ambient Condition**
- If none of the cold/hot feedback bits are asserted, transition to `AMBIENT`.
> **Note**: The bits `i_full_cold`, `i_medium_cold`, `i_low_cold` are mutually exclusive with `i_full_hot`, `i_medium_hot`, `i_low_hot`, meaning they will never be asserted at the same time.
---
## Output Logic
The output will be synchronous to `i_clk`, and should get asynchronously reset.
Given the current FSM state **(unless overridden by `i_fault` or disabled by `i_enable`)**:
- **Heating States**
- `HEAT_FULL`
- `o_heater_full = 1`, all other heater/cooler outputs = 0
- `HEAT_MED`
- `o_heater_medium = 1`, all other heater/cooler outputs = 0
- `HEAT_LOW`
- `o_heater_low = 1`, all other heater/cooler outputs = 0
- **Cooling States**
- `COOL_FULL`
- `o_aircon_full = 1`, all other heater/cooler outputs = 0
- `COOL_MED`
- `o_aircon_medium = 1`, all other heater/cooler outputs = 0
- `COOL_LOW`
- `o_aircon_low = 1`, all other heater/cooler outputs = 0
- **AMBIENT**
- All heater/aircon outputs = 0
- **Fan Control** (`o_fan`)
- `o_fan = 1` if any heater or air conditioner output is active in the current state **OR** if `i_fan_on = 1`.
- Otherwise, `o_fan = 0`.
---
## Overriding Conditions Summary
1. **Reset (`i_rst = 0`)**
- Highest-priority override: sets FSM to `AMBIENT`, outputs = 0 immediately (asynchronous).
2. **Fault (`i_fault = 1`)**
- Next-highest priority: overrides *all outputs* to 0, regardless of state or temperature feedback.
3. **Disable (`i_enable = 0`)**
- Next priority: thermostat outputs forced off (0). The FSM logic may remain in its current state internally, but no heat/cool/fan outputs are driven.
4. **Normal Operation**
- When `i_rst=1`, `i_fault=0`, and `i_enable=1`, the FSM outputs follow the state-based transitions and normal fan logic.
5. **Clearing Fault (`i_clr = 1`)**
- On the next rising clock edge, if `i_fault` is deasserted, the FSM moves to `AMBIENT` and resumes normal functionality.
-
## 4. Test Bench Requirements
### 4.1 Stimulus Generation
1. **Asynchronous Reset Scenario**
- Initiate a reset condition while the system is active.
2. **Idle Operation Scenario**
- Set up a condition where no temperature deviation is detected, the thermostat is enabled, there is no fault, and manual fan control is inactive.
3. **Extreme Cold Condition**
- Simulate a situation where the temperature feedback indicates a severe cold condition.
4. **Moderate Cold Condition**
- Create a scenario where the environment is moderately cold.
5. **Mild Cold Condition**
- Emulate a condition with only a slight drop in temperature.
6. **Extreme Hot Condition**
- Simulate a severe hot condition using temperature feedback.
7. **Moderate Hot Condition**
- Establish a scenario where the temperature feedback indicates moderate heat.
8. **Mild Hot Condition**
- Create a condition where there is only a slight increase in temperature.
9. **Conflicting Temperature Conditions**
- Provide simultaneous indications of severe cold and severe heat to test the system’s ability to prioritize among conflicting temperature conditions.
10. **Transition from Active Control to Ambient**
- First, simulate a temperature deviation that leads to active heating or cooling. Then remove the deviation so that the system naturally transitions back to an ambient (idle) state.
11. **Manual Fan Activation in Ambient Environment**
- In an ambient condition with no heating or cooling demand, manually activate the fan control.
12. **Disable Thermostat Operation**
- Under conditions that would normally trigger heating or cooling, disable the thermostat functionality.
13. **Fault Condition Enforcement**
- Introduce a fault during normal operation with active temperature deviation.
14. **Fault Clearance and Recovery**
- After inducing a fault condition, simulate the process of clearing the fault.
15. **Systematic Branch Testing:**
- **For Each FSM State:**
- Drive the thermostat naturally from AMBIENT into each of its 7 states (AMBIENT, HEAT_FULL, COOL_FULL, HEAT_MED, COOL_MED, HEAT_LOW, COOL_LOW) using specific temperature feedback vectors.
- **Within Each State:**
- Apply 7 distinct temperature feedback patterns that correspond to each branch in the state's nested decision logic (full cold, full hot, medium cold, medium hot, low cold, low hot, and default).
- **Reset Between Tests:**
- Return to AMBIENT between branch tests to ensure each condition is applied from a known starting point. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | thermostat | dut | [
{
"name": "thermostat.v",
"content": "module thermostat (\n input wire [5:0] i_temp_feedback, // Temperature feedback bits\n input wire i_fan_on, // Manual fan control\n input wire i_enable, // Enable thermostat\n input wire i_fault, // Fault signal\n inpu... | [] |
cvdp_copilot_apb_dsp_unit_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `apb_dsp_unit`. The module serves as an APB interface for configuring internal registers. These registers specify which memory addresses are used for arithmetic operations (addition or multiplication). The computed result is then made available through a designated register. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
---
### Register Descriptions
1. **`r_operand_1`**
- **Address:** 0x0
- **Function:** Holds the memory address of the first operand.
2. **`r_operand_2`**
- **Address:** 0x1
- **Function:** Holds the memory address of the second operand.
3. **`r_Enable`**
- **Address:** 0x2
- **Values:**
- `0`: DSP disabled
- `1`: Addition mode
- `2`: Multiplication mode
- `3`: Data Writing mode
4. **`r_write_address`**
- **Address:** 0x3
- **Function:** Specifies the address in memory where data will be written.
- **Default Value:** 0x00000000
- **Usage:** If `r_Enable` = 3, the data in the `r_write_data` register is written to the address specified by this register.
5. **`r_write_data`**
- **Address:** 0x4
- **Function:** Specifies the data to be written into memory.
- **Default Value:** 0x00000000
- **Usage:** If `r_Enable` = 3, the data in this register is written to the address specified by `r_write_address`.
---
### APB Interface:
#### Clock & Reset Signals
- `pclk`: APB clock input for synchronous operations.
- `presetn`: Active-low asynchronous reset signal for system initialization.
#### APB Signals
- `paddr` (input, 10 bits): Address bus for accessing internal CSR registers and Memory.
- `pselx` (input): APB select signal, indicating CSR and Memory selection.
- `penable` (input): APB enable signal, marking transaction progression.
- `pwrite` (input): Write-enable signal, distinguishing read from write operations, high for write and low for read operation.
- `pwdata` (input, 8 bits): Write data bus for sending data to CSR registers and Memory.
- `pready` (output, reg): Ready signal, indicating the completion of a transaction.
- `prdata` (output, reg, 8 bits): Read data bus for retrieving data.
- `pslverr` (output, reg): Error signal for invalid addresses or unsupported operations.
### SRAM Interface:
- `sram_valid`: At positive edge of this signal, data in `r_write_data` is latched to address in `r_write_address`.
---
### APB Protocol
1. **Read Operations**
- In the **READ_STATE**, drive `prdata` with the register value corresponding to `paddr`.
- After operation, return to **IDLE**.
2. **Write Operations**
- In the **WRITE_STATE**, update the register selected by `paddr` with `pwdata`.
- After updating the register, return to **IDLE**.
3. **Reset Behavior**
- When `presetn` is deasserted (active-low), reset all outputs and internal registers to their default values:
- Set `pready` and `pslverr` to 0.
- Clear `prdata`.
- Initialize `r_operand_1`, `r_operand_2`, `r_Enable`, `r_write_address`, and `r_write_data` to 0.
---
### Functional Behavior
1. **APB Interface Control**
- Memory is accessed via the APB interface.
- The operational mode is controlled by **`r_Enable`**:
- **Default (0x0):** DSP is disabled.
- **Write Mode (0x3):** Data can be written to memory.
- **Addition Mode (0x1):** Values at the addresses specified by **`r_operand_1`** and **`r_operand_2`** are added. The result is stored at address **0x5**.
- **Multiplication Mode (0x2):** Values at the addresses specified by **`r_operand_1`** and **`r_operand_2`** are multiplied. The result is stored at address **0x5**.
- To read computed data directly via APB, use address **0x5** and retrieve it through **`PRDATA`**.
2. **Error Handling**
- If a read or write operation is attempted on an address outside the defined registers, **`PSLVERR`** is driven high (`1'b1`).
3. **Wait States**
- This design does not support wait states. All APB read/write operations complete in two clock cycles, with **`PREADY`** always driven high (`1'b1`).
4. **Memory Interface**
- A 1 KB SRAM module serves as the memory.
**Note:** Addresses from **0x00** to **0x05** are reserved for configuration registers.
## Test Bench Requirements
### Stimulus Generation
#### 1. **Reset and Initialization**
1. Drive `presetn` low for a defined interval.
2. Drive `presetn` high to release reset.
#### 2. **APB Write Stimulus**
1. Access each **valid register** address (`0x0` to `0x4`) with:
- `pselx` = 1
- `penable` toggled appropriately
- `pwrite` = 1
- Various `pwdata` patterns (e.g., minimum, maximum, random).
2. Perform **consecutive writes** to different registers in rapid succession.
3. Issue a **write** to an **invalid address** (greater than `0x5`).
4. Attempt memory writes under various `r_Enable` states, including values outside the valid range of modes.
#### 3. **APB Read Stimulus**
1. Read from **each valid register** address (`0x0` to `0x5`) with:
- `pselx` = 1
- `penable` toggled appropriately
- `pwrite` = 0
2. Perform **back-to-back** reads of the same register and different registers.
3. Issue a **read** to an **invalid address** (greater than `0x5`).
4. Vary APB handshake signals, including cases with missing or incorrect enable signals.
#### 4. **DSP Arithmetic Stimulus**
### 4.1 **Addition Mode**
1. Set `r_Enable` to indicate addition mode.
2. Provide valid addresses in `r_operand_1` and `r_operand_2` that point to memory locations.
3. Use data-writing transactions to load different data patterns into those memory addresses.
4. Include minimal, maximal, and intermediate values to explore potential overflow and boundary conditions.
##### 4.2 **Multiplication Mode**
1. Set `r_Enable` to indicate multiplication mode.
2. Provide valid addresses in `r_operand_1` and `r_operand_2`.
3. Use memory transactions to populate these locations with a variety of patterns.
4. Include edge cases that might trigger overflow scenarios.
#### 5. **Memory Write Stimulus**
1. Set `r_Enable` to indicate write mode.
2. Vary `r_write_address` and `r_write_data` across:
- Low, high, and random valid addresses.
- Low, high, and random data values.
3. Drive `sram_valid` high to trigger the memory-write mechanism.
4. Attempt writing beyond the valid memory range.
#### 6. **Error Condition Stimulus**
1. Drive **invalid `r_Enable`** values beyond the defined modes.
2. Perform APB **read/write operations** without correctly asserting `penable` or `pselx`.
3. Access invalid or out-of-range addresses with and without proper handshake signals.
#### 7. **Stress and Concurrency Stimulus**
1. Issue **rapid sequences** of APB transactions (reads and writes) to valid and invalid addresses.
2. Continuously switch `r_Enable` among different modes (addition, multiplication, write, disabled, and any invalid code).
3. Randomize APB signals (within protocol constraints) to test corner cases of back-to-back operations.
#### 8. **Full Coverage Stimulus**
1. Stimulate **every register** in both read and write directions.
2. Exercise **all operational modes** defined in the design, plus invalid ones.
3. Drive memory addresses across the **entire valid range** and some out-of-range values.
4. Include data patterns that explore arithmetic boundary conditions (such as overflow scenarios).
#### 9. Additional Test Cases for Complete Coverage
##### 9.1. Full Bit Toggling on Registers
- Write `0xFF` and `0x00` to:
- `r_operand_1`
- `r_operand_2`
- `r_enable`
- `r_write_address`
- `r_write_data`
##### 9.2. Memory Boundary Testing
- Write to the **maximum valid memory address** (`10'h3FF` = 1023).
- Attempt an **out-of-range write** (`10'h401` = 1025) when `r_enable = MODE_WRITE`.
##### 9.3. Repeated Reset to Toggle Related Signals
- Assert and deassert `presetn` **mid-test** to toggle:
- `pready`
- `pslverr`
##### 9.4. Out-of-Range Address Read
- **Read from `10'h401`** after an out-of-range write to verify `PSLVERR`. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | apb_dsp_unit | dut | [
{
"name": "apb_dsp_unit.v",
"content": "module apb_dsp_unit (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire penable,\n input wi... | [] |
cvdp_copilot_vending_machine_0006 | medium | Non-Agentic | Complete the given partial SystemVerilog testbench `serial_line_code_converter_tb`. The testbench must instantiate the `serial_line_code_converter` RTL module and provide input stimulus for various testcases. This testbench simulates a vending machine that processes item selection, coin insertion, item dispensing, change return, and purchase cancellation.
## Description
The vending machine operates using a finite state machine (FSM) with distinct states to ensure a structured transaction flow. It begins in the IDLE state, awaiting item selection before allowing coin insertion. The machine validates inserted coins, dispenses the item upon sufficient payment, and returns change if necessary. Errors trigger the RETURN_MONEY state, ensuring incorrect transactions are handled properly, and a reset clears all internal states, preparing the machine for a new transaction.
## **Interface**
### **Inputs**
- **clk:** Clock signal for timing and synchronizing state transitions, operating on the rising edge.
- **rst:** Asynchronous, active-high reset signal that resets all internal states, outputs, and accumulated values, returning the machine to the `IDLE` state.
- **item_button(1-bit):** Signal indicating that the user has pressed the button to initiate item selection (active high). This acts as a toggle signal and should only register on the rising edge.
- **item_selected (3-bits, [2:0]):** This input represents the item chosen by the user, with valid values corresponding to the four available items (valid values: `3'b001` to `3'b100`).
- **coin_input(4-bits, [3:0]):** This input represents the value of the coin inserted, with valid values of 1, 2, 5, or 10 units.
- **cancel (1-bit):** Signal allowing the user to cancel the current transaction before the item is dispensed (active high).
### **Outputs**
- **dispense_item(1-bit):** Indicates that the selected item is ready for dispensing after the required amount is met. Active high for one clock cycle when the item is being dispensed.
- **return_change(1-bit):** Signal that excess coins are being returned as change. Active high for one clock cycle when change is being returned.
- **item_price(5-bits,[4:0]):** Output displaying the price of the currently selected item.
- **change_amount(5-bits,[4:0]):** Output representing the amount of change to be returned if excess coins were inserted.
- **dispense_item_id(3-bits,[2:0]):** Output indicating the ID of the item being dispensed.
- **error(1-bit):** Indicates that an invalid operation has occurred, such as inserting coins without selecting an item or entering invalid coin values. Active high for one clock cycle during an error condition.
- **return_money(1-bit):** Indicates that all inserted money should be returned due to cancellation or an error. Active high for one clock cycle when returning money.
## Instantiation
The testbench instantiates the `vending_machine` module as `uut` (unit under test) and connects the signals accordingly.
### Input Generation and Validation
#### Clock Generation
The `clk` signal should toggle every 5 time units, simulating a 100MHz clock.
#### Reset Handling
The `rst` signal should be high at the beginning of the simulation for at least three clock cycles.
### Test Scenarios
The testbench should generate multiple real-world scenarios involving purchases, cancellations, and error handling.
#### 1. System Initialization
- Generate a clock signal and assert the reset signal for multiple cycles to initialize the system in a defined state.e.
#### 2. Selecting an Item
- Assert and de-assert the selection button within a clock cycle while setting the selected item ID.
#### 3. Inserting Coins
- A value representing the coin input is assigned, and after a clock cycle, it is reset to zero.
#### 4. Cancelling a Purchase
- The cancel button is asserted and de-asserted within one clock cycle.
#### 5. Purchasing an Item with Exact Coins
- Select an item 1 and insert the exact required amount (5) in a single step.
#### 6. Purchasing an Item with Multiple Coin Insertions
- Select item 2 and insert a partial amount (5), followed by the remaining balance (5) in subsequent cycles.
#### 7. Purchasing an Item with Extra Coins and Getting Change
- Select item 2 and insert more than the required amount and ensure a change is computed.
#### 8. Cancelling a Purchase After Inserting Some Coins
- Select an item, insert partial coins, then assert cancel.
#### 9. Cancelling Immediately After Selecting an Item
- Select an item and immediately trigger cancellation.
#### 10. Purchasing an Expensive Item with Multiple Small Coin Insertions
- Insert small denominations over multiple steps to accumulate the required price.
#### 11. Inserting Coins Without Selecting an Item
- Insert money without item selection.
#### 12. Resetting the System After Inserting Coins or Selecting an Item
- Initiate a transaction, assert reset, and verify system restart.
#### 13. Rapid Successive Coin Insertions
- Insert multiple small denominations in quick succession.
#### 14. Rapid Coin Insertion Handling
- The same coin value is inserted multiple times in quick succession.
#### 15. Selecting an Invalid Item ID
- A non-existent item ID is chosen.
#### 16. Returning Money When No Item Is Selected
- Insert money and verify refund without selection.
#### 17. Transition from Dispensing an Item to Returning Change
- Overpay and verify that dispensing occurs before change return.
#### 18. Transition from Returning Change Back to Idle
- Complete a purchase with a change return and verify system readiness.
#### 19. Cancelling After Pressing the Item Selection Button
- Select an item and cancel before inserting money.
### Final Steps
- **Simulation End**: After all tests, wait for a few cycles and call `$finish`.
- **Waveform Dump**: Generate a VCD file for offline analysis.
### Partial Test Stimulus Generator Code:
```verilog
module vending_machine_tb;
reg clk; // Clock signal
reg rst; // Reset signal
reg item_button; // Signal for item selection button press
reg [2:0] item_selected; // Input to select one of 4 items
reg [3:0] coin_input; // Coin input
reg cancel; // Cancel button signal
wire dispense_item; // Signal to dispense item
wire return_change; // Signal to return change
wire error; // Error signal if any invalid operation occurs
wire return_money; // Signal to return all money if operation is cancelled
wire [4:0] item_price; // Price of the selected item
wire [4:0] change_amount; // Amount of change to return
wire [2:0] dispense_item_id;// ID of item being dispensed
// Instantiate the vending machine module
vending_machine uut (
.clk(clk),
.rst(rst),
.item_button(item_button),
.item_selected(item_selected),
.coin_input(coin_input),
.dispense_item(dispense_item),
.return_change(return_change),
.item_price(item_price),
.change_amount(change_amount),
.dispense_item_id(dispense_item_id),
.error(error),
.cancel(cancel),
.return_money(return_money)
);
// Clock generator: Clock signal toggles every 5 time units
always #5 clk = ~clk;
// Task to initialize the testbench (reset and initial conditions)
task initialize;
begin
clk = 0;
rst = 1;
item_button = 0;
item_selected = 3'b000;
coin_input = 0;
cancel = 0;
@(posedge clk) rst = 0;
end
endtask
// Task to select an item
task select_item(input [2:0] item);
begin
@(posedge clk)
item_button = 1;
@(posedge clk) item_button = 0;
item_selected = item;
@(posedge clk);
end
endtask
// Insert the code for the remaining test stimulus here
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | vending_machine | uut | [
{
"name": "vending_machine.sv",
"content": "module vending_machine(\n input clk, // Clock signal\n input rst, // Reset signal\n input item_button, // Signal for item selection button press (active high, rising edge)\n input [2:0]... | [] |
cvdp_agentic_lfsr_0018 | medium | Agentic | I have a documentation `docs/8Bit_lfsr_spec.md` for the `lfsr_8bit` module. Write a SystemVerilog testbench `tb_lfsr_8bit.sv` in the verif directory that generates stimulus to thoroughly test and achieve maximum functional coverage for the `lfsr_8bit` module.
___
### The interface of `lfsr_8bit` RTL module is given below:
### **Inputs:**
- `clk`: Clock signal for synchronous operation, design works on Positive edge of clock.
- `reset`: Asynchronous active-low reset signal.
- `lfsr_seed [7:0]`: A 8-bit register providing the initial seed value to the LFSR.
- `sel`: A 1-bit signal selecting the operation type (`NAND = 1`, `NOR = 0`).
- `dir`: A 1-bit signal indicating the direction of the shift (`0 = LSB to MSB`, `1 = MSB to LSB`).
- `weight [2:0]`: A 3-bit control signal specifying the weight of the feedback logic.
### **Outputs:**
- `lfsr_new [7:0]`: A 8-bit wire representing the LFSR's output after feedback and shifting.
___
### Input Generation and Validation
**Input Generation:**
1. Random Input Generation:
- Randomly generate seed values (`lfsr_seed`) to test various initial states of the LFSR.
- Vary `weight` from 0 to 7 to test feedback logic across all configurations.
- Randomize `sel` and `dir` to verify behavior for NAND/NOR operations and both shift directions.
2. Parameterized Testing:
- Cover cases for all combinations of `sel` (`NAND/NOR`) and `dir` (`LSB to MSB/MSB to LSB`).
- Include scenarios for:
- Minimum weight (`weight = 0`).
- Maximum weight (`weight = 7`).
- Boundary weight values like `weight = 1`, `weight = 7`.
3. Edge Cases:
- Reset Behavior:
- Assert reset as logic LOW to apply seed value to the LFSR.
- No Shift (`weight = 0`):
- Apply `weight` input as logic LOW to test the status of `lfsr_new`
- Maximum Weight:
- Test heavily weighted feedback logic (e.g., `weight = 7`) for both `NAND` and `NOR` operations.
- Alternating Feedback:
- Test with patterns that toggle bits in a predictable way to verify correct feedback propagation.
___
### **Instantiation**
Name the instance of the RTL as `uut`.
### **Module Functionality:**
- Feedback Logic:
- Compute feedback using weighted `NOR` or `NAND` operations based on the `sel` signal.
- Support direction control (`LSB to MSB` or `MSB to LSB`) for shift and feedback propagation.
- Shift Logic:
- Propagate bits according to the selected direction.
- Inject feedback into the appropriate end of the register. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 85
}
] | lfsr_8bit | uut | [
{
"name": "lfsr_8bit.sv",
"content": "`timescale 1ns / 1ps\n\nmodule lfsr_8bit (\n input clock,\n input reset,\n input [7:0] lfsr_seed,\n input sel, // Selector for NAND or NOR operation (0: NOR for more 0s, 1: NAND for more 1s)\n input dir, // Direction control (0: LSB to MSB, 1: MSB to LS... | [
{
"name": "8Bit_lfsr_spec.md",
"content": "# **Specification Document: 8-bit LFSR with Configurable Feedback, Direction, and Weighted Logic**\n\n## **1. Introduction**\nThis document describes the design and implementation of a **8-bit Linear Feedback Shift Register (LFSR)** using the **Galois configuration... |
cvdp_copilot_static_branch_predict_0035 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_static_branch_predict` that instantiates the `static_branch_predict` module as the Unit Under Test (UUT). The testbench must include a stimulus generator that systematically drives various input conditions to achieve a minimum of 95% code and functional coverage for the `static_branch_predict` module. The `static_branch_predict` takes a 32-bit branch or jump RISC-V instruction as input and predicts whether that branch will occur based on the conditions indicated in the instruction.
## Design Specification:
The `static_branch_predict` module takes in a 32-bit RV32I (RISC V 32-bit base Integer ISA) conditional branch and unconditional jump instructions as input. This module generally exists as part of the Instruction Fetch Stage of a pipelined processor. The branch and jump instruction can be either from the RV32I Instruction Set or from the RV32C Instruction Set. The branch and jump instructions as part of the RV32I Instruction Set are 32-bit in width, whereas those belonging to the RV32C Instruction Set are 16-bit in width. The 16-bit RV32C branch and jump instructions are converted into an equivalent 32-bit RV32I instruction using a specialized circuit called Instruction Decompresser before being applied to this module. For the module to recognize the 32-bit equivalent of the 16-bit branch and jump instructions, the inputs are properly formatted into a 32-bit value and applied. The Instruction Decompresser is not instantiated into the branch predictor module. Based on the instruction's offset in the case of the branch instruction and based on instruction in the case of a jump instruction, the branch predictor outputs two signals (i) a 1-bit signal to indicate whether the branching will occur for a given instruction or not (ii) If branching occurs, to which 32-bit address it has to get branched.
## Key Assumptions and Constraints:
- Only uncompressed 32-bit instructions are applied as input to this module.
- The module operates in a purely combinational manner without requiring any state elements such as registers.
- The Instruction Decompressor is outside the scope of this module, and the equivalent 32-bit uncompressed instruction is
given as input.
### Introduction to RISC V:
RISC-V is a royalty-free open-source instruction set architecture, which anyone can utilize to implement a processor microarchitecture (i.e. processor hardware). The RISC-V ISA consists of three variants of Integer ISA namely RV32I (32-bit instructions to handle 32-bit data), RV64I (32-bit instructions to handle 64-bit data), and RV128I (32-bit instructions to handle 128-bit data). In addition to these, there are 14 extensions. One of the extensions that will be considered in this module is RV32C (16-bit ISA called Compressed RISC-V ISA)
## RV32I Branch and Jump Instructions
The RISC-V RV32I instruction set includes both unconditional jump and conditional branch instructions. Below, we describe the encodings and behaviors for these types of instructions.
### Unconditional Jump Instructions(JAL and JALR)
`JAL` (Jump and Link instruction):
- Branches to an address obtained by adding the 32-bit program counter (pc) to a sign-extended 20-bit offset encoded in the instruction.
- Returns to resume execution from the address stored in the 32-bit link register (x1 or x5) after completing the branched subroutine. A link register (also called a return address register) is the one that holds the address from where the processor has to resume its execution after returning from a subroutine.
**Instruction Encoding**:
**| 31 - imm[20] | 30:21 - imm[10:1] | 20 - imm[11] | 19 : 12 - imm[19:12] | 11 : 7 - rd | 6 : 0 - 7'h6F |**
Assembler syntax for JAL instruction : jal rd , imm[20:1]
Target Address calculated for this instruction :
rd <--- pc + {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };
where {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 } - 32-bit sign extended offset or immediate.
Here, `rd` is a 5-bit number to identify the 32-bit destination register; `pc` - 32-bit program counter.
`JALR` (Jump and Link Register instruction):
- Branches to an address obtained by adding the 32-bit program counter to a sign-extended 12-bit offset present in a register specified in the instruction.
The instruction encoding for 32-bit uncompressed JALR instruction
**Instruction Encoding**:
**| 31 :20 - imm[11:0] | 19:15 - rs1 | 14:12 - 000 | 11 : 7 - rd | 11 : 7 - rd | 6 : 0 - 7'h67 |**
Assembler syntax for JAL instruction: jalr rd, rs1, imm[11:0]
Target address calculated for this instruction :
rd <-pc + {{20{instr[31]}}, instr[31:20]} + rs1
where
{{20{instr[31]}}, instr[31:20]} + rs1 - 32-bit sign extended offset or immediate
Here `rd` is the 5-bit number to identify a 32-bit destination register; `rs1` is the 5-bit number to identify the 32-bit source register; `pc` - 32-bit program counter
### Conditional Branch Instructions (BXXX) :
- Takes in two operands (rs1 and rs2), compares them, and branches based on the comparison result.
- The target address is obtained by adding the pc to a sign-extended 12-bit offset encoded in the instruction.
The instruction encoding for the 32-bit uncompressed Branch instruction
**Instruction Encoding**:
**| 31 - imm[12]|30:25 - imm[10:5]|24:20 - rs2 | 14 : 12 - func3| 11 : 8 - imm[4:1]|7 - imm[11]| 6 : 0 - 7'h63 |**
Assembler syntax for Branch instruction: bxxx rs1, rs2, offset
Here `rs1` and `rs2` are the 5-bit numbers to identify the 32-bit source registers which will be used for comparison
Target address calculated for this instruction :
pc + { {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 };
where,
{ {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 } - 32-bit sign extended offset or immediate; `pc` - 32-bit program counter
The different types of branch instruction :
- beq rd , rs1 , rs2 , imm[12:1] (func3 = 3'b000)
- bne rd , rs1 , rs2 , imm[12:1] (func3 = 3'b001)
- blt rd , rs1 , rs2 , imm[12:1] (func3 = 3'b100)
- bltu rd , rs1 , rs2 , imm[12:1] (func3 = 3'b110)
- bge rd , rs1 , rs2 , imm[12:1] (func3 = 3'b101)
- bgeu rd , rs1 , rs2 , imm[12:1] (func3 = 3'b111)
## RV32C Branch and Jump Instructions :
The RV32C compressed instructions are 16-bit wide, but before applying them to this module, they are converted to their equivalent 32-bit uncompressed form using an external decompressor circuit. The following sections describe how these instructions are handled.
### C.J / C.JAL Instructions:
- Equivalent to the RV32I JAL instruction, with different function codes.
The instruction encoding for the 16-bit compressed jump instruction is given below:
**Instruction Encoding**:
**| 15 : 13 - func3 | 12:2- imm[11:1]| 1 : 0 - 01 |**
Assembler syntax for C.J instruction: c.j offset[11:1]
Assembler syntax for C.JAL instruction: c.jal offset [11:1]
`func3` is a 3-bit code that differentiates between C.J and C.JAL instruction.
The 3-bit function code for C.J is 101 and C.JAL is 001.
Its equivalent 32-bit uncompressed instruction encoding is given by :
**Instruction Encoding**:
**| 31 - instr_c[12] | 30 -instr_c[8] | 29 : 28 - instr_c[10:9]| 27 - instr_c[6]| 26- instr_c[7]| 25 - instr_c[2] | 24- instr_c[11]|**
**| 23 : 21 - instr_c[5:3] | 20 : 12 - {9{instr_c[12]}}| 11 : 8 - 4'b0000 | 7 - ~instr_c[15] | 6 : 0 - 7'h6F |**
Only C.J and C.JAL instructions are supported by this module.
Other Compressed Jump Instructions that RV32C supports are C.JR and C.JALR, but these are not being tested by the module.
### C.BEQZ / C.BNEZ Instructions:
Equivalent to the RV32I BXXX instructions but check whether the content of the specified register(rs1') is zero or not.
The instruction encoding for the 16-bit compressed branch instruction is given below:
**Instruction Encoding**:
**| 15 : 13 - func3 | 12 : 10 - imm[8:6] | 9 : 7 - rs1' | 6 : 3 - imm[4:1]| 2 - imm[5]| 1 : 0 - 01 |**
- func3 is a 3-bit code that differentiates between C.BEQZ and C.BNEZ instruction
- The 3-bit function code for Compressed Branch EQual Zero (C.BEQZ) is 110 and that of Compressed Branch Not
Equal Zero (C.BNEZ) is 111
Assembler syntax for C.BEQZ instruction: c.beqz rs1' , offset[8:1]
Assembler syntax for C.BNEZ instruction: c.bnez rs1', offset[8:1]
Its equivalent 32-bit uncompressed instruction encoding is given by :
**Instruction Encoding**:
**| 31 : 28 - {4{instr_c[12]}} | 27 : 26 - instr_c[6:5] | 25 - instr_c[2]| 24 : 20 - 5'b00000 | 19 : 18 - 2'b01 | 17 : 15 - instr_c[9:7] |**
**| 14 : 13 - 2'b00 | 12 - instr_c[13] | 11 : 10 - instr_c[11:10] | 9 : 8 - instr_c[4:3] | 7 - instr_c[12] | 6 : 0 - 7'h63 |**
### Only Supported Instructions
- The following instructions are supported by this module:
- Uncompressed Instructions: JAL, JALR, BXXX.
- Compressed Instructions: C.J, C.JAL, C.BEQZ, C.BNEZ.
- For all other instructions, fetch_valid_i will be 0, indicating that they will not be predicted as taken.
### Concept of Sign Extension of Immediate(or Offset) in the RISC V Control Transfer Instruction :
Sign extension refers to identifying the sign bit of an operand and replicating it at the higher significant positions to increase the operand width to the desired value.
Illustration :
Suppose there is 8-bit data, data[7:0], say 8'b0110_1110. Suppose this has to be stored in a 32-bit register rd.
| Bit Position : Bit Value | 7 : 0 | 6 : 1 | 5 : 1 | 4: 0 | 3 : 1 | 2 : 1 | 1 : 1 | 0 : 0 |
Here the bit at position 7 is called sign-bit; Since it is 0, it indicates that it is a positive value. Hence, will be replicated in the higher 24-bit positions (i.e. from bit position 8 to bit position 31) to form a 32-bit value. This is represented in shorthand as
rd <--- {{24{0}} , data_i[7:0]};
### Static Branch Prediction Algorithm :
### For Branch Instruction:
- Immediate Extraction:
Extract the immediate value from the branch instruction.
- Sign Extension:
Sign extend the immediate to 32 bits.
- Prediction Logic and Target Address Calculation:
If the sign bit of the immediate is 1, the branch is predicted to be taken.
Otherwise, it is predicted as not taken.
The 32-bit program counter is added to the sign-extended offset or sign-extended immediate to form the target address
### For Jump Instruction:
- Immediate Extraction:
Extract the immediate value from the jump instruction.
- Sign Extension:
Sign extend the immediate to 32 bits.
- Prediction Logic and Target Address Calculation:
Always predict jumps (JAL, JALR, C.J, C.JAL) as taken.
The 32-bit program counter is added to the sign-extended offset or sign-extended immediate to form the target address
## What do the words `taken` and `not-taken` signify in case of branch prediction :
- Taken: The branch will occur, and execution will continue at the target address.
- Not-Taken: The branch will not occur, and execution continues sequentially.
### Interface :
#### Inputs:
- `fetch_rdata_i` ([31:0], 32-bit): The fetched instruction data from the instruction memory or pipeline.
- `fetch_pc_i` ([31:0], 32-bit): Program counter (PC) value of the fetched instruction.
- `fetch_valid_i` (1-bit): Active HIGH Indicates the validity of the fetched instruction.
#### Outputs:
- `predict_branch_taken_o` (1-bit): Active HIGH indicates whether the branch or jump is predicted as taken.
- `predict_branch_pc_o` ([31:0], 32-bit): Predicted target address for a taken branch or jump instruction
### Internal registers and parameters:
#### Localparams :
- OPCODE_BRANCH = 7'h63
- OPCODE_JAL = 7'h6F;
- OPCODE_JALR = 7'h67;
#### Immediate:
- `imm_j_type` ([31:0], 32-bit): Immediate for uncompressed jump (JAL) instructions, sign-extended.
- `imm_b_type` ([31:0], 32-bit): Immediate for uncompressed branch instructions, sign-extended.
- `imm_cj_type` ([31:0], 32-bit): Immediate for compressed jump instructions, sign-extended.
- `imm_cb_type` ([31:0], 32-bit): Immediate for compressed branch instructions, sign-extended.
- `branch_imm` ([31:0], 32-bit): One of the immediate values: `imm_j_type` or `imm_b_type` or `imm_cj_type` or `imm_cb_type`.
### Signals and Logic :
#### Control Signals:
- `instr` ([31:0], 32-bit): Alias for the input `fetch_rdata_i` to simplify the code.
- `instr_j`, `instr_b`, `instr_cj`, `instr_cb` (1-bit each): Signals to identify specific branch or jump types in compressed and uncompressed formats.
- `instr_b_taken` (1-bit): Indicates whether an uncompressed or compressed branch offset is negative, implying that the branch is taken.
**Instantiation** :
The testbench instantiates the `static_branch_predict` module as `uut` and connects the signals between the module and the testbench. Each input and output from the `uut` is connected to its corresponding signal in the testbench.
## **Input Generation and Validation**:
- Stimulus: Several test cases must be applied to simulate various operations of the static branch predictor. These test cases should cover a range of scenarios, including branch instructions with positive and negative offsets, jump instructions (both JAL and JALR), compressed jump and branch instructions, as well as invalid fetch conditions and non‐branch operations. For each case, the relevant signals (`predict_branch_taken_o`, `predict_branch_pc_o`) have to be displayed immediately after the application of inputs (`fetch_rdata_i`, `fetch_pc_i`, `register_addr_i`, `fetch_valid_i`).
- **Test Case 1: Branch taken, PC offset negative (B-type) [BEQ]**
Test a BEQ instruction with a negative offset, expecting the branch to be taken with the target PC computed accordingly.
- **Test Case 2: Branch taken, PC offset positive (B-type) [BEQ]**
Test a BEQ instruction with a positive offset, ensuring correct branch prediction and target PC calculation for a forward branch.
- **Test Case 3: Jump taken (J-type) with negative offset [JAL]**
Apply a JAL instruction with a negative offset to validate that the jump is correctly predicted and the computed PC reflects a backward jump.
- **Test Case 4: Jump taken (J-type) with positive offset [JAL]**
Use a JAL instruction with a positive offset to verify the proper prediction of a forward jump with the correct target PC.
- **Test Case 5: Jump with valid false (JAL)**
Apply a JAL instruction with fetch_valid_i deasserted, ensuring that no branch prediction is produced.
- **Test Case 6: Jump Register (JALR) taken with negative offset (reg = 0) [JALR]**
Test a JALR instruction with a negative offset using a zero register operand to confirm correct target PC computation.
- **Test Case 7: Jump Register (JALR) taken with positive offset (reg = 0) [JALR]**
Test a JALR instruction with a positive offset using a zero register operand.
- **Test Case 8: Jump Register (JALR) taken with negative offset (nonzero reg) [JALR]**
Apply a JALR instruction with a negative offset using a nonzero register operand to exercise immediate addition.
- **Test Case 9: Jump Register (JALR) taken with positive offset (nonzero reg) [JALR]**
Apply a JALR instruction with a positive offset using a nonzero register operand to verify proper computation.
- **Test Case 10: Jump Register (JALR) with valid false [JALR]**
Test a JALR instruction with fetch_valid_i deasserted, ensuring no prediction is produced.
- **Test Case 11: Compressed Jump taken (C.J) with positive offset [C.J]**
Test a compressed jump instruction with encoding 3'b101 and bit12 = 0, yielding a positive immediate for jump target calculation.
- **Test Case 12: Compressed Jump taken (C.J) with negative offset [C.J]**
Test a compressed jump instruction with encoding 3'b001 and bit12 = 1, producing a negative immediate for a backward jump.
- **Test Case 13: Compressed Branch not taken (C.BEQZ) with 3'b110 encoding [C.BEQZ]**
Test a compressed branch instruction with encoding 3'b110 and bit12 = 0, expecting the branch not to be taken.
- **Test Case 14: Compressed Branch taken (C.BEQZ) with 3'b110 encoding [C.BEQZ]**
Test a compressed branch instruction with encoding 3'b110 and bit12 = 1, expecting the branch to be taken.
- **Test Case 15: Compressed Branch not taken (C.BEQZ) with 3'b111 encoding [C.BEQZ]**
Test a compressed branch instruction with encoding 3'b111 and bit12 = 0, ensuring the branch is not taken.
- **Test Case 16: Compressed Branch taken (C.BEQZ) with 3'b111 encoding [C.BEQZ]**
Test a compressed branch instruction with encoding 3'b111 and bit12 = 1, expecting the branch to be taken.
- **Test Case 17: Default non‐branch (zero instruction)**
Apply an all‑zeros instruction to verify that no branch or jump is predicted.
- **Test Case 18: Default non‐branch (random instruction)**
Apply a random non‑branch instruction, confirming that the predictor remains inactive.
- **Test Case 19: Default non‐branch with valid false**
Apply a non‑branch instruction with 1fetch_valid_i1 deasserted, ensuring no prediction occurs.
- **Test Case 20: Default non‐branch (all ones)**
Apply an instruction of all ones, verifying default non‑branch behavior.
- **Test Case 21: Default non‐branch (instruction with lower 2 bits ≠ 01)**
Test an instruction that does not meet the compressed instruction format, confirming non‑branch operation.
- **Test Case 22: Default non‐branch (random pattern)**
Apply a random instruction that does not correspond to any branch or jump, ensuring default behavior.
- **Test Case 23: Default non‐branch (random pattern with valid false)**
Apply a random non‑branch instruction with fetch_valid_i deasserted.
- **Test Case 24: Custom JAL with positive immediate [JAL custom]**
Test a custom JAL instruction with a positive immediate (with instr[31] = 0) to verify proper immediate generation.
- **Test Case 25: Custom JAL with negative immediate [JAL custom]**
Test a custom JAL instruction with a negative immediate (with instr[31] = 1).
- **Test Case 26: Custom JALR with positive immediate [JALR custom]**
Test a custom JALR instruction with a positive immediate (with instr[31] = 0).
- **Test Case 27: Custom JALR with negative immediate [JALR custom]**
Test a custom JALR instruction with a negative immediate (with instr[31] = 1).
- **Test Case 28: Custom BEQ with positive offset [BEQ custom]**
Test a custom BEQ instruction with a positive offset (with instr[31] = 0) to verify correct prediction.
- **Test Case 29: Custom BEQ with negative offset [BEQ custom]**
Test a custom BEQ instruction with a negative offset (with instr[31] = 1).
- **Test Case 30: Custom Compressed Jump with varied immediate [CJ custom]**
Test a custom compressed jump instruction (CJ) with varied immediate fields (using encoding 3'b101).
- **Test Case 31: Custom Compressed Branch taken [CB custom]**
Test a custom compressed branch instruction (CB) with encoding 3'b110 and bit12 = 1, expecting the branch to be taken.
- **Test Case 32: Custom Compressed Branch not taken [CB custom]**
Test a custom compressed branch instruction (CB) with encoding 3'b110 and bit12 = 0, expecting the branch not to be taken.
- **Test Case 33: JALR with large register operand**
Test a JALR instruction with a large register operand to exercise potential arithmetic overflow in immediate addition.
- **Test Case 34: Default non‐branch (pattern with lower 2 bits ≠ 01)**
Apply a default instruction pattern where the lower two bits are not 01, confirming non‑branch operation.
- **Test Case 35: JALR with nonzero register and valid false**
Test a JALR instruction with a nonzero register operand but with fetch_valid_i deasserted, ensuring no prediction is produced.
- **Test Case 36: Default case with non‑matching compressed encoding**
Apply an instruction with lower 2 bits equal to 01 and bits [15:13] that do not match any CJ or CB encoding, thereby exercising the default branch in the case statement.
- **Test Case 37: JALR with register operand causing potential overflow**
Test a JALR instruction with a register operand that may cause arithmetic overflow during the immediate addition.
- **Test Case 38: JALR with positive offset and register causing overflow**
Test a JALR instruction with a positive offset and a register value that leads to overflow in addition.
- **Test Case 39: Custom JAL with varied immediate fields**
Test a custom JAL instruction specifically constructed to exercise the full concatenation of the JAL immediate fields.
- **Test Case 40: JALR with negative register operand**
Test a JALR instruction with a negative (two’s complement) register operand to further verify the immediate addition in JALR.
- **Test Case 41: BEQ with valid false**
Apply a BEQ instruction with fetch_valid_i deasserted to ensure that even a branch instruction is suppressed.
- **Test Case 42: Compressed Branch with valid false**
Apply a compressed branch instruction (CB) with fetch_valid_i deasserted, ensuring no branch prediction is produced.
- **Test Case 43: Default branch (non‑matching compressed encoding)**
Test an instruction with lower 2 bits equal to 01 and bits [15:13] equal to 000—which does not match any CJ or CB encoding—ensuring that the default branch in the case statement is exercised.
- **Test Case 44: JALR with minimal nonzero register operand**
Test a JALR instruction with a minimal nonzero register operand to confirm proper handling of small register values.
- **Test Case 45: Compressed Jump taken (C.J) with negative offset [C.J]**
Test a compressed jump instruction with encoding 3'b101 and bit12 = 1, forcing a negative immediate for a backward jump.
- **Test Case 46: Custom Compressed Branch with unique immediate fields**
Test a custom compressed branch (CB) instruction with unique immediate field settings to exercise additional bit slices in CB decoding.
- **Test Case 47: Custom Compressed Jump with unique immediate fields**
Test a custom compressed jump (CJ) instruction with unique immediate field values to cover remaining combinational logic in CJ decoding.
- **Test Case 48: Custom Compressed Jump with unique immediate fields (CJ)**
Test a custom compressed jump (CJ) instruction—crafted from a 16‐bit pattern (0x2D6D extended to 32 bits)—that specifically sets the lower 2 bits to 01, bits [15:13] to 001, and forces distinct values in bits [12], [11], [10:9], [8], and the lower nibble.
## Module Functionality:
#### Combinational Logic
- `Immediate Extraction`: The immediate branches and jumps are extracted from the instruction, with an appropriate sign extension based on the instruction type.
- `Instruction Type Decoding`: Decodes whether the instruction is an uncompressed branch (instr_b), an uncompressed jump (instr_j), a compressed branch (instr_cb), or a compressed jump (instr_cj) based on opcode and bit patterns.
- `Target Address Calculation`: Determines the branch offset and computes the target PC for the predicted branch or jump.
#### Branch Prediction:
- `Uncompressed Branch/Jump Detection`: Detection of uncompressed instructions (JAL, JALR, BXXX) uses opcode
matching to identify the instruction type.
- `Compressed Branch/Jump Detection`: Compressed branch/jump instructions (C.J, C.JAL, C.BEQZ, C.BNEZ) are provided
in their 32-bit uncompressed form. This module directly uses opcodes and fields from the uncompressed equivalent
to determine the offset and perform the prediction.
- `Offset-Based Prediction ': Branches are predicted as taken if the offset is negative. These predictions are assigned to
the signal `instr_b_taken`.
#### Branch or Jump Prediction:
- For jumps (`instr_j`, `instr_cj`), the module always predicts the instruction as taken.
- For branches, the module uses the `instr_b_taken` signal to decide.
#### Output Prediction Logic:
- `predict_branch_taken_o` is asserted(active-high) if the instruction is predicted to be taken.
- `predict_branch_pc_o` is calculated by adding `fetch_pc_i` to `branch_imm`, giving the predicted target address. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | static_branch_predict | uut | [
{
"name": "static_branch_predict.sv",
"content": "module static_branch_predict (\n \n // Instruction from fetch stage\n input logic [31:0] fetch_rdata_i,\n input logic [31:0] fetch_pc_i,\n input logic [31:0] register_addr_i,\n input logic fetch_valid_i,\n\n // Prediction for supplied instr... | [] |
cvdp_copilot_apb_dsp_op_0006 | medium | Non-Agentic | Create a SystemVerilog test bench for a module named `apb_dsp_op`. The test bench should systematically generate input vectors, apply them to the design under test (DUT), and aim to achieve 100% coverage.
---
## Instantiation
Name the instance of the RTL as **apb_dsp_op_dut**.
## **RTL Interface and Parameters**
| Signal | Width | Samples | In/Out | Description |
|------------|-------|---------|--------|------------------------------------------|
| clk_dsp | 1 | 1 | Input | Faster clock of 500 MHz to DSP operation |
| en_clk_dsp | 1 | 1 | Input | Enable faster DSP clock |
| PCLK | 1 | 1 | Input | APB clock of 50 MHz |
| PRESETn | 1 | 1 | Input | Active low asynchronous APB Reset |
| PADDR | 6 | 1 | Input | APB address |
| PWRITE | 1 | 1 | Input | Write/Read enable |
| PWDATA | 32 | 1 | Input | Write data |
| PSEL | 1 | 1 | Input | DSP selector |
| PENABLE | 1 | 1 | Input | APB enable |
| PRDATA | 32 | 1 | Output | Read data |
| PREADY | 1 | 1 | Output | Ready signal |
| PSLVERR | 1 | 1 | Output | Error signal |
### Parameters
- **ADDR_WIDTH**: Width of the address (6 bits).
- **DATA_WIDTH**: Width of the data (32 bits).
---
### Functional Behavior
**Internal Blocks**
1. **Control Unit**:
- Is responsible for controlling the APB interface, internal registers, SRAM operations and DSP behavior.
2. **DSP Processing**:
- Can operate with the APB interface clock or with an alternative clock 10 times higher and performs the following operation: O = A * B + C.
3. **SRAM Memory**:
- Has 64 addresses of 32 bits each.
### Register Bank
| Register | Address | Default Value | Permission | Description |
|----------------|---------|---------------|------------|----------------------------------------------------------|
| REG_OPERAND_A | 0x00 | 32'h0 | W/R | Holds the SRAM address to read the value for operand A |
| REG_OPERAND_B | 0x01 | 32'h0 | W/R | Holds the SRAM address to read the value for operand B |
| REG_OPERAND_C | 0x02 | 32'h0 | W/R | Holds the SRAM address to read the value for operand C |
| REG_OPERAND_O | 0x03 | 32'h0 | W/R | Holds the SRAM address to write the value for operand O |
| REG_CONTROL | 0x04 | 32'h0 | W/R | Holds the value equivalent to the operation control mode |
| REG_WDATA_SRAM | 0x05 | 32'h0 | W/R | Holds the data to be written to SRAM |
| REG_ADDR_SRAM | 0x06 | 32'h0 | W/R | Holds the address to be read or written to SRAM |
### Control Modes
The module's operation has control modes configured according to the value in the internal register ```reg_control```. The operating modes are described below:
- 32'd1: Enables writing to SRAM.
- 32'd2: Enables reading from SRAM.
- 32'd3: Enables reading the A operand.
- 32'd4: Enables reading the B operand.
- 32'd5: Enables reading the C operand.
- 32'd6: Enables writing the O operand.
- Other values: Only performs write and read operations on internal registers.
---
### TB Implementation Notes
1. **APB Interface**
Implement simple APB driver tasks that does the following:
- Drives PADDR, PWDATA, PWRITE when PSEL is asserted.
- Asserts PENABLE for the second phase of the transfer.
- Ensure the testbench stimulates correct read data at the right cycle.
- Ensure the testbench stimulates out-of-range access.
2. **SRAM Operations**
Implement simple SRAM driver tasks configured by the APB registers:
- Ensure the testbench stimulates correct read data at the right cycle.
- Ensure the testbench stimulates out-of-range access.
- Wait for clock synchronization after writing to SRAM.
- Waiting for multiple PCLK cycles after SRAM requests.
3. **DSP Processing**
The testbench ensures proper synchronization between PCLK and clk_dsp by:
- Waiting for multiple PCLK cycles after DSP control registers are set.
- Introducing additional @(posedge PCLK); waits before reading computed values.
- Set different address values for REG_OPERAND_A, REG_OPERAND_B, REG_OPERAND_C, and REG_OPERAND_O before DSP execution.
4. **Invalid Transactions**
The testbench ensures testing of invalid transactions by:
- Creating a task for accessing invalid APB register addresses.
- Creating a task for operating the SRAM at invalid addresses.
- Creating a task for performing DSP operations using an invalid address.
---
### Stimulus Generation
The testbench writes to the following APB registers before initiating DSP operations:
REG_OPERAND_A (0x00): Stores operand A address.
REG_OPERAND_B (0x01): Stores operand B address.
REG_OPERAND_C (0x02): Stores operand C address.
REG_OPERAND_O (0x03): Stores operand O (result) address.
REG_CONTROL (0x04): Triggers DSP operations and sets control modes.
REG_WDATA_SRAM (0x05): Writes a value to SRAM.
REG_ADDR_SRAM (0x06): Sets the SRAM address for reads and writes.
1. **Basic scripts:**
- Write to control registers.
- Write to SRAM address & data registers.
- Trigger DSP operation.
- Read back final result.
2. **Invalid Address Stimulus:**
The test bench stimulates invalid address by:
- Writing and reading from an invalid APB register address.
- Writing and reading from an invalid SRAM address.
- Performing a DSP operation with an invalid REG_OPERAND_O address.
3. **Signals Stimulus:**
- Randomize signals when it makes sense.
- Randomize valid and invalid stimuli across different tasks.
- Wait for PCLK rising edge after reset deassertion.
- Wait for CDC synchronization (insert some delay or additional posedge clocks commands in the test). | [
{
"inst_name": "apb_dsp_op_dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | apb_dsp_op | apb_dsp_op_dut | [
{
"name": "apb_dsp_op.sv",
"content": "// APB DSP Operation Module\nmodule apb_dsp_op #(\n parameter ADDR_WIDTH = 'd8,\n parameter DATA_WIDTH = 'd32\n) (\n input logic clk_dsp, // Faster clock to DSP operation\n input logic en_clk_dsp, // Enable DSP operati... | [] |
cvdp_copilot_Serial_Line_Converter_0006 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `serial_line_code_converter_tb`. The testbench must instantiate the `serial_line_code_converter` RTL module and provide input stimulus to validate its functionality. This module implements various serial line coding techniques. The testbench should include different input scenarios, such as different encoding schemes, edge cases, and invalid input handling.
---
## Description
The serial_line_code_converter module is a Verilog-based design that converts serial input data into different encoding formats based on the selected mode. The module utilizes clock division, edge detection, and various encoding techniques to modify the serial input and produce the corresponding encoded serial output.
### Encoding Implementations
1. **NRZ (Non-Return-to-Zero)**: Direct pass-through of `serial_in`.
2. **RZ (Return-to-Zero)**: Outputs high only during the first half of the clock cycle when `serial_in` is high.
3. **Differential Encoding**: Outputs the XOR of the current and previous serial input.
4. **Inverted NRZ**: Outputs the inverted value of `serial_in`.
5. **NRZ with Alternating Bit Inversion**: Inverts every alternate bit of `serial_in`.
6. **Parity Bit Output (Odd Parity)**: Generates an odd parity bit based on the serial input.
7. **Scrambled NRZ**: XORs `serial_in` with the least significant bit of the clock counter for scrambling.
8. **Edge-Triggered NRZ**: Detects rising edges of `serial_in` and outputs accordingly.
### Parameters
- **`CLK_DIV`**: Specifies the clock divider for generating clk_pulse. The default value is 16. It must be a positive integer greater than or equal to 2.
### Inputs:
- **clk**: System clock signal. The design operates synchronously with the rising edge of `clk`.
- **reset_n**: Active-low asynchronous reset signal. When asserted low, it resets all internal states and outputs.
- **serial_in**: 1-bit Input signal carrying the serial data stream to be encoded according to the selected mode.
- **mode [2:0]**: A 3-bit input that determines the encoding mode. Possible values:
- `000`: NRZ (Non-Return-to-Zero).
- `001`: RZ (Return-to-Zero).
- `010`: Differential Encoding.
- `011`: Inverted NRZ.
- `100`: NRZ with Alternating Bit Inversion.
- `101`: Parity Bit Output (Odd Parity).
- `110`: Scrambled NRZ.
- `111`: Edge-Triggered NRZ.
### Outputs:
- **serial_out**: Encoded 1-bit output signal. The encoding applied to `serial_in` is determined by the value of the `mode` input. The output updates on every clock cycle based on the selected encoding method.
---
## Testbench Setup
### Clock Generation:
- Generate a clock with a period of 10ns using an `always` block.
### Reset Signal:
- Apply an active-low reset signal at the beginning of the simulation to initialize the DUT.
### Signal Initialization:
- Initialize all testbench signals, including registers and tracking signals for the DUT behavior.
### Feature Mode Identification:
- Maintain an array of strings to define and identify the different encoding techniques implemented in the DUT.
### DUT Instantiation:
- Create an instance of the `serial_line_code_converter` module with appropriate connections for inputs and outputs.
---
## Behavioral Logic
### Clock Division:
- Simulate clock division logic in the testbench to mimic DUT timing for certain modes like RZ.
### Previous State Tracking:
- Track previous input values and states to validate encoding techniques like Differential and Edge-Triggered NRZ.
### Special Mode Handling:
- Implement specific logic for modes such as Alternate Inversion, Parity-Added, and Scrambled NRZ.
---
## Input Generation
### Stimulus Generation:
- Randomly generate serial input values (`serial_in`) for each encoding mode.
- Iterate through all 8 modes, applying input stimuli and observing DUT behavior.
---
## Waveform Analysis
- Generate a VCD file (`serial_line_code_converter.vcd`) to enable waveform analysis for debugging and verification.
---
## Test Scenarios
### Test All Modes:
- Test all 8 encoding modes in sequence.
- For each mode, generate multiple input patterns.
### Edge Case Validation:
- Generate the inputs for edge cases such as alternating inputs, random noise, and reset behavior.
### Partial Test Stimulus Generator Code :
```verilog
module serial_line_code_converter_tb;
parameter CLK_DIV = 6; // Clock division parameter for timing
// Testbench signals
logic clk, reset_n, serial_in, serial_out;
logic [2:0] mode;
// Tracking signals to mimic DUT behavior
logic [3:0] tb_counter;
logic tb_clk_pulse, tb_prev_serial_in, tb_alt_invert_state, tb_parity_out, tb_prev_value;
// Instantiate the Device Under Test
serial_line_code_converter #(CLK_DIV) dut (
.clk(clk),
.reset_n(reset_n),
.serial_in(serial_in),
.mode(mode),
.serial_out(serial_out)
);
// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Clock period of 10ns
end
// Initialize signals
initial begin
tb_counter = 0;
tb_clk_pulse = 0;
tb_prev_serial_in = 0;
tb_prev_value = 0;
tb_alt_invert_state = 0;
tb_parity_out = 0;
reset_n = 0;
serial_in = 0;
mode = 3'b000;
// Apply reset
@(negedge clk) reset_n = 1;
@(posedge clk);
end
// Insert the code for the remaining test stimulus here
endmodule
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | serial_line_code_converter | dut | [
{
"name": "serial_line_code_converter.sv",
"content": "module serial_line_code_converter #(parameter CLK_DIV = 16)(\n input logic clk, // System clock\n input logic reset_n, // Active-low reset\n input logic serial_in, // Serial input signal\n input logic [2:0] mode... | [] |
cvdp_copilot_write_through_data_direct_mapped_cache_0001 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_ddm_cache`.The testbench must instantiate the `ddm_cache` RTL module and provide input stimulus for it, focusing exclusively on generating comprehensive test vectors rather than building a full testbench. The data cache handles read and write operations from the CPU, along with memory access operations. The module supports both cached memory accesses and uncached I/O port accesses.
## Module Interface
## 1. Inputs:
- `clk(1-bit)`: Clock signal. The module operates on the rising edge of `clk`. It synchronizes the operations within the cache logic.
- `rst_n(1-bit)`: 1-bit asynchronous, active-low reset signal. This is triggered on a negedge (falling edge) of the reset signal. When rst_n is asserted (`rst_n` = 0), all the cache locations are invalidated
- `cpu_addr (32-bit,[31:0])`: A 32-bit input representing the memory address issued by the CPU for a read or write operation. This address is used by the cache to determine if a cache hit or miss occurs.
- `cpu_dout (32-bit,[31:0])`: A 32-bit input that carries data emitted by the CPU when writing to memory.
- `cpu_strobe(1-bit)`: A ACTIVE HIGH signal indicating that the CPU wants to perform a read or write operation.
- `cpu_rw:(1-bit)` A control signal indicating the type of operation to be performed by the CPU. cpu_rw = 1 represents a memory write operation, while cpu_rw = 0 represents a memory read operation.
- `uncached(1-bit)`: A control signal where uncached = 1 indicates that the operation is accessing an uncached I/O port (instead of memory). When uncached = 0, a regular memory operation is performed.
- `mem_dout(32-bit, [31:0])`: A 32-bit input that carries data from memory. This data is provided to the cache when there is a cache miss and is forwarded to the CPU if it is a read operation.
- `mem_ready(1-bit)`: A signal indicating that memory is ready with the data to be provided to the cache
## 2. Outputs:
- `cpu_din (32-bit, [31:0])`: A 32-bit output that carries data to the CPU during a read operation. This can either be data from the cache or from memory in the event of a cache miss.
- `mem_din(32-bit, [31:0])`: A 32-bit output carrying data from the CPU to memory when via cache during a write operation
- `cpu_ready(1-bit)`: A signal indication from the cache that data is ready for the CPU to be read.
- `mem_strobe(1-bit)`: A signal that indicates that the memory is going to be accessed by the cache for a read or write operation
- `mem_rw`: The read/write control signal for memory. It reflects the cpu_rw signal, indicating whether the operation is a read (0) or write (1) to memory.
- `mem_addr(32-bit ,[31:0])`: A 32-bit output representing the memory address sent to the memory during the read/write operation from the cache.
- `cache_hit(1-bit)` - A ACTIVE HIGH signal indicating memory location is available in Cache.
- `cache_miss(1-bit)` - A ACTIVE HIGH signal indicating memory location is not available in Cache.
- `d_data_out(32-bit,[31:0])` - Data at a particular index(location) of the cache.
## Instantiation :
The testbench instantiates the `ddm_cache` module as dut and connects the signals between the module and the testbench. Each input and output from the DUT is connected to its corresponding signal in the testbench.
## Input Generation and Validation:
- Clock Generation: The clock signal `clk` is generated using an always block that toggles the clock every 5 time units.
- Reset: The reset signal `rst_n` is asserted at the beginning of the simulation to ensure the cache is initialized in a known state. After a short period (10 time units), the reset is deasserted.
- Stimulus: Several test cases are applied to simulate various operations of the cache. These test cases cover a range of scenarios such as cache misses, cache writes, and uncached accesses. For each case, the relevant signals (address, data, control signals) are set, followed by a brief wait period to allow the DUT to respond.
- Test Case 1: A cache read miss occurs when the CPU accesses address 0x00000000. The memory provides data (0x11111111), and the CPU reads this data from memory after the cache miss.
- Test Case 2: A cache write occurs when the CPU accesses address 0x00000004 and writes data (0xAABBCCDD) into the cache.
- Test Case 3: A cache read hit occurs when the CPU accesses address 0x00000000. The cache provides the previously cached data (0x11111111) without needing to access memory.
- Test Case 4: A cache write and read after reset occur when the CPU writes to address 0x00000010 and then reads the data back from the cache after a reset.
- Test Case 5: An edge case occurs when the CPU writes to address 0x00000014 with two different values (0xDEADBEEF and 0xFACEFEED), followed by a read operation. The cache should return the most recent value (0xFACEFEED).
- Test Case 6: A cache miss and cache write with different memory delays occur when the CPU performs a write operation at address 0x00000018 while memory readiness (`mem_ready`) changes. The cache should handle these delays properly.
- Test Case 7: An uncached IO port access occurs when the CPU writes to IO port address 0xF0000000. This access bypasses the cache and directly interacts with the IO port.
- Test Case 8: Cache read and write operations with randomized addresses occur when the CPU performs random read and write operations. The cache should handle these operations correctly.
- Test Case 9: A cache invalidation occurs when the CPU writes data (0xDEADBEAF) to address 0x00000020, and then performs a read, resulting in a cache miss. The cache fetches new data (0xBBBBBBBB) from memory.
- Test Case 10: Boundary address tests occur when the CPU accesses the first (0x00000000) and last (0xFFFFFFFC) cacheable addresses. These boundary cases are tested to ensure correct cache handling at the limits of the address space.
- Test Case 11: Multiple cache misses and hits in sequence occur when the CPU performs operations at sequential addresses (0x00000024, 0x00000028). The cache should handle the misses and hits correctly.
- Test Case 12: A memory read with a cache miss and delayed memory readiness occurs when the CPU reads from address 0x00000050. The memory is initially not ready (`mem_ready` = 0), causing a delay before the CPU can read the data after the cache miss. The memory readiness flag is toggled to allow the read after a short delay.
## Module Functionality:
- Asynchronous Reset: When `rst_n` is asserted (`rst_n = 0`), all cache locations are invalidated This ensures the cache is reset to a known state.
- Cache Operation: On each rising edge of clk, the cache processes the incoming requests from the CPU:
- Cache Read: If the CPU issues a read request and the address is present in the cache (`cache hit`), the corresponding data is returned to the CPU without accessing memory.
- Cache Miss: If the CPU accesses a memory address that is not cached (`cache miss`), the cache issues a memory read request to the memory. Once the data is retrieved from memory, it is stored in the cache for future accesses.
- Cache Write: If the CPU writes data, the cache writes the data into the cache entry corresponding to the address. If the operation is not cached (i.e., `uncached = 1`), the data is written directly to memory instead of the cache.
- Cache Management: Each cache entry has a valid bit, a tag, and data. The tag is used to determine whether a cache entry matches the requested address, and the valid bit indicates whether the entry contains valid data. When a write operation occurs, the corresponding cache entry is updated with the new tag and data.
- Memory Read/Write: If a cache miss occurs, the module performs a memory read operation (if `cpu_rw = 0`), waits for the memory to become ready (`mem_ready`), and then forwards the data to the CPU. Similarly, for write operations (`cpu_rw = 1`), the data is written to memory after it is cached.
- Cache Write Signal: The cache write signal (`cache_write`) is asserted when a write operation occurs, either because the CPU is performing a write or because the cache is updating its contents after a cache miss.
**Partial Test Stimulus Generator Code :**
``` verilog
module tb_ddm_cache;
logic clk;
logic rst_n;
logic [31:0] cpu_addr;
logic [31:0] cpu_dout;
logic cpu_strobe;
logic cpu_rw;
logic uncached;
logic [31:0] mem_dout;
logic mem_ready;
logic [31:0] cpu_din;
logic [31:0] mem_din;
logic cpu_ready;
logic mem_strobe;
logic mem_rw;
logic [31:0] mem_addr;
logic cache_hit;
logic cache_miss;
logic [31:0] d_data_dout;
ddm_cache dut (
.clk(clk),
.rst_n(rst_n),
.cpu_addr(cpu_addr),
.cpu_dout(cpu_dout),
.cpu_strobe(cpu_strobe),
.cpu_rw(cpu_rw),
.uncached(uncached),
.mem_dout(mem_dout),
.mem_ready(mem_ready),
.cpu_din(cpu_din),
.mem_din(mem_din),
.cpu_ready(cpu_ready),
.mem_strobe(mem_strobe),
.mem_rw(mem_rw),
.mem_addr(mem_addr),
.cache_hit(cache_hit),
.cache_miss(cache_miss),
.d_data_dout(d_data_dout)
);
always begin
#5 clk = ~clk;
end
initial begin
clk = 0;
rst_n = 0;
cpu_addr = 32'h00000000;
cpu_dout = 32'h12345678;
cpu_strobe = 0;
cpu_rw = 0;
uncached = 0;
mem_dout = 32'h00000000;
mem_ready = 1;
#10 rst_n = 1;
#10;
$display("Test case 1: Cache Read Miss (CPU address 0x00000000)");
cpu_addr = 32'h00000000;
cpu_dout = 32'h12345678;
cpu_strobe = 1;
cpu_rw = 0;
uncached = 0;
mem_dout = 32'h11111111;
#10;
cpu_strobe = 0;
#50;
$display("Test case 2: Cache Write (CPU address 0x00000004)");
cpu_addr = 32'h00000004;
cpu_dout = 32'hAABBCCDD;
cpu_strobe = 1;
cpu_rw = 1;
uncached = 0;
#10;
cpu_strobe = 0;
#10;
$display("Test case 3: Cache Read Hit (CPU address 0x00000000, should hit cached data)");
cpu_addr = 32'h00000000;
cpu_strobe = 1;
cpu_rw = 0;
uncached = 0;
#10;
cpu_strobe = 0;
#10;
// Insert the code for the remaining test cases here
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 85
}
] | ddm_cache | dut | [
{
"name": "ddm_cache.sv",
"content": "module ddm_cache (\n input logic clk, // Posedge clock\n input logic rst_n, // Asynchronous Negedge reset\n input logic [31:0] cpu_addr, // Memory address emitted by the CPU\n input logic [31:0] cpu_dout, // Data emitted... | [] |
cvdp_copilot_events_to_apb_0021 | medium | Non-Agentic | Write a SystemVerilog testbench named `tb_apb_controller` that only generates stimuli for an `apb_controller` module. The testbench should generate input stimuli for different operating conditions and sequences, including the handling of multiple simultaneous events (Event A, Event B, and Event C), proper prioritization, and the built-in timeout mechanism.
---
### Module Overview
The `apb_controller` is an Advanced Peripheral Bus (APB) write controller that manages write transactions triggered by three independent events (A, B, and C). Each event carries its 32-bit address and 32-bit data input. The controller follows the APB protocol with a three-phase state machine consisting of **IDLE**, **SETUP**, and **ACCESS** phases. Events are triggered by `select_a_i`, `select_b_i`, and `select_c_i` signals for events A, B, and C respectively. Additionally, it implements a timeout mechanism to prevent indefinite stalling if the peripheral fails to respond within a specified period. it supports multiple event queuing and prioritization, ensuring that events are processed in order while dynamically adjusting their priority based on previous transactions.
---
#### Inputs:
- **`clk`**: System clock. The design is synchronized to the positive edge of this clock.
- **`reset_n`**: Active-low asynchronous reset signal that resets the controller to the `IDLE` state, clears the timeout counter, and sets all registers and outputs to 0.
- **`select_a_i`**: Active-high control signal to initiate a transaction for Event A.
- **`select_b_i`**: Active-high control signal to initiate a transaction for Event B.
- **`select_c_i`**: Active-high control signal to initiate a transaction for Event C.
- **`addr_a_i [31:0]`**: Address input for Event A.
- **`data_a_i [31:0]`**: Data input for Event A.
- **`addr_b_i [31:0]`**: Address input for Event B.
- **`data_b_i [31:0]`**: Data input for Event B.
- **`addr_c_i [31:0]`**: Address input for Event C.
- **`data_c_i [31:0]`**: Data input for Event C.
- **`apb_pready_i`**: Ready signal from the peripheral, active high. It indicates when the peripheral is ready to complete the transaction. The controller checks this signal in the `ACCESS` phase to determine transaction completion.
#### Outputs:
- **`apb_psel_o`**: An active-high signal, asserted during `SETUP`, to select the peripheral for an APB transaction.
- **`apb_penable_o`**: An active-high signal, asserted during the `ACCESS` phase, indicating the transaction is in progress.
- **`apb_pwrite_o`**: An active-high signal indicating a write operation, asserted during the `SETUP` and maintained in the `ACCESS` phase.
- **`apb_paddr_o [31:0]`**: 32-bit address output for the transaction, determined by the selected event's address input (`addr_a_i`, `addr_b_i`, or `addr_c_i`). Defaults to 0 in the `IDLE` state.
- **`apb_pwdata_o [31:0]`**: 32-bit data output for the write operation, based on the selected event's data input (`data_a_i`, `data_b_i`, or `data_c_i`). Defaults to 0 in the `IDLE` state.
### Multiple Simultaneous Behaviour Handling:
#### **1. Event Queuing**
- The module can track multiple simultaneous events (select_a_i, select_b_i, select_c_i) in an event queue.
- Once a transaction for a higher-priority event is granted, it gets the lowest priority if triggered again before the queue is emptied.
#### **2. Event Processing**
- The module processes **one event at a time** from the queue.
- After completing an event's APB transaction, it is removed from the queue and then the module proceeds to the next event.
#### Transaction Flow and Timing:
The transactions follow a three-state flow:
1. **IDLE**:
- If multiple select signals are asserted simultaneously, the controller prioritizes them as `select_a_i` (highest priority), followed by `select_b_i`, and then `select_c_i` (lowest priority).
- Evaluates the event queue to determine the next event to process.
- Transition to the `SETUP` state when an event is available.
- The **IDLE** phase lasts for one clock cycle when the queue is not empty.
- The default state is **IDLE** state, which it enters after a reset and remains in when no transactions are active
2. **SETUP**:
- After the **IDLE** phase, the controller transitions to the **SETUP** phase.
- in the **SETUP** phase the controller asserts `apb_psel_o`, and `apb_pwrite_o` and set up `apb_paddr_o` and `apb_pwdata_o` with the selected address and data.
- In this phase, `apb_penable_o` remains de-asserted.
- The **SETUP** phase lasts for one clock cycle.
3. **ACCESS**:
- After the **SETUP** phase, the controller transitions to the **ACCESS** phase.
- In **ACCESS**, `apb_penable_o` is asserted high to signal that the data transfer is in progress.
- The controller remains in this phase, waiting for `apb_pready_i` from the peripheral to be asserted high.
- In **ACCESS** phase, the signals `apb_psel_o`, `apb_pwrite_o`, `apb_paddr_o`, and `apb_pwdata_o` remains stable.
- **Write Transfer with Wait**: If `apb_pready_i` is delayed, the controller stays in **ACCESS** until `apb_pready_i` goes high.
- **Write Transfer without Wait**: If `apb_pready_i` goes high in the same clock cycle that the controller enters the **ACCESS** phase, the controller completes the transaction within the same cycle.
- **Timeout Mechanism**:
- In the **ACCESS** phase, a 4-bit timeout counter increments each clock cycle if `apb_pready_i` remains low.
- If `apb_pready_i` is not asserted within 15 cycles after entering the **ACCESS** state, the timeout counter resets the controller to the **IDLE** state and sets all outputs to 0 at the next positive edge, effectively aborting the transaction and preventing indefinite stalling.
- The timeout counter resets to zero after a successful transaction or when the controller returns to the **IDLE** state.
- After a successful transaction (when `apb_pready_i` is asserted), the controller returns to the **IDLE** state, with both `apb_psel_o` and `apb_penable_o` getting deasserted.
- After returning to the IDLE state after the APB transaction of a specific event gets completed (timeout or assertion of `apb_pready_i` to 1) the design processes the next event in the queue in case of multiple simultaneous events and the queue is not empty. If the queue is empty, a new transaction can only start by asserting a select signal (`select_a_i`, `select_b_i`, or `select_c_i`) while both `apb_psel_o` and `apb_penable_o` are low.
### Total Latency for the Transaction:
- **Minimum Latency**: From the triggering of an event when the queue is empty, the latency from the event assertion to the `apb_psel_o` assertion is **3 clock cycles**. (1 cycle each for latching the event signal, updating the queue, and asserting `apb_psel_o` for the triggered event).
- However, when the queue is not empty, the latency for the `apb_psel_o` assertion for the next event to be processed is **1 clock cycle** after the completion of the first transaction (after de-assertion of all output signals).
- When an event is retriggered after the completion of its previous APB transaction while the last event in the queue has just started, the latency for asserting `apb_psel_o` for the next event to be processed is 2. This is because the event signal is latched previously (at trigger) and only updating the queue and asserting `apb_psel_o` is required.
- Signals `apb_pwrite_o`, `apb_paddr_o` and `apb_pwdata_o` are asserted in **SETUP** phase along with `apb_psel_o` and thus have similar latency as `apb_psel_o`.
- Signal `apb_penable_o` takes one additional clock cycle than `apb_psel_o` as ` apb_penable_o` is asserted one clock cycle later (in the **ACCESS** state).
- When the event queue is not empty, each STATE requires one cycle except if `apb_pready_i` is delayed, additional cycles are spent in the `ACCESS` state until the peripheral is ready or a timeout occurs
- After an APB Transaction is completed, it takes 1 cycle to de-assert signals and to return to `IDLE`.
### Constraints:
- Assume that event signals `select_a_i`, `select_b_i`, and `select_c_i` are pulse signals high for one clock cycle and are synchronous to the clock.
- Assume that input data and addresses will be stable inputs when the events are triggered.
- If multiple events are triggered simultaneously, the highest-priority event will be processed first, followed by the other events based on their priority.
- If any event (`select_a_i`, `select_b_i`, `select_c_i`) is asserted, the same input will not reassert until at least one clock cycle after its previous APB transaction is completed. Once the previous event from a specific input is completed, the next event from the same input can trigger at any time and will be added to the queue for execution after all previously queued events.
---
### Stimulus Generation Requirements:
Instantiate the `apb_controller` module as the `dut` with all required ports connected. The testbench must cover all possible scenarios to achieve 100% coverage.
#### 1. Clock and Reset:
- Generate a continuous `clk` signal.
- Drive an active-low asynchronous reset signal to initialize the `dut` in the **IDLE** state.
#### 2. Event Triggering and Priority:
- Create pulse stimuli for the event select inputs (`select_a_i`, `select_b_i`, and `select_c_i`) that are one clock cycle wide.
- Generate random stimuli for different scenarios, including simultaneous assertion of multiple event signals (for internal prioritization) and isolated single-event activations (for one event at a time).
- Generate stimuli for the 32-bit address and data signals for each event (`addr_a_i`, `data_a_i`, `addr_b_i`, `data_b_i`, `addr_c_i`, and `data_c_i`) with fixed or varying values.
#### 3. APB Peripheral Ready Signal:
- Generate stimuli of the `apb_pready_i` input for:
- When `apb_pready_i` is asserted quickly (immediate response) to mimic minimum transaction latency.
- When `apb_pready_i` is delayed, causing the `dut` to remain longer in the **ACCESS** state and eventually leading to the timeout mechanism.
---
**Deliverables:**
A SystemVerilog testbench that generates varied input stimuli for the `apb_controller` module according to the above specifications and allows different corner cases for extended testing scenarios. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | apb_controller | dut | [
{
"name": "apb_controller.sv",
"content": "module apb_controller(\n input logic clk, // Clock signal\n input logic reset_n, // Active low asynchronous reset signal\n input logic select_a_i, // Select signal for event A\n input logic ... | [] |
cvdp_copilot_afi_ptr_0004 | medium | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `cmprs_afi_mux_ptr_tb` module is responsible for managing pointer updates for multiple channels in a memory compression system. It handles resetting pointers, arbitrating between competing channels, and updating pointers based on increments while ensuring correct rollover behavior.
## **Design Specification**
The **cmprs_afi_mux_ptr** module is responsible for managing pointer updates for multiple channels in a memory compression system. It handles resetting pointers, arbitrating between competing channels, and updating pointers based on increments while ensuring correct rollover behavior.
The testbench **cmprs_afi_mux_ptr_tb** must generate stimuli to validate the FSM transitions, pointer updates, reset behavior, and interaction with the busy signal for arbitration.
### **Inputs:**
- `hclk` (1-bit): **Clock signal**, used for synchronous operations.
- `reset` (1-bit): **Active-high reset**, initializes the system state.
- `sa_len_di` (27-bit): **Write data** for the `sa_len_ram`.
- `sa_len_wa` (3-bit): **Write address** for the `sa_len_ram`.
- `sa_len_we` (1-bit): **Write enable** for `sa_len_ram`.
- `en` (1-bit): **Enable signal**, determines whether the module is active.
- `reset_pointers` (4-bit): **Per-channel reset** control for pointers.
- `pre_busy_w` (1-bit): **Indicates if a write operation is occurring**.
- `pre_winner_channel` (2-bit): **Channel ID that won arbitration**.
- `need_to_bother` (1-bit): **Indicates whether an update is required**.
- `chunk_inc_want_m1` (2-bit): **Increment request value (minus one)**.
- `last_burst_in_frame` (1-bit): **Indicates the last burst in a frame**.
- `busy` (4-bit): **Busy flags for different channels**.
### **Outputs:**
- `ptr_resetting` (1-bit): **Indicates if pointers are resetting**.
- `chunk_addr` (27-bit): **Computed chunk address**.
- `max_wlen` (3-bit): **Maximum write length per channel**.
## **FSM States & Behavior**
- **IDLE**: Waits for reset pointers or arbitration start (`pre_busy_w`).
- **RESETTING**: Resets the requested channel pointers to zero.
- **ARBITRATION**: Determines if a pointer update is needed (`need_to_bother`).
- **UPDATE**: Updates the selected pointer, handling overflow conditions.
---
## **Testbench Requirements**
### **Instantiation**
- Module Instance: The module **cmprs_afi_mux_ptr** should be instantiated as **uut**, with all input and output signals connected for testing.
### **Input Generation**
#### **1. sa_len_ram Writing**
- The testbench must write values to all `sa_len_ram` entries.
- Verify that each entry is correctly stored.
#### **2. Pointer Resetting**
- The testbench should initiate pointer resets (`reset_pointers`).
- Verify that only the selected pointers are reset.
#### **3. Arbitration and Pointer Increment**
- Set `pre_busy_w` to initiate arbitration.
- Assign a channel (`pre_winner_channel`) and increment (`chunk_inc_want_m1`).
- Verify that the pointer updates correctly.
#### **4. Rollover Condition Testing**
- Initialize a pointer close to its maximum value.
- Assign an increment that causes rollover.
- Verify that the pointer wraps around correctly.
#### **5. FSM Transition Verification**
- Ensure that transitions between **IDLE**, **RESETTING**, **ARBITRATION**, and **UPDATE** follow expected conditions.
- Confirm that after `pre_busy_w` is deasserted, the FSM returns to **IDLE**.
#### **6. Reset During Active Update**
- Apply `reset` while in the **UPDATE** state.
- Verify that all registers return to their default values.
---
## **Control Signal Handling**
- The testbench must ensure that inputs such as `pre_busy_w`, `pre_winner_channel`, `chunk_inc_want_m1`, and `reset_pointers` are asserted at the correct moments.
- The FSM must be given enough cycles to transition and perform pointer updates before moving to the next test case.
This testbench will ensure the **cmprs_afi_mux_ptr** module functions correctly under various conditions, including normal operation, pointer resets, and overflow scenarios. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | cmprs_afi_mux_ptr | uut | [
{
"name": "cmprs_afi_mux_ptr.sv",
"content": "`timescale 1ns / 1ps\n\nmodule cmprs_afi_mux_ptr(\n input hclk, // Clock signal\n input reset, // Synchronous reset input\n input [26:0] sa_len_di, /... | [] |
cvdp_agentic_dual_port_memory_0012 | medium | Agentic | The `dual_port_memory` module's `specification.md` is in the `docs` folder. Write a SystemVerilog testbench `tb_dual_port_memory.sv` in the `verif` directory to generate **only stimulus** for the `dual_port_memory` module to achieve **maximum coverage** of the DUT.
---
### Include the Following:
#### **1. Module Instance**
- Instantiate the `dual_port_memory` module as `dut`.
- Connect all input and output ports for testing.
- Parameters `DATA_WIDTH`, `ECC_WIDTH`, `ADDR_WIDTH`, and `MEM_DEPTH` must be configurable at the top of the testbench.
#### **2. Input Generation**
- The testbench must apply the following test cases to stimulate the DUT:
##### Functional & Stimulus-Based Test Cases:
| **Test #** | **Stimulus Description** |
|------------|-----------------------------------------------------------------------------------------|
| 1 | Write and read from the same address. |
| 2 | Back-to-back sequential writes and reads to multiple addresses. |
| 3 | Sequential read-after-write hazard (write to `i`, read from `i-1`). |
| 4 | Same data (`4'b1111`) to different addresses. |
| 5 | Inject single-bit **data** corruption after a valid write. |
| 6 | Inject single-bit **ECC** corruption while data remains intact. |
| 7 | Write to **minimum (0)** and **maximum (MEM_DEPTH - 1)** addresses. |
| 8 | Write and read **walking 1s** pattern. |
| 9 | Fill the memory with all `0`s and read back to verify. |
| 10 | Write valid data and corrupt ECC on every 4th address. |
| 11 | Simultaneous read and write to the **same** address. |
| 12 | One-hot addressing pattern (e.g., 1, 2, 4, 8...). |
| 13 | Write all possible 4-bit patterns (0 to 15) to the same address. |
| 14 | Invert a value read from memory and write it back to a new address. |
| 15 | Read-modify-write test: read, update, and re-write the value. |
| 16 | Full corruption: invert **data** and **ECC** bits. |
| 17 | Flip each ECC bit individually and verify error detection. |
| 18 | Flip each data bit individually and verify error detection. |
| 19 | Toggle between writing to min and max addresses. |
| 20–36 | Random writes/reads, including even/odd patterns, address gaps, wraparounds, and reuse. |
| 37–45 | Repeating write-read cycles with incrementing data to stress address space. |
#### **3. Computation Period**
- After applying each input (especially `we = 0` for read), wait **until `data_out` and `ecc_error` settle** or a **timeout of 50 clock cycles**, whichever comes first.
- Ensure the testbench never enters an infinite loop while waiting for an ECC response.
#### **4. Monitoring and Tracing**
- Use `$display` to mark the beginning of each test case (e.g., `[Test 5] ECC Error - Data Flip`).
- Use `$monitor` to track changes in key signals:
- `clk`, `rst_n`, `we`, `addr_a`, `addr_b`, `data_in`, `data_out`, and `ecc_error`.
--- | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | dual_port_memory | dut | [
{
"name": "dual_port_memory.sv",
"content": "module dual_port_memory #(\n parameter DATA_WIDTH = 4, // Data width\n parameter ECC_WIDTH = 3, // ECC bits for Hamming(7,4)\n parameter ADDR_WIDTH = 5, // Address width\n parameter MEM_DEPTH = (1 << ADDR_WIDTH)... | [
{
"name": "specification.md",
"content": "## Introduction\n\nThe `tb_dual_port_memory` testbench is designed to verify the functionality and robustness of a **dual-port memory module with ECC (Hamming code)**. The memory module features independent read and write ports (`addr_a`, `addr_b`) and ECC-based err... |
cvdp_copilot_perceptron_0018 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_perceptron_gates` that instantiates the `perceptron_gates` module as the Unit Under Test (UUT). The testbench must include a stimulus generator only that systematically drives various input conditions to achieve a minimum of 80% code and functional coverage for the `perceptron_gates` module. The `perceptron_gates` module implements a microcoded controller to train a perceptron model. The module takes signed 4-bit inputs (`x1` and `x2`), a 4-bit threshold, a 1-bit learning rate, and a 2-bit gate selector to determine the target output based on logical gate operations. It uses a microcode ROM to sequentially execute actions like weight initialization, output computation, target selection, weight/bias updates, and convergence checks. The module outputs the updated weights, bias, perceptron response (`y`), and a stop signal when training converges.
## Design Specification:
The `perceptron_gates` module handles weight initialization, computation of perceptron outputs, target selection based on input indexes, and weight and bias updates. It features a microcoded approach for defining operational states, ensuring flexibility and reusability for perceptron-based learning tasks.
## Interface
## Inputs
- `clk` (1-bit): Positive edge-triggered clock signal for calculating the microcode ROM address.
- `rst_n` (1-bit): Negative edge-triggered reset signal. When ACTIVE LOW, `present_addr` is initialized to `4'd0`.
- `x1`, `x2` (4-bit,[3:0], signed): Perceptron inputs. Can take only Bipolar values [`4'd1`,`-4'd1`]
- `learning_rate` (1-bit): Learning rate for weight and bias updates.
- `threshold` (4-bit,[3:0], signed): Threshold value for response calculation.
- `gate_select` (2-bit,[1:0]): Specifies the gate type for determining target outputs.
## Outputs
- `percep_w1`, `percep_w2` (4-bit, [3:0], signed): Current weights of the perception. Can take Bipolar Values [`4'd1`,`-4'd1`]
- `percep_bias` (4-bit,[3:0], signed): Current bias of the perception.Can take Bipolar Values [`4'd1`,`-4'd1`]
- `present_addr` (4-bit,[3:0]): Current microcode ROM address.
- `stop` (1-bit): Indicates the end of training.
- `input_index` (3-bit,[2:0]): Tracks the current target value selected during an iteration. Can take values from 3'd0 to 3'd3.
- `y_in` (4-bit,[3:0] signed): Computed perception output. Can take Bipolar values [`4'd1`,`-4'd1`]
- `y` (4-bit, [3:0], signed): Perceptron output after applying the threshold.Can take three different values [`4'd1`,`4'd0`,`-4'd1`]
- `prev_percep_wt_1`, `prev_percep_wt_2`, `prev_percep_bias` (4-bit, [3:0], signed): Weights and Bias during a previous iteration. Can take Bipolar values [`4'd1`, `-4'd1`]
**Instantiation** :
The testbench instantiates the `perceptron_gates` module as uut and connects the signals between the module and the testbench. Each input and output from the uut is connected to its corresponding signal in the testbench.
## **Input Generation and Validation**
**Stimulus**:
The testbench continuously drives the clock (`clk`) and applies a reset (`rst_n`). Once out of reset, it goes through two main “training sets,” each one iterating over the four possible gate_select values (00, 01, 10, 11). For each `gate_select`, `target_select` is either 0 or 1 depending on whether it is in the “first training set” or “second training set.” Within each gate configuration, multiple input patterns of `x1` and `x2` (both + 1 and - 1) are driven in sequence to stimulate the `perceptron_gates` module.
## **1. Gate 00 (gate_select = 2’b00) Training**:
The code treats `gate_select` = 2’b00 as an AND-like gate.
**1.Test Case 1 (First Training Set)**:
Control:
- `gate_select` = 2’b00
- `target_select` = 1’b0
- `rst_n` should be asserted (HIGH), meaning the circuit is active.
Inputs:
The sequence for '𝑥1','𝑥2' is given by:
1. (1, 1)
2. (1, –1)
3. (–1, 1)
4. (–1, –1)
5. Repeat with similar pairs to check how weights evolve (e.g., cycling through (1, 1), (1, –1), (–1, 1), (–1, –1) again with different delays).
**2. Test Case 2 (Second Training Set)** :
Control:
- gate_select = 2’b00
- target_select = 1’b1
- A reset (rst_n=0) and re-assertion (rst_n=1) should happen right before starting this second training set.
Inputs:
- After the reset, ‘x1‘, and ‘x2‘ should be driven as a series of + 1 and -1 pairs, but in a slightly different order to verify that the perceptron updates (`weights` and `bias`) can handle new input patterns under the new `target_select` value:
(–1, 1), (1, –1), (–1, –1), (1, 1), etc.
## **2. Gate 01 (gate_select = 2’b01) Training**
The code treats `gate_select` = 2’b00 as an `OR-like gate`.
**1. Test Case 1 (First Training Set)**:
Control:
- `gate_select` = 2’b01
- `target_select` = 1’b0
- `rst_n` should be asserted (HIGH), meaning the circuit is active.
Inputs:
Patterns of (1, 1), (–1, 1), (1, –1), (–1, –1), each separated by delays (#90, #95, etc.).
**2. Test Case 2 (Second Training Set)**:
Control:
- `gate_select` = 2’b01
- `target_select` = 1’b1
Inputs:
Again, multiple +1 and -1 combinations should be applied in sequence after a reset, ensuring that the perceptron’s weights adapt to the new target criterion.
## **3. Gate 10 (`gate_select = 2’b10`) Training**
The code treats `gate_select` = 2’b00 as a `NAND-like Gate`.
**1.Test Case 1 (First Training Set)**:
Control:
- gate_select = 2’b10
- target_select = 1’b0
Inputs:
The testbench should apply (–1, –1), (–1, 1), (1, –1), (1, 1), etc., checking that the `perceptron_gates` module updates correctly.
**2. Test Case 2 (Second Training Set)**:
Control:
- gate_select = 2’b10
- target_select = 1’b1
Inputs:
After another reset, the same style of + 1 and -1 inputs should be repeated, but with `target_select` changed to test the NAND-like behavior.
## **4.Gate 11 (`gate_select = 2’b11`) Training**
The code treats `gate_select` = 2’b00 as a `NOR-like Gate`.
**1. Test Case 1 (First Training Set)**:
Control:
- `gate_select` = 2’b11
- `target_select` = 1’b0
Inputs:
Similar to the other gates, the code should drive (–1, –1), (–1, 1), (1, –1), and (1, 1) in various sequences.
**2. Test Case 2 (Second Training Set)**
Control:
- `gate_select` = 2’b11
- `target_select` = 1’b1
Inputs:
Once reset, the same pattern of inputs should be repeated, but with a different `target_select` to test whether the perceptron properly re-learns the new target.
## **Module Functionality**:
## Submodule Overview
### 1. Gate Target (`gate_target`)
Generates target outputs (`t1`, `t2`, `t3`, `t4`) based on the selected gate type.
- Inputs: `gate_select` (2-bit,[1:0]).
- Outputs : `o_1`, `o_2`, `o_3`, `o_4` (4-bit, [3:0],signed).
- Gates implemented: AND, OR, NAND, and NOR gates.
- `gate_select`:
- `2'b00` : AND Gate ; target values : (`4'd1`,`-4'd1`,`-4'd1`,`-4'd1`)
- `2'b01` : OR Gate ; target values : (`4'd1`, `4'd1`, `4'd1`,`-4'd1`)
- `2'b10` : NAND Gate ; target values : (`4'd1`, `4'd1`, `4'd1`,`-4'd1`)
- `2'b11` : NOR Gate ; target values : (`4'd1`, `-4'd1`, `-4'd1`,`-4'd1`)
### 2. Microcode ROM
- Defines a sequence of 6 micro-instructions, specifying actions such as weight initialization, output computation, target selection, and weight/bias updates.
## Algorithm Steps for Perceptron Learning
- Initialization: All weights, biases, and counters are set to zero.
- Compute Output: Compute `y_in` = `bias` + (`x1` * `w1`) + (`x2` * `w2`) and compare with the threshold to determine `y`.
- Select Target: Based on `gate_select` and` input_index`, pick the desired target value
- Update Weights and Bias: Adjust weights and bias based on the condition (`y` != `target`)
- If the condition is satisfied
- `wt1_update` = `learning_rate` * `x1` * `target`
- `wt2_update` = `learning_rate` * `x2` * `target`
- `bias_update` = `learning_rate` * `target`
- If the condition is not satisfied
- `wt1_update` = 0
- `wt2_update` = 0
- `bias_update` = 0
- The value of current weights and bias is calculated as follows :
- `percep_wt1` = `percep_w1` + `wt1_update`
- `percep_wt2` = `percep_wt2` + `wt2_update`
- `percep_bias` = `percep_bias` + `bias_update`
- Check if the `wt1_update`, `wt2_update` , and `bias_update` values are equal to their previous iteration values. If the condition is satisfied, stop the learning. Otherwise assign the `wt1_update`, `wt2_update`, and `bias_update` values to their previous iteration values and continue learning.
## Control Flow
### Microcoded Actions
- Action 0: Initialize weights and bias to zero.
- Action 1: Compute `y_in` (weighted sum + bias) and `y` (thresholded output).
- Action 2: Select target value based on `input_index `and `gate type`.
- Action 3: Update weights and bias if the perceptron output differs from the target.
- Action 4: Compare current and previous weights and bias to determine convergence.
- Action 5: Finalize updates and prepare for the next epoch.
**An epoch is the time taken to train the perceptron for a given combination of four input values**
## Key Features
- Microcoded Sequencing: Flexible execution of training steps using `microcode ROM`.
- Dynamic Target Selection: Allows gate-based logic outputs for versatile applications.
- Sequential Updates: Tracks and applies weight changes across iterations.
- Convergence Monitoring: Halts training when weights stabilize. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | perceptron_gates | uut | [
{
"name": "perceptron_gates.sv",
"content": "`timescale 1ns/1ps\nmodule perceptron_gates (\n input logic clk,// Posedge clock\n input logic rst_n,// Negedge reset\n input logic signed [3:0] x1, // First Input of the Perceptron\n input logic signed [3:0] x2, // Second Input of the Perceptron\... | [] |
cvdp_agentic_queue_0007 | easy | Agentic | I have a specification for the `queue` module in the `docs` directory (`specification.md`). Write a SystemVerilog testbench `tb_queue.sv` in the `verif` directory to generate a stimulus for the `queue` module.
Include the following in the generated testbench:
---
### 1. **Module Instance:**
- Instantiate the `queue` module as `dut`.
- Set parameters as follows:
- `DEPTH = 4`
- `DBITS = 32`
- `ALMOST_EMPTY_THRESHOLD = 1`
- `ALMOST_FULL_THRESHOLD = 4`
- Connect all input/output signals for functional stimulus testing.
---
### 2. **Input Generation:**
- Provide input sequences that stimulate all interface operations:
- Write-only (`we_i = 1`, `re_i = 0`)
- Read-only (`we_i = 0`, `re_i = 1`)
- Simultaneous read/write (`we_i = 1`, `re_i = 1`)
- Idle (`we_i = 0`, `re_i = 0`)
- Include a reset sequence at the start (`rst_ni` = 0 → 1).
- Include clear signal assertion (`clr_i = 1`) during the test.
- Enable signal `ena_i` must toggle during the test and include disabled cycles (`ena_i = 0`) to cover control FSM "else" branches.
---
### 3. **Coverage Requirements:**
- Exercise all internal RTL blocks, including:
- Pointer updates for all read/write combinations.
- Data shift and insertion logic.
- Programmable `almost_empty_o` and `almost_full_o` thresholds.
- `empty_o` and `full_o` status signal behavior.
- Trigger edge cases such as:
- Overflow condition (`we_i` when queue is full).
- Underflow condition (`re_i` when queue is empty).
- Simultaneous read/write when `queue_wadr == 0`.
- `ena_i == 0` during active clocking.
- Re-asserting reset (`rst_ni`) mid-simulation to exercise reset path. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | queue | dut | [
{
"name": "queue.sv",
"content": "module queue #(\n parameter DEPTH = 4,\n parameter DBITS = 32,\n parameter ALMOST_EMPTY_THRESHOLD = 1,\n parameter ALMOST_FULL_THRESHOLD = 4\n) (\n input logic rst_ni, // async, active-low reset\n input logic ... | [
{
"name": "specs.md",
"content": "# Queue Module Description\n\nThis module implements a parameterized fall-through queue that stores a configurable number of data words. It features a first-word-fall-through behavior where, upon a read, the next valid data element immediately appears at the output. The que... |
cvdp_copilot_binary_to_BCD_0030 | easy | Non-Agentic | Create a testbench for `binary_to_bcd` module, which converts an 8-bit binary input into a 12-bit BCD output using the Double Dabble algorithm, ensuring correct shifting, adjustment, and final conversion while validating that each BCD digit remains within the valid range (0-9). The testbench must have the instantiation of RTL module and generate stimulus for various test conditions.
___
The interface of `binary_to_bcd` RTL module is given below:
**Input:**
- `binary_in` [7:0] [8-Bit]: The binary number to be converted into BCD.
**Output:**
- `bcd_out` [11:0] [12-Bit]: The corresponding BCD output where each 4-bit group represents a decimal digit.
___
### Input Generation and Validation
**Input Generation:**
1. Fixed Test Cases:
- Test a variety of binary inputs, including boundary values, random values, and power-of-two values to validate correct behavior.
- Example test values: `0`, `1`,`9`, `10`, `15`, `45`, `99`, `123`, `200`, `255`.
2. Randomized Testing:
- Generate random binary values within the range `0–255` and compare against a reference function.
3. Edge Cases:
- Minimum input (`binary_in = 0`): BCD output `0000 0000 0000` (0).
- Maximum input (`binary_in = 255`): BCD output `0010 0101 0101` (255).
- Near-boundary conditions (`binary_in` = `9`, `10`, `99`, `100`, `199`) to verify correct BCD adjustments.
___
### Instantiation
Name the instance of RTL as `uut`.
##
### Module Functionality
**Shift and Adjust Logic:**
- Shift Register:
- The module uses a 20-bit shift register where the lower 8 bits hold the binary input, and the upper 12 bits store the BCD result.
- Adjustment Condition (`>= 5`):
- Before each shift, BCD digits are checked; if `≥ 5`, `+3` is added to prevent invalid values.
- Final Output Extraction:
- After 8 shifts, the upper 12 bits of the shift register (`shift_reg[19:8]`) contain the final BCD result. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | binary_to_bcd | uut | [
{
"name": "binary_to_bcd.sv",
"content": "`timescale 1ns / 1ps\n\nmodule binary_to_bcd (\n input logic [7:0] binary_in, // 8-bit binary input\n output logic [11:0] bcd_out // 12-bit BCD output (3 digits)\n);\n\n // Intermediate shift register to hold binary and BCD values\n logic [19:0] shift_reg;... | [] |
cvdp_copilot_binary_search_tree_sorting_0030 | medium | Non-Agentic | Implement a System Verilog testbench named `binary_search_tree_search_node_tb` to generate stimuli for a `search_binary_search_tree` module that performs a search for a given key in a binary search tree (BST).
## Design Specification:
The BST is a structure formed where each node contains a key, with its `left_child` containing `keys` less than or equal to the node, and its `right_child` containing `keys` greater than the node. The module locates the position of the `search_key` in the array sorted with the constructed BST. The position where the `search_key` is located is based on its **position in the sorted array** (sorted such that the smallest element is at index 0 and the largest element is at index `ARRAY_SIZE`-1). The array is not sorted in this module. However, the BST is constructed in a way that traversing to the nodes results in a sorted array. The module doesn't wait for the complete BST to be traversed. As soon as the `search_key` is found and its position is located, the module stops its search and transitions to the final state.
**Parameterization**
- **ARRAY_SIZE**: Specifies the number of elements in the input array.
- Default: 15
- **DATA_WIDTH**: Specifies the bit-width of each array element.
- Default: 16
### Inputs:
- `[ARRAY_SIZE*DATA_WIDTH-1:0] keys`: A packed array containing the node values of the BST.
- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] left_child`: A packed array containing the left child pointers for each node in the BST.
- `[ARRAY_SIZE*($clog2(ARRAY_SIZE)+1)-1:0] right_child`: A packed array containing the right child pointers for each node in the BST.
- `[$clog2(ARRAY_SIZE):0] root`: The index of the root node (always 0 except for an empty BST, assuming the BST is constructed such that the first element in the arrays corresponds to the root node). For an empty BST, `root` is assigned an invalid index where all bits are set to 1; Eg: 15 (for ARRAY_SIZE = 7)
- `[DATA_WIDTH-1:0] search_key`: The key to search for in the BST.
- `start`: 1-Bit active high signal to initiate the search (1 clock cycle in duration).
- `clk`: Clock Signal. The design is synchronized to the positive edge of this clock.
- `reset`: Asynchronous active high reset to reset all control signal outputs to zero and `key_position` to null pointer (all 1s).
### Outputs
- `[$clog2(ARRAY_SIZE):0] key_position`: The position of the `search_key` in the BST with respect to its sorted position. Updated at the same time when the `complete_found` is asserted. If the `search_key` is not found in the constructed BST or if the tree is empty (indicated by all entries in `left_child`, `right_child` being null pointers, and all `keys` being zero) the module sets all the bits of `key_position` to 1 (null position)
- `complete_found`: 1-Bit active high signal that is asserted once the search is complete, indicating that the key was found (1 clock cycle in duration). If the `search_key` is not found in the constructed BST or if the tree is empty `complete_found` remains at 0.
- `search_invalid`: 1-bit Active high signal that is asserted when the BST is empty or when the `search_key` doesn't exist in the given BST (1 clock cycle in duration).
### Testbench Requirements:
**Instantiation**
- **Module Instance**: The module `search_binary_search_tree` should be instantiated as `dut`, with all input and output signals connected for testing.
**Input Generation**
- **BST Generation**:
- The testbench must generate multiple test cases with different random values for `keys`, `left_child`, and `right_child` which abides by the structure of the BST where each node contains a key, with its `left_child` containing `keys` less than the node, and its `right_child` containing `keys` greater than the node.
- To accurately construct a BST including `keys`, `left_child`, and `right_child`, create a separate submodule that generates different BSTs based on the input array provided.
- To generate a BST, different input arrays can be provided as input to the new submodule responsible for constructing the BST.
- Test with all possible combinations to achieve maximum coverage. Include the corner cases, such as input arrays with all values equal and already sorted arrays in ascending or descending order.
- Testbench must also include a scenario with an empty tree where all bits of `root`, `left_child`, and `right_child` are set to one, and `keys` are set to 0.
- **Search Key (`search_key`) Generation**:
- The testbench must generate different random values of `search_key` where the random values generated must be one of the values in the `keys` for a given BST input. To be able to traverse the tree in worst-case scenarios, tests should include `search_key` generation for the smallest, largest value in the given BST.
- To handle the invalid case (`search_invalid`), the testbench must generate `search_key`, which is not present within the given BST.
**Control Signal Handling**:
- The `start` signal should be asserted to trigger the searching process, and the testbench must wait until the `complete_found` signal is asserted (to wait for the searching to be completed) when the search is valid or wait until the `search_invalid` is asserted when the `search_key` is not found within the tree or when the tree is empty.
- The new inputs `keys`, `left_child`, `right_child`, and `search_key` along with the `start` signal must only be asserted after the `complete_found` or `search_invalid` signal for the previous input array is asserted to high. This process must be repeated to cover different sequences of input array, which means different BSTs will be generated. It must be noted that while the `complete_found` or `search_invalid` signal is high, the new input `keys`, `left_child`, `right_child`, `search_key`, and `start` must not be asserted to avoid loss of `start` and new inputs. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | search_binary_search_tree | dut | [
{
"name": "search_binary_search_tree.sv",
"content": "module search_binary_search_tree #(\n parameter DATA_WIDTH = 16, // Width of the data\n parameter ARRAY_SIZE = 15 // Maximum number of elements in the BST\n) (\n\n input clk, // Clock signal\n input re... | [] |
cvdp_copilot_binary_search_tree_sorting_0015 | medium | Non-Agentic | Write a SystemVerilog testbench named `bst_sort_tb` that generates only stimulus for a binary search tree (BST) based sorting algorithm design `binary_search_tree_sort` that processes an array of unsigned integers with a parameterizable size, ARRAY_SIZE (number of elements in the array, will be greater than 0). The stimulus should be generated for a design that sorts an input array in ascending order using the BST insertion and in-order traversal logic. The sorting process should be driven by control signals and should be tested for various input arrays.
A BST is a data structure where each node has a key, and its left child contains keys less than or equal to the node, while its right child contains keys greater than the node and thereby constructs a tree. The algorithm organizes the integers into a binary search tree and traverses the tree to produce a sorted output array.
### Design Details
**Parameterization**
- **ARRAY_SIZE**: Specifies the number of elements in the input array.
- Default: 7
- **DATA_WIDTH**: Specifies the bit-width of each array element.
- Default: 8
**Functionality**
- **Array Processing**:
The design takes an unsorted array and constructs a binary search tree (BST). It then performs an in-order tree traversal to produce a sorted array. The sorting process is controlled using the start and done signals. The input array, **data_in**, should remain unchanged once the sorting process begins. Any changes to the input during the sorting operation would not be considered.
- **Control Signals**:
- **start**: An active-high signal indicating the start of the sorting operation. When asserted, the sorting begins.
- **done**: An active-high signal that indicates the sorting operation has been completed. It is asserted after the sorting process is finished.
**Inputs and Outputs**
**Inputs:**
- **clk**: Clock signal for synchronization. The design is synchronized to the positive edge of this clock.
- **reset**: Active-high asynchronous reset.When asserted, it immediately resets all outputs (**sorted_out** array and **done**) to zero.
- **start**: Active-high signal for 1 clock cycle to initiate the sorting process.
- **data_in [ARRAY_SIZE*DATA_WIDTH-1:0]**: The unsorted input array that will be sorted by the BST-based algorithm.
**Outputs:**
- **done**: An active high signal for 1 clock cycle indicates when the sorting operation is complete.
- **sorted_out [ARRAY_SIZE*DATA_WIDTH-1:0]**: The sorted array output in ascending order, such that the smallest element is at index 0 and the largest element is at index ARRAY_SIZE-1.
### Requirements:
**Instantiation**
- **Module Instance**: The BST-based sorting module should be instantiated as `dut`, with all input and output signals connected for testing.
**Input Generation and Validation**
- **Array Generation**: The testbench must generate multiple test cases with different values for **data_in**, including edge cases such as an array with all elements the same, an already sorted array, and a reverse-sorted array.
**Control Signal Handling**:
- The **start** signal should be asserted to trigger the sorting process, and the testbench must wait until the **done** signal is asserted (to wait for the sorting to be completed).
- The new input **data_in** along with the start signal must only be asserted after the **done** signal for the previous input array is asserted to high (after **done** asserts and deasserts). This process must be repeated to cover different sequences of input_data. It must be noted that while the done signal is high, the new input **data_in** and **start** must not be asserted to avoid loss of **start** and new input **data_in**.
**Test Coverage**
- Test with all possible combinations of elements within input array **data_in** via randomization as well as corner cases such as :
- **data_in** with all values equal.
- **data_in** that is already sorted.
- **data_in** in descending order. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | binary_search_tree_sort | dut | [
{
"name": "binary_search_tree_sort.sv",
"content": "module binary_search_tree_sort #(\n parameter DATA_WIDTH = 32,\n parameter ARRAY_SIZE = 15\n) (\n input clk,\n input reset,\n input reg [ARRAY_SIZE*DATA_WIDTH-1:0] data_in, // Input data to be sorted\n input start,\n output reg [ARRAY_... | [] |
cvdp_copilot_secure_read_write_bus_0005 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `secure_read_write_bus_interface`. It support both read and write operations, with authorization based on a comparison between the input key and an internal parameterized key. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
### Functional Requirements
1. **Read and Write Operations**:
- The bus performs read or write actions based on an enable signal.
- Access is authorized only if the provided key matches an internal key, with errors flagged otherwise.
### Inputs
- `i_addr` (`p_addr_width bit`): Specifies the target address for read or write operations.
- `i_data_in` (`p_data_width` bit): Data to be written during a write operation.
- `i_key_in` (`8-bit`): Key provided by the initiator for operation authorization.
- `i_read_write_enable` (`1-bit`): Specifies the requested operation; `1` for read, `0` for write.
- `i_capture_pulse` (`1-bit`): Qualifies input capture for `i_addr`, `i_data_in`, `i_key_in`, and `i_read_write_enable`.
- `i_reset_bar` (`1-bit`): Asynchronous, active-low reset to initialize internal states and registers.
### Outputs
- `o_data_out` (`p_data_width` bit): Data output during a read operation, valid only if the input key matches the internal key.
- `o_error` (`1-bit`): Asserted if the input key is incorrect and dessert if input key is correct.
### Behavioral Requirements
#### Write Operation
- If `i_read_write_enable` is **0**, the bus interprets the operation as a write request.
- At the rising edge of `i_capture_pulse`:
- If `i_key_in` matches the internal 8-bit configurable key, `i_data_in` is written to the address specified by `i_addr`.
- If `i_key_in` does not match the internal key:
- `o_error` is set to **1**.
- `o_data_out` is set to **0** (default).
#### Read Operation
- If `i_read_write_enable` is **1**, the bus interprets the operation as a read request.
- At the rising edge of `i_capture_pulse`:
- If `i_key_in` matches the internal key, data from address `i_addr` is output on `o_data_out`, and `o_error` is **0**.
- If `i_key_in` does not match:
- `o_error` is set to **1**.
- `o_data_out` remains **0**.
### Parameterization Requirements
- `p_configurable_key`: Internal 8-bit key, default value `8'hAA`.
- `p_data_width`: Configurable data width, default is **8 bits**.
- `p_addr_width`: Configurable address width, default is **8 bits**.
### Additional Requirements
1. **Edge Case Handling**:
- `i_reset_bar` reset signal should clear all internal registers and outputs when asserted low.
- Ensure that outputs default to `0` upon reset or when unauthorized access occurs.
2. **Clocking and Timing**:
- Operations are gated by the positive edge of `i_capture_pulse` for both read and write actions.
- Timing for signal latching and error assertions should align with rising edges of `i_capture_pulse`.
### Assumptions
- Assume all the inputs are synchronous to the `i_capture_pulse`
## Test Bench Requirements
### Stimulus Generation
## **1. Reset Behavior**
- The system should be tested under reset conditions.
- Reset is released.
---
## **2. Write Operations**
### **2.1 Writing Data Under Normal Conditions**
- A write operation should be performed when the interface is enabled for writing.
### **2.2 Unauthorized Write Attempt**
- An attempt should be made to write data while using an incorrect authentication key.
### **2.3 Writing at the Lower Address Boundary**
- A write operation should be performed at the smallest possible address in the addressable range.
### **2.4 Writing at the Upper Address Boundary**
- A write operation should be performed at the largest possible address in the addressable range.
### **2.5 Randomized Write Operations**
- Multiple write operations should be performed at various random addresses with different data values.
---
## **3. Read Operations**
### **3.1 Reading Data Under Normal Conditions**
- A read operation is requested, and the correct authentication key is provided.
### **3.2 Unauthorized Read Attempt**
- A read request should be made using an incorrect authentication key.
### **3.3 Reading from an Uninitialized Memory Location**
- An attempt should be made to read from an address where no data has been written, ensuring predictable behavior.
### **3.4 Reading at the Lower Address Boundary**
- A read operation should be performed at the smallest possible address.
### **3.5 Reading at the Upper Address Boundary**
- A read operation should be performed at the largest possible address in the addressable range to ensure boundary handling.
---
## **4. Error Handling & Corner Cases**
### **4.1 Switching Between Correct and Incorrect Authentication Keys**
- The system should be tested by performing multiple read and write operations while alternating between valid and invalid authentication keys.
### **4.2 Writing Without Initiating the Operation**
- An attempt should be made to write data without properly triggering the operation.
### **4.3 Reading Without Initiating the Operation**
- A read request should be simulated without properly triggering the operation.
### **4.4 Unauthorized Read Followed by an Authorized Write**
- An unauthorized read should be performed first, followed by an attempt to write data using the correct authentication key.
### **4.5 Unauthorized Write Followed by an Authorized Read**
- An unauthorized write should be attempted first, followed by an authorized read to ensure no incorrect data modifications occur.
### **4.6 Rapid Switching Between Read and Write**
- The interface should be tested with rapid consecutive read and write operations to check for any inconsistencies or race conditions.
---
## **5. Reset and System Initialization**
### **5.1 System Behavior During Reset**
- The system should be reset in the middle of operations.
### **5.2 Operations After Reset**
- Once reset is deactivated, read and write operations resumes.
---
## **6. Stress Testing**
### **6.1 Consecutive Writes**
- A series of consecutive write operations should be performed to different addresses.
### **6.2 Consecutive Reads**
- Multiple read operations should be executed in succession.
### **6.3 Immediate Read After Write**
- Data should be written to a location, and an immediate read request should be performed at the same address.
### **6.4 Frequent Changes in Authentication Key**
- Successive read and write operations should be tested while frequently changing the authentication key.
### **6.5 Combining Edge Cases**
- A complex test scenario should be created by combining multiple conditions, such as alternating between valid and invalid keys, performing reads and writes at boundary addresses, and introducing reset signals. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | secure_read_write_bus_interface | dut | [
{
"name": "secure_read_write_bus_interface.v",
"content": "module secure_read_write_bus_interface #(\n parameter p_configurable_key = 8'hAA, // Default key\n parameter p_data_width = 8, // Data width\n parameter p_addr_width = 8 // Address width\n)(\n input wir... | [] |
cvdp_copilot_cellular_automata_0002 | easy | Non-Agentic | Complete the given partial System Verilog testbench `tb_pseudoRandGenerator_ca`.The testbench must instantiate the `pseudoRandGenerator_ca` RTL module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `pseudoRandGenerator_ca` module simulates a simple pseudo-random number generator using a cellular automata algorithm with a 16-bit seed input.
## Description:
### **Inputs** :
Registers :
`CA_out` (16-bit,[15:0]): 16-bit pseudo-random output received from the **DUT**.
### **Outputs** :
Registers :
`clock (1-bit)`: Posedge Clock signal that toggles every 10ns (100 MHz) supplied to the **DUT**
`reset (1-bit)`: Active-high synchronous reset signal that resets the output of **DUT** to the initial seed value
`CA_seed` (16-bit,[15:0]): 16-bit seed value for initializing the cellular automata **DUT**.
## **Instantiation**:
The testbench instantiates the `pseudoRandGenerator_ca` module as dut and connects the signals between the module and the testbench. Each input and output from the **DUT** is connected to its corresponding signal in the testbench.
## **Input Generation and Validation**:
**Clock Generation**:
The clock signal clock is generated using an always block that toggles the clock every 10ns.
**Reset**:
The reset signal reset is asserted at the beginning of the simulation to ensure the DUT initializes to the correct seed. After a short period (150ns), the reset is de-asserted.
**Stimulus**:
Multiple test cases are applied to simulate various initial seed values for the Cellular Automata algorithm. The output from the DUT is monitored to ensure the proper sequence of pseudo-random numbers is generated.
- **Test Case 1:**
**CA_Seed**: 16'hA5A5
This case tests the cellular automata algorithm with a specific seed to observe the random output.
- **Test Case 2:**
**CA_Seed**: 16'h3C3C
This case tests a different seed to ensure the correct random sequence is generated.
- **Test Case 3:**
**CA_Seed**: 16'h1234
This case checks the behavior of the generator with a hexadecimal seed value.
- **Test Case 4:**
**CA_Seed**: 16'h4444
This case evaluates the algorithm with another specific seed.
- **Test Case 5:**
**CA_Seed**: 16'h5BEF
Testing with a random 16-bit seed value to observe variation in the random output.
- **Test Case 6:**
**CA_Seed**: 16'h0001
Verifies edge case where the seed is the smallest non-zero value.
- **Test Case 7:**
**CA_Seed**: 16'hFFFF
Verifies the upper boundary seed to ensure the algorithm handles high values correctly.
- **Test Case 8:**
CA_Seed: 16'hAAAA
Verifies the cellular automata's ability to handle seeds with alternating bits.
- **Test Case 9:**
**CA_Seed**: 16'h5555
Similar to the previous case, but with alternating low/high bits.
## **Reset Handling**:
After running the test cases, a reset is asserted again to ensure the generator is properly reset to its initial seed state and the output is as expected.
**Partial Test Stimulus Generator Code** :
```verilog
module tb_pseudoRandGenerator_ca;
logic clk;
logic reset;
logic [15:0] CA_seed; // 16-bit seed input
logic [15:0] CA_out; // 16-bit output for Cellular Automata
pseudoRandGenerator_ca dut (
.clock(clk),
.reset(reset),
.CA_seed(CA_seed),
.CA_out(CA_out)
);
always begin
#10 clk = ~clk;
end
task initialization();
begin
clk = 1'b0;
reset = 1'b1;
CA_seed = 16'hA5A5;
end
endtask
task drive_reset();
begin
reset = 1'b1;
end
endtask
task clear_reset();
begin
reset = 1'b0;
end
endtask
task run_test_case(input [15:0] test_seed);
begin
CA_seed = test_seed;
#1000;
$display("Test case with seed %h finished", test_seed);
end
endtask
initial begin
$dumpfile("tb_pseudoRandGenerator_ca.vcd");
$dumpvars(0, tb_pseudoRandGenerator_ca);
initialization();
#150;
clear_reset();
run_test_case(16'hA5A5);
// Insert the code for the remaining test cases here
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | pseudoRandGenerator_ca | dut | [
{
"name": "pseudoRandGenerator_ca.sv",
"content": "module pseudoRandGenerator_ca (\n input logic clock, // Clock input\n input logic reset, // Active-high synchronous Reset\n input logic [15:0] CA_seed, // 16-bit Cellular Automata seed\n output logic [15:0] CA_out // 16-... | [] |
cvdp_agentic_hdbn_codec_0003 | medium | Agentic | The `hdbn_top` module's specification document is in the `docs/specification.md` folder. Write a SystemVerilog testbench, `tb_hdbn_top.sv`, in the `verif` directory to only generate stimulus for the `hdbn_top` module to achieve maximum coverage of the UUT.
Include the following in the generated testbench:
### 1. **Module Instance**
The `hdbn_top` module should be instantiated as **uut**, with the input and output signals connected for testing.
### 2. **Input Generation**
The testbench must generate diverse and comprehensive input patterns to drive the encoder and decoder paths:
- Pseudorandom PRBS streams and deterministic sequences, including edge cases like long runs of zeros and alternating bits.
- Clock enable gating and reset sequences that simulate real-world startup and active operation.
- Error injection can be controlled by the `inject_error` flag, introduced after a specified startup delay.
- Optional inversion of polarity between encoder and decoder. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | hdbn_top | uut | [
{
"name": "hdbn_encoder.sv",
"content": "module hdbn_encoder\n(\n input logic reset_in, // Active high async reset\n input logic clk_in, // Rising edge clock\n input logic pulse_active_state, // Rising edge clock\n input logi... | [
{
"name": "specification.md",
"content": "# **HDBn (HDB3/HDB2) Codec Specification Document**\n\n## **1. Overview**\nThe HDBn (High-Density Bipolar) coding scheme was developed to solve critical issues in digital telecommunications transmission. Traditional AMI (Alternate Mark Inversion) coding faced proble... |
cvdp_copilot_hamming_code_tx_and_rx_0037 | easy | Non-Agentic | Develop a SystemVerilog testbench named `testbench_for_hamming_rx` to only supply stimuli to and achieve maximum possible coverage for an RTL design named `hamming_rx` . The module is a **parameterized Hamming code receiver** that takes an encoded input signal (`data_in`), which contains **data bits, parity bits, and a redundant bit**, and detects and corrects **only single-bit errors**. The corrected data is then assigned to `data_out`. Error detection and correction are performed using Hamming code principles, specifically **even parity checks (XOR operations)**.
---
### **RTL Specification for `hamming_rx`**
#### Parameterization:
- **DATA_WIDTH**: Specifies the width of the data input, configurable by the user. The default is 4 and should be greater than 0.
- **PARITY_BIT**: Specifies the number of parity bits, also configurable by the user. The default is 3.
- The **number of parity bits** should be the minimum integer value that satisfies the Hamming code formula:
[2<sup>p</sup> >= (p + m) + 1], where m is the number of data bits and p is the number of parity bits.
For example, if `m = 4`:
- `p = 0` results in \(2<sup>0</sup> >= 0 + 5\), which is false.
- `p = 1` results in \(2<sup>1</sup> >= 1 + 5\), which is false.
- `p = 2` results in \(2<sup>2</sup> >= 2 + 5\), which is false.
- `p = 3` results in \(2<sup>3</sup> >= 3 + 5\), which is true and the minimum value to satisfy the condition
- **ENCODED_DATA**: Calculated as the sum of `PARITY_BIT + DATA_WIDTH + 1`, representing the total input width according to the Hamming code formula.
- `+1` accounts for the "no error" state in the input (`data_in`) by adding a redundant bit as the least significant bit.
- For example, if `m = 4` and `p = 3`, then `ENCODED_DATA = 8`.
- **ENCODED_DATA_BIT**: Calculated as the minimum number of bits required to index `ENCODED_DATA`.
- For example, if `m = 4`, `p = 3`, and `ENCODED_DATA = 8`, then `ENCODED_DATA_BIT = 3`.
#### Input/Output Specifications:
- **Inputs:**
- `data_in[ENCODED_DATA-1:0]`: Encoded data containing the redundant bit, original data, and parity bits.
- **Outputs:**
- `data_out[DATA_WIDTH-1:0]`: An output signal containing the corrected data if an error is detected. If no error is detected, this output will mirror the data bits in the Encoded input (`data_in`).
#### Behavioral Definitions:
- The number of parity bits is determined based on the configured `PARITY_BIT` parameter.
- Each parity bit is calculated by performing an XOR operation over specific bits in `data_in`.
- Individual parity bits are combined into an error detection code, which represents the parity check result.
- Based on the parity check result
- The design locates and inverts the erroneous bit position at the error location.
- Note: The redundant bit at position 0 is not inverted.
4. **Output Assignment**:
- The data bits are retrieved from the internal **corrected data** and assigned to `data_out` from least significant bit (LSB) to most significant bit (MSB), with the lowest-index bit picked from the corrected data mapped to the LSB of `data_out`, progressing to the MSB. This ensures that `data_out` contains only the **corrected data bits, excluding the parity bits and the redundant bit**.
### **Testbench Description**
#### **Instantiation**
- **Module Instance:** The `hamming_rx` module should be instantiated as **`uut_receiver`**, with parameters, input and output signals connected for testing.
---
### **Input Generation and Validation**
1. **Input Generation:**
- The testbench should generate all possible DATA_WIDTH-bit binary values for input data (ranging from the minimum value (0) to the maximum value (2<sup>DATA_WIDTH</sup> - 1)) and extend it to include encoding bits before supplying the stimulus to the design, ensuring coverage of both typical cases and edge cases.
3. **Golden Encoder Logic:**
- Inputs provided to the module should follow a specific pattern similar to data generated from a transmitter following Hamming code principles. It should also ensure that erroneous input data is supplied with only single-bit errors (as the RTL is capable of correcting only single-bit errors)
- The testbench should encode the generated DATA_WIDTH-bit data into an ENCODED_DATA-bit data (golden encoded data). The encoding process based on Hamming code principles is explained in the Hamming code transmitter specification given below.
**Hamming code transmitter function:** This function takes an input `[DATA_WIDTH-1:0] input_data` and generates an encoded output `[ENCODED_DATA-1:0] temp_data`.
1. **Step 1**: Clear all internal registers to 0, including an internal PARITY_BIT-width array named `parity` for holding calculated parity bit values.
2. **Step 2**: Assign `input_data` to `temp_data`.
- Parity bits are placed at `temp_data` positions corresponding to powers of 2. (e.g., indices 2<sup>0</sup> = 1, 2<sup>1</sup> = 2, 2<sup>2</sup> = 4, etc.) and `temp_data[0]` is a redundant bit which is always set to 1'b0.
- The bits of `input_data` are mapped sequentially, starting from the least significant bit (LSB) to the most significant bit (MSB), into the non-parity and non-redundant positions of `temp_data`. The LSB of `input_data` aligns with the lowest-index non-parity and non-redundant position in `temp_data`, and the order of the bits is preserved.
- Example:
- For `DATA_WIDTH = 4` and `PARITY_BIT = 3`, `ENCODED_DATA` is 8, and `ENCODED_DATA_BIT` is 3:
- The `temp_data` assignment is as follows:
- `temp_data[0]` - position 000 - assign **1'b0**.
- `temp_data[1]` - position 001 - reserve for **parity[0]**.
- `temp_data[2]` - position 010 - reserve for **parity[1]**.
- `temp_data[3]` - position 011 - assign `input_data[0]`.
- `temp_data[4]` - position 100 - reserve for **parity[2]**.
- `temp_data[5]` - position 101 - assign `input_data[1]`.
- `temp_data[6]` - position 110 - assign `input_data[2]`.
- `temp_data[7]` - position 111 - assign `input_data[3]`.
3. **Step 3**: Calculate the even parity bits based on the Hamming code principle.
- Define **PARITY_BIT** (e.g., for `PARITY_BIT = 3`, calculate `parity[0]`, `parity[1]`, and `parity[2]`).
- Each parity bit calculation: For each parity bit `parity[n]` (where n ranges from 0 to PARITY_BIT-1), determine its value by performing an XOR operation on the bits in `temp_data` located at indices where the n<sup>th</sup> bit (counting from the least significant bit) of the binary index is 1. For example:
- `parity[0]` includes all indices where the least significant bit (LSB) of the binary index is 1. (positions 00**1**, 01**1**, 10**1**, and 11**1** in `temp_data`).
- Calculation: `parity[0] = XOR of temp_data[1], temp_data[3], temp_data[5], temp_data[7]`.
- `parity[1]` includes indices where the second bit from the LSB of the binary index is 1, and so forth. (positions 0**1**0, 0**1**1, 1**1**0, and 1**1**1 in `temp_data`).
- Calculation: `parity[1] = XOR of temp_data[2], temp_data[3], temp_data[6], temp_data[7]`.
4. **Step 4**: Insert the calculated parity bits into `temp_data` at positions corresponding to powers of 2.
- To simulate errors, a single bit in the **golden encoded data** (generated from the transmitter function above) should be randomly modified. This modified data is then assigned to the input `data_in[ENCODED_DATA-1:0]` of the design under test (**`uut_receiver`**).
4. **Stabilization Period:**
- After assigning each input value, the testbench should wait for at least 10 time units to ensure that the outputs have stabilized before asserting new values. | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 97
}
] | hamming_rx | uut_receiver | [
{
"name": "hamming_rx.sv",
"content": "module hamming_rx \n#(\n parameter DATA_WIDTH = 4,\n parameter PARITY_BIT = 3,\n parameter ENCODED_DATA = PARITY_BIT + DATA_WIDTH + 1,\n parameter ENCODED_DATA_BIT = $clog2(ENCODED_DATA)\n)\n(\n input [ENCODED_DATA-1:0] data_in, \n output reg [DATA_WIDTH-1:0... | [] |
cvdp_agentic_direct_map_cache_0005 | medium | Agentic | I have a `direct_map_cache` module in the RTL directory. Write a SystemVerilog testbench named `tb_direct_map_cache.sv` in the verif directory that generates a wide range of read and write operations across different modes, such as compare and non-compare, and conditionally, like forced misses.
## Module Instance
- Instantiate the `direct_map_cache` module as `uut` (Unit Under Test) in the testbench.
## Tasks
Implement separate reusable tasks, each responsible for a specific stimulus scenario or operational mode in the cache. The tasks should cover at least the following functional areas:
### Initialization and Reset
- Prepares the environment by driving reset signals and ensuring the design is in a known state prior to applying any other inputs.
### Write with Compare Disabled
- Drives signals to perform write operations where compare logic is bypassed.
- Writes random or iterated data into cache lines to populate entries.
### Read with Compare Enabled
- Exercises a read operation that checks the tag field.
### Write with Compare Enabled
- Overwrites data in cache lines if a matching tag is detected, while compare is active.
### Read with Compare Disabled
- Retrieves data in a simpler access mode without relying on tag matching.
### Miss Scenario Generation
- Forces mismatches by selecting indices and tags unlikely to match existing entries.
### Offset Error Injection
- Applies an offset pattern that should trigger an error (e.g., least significant bit set in an address where it must remain clear).
### Coverage Corner Cases
- Specifically vary conditions that test partial hits, valid bit clearing, different dirty states, and scenarios where tags match but the valid bit is not set, or vice versa.
- Generate test sequence hits corner conditions such as:
- A valid line with a matching tag.
- A valid line with a mismatching tag.
- An invalid line with a matching tag.
- An invalid line with a mismatching tag.
Each task should display the relevant signals (e.g., indices, offsets, tags, data, and status flags) and outcomes (hit/miss, error indication) for traceability. The combination of these tasks must collectively cover the full range of operational behaviors.
## Test Scenarios & Structured Logging
- Use a systematic or random sequence that calls the above tasks multiple times with varying index, tag, and data values to ensure broad coverage.
- After each operation, print diagnostic messages that show the inputs and outputs, focusing on:
- The action taken (read/write, compare mode or not).
- The cache line/index/offset accessed.
- Whether the operation resulted in a hit, miss, dirty line, or error.
## Test Execution Control
- Trigger the reset sequence to initialize the device under test.
- Call each stimulus task in an order that logically tests standard usage, corner cases, and error paths.
- Use repeat loops or nested loops (or a combination of both) to systematically cover different indices, tags, offsets, and data patterns.
- Finish the simulation using `$finish` when all tests are complete. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | direct_map_cache | uut | [
{
"name": "direct_map_cache.sv",
"content": "`timescale 1ns/1ps\nmodule direct_map_cache #(\n parameter CACHE_SIZE = 256, // Number of cache lines\n parameter DATA_WIDTH = 16, // Width of data\n parameter TAG_WIDTH = 5, // Width of the tag\n pa... | [] |
cvdp_copilot_concatenate_0003 | easy | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `enhanced_fsm_signal_processor` module by applying exhaustive test scenarios. The module uses a finite state machine (FSM) to manage signal processing operations, handle fault conditions, and report the FSM's current status. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage. The testbench should not create checkers to verify the MUT.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameter Inputs - Outputs and Functional behaviour**
### **Inputs**
- `i_clk`: Clock signal for sequential operation.
- `i_rst_n`: Active-low reset signal that resets the FSM and clears outputs.
- `i_enable`(1 bit): Enable signal to start processing; when low, the FSM remains in IDLE.
- `i_clear`(1 bit): Signal to clear outputs and reset the fault state.
- `i_ack`(1 bit): Acknowledgment signal to transition the FSM from READY to IDLE after processing is complete. It will be a pulse of 1 clock cycle.
- `i_fault`(1 bit): Signal indicating a fault condition during operation.
- `i_vector_1`: 5-bit input vector.
- `i_vector_2`: 5-bit input vector.
- `i_vector_3`: 5-bit input vector.
- `i_vector_4`: 5-bit input vector.
- `i_vector_5`: 5-bit input vector.
- `i_vector_6`: 5-bit input vector.
### **Outputs**
- `o_ready`(1 bit): Signal that indicates when outputs are valid and processing is complete. Default 0.
- `o_error`(1 bit): Signal that asserts when a fault condition is detected. Default 0.
- `o_fsm_status`(2 bits): Current FSM state, encoded as a 2-bit signal, representing one of the FSM states: IDLE(00), PROCESS(01), READY(10), or FAULT(11). Default is IDLE.
- `o_vector_1`: 8-bit output vector. Default 0.
- `o_vector_2`: 8-bit output vector. Default 0.
- `o_vector_3`: 8-bit output vector. Default 0.
- `o_vector_4`: 8-bit output vector. Default 0.
---
### **FSM States and Functionality**
#### **States**
1. **IDLE**:
- Default state.
- FSM waits for `i_enable` to assert high to transition to PROCESS.
- If `i_fault` is detected, FSM transitions to FAULT.
2. **PROCESS**:
- Concatenates six 5-bit input vectors into a single 30-bit bus, appends two `1` bits at the LSB to form a 32-bit bus, and splits it into four 8-bit output vectors.
- `o_vector_1` to `o_vector_4` maps from MSB to LSB of concatenation bus.
- If `i_fault` is detected during this state, FSM transitions to FAULT.
3. **READY**:
- Indicates processing is complete by asserting `o_ready`.
- FSM waits for `i_ack` to transition back to IDLE.
- If `i_fault` is detected, FSM transitions to FAULT.
4. **FAULT**:
- Asserts `o_error` to indicate a fault condition.
- Outputs are set to default.
- FSM transitions to IDLE only when `i_clear` is asserted and `i_fault` is deasserted.
---
### **Operational Rules**
- The FSM must progress through states sequentially, synchronized to `i_clk`.
- When `i_rst_n` is low, FSM resets to IDLE, clears outputs, and resets the fault state.
- When in FAULT, the `i_clear` signal must clear the fault condition and reset the FSM to IDLE.
- Outputs (`o_vector_1`, `o_vector_2`, `o_vector_3`, `o_vector_4`) must strictly adhere to the concatenation and splitting logic specified.
- Fault handling (`o_error` and FAULT state) must take precedence over other operations.
- All the outputs are synchronous to `i_clk`.
- `i_fault` always take precedence over any other input except `i_clk` and `i_rst_n`.
- All the input are synchronous to `i_clk`.
## Stimulus Generation
### **Test Case 1: Reset and Idle Check**
- **Stimulus**
1. `i_rst_n=0` (active-low reset), `i_enable=0`, `i_clear=0`, `i_ack=0`, `i_fault=0`
2. Release reset: `i_rst_n=1`
---
### **Test Case 2: Basic Enable → Process → Ready → Acknowledge → Idle**
- **Stimulus**
1. From IDLE, set example inputs (five-bit vectors).
- For instance:
- `i_vector_1 = 5'b00111`
- `i_vector_2 = 5'b01010`
- `i_vector_3 = 5'b10101`
- `i_vector_4 = 5'b11100`
- `i_vector_5 = 5'b00001`
- `i_vector_6 = 5'b11000`
2. `i_enable=1` → transitions to PROCESS.
3. After one PROCESS cycle, FSM moves to READY (`o_ready=1`).
4. Pulse `i_ack=1` → returns FSM to IDLE.
---
### **Test Case 3: Fault in IDLE State**
- **Stimulus**
1. FSM in IDLE (`i_enable=0`, etc.).
2. Assert `i_fault=1`.
- **Sample Input Vectors**
- Can be any values;
---
### **Test Case 4: Fault in PROCESS State**
- **Stimulus**
1. From IDLE, assert `i_enable=1` to enter PROCESS.
2. While in PROCESS, assert `i_fault=1`.
- **Sample Input Vectors**
- Similar to Test Case 2 or any other 5-bit patterns;
---
### **Test Case 5: Fault in READY State**
- **Stimulus**
1. Complete a normal PROCESS → READY cycle.
2. While `o_ready=1`, assert `i_fault=1`.
3. Hold the FSM is explicitly in the READY state by not asserting i_ack immediately, then i_fault is pulsed. This ensures that the READY -> FAULT transition is covered.
- **Sample Input Vectors**
- Use any 5-bit patterns leading into READY. Then trigger fault.
---
### **Test Case 6: Clear from FAULT State**
- **Stimulus**
1. Enter FAULT (any prior scenario).
2. Assert `i_clear=1` but keep `i_fault=1` → still in FAULT.
3. Deassert `i_fault=0` (with `i_clear=1`) → FSM → IDLE.
- **Sample Input Vectors**
- Irrelevant once in FAULT;
---
### **Test Case 7: Repeated Enable Pulses**
- **Stimulus**
1. Rapidly toggle `i_enable` (1→0→1→0) starting from IDLE.
2. Check FSM behavior in PROCESS or READY; it should ignore extra enables.
- **Sample Input Vectors**
- Use any stable 5-bit inputs;
---
### **Test Case 8: Repeated Fault Pulses**
- **Stimulus**
1. Cause a FAULT (any state).
2. Rapidly toggle `i_fault` high/low without clearing.
- **Sample Input Vectors**
- Not critical here;
---
### **Test Case 9: Data Path Validation**
- **Stimulus**
1. Vary each `i_vector_n` (5 bits) across these patterns:
- **All-zero**: `5'b00000`
- **All-ones**: `5'b11111`
- **Mixed**: e.g. `5'b10101`, `5'b01010`
- **Boundary**: e.g. `5'b00001`, `5'b10000`
2. For each pattern, do IDLE → PROCESS → READY cycle. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | enhanced_fsm_signal_processor | dut | [
{
"name": "enhanced_fsm_signal_processor.v",
"content": "// Verilog RTL Design for enhanced_fsm_signal_processor\n\nmodule enhanced_fsm_signal_processor (\n input wire i_clk, // Clock signal\n input wire i_rst_n, // Active-low reset signal\n input wire i_enable, // Enabl... | [] |
cvdp_copilot_digital_stopwatch_0017 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench`dig_stopwatch_tb`. The testbench must instantiate the `dig_stopwatch` RTL module and provide input stimulus to observe its behavior. This module implements a parameterized stopwatch with seconds, minutes, and hour tracking functionality. The testbench should include different input scenarios like start, stop, and reset operations.
## **Description**
The `dig_stopwatch` module is a stopwatch that tracks elapsed time with inputs for clock, reset, and a start/stop control signal. It provides outputs for seconds, minutes, and hours, with appropriate rollovers and tracking behavior. The module operates based on a parameterized clock frequency (`CLK_FREQ`), which determines the timebase of the stopwatch.
## **Parameters**
- **CLK_FREQ**: Defines the input clock frequency in Hz, with a default value of 200 Hz. This frequency should be an integer value in Hz greater than the minimum value of 1 Hz. The clock divider within the module uses this parameter to generate a one-second pulse (`one_sec_pulse`).
---
## **Inputs**
- **`clk`**: Clock signal for synchronizing operations. The design is synchronized to the positive edge of this clock.
- **`reset`**: Asynchronous active-high reset signal to reset all counters to zero.
- **`start_stop`**: Start/stop is a 1 bit control signal that controls if the stopwatch is running or paused.
---
## **Outputs**
- **`seconds [5:0] `**: 6-bit output representing seconds (range: 0–59).
- **`minutes [5:0]`**: 6-bit output representing minutes (range: 0–59).
- **`hour`**: Represents a one-bit signal that updates to 1 when one hour has passed.
---
### **PERIOD Calculation**
The `PERIOD` is calculated using the formula `PERIOD = (1_000_000_000 / CLK_FREQ)`, where:
- `1_000_000_000` represents 1 second in nanoseconds.
- `CLK_FREQ` is the input clock frequency in Hz.
- For `CLK_FREQ = 200`, the resulting `PERIOD = 5_000_000` nanoseconds (5 ms per clock cycle).
## **Testbench Verification Features**
### **Instantiation**
The `dig_stopwatch` module is instantiated as `uut`, with its inputs and outputs connected to corresponding testbench signals. The parameter `CLK_FREQ` is set explicitly for the testbench to validate the module under different clock frequency conditions.
### **Clock Generation**:
- A clock signal is generated with a period of `PERIOD`, ensuring a frequency of `CLK_FREQ`.
### **Reset Operation**:
- `reset` is asserted at the beginning to initialize the stopwatch and deasserted after 100 nanoseconds.
### **Start and Stop Operations**:
- The stopwatch starts with `start_stop = 1` and stops with `start_stop = 0`.
### **Wait for Specific Duration**:
- The testbench uses the one-second pulse from the stopwatch to simulate precise elapsed time durations.
### **Test Sequences**:
- **Run for 1000 seconds**: The stopwatch runs with `start_stop = 1`.
- **Pause for 200 clock cycles**: The stopwatch is paused with `start_stop = 0`.
- **Run for 3000 seconds**: The stopwatch resumes operation.
- **Pause for 500 clock cycles**: The stopwatch is paused again.
- **Reset during operation**: The `reset` signal is asserted for 5 clock cycles to reset the counters.
- **Run for 100 seconds**: After the reset, the stopwatch resumes.
### **Waveform Dumping**:
- Simulation data is saved to a `.vcd` file for waveform analysis.
### Partial Test Stimulus Generator Code :
``` verilog
module dig_stopwatch_tb;
// Parameters
parameter CLK_FREQ = 200; // 200 Hz clock
localparam PERIOD = (1_000_000_000 / CLK_FREQ);
// Testbench Signals
reg clk;
reg reset;
reg start_stop;
wire [5:0] seconds;
wire [5:0] minutes;
wire hour;
// Clock generation
initial begin
clk = 0;
forever #(PERIOD/2) clk = ~clk;
end
// Instantiate the stopwatch module
dig_stopwatch #(
.CLK_FREQ(CLK_FREQ)
) uut (
.clk(clk),
.reset(reset),
.start_stop(start_stop),
.seconds(seconds),
.minutes(minutes),
.hour(hour)
);
// Task to wait for a specific number of seconds
task wait_seconds(input integer num_seconds);
integer i;
begin
for (i = 0; i < num_seconds; i = i + 1) begin
@(posedge uut.one_sec_pulse);
$display("Hour = %0d, Minutes = %0d , Seconds= %0d ", hour,minutes,seconds);
end
end
endtask
// Insert the code for the remaining test stimulus here
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 85
}
] | dig_stopwatch | uut | [
{
"name": "dig_stopwatch.sv",
"content": "module dig_stopwatch #(\n parameter CLK_FREQ = 50000000 // Default clock frequency is 50 MHz\n)(\n input wire clk, // Input clock (parameterized frequency)\n input wire reset, // Reset signal\n input wire start_stop, ... | [] |
cvdp_copilot_generic_nbit_counter_0013 | easy | Non-Agentic | Create a `tb_generic_counter` module that serves as the top-level testbench. This module should instantiate and include a `stimulus_generator` module, which must be developed to systematically drive different input conditions to the `generic_counter` module. The `stimulus_generator` should be designed to achieve 100% functional and code coverage by exercising all counting modes implemented in the `generic_counter`. These counting modes include binary up/down counting, modulo-N counting, Johnson counting, Gray code counting, and Ring counting. The counter operates based on an enable signal, a mode signal, and a configurable reference modulo value.
---
Follows the interface description of the RTL module.
## **Inputs**
- **Parameter**:
- `N`: A configurable Parameter Value. The default Value is 8.
- **Control Signals**:
- `mode_in [2:0]`: A 3-bit register selecting the counter mode.
- `enable_in`: A 1-bit register enabling the counter operation.
- **Clock Signal**:
- `clk_in`: The counter updates its value on the rising edge of this clock signal.
- **Reset Signal**:
- `rst_in`: A 1-bit asynchronous, active-high reset signal. When asserted HIGH, the counter resets to zero.
- **Reference Modulo Value**:
- `ref_modulo [N-1:0]`: A configurable N-bit reference value used for modulo-N counting.
## **Outputs**
- **Registers**:
- `o_count [N-1:0]`: An N-bit output representing the current counter value.
---
## **Instantiation**
- **Module Instance**:
- The `generic_counter` module is instantiated as `uut` in the testbench, with its inputs and outputs connected for testing.
---
## **Input Generation**
1. **Mode Coverage**:
- The testbench must ensure that all counting modes are exercised:
- `BINARY_UP`: Counts up sequentially.
- `BINARY_DOWN`: Counts down sequentially.
- `MODULO_256`: Resets when `o_count == ref_modulo`.
- `JOHNSON`: Implements Johnson's counter behavior.
- `GRAY`: Converts binary count to Gray code.
- `RING`: Implements a rotating one-hot sequence.
2. **Enable Behavior**:
- Toggle `enable_in` dynamically and ensure that counting stops when `enable_in = 0`.
3. **Modulo-N Counting**:
- Provide various `ref_modulo` values to the module.
4. **Reset Behavior**:
- Test asynchronous reset by asserting `rst_in` during different counter states.
- Ensure that `o_count` resets to zero when `rst_in` is active.
5. **Edge Cases**:
- There will be a random transition between different counting modes during operation.
- Initialize the RTL `count` register to a random value and run it in different modes.
6. **Timing Requirements**:
- After applying inputs, the testbench waits for a stabilization period of **300 clock cycles** before asserting new values.
7. **Stimulus Generator IO Ports**:
- **`clk` (input, 1-bit)**: Clock signal synchronizes the stimulus generation process.
- **`rst` (output, 1-bit)**: Active-high reset signal that initializes the `generic_counter` module.
- **`mode` (output, 3-bit)**: Specifies the counting mode for the `generic_counter`. Different values correspond to different counting modes such as binary up/down, modulo-N, Johnson, Gray code, and Ring counting.
- **`enable` (output, 1-bit)**: Enables the `generic_counter` operation when asserted high.
- **`check_sync` (output, 1-bit)**: Indicates when to check the correctness of the counter output.
- **`ref_modulo` (output, N-bit)**: Configurable modulo value, primarily used in modulo-N counting mode to define the counting range.
---
## **Module Functionality**
1. **Asynchronous Reset**:
- When `rst_in` is asserted HIGH, `o_count` is reset to `0`.
2. **Counting Modes**:
- The counter updates `o_count` based on `mode_in`:
- **Binary Up/Down Counting**: Increments or decrements the counter.
- **Modulo Counting**: Resets `o_count` when reaching `ref_modulo`.
- **Johnson Counter**: Implements shift-and-invert behavior.
- **Gray Code Counter**: Converts binary count to Gray code.
- **Ring Counter**: Circulates a single `1` through the bit positions.
3. **Enable Control**:
- If `enable_in = 0`, `o_count` remains unchanged.
---
## **Testbench Features**
- **Input Scenarios**:
- Cover all possible counter modes.
- Randomize `mode_in`, `enable_in`, and `ref_modulo` to simulate diverse use cases.
- **Simulation Observations**:
- Use `$monitor` to log counter transitions, mode changes, and reset events for debugging. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | generic_counter | uut | [
{
"name": "generic_counter.sv",
"content": "\nmodule generic_counter #(parameter N = 8) (\n input logic clk_in, // Clock input\n input logic rst_in, // Active HIGH Reset input\n input logic [2:0] mode_in, // Mode input (3 bits)\n input logic enable_in, // Enable input\n... | [] |
cvdp_copilot_endian_swapper_0004 | medium | Non-Agentic | Develop a **SystemVerilog testbench** to generate **input stimulus** for the **`endian_swapper`** module with **DATA_BYTES = 8** (64-bit data). The testbench must systematically **apply input sequences** to exercise different functional behaviors of the DUT, ensuring that **all edge cases, control signals, and buffering mechanisms are triggered**. The testbench **must not include any checker logic or pass/fail criteria**—it is purely **stimulus-driven**.
---
## **Design Details**
### **1. Functional Behavior**
The endian swapper module processes input data and optionally swaps byte order based on control register settings. It follows an AXI Stream-based handshake mechanism to handle input and output transactions while maintaining buffering for flow control.
#### **1.1 Parameters**
- **`DATA_BYTES = 8`** → Defines the **byte width** of the data stream (`64 bits`).
- **`CLK_PERIOD = 10 ns`** → The system runs at **100 MHz** (`clk` toggles every `5 ns`).
- **`TIMEOUT = 1000`** → Defines the **maximum wait cycles** for handshake events.
#### **1.2 Input Ports**
- `clk` → **100 MHz clock** controlling data transfer.
- `reset_n` → **Active-low reset** for DUT initialization.
- `stream_in_data [63:0]` → **64-bit input data bus**.
- `stream_in_empty [2:0]` → **Indicates number of unused bytes** in input.
- `stream_in_valid` → **Asserted when input data is valid**.
- `stream_in_startofpacket` → **Marks start of packet** in input stream.
- `stream_in_endofpacket` → **Marks end of packet** in input stream.
- `stream_out_ready` → **Downstream ready signal** for output transfer.
- `csr_address [1:0]` → **CSR register address**.
- `csr_read` → **CSR read enable**.
- `csr_write` → **CSR write enable**.
- `csr_writedata [31:0]` → **32-bit CSR write data**.
#### **1.3 Output Ports**
- `stream_in_ready` → **DUT ready to accept input data**.
- `stream_out_data [63:0]` → **64-bit output data bus**.
- `stream_out_empty [2:0]` → **Number of unused bytes** in output.
- `stream_out_valid` → **Asserted when output data is valid**.
- `stream_out_startofpacket` → **Start of packet in output stream**.
- `stream_out_endofpacket` → **End of packet in output stream**.
- `csr_readdata [31:0]` → **CSR readback value**.
- `csr_readdatavalid` → **Indicates valid CSR read response**.
- `csr_waitrequest` → **Indicates CSR access is stalled**.
---
## **Testbench Structure**
### **1. Clock Generation**
- Generate a **100 MHz clock** (`clk`) by toggling it **every 5 ns** (`CLK_PERIOD/2`).
### **2. Reset Sequencing**
- Assert `reset_n = 0` for a few clock cycles, then deassert it to **initialize the DUT**.
### **3. DUT Instantiation**
- Instantiate the `endian_swapper` module with **DATA_BYTES = 8** and connect all required input/output signals.
### **4. Stimulus Sequences**
The testbench must **apply a variety of test cases** to exercise input conditions, buffer behavior, and CSR interactions.
#### **4.1 AXI Stream Data Transfers**
- **Basic Operation (No Swap)** → Send a **64-bit word** with byte-swapping disabled.
- **Byte Swapping Enabled** → Enable byte-swapping via CSR and resend test data.
- **Packet Boundary Handling** → Send **multi-word packets** with `startofpacket` and `endofpacket` signals toggling.
#### **4.2 Flow Control and Buffering**
- **Flow Control Handling** → Deassert `stream_out_ready` while sending data, then re-enable it to test backpressure handling.
- **Buffering Mechanism** → Send **multiple packets** while `stream_out_ready` is **low**, then assert it to drain data.
#### **4.3 CSR Operations**
- **CSR Read/Write** → Perform CSR **write and readback** operations to configure DUT settings.
- **CSR Access in Middle of Packet** → Issue a **CSR read while data transfer is ongoing**, ensuring the DUT handles CSR operations correctly.
#### **4.4 Edge Cases**
- **Zero Data Handling** → Send an **all-zero 64-bit word** and observe behavior.
- **Maximum Data Handling** → Send an **all-ones 64-bit word** (`0xFFFFFFFFFFFFFFFF`).
- **Partial Empty Bytes** → Vary `stream_in_empty` values and observe how the DUT processes incomplete words.
---
## **Simulation Requirements**
### **1. Waveform Generation**
- Generate a **VCD waveform file** (`endian_swapper_tb.vcd`) for **post-simulation analysis**.
### **2. AXI Stream transactions**
- Ensure **proper handshake mechanisms** (`valid`-`ready` interactions) during **data transfer sequences**.
### **3. CSR and Data Processing Interactions**
- The testbench should **issue CSR commands mid-packet** and observe how the DUT handles **simultaneous control and data operations**.
---
Develop a **testbench** that:
- **Generates stimulus** to exercise `endian_swapper` across multiple functional scenarios.
- **Ensures input variations cover** normal operation, byte-swapping, packet boundaries, flow control, and CSR interactions.
- **Executes all predefined stimulus sequences** without assertions, output verification, or pass/fail conditions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | endian_swapper | dut | [
{
"name": "endian_swapper.sv",
"content": "module endian_swapper #(\n parameter DATA_BYTES = 8\n) (\n input wire clk,\n input wire reset_n,\n\n input wire [(DATA_BYTES*8)-1:0] stream_in_data,\n input wire [$clog2(DATA_BYTES)-1:0] strea... | [] |
cvdp_copilot_signed_adder_0003 | medium | Non-Agentic | Create a stimulus generating test bench in SystemVerilog for a Verilog module named `signedadder` that add or subtract two signed 2's complement numbers, controlled by input signals and a state machine. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
## 1. Instantiation
Name the instance of the RTL as dut.
## 2. DESIGN UNDER TEST (DUT)
The DUT is a **signed 2’s complement adder/subtractor** with a built-in state machine. It can:
- **Add** (`i_mode = 0`) or **Subtract** (`i_mode = 1`) two `DATA_WIDTH`-bit signed operands.
- **Detect Overflow** for signed operations.
- Operate in a **four-state** machine (IDLE → LOAD → COMPUTE → OUTPUT).
- **Parameter**: `DATA_WIDTH` (e.g., 8 bits)
### High-Level Data Flow
1. **IDLE**: Waits for `i_enable` and `i_start`.
2. **LOAD**: Latches `i_operand_a` and `i_operand_b`.
3. **COMPUTE**: Performs the requested arithmetic operation.
4. **OUTPUT**: Updates the outputs, asserts `o_ready`, then returns to **IDLE**.
---
## 3. INPUT AND OUTPUT EXPLANATION
### Inputs
1. **`i_clk`**
- **Function**: Clock for synchronous logic.
- **Usage**: Triggers all state transitions.
2. **`i_rst_n`** (Active-Low Reset)
- **Function**: Asynchronously resets the design.
- **Usage**: Forces module to **IDLE** state, clears registers, and zeroes outputs.
3. **`i_start`**
- **Function**: Triggers loading of operands when high (if `i_enable` is also asserted).
- **Usage**: Must be pulsed high while in **IDLE** to move the state machine to **LOAD**.
4. **`i_enable`**
- **Function**: Global enable for the module.
- **Usage**: If deasserted, the design will ignore `i_start` and revert or stay in **IDLE**.
5. **`i_mode`**
- **Function**: Selects the arithmetic operation.
- **Usage**:
- `0` → Addition (`o_resultant_sum = i_operand_a + i_operand_b`)
- `1` → Subtraction (`o_resultant_sum = i_operand_a - i_operand_b`)
6. **`i_clear`**
- **Function**: Immediately clears outputs and resets the state machine to **IDLE**.
- **Usage**: When high, forces result to 0 and moves to **IDLE**.
7. **`i_operand_a`, `i_operand_b`**
- **Function**: Signed 2’s complement inputs.
- **Usage**: Values to be added or subtracted.
### Outputs
1. **`o_resultant_sum`**
- **Function**: Provides the computed result (in signed 2’s complement).
- **Usage**: Valid only in **OUTPUT** state or once `o_ready` is high.
2. **`o_overflow`**
- **Function**: High if a **signed overflow** is detected.
- **Usage**: Check this after the **COMPUTE** cycle completes.
3. **`o_ready`**
- **Function**: Indicates that `o_resultant_sum` and `o_overflow` are valid.
- **Usage**: High in **OUTPUT** state, then returns low in **IDLE**.
4. **`o_status`** (2 bits)
- **Function**: Encodes the current state of the module.
- **Usage**:
- `00`: IDLE
- `01`: LOAD
- `10`: COMPUTE
- `11`: OUTPUT
---
## 4. BEHAVIOR EXPLANATION
1. **Reset Behavior**
- When `i_rst_n` is deasserted (low), internal registers and outputs are cleared, and the module returns to the **IDLE** state.
- The reset is asynchronous: the design responds immediately to `i_rst_n`.
2. **State Machine Flow**
- **IDLE (00)**: Default/wait state. The design transitions to **LOAD** if `i_enable` and `i_start` are high.
- **LOAD (01)**: Latches `i_operand_a` and `i_operand_b` into internal registers, preparing for computation.
- **COMPUTE (10)**: Performs addition or subtraction based on `i_mode`. Internal overflow logic is used to set `o_overflow`.
- **OUTPUT (11)**: Updates `o_resultant_sum` and `o_overflow`, asserts `o_ready`, and then goes back to **IDLE**.
3. **Overflow Detection**
- Triggered when the sign of the result indicates a signed overflow:
- Both operands positive, result negative.
- Both operands negative, result positive.
- `o_overflow` goes high if either condition is met.
4. **Clear Behavior**
- When `i_clear` is high, the design resets outputs and returns to **IDLE** no matter the current state.
---
## 5. STIMULUS LIST FOR 100% COVERAGE
Below is an outline of test scenarios and input sequences to exhaustively check each design feature, state, and boundary condition. **No actual code is provided**; only the conceptual approach to drive and observe the design is described.
### A. Reset and Basic State Transition Coverage
1. **Asserting `i_rst_n = 0` During Operation**
- **Objective**: Immediate reset to **IDLE**.
- **Process**:
- Start in **IDLE**.
- Assert `i_start` and `i_enable` to move to **LOAD**.
- While in **LOAD** or **COMPUTE**, drive `i_rst_n` low.
-
2. **Using `i_clear`**
- **Objective**: Immediate clear function at each state.
- **Process**:
- Begin in **IDLE** with `i_enable = 1`.
- Assert `i_start`, capture some operands in **LOAD**.
- Deassert `i_start`, go to **COMPUTE**, then drive `i_clear` high.
### B. Normal Addition Operations
3. **Simple Positive Addition**
- **Objective**: Correct addition for small positive numbers.
- **Process**:
- `i_operand_a = 5`, `i_operand_b = 10`, `i_mode = 0`, `i_start = 1`, `i_enable = 1`.
4. **Positive + Negative (No Overflow)**
- **Objective**: Sign handling when operands have opposite signs.
- **Process**:
- `i_operand_a = 15`, `i_operand_b = -5`, `i_mode = 0`.
5. **Boundaries with No Overflow**
- **Objective**: Approach boundary without triggering overflow.
- **Process**:
- For an 8-bit example: `i_operand_a = 127`, `i_operand_b = 0`, `i_mode = 0`.
### C. Overflow in Addition
6. **Positive Overflow**
- **Objective**: Detect overflow when adding two large positive numbers.
- **Process**:
- For 8-bit: `i_operand_a = 127`, `i_operand_b = 1`, `i_mode = 0`.
7. **Negative Overflow**
- **Objective**: Detect overflow with large negative numbers.
- **Process**:
- For 8-bit: `i_operand_a = -128` (0x80), `i_operand_b = -1`, `i_mode = 0`.
### D. Subtraction Operations
8. **Basic Positive Subtraction**
- **Objective**: standard subtraction.
- **Process**:
- `i_operand_a = 20`, `i_operand_b = 5`, `i_mode = 1`.
9. **Negative Result Subtraction**
- **Objective**: Check correct negative outcome.
- **Process**:
- `i_operand_a = 5`, `i_operand_b = 20`, `i_mode = 1`.
10. **Overflow in Subtraction**
- **Objective**: Trigger overflow from subtracting.
- **Process**:
- For 8-bit: `i_operand_a = 127`, `i_operand_b = -1`, `i_mode = 1`.
11. **No-Operation Cases**
- **Objective**: `i_enable = 0`, no transitions occur.
- **Process**:
- Keep `i_enable = 0`, pulse `i_start`. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | signedadder | dut | [
{
"name": "signedadder.v",
"content": "module signedadder #(parameter DATA_WIDTH = 8)(\n input i_clk,\n input i_rst_n,\n input i_start,\n input i_enable,\n input i_mode,\n input i_clear,\n input [DATA_WIDTH-1:0] i_operand_a,\n input [DATA_WIDTH-1:0] i_operand_b,\n output reg [DATA... | [] |
cvdp_agentic_dram_controller_0004 | hard | Agentic | I have a specification of a `dramcntrl` module in the `docs` directory. Write a SystemVerilog testbench `dramcntrl_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `dramcntrl` module.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the `dramcntrl` module as `dut`, appropriately connecting all input and output signals.
- **Clock Generation**: Use a 100 MHz clock with a 10ns period (`clk_in`).
- **Reset Procedure**: Create an `apply_reset` task that asserts reset for 10 cycles and deasserts it before the stimulus begins.
- **Basic Access Tasks**:
- `do_write`: A task to drive valid write sequences with address stimulus.
- `do_read`: A task to apply read transactions at given addresses.
- `do_concurrent_rd_wr`: A task to simultaneously assert read and write operations, switching address mid-transfer.
- **Stress and Coverage Stimulus**:
- Apply known address sequences to verify deterministic behavior.
- Generate back-to-back `WR` → `RD` transitions to stress arbitration.
- To test decoder coverage, access edge and extreme address ranges (`0x000000`, `0xFFFFFF`).
- Apply randomized traffic using `random_traffic()` and long idle intervals to activate auto-refresh logic.
- Use `saturate_no_of_refs` to increment `no_of_refs_needed` to its maximum value.
- Repeatedly toggle the `bus_term_from_up` signal during transactions to activate toggle paths and TB vector logic.
- Inject 1-cycle WR and RD pulses to target delayed signal conditions in the control FSM.
- Perform transactions during refresh/busy periods to stimulate FSM edge paths.
- Introduce reset mid-transaction to verify FSM recovery paths.
- Reapply reset and re-initialize stimulus to force reentry into all operational states.
- Run sequences that stimulate boundary and cross-bank transitions in memory addressing.
- Include random WR/RD accesses with idle spacing to activate slow paths and timeouts.
- **Final Execution**:
- Repeat WR/RD/idle sequences and concurrent access with varied spacing.
- Ensure maximum toggle and block coverage of counters and delay registers.
- Add display messages or timing comments only for traceability and debugging.
Do not include checkers, assertions, or internal state comparisons. The testbench should be structured strictly for applying input stimulus to the DUT and exercising its logic comprehensively. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | dramcntrl | dut | [
{
"name": "dramcntrl.sv",
"content": "`timescale 1ns / 1ps\n\nmodule dramcntrl \n#(\n //==========================================================================\n // Parameters\n //==========================================================================\n parameter integer del ... | [
{
"name": "specs.md",
"content": "## Overview\n\nAn SDRAM controller that manages DRAM initialization, auto-refresh, and read/write operations. It uses counters, state machines, and vector arithmetic (`incr_vec`/`dcr_vec`) to schedule commands and generate DRAM control signals (`addr`, `ba`, `clk`, `cke`, `... |
cvdp_copilot_csr_using_apb_0005 | medium | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `csr_apb_interface` module, which is responsible for data transactions over the Advanced Peripheral Bus (APB) interface.
## Interface: **csr_using_apb**
**Clock & Reset**:
`pclk`: APB clock input for synchronous operations.
`presetn`: Active-low asynchronous reset signal, used to initialize the system.
**Inputs & Outputs Ports**:
**APB Signals:**
`paddr` (input, 32 bits): Address bus to access the internal CSR registers.
`pselx` (input): APB select signal, indicates CSR selection.
`penable` (input): APB enable signal, signals transaction progression.
`pwrite` (input): Write enable signal, differentiating read and write operations.
`pwdata` (input, 32 bits): Write data bus to send data to CSR registers.
`pready` (output, reg): Ready signal indicating transaction completion.
`prdata` (output, reg, 32 bits): Read data bus for CSR data retrieval.
`pslverr` (output, reg): Error signal for invalid addresses or unsupported operations.
**Internal Registers**:
`DATA_REG (0x10)`: Stores two 10-bit values, data1 and data2, and a 12-bit reserved section.
`CONTROL_REG (0x14)`: Contains a control enable bit, mode bit, and 30 reserved bits.
`INTERRUPT_REG (0x18)`: Holds interrupt enable flags for various conditions and 28 reserved bits.
## Specifications
**Read Operations**:
- During the READ_STATE, assert pready and load prdata with the register value based on paddr.
- Return to IDLE after asserting pready for one cycle.
**Write Operations**:
- During the WRITE_STATE, assert pready and update the register selected by paddr with pwdata.
- For DATA_REG, split pwdata into fields for data1, data2, and the reserved section.
- For CONTROL_REG and INTERRUPT_REG, update only specified bits.
- Return to IDLE after asserting pready for one cycle.
**Reset Behavior**:
- On presetn deassertion, reset all outputs and internal registers to their default values:
- Set pready and pslverr to 0.
- Clear prdata.
- Initialize data1, data2, overflow_ie, sign_ie, parity_ie, and zero_ie to 0.
---
## **Testbench Requirements**
### **Instantiation**
- **Module Instance:** The **csr_apb_interface** module is instantiated as `uut`, with all input and output signals connected.
---
### **Input Generation**
#### **1. Writing to `DATA_REG`**
- The testbench writes a **random 32-bit value** to `DATA_REG`.
#### **2. Reading from `DATA_REG`**
- A read operation is performed from `DATA_REG`.
#### **3. Writing and Reading from `CONTROL_REG`**
- A **random 32-bit value** is written to `CONTROL_REG`.
- The value is read back.
#### **4. Writing and Reading from `INTERRUPT_REG`**
- A **random 32-bit value** is written to `INTERRUPT_REG`.
- The value is read back.
#### **5. Invalid Address Access**
- A write is attempted to an **unknown address (`0x20`)**.
#### **6. Read Transaction Without `pselx` Asserted**
- A read is attempted from `DATA_REG` **without asserting `pselx`**.
#### **7. Write Transaction Without `penable` Asserted**
- A write is performed to `CONTROL_REG` **without `penable` assertion**.
#### **8. Corner Cases for Write Data**
- **All 1s (`0xFFFFFFFF`)** and **all 0s (`0x00000000`)** are written to `DATA_REG`.
#### **9. Reset Behavior**
- The reset signal (`presetn = 0`) is applied in the middle of operations.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | csr_apb_interface | uut | [
{
"name": "csr_apb_interface.sv",
"content": "`timescale 1ns / 1ps\nmodule csr_apb_interface (\n input pclk, // Clock input for synchronization\n input presetn, // Active-low asynchronous reset input\n input [31:0] paddr, ... | [] |
cvdp_copilot_32_bit_Brent_Kung_PP_adder_0004 | medium | Non-Agentic | Complete the given partial System Verilog testbench `tb_brent_kung_adder`. The testbench must instantiate the `brent_kung_adder` RTL module and provide input stimulus for it focusing exclusively on generating comprehensive test vectors rather than building a full testbench. A Brent Kung Adder is a parallel prefix adder engineered for efficiently computing the sum of two 32-bit inputs along with a carry input.
## Description :
### Inputs :
Registers :
- `sum (32-bit,[31:0])` - 32-bit sum received from the UUT
- `carry_out(1-bit)` - 1-bit output carry received from the UUT.
### Outputs :
Registers :
- `a (32-bit,[31:0])` - 32-bit augend generated by TB to UUT.
- `b(32-bit,[31:0])` - 32-bit addend generated by TB to UUT.
- `carry_in(1-bit)` - 1-bit input carry generated by TB to UUT.
## Instantiation :
The testbench instantiates the `brent_kung_adder` module as uut and connects the signals between the module and the testbench. Each input and output from the UUT is connected to its corresponding signal in the testbench.
## Input Generation and Validation:
- Stimulus: Several test cases are applied to simulate various operations of the brent kung adder. These test cases cover a range of scenarios such as adding with smallest non-zero numbers, adding with largest numbers, random addends and augends, etc. For each case, the relevant signals (`sum`, `carry_out`) are followed immediately after the application of inputs (`a`,`b`,`carry_in`).
**Test Case 1: Zero inputs** :
- Description: Test the adder with all inputs set to zero, expecting no sum or carry-out.
**Test Case 2: Large positive numbers with no carry** :
- Description: Adds two large positive numbers (`0x7FFFFFFF`) with no carry-in, testing for proper addition without overflow.
**Test Case 3: Adding two large negative numbers, carry-out expected** :
- Description: Adds two large negative numbers (`0x80000000`), expecting a carry-out as the sum wraps around.
**Test Case 4: Numbers with different magnitudes**:
- Description: Tests the adder with numbers of different magnitudes (0x0000FFFF and 0xFFFF0000) to verify correct handling of mixed inputs.
**Test Case 5: Large numbers with carry-in** :
- Description: Adds two large numbers (`0xFFFFFFFF`) with carry-in, testing for correct propagation of carry during overflow.
**Test Case 6: Alternating 1's and 0's, no carry-in** :
- Description: Tests the adder with alternating 1's and 0's for each operand without a carry-in, verifying correct addition without any carries.
**Test Case 7: Random values with carry-in** :
- Description: Adds random values with carry-in, testing the adder’s ability to handle arbitrary inputs with carry propagation.
**Test Case 8: Large hexadecimal numbers** :
- Description: Adds large hexadecimal numbers (0xF0F0F0F0 and 0x0F0F0F0F) without carry-in, testing how the adder handles large numbers.
**Test Case 9: Random edge case with carry-in** :
- Description: Tests a random edge case with carry-in, checking for correct addition when both operands are large random values.
**Test Case 10: Random edge case, carry-out expected** :
- Description: Adds two large random values with carry-out expected, verifying that the adder correctly handles large random numbers and carry propagation.
**Test Case 11: Simple increasing values with carry-in** :
- Description: Adds simple increasing values (0x11111111 and 0x22222222) with carry-in, testing the adder with straightforward values and carry propagation.
**Test Case 12: Smallest non-zero inputs with carry-in** :
- Description: Adds the smallest non-zero values (0x00000001 and 0x00000001) with carry-in, verifying the adder’s handling of small values and carry propagation.
## Module Functionality :
- The brent-kung adder uses a parallel prefix tree approach to efficiently calculate the carry signals at each stage, which helps to reduce the delay for carry propagation.
- The adder computes the sum and carry-out by progressively calculating propagate and generate signals across multiple hierarchical stages (from P1/G1 to P6/G6).
- The carry signals (`C`) are generated in each stage by combining the results of the previous stage's propagate and generate signals.
- Finally, the sum is computed using the propagate signals XORed with the carry signals, and the carry-out is the final carry from the last stage.
The **different hierarchical stages of the brent_kung adder and their operations is as follows** :
**First Stage (P1 and G1 generation)**:
- The first stage computes the propagate (P1) and generate (G1) signals for each bit of a and b. The P1 signal indicates if there will be a carry from the previous bit, while the G1 signal indicates if there is a generate of carry at the current bit.
- `P1[i] = a[i] ^ b[i]`: Propagate signal for bit i.
- `G1[i] = a[i] & b[i]`: Generate signal for bit i.
**Second Stage (G2 and P2 generation)**:
- In this stage, the module generates the G2 and P2 signals for pairs of bits. The second stage is a hierarchical combination of G1 and P1 signals from the first stage.
For each pair of bits (i and i+1), the following calculations occur:
- `G2[i/2] = G1[i+1] | (P1[i+1] & G1[i])`: This computes the G2 signal, which tells if there is a carry generated by this pair of bits.
- `P2[i/2] = P1[i+1] & P1[i]`: This computes the P2 signal for the pair.
**Third Stage (G3 and P3 generation)**:
- The G3 and P3 signals are generated for groups of four bits.
- `G3[i/2] = G2[i+1] | (P2[i+1] & G2[i])`: This generates the G3 signal for each group of two G2 signals.
- `P3[i/2] = P2[i+1] & P2[i]`: This generates the P3 signal for each pair of P2 signals.
**Fourth Stage (G4 and P4 generation)**:
- The G4 and P4 signals are generated for groups of eight bits.
- `G4[i/2] = G3[i+1] | (P3[i+1] & G3[i])`: Combines G3 and P3 signals to generate G4.
- `P4[i/2] = P3[i+1] & P3[i]`: Combines P3 signals to generate P4.
**Fifth Stage (G5 and P5 generation)**:
- The next stage computes G5 and P5 signals, each for a group of 16 bits.
- `G5[i/2] = G4[i+1] | (P4[i+1] & G4[i])`: Combines G4 and P4 to generate G5.
- `P5[i/2] = P4[i+1] & P4[i]`: Combines P4 signals to generate P5.
**Sixth Stage (G6 and P6 generation)**:
- The final stage computes the G6 and P6 signals:
- `G6 = G5[1] | (P5[1] & G5[0])`: Combines G5 and P5 to generate G6.
- `P6 = P5[1] & P5[0]`: Combines P5 signals to generate P6.
**Carry Propagation (C array)**:
- The carry signals (C[i]) are computed by combining the G and P signals at each stage.
For example:
- `C[1] = G1[0] | (P1[0] & carry_in)`: The carry for the first bit is calculated based on the initial carry-in.
- Each subsequent C[i] is computed using the corresponding G and P signals from the previous stages, ensuring that carries are propagated through the entire adder.
**Final Sum and Carry-Out**:
- The final sum is computed as the XOR of the propagate signals and the carry signals:
- `sum = P1 ^ {C[31:1], carry_in}`: The sum is the bitwise XOR of the propagate signals (P1) and the carry signals (C).
- The final carry-out is the carry generated at the last stage:
- `carry_out = C[32]`: This is the final carry-out value.
**Partial Test Stimulus Generator Code** :
```verilog
module tb_brent_kung_adder;
logic [31:0] a;
logic [31:0] b;
logic carry_in;
logic [31:0] sum;
logic carry_out;
logic [31:0] start_time;
logic [31:0] end_time;
brent_kung_adder uut (
.a(a),
.b(b),
.carry_in(carry_in),
.sum(sum),
.carry_out(carry_out)
);
task measure_latency(input [31:0] start, input [31:0] end_time);
begin
$display("Latency = %t time units", end_time - start);
end
endtask
initial begin
a = 32'b0;
b = 32'b0;
carry_in = 0;
start_time = $time;
#10;
a = 32'b00000000000000000000000000000000;
b = 32'b00000000000000000000000000000000;
carry_in = 0;
#10;
end_time = $time;
measure_latency(start_time, end_time);
$display("Test Case 1: a = %h, b = %h, carry_in = %b, expected_sum = %h, expected_carry_out = %b , actual_sum = %h , actual_carry_out = %b", a, b, carry_in, sum, carry_out,sum,carry_out);
start_time = $time;
#10;
a = 32'h7FFFFFFF;
b = 32'h7FFFFFFF;
carry_in = 0;
#10;
end_time = $time;
measure_latency(start_time, end_time);
$display("Test Case 2: a = %h, b = %h, carry_in = %b, expected_sum = %h, expected_carry_out = %b , actual_sum = %h , actual_carry_out = %b", a, b, carry_in, sum, carry_out,sum,carry_out);
// Insert the code for the remaining test stimulus here
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | brent_kung_adder | uut | [
{
"name": "brent_kung_adder.sv",
"content": "module brent_kung_adder(\n input logic [31:0] a,\n input logic [31:0] b,\n input logic carry_in,\n output logic [31:0] sum,\n output logic carry_out\n);\n logic [31:0] P1, G1;\n logic [32:1] C;\n logic [15:0] G2, P2;\n logic [7:0] G3... | [] |
cvdp_agentic_door_lock_0003 | medium | Agentic | I have a specification of a `door_lock` module in the `docs` directory. Write a SystemVerilog testbench `tb_door_lock.sv` in the `verif` directory to only generate stimuli and achieve maximum coverage for the `door_lock` module.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the `door_lock` module as `door_lock_inst`, ensuring all input and output signals are properly connected for testing.
- **Clock Generation**: Implement a 10ns period clock.
- **Reset Procedure**: Include a reset task that initializes all inputs before stimulus is applied.
- **Password Entry Task**: Implement a task to drive a sequence of key inputs followed by confirmation. This task should support both correct and incorrect passwords.
- **Admin Override Task**: Create a task that drives the admin override sequence on the relevant signals.
- **Password Change Task**: Add a task to drive admin mode signals and provide a new password via stimulus.
- **Stimulus Scenarios**:
- Apply stimulus corresponding to a correct password entry.
- Apply stimulus for incorrect password entries.
- Apply stimulus for multiple incorrect attempts to trigger lockout-related behavior.
- Apply admin override stimulus.
- Apply a sequence to change the password via admin inputs, followed by stimulus for the new password.
- Generate random password sequences and apply them repeatedly to test behavior under stress.
Do not include checker logic or internal state validation. The testbench should be structured for applying input stimulus only and include display messages for traceability and debug. | [
{
"inst_name": "door_lock_inst",
"metric": "Overall Average",
"target_percentage": 95
}
] | door_lock | door_lock_inst | [
{
"name": "door_lock.sv",
"content": "module door_lock #(\n parameter PASSWORD_LENGTH = 4, // Number of digits in the password\n parameter MAX_TRIALS = 4 // Maximum allowed incorrect attempts\n) (\n input logic clk , // Clock signal\n input logic ... | [
{
"name": "specification.md",
"content": "# Door Lock System Specification Document\n\n## **Introduction**\nThe **Door Lock System** is a password-protected authentication module designed for **PIN-based access control** with a configurable password length. The module provides user authentication through pa... |
cvdp_copilot_secure_variable_timer_0006 | medium | Non-Agentic | Create a self-checking test bench in SystemVerilog for a Verilog module named `secure_variable_timer`. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
| **Port Name** | **Direction** | **Width** | **Description** |
|--------------------|---------------|-----------|------------------------------------------------------------------------------|
| `i_clk` | Input | 1 | Clock signal, rising-edge triggered. |
| `i_rst_n` | Input | 1 | Active-low synchronous reset signal. |
| `i_data_in` | Input | 1 | Serial data input for detecting the start pattern and configuring the delay. |
| `o_time_left` | Output | 4 | 4-bit output showing remaining time during the counting phase. |
| `o_processing` | Output | 1 | Asserted high when the timer is actively counting. |
| `o_completed` | Output | 1 | Asserted high when the timer completes its delay cycle. |
| `i_ack` | Input | 1 | Acknowledgment signal from the user to reset the timer after completion. |
---
### Functional Requirements
The module operates as a timer with the following behavior:
1. **Start Sequence Detection**:
- The timer begins when the serial data input (`i_data_in`) detects the bit sequence `1101` in the incoming stream.
2. **Delay Duration Configuration**:
- After detecting the `1101` sequence, the module reads the next 4 bits (most significant bit first) from the `i_data_in` input.
- These 4 bits define the delay value (`delay[3:0]`), which determines the timer duration.
3. **Counting Phase**:
- The timer counts for exactly ((delay[3:0] + 1) * 1000) clock cycles:
- Example: If `delay = 0`, the timer counts for 1000 cycles; if `delay = 5`, the timer counts for 6000 cycles.
- During this phase:
- The `o_processing` output is asserted high.
- The `o_time_left` output decrements as follows:
- Starts at `delay` for the first 1000 cycles.
- Decrements by 1 every subsequent 1000 cycles until reaching 0.
4. **Completion and Reset**:
- Once the counting phase completes:
- The `o_completed` signal is asserted high to notify the user.
- The module waits for the `i_ack` signal to reset itself and begin searching for the next `1101` sequence.
5. **Idle State**:
- When not actively counting:
- The `o_time_left` output is a don't-care value.
- The module resumes searching the `i_data_in` input for the `1101` sequence.
---
### Design Constraints
- **Clock and Reset**:
- On reset, the module enters the idle state, ready to search for the `1101` sequence.
- **Input Handling**:
- The `i_data_in` input is ignored during the counting phase.
- Only transitions to the configuration phase when the `1101` sequence is detected.
- **Output Behavior**:
- The `o_time_left` output is only valid during the counting phase and must correctly represent the remaining time as described.
---
### Implementation Notes
1. **State Machine Design**:
- Implement a finite state machine (FSM) to manage the following states:
- **Idle**: Search for the `1101` pattern in the `i_data_in` input.
- **Configure Delay**: Shift in the next 4 bits to set the delay value (`delay[3:0]`).
- **Counting**: Count for \((\text{delay[3:0]} + 1) \times 1000\) clock cycles.
- **Done**: Assert the `o_completed` output and wait for `i_ack` before resetting.
2. **Counting Logic**:
- Use a counter to count the total clock cycles required for the delay.
- Maintain a decrementing `o_time_left` output to reflect the remaining time.
---
## Stimulus generation
1. **Reset & Idle**
- Assert `i_rst_n=0`, then drive high.
2. **No Start Sequence**
- Feed random bits avoiding `1101`.
3. **Start Sequence Detection**
- Provide `1101` immediately, then incomplete 4-bit delay.
4. **Various Delay Values**
- After `1101`, supply 4-bit delays from `0000` to `1111`.
5. **Completion & Acknowledgment**
- Feed `1101 + valid_delay`; wait for `o_completed=1`.
- Assert `i_ack`;
6. **Overlapping Start Sequence**
- Input bit patterns like `11101` or `1101101`.
7. **Spurious Input During Count**
- Once counting, feed random `i_data_in`.
8. **Reset Mid-Count**
- While counting, assert `i_rst_n=0`.
-
9. **Consecutive Timers**
- Drive multiple `1101 + 4-bit` sequences back-to-back. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | secure_variable_timer | dut | [
{
"name": "secure_variable_timer.v",
"content": "module secure_variable_timer (\n input wire i_clk, // Clock signal (rising-edge triggered)\n input wire i_rst_n, // Active-low synchronous reset signal\n input wire i_data_in, // Serial data input\n output... | [] |
cvdp_copilot_IIR_filter_0016 | medium | Non-Agentic | Create a SystemVerilog testbench module named **`iir_filter_tb`** that instantiates the `iir_filter` module and applies stimulus to the instantiated module for different test scenarios.
---
### **Inputs**
- **Clock Signal**:
- `clk`: Positive edge-triggered clock signal driving the IIR filter.
- **Reset Signal**:
- `rst`: Asynchronous active-high reset signal to initialize the module.
- **Input Sample**:
- `x[15:0]`: A signed **16-bit input signal** representing the input samples to the filter.
### **Outputs**
- **Filtered Output**:
- `y[15:0]`: A signed **16-bit output signal** representing the filter's processed output.
---
## **Input Generation**
### **Test Stimulus**
The testbench systematically has to apply various input waveforms to the IIR filter under different conditions:
1. **Impulse Test**
- Apply a single nonzero value (`16'h4000`) followed by zeros.
2. **Step Test**
- Apply a **constant step input** (`16'h3000`) for a duration.
- filter stabilization and steady-state.
3. **Sinusoidal Input Test**
- Apply a **sine wave signal** at different frequencies and amplitudes.
- Evaluates frequency and phase shift characteristics.
4. **Ramp Input Test**
- Apply a **gradually increasing input** from a negative to positive value.
- Observes filter behavior in linear input variations.
5. **Noise Test**
- Apply **random noise samples** within a predefined amplitude range.
- Ensures the filter does not amplify undesired noise excessively.
6. **Stability Test**
- Apply a **constant DC input** and monitor output over an extended period.
- Ensures no instability, drift, or oscillations occur.
7. **Overflow Test**
- Apply **maximum and minimum possible values** (`16'h7FFF` and `16'h8000`).
- saturation handling and prevents wraparound errors.
8. **Frequency Sweep Test**
- Apply a **gradual frequency sweep** from a low to high frequency.
- Analyzes frequency over the full spectrum.
9. **Alternating Step Test**
- Alternates between two amplitude levels (`16'h3000` and `-16'h3000`).
- Checks transient to abrupt changes in input.
10. **Double Impulse Test**
- Sends **two impulses** separated by a specific delay.
- Evaluates filter behavior when multiple transient events occur.
11. **Max Amplitude Test**
- Continuously apply **maximum amplitude samples** (`16'h7FFF` and `16'h8000`).
- Ensures the filter does not produce unstable behavior.
---
## **Instantiation**
- The **`iir_filter`** instance in the testbench is named **`dut`**.
---
## **Module Interface**
### **Inputs**
- `clk`: Clock signal.
- `rst`: Asynchronous active-high reset.
- `x[15:0]`: 16-bit signed input sample.
### **Outputs**
- `y[15:0]`: 16-bit signed output sample.
---
## **Module Functionality**
1. **Filter Processing**
- The `iir_filter` processes the input sample `x` and produces a filtered output `y`.
2. **Reset Behavior**
- When `rst` is HIGH, the filter resets internal states, and `y` is cleared to `0`.
3. **Edge Cases**
- Handling of large amplitude signals without overflow.
- Stability under constant or repetitive input patterns.
--- | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | iir_filter | dut | [
{
"name": "iir_filter.sv",
"content": "module iir_filter (\n input logic clk,\n input logic rst,\n input logic signed [15:0] x, // Input sample\n output logic signed [15:0] y // Output sample\n);\n\n // Filter coefficients\n parameter signed [15:0] b0 = 16'h0F00;\n parameter signe... | [] |
cvdp_copilot_gcd_0028 | easy | Non-Agentic | Write a testbench to only generate stimulus for a `gcd_3_ip` that calculates the greatest common divisor (GCD) for three signed inputs, using the Euclidean algorithm, and generates the output `OUT` and `done` sequentially when `go` is asserted and inputs `A`, `B` and `C` are applied. In this design, the `OUT` output is generated over multiple clock cycles, and the output is considered valid when `done` is asserted.
The Euclidean algorithm calculates the GCD by iteratively replacing the larger of two numbers with the difference between the two numbers. This process is repeated, reducing the larger number each time, until the two numbers become equal. At this point, the value of either number is the GCD of the original inputs.
## Design Details
**Parameterization**
- `WIDTH` (Default 32, must be greater than 0 and less than 33): Bit-width of `A`, `B`, `C` and `OUT `.
- `SIGNED_EN` (Default 1): Enable (SIGNED_EN=1) or disable (SIGNED_EN=0) signed input handling.
**Functionality**
1. **Computation, Accumulation, and Output Stage**
- Computes the GCD of the three inputs and assigns to `OUT`, making it available as the final output.
2. **Done Signal Behavior**
- The `done` signal goes high after the `OUT` is fully computed and valid.
3. **Reset Behavior**
- `rst`: Active-high synchronous reset. When asserted high, it immediately clears all registers and outputs to 0, including `OUT`, `done`.
### Inputs and Outputs
- **Inputs**:
- `clk`: Clock signal. The design should be synchronized to the positive edge of this clock signal..
- `rst`: Active high synchronous reset signal.
- `A [WIDTH-1:0]`: Input value A.
- `B [WIDTH-1:0]`: Input value B.
- `C [WIDTH-1:0]`: Input value C.
- `go`: Start signal to initiate GCD calculation. Active high.
- **Outputs**:
- `OUT [WIDTH-1:0]`: Output for the calculated GCD.
- `done`: Active high signal that indicates when the computation is complete.
### Additional Details
- **Control Signal Behavior**:
- Both `go` and `done` are asserted high for one cycle.
- Once `done` is asserted, new inputs will be fed to the system on the current rising edge of `clk` following this assertion.
## Testbench requirements:
**Instantiation**
- Module Instance: The gcd_3_ip module should be instantiated as `dut`, with the input and output signals connected for testing.
---
**Input Generation**
- Input Generation: The testbench must generate inputs of WIDTH-bit binary values for `A`, `B` and `C` and 1-bit `go` to cover all possibilities, including the corner cases. Include negative values if SIGNED_EN is 1. Also test for input value 0.
- Computation Period: After setting each pair of inputs, the testbench should wait till assertion of `done` to ensure the outputs have stabilized, before asserting new values. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | gcd_3_ip | dut | [
{
"name": "gcd_top.sv",
"content": "`timescale 1ns/1ps\nmodule gcd_3_ip #(\n parameter WIDTH = 32,\n parameter SIGNED_EN = 1\n )(\n input clk,\n input rst,\n input [WIDTH-1:0] A,\n input [WIDTH-1:0] B,\n input [WIDTH-1:0] C,\n ... | [] |
cvdp_copilot_single_cycle_arbiter_0004 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `single_cycle_arbiter` module. This module implements a **fixed-priority, single-cycle arbitration** mechanism that grants exactly one request per cycle based on a priority scheme where **Port 0 has the highest priority** and **Port N-1 has the lowest priority**. The testbench must validate arbitration logic and priority enforcement and ensure proper handling of various request patterns, including edge cases.
---
### **Inputs:**
- `clk`: **Clock signal with a 10ns period.**
- `reset`: **Active-high reset signal.**
- `req_i`: **Request signal, `N`-bit wide, where each bit represents a request from a different source.**
### **Outputs:**
- `gnt_o`: **Grant signal, `N`-bit wide, indicating which request has been granted.**
---
### **Instantiation**
The testbench must instantiate a single instance of the `single_cycle_arbiter` module:
- **Primary Arbiter Module (`uut`)**: Instantiated with `N=8` to test typical request/grant scenarios.
---
### **Testbench Requirements**
The testbench must apply a **wide range of test patterns** covering various arbitration conditions:
1. **Clock Generation:**
- `clk` must toggle every **5 time units**, ensuring a **10 ns clock period**.
2. **Reset Handling:**
- `reset` must be **asserted for multiple cycles** before deasserting.
- The module must correctly initialize its outputs upon reset.
3. **Stimulus Generation Strategy:**
- The testbench **must not verify outputs** (only generate inputs).
- The following test sequences must be executed:
- **No Requests**: Ensure `gnt_o` remains inactive.
- **Single Request Activation**: Apply requests to individual ports one at a time.
- **Simultaneous Requests**: Apply multiple requests and observe prioritization.
- **Sequential Requests**: Shift requests sequentially over cycles to verify shifting behavior.
- **Randomized Testing**: Generate **50 iterations** of randomized request patterns.
- **Edge Cases**:
- **Simultaneous Multiple-Level Requests**: Activate requests at non-adjacent positions (e.g., `8'b11000110`).
- **Even-Indexed Requests Active**: Ensure correct arbitration for `8'b10101010`.
- **Odd-Indexed Requests Active**: Ensure correct arbitration for `8'b01010101`.
- **Alternating Request Patterns**: Exercise `8'b10011001`.
- **Back-to-Back Requests Across Cycles**: Apply requests in consecutive cycles while ensuring arbitration propagates.
- **Mid-Run Reset Handling**:
- Apply reset **during an ongoing arbitration sequence**.
- Apply new requests after reset to verify proper reinitialization.
4. **Handling Continuous and Edge Cases:**
- The testbench must ensure arbitration operates **correctly across all request patterns**.
- **High-frequency toggling** of requests must be exercised.
5. **Waveform Generation:**
- The testbench must generate a `.vcd` waveform file to allow waveform analysis.
---
### **Coverage and Compliance**
- The testbench must ensure **high coverage** across all possible arbitration conditions.
- The **DUT instance name `uut` must be explicitly used** for instantiation.
---
### **Test Plan Overview**
The testbench must ensure **96%+ input stimulus coverage** by applying:
- **Request arbitration testing** across different scenarios.
- **Edge case handling** for alternating and simultaneous requests.
- **Randomized input variations** to ensure robustness.
- **Pipeline behavior verification** to confirm proper priority enforcement.
- **Handling of multiple active requests** to validate correct grant selection.
This testbench will provide a **comprehensive input stimulus environment** for `single_cycle_arbiter`, ensuring correct operation under various test conditions.
---
### **Note:**
- The testbench **must only generate stimulus** without verifying outputs.
- The **DUT instance name `uut` must be explicitly used** for instantiation.
- **Ensure the maximum possible input coverage** without adding assertions or comparisons.
Can you implement a **SystemVerilog testbench** with the above stimulus requirements? | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 96
}
] | single_cycle_arbiter | uut | [
{
"name": "single_cycle_arbiter.sv",
"content": "module single_cycle_arbiter #(\n parameter N = 32\n) (\n input logic clk,\n input logic reset,\n input logic [N-1:0] req_i,\n output logic [N-1:0] gnt_o\n);\n\n // --------------------------------------------------------\n //... | [] |
cvdp_copilot_IIR_filter_0012 | medium | Non-Agentic | Complete the Given Partial SystemVerilog Testbench `iir_filt_tb`. The testbench must instantiate the `iir_filt` RTL module and provide input stimulus for it, focusing exclusively on generating comprehensive test vectors rather than building a full testbench. The IIR filter processes three input signals and outputs three corresponding filtered signals based on a selectable filter configuration.
---
## **Module Interface**
### **1. Inputs:**
- **`clk (1-bit)`**: Active high Clock signal that synchronizes operations within the filter logic.
- **` reset (1-bit)`**: Active-high Asynchronous reset signal that clears the internal states of the filter.
- **`in_1 [15:0] (16-bit, signed)`**: First input signal to the filter.
- **`in_2 [15:0] (16-bit, signed)`**: Second input signal to the filter.
- **`in_3 [15:0] (16-bit, signed)`**: Third input signal to the filter.
- **`filter_select [1:0] (2-bit, unsigned)`**: Filter selection signal that determines which filter coefficients are applied.
### **2. Outputs:**
- **`out_1 [15:0] (16-bit, signed)`**: Filtered output corresponding to `in_1`.
- **`out_2 [15:0] (16-bit, signed)`**: Filtered output corresponding to `in_2`.
- **`out_3 [15:0] (16-bit, signed)`**: Filtered output corresponding to `in_3`.
---
## **Instantiation:**
The testbench instantiates the `iir_filt` module as `uut` and connects the signals between the module and the testbench. Each input and output from the DUT is connected to its corresponding signal in the testbench.
---
## **Input Generation and:**
- **Clock Generation:** Active high clock signal `clk` toggles every 5 time units to simulate a 100 MHz clock.
- **Reset:** The reset signal `reset` is asserted at the beginning of the simulation to initialize the filter to a known state. After 20 time units, the reset is deasserted.
- **Stimulus:** Several test cases are applied to different filtering operations. These test cases, edge cases, stress conditions, dynamic switching, invalid input handling, to filter coefficient changes.
---
## **Test Cases:**
### **1. Edge Case Testing**
- Test extreme values such as maximum (`16'h7FFF`), minimum (`16'h8000`), alternating patterns (`16'hAAAA`), and zero (`16'h0000`).
### **2. Stress Testing**
- Apply 500 cycles of randomized input signals and `filter_select` values.
### **3. Dynamic Switching Test**
- Randomly change `filter_select` every 10 cycles while continuously providing input data.
- Ensure the filter transitions smoothly without abrupt artifacts.
### **4. Invalid `filter_select` Test**
- Iterate through all possible `filter_select` values (0 to 3), including out-of-range values.
### **5. Step Test**
- Apply a step input (`16'h1000`) and observe how the filter responds over multiple cycles.
- Reset input to zero and monitor the settling behavior.
### **6. Coefficient Transition Test**
- Apply a constant input and cycle through different `filter_select` values to test filter coefficient switching behavior.
### **7. Single Channel Test**
- Provide input to one channel at a time (`in_1`, `in_2`, `in_3`) while keeping the others zero.
### **8. All-Zero Input Test**
- Feed all-zero inputs and ensure that outputs remain zero across different filter selections.
### **9. Post-Reset Behavior Test**
- Apply input after reset, if the filter starts processing correctly.
### **10. Arithmetic Overflow Test**
- Test filter behavior when inputs are at saturation limits (`16'h7FFF` and `16'h8000`).
### **11. Filter Coefficient Combinations Test**
- Apply known values to the inputs and cycle through filter selections.
---
## **Module Functionality:**
- **Reset Handling:** The filter should correctly initialize all internal states upon reset.
- **Filter Processing:** The selected filter should be applied to the inputs, and the outputs should reflect the processed values.
- **Coefficient Switching:** Changing `filter_select` should update the filter behavior smoothly.
- **Input Dependency:** Each output should primarily depend on its respective input (`out_1` on `in_1`, `out_2` on `in_2`, etc.).
- **Saturation and Stability:** The filter should handle extreme values without causing instability.
---
```verilog
module iir_filt_tb();
// DUT Inputs
reg clk;
reg reset;
reg signed [15:0] in_1;
reg signed [15:0] in_2;
reg signed [15:0] in_3;
reg [1:0] filter_select;
// DUT Outputs
wire signed [15:0] out_1;
wire signed [15:0] out_2;
wire signed [15:0] out_3;
// Instantiate the DUT
iir_filt #(.WIDTH(16)) uut (
.clk(clk),
.reset(reset),
.in_1(in_1),
.in_2(in_2),
.in_3(in_3),
.filter_select(filter_select),
.out_1(out_1),
.out_2(out_2),
.out_3(out_3)
);
// Clock generation
initial clk = 0;
always #5 clk = ~clk; // 100 MHz clock
// Test procedure
initial begin
// Initialize inputs
reset = 1;
#20;
reset = 0;
$display("[%0t] DUT reset completed", $time);
// Edge case testing
$display("[%0t] Starting edge case testing", $time);
in_1 = 16'h7FFF; in_2 = 16'h8000; in_3 = 16'h7FFF; filter_select = 2'b00; #20;
in_1 = -16'h8000; in_2 = -16'h7FFF; in_3 = 16'h7FFF; filter_select = 2'b01; #20;
in_1 = 16'hAAAA; in_2 = 16'h5555; in_3 = 16'hAAAA; filter_select = 2'b10; #20;
in_1 = 16'h0000; in_2 = 16'h0000; in_3 = 16'h0000; filter_select = 2'b11; #20;
in_1 = 16'h1234; in_2 = 16'h5678; in_3 = 16'h9ABC; filter_select = 2'b00; #20;
$display("[%0t] Edge case testing completed", $time);
// Stress testing
$display("[%0t] Starting stress testing", $time);
reset = 1; #20; reset = 0;
repeat (500) begin
filter_select = $random % 4;
in_1 = $random;
in_2 = $random;
in_3 = $random;
#20;
end
$display("[%0t] Stress testing completed", $time);
// Insert the code for the remaining test cases here
// Finish simulation
$display("[%0t] Testbench simulation completed", $time);
$finish;
end
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 80
}
] | iir_filt | uut | [
{
"name": "iir_filt.sv",
"content": "module iir_filt #(parameter WIDTH = 16)(\n input clk,\n input reset,\n input signed [WIDTH-1:0] in_1,\n input signed [WIDTH-1:0] in_2,\n input signed [WIDTH-1:0] in_3,\n input [1:0] filter_select, // 00: Butterworth, 01: Chebyshev, 10: Elliptic\n out... | [] |
cvdp_copilot_skid_register_0004 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `skid_register` module. This module serves as a pipeline register with a skid buffer to handle backpressure. The testbench must simulate various scenarios to verify data flow, handshake mechanisms, and buffer operations.
---
### **Inputs:**
- `clk`: **1-bit clock signal**, toggling every **5 time units** (100MHz operation).
- `rst`: **Active-high reset signal** to initialize the module.
- `up_bus`: **8-bit data input from upstream**.
- `up_val`: **Valid signal from upstream indicating data presence**.
- `dn_rdy`: **Ready signal from downstream indicating it can accept data**.
### **Outputs:**
- `up_rdy`: **Ready signal from the module for upstream communication**.
- `dn_bus`: **8-bit data output to the downstream**.
- `dn_val`: **Valid signal for downstream data**.
---
### **Instantiation**
The testbench must instantiate a single instance of the `skid_register` module:
- **Skid Register Module (`dut`)**: Instantiated with its default configuration to verify data buffering and pipeline behavior.
---
### **Testbench Requirements**
The testbench must apply a **wide range of test patterns** covering various operating conditions of the `skid_register` module:
1. **Clock Generation:**
- `clk` must toggle every **5 time units**, ensuring a **10 ns clock period**.
2. **Reset Handling:**
- `rst` must be **asserted at the beginning** of the simulation for **three cycles**.
- The module must correctly initialize internal registers when `rst` is de-asserted.
3. **Stimulus Generation Strategy:**
- The testbench **must not verify outputs** (only generate inputs).
- The following test sequences must be executed:
- **No Backpressure (50 cycles)**: `dn_rdy` asserted while `up_val` and `up_bus` receive random values.
- **Full Backpressure (20 cycles)**: `dn_rdy` de-asserted to stall downstream data flow.
- **Random Backpressure (100 cycles)**: `dn_rdy` toggles randomly while `up_val` sends variable data.
- **Pipeline Flush (20 cycles)**: Ensure buffered data is correctly forwarded when `dn_rdy` remains asserted.
- **Multiple Data Transactions**: Apply various input patterns to check how the module buffers and forwards data.
- **Randomized Data Sequences**: Generate multiple upstream and downstream handshake variations.
- **Continuous Streaming Mode**: Test without stalls to check smooth data flow.
- **Pipeline Stall and Restart**: Temporarily hold `dn_rdy` low and later assert it to observe how the module resumes.
- **Edge Case Timing Conditions**: Stress test with fast-changing `up_val` and `dn_rdy` transitions.
4. **Handling Continuous and Edge Cases:**
- The testbench must ensure a **full range of data transactions** occur correctly.
- **Edge cases of data buffering** must be exercised to verify stall and release conditions.
5. **Waveform Generation:**
- The testbench must generate a `.vcd` waveform file to allow waveform analysis.
---
### **Coverage and Compliance**
- The testbench must ensure **high coverage** across all pipeline behaviors and backpressure conditions.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
---
### **Test Plan Overview**
The testbench must ensure **comprehensive RTL coverage** by applying:
- **Valid data transfers** under continuous downstream availability.
- **Stall conditions** when downstream is blocked.
- **Randomized test scenarios** for data and handshake signals.
- **Buffer management validation** under varied input sequences.
- **Reset handling** to verify asynchronous initialization integrity.
- **High-frequency toggling of control signals** to test robustness.
- **Back-to-back input bursts and sporadic handshakes** to assess real-world performance.
This testbench should provide a **comprehensive input stimulus environment** for `skid_register`, ensuring correct operation under various test conditions.
---
### **Note:**
- The testbench **must only generate stimulus** without verifying outputs.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
- **Ensure the maximum possible input coverage** without adding assertions or comparisons.
Can you implement a **SystemVerilog testbench** with the above stimulus requirements? | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | skid_register | dut | [
{
"name": "skid_register.sv",
"content": "module skid_register\n #(parameter DATA_WIDTH = 32)\n(\n input wire clk,\n input wire rst,\n\n // Upstream (source) side\n input wire [DATA_WIDTH-1:0] up_bus,\n input wire up_val,\n ... | [] |
cvdp_copilot_asyc_reset_0004 | easy | Non-Agentic | Create a **testbench** to apply **stimulus** to the `async_reset` module. This module implements an asynchronous reset mechanism along with a countdown counter. The counter initializes to `5'h1F` upon reset and decrements on each clock cycle until reaching zero. The module also provides gated clock and reset release signals based on specific counter thresholds.
---
### **Inputs:**
- `clk`: **Clock input** for driving the module’s sequential logic.
- `reset`: **Active-high, asynchronous reset signal**. When asserted, the counter resets to `5'h1F`.
### **Outputs:**
- `cnt_q [4:0]`: **5-bit counter output**, representing the current counter value.
- `gate_clk_o`: **Gated clock output**, enabled when the counter is greater than zero and less than `5'hE`.
- `release_reset_o`: **Reset release output**, active when the counter is less than `5'h8`.
---
### **Instantiation**
The testbench must instantiate a single instance of the `async_reset` module:
- **Asynchronous Reset Module (`dut`)**: Instantiated with its default configuration to verify correct counter behavior and reset handling.
---
### **Testbench Requirements**
The testbench must apply a **wide range of test patterns** to verify the module’s response to various reset and counter conditions:
1. **Clock Generation:**
- `clk` must toggle every **5 time units**, ensuring a **10 ns clock period**.
2. **Reset Handling:**
- `reset` must be **asserted for multiple clock cycles** before being de-asserted.
- The module must correctly initialize `cnt_q` to `5'h1F` when `reset` is de-asserted.
3. **Stimulus Generation Strategy:**
- The testbench **must not verify outputs** (only generate inputs).
- The following test sequences must be executed:
- **Counter decrement sequence**: Verify decrement from `5'h1F` to `0`.
- **Mid-count reset**: Apply reset when `cnt_q = 5'hF` and ensure re-initialization.
- **Gate clock boundary**: Ensure `gate_clk_o` transitions correctly when `cnt_q` moves from `5'hE` to `5'hD`.
- **Release reset boundary**: Validate `release_reset_o` activation when `cnt_q` moves below `5'h8`.
- **Counter stability at zero**: Ensure `cnt_q` holds at `0` after reaching the minimum value.
- **Reset during critical transitions**: Apply reset at `cnt_q = 5'hE` and `cnt_q = 5'h8`.
4. **Handling Continuous and Edge Cases:**
- The testbench must ensure a **full countdown cycle** occurs correctly.
- **Edge case transitions** must be included to verify correct signal toggling.
5. **Waveform Generation:**
- The testbench must generate a `.vcd` waveform file to allow waveform analysis.
---
### **Coverage and Compliance**
- The testbench must ensure **high coverage** across all counter states and transitions.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
---
### **Test Plan Overview**
The testbench must ensure **comprehensive RTL coverage** by applying:
- **Full counter sequence testing** (from `5'h1F` to `0`).
- **Timing-based reset checks** (handling valid reset during key transitions).
- **Mid-count resets** to ensure proper re-initialization.
- **Boundary conditions** for `gate_clk_o` and `release_reset_o`.
- **Reset handling** to verify asynchronous behavior and re-initialization integrity.
This testbench will provide a **comprehensive input stimulus environment** for `async_reset`, ensuring correct operation under various test conditions.
---
### **Note:**
- The testbench **must only generate stimulus** without verifying outputs.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
- **Ensure the maximum possible input coverage** without adding assertions or comparisons.
Can you implement a **SystemVerilog testbench** with the above stimulus requirements? | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | async_reset | dut | [
{
"name": "async_reset.sv",
"content": "module async_reset (\n input logic clk,\n input logic reset,\n\n output logic release_reset_o,\n output logic gate_clk_o,\n output logic [4:0] cnt_q\n);\n\n// --------------------------------------------------------\n// Asynchr... | [] |
cvdp_copilot_nbit_swizzling_0009 | easy | Non-Agentic | Write a SystemVerilog testbench for a `nbit_swizzling` module that performs bitwise operations on input data based on a selection signal(`sel`). The testbench should only provide a sequence of test cases to the instantiated RTL module for nbit-swizzling transformations based on the selection signal and ensure proper synchronization of different input signals.
## Description
**Parameters:**
- `DATA_WIDTH`: Defines the data width of the input and output signals. (default: 16)
**Inputs:**
- `data_in ([DATA_WIDTH-1:0])`: The input data to be swizzled.
- `sel ([1:0])`: Selection signal controlling the swizzling mode.
**Outputs:**
- `data_out([DATA_WIDTH-1:0])`: The swizzled output data.
## Module Description
The `nbit_swizzling` module takes an N-bit input (`data_in`) and performs different bit-swizzling transformations based on the selection signal (`sel`).
The behavior of `nbit_swizzling` is controlled by `sel`:
- **`sel = 2'b00`**: Complete bitwise reversal of `data_in`.
- **`sel = 2'b01`**: Swap upper and lower halves of `data_in`.
- **`sel = 2'b10`**: Swap quarter sections of `data_in`.
- **`sel = 2'b11`**: Swap eighth sections of `data_in`.
- **`Default:`** `data_out` equals to `data_in`.
**Edge Cases:**
- `DATA_WIDTH` must be at least 16 and a multiple of 8.
- The design(`nbit_swizzling`) must be implemented as combinational logic.
## Testbench Requirements
### Module Instantiation:
- The `nbit_swizzling` module should be instantiated as uut, with all input and output signals properly connected. The testbench must achieve **100% coverage** by covering all input cases.
### Input Stimulus Generation
The testbench implements six test cases, each designed to validate a specific functionality:
**Test 1: full_reverse**
- Repeat 1000 times. Set `sel` = 2'b00.
- Apply random values of `data_in` value in the range 0 to (2**`DATA_WIDTH`)-1.
**Test 2: half_reverse**
- Repeat 1000 times. Set `sel` = 2'b01.
- Apply random values of `data_in` value in the range 0 to (2**`DATA_WIDTH`)-1.
**Test 3: quarter_reverse**
- Repeat 1000 times. Set `sel` = 2'b10.
- Apply random values of `data_in` value in the range 0 to (2**`DATA_WIDTH`)-1.
**Test 4: eighth_reverse**
- Repeat 1000 times. Set `sel` = 2'b11.
- Apply random values of `data_in` value in the range 0 to (2**`DATA_WIDTH`)-1.
**Test 5: unknown_test**
- Repeat 1000 times. Randomize `data_in`. Set `sel` = 2'bxx.
- Validate the module's stability across different input patterns.
**Test 6: random_test**
- Repeat 1000 times. Randomize `sel` and `data_in`.
- Validate the module's stability across different input patterns.
**Synchronization**
- After applying the new randomized inputs(`data_in` and `sel`), wait for **#10ns** before checking the outputs.
Can you implement a SystemVerilog testbench with the above specifications to thoroughly validate all test cases? | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | nbit_swizzling | uut | [
{
"name": "nbit_swizzling.sv",
"content": "module nbit_swizzling #(parameter DATA_WIDTH = 64)(\n input [DATA_WIDTH-1:0] data_in, // Input data of size DATA_WIDTH \n input [1:0] sel, \t // 2-bit selection signal ... | [] |
cvdp_copilot_hill_cipher_0012 | easy | Non-Agentic | Create a testbench to generate the stimuli for the `hill_cipher` module, which applies a 3×3 key matrix to a 3-letter (15-bit) plaintext vector, computing the ciphertext (also 3 letters, 15 bits) modulo 26.
---
## Description
### Inputs
- **Registers**:
- `clk (1 bit)`: Clock signal that drives the internal finite state machine (FSM) and arithmetic logic.
- `reset (1 bit)`: Active-high, synchronous reset that clears all registers and returns the module to the `IDLE` state.
- `start (1 bit)`: A strobe signal indicating the module should begin computing the ciphertext for the provided `plaintext` and `key`.
- `plaintext (15 bits)`: Three letters, each 5 bits, forming the message to encrypt.
- `key (45 bits)`: A 3×3 matrix of 9 elements, each 5 bits, used to multiply the plaintext vector in the Hill Cipher algorithm.
### Outputs
- **Wires**:
- `ciphertext (15 bits)`: The resulting 3-letter (5 bits per letter) encrypted output.
- `done (1 bit)`: Goes high for one cycle when the module finishes encryption, signaling the `ciphertext` is valid.
---
## Input Generation
- **Random Input Generation**:
The testbench provides random 15-bit values for `plaintext` (covering possible 3-letter combinations) and 45-bit values for `key` (covering random 3×3 matrices). These random tests help uncover boundary issues and verify the FSM’s transitions.
- **Directed Patterns**:
The testbench also applies specific edge-case values for `plaintext` and `key`, such as:
- `plaintext = 15'h0000` (all zeros).
- `key = 45'h0000000000` (all zeros).
- Maximal or near-maximal values to ensure the modulo operations function correctly.
- Sequences that check if multiple consecutive encryption requests work as intended.
---
## Stabilization Period
- The testbench asserts `start` for **one clock cycle** after setting `plaintext` and `key`.
- It then waits until `done` goes high, indicating the FSM has advanced through `COMPUTE`, `COMPUTE_MOD`, and finally `DONE`.
- Once `done=1`, the testbench samples `ciphertext` and logs the result.
---
## Instantiation
Name the instance of the module as `uut`.
---
Follows the specification for building the RTL of the module, use it as reference for the verification environment too:
### Module Interface
1. **Inputs**:
- `clk (1 bit)`
- `reset (1 bit)`
- `start (1 bit)`
- `plaintext [14:0]`
- `key [44:0]`
2. **Outputs**:
- `ciphertext [14:0]`
- `done`
### Module Functionality
Instead of viewing the key as a matrix, consider it as **9 separate 5-bit key elements**, grouped in **3 sets** (each set has 3 elements). The `plaintext` is **3 letters**, each 5 bits. The module computes each output letter as follows:
1. **Multiply & Sum**:
For one of the 3 output letters, the module multiplies each of the 3 plaintext letters (5 bits each) by the corresponding key element in that set. It then adds these 3 products together.
2. **Modulo Operation**:
Because we want each letter to stay in the range `0–25` (the alphabet size), the module takes the sum **modulo 26**. This final value (0–25) becomes one letter of the encrypted output.
3. **Three Times**:
The module repeats Steps 1 and 2 for each of the **3 sets** of key elements, creating **3 encrypted letters**.
4. **Finite State Machine**:
- **IDLE**: Waits until `start` is asserted.
- **COMPUTE**: Calculates partial sums (multiply-and-add) for each of the 3 output letters.
- **COMPUTE_MOD**: Finalizes each sum modulo 26, storing the results in internal registers for `ciphertext`.
- **DONE**: Pulses `done=1` for one clock cycle to signal the `ciphertext` is valid, then returns to IDLE.
5. **Reset**:
When `reset` is asserted, the FSM returns to `IDLE`, and internal registers are cleared. The outputs (`ciphertext`, `done`) remain in their initial states (zeros) until the next valid compute cycle.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | hill_cipher | uut | [
{
"name": "hill_cipher.sv",
"content": "`timescale 1ns/1ps\n\nmodule hill_cipher (\n input logic clk,\n input logic reset,\n input logic start,\n input logic [14:0] plaintext, // 3 letters, 5 bits each\n input logic [44:0] key, // 9 elements, 5 bits each\n output logic [14:0] cip... | [] |
cvdp_copilot_matrix_multiplier_0022 | easy | Non-Agentic | Write a testbench for the `matrix_multiplier` module, which performs matrix multiplication for configurable dimensions. The testbench should focus only on generating stimuli to exercise all key features of the module.
---
## Design Details
### **Parameterization**
1. **ROW_A**: Number of rows in Matrix A. (Default=4)
2. **COL_A**: Number of columns in Matrix A. (Default=4)
3. **ROW_B**: Number of rows in Matrix B. (Default=4)
4. **COL_B**: Number of columns in Matrix B. (Default=4)
5. **INPUT_DATA_WIDTH**: Bit-width of the input matrix elements. (Default=8)
6. **OUTPUT_DATA_WIDTH**: Bit-width of the output matrix elements, calculated as `(INPUT_DATA_WIDTH * 2) + $clog2(COL_A)`.
### **Inputs and Outputs**
- **Inputs**:
- `clk`: Clock signal (positive edge-triggered).
- `srst`: Active-high synchronous reset signal.
- `valid_in`: Active high signal, indicates that `matrix_a` and `matrix_b` contain valid inputs.
- `[(ROW_A*COL_A*INPUT_DATA_WIDTH)-1:0] matrix_a`: Flattened 1D representation of input Matrix A.
- `[(ROW_B*COL_B*INPUT_DATA_WIDTH)-1:0] matrix_b`: Flattened 1D representation of input Matrix B.
- **Outputs**:
- `valid_out`: Active high signal, indicates that the output matrix `matrix_c` is valid.
- `[(ROW_A*COL_B*OUTPUT_DATA_WIDTH)-1:0] matrix_c`: Flattened 1D representation of the result Matrix C.
### Example of Matrix Flattening:
Suppose you have two input matrices A and B to multiply:
- **Matrix A (2x3)**:
```text
| a11 a12 a13 |
| a21 a22 a23 |
```
- **Matrix B (3x2)**:
```text
| b11 b12 |
| b21 b22 |
| b31 b32 |
```
The resulting output matrix from the multiplication of the above matrices would be:
- **Matrix C (2x2)**:
```text
| c11 c12 |
| c21 c22 |
```
The flattened representation of these matrices will be as follows:
- **Flattened Matrix A (2x3)**:
```text
matrix_a = {a23, a22, a21, a13, a12, a11}
```
- **Flattened Matrix B (3x2)**:
```text
matrix_b = {b32, b31, b22, b21, b12, b11}
```
- **Flattened Matrix C (2x2)**:
```text
matrix_c = {c22, c21, c12, c11}
```
- **Note** : The design enables the processing of a new input set (matrix_a, matrix_b, and valid_in) in every clock cycle while maintaining a latency of $clog2(COL_A) + 2 clock cycles from valid_in to valid_out.
---
### Testbench Requirements
#### Instantiation
- Instantiate the `matrix_multiplier` module as `matrix_multiplier_inst`, connecting all input and output signals.
- Support configurable matrix sizes using defines:
- **`MATRIX_MULT_2x2`**: Sets `ROW_A = 2`, `COL_A = 2`, `ROW_B = 2`, `COL_B = 2`.
- **`MATRIX_MULT_3x3`**: Sets `ROW_A = 3`, `COL_A = 3`, `ROW_B = 3`, `COL_B = 3`.
- **`NON_SQUARE_MATRIX_MULT`**: Sets `ROW_A = 2`, `COL_A = 3`, `ROW_B = 3`, `COL_B = 2`.
- **`MATRIX_MULT_1x1`**: Sets `ROW_A = 1`, `COL_A = 1`, `ROW_B = 1`, `COL_B = 1`.
- **Default Configuration**: If no define is enabled, use `ROW_A = 4`, `COL_A = 4`, `ROW_B = 4`, `COL_B = 4`.
---
### **Stimulus Generation**
1. **Randomized Inputs**:
- Generate random values for `matrix_a` and `matrix_b` based on their respective dimensions (`ROW_A x COL_A` for Matrix A and `ROW_B x COL_B` for Matrix B).
- Randomly toggle the `valid_in` signal to mimic varying input availability.
2. **Control Signals**:
- Assert `srst` at the start of the simulation to reset the pipeline and output.
- Randomly toggle `valid_in` during operation to simulate intermittent valid input availability.
3. **Continuous Stimulus**:
- Continuously provide randomized `matrix_a` and `matrix_b` inputs for the duration of the simulation to ensure complete coverage of the RTL. | [
{
"inst_name": "matrix_multiplier_inst",
"metric": "Overall Average",
"target_percentage": 100
}
] | matrix_multiplier | matrix_multiplier_inst | [
{
"name": "matrix_multiplier.sv",
"content": "module matrix_multiplier #(\n parameter ROW_A = 4 , // Number of rows in matrix A\n parameter COL_A = 4 , // Number of columns in matrix... | [] |
cvdp_agentic_bcd_adder_0006 | easy | Agentic | I have a `bcd_adder` module implemented in the RTL directory. Write a SystemVerilog testbench `tb_bcd_adder.sv` in the verif directory that generates stimuli to thoroughly test and achieve maximum coverage for the bcd_adder module.
Include the following in the generated testbench:
### Module Instance
Instantiate the `bcd_adder` module as `uut`, ensuring all input and output ports (`a`, `b`, `sum`, `cout`, `invalid`) are properly connected.
### Test Stimulus Task
Implement a reusable task `bcd_addition` that drives inputs `a` and `b` with 4-bit values and displays the outputs with context for traceability and debug.
### Test Scenarios
- Apply all combinations of 4-bit inputs from 0 to 15 for both `a` and `b` to test BCD-valid and BCD-invalid input pairs.
- Display the results of each operation with `a`, `b`, `sum`, `cout`, and `invalid` values.
- Highlight test coverage for both valid and invalid BCD inputs.
### Test Execution Control
- Include a task that systematically iterates over all input combinations using nested loops.
- Print headers and structured logs for traceability.
### Simulation Control
- Use an initial block to trigger the tests and call `$finish` after completion.
- Include waveform dumping via `$dumpfile` and `$dumpvars` for post-simulation analysis.
Do not include scoreboard/checker logic or internal assertions. The testbench should focus solely on stimulus generation and visibility into the DUT response for debug purposes. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | bcd_adder | uut | [
{
"name": "four_bit_adder.sv",
"content": "//module of four_bit_adder\nmodule four_bit_adder( \n input [3:0] a, // 4-bit input a\n input [3:0] b, // 4-bit input b\n input cin, // Carry input\n ... | [
{
"name": "bcd_adder_spec.md",
"content": "# BCD Adder Module (bcd_adder)\n\nThis module adds two 4-bit BCD numbers and ensures the result remains in valid BCD form (0–9 per digit). It first detects invalid inputs (values above 9) and clamps them to 9 before performing the addition. If the intermediate resu... |
cvdp_copilot_decode_firstbit_0017 | medium | Non-Agentic | Create a **testbench** to apply **stimulus** to the `cvdp_copilot_decode_firstbit` module. This module detects the first set bit in a **32-bit binary input** and outputs its position in either **binary or one-hot encoding**. The testbench must generate a diverse set of input patterns while ensuring compliance with the module’s **clocking, reset, and pipeline behavior**.
---
### **Inputs:**
- `Clk`: **1-bit clock signal**, toggling every **5 time units** (100MHz operation).
- `Rst`: **Active-high reset signal** to initialize the module.
- `In_Data`: **32-bit input bus** for data values.
- `In_Valid`: **Signal indicating valid input data**.
### **Outputs:**
- `Out_FirstBit`: **Position of the first set bit** (Binary or One-Hot encoded).
- `Out_Found`: **Indicates if a set bit was found**.
- `Out_Valid`: **Indicates valid output data**.
---
### **Module Specifications for Stimulus Generation**
The `cvdp_copilot_decode_firstbit` module supports configurable first-bit detection with the following key parameters:
- **Input Processing:**
- Detects **first set bit** from LSB to MSB.
- Supports **optional input registers (`InReg_g`)**.
- **Output Processing:**
- Provides index in **Binary or One-Hot encoding (`OutputFormat_g`)**.
- Supports **optional output registers (`OutReg_g`)**.
- **Pipeline Stages:**
- Configurable **pipeline registers (`PlRegs_g`)** for adjustable latency.
- **Clock and Reset Behavior:**
- Operates on the **rising edge** of `Clk`.
- Initializes internal registers upon `Rst` assertion.
---
### **Instantiation**
The testbench must instantiate a single instance of the `cvdp_copilot_decode_firstbit` module with instantiation name `dut`:
- **Decode First Bit Module (`dut`)**: Instantiated with the following parameter values:
- `InWidth_g = 32`
- `InReg_g = 0`
- `OutReg_g = 0`
- `PlRegs_g = 0`
- `OutputFormat_g = 0` (Binary Encoding)
---
### **Testbench Requirements**
The testbench must apply a **wide range of test patterns** covering various input scenarios:
1. **Clock Generation:**
- `Clk` must toggle every **5 time units**, ensuring a **100MHz clock period**.
2. **Reset Handling:**
- `Rst` must be **asserted at the beginning** of the simulation for **three cycles**.
- The module must be **initialized properly** before input stimulus is applied.
3. **Stimulus Generation Strategy:**
- The testbench **must not verify outputs** (only generate inputs).
- Generate input patterns covering:
- **Single-bit set inputs**.
- **All-zero inputs**.
- **Multiple-bit patterns**.
- **Random bit patterns**.
- **First-bit at different positions**.
- **First and last bit set**.
- **Changing valid input sequences**.
- **Pipeline latency variations**.
4. **Handling Consecutive and Random Inputs:**
- The testbench must ensure **continuous valid input scenarios** are covered.
- Include **randomized sequences** to simulate realistic DUT behavior.
5. **Reset in Mid-Operation:**
- The testbench should **toggle reset during execution** to ensure the module properly re-initializes.
---
### **Coverage and Compliance**
- The testbench must ensure **high coverage** across all input variations.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
- The **RTL should not be in context** but will be provided in `/harness/<issue number>/src/`.
---
### **Test Plan Overview**
- **Basic input cases** (all zeros, single-bit set, multiple bits set).
- **Timing-based tests** (handling valid input over consecutive cycles).
- **Randomized patterns** to ensure robustness.
- **Pipeline configuration tests** to validate latency effects.
- **Reset handling** to verify re-initialization integrity.
This testbench should provide a **comprehensive input stimulus environment** for `cvdp_copilot_decode_firstbit`, ensuring correct operation across multiple configurations.
---
### **Note:**
- The testbench **must only generate stimulus** without verifying outputs.
- The **DUT instance name `dut` must be explicitly used** for instantiation.
- **Ensure the maximum possible input coverage** without adding assertions or comparisons.
Can you implement a **SystemVerilog testbench** with the above stimulus requirements? | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
}
] | cvdp_copilot_decode_firstbit | dut | [
{
"name": "cvdp_copilot_decode_firstbit.sv",
"content": "module cvdp_copilot_decode_firstbit #(\n parameter integer InWidth_g = 32,\n parameter InReg_g = 1,\n parameter OutReg_g = 1,\n parameter integer PlRegs_g = 1,\n parameter OutputFormat_g = 0 // 0: Binary, 1: One-Hot Encoding\n)(\n i... | [] |
cvdp_copilot_cdc_pulse_synchronizer_0017 | easy | Non-Agentic | Complete the given SystemVerilog testbench for the `cdc_pulse_synchronizer` module. The testbench currently instantiates the UUT and should include a stimulus generator (`stimulus_generator`) that dynamically produces a wide range of test scenarios to ensure 100% functional and code coverage. The stimulus generator should validate the design under various conditions, including the below module functionality.
---
## Description
### Inputs
- `src_clock`: Source clock signal driving the source domain(positive edge triggered).
- `des_clock`: The destination clock signal drives the destination domain(positive edge triggered).
- `rst_in`: The Asynchronous reset signal (active high) to reset the synchronizer.
- `src_pulse`: The input pulse signal is generated in the source clock domain. High for one clock cycle.
### Outputs
- `des_pulse`: Synchronized pulse output in the destination clock domain. High for one des_clock cycle.
## Input Generation
### Input Generation
- **Clock Frequencies**:
- Generate random frequencies for `src_clock` and `des_clock` to cover a wide range, including:
- Low frequencies (e.g., 1 MHz).
- High frequencies (e.g., 250 MHz).
- Closely matched frequencies (e.g., 90 MHz vs. 100 MHz).
- Extreme frequency disparities (e.g., 1 MHz vs. 100 MHz).
- **Random Scenarios**:
- Create diverse patterns for `src_pulse`, such as:
- Random Frequencies.
- **Reset Behavior**:
- Apply resets during various states, including:
- Idle state.
- Active pulse synchronization.
- Clock alignment and misalignment scenarios.
---
Follows the specification for building the RTL of the module, use it as a reference for the verification environment too:
## Module Functionality
1. **Pulse Synchronization**:
- The module uses a toggle flip-flop mechanism in the source domain and a double flip-flop synchronizer in the destination domain to synchronize `src_pulse` with `des_clock`.
2. **Reset Behavior**:
- When `rst_in` is asserted, all internal states (`pls_toggle`, `pls_toggle_synca`, `pls_toggle_syncb`, and `pls_toggle_syncc`) are cleared to zero, ensuring proper initialization.
3. **Edge Cases**:
- Correct synchronization under extreme clock frequency mismatches.
- Reset during pulse synchronization and at random intervals.
---
```verilog
module tb_cdc_pulse_synchronizer;
// Testbench signals
logic src_clock;
logic des_clock;
logic rst_in;
logic src_pulse;
logic des_pulse;
// Instantiate the DUT
cdc_pulse_synchronizer uut (
.src_clock(src_clock),
.des_clock(des_clock),
.rst_in(rst_in),
.src_pulse(src_pulse),
.des_pulse(des_pulse)
);
// Insert the code here to generate stimulus generation logic
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | cdc_pulse_synchronizer | uut | [
{
"name": "cdc_pulse_synchronizer.sv",
"content": "module cdc_pulse_synchronizer (\n input logic src_clock, // Source Clock Domain\n input logic des_clock, // Destination Clock Domain\n input logic rst_in, // Reset\n input logic src_pulse, // Source Pulse\n output logic des_pul... | [] |
cvdp_copilot_Attenuator_0011 | easy | Non-Agentic | Create a testbench for the `Attenuator` module, which takes a 5-bit input (`data`) and shifts it out serially after detecting changes, finally latching with `ATTN_LE`.
---
## Description
### Inputs
- **Registers**:
- `clk (1 bit)`: Clock signal driving the state machine and internal half-rate clock generation (`clk_div2`).
- `reset (1 bit)`: Active-high, synchronous reset. When asserted, all state registers and outputs (`ATTN_CLK`, `ATTN_DATA`, `ATTN_LE`) are forced zero.
- `data (5 bits)`: An input register. Any change from the previous value triggers a **LOAD** phase, followed by serial shifting and a final latch.
### Outputs
- **Wires**:
- `ATTN_CLK (1 bit)`: A clock-like output pulsed high during the **SHIFT** state to shift bits from the internal register.
- `ATTN_DATA (1 bit)`: Serial data output, sending the shifted 5-bit pattern bit by bit.
- `ATTN_LE (1 bit)`: Latch enable signal pulsed high for one cycle after shifting completes.
---
## Input Generation
- **Random Input Generation**:
The testbench drives random 5-bit values on `data` to ensure the module sees a range of patterns:
- Different bit combinations (e.g., `5'b00000`, `5'b11111`, random).
- Consecutive changes that repeatedly trigger LOAD → SHIFT → LATCH sequences.
- Long intervals without change, remaining in the **IDLE** state.
- **Edge Cases**:
The testbench should also drive specific sequences:
- Repeated identical data, ensuring the module stays in **IDLE** (no SHIFT or LATCH).
- Patterns that confirm each bit is shifted correctly in order (`ATTN_DATA`) while toggling `ATTN_CLK`.
- Observing `ATTN_LE` pulses for one cycle when shifting completes.
---
## Stabilization Period
- The testbench waits a few clock cycles (e.g., 2–4 cycles of `clk`) after driving each new `data` value to allow the FSM to step from **LOAD** into **SHIFT** and eventually **LATCH** if 5 bits are shifted.
---
## Instantiation
Name the instance of the module as `uut`.
---
Follows the specification for building the RTL of the module, use it as reference for the verification environment too:
### Module Interface
1. **Inputs**:
- `clk`: 1-bit clock signal.
- `reset`: 1-bit active-high reset.
- `data [4:0]`: 5-bit register whose changes trigger loading and shifting.
2. **Outputs**:
- `ATTN_CLK` (1 bit): Pulsed during SHIFT to clock out each bit.
- `ATTN_DATA` (1 bit): Serial data output from the shift register.
- `ATTN_LE` (1 bit): Asserted for one cycle after all 5 bits shift out, latching the final result externally.
### Module Functionality
- **Clock Division**:
An internal `clk_div2` toggles on every rising edge of `clk`, creating a slower clock domain for shifting.
- **Finite State Machine**:
- **IDLE**: Waits if `data == old_data`. On detecting `data != old_data`, transitions to **LOAD**.
- **LOAD**: Captures `data` into `shift_reg`, outputs the MSB on `ATTN_DATA`, and prepares for shifting.
- **SHIFT**: Toggles `ATTN_CLK` high and left-shifts the remaining bits, decreasing a bit counter until 0.
- **LATCH**: Pulses `ATTN_LE` high for one cycle, then returns to **IDLE**.
- **Reset Conditions**:
- While `reset=1`, `current_state` = **IDLE**, `shift_reg` = `5'b00000`, `ATTN_CLK=0`, `ATTN_DATA=0`, `ATTN_LE=0`.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | Attenuator | uut | [
{
"name": "Attenuator.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Attenuator (\n input clk,\n input reset,\n input [4:0] data,\n output reg ATTN_CLK,\n output reg ATTN_DATA,\n output reg ATTN_LE\n);\n\nreg clk_div2;\nreg [1:0] current_state, next_state;\nreg [... | [] |
cvdp_copilot_gray_to_binary_0014 | easy | Non-Agentic | Create a testbench for the `gray_to_binary` module, which converts an N-bit Gray code input into its N-bit binary equivalent using combinational logic. The testbench must have the instantiation of RTL module and generate stimulus for various test conditions.
### Interface of gray_to_binary RTL Module
**Parameter:**
- `WIDTH`: Width of the Gray code(`Default: 4`)
**Inputs:**
- `gray_in [WIDTH-1:0]`: The Gray code input that needs to be converted into binary.
**Outputs:**
- `binary_out [WIDTH-1:0]`: The corresponding binary output derived from the Gray code input.
##
### Input Generation and Validation
1. Fixed Test Cases
- Test a variety of Gray code inputs, including:
- Boundary values (0, `max value`)
- Alternating bit patterns (`0101`, `1010`)
- Power-of-two values to check conversion correctness.
- Example test values:
- `0000`, `0001`, `0011`, `0110`, `1111`, `1000`, `1100`, `1010`.
2. Randomized Testing
- Generate random Gray code values and compare them against a reference binary conversion function.
3. Edge Cases
- Minimum Input (`gray_in = 0`) → Expected Binary Output: `0000`
- Maximum Input (`gray_in = 1111`) → Expected Binary Output: `1000`
- One-bit change transitions:
- `0001 → 0000`
- `0011 → 0010`
- `0111 → 0100`
- Ensures that only one bit changes at a time.
___
### Instantiation
Instantiate the RTL module inside the testbench and name the instance as `uut`.
##
### Module Functionality
1. XOR-Based Conversion Logic
- The MSB of `binary_out` is directly assigned from gray_in's MSB.
- Each subsequent bit is computed as:
`B[i]=B[i+1] XOR G[I]`
2. Test One-Bit Change Property
- Ensure that each successive Gray code value only changes one bit when converted back to binary. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | gray_to_binary | uut | [
{
"name": "gray_to_binary.sv",
"content": "`timescale 1ns / 1ps\n\nmodule gray_to_binary #(\n parameter WIDTH = 4\n) (\n input logic [WIDTH-1:0] gray_in, // Gray code input\n output logic [WIDTH-1:0] binary_out // Binary output\n);\n\n always @* begin\n binary_out[WIDTH-1] = gray_in[WIDTH-... | [] |
cvdp_copilot_word_change_detector_0012 | medium | Non-Agentic | Complete the Given Partial System Verilog Testbench `tb_Word_Change_Pulse`. The testbench must instantiate the `Word_Change_Pulse` RTL module and provide input stimulus to validate its behavior. This module detects word changes and pattern matches in a DATA_WIDTH-bit data stream based on a specified mask and pattern.
## Description
**Parameters:**
- `DATA_WIDTH`: Specifies the bit width of the input data word `data_in`. Default is 8. It must be a positive integer greater than or equal to 1.
**Inputs:**
- `clk`: Clock signal for synchronizing operations. The design is synchronized to the positive edge of this clock.
- `reset`:Active-high asynchronous reset signal to initialize the module.
- `data_in [DATA_WIDTH-1:0]`: Input data word whose changes are to be detected.
- `mask [DATA_WIDTH-1:0]`: Mask signal to enable/disable change detection per bit (1 = detect changes, 0 = ignore changes)
- `match_pattern [DATA_WIDTH-1:0]`: Pattern to compare against the (masked) input data word.
- `enable`: Active-high signal, which enables the module’s operation.
- `latch_pattern`: When high, latches the current match_pattern into an internal register.
**Outputs:**
- `word_change_pulse`: Output signal that pulses high one clock cycle after any bit in data_in changes.
- `pattern_match_pulse`: Pulses high to indicate the masked input data word matches the latched pattern.
- `latched_pattern [DATA_WIDTH-1:0]`: Register that holds the latched pattern for comparison
## Module Functionality
The Word_Change_Pulse module should perform the following:
- **Pattern Latching**: When latch_pattern is asserted, match_pattern should be stored in latched_pattern.
- **Word Change Detection**: The word_change_pulse should be asserted if any masked bit in data_in differs from data_in_prev.
- **Pattern Match Detection**: The pattern_match_pulse should be asserted if the masked bits of data_in match latched_pattern.
- **Enable Control**: If enable = 0, pulses should not be generated.
- **Reset Behavior**: Upon assertion of reset, all outputs should be initialized to zero.
## Instantiation
The testbench should instantiate the Word_Change_Pulse module as `uut` and connect the signals accordingly.
## Input Generation
### Clock Generation
The clk signal should toggle every 5 time units, resulting in a 100MHz operation.
### Reset Handling
The reset signal should be asserted at the beginning of the simulation for three cycles. It should then be de-asserted, ensuring the DUT starts in a known state.
### Stimulus
Several test cases are applied to simulate different operations of the Word_Change_Pulse module. These cases cover a range of scenarios, including detecting word changes, pattern matching, masking behavior, enable-based operations, and edge cases.
### Test Phases
The testbench should consist of multiple test phases, each targeting different behaviors of the module:
#### Phase 1: Default Pattern Latching
Latch a pattern of all zeros (00000000).
#### Phase 2: Word Change Pulse Tests
- All bits transition from 0 → 1.
- All bits transition from 1 → 0.
- Single-bit flips (LSB, MSB).
- Alternating bit patterns.
- No changes in data_in (pulse should not be triggered).
#### Phase 3: Pattern Match Pulse Tests
Latch a specific pattern.
Apply data_in values that:
- Match the pattern with the full mask.
- Mismatch with full mask.
- Partial match with partial mask.
#### Phase 4: Masking Behavior
- **Full Mask**: mask = 8'b11111111
- **No Mask**: mask = 8'b00000000 (should suppress pulses).
- **Random Mask Values**: Generate correct selective comparison.
#### Phase 5: Enable Control
Run tests with enable = 0 to ensure no pulses are generated.
#### Phase 6: Generate Word Change and Pattern Match Pulses with Masking
- No Change Scenario.
- Single-Bit Transitions.
- Multiple-Bit Transitions.
- Fully Masked Changes.
- Pattern Match Case Without Changes.
- Partial Mask and Upper Bits Transition.
#### Phase 7: Stress Testing
- Apply randomized data sequences over 100 cycles.
- Introduce delays and glitches.
### Final Steps
- Waveform Dump: Generate a VCD file (Word_Change_Pulse.vcd) for visualization.
### Partial Test Stimulus Generator Code :
```verilog
module tb_Word_Change_Pulse;
// Parameters
parameter DATA_WIDTH = 8;
// Testbench Signals
reg clk;
reg reset;
reg enable;
reg latch_pattern;
reg [DATA_WIDTH-1:0] data_in;
reg [DATA_WIDTH-1:0] mask;
reg [DATA_WIDTH-1:0] match_pattern;
reg [DATA_WIDTH-1:0] data_in_prev;
wire word_change_pulse;
wire pattern_match_pulse;
wire [DATA_WIDTH-1:0] latched_pattern;
// Instantiate the DUT
Word_Change_Pulse #(
.DATA_WIDTH(DATA_WIDTH)
) dut (
.clk(clk),
.reset(reset),
.enable(enable),
.latch_pattern(latch_pattern),
.data_in(data_in),
.mask(mask),
.match_pattern(match_pattern),
.word_change_pulse(word_change_pulse),
.pattern_match_pulse(pattern_match_pulse),
.latched_pattern(latched_pattern)
);
// Clock Generation
initial clk = 0;
always #5 clk = ~clk;
task run_test(
input [DATA_WIDTH-1:0] test_data,
input [DATA_WIDTH-1:0] test_mask,
input [DATA_WIDTH-1:0] test_pattern,
input string testcase_name,
input reg test_enabled
);
begin
@(posedge clk);
data_in = test_data;
mask = test_mask;
match_pattern = test_pattern;
enable = test_enabled;
@(posedge clk);
$display("%s: data_in=%b, mask=%b, enable=%b -> word change pulse=%b",
testcase_name, test_data, test_mask, enable, word_change_pulse);
end
endtask
// Insert the code for the remaining test stimulus here
endmodule
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | Word_Change_Pulse | uut | [
{
"name": "Word_Change_Pulse.sv",
"content": "// Word_Change_Pulse Module with Maskable Input, Pattern Matching, and Advanced Features\nmodule Word_Change_Pulse #(\n parameter DATA_WIDTH = 8 // Default word width\n) (\n input wire clk, // Clock signal for synchronizing ... | [] |
cvdp_copilot_image_stego_0014 | medium | Non-Agentic | Develop a SystemVerilog module named `tb_image_stego` that generates input stimulus to verify the `image_stego` module. The `image_stego` module embeds bits of data into an image. Each pixel is 8 bits, and up to 4 bits can be embedded according to a `mask` control. The data bits are first XOR-encrypted by an 8-bit key. The purpose of `tb_image_stego` is to thoroughly test all features of the `image_stego` module, achieving complete functional and toggle coverage.
---
## Module Interface
### **Parameters**
- **`row`** *(default = 2)*
Number of rows in the image.
- **`col`** *(default = 2)*
Number of columns in the image.
- **`EMBED_COUNT_WIDTH`** *(default = 3)*
Width of the `embedded_pixel_count` output.
*(Each pixel is 8 bits, so total bits in `img_in` and `img_out` is `row * col * 8`.)*
---
## Port List
| **Port Name** | **Direction** | **Width** | **Description** |
|----------------------------------------------|---------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------------|
| `img_in[(row*col*8)-1:0]` | **Input** | `row*col*8` bits | Contains the original image data, 8 bits per pixel. |
| `data_in[(row*col*4)-1:0]` | **Input** | `row*col*4` bits | Data bits to be embedded, allowing up to 4 bits per pixel. |
| `bpp[2:0]` | **Input** | 3 bits | Indicates how many bits per pixel to embed: `000=1`, `001=2`, `010=3`, `011=4`. Other values are invalid and result in no embedding. |
| `encryption_key[7:0]` | **Input** | 8 bits | Key used for XOR encryption of `data_in`. |
| `mask[(row*col)-1:0]` | **Input** | `row*col` bits | Pixel-wise mask enabling embedding: `1=embed`, `0=pass-through`. |
| `img_out[(row*col*8)-1:0]` | **Output** | `row*col*8` bits | Image data after embedding the specified bits into some (or none) of the pixels. |
| `error_out` | **Output** | 1 bit | Indicates odd parity in `data_in`. |
| `embedded_pixel_count[EMBED_COUNT_WIDTH-1:0]`| **Output** | `EMBED_COUNT_WIDTH` bits | Holds the total count of pixels in which data was actually embedded. |
| `embedding_done[1:0]` | **Output** | 2 bits | Reflects the embedding status: `00=Idle`, `01=In-progress`, `10=Done`, `11=No-embed`. |
---
## Functional Description
1. **Parity Checking**
- The module calculates the XOR of all bits in `data_in`. If an **odd** number of bits in `data_in` is set to 1, `error_out` is driven high (`1`).
- This ensures the system can detect if the embedded data has non-even parity.
2. **Encryption**
- The bits of `data_in` are split into 8-bit blocks. Each block is XORed with the 8-bit `encryption_key`.
- This process creates an **encrypted** data stream, referred to internally as `data_in_encrypted`.
3. **Embedding**
- The image has `(row * col)` pixels, each indexed by `i` ranging from `0` to `row * col - 1`.
- For each pixel `i`, if `mask[i]` is `1`, the module replaces the **lowest** bits (based on `bpp`) in `img_in[i*8 +: 8]` with bits from `data_in_encrypted`.
- **Incrementing Embedded Pixel Count**:
- Each time a pixel is modified, `embedded_pixel_count` is incremented by `1`.
- **`embedding_done` Transitions**:
- **`2'b01` (In-progress)**: Once embedding starts (i.e., at least one `mask[i] == 1` pixel is encountered).
- **`2'b10` (Done)**: Set when at least one pixel has been embedded successfully.
- **`2'b11` (No-embed)**: If `mask != 0` but no bits actually get embedded (e.g., because `bpp` is invalid).
4. **Idle vs. Non-Idle**
- **Idle**: If `mask == 0`, the module does not modify any pixels, so `img_out` equals `img_in`.
- **Non-Idle**: If `mask != 0`, embedding logic attempts to modify pixels. However, if it results in no modified pixels for some reason (e.g., `bpp` is invalid), `embedding_done` becomes `2'b11`.
---
## Instantiation
Use an instance of `image_stego` named `uut` within the testbench `tb_image_stego`.
---
## Required Stimulus Description
The objective is to achieve **100% code and toggle coverage** for the `image_stego` module by systematically exercising its functionality. The stimulus should ensure that all key features, edge cases, and status transitions of the design are thoroughly tested to maintain coverage goals.
| **Test Condition** | **Purpose** |
|-----------------------------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| **BPP Variations** | Embedding for `bpp = 000, 001, 010, 011`, ensuring the correct number of bits are replaced in each pixel. Other `bpp` values should result in no embedding to cover the `2'b11` state. |
| **Mask Patterns** | Embedding for different mask patterns (e.g., all zeros, all ones, partial patterns). |
| **Encryption Keys** | Ensure the XOR process covers various `encryption_key` values (0x00, 0xFF, random, etc.). |
| **Parity Checks** | Provide even and odd `data_in` to check proper assertion of `error_out`. |
| **Pixel Count** | `embedded_pixel_count` increments only for pixels that are actually embedded. |
| **Embedding Done States** | Test `embedding_done` transitions: `00 (Idle)` → `01 (In-progress)` → `10 (Done)` or `11 (No-embed)`. |
| **Randomized Scenarios** | Randomize `img_in`, `data_in`, `bpp`, `encryption_key`, and `mask` to cover unexpected corner cases. | | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | image_stego | uut | [
{
"name": "image_stego.sv",
"content": "`timescale 1ns/1ps\nmodule image_stego #(\n parameter row = 2,\n parameter col = 2,\n parameter EMBED_COUNT_WIDTH = 3\n)(\n input [(row*col*8)-1:0] img_in,\n input [(row*col*4)-1:0] data_in,\n input [2:0] bpp,\n input [7:0] encryption_key,\n input [(row*col)-1... | [] |
cvdp_copilot_sobel_filter_0015 | easy | Non-Agentic | Write a SystemVerilog testbench for a Sobel filter module named `sobel_filter` that performs edge detection on a stream of pixel data. The Sobel filter calculates the gradient magnitude using a 3x3 pixel window and determines whether the edge strength exceeds a predefined threshold `THRESHOLD`. The testbench should only provide stimuli for the design across various input scenarios, including edge cases, and ensure proper synchronization of different input signals.
#### Inputs:
- `clk`: Clock signal for synchronization. The design is synchronized to the positive edge of this clock.
- `rst_n`: Active-low asynchronous reset. Clears internal buffers, counters, and outputs.
- `pixel_in [7:0]`: 8-bit input pixel data.
- `valid_in`: An active-high signal that indicates the validity of the `pixel_in` data.
#### Outputs:
- `edge_out [7:0]`: 8-bit output indicating the presence of an edge (255 for an edge, 0 otherwise).
- `valid_out`: An active-high signal that indicates when `edge_out` is valid.
### Overview of the Design:
The Sobel filter detects edges in an image by first computing the gradients in the horizontal (`Gx`) and vertical (`Gy`) directions, then calculating the gradient magnitude (`|Gx| + |Gy|`) and comparing it to a threshold to determine whether a pixel is part of an edge. The `THRESHOLD` is set to a default value of 128, which defines the threshold for edge detection. Pixels with gradient magnitudes greater than this value are classified as edges.
A 3x3 window of pixels is sent as a continuous stream of inputs through `pixel_in`, and `valid_in` remains high while pixels are supplied. The module uses a 3x3 buffer to store pixel data, ensuring it only outputs valid results (`valid_out` and `edge_out`) once the buffer is fully populated with 9 pixels. Pixels are shifted sequentially to store new incoming pixels. (The input is sent row by row, left to right. Starting from the top row, the traversal proceeds to the bottom row.) The filter performs convolution when the buffer is fully populated and outputs the result. After processing each window, the module clears the buffer and waits for the next set of 9 pixels. The buffer is also cleared when reset is asserted. Assume that the handling of overlapping windows is handled externally, and this design processes each window as a new one (no storing of pixels from the previous window).
---
### Testbench Requirements:
#### Module Instantiation:
- The Sobel filter module should be instantiated as `dut`, with all input and output signals properly connected. The testbench must cover all possible input scenarios to achieve 100% coverage.
#### Input Stimulus Generation:
1. **Pixel Stream Generation:**
- The testbench should generate a stream of 8-bit pixel values (`pixel_in`) and assert `valid_in` when pixel data is valid.
- Include edge cases like:
- Uniform pixel values (all zeros, all maximum values).
- Pixel gradients (e.g., increasing or decreasing values across the 3x3 window).
- Random pixel values to simulate real-world scenarios.
2. **Synchronization:**
- The RTL design maintains a continuous stream of valid pixels by monitoring the assertion of `valid_in`. When `valid_in` remains consistently asserted after a full window is completed, the module resets the count and begins loading a new set of pixels. Therefore, the test case must be designed to reset `valid_in` after loading a 3×3 block of pixels and also to continuously assert `valid_in` for multiple input windows. Additionally, it should be capable of resetting `valid_in` mid-stream to cover all possible scenarios.
3. Reset Testing:
- Set the reset (`rst_n`) to clear all internal states (e.g., pixel buffer, counters, outputs) between input windows to create a scenario where the module receives inputs after the reset is de-asserted. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | sobel_filter | dut | [
{
"name": "sobel_filter.sv",
"content": "module sobel_filter (\n input logic clk,\n input logic rst_n,\n input logic [7:0] pixel_in,\n input logic valid_in,\n output logic [7:0] edge_out,\n output logic valid_out\n);\n \n logic s... | [] |
cvdp_copilot_fixed_arbiter_0004 | easy | Non-Agentic | Write a SystemVerilog testbench to generate stimulus for the `fixed_priority_arbiter` module. The testbench should validate the priority-based grant mechanism by applying different request patterns, including single, multiple, and no request scenarios. Additionally, it should verify the reset functionality and ensure the grant signal is correctly assigned based on priority.
## Design Details
1. **Inputs**:
- `clk`: 1-bit clock signal for synchronization.
- `reset`: 1-bit active-high reset signal to initialize the arbiter.
- `req`: 8-bit request signal, where each bit represents a request from a unique source.
2. **Output**:
- `grant`: 8-bit grant signal, where one bit is set high to indicate the granted request based on a **fixed priority scheme**.
3. **Module Functionality**:
- **Single Request Handling**:
- Assert one request bit at a time in `req` and verify the corresponding bit in `grant` is set high.
- **Multiple Requests Handling**:
- Simultaneously assert multiple request bits and verify that the arbiter grants access to the **highest-priority request**.
- **No Requests**:
- Assert `req = 8'b00000000` and verify that `grant` is cleared to `8'b00000000`.
- **Reset Behavior**:
- Apply an active reset (`reset = 1`) during active requests and verify that `grant` is cleared to `8'b00000000`.
---
## **Testbench Requirements**
### **Instantiation**
The testbench must instantiate the **fixed_priority_arbiter** module as **dut** with proper connections for all signals.
### **Input Generation**
The testbench should generate different request patterns to verify correct priority handling, including:
- Single Requests: Apply requests one at a time to check correct grant assignment.
- Multiple Requests: Apply overlapping requests to ensure the arbiter always grants the highest-priority request.
- No Requests: Ensure the grant signal remains `00000000` when no requests are present.
- Reset Behavior: Apply reset during active requests to verify that `grant` is cleared.
### **Tasks for Test Stimulus**
- Apply Reset (`apply_reset`)
- A task to assert `reset`, wait for a few clock cycles, and deassert it to verify correct initialization.
- Drive Request (`drive_request`)
- A task to apply a specific request pattern, hold it for a few cycles, and check the corresponding grant output.
---
This testbench will validate the **fixed_priority_arbiter** functionality and ensure its behavior under various input conditions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | fixed_priority_arbiter | dut | [
{
"name": "fixed_priority_arbiter.sv",
"content": "`timescale 1ns / 1ps\n\nmodule fixed_priority_arbiter(\n input clk, // Clock signal\n input reset, // Active high reset signal\n input [7:0] req, // 8-bit request signal; each bit represents a request from a different so... | [] |
cvdp_agentic_spi_complex_mult_0008 | medium | Agentic | Design a SystemVerilog testbench, `spi_complex_mult_tb.sv`, in the verif directory to only generate stimulus and achieve maximum coverage for the module on the file in `rtl/spi_complex_mult.sv`. Refer to the specification in `docs/specification.md`, which defines a SPI Slave that receives the complex number components Ar, Ai, Br, and Bi (real and imaginary parts) via SPI and performs complex multiplication using DSP operations. The results are stored in internal registers and can be transmitted back through SPI.
Include the following in the generated testbench:
Module instance: The module should be instantiated as dut, with the input and output signals connected for testing.
Input generation: The testbench must generate random inputs for the data signals. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 97
}
] | spi_complex_mult | dut | [
{
"name": "spi_complex_mult.sv",
"content": "module spi_complex_mult #(\n parameter IN_WIDTH = 'd16, // Parameter defining the input width\n parameter OUT_WIDTH = 'd32 // Parameter defining the output width\n) (\n input logic rst_async_n, // Asynchronous reset signal, active low... | [
{
"name": "specification.md",
"content": "# SPI Slave Complex Multiplication Specification\n\n## Overview\nThe `spi_complex_mult` module implements a SPI Slave module that receives the complex number components Ar, Ai, Br, and Bi (real and imaginary parts) via SPI and performs complex multiplication using D... |
cvdp_copilot_secure_read_write_register_bank_0006 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `secure_read_write_register_bank`. It allows read and write operations only after unlocking, which requires specific values written to the first two addresses in sequence.The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behaviour**
### Parameter
1. **p_address_width**: The address width parameter with default value of 8 bits. It will be used to create the addressable space of register bank module.
2. **p_data_width**: The data width parameter with default value of 8 bits.
3. **p_unlock_code_0**: The unlock code to be written at address zero. The default value is 0xAB.
4. **p_unlock_code_1**: The unlock code to be written at address one. The default value is 0xCD.
### Inputs
1. **i_addr**: `p_addr_width`-bit input. Specifies the target address for read or write operations.
2. **i_data_in**: `p_data_width`-bit input. Data input to be written to the register bank during a write operation.
3. **i_read_write_enable**: 1-bit input control signal. Determines the operation type:
- `0`: Write operation.
- `1`: Read operation.
4. **i_capture_pulse**: 1-bit capture pulse signal. Triggers the read or write operation on positive edge of this signal. It will act as clock for register bank.
5. **i_rst_n**: 1-bit asynchronous active low reset, to reset the unlock state machine
### Outputs
1. **o_data_out**: `p_data_width`-bit output. Data output bus that reflects the value read from the register bank during a read operation.
### Functional Requirements
#### 1. Write Operation
- If **i_read_write_enable** is `0`, the module interprets this as a write operation.
- On the **rising edge** of **i_capture_pulse**, the value of **i_data_in** is written to the register at the address specified by **i_addr**.
- **o_data_out** should output `0` during write operations as a default state.
#### 2. Read Operation
- If **i_read_write_enable** is `1`, the module interprets this as a read operation.
- On the **rising edge** of **i_capture_pulse**, **o_data_out** outputs the data stored at the address specified by **i_addr**.
- **o_data_out** only reflects the read data during read operations.
### Security Access Requirements
1. **Unlocking Mechanism**:
- **To unlock the register bank**, two sequential operations must be completed:
- First, the specific **parameterized unlock code** (matching **p_data_width**) must be written to address `0`.
- Then, a specific **parameterized trigger code** must be written to address `1`.
- If both conditions are met, the register bank unlocks, enabling access to read and write for all addresses.
- If, at any positive edge of i_capture_pulse, values are written to address 0 or 1 does not equal to given parameterized unlock code, the register bank will reset, resulting in lock of register bank. User needs to unlock the register bank once again.
- If the unlock sequence is incomplete, access to other addresses will remain restricted as follows:
- **Read Operation**: Outputs `0` on **o_data_out**.
- **Write Operation**: Prevents writing to any address except `0` and `1`.
- When i_rst_n goes low, then this unlocking mechanism resets and user needs to unlock the register bank once again.
2. **Restricted Access Addresses**:
- Addresses `0` and `1` are write-only and cannot be read.
- Other addresses remain inaccessible for both read and write until the unlock sequence is completed.
### Constraints and Edge Cases
- Ensure that addresses `0` and `1` cannot be read.
- Any read or write attempt on other addresses before unlocking should default **o_data_out** to `0` and prevent writing, respectively.
- The writing of address `0` and address `1` should be concurrent, else register bank should be locked.
## Test Bench Requirements
### Stimulus Generation
1. **Reset and Initialization:**
- Assert the asynchronous reset signal briefly and then release it.
2. **Locked State – Write Operation to a General Register:**
- While the module is locked, perform a write operation to a register that is not part of the unlock sequence.
3. **Locked State – Read Operation from a General Register:**
- In the locked state, perform a read operation from a register outside the unlock sequence.
4. **Locked State – Read Operation from the Unlock Addresses:**
- While locked, attempt to read from the registers reserved for the unlock sequence.
5. **Successful Unlock Sequence and General Access:**
- Perform the unlock sequence by writing the appropriate unlock code to the first designated address followed by writing the corresponding unlock code to the second designated address, with both operations synchronized to the capture pulse.
- Once unlocked, perform a write to a general register and then read from that register.
6. **Unlock Failure – Incorrect Code in the First Step:**
- Attempt to start the unlock sequence by writing an incorrect code to the first designated address.
- Continue by performing the expected operation at the second designated address.
7. **Unlock Failure – Incorrect Code in the Second Step:**
- Initiate the unlock sequence correctly at the first designated address.
- Then write an incorrect code to the second designated address.
8. **Out-of-Sequence Write Aborting Unlock:**
- Begin the unlock sequence by writing the proper code to the first designated address.
- Instead of proceeding to the second designated address, write to a different register.
9. **Unlocked State – Incorrect Write to Unlock Address Causes Relock:**
- After achieving the unlocked state, perform a write operation with an incorrect code to one of the designated unlock addresses.
- Perform additional write/read operations on a general register to ensure that access remains restricted.
10. **Unlocked State – Read Operation from Unlock Addresses:**
- In the unlocked state, attempt to read from the registers used for the unlock sequence.
11. **Boundary Register Operation:**
- Once unlocked, perform a write operation to the highest addressable register in the bank.
- Follow this with a read from that boundary register.
12. **Capture Pulse Synchronization:**
- Modify control inputs (such as address selection, data to be written, or operation type) between capture pulses.
13. **Reset During Active Operation:**
- While the module is unlocked, perform a write operation to a general register.
- Assert the asynchronous reset during the operation and then de-assert it.
- Attempt a read from the previously written register.
14. **Incorrect Unlock Sequence Order:**
- Attempt to initiate the unlock sequence by writing to the second designated address before writing to the first designated address.
15. **Multiple Sequential Unlock Attempts:**
- First, attempt an unlock sequence that intentionally fails by providing an incorrect code in one of the steps.
- Then, retry the unlock sequence using the proper codes in the correct order. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 96
}
] | secure_read_write_register_bank | dut | [
{
"name": "secure_read_write_register_bank.v",
"content": "// -----------------------------------------------------------------------------\n// Module Name: secure_read_write_register_bank\n// Description: \n// This module implements a secure, parameterized register bank with access \n// control. It uses a ... | [] |
cvdp_agentic_search_algorithm_0001 | medium | Agentic | I have a specification of a `linear_search_top` module in the `docs` directory. Write a SystemVerilog testbench `tb_linear_search.sv` in the `verif` directory to only generate stimulus for the `linear_search_top` module and achieve maximum coverage of the design.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the `linear_search_top` module as `linear_search_top_inst`, with all ports connected appropriately.
- **Clock and Reset**: Generate a 10ns clock and include a synchronous, active-high reset task to initialize the DUT before applying any stimulus.
- **Memory Initialization Stimulus**: Use the memory write interface (`mem_write_en`, `mem_write_addr`, `mem_write_data`) to populate memory with a variety of patterns before each search.
- **Search Control Stimulus**: Drive the `start` signal to initiate the search, and optionally use the `pause` signal to temporarily suspend it. Resume the search by deasserting `pause`.
- **Test Scenarios** (generate input stimulus for each of the following):
- Write a pattern where the `key` appears at every 4th address.
- Write memory such that the `key` appears only once.
- Fill memory completely with the `key` to trigger match buffer overflow.
- Repeat the full-match test but insert a `pause` during the search.
- Write exactly `MAX_MATCHES` instances of the `key` to test buffer boundaries without overflow.
- Test edge cases where the `key` is placed only at the first, last, or middle address.
- Perform back-to-back searches with different `key` values and spacing patterns.
- Randomize memory contents and the `key` for a randomized match pattern test.
- Apply high-volume randomized testing (e.g., 10,000 iterations) with varying numbers and locations of matches.
Do not include any assertions or output checking logic. The testbench must focus only on applying stimulus to the DUT and observing outputs passively. | [
{
"inst_name": "linear_search_top_inst",
"metric": "Overall Average",
"target_percentage": 100
},
{
"inst_name": "datapath",
"metric": "Overall Average",
"target_percentage": 100
},
{
"inst_name": "ctrl",
"metric": "Overall Average",
"target_percentage": 100
}
] | linear_search_top | linear_search_top_inst | [
{
"name": "linear_search_datapath.sv",
"content": "module linear_search_datapath #(\n parameter DATA_WIDTH = 8 ,\n parameter ADDR_WIDTH = 4 ,\n parameter MEM_DEPTH = 1 << ADDR_WIDTH, // Total memory size\n parameter MAX_MATCHES = 8 // Max number of indices ... | [
{
"name": "specification.md",
"content": "# Linear Search Engine Specification Document\n\n## **Introduction**\nThe **Linear Search Engine** is a parameterized, hierarchical RTL design that performs a **linear search** over a memory array to find all locations where a given key matches stored data. It suppo... |
cvdp_copilot_wb2ahb_0004 | medium | Non-Agentic | Write a System Verilog testbench to generate stimulus for a `wishbone_to_ahb_bridge_tb` module, which is responsible for bridging transactions between a Wishbone master and an AHB slave.
## **Design Specification**
The `wishbone_to_ahb_bridge` module serves as a bridge between the Wishbone bus and the AMBA AHB bus, facilitating data transfers between a Wishbone master and an AHB slave. The bridge is responsible for handling address alignment, transfer size selection, and acknowledgment signaling, ensuring compatibility between the two protocols.
### **Functionality**
- The bridge takes Wishbone signals (`cyc_i`, `stb_i`, `we_i`, `sel_i`, `addr_i`, `data_i`) as inputs and converts them into AHB-compatible signals (`haddr`, `hwrite`, `hsize`, `htrans`, `hwdata`).
- The bridge properly aligns **Wishbone byte enables (`sel_i`)** to the corresponding **AHB address and data phase transactions**.
- Acknowledgment (`ack_o`) is generated when the **AHB slave is ready (`hready`)**, ensuring correct transaction completion.
- Supports **single transfers** with **variable transfer sizes** (`byte`, `half-word`, `word`).
- Includes **address holding logic** to maintain proper transactions in case of stalled AHB responses.
---
### Inputs
- **Wishbone Ports (from WB Master):**
- `clk_i`: Clock signal for Wishbone operations.
- `rst_i`: Active-low reset signal to initialize the bridge.
- `cyc_i`: Indicates a valid Wishbone transaction cycle.
- `stb_i`: Strobe signal for valid data on the Wishbone interface.
- `sel_i[3:0]`: Byte enables to select which bytes are active.
- `we_i`: Write enable signal.
- `addr_i[31:0]`: Address for the Wishbone transaction.
- `data_i[31:0]`: Write data from the Wishbone master.
- **AHB Ports (from AHB Slave):**
- `hclk`: Clock signal for AHB operations.
- `hreset_n`: Active-low reset signal for the AHB interface.
- `hrdata[31:0]`: Read data from the AHB slave.
- `hresp[1:0]`: AHB response signal.
- `hready`: Indicates when the AHB slave is ready.
### Outputs
- **Wishbone Outputs:**
- `data_o[31:0]`: Read data back to the Wishbone master.
- `ack_o`: Acknowledge signal for Wishbone operations.
- **AHB Outputs:**
- `htrans[1:0]`: AHB transaction type.
- `hsize[2:0]`: Size of the AHB transfer.
- `hburst[2:0]`: Burst type (always single in this design).
- `hwrite`: Write enable signal for AHB transactions.
- `haddr[31:0]`: Address for the AHB transaction.
- `hwdata[31:0]`: Write data to the AHB slave.
---
## **Testbench Requirements**
### **Instantiation**
- The `wishbone_to_ahb_bridge` module must be instantiated as **DUT (Device Under Test)**.
- All input and output signals should be properly connected for functional verification.
### **Test Scenarios**
#### **Clock and Reset Generation**
- Generate two separate clocks:
- `clk_i` for the Wishbone interface.
- `hclk` for the AHB interface.
- Implement an asynchronous reset (`rst_i` for Wishbone, `hreset_n` for AHB) at the start of the test.
#### **Wishbone Transactions**
##### **Write Transactions**
- Perform multiple write operations using different addresses, data values, and byte enable (`sel_i`) configurations.
- Validate the correct Wishbone to AHB conversion by checking:
- Address alignment
- Transfer size selection (`hsize`)
- Data transfer correctness (`hwdata`)
- Acknowledgment (`ack_o`)
- Include test cases for:
- Byte writes (`sel_i = 4'b0001, 4'b0010, 4'b0100, 4'b1000`)
- Half-word writes (`sel_i = 4'b0011, 4'b1100`)
- Word writes (`sel_i = 4'b1111`)
##### **Read Transactions**
- Perform read operations using different addresses.
- Ensure correct data retrieval from the AHB slave (`hrdata` → `data_o`).
- Verify acknowledgment timing.
#### **Address Alignment and Endianness Handling**
- Check how the bridge modifies Wishbone addresses to match AHB alignment rules.
- Ensure that byte and half-word transfers properly align data in `hwdata` and `data_o`.
#### **AHB Protocol Compliance**
- Validate the AHB transaction type (`htrans`) for different Wishbone operations:
- Idle (2'b00)
- Non-sequential (2'b10)
- Sequential (2'b11) – if burst support is added in the future
- Verify proper operation of:
- AHB Ready Handling (`hready`):
- Ensure bridge correctly waits for `hready` before transferring data.
- AHB Response Handling (`hresp`):
- Include test cases where the AHB slave returns an error response (`hresp = 2'b01`).
- Check whether the bridge correctly stalls and recovers from such conditions.
#### **Error and Recovery Handling**
- AHB Error (`hresp = 2'b01`)
- Ensure the bridge correctly halts and resets the transaction.
- AHB Busy Handling (`hready = 0`)
- Verify that the bridge waits and resumes when `hready` becomes `1`.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | wishbone_to_ahb_bridge | uut | [
{
"name": "wishbone_to_ahb_bridge.sv",
"content": "`timescale 1ns / 1ps\n\nmodule wishbone_to_ahb_bridge\n // Wishbone ports from WB master\n (\n input clk_i, // Clock input for Wishbone\n input rst_i, // Reset input for Wishbone\n input cyc_i, // Cycle signal from... | [] |
cvdp_copilot_adc_data_rotate_0009 | easy | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `adc_data_rotate` module by applying exhaustive test scenarios. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage. The testbench should not create checkers to verify the MUT.
---
## **Instantiation**
Name the instance of the RTL as `dut`.
## **RTL Parameter Inputs - Outputs and Functional behaviour**
### Parameterization
- The module supports parameterized data width, `DATA_WIDTH`, with a default value of 8 bits. This allows the module to handle various input data sizes.
### Inputs
- **`i_clk`** (logic): Clock signal to synchronize the module’s operation.
- **`i_rst_n`** (logic): Active-low reset signal. When asserted (`i_rst_n = 0`), all outputs reset to their idle state.
- **`i_adc_data_in`** (logic [`DATA_WIDTH`-1:0]): Input data to be rotated.
- **`i_shift_count`** (logic [3:0]): Specifies the number of bits to rotate. Supports up to 15-bit rotation.
- **`i_shift_direction`** (logic): Controls the rotation direction:
- `0`: Left Rotate
- `1`: Right Rotate
### Outputs
- **`o_processed_data`** (logic [`DATA_WIDTH`-1:0]): The rotated result of the input `i_adc_data_in`.
- **`o_operation_status`** (logic): Indicates the operation state:
- `0`: Reset state
- `1`: Active rotation
### Reset Behavior
- When `i_rst_n` is asserted (`i_rst_n = 0`):
- `o_processed_data` resets to `0`.
- `o_operation_status` resets to `0`.
### Rotation Behavior
- On the rising edge of `i_clk` and when `i_rst_n = 1`, the module performs:
- **Left Rotate** (`i_shift_direction = 0`): Bits shifted out from the left re-enter on the right.
- **Right Rotate** (`i_shift_direction = 1`): Bits shifted out from the right re-enter on the left.
### Operation Status
- During rotation, `o_operation_status` is set to `1` to indicate an active state.
## Constraints and Edge Cases
### **Edge Cases**:
- Handle rotation amounts of 0 and `DATA_WIDTH` effectively (e.g., rotation by `0` bits should result in no change).
- Ensure correct behavior when `i_shift_count` exceeds `DATA_WIDTH`. This means any shift count above **DATA_WIDTH** automatically wraps to the equivalent smaller shift.
---
## Stimulus generation
1. Reset and Initialization
- **Reset Assert/Deassert**: Set `i_rst_n = 0`, then `1`.
- **Repeated Resets**: Assert/deassert `i_rst_n` multiple times quickly.
2. No Shift (Shift Count = 0)
- **Left and Right Directions**: `i_shift_count = 0`, both directions.
- **Data Patterns**: All-0s, all-1s, and alternating bits (e.g., `10101010`).
3. Single-Bit Shifts
- **Left Shift by 1**: `i_shift_count = 1`, `i_shift_direction = 0`.
- **Right Shift by 1**: `i_shift_count = 1`, `i_shift_direction = 1.
4. Multiple Bit Shifts
- **Mid-Range Counts**: For `i_shift_count` like `3`, `4`, and `7`, apply various `i_adc_data_in` values.
- **Full-Range Counts**: Sweep `i_shift_count` from `0` to `15`.
5. Special Edge Cases
- **Shift = Data Width** (e.g., 8): complete rotation.
- **Shift = 15**: Highest valid count. Wrap-around for both directions.
- **All 1s / All 0s**: Rotation uniform bit patterns.
- **Alternating Bits**: Wrap-around (`10101010`, `01010101`) under all shift counts/directions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 92
}
] | adc_data_rotate | dut | [
{
"name": "adc_data_rotate.sv",
"content": "module adc_data_rotate #(\n parameter DATA_WIDTH = 8 // Parameterized data width (default = 8)\n)(\n // Inputs\n input logic i_clk, // Clock signal\n input logic i_rst_n, // Active-low res... | [] |
cvdp_copilot_Synchronous_Muller_C_Element_0003 | easy | Non-Agentic | Write a SystemVerilog testbench to only generate stimulus for a `sync_muller_c_element` design with configurable inputs and pipeline depth. This design processes input signals through a configurable pipeline and produces a single-bit output based on the state of the inputs in the final pipeline stage, outputting 1 only when all inputs are 1 and 0 only when all inputs are 0, while maintaining its state otherwise.
---
## Design Details
### **Parameterization**
1. **NUM_INPUT**: Specifies the number of input signals.
- Default: 2
2. **PIPE_DEPTH**: Defines the number of pipeline stages.
- Default: 1
### **Functional Behavior**
1. **Pipeline Operation**:
- The pipeline captures and shifts the input states through `PIPE_DEPTH` stages.
- Inputs propagate stage by stage until they reach the final stage.
2. **Output Logic**:
- The output signal is set based on the status of propagated input signals at the last pipeline stage.
3. **Control Signal Behavior**:
- **Reset (`srst`)**: Active-high synchronous reset that clears the pipeline and output.
- **Clear (`clr`)**: Clears the pipeline and output without resetting.
- **Clock Enable (`clk_en`)**: Controls whether the pipeline registers update on the rising edge of the clock.
### **Inputs and Outputs**
- **Inputs**:
- `clk`: Clock signal.
- `srst`: Synchronous reset signal (active high).
- `clr`: Active high clear signal.
- `clk_en`: Active high clock enable signal.
- `inp[NUM_INPUT-1:0]`: NUM_INPUT-width vector representing the input signals.
- **Outputs**:
- `out`: Output signal based on the logical state of the inputs in the last pipeline stage.
---
### Testbench Requirements:
#### Instantiation
- **Module Instance**: The `sync_muller_c_element` module must be instantiated as `sync_muller_c_element_inst`, with all input and output signals connected for testing.
---
#### Input Generation
- **Input Patterns**: The testbench should continuously drive various input patterns to `inp` to cover all possibilities including:
- All `0`s, all `1`s, alternating patterns, and other corner cases.
- Randomized input patterns to exercise pipeline behavior.
- **Control Signals**:
- Assert `srst` at the start of the simulation to reset the pipeline and output.
- Toggle `clr` during operation to clear the pipeline and output.
- Drive `clk_en` high and low during operation to test its effect on pipeline propagation.
- **Output Latency**: Outputs will reflect the processed state of the inputs after a latency of `PIPE_DEPTH + 1` clock cycles. New inputs do not have to wait for this latency and can continue to be applied every clock cycle. | [
{
"inst_name": "sync_muller_c_element_inst",
"metric": "Overall Average",
"target_percentage": 100
}
] | sync_muller_c_element | sync_muller_c_element_inst | [
{
"name": "sync_muller_c_element.sv",
"content": "module sync_muller_c_element #(\n parameter NUM_INPUT = 2, // Number of input signals\n parameter PIPE_DEPTH = 1 // Number of pipeline stages\n) (\n input logic clk , // Clock signal\n input logic srst , // Synchr... | [] |
cvdp_agentic_helmholtz_0003 | medium | Agentic | The specification document for the `helmholtz_top_module` is present in the `docs` folder. Write a SystemVerilog testbench, `helmholtz_top_module_tb.sv`, in the `verif` directory to only generate stimulus for the `helmholtz_top_module` to achieve maximum coverage of the DUT.
Include the following in the generated testbench:
### 1. **Module Instance**:
The `helmholtz_top_module` should be instantiated as `dut`, with all input and output ports properly connected.
### 2. **Input Generation**:
The testbench must generate a comprehensive range of stimuli for all inputs:
- Signed `audio_in` values, including edge cases (`0`, `±32767`, alternating polarity)
- A sweep and random values for `base_freq` and `q_factor` across their entire valid range
- Control signal combinations:
- `calibrate` = `0`/`1`
- `mod_enable` = `0`/`1`
- Rapid toggling and corner case behavior (e.g., toggling mid-operation)
- Include sine wave approximations and burst stimulus for realistic input simulation
### 3. **Computation Period**:
After applying a stimulus input set, the testbench should wait a sufficient number of cycles for the pipeline and FSMs to settle. During this time:
- Display the `cal_done_flags` and `audio_out` outputs
- Ensure at least 8–12 clock cycles pass before applying the next set of inputs
- Ensure inputs are only changed when the design is not in reset or calibration unless intentionally testing those conditions
### 4. **Logging**:
The testbench must include `$display` statements that log the input values and relevant control signals for every test cycle to assist with waveform analysis and debugging.
--- | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
}
] | helmholtz_top_module | dut | [
{
"name": "helmholtz_top_module.sv",
"content": "module helmholtz_resonator #(\n parameter WIDTH = 16,\n parameter FRAC_BITS = 8,\n parameter CAL_TOLERANCE = 10 // 10% tolerance //\n)(\n input logic clk,\n input logic rst,\n input logic calibrate,\n input logic signed [WIDTH-1:0] audio_... | [
{
"name": "specs_tb.md",
"content": "# Helmholtz Resonator Audio Processor Specification Document\n\n## Introduction\n\nThe **Helmholtz Resonator Audio Processor** is a pipelined and modular Verilog design intended for real-time audio signal processing. It is inspired by acoustic resonance principles and de... |
cvdp_copilot_ping_pong_buffer_0004 | easy | Non-Agentic | Complete the Ping-Pong Buffer Testbench in SystemVerilog. The testbench must instantiate the `ping_pong_buffer` RTL module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `ping_pong_buffer` module simulates a dual-buffer system that allows concurrent read/write operations while alternating between two buffers.
---
## **Description**:
### **Inputs** :
- **Registers**:
- `clk` (1-bit): Active high Clock signal that toggles every **10 ns** (100 MHz) and is supplied to the **DUT**.
- `rst_n` (1-bit): **Active-low** asynchronous reset signal that resets the buffer and control logic of the **DUT**.
- `write_enable` (1-bit): Enables writing of data into the buffer.
- `read_enable` (1-bit): Enables reading of data from the buffer.
- `data_in` (8-bit, `[7:0]`): 8-bit input data that is written into the buffer.
### **Outputs** :
- **Registers**:
- `data_out` (8-bit, `[7:0]`): 8-bit output data read from the buffer.
- `buffer_full` (1-bit): Indicates whether the buffer is full.
- `buffer_empty` (1-bit): Indicates whether the buffer is empty.
- `buffer_select` (1-bit): Indicates the currently active buffer.
---
## **Instantiation**:
The testbench instantiates the `ping_pong_buffer` module as `dut` and connects the signals between the module and the testbench. Each input and output from the **DUT** is connected to its corresponding signal in the testbench.
---
## **Input Generation and Validation**:
### **Clock Generation**:
The Active high clock signal `clk` is generated using an `always` block that toggles every **10 ns**.
### **Reset**:
The Asynchronous reset signal `rst_n` is **asserted** at the beginning of the simulation to ensure the **DUT** initializes correctly. After a short period (**150 ns**), the reset is **de-asserted**.
### **Stimulus**:
Multiple test cases are applied to simulate various buffer conditions and validate the correct behavior of the **ping-pong buffer**:
- **Test Case 1: Basic Write and Read**
- **Write** values sequentially into the buffer.
- **Read** them back to verify correct data storage and retrieval.
- **Test Case 2: Buffer Alternation**
- Write `DEPTH` elements to trigger **buffer switch**.
- Ensure correct alternation between ping and pong buffers.
- **Test Case 3: Writing to Full Buffer**
- Fill the buffer.
- Attempt an extra write and verify **buffer_full** signal.
- **Test Case 4: Reading from Empty Buffer**
- Ensure `buffer_empty` is asserted when reading beyond available data.
- **Test Case 5: Reset Handling**
- Apply **reset** during active operations.
- Ensure buffer returns to **initial state**.
- **Test Case 6: Edge Case - Minimum Data**
- Write and read a **single byte**.
- Ensure correct behavior in minimal operation scenarios.
- **Test Case 7: Edge Case - Maximum Data**
- Write **DEPTH** elements.
- Read all data and verify **buffer alternation**.
---
## **Reset Handling**:
After running the test cases, a **reset is asserted again** to verify that the buffer properly resets and returns to the **initial state**, with `buffer_empty` asserted.
---
```systemverilog
module tb_ping_pong_buffer;
localparam DEPTH = 256;
logic clk;
logic rst_n;
logic write_enable;
logic read_enable;
logic [7:0] data_in;
logic [7:0] data_out;
logic buffer_full;
logic buffer_empty;
logic buffer_select;
// Instantiate the DUT
ping_pong_buffer dut (
.clk(clk),
.rst_n(rst_n),
.write_enable(write_enable),
.read_enable(read_enable),
.data_in(data_in),
.data_out(data_out),
.buffer_full(buffer_full),
.buffer_empty(buffer_empty),
.buffer_select(buffer_select)
);
// Clock generation
always #5 clk = ~clk;
initial begin
// Initialize signals
clk = 0;
rst_n = 0;
write_enable = 0;
read_enable = 0;
data_in = 0;
$display("Applying Reset...");
#10 rst_n = 1;
$display("Testing Basic Write and Read Operations...");
for (int i = 0; i < 10; i++) begin
@(posedge clk);
write_enable = 1;
data_in = i;
@(posedge clk);
write_enable = 0;
@(posedge clk);
read_enable = 1;
@(posedge clk);
read_enable = 0;
@(posedge clk);
end
// Insert code here to complete the Testbench
endmodule
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | ping_pong_buffer | dut | [
{
"name": "ping_pong_buffer.sv",
"content": "module ping_pong_buffer (\n input logic clk,\n input logic rst_n,\n input logic write_enable,\n input logic read_enable,\n input logic [7:0] data_in,\n output logic [7:0] data_out,\n output logic buffer_full,\n output logic buffer_empty,\n... | [] |
cvdp_copilot_hebbian_rule_0020 | medium | Non-Agentic | Create a SystemVerilog testbench module named `tb_hebb_gates` that instantiates the `hebb_gates` module as the Unit Under Test (UUT). The testbench must include a stimulus generator that systematically drives various input conditions to achieve a minimum of 95% code and functional coverage for the `hebb_gates` module. The `hebb_gates` implements a Moore Finite State Machine (FSM) to train a Hebbian learning model. The module takes signed 4-bit inputs (`a` and `b`), a 2-bit gate selector, and control signals for starting the FSM and resetting the system. It sequentially performs training steps such as weight initialization, target selection, weight/bias updates, and convergence checks using the Hebbian learning rule. The module outputs the updated weights (`w1` and `w2`), bias, and the FSM's current and next state. The system uses a gate selection module to determine the target outputs based on logical gate operations for training.
## Design Specifications:
- Hebbian rule is a type of unsupervised neural network learning algorithm
## Abstract Algorithm:
- The hebbian or hebb rule works based on the following algorithm
- **Step 1**: Initialize all the weights and bias to zero.
w<sub>I</sub> = 0 for i = 1 to n, n is the number of input vectors
- **Step 2**: For each input training vector and target output pair, do the following:
- **Step 2a**: Set activation for input units
x<sub>i</sub>=s<sub>i</sub>, x is a register to store the input vector, where x is a register to store the input vector
- **Step 2b**: Set activation for output unit
y = t, where t is the target vector and y is the output vector
- **Step 2c**: Adjust the weights and bias
w<sub>i</sub>(new) = w<sub>i</sub>(old) + delta_w
bias(new) = bias(old) + delta_b
Where:
delta_w = x<sub>I</sub> * t
delta_b = t
## Inputs and Outputs:
## Inputs:
- `clk` (1-bit): Posedge Clock signal.
- `rst` (1-bit): Asynchronous Negedge Reset signal. When asserted LOW , the FSM is initialized to State_0 and iteration counter is initialized to 0.
- `start `(1-bit): Active HIGH Signal to initiate the FSM.
- `a`, `b` (4-bit each, [3:0], signed): Bipolar input signals [-1 ,1]. Only -1 and 1 have to be considered as valid inputs
- `target_select`(2-bit,[1:0]): Selector to specify the target for a given gate.
- `gate_select` (2-bit,[1:0]): Selector to specify the given gate
## Outputs:
- `w1`, `w2` (4-bit each,[3:0], signed): Trained weights for the inputs.
- `bias` (4-bit, signed,[3:0]): Trained bias value.
- `present_state`, `next_state` (4-bit each,[3:0]): Current and next states of the Training FSM.
**Instantiation** :
The testbench instantiates the `hebb_gates` module as uut and connects the signals between the module and the testbench. Each input and output from the uut is connected to its corresponding signal in the testbench.
## **Input Generation and Validation**:
**Stimulus**: The test bench should employ multiple tasks to simulate training epochs for different gate selections, each applying a sequence of input stimuli. Each task should correspond to one epoch for a given gate configuration and varies the input combinations of signals' a and `b`, along with control signals `gate_select` and `target_select`.
**Gate 00 (gate_select = 2’b00) Epochs**:
**Test Case 1: First Epoch for Gate 00**:
- Control: `gate_select` should be set to 00, `target_select` should be set to 00, and `start` should be asserted HIGH.
- Inputs: A sequence where (a, b) takes on values: (1, 1) → (1, –1) → (–1, 1) → (–1, –1).
**Test Case 2: Second Epoch for Gate 00**:
- Control: `gate_select` should be set to 00, and `target_select` should be set to 01.
- Inputs: The sequence is modified to start with (–1, –1) and then vary through (–1, 1), (1, –1), and (1, 1).
**Test Case 3: Third Epoch for Gate 00**:
- Control: `gate_select` should be set to 00, `target_select` should be set to 10.
- Inputs: Similar to previous epochs but with a different ordering of input polarity to test consistency in weight and state transitions.
**Test Case 4: Fourth Epoch for Gate 00**:
- Control: `gate_select` should be set to 00, `target_select` should be set to 11.
- Inputs: Another permutation of input values is applied to verify module behavior further.
**Test Case 5: Fifth Epoch for Gate 00 (Invalid Target)**:
- Control: `gate_select` should be set to 00, `target_select` should be set to an unknown value (2’bxx).
- Inputs: Standard sequence similar to the first epoch.
**Gate 01 (gate_select = 2’b01), Gate 10 (gate_select = 2’b10), and Gate 11 (gate_select = 2’b11) Epochs**:
- For each valid gate (01, 10, 11), the testbench defines four epochs with explicitly defined target selections (00, 01, 10, 11) and a fifth epoch using an unknown target (2’bxx).
- In each epoch, the tasks apply a similar method: a sequence of input combinations is applied to a and b with specific delays (#60, #70, #80, etc.) to mimic realistic timing conditions.
**Invalid Gate Epochs**:
**Test Case: Invalid Epochs 1–5**
- Control: `gate_select` should be set to an unknown value (2’bxx), with target selections both valid (00–11) and completely unknown (2’bxx).
Inputs: A variety of input patterns (including zeros and mixed values) are applied.
## Learning Logic:
- Weights (w1, w2) and bias are updated incrementally based on the input values and a computed error:
delta_w1 = x1 * target
delta_w2 = x2 * target
delta_b = target
w1 = w1 + delta_w1
w2 = w2 + delta_w2
bias = bias + delta_b
- Target values are determined using a `gate_target` submodule based on `gate_select`:
- gate_select = 2'b00: AND gate behavior.
- gate_select = 2'b01: OR gate behavior.
- gate_select = 2'b10: NAND gate behavior.
- gate_select = 2'b11: NOR gate behavior.
## FSM Design:
There are 11 states handled by Moore FSM.
- State_0: Reset state.
- State_1: Capture inputs.
- State_2-State_6: Assign targets based on the selected gate.
- State_7: Compute deltas for weights and bias.
- State_8: Update weights and bias.
- State_9: Loop through training iterations.
- State_10: Return to the initial state.
## Functional Requirements:
- Weight adjustment must follow the Hebbian learning rule.
- The FSM must support multiple training iterations for every possible input combination of a two-input logic gate.
- Outputs (`w1`, `w2`, `bias`) should reflect trained values at the end of the process. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | hebb_gates | uut | [
{
"name": "hebb_gates.sv",
"content": "`timescale 1ns/1ps\nmodule hebb_gates(\n input logic clk, // Posedge clk\n input logic rst, // Asynchronous negedge rst\n input logic start, // To start the FSM\n input logic [1:0] t... | [] |
cvdp_copilot_sync_serial_communication_0009 | easy | Non-Agentic | Write a SystemVerilog testbench for a `sync_serial_communication_tx_rx` module, which simulates the `tx_block` and `rx_block` modules and performs data transfer operations with a focus on ensuring the proper handling of data values, selection signals(`sel`), and asynchronous resets. The testbench must apply a sequence of test cases to the instantiated RTL module, focusing on data transfer operations.
## Description
**Inputs:**
- `clk`: Clock signal for synchronization. Design works on the posedge of `clk`.
- `reset_n`: Active-low asynchronous reset signal.
- `sel [2:0]`: Controls the data width for the transmitter (TX):
- `3'h0:` 0 bits. No transmission happens
- `3'h1:` 8 bits. `data_in [7:0]` is the valid data to be transmitted.
- `3'h2:` 16 bits. `data_in [15:0]` is the valid data to be transmitted.
- `3'h3:` 32 bits. `data_in [31:0]` is the valid data to be transmitted.
- `3'h4:` 64 bits. `data_in [63:0]` is the valid data to be transmitted.
- Default: 0 bits
- `data_in [63:0]`: Input data signal.
**Outputs:**
- `data_out [63:0]`: Output data received from the communication module.
- `done`: Signal indicating transmission completion.
## Module Description
The `sync_serial_communication_tx_rx` module simulates serial communication behavior with configurable selection modes (`sel`).
- **Transmission block(`tx_block`):**
- The transmitter(TX) and receiver (RX) operate synchronously, driven by the same clock signal (`clk`) and reset (`reset_n`).
- Upon reset (reset_n) became LOW, all internal counters and registers are reset to their initial values.
- The transmitter (TX) is responsible for serializing 8, 16, 32, or 64-bit data input based on the `sel` signal and produces serial data.
- During data transfer, a gated clock signal serial_clk which operates at the frequency of clk has to be transmitted to the receiver (RX) alongside the serial data. When no data is transmitted, it remains at a fixed logic state of either HIGH or LOW.
- The transmitter (TX) generates the serial clock signal serial_clk that is used by both the transmitter (TX) and receiver (RX) for synchronized communication to transmit and receive one bit each during the positive edge of the clock.
- **Receiver block(`rx_block`):**
- Data sampling in the receiver (RX) is valid whenever serial_clk is active.
- The `sel` in the RX module receives the same value of sel maintained by the TX module
- The receiver (RX) receives the serial data from the transmitter (TX) and reconstructs it into a 64-bit parallel output (`data_out`).
- The `data_out` will have the following data based on the `sel` value
- If `sel` is 000, `data_out` = 64'h0
- If `sel` is 001, `data_out` = {56'h0,data_in[7:0]}
- If `sel` is 010, `data_out` = {48'h0,data_in[15:0]}
- If `sel` is 011, `data_out` = {32'h0,data_in[31:0]}
- If `sel` is 100, `data_out` = data_in[63:0]
- default: 64'h0
- The `done` signal High indicates the valid output.
- Reset behavior ensures that the system initializes correctly before starting new data transactions.
## Testbench Requirements
### Module Instantiation:
- The `sync_serial_communication_tx_rx` module should be instantiated as uut, with all input and output signals properly connected. The testbench must achieve **100% coverage** by covering all input cases.
### Input Stimulus Generation
The testbench implements task designed to validate a specific functionality:
**drive_data task:**
- Accepts three integer inputs: sel_mode, range, and data_in_val.
- Waits for a positive edge of the `clk` signal.
- Based on sel_mode, assigns different portions of data_in_val to data_in:
- If sel_mode == 1, assign the least significant 8 bits ([7:0]).
- If sel_mode == 2, assign the least significant 16 bits ([15:0]).
- If sel_mode == 3, assign the least significant 32 bits ([31:0]).
- If sel_mode == 4, assign the full 64-bit value ([63:0]).
- Otherwise, set range_value = 8 and data_in_rand = 64'd0.
- Assign `data_in` = data_in_val and iterate range times, setting `sel` = sel_mode[2:0] at each iteration, synchronized to `clk`.
- Wait for the `done` signal to be asserted.
- Print a message displaying the values of `sel`, `data_in`, `data_out`, and `done`.
**initial block:**
- Asserts `reset_n` and initializes `data_in` to zero.
- Calls a reset procedure.
- Repeats a random test sequence 10,000 times:
- Randomly selects a sel_value between 1 to 4.
- Sets range_value and data_in_rand based on sel_value:
- **sel_value == 1:** range_value = 8, data_in_rand is a random 7-bit number.
- **sel_value == 2:** range_value = 16, data_in_rand is a random 16-bit number.
- **sel_value == 3:** range_value = 32, data_in_rand is a random 31-bit number.
- **sel_value == 4:** range_value = 64, data_in_rand is a random 64-bit number.
- Otherwise, range_value = 8, data_in_rand = 64'd0.
- Calls the `drive_data` task with the generated values.
- Calls the reset procedure.
- After completion, waits **100 ns** and terminates the simulation.
Can you implement a SystemVerilog testbench with the above specifications to thoroughly validate the task? | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | sync_serial_communication_tx_rx | uut | [
{
"name": "sync_serial_communication_top.sv",
"content": "`timescale 1ns / 1ps\nmodule sync_serial_communication_tx_rx(\n input clk, // Clock signal\n input reset_n, // Active low reset signal\n input [2:0] sel, // Selection signal for TX block\n ... | [] |
cvdp_copilot_hamming_code_tx_and_rx_0029 | easy | Non-Agentic | Create a testbench that only supplies stimulus to a `hamming_code_tx_for_4bit` module, which encodes 4-bit input data `data_in` into an 8-bit output `data_out` using Hamming code principles for error detection and correction. Hamming code helps generate parity bits, which are combined with the original data to detect and correct single-bit errors.
---
## **Testbench Description**
**Inputs**
- Registers: `data_in` is a 4-bit register that provides binary inputs to the module.
**Outputs**
- Wire: An 8-bit wire, `data_out`, with 4 data bits, 3 parity bits and an extra redundant bit added to pad the output to 8 bits.
---
## **Instantiation**
- Module Instance: The `hamming_code_tx_for_4bit` module should be instantiated as **uut_transmitter**, with the input and output signals connected for testing.
---
## **Input Generation and Validation**
- Input Generation: The testbench must generate pairs of 4-bit binary values for `data_in` to cover all possibilities, including corner cases.
- Corner cases Input Generation: The testbench must generate pairs of 4-bit binary values from minimum value 0 to maximum 2<sup>4</sup> - 1
- Stabilization Period: After setting each pair of inputs, the testbench waits 10 time units to ensure the outputs have stabilized before asserting new values.
---
## **RTL Specification:**
1. **Module interface:**
- Input:
`data_in[3:0]`: A 4-bit input signal representing the original data to be transmitted.
- Output:
`data_out[7:0]`: An 8-bit output signal representing the encoded data.
2. **Module Functionality**:
The module encodes the data based on the following steps:
1. `data_out[0]`: This bit is fixed to 0 as a redundant bit.
2. `data_out[1]`, `data_out[2]` `data_out[4]`: Parity bits , calculated using the XOR operation to ensure even parity of specific input bits.
3. `data_out[3]`, `data_out[5]`, `data_out[6]`, `data_out[7]`: These are assigned `data_in[0]`, `data_in[1]`, `data_in[2]`, `data_in[3]` respectively, preserving the order of the input data.
3 **Timing and Synchronization:**
- This design is purely combinational. The output must be immediately updated with a change in the input. | [
{
"inst_name": "uut_transmitter",
"metric": "Overall Average",
"target_percentage": 91
}
] | hamming_code_tx_for_4bit | uut_transmitter | [
{
"name": "hamming_code_tx_for_4bit.sv",
"content": "module hamming_code_tx_for_4bit( \n input[3:0] data_in,\n output[7:0] data_out\n);\n assign data_out[0] = 1'b0;\n assign data_out[1] = data_in[0] ^ data_in[1] ^ data_in[3]; // 2^0\n assign data_out[2] = data_in[0] ^ data_in[2] ^ data_in[3]; // 2^1\n ... | [] |
cvdp_copilot_sram_fd_0024 | easy | Non-Agentic | Generate a SystemVerilog testbench named `cvdp_sram_fd_tb` that only generates stimulus, to systematically drive input signals to a **cvdp_sram_fd** module. The stimulus should comprehensively cover all valid read and write operations with constraints as mentioned below.
---
## Module Overview:
The **cvdp_sram_fd** module is a full-duplex, dual-port static RAM (SRAM) with independent read and write access on two separate ports (**Port A** and **Port B**). The memory has a configurable data width (`DATA_WIDTH`) and address width (`ADDR_WIDTH`).
**Key Features:**
- **Dual-port architecture**: Supports concurrent read/write operations on both ports.
- **Synchronous operation**: Inputs are sampled on the rising edge of `clk`.
- **Read-First behavior**: If a read and write happens at the same address in the same cycle, the read returns the old data before the write updates it.
---
### **Parameters:**
- `DATA_WIDTH (default: 8)`: Width of the data bus.
- `ADDR_WIDTH (default: 4)`: Width of the address bus.
- `RAM_DEPTH`: Determines the depth of the memory. It is derived using the `ADDR_WIDTH` parameter to match the full range of unique addresses possible with the given address width.
### **Ports:**
#### 1. Clock and Control Signal Inputs:
- `clk`: System clock. All input transitions are synchronized to the **rising edge** of `clk`.
- `ce`: Chip enable (active high).
- When `ce` is **low**, the memory ignores all inputs and does not perform read or write operations (`a_rdata` and `b_rdata` are set to zero).
- When `ce` is **high**, the memory operates normally.
#### 2. Port A:
**Inputs:**
- `a_we`: Write enable (active high).
- `a_oe`: Read enable (active high).
- `a_addr [ADDR_WIDTH-1:0]`: Address bus.
- `a_wdata [DATA_WIDTH-1:0]`: Write data.
**Output:**
- `a_rdata [DATA_WIDTH-1:0]`: Read data output.
#### 3. Port B:
**Inputs:**
- `b_we`: Write enable (active high).
- `b_oe`: Read enable (active high).
- `b_addr [ADDR_WIDTH-1:0]`: Address bus.
- `b_wdata [DATA_WIDTH-1:0]`: Write data.
**Output:**
- `b_rdata [DATA_WIDTH-1:0]`: Read data output.
#### 4. Memory Array:
- The module consist of an internal memory array `mem` with depth `RAM_DEPTH` and width `DATA_WIDTH`.
#### 5. Operational Behavior:
- **Port A Operations:**
- **Write Operation:**
- Occurs when `ce` and `a_we` are high.
- The data on `a_wdata` is written to the memory location specified by `a_addr`.
- **Read Operation:**
- Occurs when `ce` is high, and `a_oe` is high.
- The data from the memory location specified by `a_addr` is loaded into `a_rdata`.
- `a_rdata` retains its previous value if `a_oe` is low while `ce` is high
- **Priority:**
- If both `a_we` and `a_oe` are high, the read operation takes precedence, where data previously stored at the address appears on the output while the input data is being stored in memory.
- **Timing:**
- **Write Latency:** 1 clock cycle.
- **Read Latency:** 1 clock cycle.
- **Port B Operations:**
- This port behaves same as Port A. The signals controlling this port are `b_we`, `b_oe`, `b_addr`, `b_wdata` and the output is driven on `b_rdata`.
#### 6. Simultaneous Access Handling:
- The memory supports simultaneous operations on both ports, including:
- Reads on both ports.
- Writes on both ports.
- A read on one port and a write on the other.
- **Same Address Access:**
- **If both ports access the same address:**
- Read and write: Follow a "read-first" approach which means that if a write and read occur at the same address simultaneously, data previously stored at the address appears on the output while the input data is being stored in memory.
- Reads on both ports: Should be supported with both ports providing the same output data.
- It is assumed that the write access will not occur for the same address on both ports together. Such a collision is not handled.
#### 7. Assumptions and Constraints:
- All inputs are synchronous and are sampled on the rising edge of `clk`.
- Input addresses (`a_addr`, `b_addr`) are within the valid range (`0` to `RAM_DEPTH - 1`).
- Data inputs (`a_wdata`, `b_wdata`) are valid when write enables (`a_we`, `b_we`) are high.
- If neither read nor write is enabled for a port during a clock cycle (with `ce` high), the port maintains its previous output state.
#### 8. Boundary Conditions:
- `DATA_WIDTH` and `ADDR_WIDTH` must be positive integers greater than zero.
---
## **Testbench Requirements:**
### **Module Instantiation:**
The **cvdp_sram_fd** module should be instantiated as `DUT`, with all input and output signals properly connected. The testbench must cover all possible scenarios to achieve 100% coverage.
### **Stimuli Generation for Dual-Port SRAM Testbench:**
#### 1. Clock and Enable Control:
- Generate a continuous clock signal with a period of 10 time units.
- Toggle `ce` periodically to simulate active/inactive states.
#### 2. Address and Data Generation:
- **Address Sequences**
- Use randomized or structured address sequences for `a_addr` and `b_addr` for read and write operations.
- **Data Sequences**
- Generate randomized `a_wdata` and `b_wdata` values.
- Drive valid data only when write enable (`a_we`, `b_we`) is high.
#### 3. Different Scenarios:
- **A.Independent Operations**
- **Single Port Write-Read:** Generate stimuli for Port A to write to a given address and read from the same address after the write is complete. Perform the same operation on port B
- **B. Simultaneous Operations**
- **Simultaneous Writes:**
- Generate stimuli to simultaneously write and read from the same port and from the same address.
- Generate stimuli to simultaneously write from one port and read from the other at the same address.
- Generate stimuli to simultaneously write from one port and read from the other at different addresses.
- **C. Special Cases**
- **Boundary Testing:** Generate stimuli to write at minimum (`0`) and maximum (`RAM_DEPTH-1`) addresses.
- **Chip Enable Disabled:** Generate stimuli for `ce = 0`.
- **Chip Enabled with no operation:** Generate stimuli for `ce = 1` with no read/write operations on either port.
---
**Expected Output:**
A SystemVerilog testbench that generates varied input stimuli for the **cvdp_sram_fd** module according to the above specifications and allows different corner cases for extended testing scenarios. | [
{
"inst_name": "DUT",
"metric": "Overall Average",
"target_percentage": 100
}
] | cvdp_sram_fd | DUT | [
{
"name": "cvdp_sram_fd.sv",
"content": "/**************************************************************************\nFILENAME: cvdp_sram_fd.sv\nDESCRIPTION: This file contains the RTL for a full-duplex dual-port RAM in SystemVerilog.\nLATENCY: Write latency = 1 clk cycle\n Read latency ... | [] |
cvdp_copilot_MSHR_0003 | medium | Non-Agentic | Develop a SystemVerilog module named `tb_cache_mshr` that only generates input stimulus to a `cache_mshr` module. `cache_mshr` module implements Miss Status Handling Registers (MSHR). The MSHR is a critical component of a **non-blocking cache architecture**, enabling the system to handle multiple outstanding cache misses concurrently.
---
## RTL Specification
### **Parameters**
- **`INSTANCE_ID`** *(default = "mo_mshr")*:
A string identifier for the MSHR instance. This parameter allows users to assign a unique name to each instance of the MSHR module.
- **`MSHR_SIZE`** *(default = 32)*:
Specifies the total number of entries available in the MSHR. This defines how many pending requests can be tracked simultaneously.
- **`CS_LINE_ADDR_WIDTH`** *(default = 10)*:
The bit-width required to represent the cache line address. This parameter determines the number of unique cache lines that can be indexed.
- **`WORD_SEL_WIDTH`** *(default = 4)*:
Specifies the number of bits needed to select a specific word within a cache line. For example, with a cache line containing 16 words, ( log<sub>2</sub>(16) = 4 ) bits are required.
- **`WORD_SIZE`** *(default = 4)*:
Word size in **bytes**. It represents the number of bits in the byte enable signal for a word. This indicates which bytes within the word are active during a write operation.
---
### **Derived Parameters**
- **`TAG_WIDTH`**:
The bit-width of the tag portion of the address. It is calculated as:
32 - `CS_LINE_ADDR_WIDTH`+ log2(`WORD_SIZE`) + `WORD_SEL_WIDTH`
- **`CS_WORD_WIDTH`**:
word width in bits . It is calculated as WORD_SIZE * 8
- **`DATA_WIDTH`**:
Defines the total data width for each MSHR entry. It is calculated as:
`WORD_SEL_WIDTH` + `WORD_SIZE` + `CS_WORD_WIDTH` + `TAG_WIDTH`
- **`MSHR_ADDR_WIDTH`**:
Defines the number of bits required to address all entries in the MSHR. It is calculated as:
`$clog2(MSHR_SIZE)`
---
### Port List
| **Port Name** | **Direction** | **Description** |
|-----------------------------------------|---------------|------------------------------------------------------------------------------------------------|
| `clk` | Input | Clock signal. The design registers are triggered on its positive edge. |
| `reset` | Input | Active high synchronous reset signal |
| `allocate_valid` | Input | Active high signal indicating a new core request for allocation. |
| `allocate_addr[CS_LINE_ADDR_WIDTH-1:0]` | Input | Cache line address of the new request. |
| `allocate_data[DATA_WIDTH-1:0]` | Input | Request data containing the word address, byte enable signal, write data, and tag information. |
| `allocate_rw` | Input | Read/write operation type for the new request. 1'b1 = write request, 1'b0 = read request |
| `allocate_id[MSHR_ADDR_WIDTH-1:0]` | Output | ID of the allocated slot. |
| `allocate_pending` | Output | Active high signal indicating if a new request is for a cache line that is already pending. |
| `allocate_previd[MSHR_ADDR_WIDTH-1:0]` | Output | ID of the previous entry for the same cache line if `allocate_pending` asserted. |
| `allocate_ready` | Output | Active high signal indicating if a new request can be allocated. If MSHR isn't full |
| `finalize_valid` | Input | Active high signal indicating a finalize operation is being requested. |
| `finalize_id[MSHR_ADDR_WIDTH-1:0]` | Input | ID of the entry being finalized. |
### Functional description:
This design should integrate seamlessly into a non-blocking cache system with a 32-bit address system, where tag access and MSHR access occur in parallel.
- On core request, `allocate_valid`, the MSHR allocates an entry for the incoming core request, regardless of whether it is a hit or miss. `allocate_valid` could only be asserted when `allocate_ready` is asserted, indicating there is an available MSHR entry
- In the subsequent cycle, the cache tag access determines if the request is a hit or miss. If the request is a cache hit, the allocated MSHR entry is immediately marked invalid. `finalize_valid` will be asserted only on cache hit, `finalize_id` should be one of the allocated indexes.
---
## Testbench Requirements
### Instantiation
Name the instance of the RTL as `dut`.
### Required Stimulus Description:
The objective is to achieve **100% code and toggle coverage** for the `cache_mshr` module by systematically exercising its functionality. The stimulus should ensure that all key features and transitions of the module are exercised while maintaining coverage goals.
- Use a `cache_mshr` instance named `dut` in the testbench.
- Supply stimulus to ensure that all MSHR entries are allocated during simulation, randomly asserting `allocate_valid` at random clock negative edges and randomize input signals: `allocate_addr`, `allocate_data`, and `allocate_rw`.
- Supply stimulus to ensure that all MSHR entries are finalized during simulation, randomly asserting `finalize_valid` at random clock negative with `finalize_id` one of the allocated slots.
- Fully exercise state transitions for every entry, including toggling between **write** and **read** operations.
- Fully exercise cases where each entry points to the next request for the same cache line ( eg: use a fixed cache line)
- Cover the module’s behavior when the MSHR reaches full capacity, including the deassertion of `allocate_ready`.
- Cover that `allocate_ready` is reasserted when entries are finalized and space becomes available.
- Generate stimuli for both cache hit and miss scenarios randomly to ensure proper entry finalization and release.
### Latency:
- Allocation Requests: The module introduces a latency of 1 clock cycle for each allocation request.
- Finalize Requests: The module introduces a latency of 1 clock cycle for each finalize release request. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | cache_mshr | dut | [
{
"name": "cache_mshr.sv",
"content": "`define NOTCONNECTED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \\\n . x () \\\n /* verilator lint_on PINCONNECTEMPTY */\n\nmodule cache_mshr #(\n parameter INSTANCE_ID = \"mo_mshr\" ,\n ... | [] |
cvdp_agentic_rgb_color_space_conversion_0009 | medium | Agentic | The specification document for the `rgb_color_space_conversion` module is present in the `docs` folder. Write a SystemVerilog testbench, `tb_rgb_color_space_conversion.sv`, in the `verif` directory to only generate stimulus for the `rgb_color_space_conversion` module to achieve maximum coverage of the UUT.
Include the following in the generated testbench:
### 1. **Module Instance**:
The `rgb_color_space_conversion` module should be instantiated as `uut`, with the input and output signals connected for testing.
### 2. **Input Generation**:
The testbench must generate inputs to cover all possibilities, including corner cases, edge cases, and high-range values.
### 3. **Computation Period**:
After setting each pair of inputs, the testbench should wait until the assertion of the `valid_out` signal to ensure the outputs have stabilized before providing the next input. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | rgb_color_space_conversion | uut | [
{
"name": "rgb_color_space_conversion.sv",
"content": "module rgb_color_space_conversion (\n input clk,\n input rst,\n\n // Memory ports to initialize (1/delta) values\n input we,\n input [7:0] waddr,\n input [24:0] wdata,\n\n // ... | [
{
"name": "specification.md",
"content": "# RGB to HSV/HSL Conversion Module Specification Document\n\n## Introduction\n\nThe **RGB to HSV/HSL Conversion Module** is designed to convert RGB (Red, Green, Blue) color space values into both HSV (Hue, Saturation, Value) and HSL (Hue, Saturation, Lightness) colo... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.