LLM4Cov
Collection
6 items • Updated
id string | difficulty string | is_agentic string | instruction string | targets list | dut_module_name string | dut_instance_name string | rtl_files list | spec_files list |
|---|---|---|---|---|---|---|---|---|
cvdp_agentic_byte_enable_ram_0004 | medium | Agentic | I have a specification of a custom_byte_enable_ram module in the docs directory. Write a SystemVerilog testbench `tb_custom_byte_enable_ram.sv` in the verif directory to apply stimulus and achieve maximum coverage for the `custom_byte_enable_ram` module.
Include the following in the generated testbench:
**Module Instance**:
Instantiate the `custom_byte_enable_ram` module as `uut`, ensuring that all input and output ports (covering both port A and port B) are properly connected.
**Clock Generation**:
Implement a clock generator with a 10ns period.
**Stimulus Scenarios**:
In the testbench’s initial block, apply a series of stimulus sequences with delays and $display statements (without using tasks) that cover the following 13 test cases:
- **Test 1**: Full write via port A at address 0 followed by a read-back.
- **Test 2**: Partial write via port B at address 1 followed by a read-back.
- **Test 3**: Dual-port simultaneous write at address 2 with port A writing lower bytes and port B writing upper bytes, then reading back from both ports.
- **Test 4**: Sequential partial writes on port A at address 3, with an initial write using one byte-enable pattern and a subsequent write using a complementary pattern, then reading back.
- **Test 5**: Independent full writes on port A (at address 5) and port B (at address 6) with subsequent reads.
- **Test 6**: Dual-port full write at the same address (address 4) by both ports, then reading the final value (noting that port A’s bytes have priority).
- **Test 7**: Dual-port overlapping partial write at address 7 with interleaved byte enables, then reading back.
- **Test 8**: Dual-port write at address 9 where port A has no active byte enables and port B performs a full write, followed by a read-back.
- **Test 9**: Sequential writes at address 10 with an initial full write via port A and a subsequent partial update via port B, then reading back.
- **Test 10**: A no-update scenario at address 11 where an initial full write is not altered by a cycle with both ports enabled but with zero byte enables, then reading back.
- **Test 11**: Write at address 25 with only port B enabled, then reading back from both ports.
- **Test 12**: Read at addresses 100 and 101 with both ports disabled to verify unchanged memory.
- **Test 13**: Separate partial writes at different addresses (address 12 via port A and address 13 via port B) with subsequent reads.
The testbench should structure these stimulus sequences directly within an initial block using appropriate delays and $display calls for traceability and debugging. Do not include checker logic or internal state validation—this testbench is solely for generating stimulus. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | custom_byte_enable_ram | uut | [
{
"name": "custom_byte_enable_ram.sv",
"content": "module custom_byte_enable_ram \n #(\n parameter XLEN = 32,\n parameter LINES = 8192\n )\n (\n input logic clk,\n input logic[$clog2(LINES)-1:0] addr_a,\n input logic en_a,\n input logic[XLEN... | [
{
"name": "specs.md",
"content": "# Custom Byte-Enable RAM Module\n\nThis module implements a dual-port RAM with byte-enable support and pipelining, designed for efficient memory operations in systems such as processors or embedded controllers. It features separate interfaces for two independent ports (Port... |
cvdp_copilot_hamming_code_tx_and_rx_0031 | easy | Non-Agentic | Create a testbench to only supply stimulus to a `hamming_code_receiver` module. This module decodes an 8-bit input signal and detects single-bit errors using Hamming code principles. The receiver performs "even parity checks" to identify single-bit errors in `data_in` and provides corrected 4-bit data through the output port `data_out[3:0]`.
---
### **RTL Specification**
#### 1. **Module Interface**
**Inputs:**
- `data_in[7:0]` – An 8-bit input signal containing 4 data bits, 3 parity bits, and 1 redundant bit.
**Output:**
- `data_out[3:0]` – A 4-bit output signal containing the corrected data if an error is detected. If no error is detected, the output mirrors the data bits in the input (`data_in`).
#### 2. **Module Functionality**
The module uses Hamming code principles to detect and correct single-bit errors in the 8-bit input (`data_in`). The organization of bits in the input is as follows:
- **Parity Bits:** Placed at positions that are powers of 2 in `data_in`:
- `data_in[1]` (2<sup>0</sup> = 1),
- `data_in[2]` (2<sup>1</sup> = 2),
- `data_in[4]` (2<sup>2</sup> = 4).
- **Data Bits:** Placed sequentially in positions that are not powers of 2:
- `data_in[3]`, `data_in[5]`, `data_in[6]`, and `data_in[7]`.
#### 2.1. **Error Detection and Correction**
- The module calculates three syndrome bits (`c1`, `c2`, `c3`) using XOR operations on specific data and parity bits from `data_in`. These syndrome bits indicate the position of any error within the 7 most significant bits (`data_in[7:1]`).
- If an error is detected, the incorrect bit is corrected.
#### 2.2. **Output Assignment**
- After error correction, the module retrieves the 4 data bits from the corrected input and assigns them to the output port `data_out[3:0]`.
- The positions of the data bits in the input correspond to:
- `data_in[3]`, `data_in[5]`, `data_in[6]`, and `data_in[7]`.
#### 3. **Timing and Synchronization**
- The design is purely combinational, meaning the output is updated immediately after any change in the input.
---
### **Testbench Requirements**
- **Module Instance:** The `hamming_code_receiver` module should be instantiated as **`uut_receiver`**, with input and output signals connected for testing.
---
### **Input Generation and Validation**
1. **Input Generation:**
- The testbench should generate all possible 4-bit binary values for input data (ranging from the minimum value (0) to the maximum value (2<sup>4</sup> - 1)) and extend it to include encoding bits before supplying the stimulus to the design, ensuring coverage of both typical cases and edge cases.
3. **Golden Encoder Logic:**
- Inputs provided to the module should follow a specific pattern similar to data generated from a transmitter following hamming code principles. It should also ensure that erroneous input data is supplied with only single-bit errors (as the RTL is capable of correcting only single-bit errors)
- The testbench should encode the generated 4-bit data into an 8-bit data (golden encoded data) using Hamming code principles for error detection.
- The encoding process based on Hamming code principles is as follows: (Assume the 4-bit data generated internally is `data_in` and it is extended to `golden_data_out`)
1. **`golden_data_out[0]`**: A redundant bit, fixed at 0.
2. **`golden_data_out[1]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[0]`, `data_in[1]`, and `data_in[3]`.
3. **`golden_data_out[2]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[0]`, `data_in[2]`, and `data_in[3]`.
4. **`golden_data_out[4]`**: Parity bit ensuring even parity (XOR) for the input bits at positions `data_in[1]`, `data_in[2]`, and `data_in[3]`.
5. **`golden_data_out[3]`, `golden_data_out[5]`, `golden_data_out[6]`, `golden_data_out[7]`**: These are the data bits `data[0]`, `data[1]`, `data[2]`, and `data[3]` respectively, in the same order.
- To simulate errors, a single bit in the **golden encoded data** must be randomly modified. This modified data should then be assigned to the input of the design under test (**`uut_receiver`**).
4. **Stabilization Period:**
- After assigning each input value, the testbench must wait for 10 time units to ensure that the outputs have stabilized before asserting new values.
--- | [
{
"inst_name": "uut_receiver",
"metric": "Overall Average",
"target_percentage": 100
}
] | hamming_code_receiver | uut_receiver | [
{
"name": "hamming_code_receiver.sv",
"content": "module hamming_code_receiver (\n input[7:0] data_in,\n output [3:0] data_out\n);\n \n wire c1,c2,c3,error;\n reg[7:0] correct_data;\n \n \n assign c3 = data_in[1] ^ data_in[3] ^ data_in[5] ^ data_in[7];\n assign c2 = data_in[2] ^ data_in[3] ^ data_in... | [] |
cvdp_copilot_simple_spi_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `spi_fsm`. The module handles data transmission in a serial format from a 16-bit input vector (`i_data_in`) using an SPI protocol. The design includes proper state transitions, signal handling, and timing synchronization to ensure accurate data transmission. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
### Inputs
1. **`i_clk`** (1-bit, Input):
- System clock signal for synchronous operations.
2. **`i_rst_b`** (1-bit, Input):
- Active-low asynchronous reset. Upon activation, the system must reset all internal states and outputs.
3. **`i_data_in`** (16-bit, Input):
- Input data vector to be serialized and transmitted through the SPI bus.
4. **`i_enable`** (1-bit, Input):
- Control signal to enable or disable the block.
- High (`1`): The block operates normally, and data transmission occurs.
- Low (`0`): The block resets to the idle state, disabling transmission.
5. **`i_fault`** (1-bit, Input):
- Indicates a fault condition. If asserted, the FSM transitions to an error state, halts all activity, and drives outputs to safe defaults.
6. **`i_clear`** (1-bit, Input):
- Forces the FSM to immediately clear the current transaction, clear counters, and transition to the idle state.
---
### Outputs
1. **`o_spi_cs_b`** (1-bit, Output):
- Active-low SPI chip select signal to indicate the start and end of a transmission. Default is logic high when idle.
2. **`o_spi_clk`** (1-bit, Output):
- SPI clock signal for synchronizing data transfers. The clock signal toggles during transmission. Default is logic low when idle or disabled.
3. **`o_spi_data`** (1-bit, Output):
- Serialized SPI data output derived from the `i_data_in` input vector. Default is logic low when idle or disabled.
4. **`o_bits_left`** (5-bit, Output):
- Tracks the number of bits remaining to be transmitted during the SPI session. Default is `0x10` (all bits remaining).
5. **`o_done`** (1-bit, Output):
- Pulses high for exactly one clock cycle when a transaction is successfully completed or the FSM transitions to an error state.
6. **`o_fsm_state`** (2-bit, Output):
- Reflects the internal FSM state for external monitoring:
- `00` = Idle
- `01` = Transmit
- `10` = Clock Toggle
- `11` = Error
---
### Behavioral Requirements
1. **FSM States**:
- **Idle** (`00`): Initialize SPI signals (`o_spi_cs_b = 1`, `o_spi_clk = 0`) and wait for `i_enable = 1` to begin transmission.
- **Transmit** (`01`): Activate SPI signals (`o_spi_cs_b = 0`), load the MSB of `i_data_in` into `o_spi_data`, and start shifting the bits out sequentially.
- **Clock Toggle** (`10`): Toggle `o_spi_clk` to latch `o_spi_data` externally, decrement `o_bits_left`, and determine if more bits remain to be transmitted. If all bits are sent, assert `o_done` and transition to Idle.
- **Error** (`11`): Entered upon assertion of `i_fault`. All SPI outputs are driven to safe values (`o_spi_cs_b = 1`, `o_spi_clk = 0`, `o_spi_data = 0`,`o_done`=0,`o_bits_left=10`), and the FSM remains here until cleared or reset.
2. **Control Signals**:
- **Enable (`i_enable`)**:
- If asserted (`1`): FSM proceeds through normal transmission states (`Transmit` and `Clock Toggle`).
- If deasserted (`0`): FSM immediately transitions to Idle and resets all active outputs.
- **Clear (`i_clear`)**:
- When asserted, FSM immediately transitions to Idle, resetting all counters and outputs regardless of the current state.
3. **Done Signal (`o_done`)**:
- Asserted (high) for one clock cycle upon successful completion of transmission.
4. **FSM State Output (`o_fsm_state`)**:
- Reflects the current FSM state in real-time for external monitoring.
## Test Bench Requirements
### Stimulus Generation
**1. Reset and Initialization**
- Apply the reset is applied.
**2. Normal SPI Transmission**
- Enable the FSM and provide a valid data input to initiate a transmission.
- Introduce multiple consecutive transmissions without disabling the FSM to check if data is continuously processed as expected.
- Attempt to modify the input data while transmission is ongoing to ensure that changes do not interfere with the current operation.
**3. Control Signal Handling**
- Disable the FSM while a transmission is in progress.
- Force the FSM to clear its current operation while actively transmitting to confirm that it returns to idle without completing the remaining shifts.
**4. Error Handling**
- Introduce an error condition during transmission.
- Attempt to recover from the error by applying a reset-like condition.
**5. Clock and Edge Case Behavior**
- Make the FSM to properly toggle the SPI clock signal during transmission, synchronizing data shifts.
- Test the handling of extreme data values, including cases where only a single bit is set.
- Execute back-to-back transmissions with varying data patterns. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 94
}
] | spi_fsm | dut | [
{
"name": "spi_fsm.v",
"content": "module spi_fsm (\n input wire i_clk, // System clock\n input wire i_rst_b, // Active-low async reset\n input wire [15:0] i_data_in, // Parallel 16-bit data to transmit\n input wire i_enable, // Enable block\n input... | [] |
cvdp_copilot_word_reducer_0012 | easy | Non-Agentic | Create a testbench named `tb_Bit_Difference_Counter` using SystemVerilog to generate stimulus for the `Bit_Difference_Counter` module, which calculates the hamming distance (bitwise difference) between two inputs of equal bit width. The testbench should apply edge-case scenarios and random input patterns to thoroughly exercise the module. The testbench should only contain stimulus generator.
## Module: `Bit_Difference_Counter`
### Parameters:
- **BIT_WIDTH**: Defines the width of the input vectors, with a default value of 3. This parameter must be a positive integer greater than or equal to 1.
- **COUNT_WIDTH**: The expression calculates $clog2(BIT_WIDTH + 1), which is the width required to represent the maximum possible number of differing bits.
### Inputs
1. **`[BIT_WIDTH-1:0] input_A`**: A binary input signal.
2. **`[BIT_WIDTH-1:0] input_B`**: A binary input signal of the same width as `input_A`.
### Output
1. **`[COUNT_WIDTH-1:0] bit_difference_count`**: The output indicates the Hamming distance between `input_A` and `input_B`. The Hamming distance is the number of differing bits between the two inputs.
## Testbench Design
### Instantiation
The `Bit_Difference_Counter` module is instantiated as `dut`, with the following connections:
- **Inputs**: `input_A` and `input_B`
- **Output**: `bit_difference_count`
## Input Generation
### Edge Case Testing
1. **All Zero Inputs**: Generate a test case where both inputs are composed entirely of zeros (0).
2. **All One Inputs**: Generate a test case where both inputs are composed entirely of ones (1).
3. **Completely Different Inputs**: Generate a test case where one input is all zeros and the other is all ones.
4. **Single Bit Differences**: For each bit position in the input, generate test cases where the inputs differ by only that single bit.
### Randomized Testing
- Randomly generates 100 test cases for `input_A` and `input_B`, covering various combinations of differing bits. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 100
}
] | Bit_Difference_Counter | dut | [
{
"name": "Data_Reduction.sv",
"content": "`timescale 1ns / 1ps\n\nmodule Bit_Difference_Counter\n#(\n parameter BIT_WIDTH = 3, // Defines the width of the input vectors.\n localparam COUNT_WIDTH = $clog2(BIT_WIDTH + 1) // Calculates the width required to represent th... | [] |
cvdp_agentic_ttc_lite_0007 | hard | Agentic | I have a specification of a `ttc_counter_lite` module in the `docs` directory. Write a SystemVerilog TB `ttc_counter_lite_tb.sv` in the `verif` directory to only generate stimuli and achieve maximum functional coverage for the `ttc_counter_lite` module.
Include the following in the generated testbench:
- **Module Instance**: Instantiate the `ttc_counter_lite` module as `dut`, appropriately connecting all input and output signals.
- **Clock Generation**: Use a 100 MHz clock with a 10ns period (`clk_in`).
- **Reset Procedure**: Create an apply_reset task that
- Asserts reset for 10 clock cycles.
- Desserts it before the stimulus begin
- Reapplies reset mid-operation to test FSM recovery behavior.
- **Basic Register Access Tasks**
Implement the following tasks to drive valid AXI-style register-level operations:
- axi_write: Drives write transactions using `axi_addr`, `axi_wdata`, and `axi_write_en`.
- axi_read: Performs read transactions and prints `axi_rdata` for traceability and debug visibility.
- axi_read_force_toggle_full: Forces and releases upper toggle bits in `axi_rdata` to stimulate data bus transitions.
- drive_counter_to_upper_bits: Configures the control, match, and reload registers to run the counter long enough to
toggle the upper counter bits.
- toggle_prescaler_bits: Writes and clears the prescaler register to trigger bit toggles and verify prescaler logic.
- **Stress and Coverage Stimulus**:
Apply diverse stimuli to activate all reachable RTL states, signal transitions, and FSM paths:
- Read all defined address registers after reset to cover initial state logic.
- Write to `MATCH` and `RELOAD` registers using:
- Minimum value: `0x00000000`
- Maximum value: `0x0000FFFF`
- Drive various `CONTROL` register modes including:
- Enable / Disable
- Reload mode
- Interval mode
- Cover counter wrap-around and overflow behavior using small reload and match values.
- Perform writes/reads to invalid or unused addresses(e.g., `0xF`, `0x1000`) to trigger decoder edge cases.
- Toggle enable modes during ongoing counting to test runtime configurability.
- Apply **1-cycle read/write pulses** to target glitchy signal paths or edge-sensitive conditions.
- Perform **reset mid-operation** and after multiple transactions to test FSM recovery behavior.
- Write known upper-bit patterns to all writable registers and read them back to observe **toggle logic** in `axi_rdata`.
- Repeat read/write sequences to:
- `CONTROL`
- `MATCH`
- `RELOAD`
- `PRESCALER`
- **Stress and Sequence Coverage**
Run repeated sequences and edge cases to validate internal behavior:
- Enable timer → wait → read counter
- Enable → Disable → Enable transitions
- Write **invalid configuration values** to test FSM error handling
- Perform `Write → Read` transitions with:
- Short delays
- Long idle intervals
- Issue high-speed, back-to-back register accesses with minimal spacing
- Vary `axi_addr` to cover:
- All address bits
- Edge and boundary cases
Do not include checkers, assertions, or internal state comparisons. The testbench should be structured strictly for applying input stimulus to the DUT and exercising its logic comprehensively. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 99
}
] | ttc_counter_lite | dut | [
{
"name": "ttc_counter_lite.sv",
"content": "`timescale 1ns / 1ps\nmodule ttc_counter_lite (\n input wire clk, // Clock signal\n input wire reset, // Reset signal\n input wire [3:0] axi_addr, // AXI address for read/write\n input wire [3... | [
{
"name": "specification.md",
"content": "# ttc_counter_lite Specification Document\n\n## Introduction\n\nThe **ttc_counter_lite** module implements a lightweight, programmable timer with support for **interval and single-shot counting modes**. It includes a 16-bit up-counter, configurable match and reload ... |
cvdp_copilot_bcd_adder_0007 | easy | Non-Agentic | Create a testbench to generate stimulus for the `bcd_adder` module, which performs Binary Coded Decimal (BCD) addition on two 4-bit inputs, a and b.
## Testbench Description
### Inputs
- Registers: a and b are 4-bit registers that provide the two BCD numbers to be added.
### Outputs
- The outputs from the BCD adder include a 4-bit sum (`sum`) and a carry-out signal (`cout`).
### Instantiation
- The bcd_adder module is instantiated as uut, with the input and output signals connected for testing.
## Input Generation
- Input Data Generation: The testbench generates all possible combinations of a and b in the range from 0 to 9 (since the inputs are BCD digits).
---
Follows the specification for building the RTL of the module, use it as a reference for the verification environment too:
### Inputs
- [3:0] a: 4-bit input representing a BCD value.
- [3:0] b: 4-bit input representing another BCD value.
### Outputs
- [3:0] sum: 4-bit output representing the BCD-corrected sum of `a` and `b`.
- cout: Single-bit output indicating if a carry is generated during the BCD addition.
---
### Design Description
The `bcd_adder` module performs Binary Coded Decimal (BCD) addition. It consists of three primary blocks:
1. **Binary Adder:** A 4-bit binary adder calculates the intermediate sum (`binary_sum`) and carry (`binary_cout`).
2. **Logic Block:** Detects whether BCD correction is needed based on the upper bits of the intermediate binary sum.
3. **BCD Correction:** If correction is required, adds 6 to the intermediate sum to produce the final BCD-corrected output. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | bcd_adder | uut | [
{
"name": "bcd_adder.sv",
"content": "module bcd_adder( \n input [3:0] a, // 4-bit BCD input\n input [3:0] b, // 4-bit BCD input\n output [3:0] sum, // The corrected 4-bit BCD result of the addition\n ... | [] |
cvdp_copilot_apb_history_shift_register_0003 | medium | Non-Agentic | Create a test bench in SystemVerilog for a Verilog module named `APBGlobalHistoryRegister`. The register updates synchronously on every gated rising edge of the `history_shift_valid` clock, shifting in predicted outcomes or restoring history on mispredictions. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
---
## Instantiation
Name the instance of the RTL as **dut**.
## **RTL Parameters, Inputs - Outputs and Functional behavior**
---
### 1. Interface
#### 1.1 Clock & Reset Signals
- **`pclk`** (input): APB clock input used for all synchronous operations.
- **`presetn`** (input, active-low): Asynchronous reset for system initialization.
#### 1.2 APB Signals
- **`paddr`** (input, 10 bits): Address bus for accessing internal CSR registers.
- **`pselx`** (input): APB select signal, indicates CSR/memory selection.
- **`penable`** (input): APB enable signal, marks transaction progression.
- **`pwrite`** (input): Write-enable signal. High for writes, low for reads.
- **`pwdata`** (input, 8 bits): Write data bus for sending data to CSR registers or memory.
- **`pready`** (output, reg): Ready signal, driven high to indicate the end of a transaction.
- **`prdata`** (output, reg, 8 bits): Read data bus for retrieving data from the module.
- **`pslverr`** (output, reg): Error signal, asserted on invalid addresses.
#### 1.3 History Shift Interface
- **`history_shift_valid`** (input): On the rising edge of this signal, the values in `control_register` and `train_history` are considered valid and will trigger an update of the predict_history register.
#### 1.4 Clock Gating Enable
- **`clk_gate_en`** (input): Signal in domain of `pclk`, which will be toggle only on negative edge of `pclk` to avoid glitches. Assertion of this signal will gate the `pclk` internally to minimize switching power.
#### 1.4 Status & Interrupt Signals
- **`history_full`** (output): Indicates if the 8-bit shift register is full (all bits set to 1).
- **`history_empty`** (output): Indicates if the 8-bit shift register is empty (all bits cleared to 0).
- **`error_flag`** (output): Indicates detected errors for invalid address.
- **`interrupt_full`** (output): Asserted high to signal an interrupt when history_full is set.
- **`interrupt_error`** (output): Asserted high to signal an interrupt when error_flag is set.
---
### 2. Register Descriptions
1. **`control_register`**
- **Address:** `0x0`
- Bit fields (from LSB to MSB):
- `predict_valid` (control_register[0]): Indicates a valid branch prediction.
- `predict_taken` (control_register[1]): Predicted direction of the branch (1 = taken, 0 = not taken).
- `train_mispredicted` (control_register[2]): Indicates a branch misprediction occurred.
- `train_taken` (control_register[3]): Actual direction of the mispredicted branch (1 = taken, 0 = not taken).
- control_register[7:4]: Reserved and will be read 0.
- Read and write register.
2. **`train_history`**
- **Address:** `0x1`
- 7 bits (`train_history[6:0]`) representing the recorded branch history prior to the mispredicted branch.
- train_history[7]: Reserved and will be read 0.
- Read and write register.
3. **`predict_history`**
- **Address:** `0x2`
- 8-bit register representing the current state of the branch history shift register.
- Updated only on the rising edge of `history_shift_valid`.
- Can be read via the APB interface (using `prdata`).
- Can't be written via APB interface.
---
### 3. Functional Description
#### 3.1 APB Protocol
1. **Read Operations**
- In the **READ_STATE**:
- Drive `prdata` with the register value corresponding to `paddr`.
- After the read completes, return to **IDLE**.
2. **Write Operations**
- In the **WRITE_STATE**:
- Update the register selected by `paddr` with `pwdata`.
- After the write completes, return to **IDLE**.
3. **Reset Behavior**
- When `presetn` is deasserted (active-low):
- Reset `pready` and `pslverr` to 0.
- Clear `prdata`.
- Initialize `control_register` and `train_history` to 0.
- Reset the shift register to zero (`predict_history = 8'b0`).
#### 3.2 APB Interface Control
1. **Basics**
- Registers are accessed via the APB interface using `paddr`.
- To read the computed prediction history, use address **0x2**; the data is returned on `prdata`.
2. **Error Handling**
- If `paddr` does not correspond to a valid register, assert `pslverr` (`1'b1`).
3. **Wait States**
- This design does not support wait states. All read/write operations complete in two clock cycles, and `pready` is always driven high (`1'b1`).
---
### 4. Prediction Update Logic
1. **Normal Update**
- If `predict_valid = 1` and no misprediction occurs (`train_mispredicted = 0`), the shift register updates by shifting in `predict_taken` from the least significant bit (LSB). The youngest branch direction is stored in `predict_history[0]`.
2. **Misprediction Handling**
- If `train_mispredicted = 1`, the shift register is updated synchronously with `history_shift_valid` to load the concatenation of `train_history` (7 bits) with `train_taken` (1 bit). This restores the history state before the mispredicted branch while incorporating the actual outcome of the mispredicted branch.
3. **Priority**
- If both `predict_valid` and `train_mispredicted` are asserted simultaneously, `train_mispredicted` takes precedence. The misprediction state overrides any prediction to ensure correct recovery of the pipeline state.
4. **Output Behavior**
- `predict_history` (the shift register) is updated only on the rising edge of `history_shift_valid`.
- `history_full` is asserted if predict_history contains all ones (8'hFF) else it will be deasserted.
- `history_empty` is asserted if predict_history contains all zeros (8'h00) else it will be deasserted.
- `interrupt_full` is directly driven by history_full.
- `interrupt_error` is directly driven by error_flag.
Note: Need not to worry about mixing synchronous (pclk) and asynchronous (history_shift_valid) control which can lead to metastability and timing issues. The history_shift_valid will trigger only in absense of pclk.
## Test Bench Requirements
### Stimulus Generation
## 1. **Reset & Initialization Stimuli**
- **Apply and Release Reset**
1. Deassert the active-low reset (`presetn`) after a certain period while the clock toggles, ensuring all internal registers begin at default states.
2. Keep clock transitions valid during reset deassertion.
---
## 2. **APB Interface Stimuli**
### 2.1 **Valid Register Accesses**
- **Write to Control Register**
1. Present the address corresponding to `control_register` on `paddr`.
2. Drive APB signals (`pselx`, `penable`, `pwrite`) for a valid write transaction.
3. Provide varied data patterns on `pwdata` that affect bits `[3:0]` of `control_register`.
- **Write to Train History Register**
1. Present the address corresponding to `train_history` on `paddr`.
2. Drive valid APB write signals.
3. Send multiple data patterns that affect bits `[6:0]`.
- **Read from Control/Register/Train History/Predict History**
1. Present each valid address in turn (`0x0`, `0x1`, `0x2`).
2. Drive APB signals for read transactions.
### 2.2 **Invalid Register Access**
- **Access Addresses Beyond Valid Range**
1. Set `paddr` to a value beyond the defined valid set (greater than `0x2`).
2. Drive an APB read or write cycle.
---
## 3. **Clock Gating Stimuli**
- **Toggle `clk_gate_en`**
1. Drive `clk_gate_en` active and inactive at different moments, including while issuing valid APB transactions.
2. Ensure transitions occur on safe clock edges, demonstrating partial or no internal updates under gating.
---
## 4. **Shift Register Update Stimuli**
### 4.1 **No Update Condition**
- **Drive Control Bits for No-Action**
1. Set `predict_valid` and `train_mispredicted` to inactive states.
2. Pulse the `history_shift_valid` signal.
### 4.2 **Normal Prediction Updates**
- **Drive Valid Prediction**
1. Set `predict_valid` active in `control_register`.
2. Alternate the predicted direction bit (`predict_taken`) across multiple pulses of `history_shift_valid`.
3. Repeat for various patterns of taken/not-taken.
### 4.3 **Misprediction Handling**
- **Restore from Train History**
1. Write desired values into `train_history`.
2. Set `train_mispredicted` active, along with a chosen `train_taken` bit.
3. Drive `history_shift_valid` to force the restore path.
- **Simultaneous Valid Prediction & Misprediction**
1. Set both `predict_valid` and `train_mispredicted` active in the same cycle.
2. Pulse `history_shift_valid`.
---
## 5. **Edge Conditions for the Shift Register**
- **All-Zero to All-One Transitions**
1. Repeatedly provide inputs (via normal prediction or misprediction) so that the shift register transitions from all zeros to all ones.
2. Similarly, drive it back from all ones to all zeros with a series of stimuli.
---
## 6. **Error & Interrupt Stimuli**
- **Trigger Invalid APB Transactions**
1. Provide out-of-range addresses and drive write or read cycles.
- **Generate Interrupt Conditions**
1. Fill the shift register to all ones (to drive any “full” interrupt).
2. Cause invalid address access (to drive error interrupt).
---
## 7. **Combined Complex Sequences**
- **Integrated Flow**
1. Begin with reset cycling.
2. Perform valid reads and writes to internal registers.
3. Toggle `clk_gate_en`.
4. Issue valid predictions and a series of mispredictions.
5. Drive the shift register from empty to full.
6. Include at least one invalid address access mid-sequence.
## 8. **Additional Test Scenarios**
- **Reset During Operation** – Ensures the system can reinitialize correctly when reset is asserted dynamically, not just at startup.
- **Reserved Bit Handling** – Toggles unused register fields to confirm they remain stable and do not interfere with functionality.
- **Expanded Address Access** – Interacts with a broader address range to verify correct handling of both valid and invalid accesses.
- **Repeated Prediction History Reads** – Ensures the stored history updates correctly and all bits are exercised across different states.
- **Response Signal Validation** – Checks readiness and status transitions across reset, transactions, and different operating conditions. | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 98
}
] | APBGlobalHistoryRegister | dut | [
{
"name": "APBGlobalHistoryRegister.v",
"content": "module APBGlobalHistoryRegister (\n // APB clock & reset\n input wire pclk,\n input wire presetn, // Active-low reset\n\n // APB signals\n input wire [9:0] paddr,\n input wire pselx,\n input wire ... | [] |
cvdp_copilot_ring_token_0004 | easy | Non-Agentic | Create a SystemVerilog testbench module named **`tb_token_ring_fsm`** that instantiates the `token_ring_fsm` module as the Unit Under Test (UUT). The testbench must include a **stimulus generator** that systematically drives various input conditions to achieve **100% code and functional coverage** for the `token_ring_fsm`. The `token_ring_fsm` implements a **Finite State Machine (FSM)-based token-passing mechanism** in a four-node ring network, ensuring controlled data transmission between nodes. The stimulus should cover **all state transitions, token passing, data transmission scenarios, and asynchronous reset conditions** while logging outputs for debugging and verification.
---
## **Description**
### **Inputs**
- **Clock Signal**:
- `clk`: Positive edge-triggered clock signal driving the FSM.
- **Reset Signal**:
- `rst`: Asynchronous active-high reset signal that initializes the FSM.
- **Data and Control Inputs**:
- `data_in [3:0]`: A 4-bit input representing binary data for transmission by the current node.
- `has_data_to_send`: A 1-bit signal indicating whether the current node has data to send.
### **Outputs**
- **Data and Token Outputs**:
- `data_out [3:0]`: A 4-bit output representing the data transmitted by the current node.
- `token_received [3:0]`: A 4-bit one-hot encoded signal indicating which node currently holds the token.
- `token [3:0]`: A 4-bit one-hot encoded signal representing the token being passed to the next node.
---
## **Input Generation**
### **State Transitions and Token Passing**
- Drive the FSM through all four states:
- `NODE0 to NODE1 to NODE2 to NODE3 to NODE0` in a cyclic manner.
- Ensure that `token_received` correctly identifies the node holding the token.
- Simulate token passing by shifting the `token` signal across nodes and verifying correct cycling.
### **Data Transmission Stimulus**
- Generate various patterns for `data_in` and toggle `has_data_to_send` to simulate:
- Nodes transmitting data when they hold the token.
- Nodes idling when `has_data_to_send` is LOW.
- Different data values being sent across nodes.
### **Edge Case Testing**
- **Reset Behavior**:
- Apply `rst` at different states to ensure FSM returns to `NODE0`.
- Verify that `token_received` is set to `4'b0001` and `data_out`, `token` are cleared.
- **Token Handling**:
- Simulate idle conditions where no node is ready to send data.
- Inject forced token values using `force` and `release` commands to verify FSM recovery.
- **Overlapping Data Transmission**:
- Test scenarios where multiple nodes attempt to send data consecutively.
- Ensure only the node holding the token transmits data.
---
## **Instantiation**
- The instance of the RTL should be named **`uut`**.
---
## **Module Interface**
### **Inputs**
- `clk`: Clock signal.
- `rst`: Asynchronous active-high reset signal.
- `data_in [3:0]`: Data input for transmission.
- `has_data_to_send`: Indicates whether the node has data to send.
### **Outputs**
- `data_out [3:0]`: Transmitted data output.
- `token_received [3:0]`: Indicates the node currently holding the token.
- `token [3:0]`: Indicates the token being passed to the next node.
---
## **Module Functionality**
1. **Token Passing Mechanism**:
- The FSM cycles through the four nodes, passing the token sequentially.
- The node with the token is allowed to transmit data if `has_data_to_send` is HIGH.
2. **Data Transmission**:
- When a node holds the token and `has_data_to_send` is HIGH, `data_out` reflects `data_in`.
- If no node is ready to send, `data_out` remains `4'b0000`.
3. **Reset Behavior**:
- When `rst` is asserted HIGH, the FSM resets to `NODE0`, `token_received` is set to `4'b0001`, and other outputs are cleared.
4. **Edge Cases**:
- Idle conditions where no node transmits data.
- Forced invalid states and token values to test FSM recovery.
- Multiple data transmissions in consecutive cycles.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 100
}
] | token_ring_fsm | uut | [
{
"name": "token_ring_fsm.sv",
"content": "module token_ring_fsm (\n input logic clk, // Clock input\n input logic rst, // Reset input\n input logic [3:0] data_in, // Data input from node\n output reg [3:0] data_out, // Data output to node\n input logic has_dat... | [] |
cvdp_copilot_morse_code_0027 | easy | Non-Agentic | Complete the given partial SystemVerilog testbench `morse_encoder_tb`. The testbench must instantiate the `morse_encoder` **RTL** module and provide input stimulus for it, focusing exclusively on generating test vectors rather than building a full testbench.
The `morse_encoder` module converts an **8-bit ASCII input** into a **6-bit Morse code output** along with the **length** of the Morse representation.
---
## **Description:**
### **Inputs**:
Registers:
- `ascii_in` (8-bit, `[7:0]`): ASCII character input supplied to the **DUT**.
### **Outputs**:
Registers:
- `morse_out` (6-bit, `[5:0]`): Encoded Morse representation received from the **DUT**.
- `morse_length` (4-bit, `[3:0]`): Length of the Morse code sequence for the given input character.
---
## **Instantiation:**
The testbench instantiates the `morse_encoder` module as **dut** and connects the signals between the module and the testbench.
Each input and output from the **DUT** is connected to its corresponding signal in the testbench.
---
## **Input Generation and Validation:**
### **Stimulus Generation:**
Multiple test cases are applied to verify Morse encoding for different ASCII characters. The output from the **DUT** is monitored using `$display`.
### **Test Cases:**
- **Alphabet (Uppercase)**
- `ascii_in = 8'h41;` // 'A'
- `ascii_in = 8'h42;` // 'B'
- `ascii_in = 8'h43;` // 'C'
- `ascii_in = 8'h44;` // 'D'
- `ascii_in = 8'h45;` // 'E'
- `ascii_in = 8'h46;` // 'F'
- `ascii_in = 8'h47;` // 'G'
- `ascii_in = 8'h48;` // 'H'
- `ascii_in = 8'h49;` // 'I'
- `ascii_in = 8'h4A;` // 'J'
- `ascii_in = 8'h4B;` // 'K'
- `ascii_in = 8'h4C;` // 'L'
- `ascii_in = 8'h4D;` // 'M'
- `ascii_in = 8'h4E;` // 'N'
- `ascii_in = 8'h4F;` // 'O'
- `ascii_in = 8'h50;` // 'P'
- `ascii_in = 8'h51;` // 'Q'
- `ascii_in = 8'h52;` // 'R'
- `ascii_in = 8'h53;` // 'S'
- `ascii_in = 8'h54;` // 'T'
- `ascii_in = 8'h55;` // 'U'
- `ascii_in = 8'h56;` // 'V'
- `ascii_in = 8'h57;` // 'W'
- `ascii_in = 8'h58;` // 'X'
- `ascii_in = 8'h59;` // 'Y'
- `ascii_in = 8'h5A;` // 'Z'
- **Numbers (0-9)**
- `ascii_in = 8'h30;` // '0'
- `ascii_in = 8'h31;` // '1'
- `ascii_in = 8'h32;` // '2'
- `ascii_in = 8'h33;` // '3'
- `ascii_in = 8'h34;` // '4'
- `ascii_in = 8'h35;` // '5'
- `ascii_in = 8'h36;` // '6'
- `ascii_in = 8'h37;` // '7'
- `ascii_in = 8'h38;` // '8'
- `ascii_in = 8'h39;` // '9'
- **Punctuation and Special Characters**
- `ascii_in = 8'h2E;` // '.'
- `ascii_in = 8'h2C;` // ','
- `ascii_in = 8'h3F;` // '?'
- `ascii_in = 8'h27;` // "'"
- `ascii_in = 8'h21;` // '!'
- `ascii_in = 8'h2F;` // '/'
- `ascii_in = 8'h28;` // '('
- `ascii_in = 8'h29;` // ')'
- `ascii_in = 8'h26;` // '&'
- `ascii_in = 8'h3A;` // ':'
- `ascii_in = 8'h3B;` // ';'
- `ascii_in = 8'h3D;` // '='
- `ascii_in = 8'h2B;` // '+'
- `ascii_in = 8'h2D;` // '-'
- `ascii_in = 8'h22;` // '"'
- `ascii_in = 8'h40;` // '@'
- **Edge Cases and Invalid Inputs**
- `ascii_in = 8'h00;` // NULL
- `ascii_in = 8'hFF;` // Maximum 8-bit value
- `ascii_in = 8'h7B;` // '{'
- `ascii_in = 8'h7F;` // DEL
- `ascii_in = 8'h5D;` // ']'
- `ascii_in = 8'h5B;` // '['
- `ascii_in = 8'h7A;` // 'z' (Lowercase)
- `ascii_in = 8'h7C;` // '|'
---
## **Reset Handling:**
At the beginning of the test, an **initial condition** is set to ensure the **DUT** starts in a known state. The testbench then applies each test case sequentially.
---
```verilog
module morse_encoder_tb;
reg [7:0] ascii_in;
wire [5:0] morse_out;
wire [3:0] morse_length;
morse_encoder dut (
.ascii_in(ascii_in),
.morse_out(morse_out),
.morse_length(morse_length)
);
initial begin
$display("Starting Testbench...");
// Insert code here for Test bench
endmodule
``` | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 95
}
] | morse_encoder | dut | [
{
"name": "morse_encoder.sv",
"content": "module morse_encoder (\n input wire [7:0] ascii_in, // ASCII input character\n output reg [5:0] morse_out, // Morse code output \n output reg [3:0] morse_length // Length of the Morse code sequence\n);\n\n always @(*) begin\n case (a... | [] |
cvdp_copilot_restoring_division_0006 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module generates the output `quotient`, `remainder`, and `valid` once the computation is completed for the given `dividend` and `divisor` when the `start` signal is asserted.
## **Design Details**
### **Parameterization**
- **WIDTH**: Specifies the bit-width of the dividend and divisor.
- **Default**: 6 bits
### **Functionality**
The **restoring_division** module implements division using a shift-subtract approach:
- The division process must finish within WIDTH clock cycles if WIDTH is a power of 2 (2^n) to ensure all data is processed; otherwise (if WIDTH is not a power of 2), it will take WIDTH+1 clock cycles.
- The FSM governs the state transitions and ensures proper computation.
- The division process begins when `start` is asserted and completes when `valid` is high.
## **Signal Behavior**
### Inputs:
- **`clk`**: 1-bit clock signal, toggles every 5 time units.
- **`rst`**: Active-low reset signal to initialize the module.
- **`start`**: Start signal to begin the division process.
- **`dividend`**: `WIDTH`-bit input representing the dividend.
- **`divisor`**: `WIDTH`-bit input representing the divisor.
### Outputs:
- **`quotient`**: `WIDTH`-bit result of the division operation.
- **`remainder`**: `WIDTH`-bit remainder of the division operation.
- **`valid`**: 1-bit signal indicating completion of division.
---
## **Testbench Requirements**
### **Instantiation**
- **Module Instance**: The **restoring_division** module should be instantiated as `uut`, with all inputs and outputs properly connected.
### **Input Generation and Validation**
1. **Clock Generation**:
- The testbench must generate a clock signal with a 10 ns period.
- The clock should toggle every **5 time units**.
2. **Reset Behavior**:
- The reset signal should be asserted low initially.
- After 10 ns, reset should be de-asserted (set high) to allow normal operation.
3. **Division Test Cases**:
- A **task** named `run_test` should be used to apply test cases dynamically.
- The testbench should generate **random** values for `dividend` and `divisor`.
- The **divisor should never be zero** (handled by ensuring divisor ≥ 1).
- The division process should be started by asserting `start` high for one cycle.
- The testbench must **wait for `valid`** to be asserted before capturing the results.
- The computed **quotient and remainder** should be displayed for debugging.
--- | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\n\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start signal to b... | [] |
cvdp_copilot_restoring_division_0034 | easy | Non-Agentic | Write a testbench to generate stimulus only for the `restoring_division` module, which performs restoring division on two unsigned positive integer inputs. The module produces the `quotient`, `remainder`, and asserts the `valid` signal upon computation completion. Additionally, it sets the `divisor_valid_result` flag to indicate whether the divisor was valid (nonzero) when the `start` signal is asserted with the `dividend` and `divisor` inputs.
---
## **Design Details**
### **Parameterization**
- **WIDTH**: Specifies the bit-width of the dividend and divisor.
- **Default**: 6
### **Functionality**
The **restoring_division** module performs unsigned integer division using a sequential **restoring division algorithm**. The quotient and remainder are computed iteratively over multiple clock cycles.
#### **Division Process and Output Behavior**
- The computation is **iterative** and progresses bit-by-bit over **WIDTH** clock cycles.
- The division process must finish within WIDTH clock cycles if WIDTH is a power of 2 (2^n) to ensuring all data is processed; otherwise (if WIDTH is not a power of 2), it will take WIDTH+1 clock cycles.
- Once the computation is complete, the **valid** signal is asserted high to indicate that the **quotient** and **remainder** outputs are stable and valid.
- The **divisor_valid_result** signal ensures that valid results are only produced when the divisor is nonzero.
### **Inputs:**
- `clk` (1-bit): Clock signal, toggles every 5 time units (**100MHz operation**).
- `rst` (1-bit): **Active-low** reset signal to initialize the module.
- `start` (1-bit): Start signal to begin the division process.
- `dividend` (6-bit): Dividend input value.
- `divisor` (6-bit): Divisor input value.
### **Outputs:**
- `quotient` (6-bit): Computed quotient output.
- `remainder` (6-bit): Computed remainder output.
- `valid` (1-bit): Signal indicating division completion.
- `divisor_valid_result` (1-bit): Signal indicating if divisor was valid (not zero).
---
## **Testbench Requirements**
### **Instantiation**
- The **restoring_division** module should be instantiated as **uut** (Unit Under Test), with all input and output signals connected.
### **Input Generation and Validation**
- **Randomized Inputs**: The testbench must generate multiple test cases, covering:
- **Random dividend & random nonzero divisor**
- **Dividend = 0** (Edge case)
- **Divisor = 0** (Edge case, division by zero)
- **Dividend < Divisor** (Ensuring the quotient is 0 and remainder = dividend)
- **Stabilization Period**: After applying inputs, the testbench must wait until the **valid** signal is asserted before checking outputs.
### **Control Signal Behavior**
- The **start** signal should be asserted high for **one clock cycle** before being de-asserted.
- The testbench must ensure that **valid** is asserted only after the computation is complete.
---
This testbench will verify the **correctness, stability, and edge-case behavior** of the **restoring_division** module. It ensures that the division process adheres to the restoring division algorithm and produces accurate results across all test scenarios. | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 95
}
] | restoring_division | uut | [
{
"name": "restore_division.sv",
"content": "`timescale 1ns / 1ps\nmodule restoring_division #(parameter WIDTH = 6) (\n input clk, // Clock signal\n input rst, // Reset signal (active low)\n input start, // Start s... | [] |
cvdp_copilot_microcode_sequencer_0028 | medium | Non-Agentic | Complete the given partial System Verilog Testbench `tb_microcode_sequencer`.The testbench must instantiate the `microcode_sequencer` RTL module and provide input stimulus for it, apply various input combinations representing different instructions and conditions such as resetting, fetching instructions, loading data, pushing/popping from the stack, jumping, conditional holds, and program suspensions and edge cases with invalid instructions and test conditional failures rather than building a full testbench.
The module interface is given below :
## **Module Interface** :
### Inputs:
- `clk`(1-bit): The positive edge-triggered clock signal required for the sequential components.
- `c_n_in`(1-bit): Carry-in signal for the ripple carry adder.
- `c_inc_in`(1-bit): Carry-in for the program counter incrementer.
- `r_en`(1-bit): ACTIVE LOW auxiliary register enable signal.
- `cc`(1-bit): ACTIVE LOW condition code input for instruction decoding.
- `ien`(1-bit): ACTIVE LOW instruction enable signal.
- `d_in`(4-bit , [3:0]): A 4-bit data input bus.
- `instr_in`(5-bit, [4:0]): A 5-bit opcode representing the instruction.
- `oen`(1-bit): ACTIVE LOW output enable for the data output path.
### Outputs:
- `d_out`(4-bit,[3:0]): A 4-bit address output bus.
- `c_n_out`(1-bit): Carry-out signal from the ripple carry adder. LOGIC HIGH in this signal indicates the presence of carry.
- `c_inc_out`(1-bit): Carry-out signal from the program counter incremented. LOGIC HIGH in this signal indicates the presence of carry.
- `full`(1-bit): ACTIVE HIGH signal indicates if the Last In First Out (LIFO) stack is full.
- `empty`(1-bit): ACTIVE HIGH signal indicates if the LIFO stack is empty.
- `g_n_out`: Group generate signal from the arithmetic unit.
- `p_n_out`: Group propagate signal from the arithmetic unit.
- `g_inc_out`: Group generate signal from the program counter incrementer.
- `p_inc_out`: Group propagate signal from the program counter incrementer.
## Instantiation :
The testbench instantiates the `microcode_sequencer` module as **uut** and connects the signals between the module and the testbench. Each input and output from the **uut** is connected to its corresponding signal in the testbench.
## Input Generation and Validation:
**Stimulus**:
Several test cases are applied to simulate various operations of the microcode_sequencer. These test cases cover a wide range of scenarios such as different types of instructions (reset, fetch, load, push, pop, jump, etc.), as well as conditional and unconditional instruction executions. For each test case, the relevant outputs (`d_out`, `c_n_out`, `c_inc_out`, `full`, `empty`, `g_n_out`, `p_n_out`, `g_inc_out`, `p_inc_out`) are monitored immediately after the application of inputs to validate the functionality.
**Test Case 1: Instruction Disable** :
- Description: This test case disables the instruction input (`5'bxxxxx`). With no valid instruction provided, the microcode sequencer should remain idle and output default values, reflecting no operation being performed. The outputs should show that the sequencer is in a non-operational state with the `uut.pc_out_w` value remaining at 0000.
**Test Case 2: Reset Instruction** :
- The test applies a reset instruction (`5'b00000`), which should clear all registers and reset the state of the sequencer. The outputs should reflect the sequencer being reset, with `d_out`, `c_n_out`, `c_inc_out`, and `uut.pc_out_w` values showing their initial conditions (`0000` for `d_out`, `0000` for `uut.pc_out_w`, and `full` set to `0`, `empty` set to `1`).
**Test Case 3: Fetch PC Instruction** :
- This test case applies a fetch PC instruction (`5'b00001`), where the program counter (PC) is fetched. The sequencer should output the program counter incremented by 1. In this case, the expected output for uut.pc_out_w is `0001`, with `d_out` reflecting the fetched value.
**Test Case 4: Fetch R Instruction** :
- The sequencer applies a fetch R instruction (`5'b00010`), which fetches the value from register R. The expected outcome is that the value in `d_out` should be the value of register R (`101` in this case) with `uut.pc_out_w` incrementing accordingly (`0010`).
**Test Case 5: Fetch D Instruction** :
- This test case applies a fetch D instruction (`5'b00011`). The sequencer fetches the value from the D input(`d_in`), with `d_out` reflecting the value of D (`110`) and `uut.pc_out_w` incrementing as expected (`0011`).
**Test Case 6: Fetch R + D Instruction** :
- A fetch R + D instruction (`5'b00100`) is applied, where the sequencer fetches and combines data from both the auxiliary register and `d_in`. The expected result is `d_out` showing the combined data (111), and `uut.pc_out_w` reflecting the expected increment (`0100`).
**Test Case 7: Fetch PC + D Instruction** :
- This test case applies a fetch PC + D instruction (`5'b00101`), which combines the values of the program counter (PC) and the `d_in`. The d_out value should reflect the combination (`1100`), and `uut.pc_out` should increment to `0101`.
**Test Case 8: Fetch PC + R Instruction** :
- The test applies a fetch PC + R instruction (`5'b00110`), where the sequencer fetches both the program counter (PC) and the Auxiliary register. The expected output for `d_out` should be a combination of the content of the PC and auxiliary register (`1101`), and `pc_out `increments accordingly to `0110`.
**Test Case 9: Fetch PC to R Instruction** :
- A fetch PC to R instruction (`5'b01000`) is applied, where the program counter (`PC`) is transferred to the auxiliary register. The expected output should show `d_out` reflecting the PC value (`111`), and `pc_out` incrementing as expected (`0111`).
**Test Case 10: Fetch R+D to R Instruction** :
- This case applies a fetch R + D to R instruction (`5'b01001`), where the data from both the auxiliary register and `d_in` are fetched, added, and transferred to the auxiliary register. The expected output should reflect this combination (`11` for `d_out`), and the program counter should increment (`1000` for `uut.pc_out_w`).
**Test Case 11: Load R Instruction** :
- A load R instruction (`5'b01010`) is applied, where data from an`d_in` is loaded into the auxiliary register. The output should reflect the `uut.pc_out_w` value (`1001` for `d_out`), and the program counter (`uut.pc_out_w`) should be incremented accordingly (`1001`).
**Test Case 12: Push PC Instruction** :
- A push PC instruction (`5'b01011`) is tested, where the program counter (`PC`) is pushed onto the stack. The output shows the updated stack (`d_out` as `1010`) and empty flag reflecting the stack status (`0`).
**Test Case 13: Pop PC Instruction** :
- A pop PC instruction (`5'b01110`) is applied, where the program counter (PC) is popped from the stack. The expected output shows the popped value (`1011`) in d_out and the updated program counter (`uut.pc_out_w` as `1101`).
**Test Case 14: Push D Instruction** :
- A push D instruction (`5'b01100`) is tested, where data from the `d_in` is pushed onto the stack. The expected output is that `d_out` reflects the pushed value and 1uut.pc_out_w1 should increment appropriately.
**Test Case 15: Pop Stack Instruction** :
- A pop stack instruction (`5'b01101`) tests the sequencer's ability to pop data from the stack. The expected outputs should show the data being popped correctly (`d_out` reflects the popped value) and the stack's status with empty being checked.
**Test Case 16: HOLD** :
- A hold instruction (`5'b01111`) is applied to check that the sequencer halts its operation. The expected behavior is that the sequencer should not move to the next instruction and `uut.pc_out_w` stays in the current state.
**Test Case 17: Fail Conditional Instruction** :
- This test applies an invalid instruction (`5'b1xxxx`) with conditional failure (`cc` = `1`). The sequencer should fail to process the instruction and output appropriate values (`d_out` reflecting updated `uut.pc_out_w` value).
**Test Case 18: Jump R Instruction** :
- A jump R instruction (`5'b10000`) is applied, where the sequencer performs a jump using the auxiliary register value. The expected output shows a jump action with `d_out` reflecting the jump address.
**Test Case 19: Jump D Instruction** :
- A jump D instruction (`5'b10001`) tests the sequencer’s ability to jump based on the `d_in` value. The expected outcome is that `d_out` reflects the jump address based on the value of `d_in`.
**Test Case 20: Jump 0 Instruction** :
- A jump 0 instruction (`5'b10010`) applies a jump to address `0`. The output should reflect this jump, with `uut.pc_out_w` updated to `0000`.
**Test Case 21: Jump R+D Instruction** :
- A jump R+D instruction (`5'b10011`) applies a jump based on the sum of the auxiliary register and `d_in`. The expected output should reflect the sum.
**Test Case 22: Jump PC+D Instruction** :
- A jump PC+D instruction (`5'b10100`) applies a jump based on the sum of PC and `d_in`. The expected behavior is that `d_out `reflects the result of PC and `d_in` combined.
**Test Case 23: Jump PC+R Instruction** :
- A jump PC+R instruction (`5'b10101`) applies a jump based on the sum of PC and auxiliary register. The expected output should reflect this combination in `d_out`.
**Test Case 24: JSB R Instruction** :
- A JSB R instruction (`5'b10110`) applies a jump to a subroutine based on the auxiliary register. The output should show the subroutine jump address in `d_out`.
**Test Case 25: JSB D Instruction** :
- A JSB D instruction (`5'b10111`) applies a jump to the subroutine address based on the `d_in`. The sequencer should handle the jump correctly by appropriately updating `d_out`.
**Test Case 26: JSB 0 Instruction** :
- A JSB 0 instruction (`5'b11000`) applies a jump to a subroutine at address 0. The expected output should reflect the jump to address 0.
**Test Case 27: JSB R+D Instruction** :
- A JSB R+D instruction (5'b11001) applies a jump to the subroutine address based on the sum of the auxiliary register and `d_in`. The sequencer should perform the jump correctly.
**Test Case 28: JSB PC+D Instruction** :
- A JSB PC+D instruction (`5'b11010`) applies a jump to the subroutine address based on the sum of PC and `d_in`. The expected outcome should reflect the subroutine jump at `d_out`.
**Test Case 29: Fetch S+D Instruction** :
- This test applies a fetch S+D instruction (`5'b00111`), where the sequencer fetches and adds values of popped stack value (S) with `d_in`. The expected output should reflect the appropriate address at `d_out`.
**Test Case 30: Return S Instruction** :
- The return S instruction (`5'b11100`) tests the sequencer’s ability to return from a subroutine. The expected outcome should show the return address at `d_out`.
**Test Case 31: Return S+D Instruction** :
- The return S+D instruction (`5'b11101`) checks the sequencer’s ability to return from a subroutine with the sum of popped value from the stack and `d_in`. The expected output should be reflected at `d_out`.
**Test Case 32: Conditional Hold** :
- The conditional hold instruction (`5'b11110`) tests the sequencer’s ability to hold execution based on a condition. The expected outcome should show that the sequencer halts.
**Test Case 33: Program Suspend** :
- The program suspend instruction (`5'b11111`) checks the sequencer’s ability to suspend its program flow. The expected behavior is that the sequencer stops and no further instructions are executed.
## Module Functionality :
**Microcode Sequencer Module (microcode_sequencer)** :
Purpose: This module controls the operation of a microprocessor by sequencing operations based on the instructions it receives. It interacts with other modules (like stack, program counter, arithmetic operations, and instruction decoder) to control the flow of data.
It contains the following components :
**LIFO Stack Module (lifo_stack)** :
**Purpose**: Implements a stack with push and pop functionality, allowing data to be stored and retrieved in a last-in-first-out
order.
**Components**:
- **Stack Pointer**: Tracks the current position in the stack and controls whether the stack is full or empty.
- **Stack RAM**: Stores the actual stack data.
- **Stack Data Mux**: Selects which data (either from the program counter or data input) should be pushed onto the stack.
**Program Counter Module (program_counter)** :
**Purpose**: Handles the program counter (PC), which keeps track of the next instruction to execute. It can increment
based on different conditions.
**Components**:
- **PC Mux**: Selects the input for the program counter (either from the adder or program counter).
- **PC Incrementer**: Performs the actual increment of the program counter based on carry and increment signals.
- **PC Register**: Stores the current value of the program counter.
**Instruction Decoder (instruction_decoder)** :
**Purpose**: Decodes the incoming instruction (instr_in) and generates control signals for various operations like
increment, push, pop, stack operations, etc.
**Microcode Arithmetic Module (microcode_arithmetic)**
**Purpose**: Performs arithmetic operations like addition using a carry lookahead adder. It uses data from various inputs
(program counter, stack, data input) and processes it based on the instruction.
**Components**:
**Auxiliary Register**: Stores data that can be modified based on the control signals (rsel, rce).
**MUXes**: Control the selection of data from different sources (registers, stack, program counter) to be used in arithmetic
operations.
**Full Adder**: Performs the actual arithmetic operations and generates the result, carry, group, generate, and propagate
signals. It is implemented using 4-bit carry-lookahead logic.
**Partial Test Stimulus Generator Code** :
```verilog
module tb_microcode_sequencer;
// Inputs to the DUT
logic clk;
logic c_n_in;
logic c_inc_in;
logic r_en;
logic cc;
logic ien;
logic [3:0] d_in;
logic [4:0] instr_in;
logic oen;
// Outputs from the DUT
logic [3:0] d_out;
logic c_n_out;
logic c_inc_out;
logic full;
logic empty;
logic g_n_out;
logic p_n_out;
logic g_inc_out;
logic p_inc_out;
microcode_sequencer uut (
.clk(clk),
.c_n_in(c_n_in),
.c_inc_in(c_inc_in),
.r_en(r_en),
.cc(cc),
.ien(ien),
.d_in(d_in),
.instr_in(instr_in),
.oen(oen),
.d_out(d_out),
.c_n_out(c_n_out),
.c_inc_out(c_inc_out),
.full(full),
.empty(empty),
.g_n_out(g_n_out),
.p_n_out(p_n_out),
.g_inc_out(g_inc_out),
.p_inc_out(p_inc_out)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Task to test specific cases
task run_test_case(
input logic [4:0] test_instr, // Instruction input
input logic test_carry_in, // Carry input
input logic test_carry_inc, // Carry increment input
input logic test_reg_en, // Register enable
input logic test_cond_code, // Condition code
input logic test_instr_en, // Instruction enable
input logic [3:0] test_data_in, // Data input
input logic test_output_en, // Output enable
input string case_name // Name of the test case
);
begin
// Apply inputs
instr_in = test_instr;
c_n_in = test_carry_in;
c_inc_in = test_carry_inc;
r_en = test_reg_en;
cc = test_cond_code;
ien = test_instr_en;
d_in = test_data_in;
oen = test_output_en;
#20;
$display("Running test case: %s", case_name);
$display("time = %0t , Inputs: instr_in = %0b, c_n_in = %b, c_inc_in = %b, r_en = %b, cc = %b, ien = %b, d_in = %0b, oen = %b",
$time,test_instr, test_carry_in, test_carry_inc, test_reg_en, test_cond_code, test_instr_en, test_data_in, test_output_en);
$display("time = %0t , d_out = %0b, c_n_out = %b, c_inc_out = %b, full = %b, empty = %b, g_n_out = %b, p_n_out = %b, g_inc_out = %b, p_inc_out = %b , pc_out = %b",
$time,d_out, c_n_out, c_inc_out, full, empty, g_n_out, p_n_out, g_inc_out, p_inc_out,uut.pc_data_w);
end
endtask
initial begin
$dumpfile("microcode_sequencer.vcd");
$dumpvars(0, tb_microcode_sequencer);
$display("Starting testbench for microcode_sequencer...");
run_test_case(5'bxxxxx, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 4'bxxxx, 1'b0, "Instruction Disable");
run_test_case(5'b00000, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 4'bxxxx, 1'b0, "Reset Instruction");
run_test_case(5'b00001, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'bxxxx, 1'b0, "Fetch PC Instruction");
run_test_case(5'b00010, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0101, 1'b0, "Fetch R Instruction");
run_test_case(5'b00010, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0110, 1'b0, "Fetch R Instruction");
run_test_case(5'b00011, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0110, 1'b0, "Fetch D Instruction");
run_test_case(5'b00011, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 4'b0110, 1'b0, "Fetch D Instruction");
run_test_case(5'b00011, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 4'b0111, 1'b0, "Fetch D Instruction");
// Insert the code for remaining test cases here
``` | [
{
"inst_name": "uut",
"metric": "Overall Average",
"target_percentage": 90
}
] | microcode_sequencer | uut | [
{
"name": "microcode_sequencer.sv",
"content": "module microcode_sequencer (\n // Inputs\n input logic clk, // Input Clock\n input logic c_n_in, // Input Carry for Carry Lookahead Adder\n input logic c_inc_in, // Input Carry for Carry Lookahead Program Counter Incrementer\n input logic r_en, // A... | [] |
cvdp_agentic_async_fifo_compute_ram_application_0004 | medium | Agentic | Create a test bench in SystemVerilog for a Verilog module named `async_fifo`. The **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory and Gray-coded pointers for reliable synchronization. The test bench should systematically generate input vectors, apply them to the module under test (MUT) and aim to achieve 100% or the maximum possible coverage.
# Stimulus Generation
Below are all test cases designed to maximize coverage of the `async_fifo` module.
**Setup:**
- `p_data_width = 8`
- `p_addr_width = 4`
- Write clk = 10 ns, Read clk = 12 ns
---
## Test Case 1: Basic Write-Read
**Description:**
Write a sequence of data and read it back with asynchronous clocks.
**Sequence:**
1. Deassert resets.
2. Write 8 sequential values.
3. Read back all values.
---
## Test Case 2: Fill-and-Drain (Full/Empty Flag Test)
**Description:**
Completely fill and then completely drain the FIFO.
**Sequence:**
1. Write 16 items to FIFO.
2. Observe `o_fifo_full = 1`.
3. Read all data.
4. Observe `o_fifo_empty = 1`.
---
## Test Case 3: Pointer Wrap-Around
**Description:**
Test pointer wrap-around logic at FIFO depth boundaries.
**Sequence:**
1. Continuously write 20 items.
2. Slowly read back data.
---
## Test Case 4: Write Domain Reset
**Description:**
Test behavior when only the write side is reset.
**Sequence:**
1. Write till Fifo is full.
2. Reset `i_wr_rst_n`.
3. Read Back.
---
## Test Case 5: Read Domain Reset
**Description:**
Test behavior when only the read side is reset.
**Sequence:**
1. Continuously write data.
2. Reset `i_rd_rst_n`.
3. Read Back.
---
## Test Case 6: Simultaneous Reset
**Description:**
Reset both domains simultaneously.
**Sequence:**
1. Write and read some data.
2. Assert both resets.
3. Resume operation.
--- | [
{
"inst_name": "dut",
"metric": "Overall Average",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Assertion",
"target_percentage": 100
},
{
"inst_name": "dut",
"metric": "Toggle",
"target_percentage": 90
},
{
"inst_name": "dut",
"metric": "Block",... | async_fifo | dut | [
{
"name": "async_fifo.sv",
"content": "module async_fifo\n #(\n parameter p_data_width = 32, // Parameter to define the width of the data\n parameter p_addr_width = 16 // Parameter to define the width of the address\n )(\n input wire i_wr_clk, // Write ... | [
{
"name": "fifo.md",
"content": "# Asynchronous FIFO Specification\n\n## 1. Overview\n\nThe **async_fifo** design is a parameterizable asynchronous FIFO module. It uses separate clock domains for writing and reading, providing safe data transfer between two clock domains. The design employs dual-port memory... |
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