commit_hash stringlengths 40 40 | author stringlengths 1 57 | date timestamp[s]date 2010-07-26 04:45:09 2026-04-14 18:21:10 | message stringlengths 8 1.39M | diff stringlengths 68 51.2k | files_changed int64 1 136 | insertions int64 0 2.35k | deletions int64 0 1.9k |
|---|---|---|---|---|---|---|---|
f905dc914b321d2bce979724d177c5653431f1bf | Dan Gohman | 2017-08-29T00:07:28 | Enable missing_docs errors in the wasm crate.
This adds `#![deny(missing_docs)]` to the wasm crate, and adds documentation
to several struct and enum fields, as needed. | diff --git a/lib/wasm/src/lib.rs b/lib/wasm/src/lib.rs
index 5006e5c9a..bb342bf7c 100644
--- a/lib/wasm/src/lib.rs
+++ b/lib/wasm/src/lib.rs
@@ -10,6 +10,8 @@
//!
//! The main function of this module is [`translate_module`](fn.translate_module.html).
+#![deny(missing_docs)]
+
extern crate wasmparser;
extern crate... | 3 | 26 | 6 |
6d9198d55f84c7bf265af826a9fb94c0af47486e | Jakob Stoklund Olesen | 2017-08-28T18:13:53 | Recompute the dominator tree on demand.
The legalizer can invalidate the dominator tree, but we don't actually
need a dominator tree during legalization, so defer the construction of
the domtree.
- Add an "invalid" state to the dominator tree along with clear() and
is_valid() methods to test it.
- Invalidate the do... | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index 7fec7ea0f..6f80f1605 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -63,7 +63,7 @@ impl Context {
///
/// Returns the size of the function's code.
pub fn compile(&mut self, isa: &TargetIsa) -> Resu... | 3 | 34 | 5 |
fecbcbb7b48e72da9034b1d1906482a080f4fabe | Jakob Stoklund Olesen | 2017-08-25T17:36:25 | Drop the domtree argument to legalize_function().
Future legalization patterns will have the ability to mutate the
flowgraph, so the domtree's list of RPO blocks is not a good guide for
iteration. Use the layout order instead. This will pick up any new EBBs
inserted. | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index 9967f1e11..7fec7ea0f 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -103,7 +103,7 @@ impl Context {
/// Run the legalizer for `isa` on the function.
pub fn legalize(&mut self, isa: &TargetIsa) -> Cton... | 2 | 5 | 11 |
a9238eda7a3e03c95994f63df6efe85e6e38f90c | Jakob Stoklund Olesen | 2017-08-19T00:14:31 | Clean up the documentation for the entity module. | diff --git a/lib/cretonne/src/entity/list.rs b/lib/cretonne/src/entity/list.rs
index 3685f00ea..e70909bf6 100644
--- a/lib/cretonne/src/entity/list.rs
+++ b/lib/cretonne/src/entity/list.rs
@@ -1,51 +1,4 @@
//! Small lists of entity references.
-//!
-//! This module defines an `EntityList<T>` type which provides simila... | 5 | 113 | 95 |
9cb0529be4e221369e2250034d7680ba5c72a4a4 | Jakob Stoklund Olesen | 2017-08-18T23:09:13 | Move EntityList and SparseMap into the entity module.
These data structures are dependent on EntityRef and EntityMap, so it
makes sense to keep them in the same module. | diff --git a/lib/cretonne/src/entity_list.rs b/lib/cretonne/src/entity/list.rs
similarity index 100%
rename from lib/cretonne/src/entity_list.rs
rename to lib/cretonne/src/entity/list.rs
diff --git a/lib/cretonne/src/entity/mod.rs b/lib/cretonne/src/entity/mod.rs
index 58f900abc..9a9cc5d72 100644
--- a/lib/cretonne/src... | 14 | 17 | 15 |
7e08b14cf6d967502fa923773a269cfd88568540 | Jakob Stoklund Olesen | 2017-08-18T22:04:10 | Split EntityMap into entity::PrimaryMap and entity::EntityMap.
The new PrimaryMap replaces the primary EntityMap and the PrimaryEntityData
marker trait which was causing some confusion. We now have a clear
division between the two types of maps:
- PrimaryMap is used to assign entity numbers to the primary data for an... | diff --git a/cranelift/src/filetest/binemit.rs b/cranelift/src/filetest/binemit.rs
index 09a6955b5..af6e72f21 100644
--- a/cranelift/src/filetest/binemit.rs
+++ b/cranelift/src/filetest/binemit.rs
@@ -107,11 +107,11 @@ impl SubTest for TestBinEmit {
// Give an encoding to any instruction that doesn't already h... | 30 | 413 | 363 |
859937209854ec1332dca68c66a1775d8f7402a5 | Jakob Stoklund Olesen | 2017-08-18T21:37:03 | Rename the entity_ref module to 'entity'.
This is in preparation for moving a number of data structures into
sub-modules of the 'entity' module:
- EntityList
- EntityMap
- SparseMap | diff --git a/lib/cretonne/src/entity_ref.rs b/lib/cretonne/src/entity/mod.rs
similarity index 91%
rename from lib/cretonne/src/entity_ref.rs
rename to lib/cretonne/src/entity/mod.rs
index 9990b521f..26c1e5435 100644
--- a/lib/cretonne/src/entity_ref.rs
+++ b/lib/cretonne/src/entity/mod.rs
@@ -2,6 +2,8 @@
//!
//! This... | 16 | 23 | 21 |
8546cabc8fa9c900695e870547b6c565e4557c8c | Denis Merigoux | 2017-08-08T20:43:20 | Verifier now checks it branch target ebbs are inserted in the layout | diff --git a/lib/cretonne/src/verifier/mod.rs b/lib/cretonne/src/verifier/mod.rs
index d3f05ef4c..be9545621 100644
--- a/lib/cretonne/src/verifier/mod.rs
+++ b/lib/cretonne/src/verifier/mod.rs
@@ -297,7 +297,7 @@ impl<'a> Verifier<'a> {
}
fn verify_ebb(&self, inst: Inst, e: Ebb) -> Result {
- if !sel... | 1 | 1 | 1 |
051bc08d23df0930be5e959645c50dd0cdf411d4 | Denis Merigoux | 2017-08-11T22:49:47 | Added description and license to Cargo.toml | diff --git a/lib/wasm2cretonne-util/Cargo.toml b/lib/wasm2cretonne-util/Cargo.toml
index a4f3eb94a..f709e4afa 100644
--- a/lib/wasm2cretonne-util/Cargo.toml
+++ b/lib/wasm2cretonne-util/Cargo.toml
@@ -3,6 +3,9 @@ name = "wasm2cretonne-util"
version = "0.0.0"
authors = ["The Cretonne Project Developers"]
publish = fa... | 3 | 9 | 0 |
727f297ba99473904d8817b8a5e64fe46a5e0c44 | Denis Merigoux | 2017-08-11T20:38:56 | Bugfix: wrong jump arguments for br_if to loops | diff --git a/lib/wasm2cretonne/src/code_translator.rs b/lib/wasm2cretonne/src/code_translator.rs
index 090d2bbbb..b1647a9ae 100644
--- a/lib/wasm2cretonne/src/code_translator.rs
+++ b/lib/wasm2cretonne/src/code_translator.rs
@@ -499,8 +499,12 @@ fn translate_operator(op: &Operator,
let val = stack.pop().un... | 1 | 15 | 5 |
ffae39377c83f2c8bd26cdcbabce6ec75c9d6ac6 | Jakob Stoklund Olesen | 2017-08-04T23:00:48 | Switch branch relaxation to a FuncCursor. | diff --git a/lib/cretonne/src/binemit/relaxation.rs b/lib/cretonne/src/binemit/relaxation.rs
index 0d0c07df3..e49b53462 100644
--- a/lib/cretonne/src/binemit/relaxation.rs
+++ b/lib/cretonne/src/binemit/relaxation.rs
@@ -28,7 +28,8 @@
//! ```
use binemit::CodeOffset;
-use ir::{Function, DataFlowGraph, Cursor, Curso... | 1 | 19 | 25 |
92c3d8f87b13108e014deb6d56a01babc9056a00 | Jakob Stoklund Olesen | 2017-08-04T22:31:08 | Add a FuncCursor type to the cursor library.
A FuncCursor works a like a layout cursor, but it holds a reference to
the entire function and lets you re-borrow the function reference.
Rewrite the dominator tree unit tests with a FuncCursor instead of a
layout cursor to demonstrate the difference. It avoids the constra... | diff --git a/lib/cretonne/src/cursor.rs b/lib/cretonne/src/cursor.rs
index b706531ee..3719aa1d3 100644
--- a/lib/cretonne/src/cursor.rs
+++ b/lib/cretonne/src/cursor.rs
@@ -10,6 +10,67 @@ pub use ir::layout::CursorBase as Cursor;
pub use ir::layout::CursorPosition;
pub use ir::layout::Cursor as LayoutCursor;
+/// F... | 2 | 167 | 134 |
e904bff420c5577899e0678ce2d8ece60915f9ee | Jakob Stoklund Olesen | 2017-08-04T22:02:46 | Use EncCursor for reload.rs.
Same deal as for spilling. Place an EncCursor in the context and use
that to reference into the IR function when necessary. | diff --git a/lib/cretonne/src/ir/layout.rs b/lib/cretonne/src/ir/layout.rs
index b219a13bb..3f31d34f2 100644
--- a/lib/cretonne/src/ir/layout.rs
+++ b/lib/cretonne/src/ir/layout.rs
@@ -709,8 +709,7 @@ pub trait CursorBase {
fn at_first_inst(mut self, ebb: Ebb) -> Self
where Self: Sized
{
- let... | 2 | 99 | 134 |
f15abe715401da187d9103ea05834a2d03fb0649 | Jakob Stoklund Olesen | 2017-08-04T21:13:56 | Use EncCursor in regalloc/spilling.rs
Use an EncCursor instead of a layout cursor to keep track of the
current position in the function. Since the EncCursor holds a reference
to the whole IR function insteadof just the layout, we can rework how IR
borrowing works.
The Context data structure that's live during the spi... | diff --git a/lib/cretonne/src/regalloc/spilling.rs b/lib/cretonne/src/regalloc/spilling.rs
index e1e610c3f..12a938c81 100644
--- a/lib/cretonne/src/regalloc/spilling.rs
+++ b/lib/cretonne/src/regalloc/spilling.rs
@@ -15,10 +15,9 @@
//! be compatible. Otherwise, the value must be copied into a new register for some ... | 1 | 81 | 113 |
87cee86acbf8e6e496d67595e780911256774e01 | Jakob Stoklund Olesen | 2017-08-04T04:08:36 | Cursor library.
Add a new cursor module and define an EncCursor data type in it. An
EncCursor is a cursor that inserts instructions with a valid encoding
for the ISA. This is useful for passes generating code after
legalization.
Implement a builder interface via the new InstInserterBase trait such
that the EncCursor ... | diff --git a/lib/cretonne/src/cursor.rs b/lib/cretonne/src/cursor.rs
new file mode 100644
index 000000000..b706531ee
--- /dev/null
+++ b/lib/cretonne/src/cursor.rs
@@ -0,0 +1,105 @@
+//! Cursor library.
+//!
+//! This module defines cursor data types that can be used for inserting instructions.
+
+use ir;
+use isa::Tar... | 3 | 122 | 39 |
621abb50269b9f9924a843183307d617defba3e4 | Jakob Stoklund Olesen | 2017-08-04T18:23:37 | Reorganize the instruction builder traits.
Leave the primary InstBuilderBase trait alone, but add an alternative
InstInserterBase trait that can be implemented instead by builders that
always allocate new instructions with dfg.make_inst().
Any implementation of InstInserterBase can be used as an instruction
builder b... | diff --git a/lib/cretonne/src/ir/builder.rs b/lib/cretonne/src/ir/builder.rs
index 59de1f68b..697acfebd 100644
--- a/lib/cretonne/src/ir/builder.rs
+++ b/lib/cretonne/src/ir/builder.rs
@@ -4,7 +4,7 @@
//! function. Many of its methods are generated from the meta language instruction definitions.
use ir::types;
-use... | 4 | 115 | 54 |
aa0c37235a4ad93ce9cef9701d9c9fffdf75415e | Jakob Stoklund Olesen | 2017-08-04T01:03:58 | Add CursorBase builder methods.
The CursorBase::at_* are convenience methods for building a cursor that
points to a specific instruction. | diff --git a/lib/cretonne/src/ir/layout.rs b/lib/cretonne/src/ir/layout.rs
index b1e068ff5..081a28905 100644
--- a/lib/cretonne/src/ir/layout.rs
+++ b/lib/cretonne/src/ir/layout.rs
@@ -672,6 +672,47 @@ pub trait CursorBase {
/// Borrow a mutable reference to the function layout that this cursor is navigating.
... | 2 | 43 | 5 |
f1758820304c8643e6052e34019d7dad286f9ddd | Jakob Stoklund Olesen | 2017-08-04T15:44:17 | Avoid evaluating dbg!() arguments in a closure.
The dbg!() macro should behave like a function call in how it evaluates
its arguments, and captures by Rust closures are not fully compatible
with path-specific borrowing. Specifically:
let borrow = &mut obj.foo;
dbg!("{}", obj.bar);
would fail because the clos... | diff --git a/lib/cretonne/src/dbg.rs b/lib/cretonne/src/dbg.rs
index dc7793f3d..bf1b92ef7 100644
--- a/lib/cretonne/src/dbg.rs
+++ b/lib/cretonne/src/dbg.rs
@@ -15,7 +15,7 @@ use std::env;
use std::ffi::OsStr;
use std::fmt;
use std::fs::File;
-use std::io::{Write, BufWriter};
+use std::io::{self, Write};
use std::s... | 1 | 8 | 10 |
05ba8dcab652d306b24c12ef1a547c087057ff6c | Denis Merigoux | 2017-08-04T01:26:41 | Added partial recompute of dominator tree in case of Ebb splitting (#135)
* Partial recompute for dominator tree in case of ebb splitting
Implemented via striding in RPO numbers | diff --git a/lib/cretonne/src/dominator_tree.rs b/lib/cretonne/src/dominator_tree.rs
index 14f08e426..6e61eeaa9 100644
--- a/lib/cretonne/src/dominator_tree.rs
+++ b/lib/cretonne/src/dominator_tree.rs
@@ -7,10 +7,16 @@ use packed_option::PackedOption;
use std::cmp::Ordering;
+// RPO numbers are not first assigned ... | 2 | 164 | 4 |
92392c6041ba02370be515978bb4a6a59878ea04 | Jakob Stoklund Olesen | 2017-08-03T20:48:30 | Add a prologue_epilogue() hook to TargetIsa.
This will compute the stack frame layout as appropriate for the
function's calling convention and insert prologue and epilogue code.
The default implementation is not useful, each target ISA will need to
override this function. | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index d0288789f..9967f1e11 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -68,6 +68,7 @@ impl Context {
self.legalize(isa)?;
self.regalloc(isa)?;
+ self.prologue_epilogue(isa)?;
self... | 2 | 20 | 0 |
39cc7efc2dd92edf5c076abed636efaa86a23be3 | Jakob Stoklund Olesen | 2017-08-03T20:31:58 | Move the stack layout computation into its own module.
This is trying to keep algorithms out if the ir module which deals with
the intermediate representation.
Also give the layout_stack() function a Result return value so it can
report a soft error when the stack frame is too large instead of
asserting. Since local ... | diff --git a/lib/cretonne/src/ir/stackslot.rs b/lib/cretonne/src/ir/stackslot.rs
index ea28eeae1..6f3de96cd 100644
--- a/lib/cretonne/src/ir/stackslot.rs
+++ b/lib/cretonne/src/ir/stackslot.rs
@@ -5,7 +5,6 @@
use entity_map::{EntityMap, PrimaryEntityData, Keys};
use ir::{Type, StackSlot};
-use std::cmp::{min, max};... | 4 | 194 | 172 |
5fa991e325de8e71d27b8016fbe2bff60ba8a378 | Aleksey Kuznetsov | 2017-07-29T15:05:45 | Apply conditional compilation of isa targets | diff --git a/lib/cretonne/src/isa/mod.rs b/lib/cretonne/src/isa/mod.rs
index b808b8874..7caac93a6 100644
--- a/lib/cretonne/src/isa/mod.rs
+++ b/lib/cretonne/src/isa/mod.rs
@@ -27,10 +27,10 @@
//! let shared_flags = settings::Flags::new(&shared_builder);
//!
//! match isa::lookup("riscv") {
-//! None => {
+//! ... | 4 | 55 | 28 |
c057e005ce9a5c177088ead714aaebd476b8048f | Aleksey Kuznetsov | 2017-07-29T11:21:41 | Implement conditional compilation configuration in build.rs | diff --git a/lib/cretonne/build.rs b/lib/cretonne/build.rs
index 4766a032e..2653bf54a 100644
--- a/lib/cretonne/build.rs
+++ b/lib/cretonne/build.rs
@@ -8,6 +8,13 @@
// OUT_DIR
// Directory where generated files should be placed.
//
+// TARGET
+// Target triple provided by Cargo.
+//
+// CRETONNE_TARGETS (Op... | 1 | 104 | 0 |
5edf48b5488911d6127f1c3cbc5762094b0b2203 | Jakob Stoklund Olesen | 2017-08-02T19:58:53 | Compute the stack frame layout.
Add a StackSlots::layout() method which computes the total stack frame
size and assigns offsets to all spill slots and local variables so they
don't interfere with each other or with incoming or outgoing function
arguments.
Stack slots are given an ad hoc alignment that is the natural ... | diff --git a/lib/cretonne/src/ir/stackslot.rs b/lib/cretonne/src/ir/stackslot.rs
index 56dd037dc..ea28eeae1 100644
--- a/lib/cretonne/src/ir/stackslot.rs
+++ b/lib/cretonne/src/ir/stackslot.rs
@@ -5,10 +5,23 @@
use entity_map::{EntityMap, PrimaryEntityData, Keys};
use ir::{Type, StackSlot};
+use std::cmp::{min, max... | 1 | 230 | 12 |
587f37ec6cfa1297824c621c2724fca3c943b192 | Dan Gohman | 2017-08-02T18:19:16 | Don't use documentation-style comments inside a function body. (#131) | diff --git a/lib/cretonne/src/regalloc/coalescing.rs b/lib/cretonne/src/regalloc/coalescing.rs
index 964644fad..29051bf42 100644
--- a/lib/cretonne/src/regalloc/coalescing.rs
+++ b/lib/cretonne/src/regalloc/coalescing.rs
@@ -383,8 +383,8 @@ impl<'a> Context<'a> {
succ_val: Value,
... | 1 | 2 | 2 |
406d82f62a9602e75d1d3f5ebea49af04f1afdf4 | Dan Gohman | 2017-08-02T18:05:49 | Avoid floating-point types in Ieee32::new and Ieee64::new. (#130)
* Avoid floating-point types in Ieee32::new and Ieee64::new.
This eliminates the need for unsafe code in code that uses Cretonne, a few
instances of unsafe code in Cretonne itself, and eliminates the only instance
of floating point in Cretonne.
... | diff --git a/lib/cretonne/src/ir/immediates.rs b/lib/cretonne/src/ir/immediates.rs
index fa6185cb8..c525305a1 100644
--- a/lib/cretonne/src/ir/immediates.rs
+++ b/lib/cretonne/src/ir/immediates.rs
@@ -7,9 +7,11 @@
use std::fmt::{self, Display, Formatter};
use std::{i32, u32};
-use std::mem;
use std::str::FromStr;
... | 2 | 52 | 35 |
ce9e6fe53ea81c16ac61121d030dd5605d113f06 | Jakob Stoklund Olesen | 2017-07-31T22:04:41 | Verify the location of outgoing call arguments.
Once a signature has been legalized, the arguments to any call using
that signature must be assigned to the proper stack locations. Outgoing
arguments that are passed on the stack must be assigned to matching
OutgoingArg stack slot locations.
Outgoing arguments that are... | diff --git a/lib/cretonne/src/verifier/mod.rs b/lib/cretonne/src/verifier/mod.rs
index a1e04fbb7..751f6d5f6 100644
--- a/lib/cretonne/src/verifier/mod.rs
+++ b/lib/cretonne/src/verifier/mod.rs
@@ -57,7 +57,7 @@ use flowgraph::ControlFlowGraph;
use ir::entities::AnyEntity;
use ir::instructions::{InstructionFormat, Bra... | 1 | 61 | 1 |
7d9edc2d5ee20bf3fda084873bb5fe389466d96f | Jakob Stoklund Olesen | 2017-07-31T19:58:20 | Keep track of OutgoingArg stack slots.
Stack slots for outgoing arguments can be reused between function calls.
Add a list of outgoing argument stack slots allocated so far, and
provide a `get_outgoing_arg()` method which will reuse any outgoing
stack slots with matching size and offset. | diff --git a/lib/cretonne/src/ir/stackslot.rs b/lib/cretonne/src/ir/stackslot.rs
index c6fd64ce5..56dd037dc 100644
--- a/lib/cretonne/src/ir/stackslot.rs
+++ b/lib/cretonne/src/ir/stackslot.rs
@@ -75,6 +75,9 @@ pub struct StackSlotData {
/// On Intel ISAs, the base address is the stack pointer *before* the return ... | 1 | 62 | 1 |
b547b786837e3f0e42fe85c24d34ca3b35d505d3 | Denis Merigoux | 2017-07-27T23:30:48 | Bugfix: encode function wasn't calling legalize function properly | diff --git a/lib/cretonne/src/isa/mod.rs b/lib/cretonne/src/isa/mod.rs
index 6c4304082..f85c98df5 100644
--- a/lib/cretonne/src/isa/mod.rs
+++ b/lib/cretonne/src/isa/mod.rs
@@ -170,7 +170,7 @@ pub trait TargetIsa {
ctrl_typevar: ir::Type)
-> Result<Encoding, Legalize> {
let mut it... | 1 | 1 | 1 |
637966dc7fb890dec6e8e38d0944bedb1d4393ab | Jakob Stoklund Olesen | 2017-07-25T23:33:35 | Add support for legalization codes in the encoding tables.
The new encoding format allows entries that mean "stop with this
legalization code" which makes it possible to configure legalization
actions per instruction, instead of only per controlling type variable.
This patch adds the Rust side of the legalization cod... | diff --git a/lib/cretonne/src/isa/arm32/mod.rs b/lib/cretonne/src/isa/arm32/mod.rs
index 1e5cde38d..f9a44db25 100644
--- a/lib/cretonne/src/isa/arm32/mod.rs
+++ b/lib/cretonne/src/isa/arm32/mod.rs
@@ -10,7 +10,7 @@ use binemit::{CodeSink, MemoryCodeSink, emit_function};
use super::super::settings as shared_settings;
... | 6 | 116 | 97 |
4142a9ca9cf64009057675f9dd4daf21f213390b | Jakob Stoklund Olesen | 2017-07-22T04:10:32 | Return a Result from constant_hash::probe.
When a hash table probe fails, return the index of the failed entry.
This can be used to store default values in the sentinel entries. | diff --git a/lib/cretonne/src/constant_hash.rs b/lib/cretonne/src/constant_hash.rs
index 08cc2944c..a165654dc 100644
--- a/lib/cretonne/src/constant_hash.rs
+++ b/lib/cretonne/src/constant_hash.rs
@@ -24,8 +24,12 @@ pub trait Table<K: Copy + Eq> {
/// The provided `hash` value must have been computed from `key` using ... | 4 | 38 | 22 |
2f7057b96f41ef4969fa1472348e303731bc68e1 | Jakob Stoklund Olesen | 2017-07-18T01:13:05 | Add a Context::emit_to_memory function.
This function will emit the binary machine code into contiguous raw
memory while sending relocations to a RelocSink.
Add a MemoryCodeSink for generating machine code directly into memory
efficiently. Allow the TargetIsa to provide emit_function
implementations that are speciali... | diff --git a/cranelift/src/filetest/compile.rs b/cranelift/src/filetest/compile.rs
index 15db119ef..f3766f001 100644
--- a/cranelift/src/filetest/compile.rs
+++ b/cranelift/src/filetest/compile.rs
@@ -51,12 +51,9 @@ impl SubTest for TestCompile {
// Finally verify that the returned code size matches the emit... | 9 | 168 | 13 |
28457f82c3ebf06b9d6062546374481914cecc8f | Jakob Stoklund Olesen | 2017-07-18T01:13:05 | Add a Context::emit_to_memory function.
This function will emit the binary machine code into contiguous raw
memory while sending relocations to a RelocSink.
Add a MemoryCodeSink for generating machine code directly into memory
efficiently. Allow the TargetIsa to provide emit_function
implementations that are speciali... | diff --git a/lib/cretonne/src/binemit/memorysink.rs b/lib/cretonne/src/binemit/memorysink.rs
new file mode 100644
index 000000000..f3fd5cebb
--- /dev/null
+++ b/lib/cretonne/src/binemit/memorysink.rs
@@ -0,0 +1,108 @@
+//! Code sink that writes binary machine code into contiguous memory.
+//!
+//! The `CodeSink` trait ... | 9 | 168 | 13 |
6d6035b91859e76993f33f945b16e7bbea71e757 | Jakob Stoklund Olesen | 2017-07-13T20:18:18 | CSSA verifier.
During register allocation, the code must be kept in conventional SSA
form. Add a verifier that checks this property. | diff --git a/lib/cretonne/src/regalloc/context.rs b/lib/cretonne/src/regalloc/context.rs
index 1961add95..052398460 100644
--- a/lib/cretonne/src/regalloc/context.rs
+++ b/lib/cretonne/src/regalloc/context.rs
@@ -17,7 +17,7 @@ use regalloc::spilling::Spilling;
use regalloc::virtregs::VirtRegs;
use result::CtonResult;... | 5 | 137 | 3 |
9e3b6a6eba83e0690dd5ee097e7eca5d5c4b3a81 | Jakob Stoklund Olesen | 2017-07-11T23:26:16 | Add a Context::compile() function which runs all compiler passes.
This is the main entry point to the code generator. It returns the
computed size of the functions code.
Also add a 'test compile' command which runs the whole code generation
pipeline. | diff --git a/cranelift/src/filetest/binemit.rs b/cranelift/src/filetest/binemit.rs
index 15f5b0a98..d359cea79 100644
--- a/cranelift/src/filetest/binemit.rs
+++ b/cranelift/src/filetest/binemit.rs
@@ -12,7 +12,7 @@ use cretonne::ir::entities::AnyEntity;
use cretonne::isa::TargetIsa;
use cton_reader::TestCommand;
use... | 5 | 143 | 8 |
6cc729a69b06a887d8c37c6ea6f60f87baab4b5a | Jakob Stoklund Olesen | 2017-07-11T23:26:16 | Add a Context::compile() function which runs all compiler passes.
This is the main entry point to the code generator. It returns the
computed size of the functions code.
Also add a 'test compile' command which runs the whole code generation
pipeline. | diff --git a/lib/cretonne/src/binemit/relaxation.rs b/lib/cretonne/src/binemit/relaxation.rs
index d80d17d7b..3420134d1 100644
--- a/lib/cretonne/src/binemit/relaxation.rs
+++ b/lib/cretonne/src/binemit/relaxation.rs
@@ -31,11 +31,12 @@ use binemit::CodeOffset;
use ir::{Function, DataFlowGraph, Cursor, InstructionData... | 5 | 143 | 8 |
0917cfe7f469fe7a278262543114b56fd8cc2e55 | Jakob Stoklund Olesen | 2017-07-12T17:37:50 | Attach encodings to regmove instructions generated during coloring.
All emitted regmove instructions must be materialized as real move
instructions. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 85911efd0..21a4453bb 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -43,7 +43,8 @@
//! The exception is the entry block whose arguments are colored from the ABI requiremen... | 1 | 13 | 4 |
69f974ba5d320c0dbe2e6186d6a3b1de410df844 | Jakob Stoklund Olesen | 2017-07-12T17:12:20 | Add an ISA argument to dfg.display_inst().
Include ISA-specific annotations in tracing and error messages. | diff --git a/cranelift/src/filetest/binemit.rs b/cranelift/src/filetest/binemit.rs
index 2f695bff1..15f5b0a98 100644
--- a/cranelift/src/filetest/binemit.rs
+++ b/cranelift/src/filetest/binemit.rs
@@ -127,7 +127,7 @@ impl SubTest for TestBinEmit {
AnyEntity::Inst(inst) => {
... | 10 | 42 | 33 |
b6d4b884ad058f77f40f1783b8e9f0428aac2749 | Jakob Stoklund Olesen | 2017-07-12T17:12:20 | Add an ISA argument to dfg.display_inst().
Include ISA-specific annotations in tracing and error messages. | diff --git a/lib/cretonne/src/binemit/mod.rs b/lib/cretonne/src/binemit/mod.rs
index 33cce8d2b..eaa721d51 100644
--- a/lib/cretonne/src/binemit/mod.rs
+++ b/lib/cretonne/src/binemit/mod.rs
@@ -53,5 +53,5 @@ pub trait CodeSink {
pub fn bad_encoding(func: &Function, inst: Inst) -> ! {
panic!("Bad encoding {} for {}... | 10 | 42 | 33 |
e4da2e1f22707cb542af0dbb5a84696ec6533766 | Jakob Stoklund Olesen | 2017-07-12T16:59:00 | Include ISA-specific information in verifier errors.
When the test driver reports a verifier error, make sure to include the
TargetIsa when printing the failing function. | diff --git a/cranelift/src/filetest/legalizer.rs b/cranelift/src/filetest/legalizer.rs
index 806730b4e..0c5ea04b7 100644
--- a/cranelift/src/filetest/legalizer.rs
+++ b/cranelift/src/filetest/legalizer.rs
@@ -43,7 +43,7 @@ impl SubTest for TestLegalizer {
comp_ctx.flowgraph();
comp_ctx
.l... | 6 | 14 | 10 |
71af555e6f6fa094be42e51676492dd04d0c3053 | Jakob Stoklund Olesen | 2017-07-12T16:59:00 | Include ISA-specific information in verifier errors.
When the test driver reports a verifier error, make sure to include the
TargetIsa when printing the failing function. | diff --git a/src/filetest/legalizer.rs b/src/filetest/legalizer.rs
index 806730b4e..0c5ea04b7 100644
--- a/src/filetest/legalizer.rs
+++ b/src/filetest/legalizer.rs
@@ -43,7 +43,7 @@ impl SubTest for TestLegalizer {
comp_ctx.flowgraph();
comp_ctx
.legalize(isa)
- .map_err(|e| p... | 6 | 14 | 10 |
60efc6893197cdf1c39e9f39686d4ee3c0686ef2 | Jakob Stoklund Olesen | 2017-07-05T21:22:34 | Only print pressure for toprcs containing registers.
Many ISAs don't need 4 top-level register classes, so don't print them. | diff --git a/lib/cretonne/src/regalloc/pressure.rs b/lib/cretonne/src/regalloc/pressure.rs
index 3bf1e68f5..fd9cf7c36 100644
--- a/lib/cretonne/src/regalloc/pressure.rs
+++ b/lib/cretonne/src/regalloc/pressure.rs
@@ -238,7 +238,9 @@ impl fmt::Display for Pressure {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Res... | 1 | 3 | 1 |
9108716cb78349d8d218b1b1921be1a39e579bbd | Jakob Stoklund Olesen | 2017-07-01T02:09:10 | Implement fmt::Display for AllocatableSet.
Also add a display() method which accepts a RegInfo reference. | diff --git a/lib/cretonne/src/regalloc/allocatable_set.rs b/lib/cretonne/src/regalloc/allocatable_set.rs
index aecd338e7..063c8e63a 100644
--- a/lib/cretonne/src/regalloc/allocatable_set.rs
+++ b/lib/cretonne/src/regalloc/allocatable_set.rs
@@ -5,7 +5,8 @@
//! "register unit" abstraction. Every register contains one o... | 2 | 50 | 2 |
aa3bf4467eb47bed39c979c5d5645adacaf135d2 | Jakob Stoklund Olesen | 2017-06-30T15:41:54 | Hook up the handling of tied register constraints.
Tests are forthcoming, we need to implement Intel ABI lowering first. | diff --git a/lib/cretonne/src/regalloc/liverange.rs b/lib/cretonne/src/regalloc/liverange.rs
index 95dfb49f2..9174e0cdb 100644
--- a/lib/cretonne/src/regalloc/liverange.rs
+++ b/lib/cretonne/src/regalloc/liverange.rs
@@ -399,7 +399,7 @@ impl LiveRange {
}
}
- /// Check if this live range reaches a us... | 2 | 17 | 6 |
2b999d9bd67751ced2b091a778830c2f2977df05 | Jakob Stoklund Olesen | 2017-06-29T22:13:04 | Add an Index<Value> implementation to Liveness.
Use it to access live ranges that are supposed to be there. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 1a21f78f7..733506ef0 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -474,17 +474,14 @@ impl<'a> Context<'a> {
//
// It is possible... | 4 | 17 | 12 |
ae661631aa9313d7e252753635de07d67e92d6a9 | Jakob Stoklund Olesen | 2017-06-29T20:29:43 | Only color EBB arguments that have register affinity.
It is possible to pass a register value as an argument to an EBB that
expects a "None" affinity. In that case, the destination EBB value
should not be colored. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index c2353de40..1a21f78f7 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -200,13 +200,13 @@ impl<'a> Context<'a> {
.get(value)
.expect("No live... | 1 | 14 | 7 |
d6f73ac4c878a26e73fb32bd5a3bde805c80fbf3 | Jakob Stoklund Olesen | 2017-06-29T18:11:46 | Split spill_from() into spill_candidate() and spill_reg().
We'll need to pick a spill candidate from a set and allow for the search
to fail to find anything.
This also allows slightly better panic messages when we run out of
registers. | diff --git a/lib/cretonne/src/regalloc/spilling.rs b/lib/cretonne/src/regalloc/spilling.rs
index c64fd565e..1b438a7b5 100644
--- a/lib/cretonne/src/regalloc/spilling.rs
+++ b/lib/cretonne/src/regalloc/spilling.rs
@@ -260,7 +260,14 @@ impl<'a> Context<'a> {
// Add register def to pressure, spill if need... | 1 | 31 | 21 |
165e80d9bf2a272614ce33a4aec6d5af0359f705 | Jakob Stoklund Olesen | 2017-06-27T23:04:50 | Process ghost instruction kills during coloring.
Ghost instructions don't generate code, but they can keep registers
alive. The coloring pass needs to process values killed by ghost
instructions so it knows when the registers are freed up.
Also track register pressure changes from ghost kills in the spiller. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 56244bcc3..878656ae8 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -147,8 +147,11 @@ impl<'a> Context<'a> {
&mut regs,
... | 4 | 69 | 3 |
222ea748303961bea1c6d5e6e32e910210da58bf | Jakob Stoklund Olesen | 2017-06-23T17:43:59 | Spill whole virtual registers at a time.
When the spiller decides to spill a value, bring along all of the values
in its virtual register. This ensures that we won't have problems with
computing register pressure around EBB arguments. They will always be
register-to-register or stack-to-stack with related values using... | diff --git a/lib/cretonne/src/regalloc/context.rs b/lib/cretonne/src/regalloc/context.rs
index 78e159574..0908b02a1 100644
--- a/lib/cretonne/src/regalloc/context.rs
+++ b/lib/cretonne/src/regalloc/context.rs
@@ -66,14 +66,14 @@ impl Context {
// phases.
self.tracker.clear();
- // First pass:... | 2 | 18 | 11 |
d5055275c4b76c7caa5937b7eeb6b50d1c57afe1 | Jakob Stoklund Olesen | 2017-06-20T22:17:19 | Virtual registers.
Add a VirtRegs collection which tracks virtual registers.
A virtual register is a set of related SSA values whose live ranges
don't interfere. It is advantageous to use the same register or spill
slot for al the values in a virtual register. It reduces copies for EBB
arguments. | diff --git a/lib/cretonne/src/regalloc/context.rs b/lib/cretonne/src/regalloc/context.rs
index b404602a3..ea2cdcd92 100644
--- a/lib/cretonne/src/regalloc/context.rs
+++ b/lib/cretonne/src/regalloc/context.rs
@@ -13,6 +13,7 @@ use regalloc::live_value_tracker::LiveValueTracker;
use regalloc::liveness::Liveness;
use r... | 3 | 141 | 0 |
d079dead9ad434ab8a8a2cd9157b09ec93826736 | Jakob Stoklund Olesen | 2017-06-22T16:31:32 | Skip ghost instructions when coloring.
Ghost instructions don't have an encoding, and don't appear in the
output. The values they define do not need to be assigned to registers,
so they can be skipped. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index c71218e7c..56244bcc3 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -31,18 +31,18 @@
//! defined by the instruction and only consider the colors of other values that are l... | 1 | 16 | 24 |
03a856f4dafcfa8baa8b31c590a6042c35ccbd0c | Jakob Stoklund Olesen | 2017-06-22T15:44:08 | Implement Display and Debug for the program point types. | diff --git a/lib/cretonne/src/ir/progpoint.rs b/lib/cretonne/src/ir/progpoint.rs
index 373bc382a..7adeb43c5 100644
--- a/lib/cretonne/src/ir/progpoint.rs
+++ b/lib/cretonne/src/ir/progpoint.rs
@@ -82,15 +82,28 @@ impl From<ProgramPoint> for ExpandedProgramPoint {
}
}
-impl fmt::Display for ProgramPoint {
+impl ... | 1 | 15 | 2 |
10e4b2fa06cee7940541474505a9fbcebd886b95 | Jakob Stoklund Olesen | 2017-06-21T17:03:39 | Add two interference checking methods to LiveInterval.
The overlaps_def() method tests if a definition would conflict with the
live range.
The reaches_use() method tests if a live range is live at an
instruction. | diff --git a/lib/cretonne/src/regalloc/liverange.rs b/lib/cretonne/src/regalloc/liverange.rs
index 9866fabb2..95dfb49f2 100644
--- a/lib/cretonne/src/regalloc/liverange.rs
+++ b/lib/cretonne/src/regalloc/liverange.rs
@@ -108,7 +108,7 @@
//!
use std::cmp::Ordering;
-use ir::{Inst, Ebb, Value, ProgramPoint, ProgramOr... | 1 | 35 | 1 |
b6cff6a98a95d23127a40445bbced31d22134f6b | Jakob Stoklund Olesen | 2017-06-20T17:07:23 | Move EntityRef and entity_impl! into a new module.
The EntityRef trait is used by more than just the EntityMap now, so it
should live in its own module.
Also move the entity_impl! macro into the new module so it can be used
for defining new entity references anywhere. | diff --git a/lib/cretonne/src/entity_list.rs b/lib/cretonne/src/entity_list.rs
index 1ccddc3ae..4b535e3f5 100644
--- a/lib/cretonne/src/entity_list.rs
+++ b/lib/cretonne/src/entity_list.rs
@@ -46,12 +46,11 @@
//! The index stored in an `EntityList` points to part 2, the list elements. The value 0 is
//! reserved for ... | 14 | 85 | 100 |
0c7316ae28d17f436e5c362a259bdd1c94180228 | Dan Gohman | 2017-06-19T23:24:10 | Lint fixes (#99)
* Replace a single-character string literal with a character literal.
* Use is_some() instead of comparing with Some(_).
* Add code-quotes around type names in comments.
* Use !...is_empty() instead of len() != 0.
* Tidy up redundant returns.
* Remove redundant .clone() calls.
* Remo... | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index 90c4948b4..5e23ed3ef 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -60,7 +60,7 @@ impl Context {
///
/// The `isa` argument is currently unused, but the verifier will soon be able to also
/// chec... | 24 | 132 | 137 |
ddbf46bef4697bf4c2a21e70f1faa632c8024c0f | Jakob Stoklund Olesen | 2017-06-16T20:08:13 | Add typedefs for the common entity maps.
The various entity maps in a function end up being referenced in
multiple places, so create typedefs for them. | diff --git a/lib/cretonne/src/binemit/relaxation.rs b/lib/cretonne/src/binemit/relaxation.rs
index 517867c72..53b7fd011 100644
--- a/lib/cretonne/src/binemit/relaxation.rs
+++ b/lib/cretonne/src/binemit/relaxation.rs
@@ -28,9 +28,8 @@
//! ```
use binemit::CodeOffset;
-use entity_map::EntityMap;
-use ir::{Function, ... | 5 | 45 | 32 |
605bda292565a77d701086dc83cb5b039aa9cc3c | Jakob Stoklund Olesen | 2017-06-16T18:51:41 | Add a stack frame manager.
Use a new StackSlots struct to keep track of a function's stack slots
instead of just an entity map. This let's us build more internal data
structures for tracking the stack slots if necessary.
Start by adding a make_spill_slot() function that will be used by the
register allocator. | diff --git a/lib/cretonne/src/ir/function.rs b/lib/cretonne/src/ir/function.rs
index 075ee7c6f..3cb547fdf 100644
--- a/lib/cretonne/src/ir/function.rs
+++ b/lib/cretonne/src/ir/function.rs
@@ -5,8 +5,8 @@
use binemit::CodeOffset;
use entity_map::{EntityMap, PrimaryEntityData};
-use ir::{FunctionName, Signature, Val... | 3 | 73 | 6 |
96f122821109ce2015e2115c37a5cc97c36ce8a3 | Jakob Stoklund Olesen | 2017-06-14T19:05:47 | Always call reassign_in for register ABI arguments.
Even if an argument is already in the correct register, make sure that
we detect conflicts by registering the no-op move. This also means that
the ABI argument register won't be turned into a variable for the
solver. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 8fd602fe3..53546de07 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -430,18 +430,16 @@ impl<'a> Context<'a> {
locations: &EntityMap<Value, ValueLo... | 2 | 19 | 19 |
897c363714f2e0ae6a34d0f432f91f43f382bf7e | Jakob Stoklund Olesen | 2017-06-14T17:35:01 | Update docopt dependency to 0.8.0.
This breaks our depending on two different versions of the regex
library.
This updated docopt uses serde instead of rustc_serialize. | diff --git a/cranelift/Cargo.toml b/cranelift/Cargo.toml
index d0da28f91..06eed706e 100644
--- a/cranelift/Cargo.toml
+++ b/cranelift/Cargo.toml
@@ -16,8 +16,9 @@ path = "src/cton-util.rs"
cretonne = { path = "lib/cretonne" }
cretonne-reader = { path = "lib/reader" }
filecheck = { path = "lib/filecheck" }
-docopt = ... | 2 | 10 | 7 |
e7c6efa31e3e8e76568cc533f7998956228bd404 | Jakob Stoklund Olesen | 2017-06-14T17:35:01 | Update docopt dependency to 0.8.0.
This breaks our depending on two different versions of the regex
library.
This updated docopt uses serde instead of rustc_serialize. | diff --git a/Cargo.toml b/Cargo.toml
index d0da28f91..06eed706e 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -16,8 +16,9 @@ path = "src/cton-util.rs"
cretonne = { path = "lib/cretonne" }
cretonne-reader = { path = "lib/reader" }
filecheck = { path = "lib/filecheck" }
-docopt = "0.6.86"
-rustc-serialize = "0.3.19"
-nu... | 2 | 10 | 7 |
9cea092bc32bd37a6cd49b457c9b94e293932256 | Jakob Stoklund Olesen | 2017-06-12T18:55:01 | Track transient register counts in Pressure.
The register pressure tracker now has to separate register counts: base
and transient.
The transient counts are used to track spikes of register pressure, such
as dead defs or temporary registers needed to satisfy instruction
constraints.
The base counts represent long-li... | diff --git a/lib/cretonne/src/regalloc/pressure.rs b/lib/cretonne/src/regalloc/pressure.rs
index 14e444169..6ddf6bdf4 100644
--- a/lib/cretonne/src/regalloc/pressure.rs
+++ b/lib/cretonne/src/regalloc/pressure.rs
@@ -26,6 +26,12 @@
//!
//! Currently, the only register bank with multiple top-level registers is the `ar... | 1 | 49 | 11 |
ea8a8a95a89c9c7f403ffa1e054a4b959f077934 | Jakob Stoklund Olesen | 2017-06-12T21:59:34 | Remove the ebb_dominates function.
This is now subsumed by the generic 'dominates' function. | diff --git a/lib/cretonne/src/dominator_tree.rs b/lib/cretonne/src/dominator_tree.rs
index 8022ee109..14f08e426 100644
--- a/lib/cretonne/src/dominator_tree.rs
+++ b/lib/cretonne/src/dominator_tree.rs
@@ -141,28 +141,6 @@ impl DominatorTree {
if a == ebb_b { inst_b } else { None }
}
- /// Returns `tr... | 4 | 5 | 27 |
a1dfd0f06f615b3c30a34acc76e5589601f2dafa | Jakob Stoklund Olesen | 2017-06-12T21:52:42 | Generalize DominatorTree::dominates.
This is now a generic function that can test arbitrary combinations of
instructions and EBBs for dominance.
It can handle anything that converts into an expanded program point,
including a ValueDef.
Also fix a bug if the earlier dominates() function which didn't properly
handle b... | diff --git a/lib/cretonne/src/dominator_tree.rs b/lib/cretonne/src/dominator_tree.rs
index 66fdeb2ff..8022ee109 100644
--- a/lib/cretonne/src/dominator_tree.rs
+++ b/lib/cretonne/src/dominator_tree.rs
@@ -97,9 +97,48 @@ impl DominatorTree {
/// is unreachable.
///
/// An instruction is considered to domi... | 1 | 117 | 3 |
4f9ff548bdbfb96916bffee13c0b3a3148d67b48 | Jakob Stoklund Olesen | 2017-06-12T20:53:12 | Generalize rpo_cmp to handle all program points.
When comparing instructions in the same EBB, behave like the RPO visits
instructions in program order.
- Add a Layout::pp_ebb() method for convenience. It gets the EBB
containing any program point.
- Add a conversion from ValueDef to ExpandedProgramPoint so it can be... | diff --git a/lib/cretonne/src/dominator_tree.rs b/lib/cretonne/src/dominator_tree.rs
index 6d42cefb3..66fdeb2ff 100644
--- a/lib/cretonne/src/dominator_tree.rs
+++ b/lib/cretonne/src/dominator_tree.rs
@@ -2,7 +2,7 @@
use entity_map::EntityMap;
use flowgraph::{ControlFlowGraph, BasicBlock};
-use ir::{Ebb, Inst, Func... | 3 | 48 | 5 |
2f33848fcdd9f7b49e04ab76ba6f8c05ce51cd8d | Denis Merigoux | 2017-06-09T23:20:38 | Improved DFG API (#95)
* Improved DFG API with swap_remove_ebb_args and append_inst_arg
* Implemented EntityList::swap_remove
And used it for dfg::swap_remove_ebb_arg | diff --git a/lib/cretonne/src/entity_list.rs b/lib/cretonne/src/entity_list.rs
index 946bb7ba0..1ccddc3ae 100644
--- a/lib/cretonne/src/entity_list.rs
+++ b/lib/cretonne/src/entity_list.rs
@@ -416,7 +416,7 @@ impl<T: EntityRef> EntityList<T> {
}
}
- /// Removes the element at position `index` from th... | 2 | 82 | 2 |
81284dbd93703d8e16032073a006d5244dd2b663 | Denis Merigoux | 2017-06-08T16:41:57 | LICM pass: small changes after code review (#94) | diff --git a/lib/cretonne/src/licm.rs b/lib/cretonne/src/licm.rs
index fc4b7e251..1c9e1930f 100644
--- a/lib/cretonne/src/licm.rs
+++ b/lib/cretonne/src/licm.rs
@@ -46,7 +46,7 @@ pub fn do_licm(func: &mut Function,
};
// The last instruction of the pre-header is the termination instruction (us... | 1 | 6 | 14 |
6563270c63fa6986053cf5f0522ef8d316a37873 | Jakob Stoklund Olesen | 2017-06-07T20:41:29 | Remove cfg.postorder_ebbs().
This is now unused. Use domtree.cfg_postorder() instead.
Also remove the dead cfg.ebbs(). | diff --git a/lib/cretonne/src/flowgraph.rs b/lib/cretonne/src/flowgraph.rs
index f445d2c8f..45596d41e 100644
--- a/lib/cretonne/src/flowgraph.rs
+++ b/lib/cretonne/src/flowgraph.rs
@@ -25,8 +25,7 @@
use ir::{Function, Inst, Ebb};
use ir::instructions::BranchInfo;
-use entity_map::{EntityMap, Keys};
-use std::collec... | 1 | 3 | 46 |
f22461b4b3d50dc488d9d05ab83895917b105aae | Jakob Stoklund Olesen | 2017-06-07T20:38:27 | Stop using cfg.postorder_ebbs().
Switch to the new domtree.cfg_postorder() which returns a reference to a
pre-computed post-order instead of allocating memory and computing a new
post-order. | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index a67a4bde0..90c4948b4 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -75,7 +75,7 @@ impl Context {
/// Run the legalizer for `isa` on the function.
pub fn legalize(&mut self, isa: &TargetIsa) -> CtonRe... | 4 | 12 | 10 |
0d227fd23044b1db0f1922e88634bf1e1955c9b3 | Jakob Stoklund Olesen | 2017-05-24T16:28:15 | Add a minimalistic reload pass.
The reload pass inserts spill and fill instructions as needed so
instructions that operate on registers will never see a value with stack
affinity.
This is a very basic implementation, and we can't write good test cases
until we have a spilling pass. | diff --git a/lib/cretonne/src/ir/dfg.rs b/lib/cretonne/src/ir/dfg.rs
index 363b80d2c..a402274d5 100644
--- a/lib/cretonne/src/ir/dfg.rs
+++ b/lib/cretonne/src/ir/dfg.rs
@@ -323,6 +323,16 @@ pub enum ValueDef {
Arg(Ebb, usize),
}
+impl ValueDef {
+ /// Unwrap the instruction where the value was defined, or pa... | 5 | 306 | 1 |
dcdfa59aec756ddf2d64d42f912357bd601b4d1b | Jakob Stoklund Olesen | 2017-06-07T18:33:47 | Implement a conversion from ValueDef into ProgramPoint.
A ValueDef is really no more than a program point plus an
argument/result number. | diff --git a/lib/cretonne/src/ir/progpoint.rs b/lib/cretonne/src/ir/progpoint.rs
index 7d57ab8cb..c99e79dbe 100644
--- a/lib/cretonne/src/ir/progpoint.rs
+++ b/lib/cretonne/src/ir/progpoint.rs
@@ -1,7 +1,7 @@
//! Program points.
use entity_map::EntityRef;
-use ir::{Ebb, Inst};
+use ir::{Ebb, Inst, ValueDef};
use s... | 1 | 10 | 1 |
9adfd8709b61cf5c9a015efeef65d842b546d58e | Jakob Stoklund Olesen | 2017-06-07T17:39:47 | Add Liveness methods for updating live ranges.
The create_dead() methods can create a live range for a new value, and
extend_local() can extend a live range within an EBB where it is already
live.
This is enough to update liveness for new values as long as they stay
local to their EBB. | diff --git a/lib/cretonne/src/regalloc/liveness.rs b/lib/cretonne/src/regalloc/liveness.rs
index f2c9944d4..3ced8ebc0 100644
--- a/lib/cretonne/src/regalloc/liveness.rs
+++ b/lib/cretonne/src/regalloc/liveness.rs
@@ -177,7 +177,7 @@
use flowgraph::ControlFlowGraph;
use ir::dfg::ValueDef;
-use ir::{Function, Value, ... | 2 | 50 | 1 |
402cb8e1f63f85859c28e376012866451d0197ab | Jakob Stoklund Olesen | 2017-06-05T22:07:48 | Add a dfg::replace_result() method.
This is analogous to replace_ebb_arg(). It replaces an instruction
result value with a new value, leaving the old value in a detached
state. | diff --git a/lib/cretonne/src/ir/dfg.rs b/lib/cretonne/src/ir/dfg.rs
index c3c5422e7..363b80d2c 100644
--- a/lib/cretonne/src/ir/dfg.rs
+++ b/lib/cretonne/src/ir/dfg.rs
@@ -10,6 +10,7 @@ use ir::{Ebb, Inst, Value, Type, SigRef, Signature, FuncRef, ValueList, ValueLis
use write::write_operands;
use std::fmt;
use std:... | 1 | 40 | 0 |
de0f0e5f0ab7f4083f305683b1ab811e8ead42d7 | Igor | 2017-06-03T19:40:53 | Updated the regex crate to 0.2.2 as per issue #88 (#90)
* Updated the regex crate to 0.2.2 as per issue #88
* Added potential fix for cryptic CI error.
* Fixed incorrect handling of regex name call.
Fixes #88 | diff --git a/lib/filecheck/Cargo.toml b/lib/filecheck/Cargo.toml
index ee31a8fa4..41effb059 100644
--- a/lib/filecheck/Cargo.toml
+++ b/lib/filecheck/Cargo.toml
@@ -11,4 +11,4 @@ documentation = "https://docs.rs/filecheck"
name = "filecheck"
[dependencies]
-regex = "0.1.71"
+regex = "0.2.2"
diff --git a/lib/fileche... | 3 | 16 | 15 |
c1d095de18f28d22fac59a2a8f2a36b2bb3d03cf | Aleksey Kuznetsov | 2017-06-03T11:20:41 | Run rustfmt on lib/filecheck/tests/basic.rs | diff --git a/lib/filecheck/tests/basic.rs b/lib/filecheck/tests/basic.rs
index 595158192..15e74788d 100644
--- a/lib/filecheck/tests/basic.rs
+++ b/lib/filecheck/tests/basic.rs
@@ -28,7 +28,10 @@ fn no_directives() {
#[test]
fn no_matches() {
- let c = CheckerBuilder::new().text("regex: FOO=bar").unwrap().finish... | 1 | 52 | 25 |
16df1f1cf521c95c16b1a5f8b9294216b60868bd | Jakob Stoklund Olesen | 2017-06-02T22:08:02 | Compute a CFG post-order when building the dominator tree.
The DominatorTree has existing DomNodes per EBB that can be used in lieu
of expensive HastSets for the depth-first traversal of the CFG.
Make the computed and cached post-order available for other passes
through the `cfg_postorder()` method which returns a sl... | diff --git a/cranelift/tests/cfg_traversal.rs b/cranelift/tests/cfg_traversal.rs
index 903b1a1ec..21e2a086b 100644
--- a/cranelift/tests/cfg_traversal.rs
+++ b/cranelift/tests/cfg_traversal.rs
@@ -1,30 +1,27 @@
extern crate cretonne;
extern crate cton_reader;
-use self::cretonne::entity_map::EntityMap;
use self::c... | 2 | 111 | 41 |
22ad3c0bf8e8f0f64470e471c19f1b8c0ec2c799 | Jakob Stoklund Olesen | 2017-06-02T22:08:02 | Compute a CFG post-order when building the dominator tree.
The DominatorTree has existing DomNodes per EBB that can be used in lieu
of expensive HastSets for the depth-first traversal of the CFG.
Make the computed and cached post-order available for other passes
through the `cfg_postorder()` method which returns a sl... | diff --git a/lib/cretonne/src/dominator_tree.rs b/lib/cretonne/src/dominator_tree.rs
index ed6aa4dbd..6d42cefb3 100644
--- a/lib/cretonne/src/dominator_tree.rs
+++ b/lib/cretonne/src/dominator_tree.rs
@@ -25,6 +25,12 @@ struct DomNode {
/// The dominator tree for a single function.
pub struct DominatorTree {
nod... | 2 | 111 | 41 |
b02ccea8dc601783fe93419ea757c04eb2d79423 | Denis Merigoux | 2017-06-02T22:00:29 | Loop analysis of the IL
* Implemented in two passes
* First pass discovers the loops headers (they dominate one of their predecessors)
* Second pass traverses the blocks of each loop
* Discovers the loop tree structure
* Offers a new LoopAnalysis data structure queried from outside the module | diff --git a/lib/cretonne/src/context.rs b/lib/cretonne/src/context.rs
index ce4b26957..9b0b3b31a 100644
--- a/lib/cretonne/src/context.rs
+++ b/lib/cretonne/src/context.rs
@@ -12,6 +12,7 @@
use dominator_tree::DominatorTree;
use flowgraph::ControlFlowGraph;
use ir::Function;
+use loop_analysis::LoopAnalysis;
use i... | 6 | 360 | 5 |
4f26764e7149be06f278e3cf6cdcb6d3ec20a872 | Aleksey Kuznetsov | 2017-06-01T15:48:36 | Remove unnecessary cloned() in reader::lexer::trailing_digits() | diff --git a/lib/reader/src/lexer.rs b/lib/reader/src/lexer.rs
index c5c2aa5d8..bbbb02349 100644
--- a/lib/reader/src/lexer.rs
+++ b/lib/reader/src/lexer.rs
@@ -87,8 +87,7 @@ fn trailing_digits(s: &str) -> usize {
s.as_bytes()
.iter()
.rev()
- .cloned()
- .take_while(|&b| b'0' <= b ... | 1 | 1 | 2 |
1d8efaad83f41afae8188a51eeb6d5c8cd97f5b7 | Jakob Stoklund Olesen | 2017-05-16T17:02:57 | Add a register pressure tracker.
The spilling and reload passes need to ensure that the set of live
ranges with register affinity can always be assigned registers. The
register pressure tracker can count how many registers are in use for
each top-level register class and give guidance on the type of
registers that nee... | diff --git a/lib/cretonne/src/regalloc/mod.rs b/lib/cretonne/src/regalloc/mod.rs
index fd2e78e9c..473a9fdb2 100644
--- a/lib/cretonne/src/regalloc/mod.rs
+++ b/lib/cretonne/src/regalloc/mod.rs
@@ -11,6 +11,7 @@ pub mod coloring;
mod affinity;
mod context;
mod diversion;
+mod pressure;
mod solver;
pub use self::a... | 2 | 297 | 0 |
d1e37def3f0587dffa55cd4a6524df5bfde113ed | Jakob Stoklund Olesen | 2017-05-16T17:46:19 | Implement ExactSizeIterator for RegSetIter.
The set of available registers in a register class is known ahead of
time. It can be computed with pop-count. | diff --git a/lib/cretonne/src/regalloc/allocatable_set.rs b/lib/cretonne/src/regalloc/allocatable_set.rs
index 756ad1d34..6ad8019ba 100644
--- a/lib/cretonne/src/regalloc/allocatable_set.rs
+++ b/lib/cretonne/src/regalloc/allocatable_set.rs
@@ -5,8 +5,9 @@
//! "register unit" abstraction. Every register contains one o... | 1 | 10 | 1 |
31b7330b8d7621f67043fd2ef6f95bdda8cdee68 | Jakob Stoklund Olesen | 2017-05-12T22:31:08 | Return the first applicable encoding from general_encoding().
We'll arrange encoding lists such that the first suitable encoding is
the best choice for the legalizer. This is the most intuitive way of
generating the encodings.
After register allocation, we may choose a different encoding, but that
will require lookin... | diff --git a/lib/cretonne/src/isa/enc_tables.rs b/lib/cretonne/src/isa/enc_tables.rs
index cfb0066b8..d7dde71ee 100644
--- a/lib/cretonne/src/isa/enc_tables.rs
+++ b/lib/cretonne/src/isa/enc_tables.rs
@@ -114,11 +114,11 @@ const CODE_ALWAYS: EncListEntry = PRED_MASK;
/// The encoding list terminator.
const CODE_FAIL:... | 1 | 6 | 6 |
6fd95c1158d2babe326694201766fa84d6dbffcd | Jakob Stoklund Olesen | 2017-05-12T00:58:11 | Implement reloc_names() for all targets.
This gets rid of the last TargetIsa method with a default
implementation. | diff --git a/lib/cretonne/src/isa/arm32/binemit.rs b/lib/cretonne/src/isa/arm32/binemit.rs
index dcc76331a..cf12bdbde 100644
--- a/lib/cretonne/src/isa/arm32/binemit.rs
+++ b/lib/cretonne/src/isa/arm32/binemit.rs
@@ -4,3 +4,5 @@ use binemit::{CodeSink, bad_encoding};
use ir::{Function, Inst};
include!(concat!(env!(... | 5 | 13 | 3 |
9be262e8780bf91911d50b6dcf5e24481db7955f | Jakob Stoklund Olesen | 2017-05-10T22:36:14 | Implement a move resolver for the register constraint solver.
After finding a register solution, it need to be executed as a sequence
of regmove instructions. This often requires a topological ordering of
the moves so they don't conflict.
When the solution contains cycles, try to grab an available scratch
register to... | diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 122dec8e7..91a25595f 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -164,6 +164,12 @@ impl fmt::Display for RegClassData {
}
}
+impl fmt::Debug for RegClassData {
+ fn fmt(&self... | 3 | 302 | 8 |
b521254149a9d655814cf01caf47ed50c9c3cf96 | Jakob Stoklund Olesen | 2017-05-10T19:31:59 | Solver variables keep track of where they came from.
The register constraint solver has two kinds of variables:
1. Live values that were already in a register, and
2. Values defined by the instruction.
Make a record of the original register holding the first kind of value. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 521b1c9cb..d8d3571ad 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -357,7 +357,7 @@ impl<'a> Context<'a> {
.unwrap_or_else(|_| self.iterate_solution());
... | 2 | 39 | 26 |
21b4c3a00bc2679e06d3e61051b16642225cc41f | Jakob Stoklund Olesen | 2017-05-11T18:48:58 | Simplify the dead EBB argument tracking.
It is not necessary to to a second pass over the live values to update
the set of available registers. The color_args() and color_entry_args()
functions can do that in a single pass. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index 6c0c906f9..521b1c9cb 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -163,24 +163,14 @@ impl<'a> Context<'a> {
tracker.ebb_top(ebb, &func.dfg, self.liveness, &f... | 1 | 14 | 14 |
94944d20576759deadb6415d80e95e4a346bc2b6 | Jakob Stoklund Olesen | 2017-05-11T18:25:35 | Keep dead EBB arguments around in LiveValueTracker::ebb_top().
Provide a drop_dead_args() function which deletes them instead.
We still need to assign a register to dead EBB arguments, so they can't
just be ignored. | diff --git a/lib/cretonne/src/ir/layout.rs b/lib/cretonne/src/ir/layout.rs
index b8ef83e75..abf0f3f48 100644
--- a/lib/cretonne/src/ir/layout.rs
+++ b/lib/cretonne/src/ir/layout.rs
@@ -435,6 +435,11 @@ impl Layout {
self.assign_inst_seq(inst);
}
+ /// Fetch an ebb's first instruction.
+ pub fn fir... | 3 | 46 | 12 |
2c0d4136b0f87beb407256f4cb505d5f321bbe31 | Jakob Stoklund Olesen | 2017-05-11T18:03:18 | Propagate a few more LiveRange properties to LiveValue.
The live value tracker goes through the trouble of looking up the live
range for each value it tracks. We can cache a few more interesting
properties from the live range in the LiveValue struct. | diff --git a/lib/cretonne/src/regalloc/live_value_tracker.rs b/lib/cretonne/src/regalloc/live_value_tracker.rs
index 4ef7df8d3..76e2fcb0d 100644
--- a/lib/cretonne/src/regalloc/live_value_tracker.rs
+++ b/lib/cretonne/src/regalloc/live_value_tracker.rs
@@ -11,6 +11,7 @@ use ir::{Inst, Ebb, Value, DataFlowGraph, Program... | 1 | 15 | 6 |
fb9d86f8522ea5f872ba0ffdb8f5a768819984ed | Dan Gohman | 2017-05-11T13:27:13 | Fix rustfmt diffs. | diff --git a/cranelift/src/filetest/legalizer.rs b/cranelift/src/filetest/legalizer.rs
index aa6385c22..806730b4e 100644
--- a/cranelift/src/filetest/legalizer.rs
+++ b/cranelift/src/filetest/legalizer.rs
@@ -4,7 +4,7 @@
//! the result to filecheck.
use std::borrow::Cow;
-use cretonne::{self};
+use cretonne;
use c... | 2 | 2 | 2 |
526feb161a682ad681d395a0bf34d8ba4be5a379 | Dan Gohman | 2017-05-11T13:27:13 | Fix rustfmt diffs. | diff --git a/src/filetest/legalizer.rs b/src/filetest/legalizer.rs
index aa6385c22..806730b4e 100644
--- a/src/filetest/legalizer.rs
+++ b/src/filetest/legalizer.rs
@@ -4,7 +4,7 @@
//! the result to filecheck.
use std::borrow::Cow;
-use cretonne::{self};
+use cretonne;
use cretonne::ir::Function;
use cton_reader:... | 2 | 2 | 2 |
ad9a942f5266a76eef3d458f1915f6dfb699f1c8 | Dan Gohman | 2017-05-10T21:58:14 | Use write! in utility code, rather than calling write_function directly. | diff --git a/cranelift/src/filetest/legalizer.rs b/cranelift/src/filetest/legalizer.rs
index 8fd7f45b1..aa6385c22 100644
--- a/cranelift/src/filetest/legalizer.rs
+++ b/cranelift/src/filetest/legalizer.rs
@@ -4,10 +4,11 @@
//! the result to filecheck.
use std::borrow::Cow;
-use cretonne::{self, write_function};
+us... | 3 | 8 | 6 |
c571975a5c95d61fa61a91e5bcd1c3b051d16f1d | Dan Gohman | 2017-05-10T21:58:14 | Use write! in utility code, rather than calling write_function directly. | diff --git a/src/filetest/legalizer.rs b/src/filetest/legalizer.rs
index 8fd7f45b1..aa6385c22 100644
--- a/src/filetest/legalizer.rs
+++ b/src/filetest/legalizer.rs
@@ -4,10 +4,11 @@
//! the result to filecheck.
use std::borrow::Cow;
-use cretonne::{self, write_function};
+use cretonne::{self};
use cretonne::ir::F... | 3 | 8 | 6 |
6b4c28d554dc849557101782cbda9854cc632c1a | Jakob Stoklund Olesen | 2017-04-28T22:41:28 | Use a constraint solver for register coloring.
Most of the time, register coloring is almost trivial: just pick
available registers for the values defined by the current instruction.
However, some instructions have register operand constraints, and it may
be necessary to move live registers around to satisfy the const... | diff --git a/lib/cretonne/src/isa/encoding.rs b/lib/cretonne/src/isa/encoding.rs
index 93888b109..b5062d988 100644
--- a/lib/cretonne/src/isa/encoding.rs
+++ b/lib/cretonne/src/isa/encoding.rs
@@ -104,7 +104,7 @@ pub struct EncInfo {
impl EncInfo {
/// Get the value operand constraints for `enc` if it is a lega... | 4 | 760 | 102 |
2873019779365118ae6f034f4830850de4d79d87 | Jakob Stoklund Olesen | 2017-05-02T20:48:19 | Add a register diversion tracker.
Keep track of the current location of register values as regmove
instructions are encountered throughout an EBB. | diff --git a/lib/cretonne/src/regalloc/diversion.rs b/lib/cretonne/src/regalloc/diversion.rs
new file mode 100644
index 000000000..2096af872
--- /dev/null
+++ b/lib/cretonne/src/regalloc/diversion.rs
@@ -0,0 +1,114 @@
+//! Register diversions.
+//!
+//! Normally, a value is assigned to a single register or stack locati... | 2 | 116 | 0 |
402e437a4aaf2d0fe551962d1d996e32dfcb5eb8 | Jakob Stoklund Olesen | 2017-05-08T20:57:39 | Also return live-through values from process_inst().
The coloring algorithm will need to look at the live-through values to
check if they interfere with fixed-register outputs for calls etc. | diff --git a/lib/cretonne/src/regalloc/coloring.rs b/lib/cretonne/src/regalloc/coloring.rs
index a1b389957..f664c43c4 100644
--- a/lib/cretonne/src/regalloc/coloring.rs
+++ b/lib/cretonne/src/regalloc/coloring.rs
@@ -276,7 +276,7 @@ impl<'a> Context<'a> {
locations: &mut EntityMap<Value, ValueLoc>) {... | 2 | 16 | 7 |
f8a3a01f96d126d8550a2ab04bf451953a12ca63 | Jakob Stoklund Olesen | 2017-05-02T16:59:58 | Add a few register utilities. | diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 76fd39685..122dec8e7 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -151,6 +151,11 @@ impl RegClassData {
let uoffset = offset * self.width as usize;
self.first + uoffset... | 3 | 51 | 1 |
aaa70a677d3604ee90d03ef240710bab4137752b | Jakob Stoklund Olesen | 2017-05-08T19:20:35 | Add a regs_overlap function to the isa module.
Test it with the arm32 register banks which have the most interesting
properties. Most other registers have a single register unit. | diff --git a/lib/cretonne/src/isa/arm32/registers.rs b/lib/cretonne/src/isa/arm32/registers.rs
index 69571976c..283f113d1 100644
--- a/lib/cretonne/src/isa/arm32/registers.rs
+++ b/lib/cretonne/src/isa/arm32/registers.rs
@@ -6,7 +6,7 @@ include!(concat!(env!("OUT_DIR"), "/registers-arm32.rs"));
#[cfg(test)]
mod tes... | 3 | 47 | 2 |
71128611a711ad9820ff65540beedbad0fdeab47 | Jakob Stoklund Olesen | 2017-04-28T00:39:58 | Extract the topological ordering into a module.
Multiple passes will need to iterate over EBBs in a
dominator-topological order. Move that functionality into a separate
module. | diff --git a/lib/cretonne/src/lib.rs b/lib/cretonne/src/lib.rs
index 986c45355..1f51b38d3 100644
--- a/lib/cretonne/src/lib.rs
+++ b/lib/cretonne/src/lib.rs
@@ -35,4 +35,5 @@ mod packed_option;
mod partition_slice;
mod predicates;
mod ref_slice;
+mod topo_order;
mod write;
diff --git a/lib/cretonne/src/regalloc/col... | 4 | 144 | 46 |
9db131c3bffc9a02ffc7d6d6e3ed2ff9ac27ddc1 | Jakob Stoklund Olesen | 2017-04-25T22:40:06 | Rename Affinity::Any to Affinity::None.
This value affinity doesn't mean "whatever", it means that the value
does not interact with any real instructions, where "real" means
instructions that have a legal encoding.
Update the liveness verifier to check this property:
- Encoded instructions can only use real values.
... | diff --git a/lib/cretonne/src/regalloc/affinity.rs b/lib/cretonne/src/regalloc/affinity.rs
index f6ca58748..64d2b640d 100644
--- a/lib/cretonne/src/regalloc/affinity.rs
+++ b/lib/cretonne/src/regalloc/affinity.rs
@@ -15,8 +15,11 @@ use isa::{TargetIsa, RegInfo, RegClassIndex, OperandConstraint, ConstraintKind};
/// Pr... | 3 | 53 | 8 |
2f81fbdb7779ca4500cf668129df82e54ea489b2 | Jakob Stoklund Olesen | 2017-04-26T18:15:46 | Add an Affinity::display() method.
Make it possible to display affinities given a RegInfo reference. | diff --git a/lib/cretonne/src/isa/registers.rs b/lib/cretonne/src/isa/registers.rs
index 864b950f6..3c4f1b411 100644
--- a/lib/cretonne/src/isa/registers.rs
+++ b/lib/cretonne/src/isa/registers.rs
@@ -153,6 +153,12 @@ impl RegClassData {
}
}
+impl fmt::Display for RegClassData {
+ fn fmt(&self, f: &mut fmt::... | 2 | 37 | 0 |
a20ae9eade83c307c7719fb66311bd21dd7561fd | Jakob Stoklund Olesen | 2017-04-26T17:47:43 | Assign an affinity to function argument values.
Use the argument types from the function signature to initialize the
affinity of register and stack arguments. | diff --git a/lib/cretonne/src/regalloc/affinity.rs b/lib/cretonne/src/regalloc/affinity.rs
index 529828759..f56b96d43 100644
--- a/lib/cretonne/src/regalloc/affinity.rs
+++ b/lib/cretonne/src/regalloc/affinity.rs
@@ -8,7 +8,8 @@
//! subclass. This is just a hint, and the register allocator is allowed to pick a registe... | 2 | 24 | 7 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.