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#!/usr/bin/python
# convert LLVM GenInstrInfo.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenInstrInfo.inc> <arch>" %sys.argv[0])
sys.exit(1)
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# return (arch, mnem)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
if arch.upper() == 'AArch64':
arch = 'ARM64'
return (arch, insn_mnem)
# get (arch, first insn) from MatchTable
def get_first_insn(filename):
f = open(filename)
lines = f.readlines()
f.close()
count = 0
for line in lines:
line = line.strip()
if len(line) == 0:
continue
# Intel syntax in Table1
if 'MatchEntry MatchTable1[] = {' in line:
count += 1
#print(line.strip())
continue
if count == 1:
arch, mnem = extract_insn(line)
return (arch, mnem)
return (None, None)
#arch, first_insn = get_first_insn(sys.argv[2])
#first_insn = first_insn.upper()
#print(arch, first_insn)
arch = sys.argv[2].upper()
if arch.upper() == 'AARCH64':
arch = 'AArch64'
elif arch.upper() == 'ARM64':
arch = 'AArch64'
print("""
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Instruction Enum Values and Descriptors *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
""")
enum_count = 0
f = open(sys.argv[1])
lines = f.readlines()
f.close()
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
print(line.strip())
continue
line = line.strip()
if enum_count == 1:
if line == '};':
# done with first enum
break
else:
# skip pseudo instructions
if '__' in line or 'setjmp' in line or 'longjmp' in line or 'Pseudo' in line:
pass
else:
print("\t%s_%s" %(arch, line))
print('};\n')
print("#endif // GET_INSTRINFO_ENUM")
if arch == 'ARM64':
sys.exit(0)
print("")
print("#ifdef GET_INSTRINFO_MC_DESC")
print("#undef GET_INSTRINFO_MC_DESC")
print("")
print("#define nullptr 0")
print("")
in_insts = False
for line in lines:
if line.strip() == '':
continue
line = line.rstrip()
if 'static const MCOperandInfo ' in line:
line2 = line.replace('::', '_')
print(line2)
elif 'Insts[] = {' in line:
# extern const MCInstrDesc ARMInsts[] = {
line2 = line.replace('extern const ', 'static const ')
print("")
print(line2)
in_insts = True
elif in_insts:
if line == '};':
print(line)
break
# { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
# take 2nd & 10th entries
tmp = line.split(',')
print(" { %s, %s }," %(tmp[1].strip(), tmp[9].strip()))
print("")
print("#endif // GET_INSTRINFO_MC_DESC")
#static const MCInstrDesc ARMInsts[] = {
#static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/instrinfo-arch.py
|
#!/usr/bin/python
# print list of instructions LLVM inc files, for Capstone disassembler.
# this will be put into capstone/<arch>.h
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenAsmMatcher.inc> <GenInstrInfo.inc> MappingInsn.inc" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[3])
mapping = f.readlines()
f.close()
print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
""")
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# extract insn from GenAsmMatcher Table
# return (arch, mnem, insn_id)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
if arch.upper() == 'AARCH64':
arch = 'ARM64'
return (arch, insn_mnem, tmp[1])
# extract all insn lines from GenAsmMatcher
# return arch, insn_id_list, insn_lines
def extract_matcher(filename):
f = open(filename)
lines = f.readlines()
f.close()
match_count = 0
count = 0
#insn_lines = []
insn_id_list = {}
arch = None
first_insn = None
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if 'MatchEntry MatchTable1[] = {' in line.strip():
match_count += 1
#print(line.strip())
continue
line = line.strip()
if match_count == 1:
count += 1
if line == '};':
# done with first enum
break
else:
_arch, mnem, insn_id = extract_insn(line)
if count == 1:
arch, first_insn = _arch, insn_id
if not insn_id in insn_id_list:
# print("***", arch, mnem, insn_id)
insn_id_list[insn_id] = mnem
#insn_lines.append(line)
#return arch, first_insn, insn_id_list, insn_lines
return arch, first_insn, insn_id_list
#arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1])
arch, first_insn, insn_id_list = extract_matcher(sys.argv[1])
arch = arch.upper()
#for line in insn_id_list:
# print(line)
insn_list = []
#{
# X86_AAA, X86_INS_AAA,
##ifndef CAPSTONE_DIET
# { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
##endif
#},
def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong):
if not mnem_can_be_wrong:
insn = "%s_INS_%s" %(arch.upper(), mnem.upper())
if insn in insn_list:
return
print('\t"%s", // %s' %(mnem.lower(), insn))
insn_list.append(insn)
return
insn = "%s_%s" %(arch.upper(), insn_id)
# so mnem can be wrong, we need to verify with MappingInsn.inc
# first, try to find this entry in old MappingInsn.inc file
for i in range(len(mapping)):
tmp = mapping[i].split(',')
if tmp[0].strip() == insn:
insn = tmp[1].strip()
if insn in insn_list:
return
mnem = insn[len("%s_INS_" %(arch)):]
#print("==== get below from MappingInsn.inc file: %s" %insn)
print('\t"%s", // %s' %(mnem.lower(), insn))
insn_list.append(insn)
return
# extract from GenInstrInfo.inc, because the insn id is in order
enum_count = 0
meet_insn = False
f = open(sys.argv[2])
lines = f.readlines()
f.close()
count = 0
last_mnem = None
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
#print(line.strip())
continue
line = line.strip()
if enum_count == 1:
if 'INSTRUCTION_LIST_END' in line:
break
else:
insn = None
if meet_insn:
# enum items
insn = line.split('=')[0].strip()
if 'CALLSTACK' in insn or 'TAILJUMP' in insn:
# pseudo instruction
insn = None
elif line.startswith(first_insn):
insn = line.split('=')[0].strip()
meet_insn = True
if insn:
count += 1
if insn == 'BSWAP16r_BAD':
last_mnem = 'BSWAP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp32':
last_mnem = 'FCMOVNP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVP_Fp3':
last_mnem = 'FCMOVP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrm_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVSX16rm16':
last_mnem = 'MOVSX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVZX16rm16':
last_mnem = 'MOVZX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'ST_Fp32m':
last_mnem = 'FST'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp64':
last_mnem = 'FCMOVNU'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrr_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSSrm_Int':
last_mnem = 'CMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSDrm_Int':
last_mnem = 'VCMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSSrm_Int':
last_mnem = 'VCMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPCMOVYrrr_REV':
last_mnem = 'VPCMOV'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESDZm':
last_mnem = 'VRNDSCALESD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESSZm':
last_mnem = 'VRNDSCALESS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPDZ128rm':
last_mnem = 'VMAXPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPSZ128rm':
last_mnem = 'VMAXPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSDZrm':
last_mnem = 'VMAXSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSSZrm':
last_mnem = 'VMAXSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPDZ128rm':
last_mnem = 'VMINPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPSZ128rm':
last_mnem = 'VMINPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSDZrm':
last_mnem = 'VMINSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSSZrm':
last_mnem = 'VMINSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMOV64toPQIZrm':
last_mnem = 'VMOVQ'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PDYrr_REV':
last_mnem = 'VPERMILPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PSYrr_REV':
last_mnem = 'VPERMILPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SI64Zrm_Int':
last_mnem = 'VCVTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SSrm_Int':
last_mnem = 'VCVTSD2SS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSS2SI64Zrm_Int':
last_mnem = 'VCVTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSD2SI64Zrm_Int':
last_mnem = 'VCVTTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSS2SI64Zrm_Int':
last_mnem = 'VCVTTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUBADD'):
if insn[len('VFMSUBADD')].isdigit():
last_mnem = insn[:len('VFMSUBADD123xy')]
else:
last_mnem = insn[:len('VFMSUBADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADDSUB'):
if insn[len('VFMADDSUB')].isdigit():
last_mnem = insn[:len('VFMADDSUB123xy')]
else:
last_mnem = insn[:len('VFMADDSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADD'):
if insn[len('VFMADD')].isdigit():
last_mnem = insn[:len('VFMADD123PD')]
else:
last_mnem = insn[:len('VFMADDPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUB'):
if insn[len('VFMSUB')].isdigit():
last_mnem = insn[:len('VFMSUB123PD')]
else:
last_mnem = insn[:len('VFMSUBPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMADD'):
if insn[len('VFNMADD')].isdigit():
last_mnem = insn[:len('VFNMADD123xy')]
else:
last_mnem = insn[:len('VFNMADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMSUB'):
if insn[len('VFNMSUB')].isdigit():
last_mnem = insn[:len('VFNMSUB123xy')]
else:
last_mnem = insn[:len('VFNMSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn in insn_id_list:
# trust old mapping table
last_mnem = insn_id_list[insn].upper()
print_entry(arch.upper(), insn, last_mnem, mapping, False)
else:
# the last option when we cannot find mnem: use the last good mnem
print_entry(arch.upper(), insn, last_mnem, mapping, True)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/mapping_insn_name.py
|
#!/usr/bin/python
# convert LLVM GenAsmWriter.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenAsmWriter.inc> <Output-GenAsmWriter.inc> <Output-GenRegisterName.inc> <arch>" %sys.argv[0])
sys.exit(1)
arch = sys.argv[4]
f = open(sys.argv[1])
lines = f.readlines()
f.close()
f1 = open(sys.argv[2], 'w+')
f2 = open(sys.argv[3], 'w+')
f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n")
f1.write("/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */\n")
f1.write("\n")
f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n")
f2.write("/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */\n")
f2.write("\n")
need_endif = False
in_getRegisterName = False
in_printAliasInstr = False
fragment_no = None
skip_printing = False
skip_line = 0
skip_count = 0
def replace_getOp(line):
line2 = line
if 'MI->getOperand(0)' in line:
line2 = line.replace('MI->getOperand(0)', 'MCInst_getOperand(MI, 0)')
elif 'MI->getOperand(1)' in line:
line2 = line.replace('MI->getOperand(1)', 'MCInst_getOperand(MI, 1)')
elif 'MI->getOperand(2)' in line:
line2 = line.replace('MI->getOperand(2)', 'MCInst_getOperand(MI, 2)')
elif 'MI->getOperand(3)' in line:
line2 = line.replace('MI->getOperand(3)', 'MCInst_getOperand(MI, 3)')
elif 'MI->getOperand(4)' in line:
line2 = line.replace('MI->getOperand(4)', 'MCInst_getOperand(MI, 4)')
elif 'MI->getOperand(5)' in line:
line2 = line.replace('MI->getOperand(5)', 'MCInst_getOperand(MI, 5)')
elif 'MI->getOperand(6)' in line:
line2 = line.replace('MI->getOperand(6)', 'MCInst_getOperand(MI, 6)')
elif 'MI->getOperand(7)' in line:
line2 = line.replace('MI->getOperand(7)', 'MCInst_getOperand(MI, 7)')
elif 'MI->getOperand(8)' in line:
line2 = line.replace('MI->getOperand(8)', 'MCInst_getOperand(MI, 8)')
return line2
def replace_getReg(line):
line2 = line
if 'MI->getOperand(0).getReg()' in line:
line2 = line.replace('MI->getOperand(0).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 0))')
elif 'MI->getOperand(1).getReg()' in line:
line2 = line.replace('MI->getOperand(1).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 1))')
elif 'MI->getOperand(2).getReg()' in line:
line2 = line.replace('MI->getOperand(2).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 2))')
elif 'MI->getOperand(3).getReg()' in line:
line2 = line.replace('MI->getOperand(3).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 3))')
elif 'MI->getOperand(4).getReg()' in line:
line2 = line.replace('MI->getOperand(4).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 4))')
elif 'MI->getOperand(5).getReg()' in line:
line2 = line.replace('MI->getOperand(5).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 5))')
elif 'MI->getOperand(6).getReg()' in line:
line2 = line.replace('MI->getOperand(6).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 6))')
elif 'MI->getOperand(7).getReg()' in line:
line2 = line.replace('MI->getOperand(7).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 7))')
elif 'MI->getOperand(8).getReg()' in line:
line2 = line.replace('MI->getOperand(8).getReg()', 'MCOperand_getReg(MCInst_getOperand(MI, 8))')
return line2
# extract param between text()
# MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()))
def extract_paren(line, text):
i = line.index(text)
return line[line.index('(', i)+1 : line.index(')', i)]
# extract text between <>
# printSVERegOp<'q'>
def extract_brackets(line):
if '<' in line:
return line[line.index('<')+1 : line.index('>')]
else:
return ''
# delete text between <>, including <>
# printSVERegOp<'q'>
def del_brackets(line):
if '<' in line:
return line[:line.index('<')] + line[line.index('>') + 1:]
else:
return line
def print_line(line):
line = line.replace('::', '_')
line = line.replace('nullptr', 'NULL')
if not skip_printing:
if in_getRegisterName:
f2.write(line + "\n")
else:
f1.write(line + "\n")
for line in lines:
line = line.rstrip()
#print("@", line)
# skip Alias
if arch.upper() == 'X86':
if 'PRINT_ALIAS_INSTR' in line:
# done
break
if skip_line:
skip_count += 1
if skip_count <= skip_line:
# skip this line
continue
else:
# skip enough number of lines, reset counters
skip_line = 0
skip_count = 0
if "::printInstruction" in line:
if arch.upper() in ('AARCH64', 'ARM64'):
#print_line("static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)\n{")
print_line("static void printInstruction(MCInst *MI, SStream *O)\n{")
else:
print_line("static void printInstruction(MCInst *MI, SStream *O)\n{")
elif 'const char *AArch64InstPrinter::' in line:
continue
elif 'getRegisterName(' in line:
if 'unsigned AltIdx' in line:
print_line("static const char *getRegisterName(unsigned RegNo, unsigned AltIdx)\n{")
else:
print_line("static const char *getRegisterName(unsigned RegNo)\n{")
elif 'getRegisterName' in line:
in_getRegisterName = True
print_line(line)
elif '::printAliasInstr' in line:
if arch.upper() in ('AARCH64', 'PPC'):
print_line("static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI)\n{")
print_line(' #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))')
else:
print_line("static bool printAliasInstr(MCInst *MI, SStream *OS)\n{")
print_line(" unsigned int I = 0, OpIdx, PrintMethodIdx;")
print_line(" char *tmpString;")
in_printAliasInstr = True
elif 'STI.getFeatureBits()[' in line:
if arch.upper() == 'ARM':
line2 = line.replace('STI.getFeatureBits()[', 'ARM_getFeatureBits(MI->csh->mode, ')
elif arch.upper() == 'AARCH64':
line2 = line.replace('STI.getFeatureBits()[', 'AArch64_getFeatureBits(')
line2 = line2.replace(']', ')')
print_line(line2)
elif ', STI, ' in line:
line2 = line.replace(', STI, ', ', ')
if 'printSVELogicalImm<' in line:
if 'int16' in line:
line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm16')
line2 = line2.replace('<int16_t>', '')
elif 'int32' in line:
line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm32')
line2 = line2.replace('<int32_t>', '')
else:
line2 = line2.replace('printSVELogicalImm', 'printSVELogicalImm64')
line2 = line2.replace('<int64_t>', '')
if 'MI->getOperand(' in line:
line2 = replace_getOp(line2)
# C++ template
if 'printPrefetchOp' in line2:
param = extract_brackets(line2)
if param == '':
param = 'false'
line2 = del_brackets(line2)
line2 = line2.replace(', O);', ', O, %s);' %param)
line2 = line2.replace(', OS);', ', OS, %s);' %param)
elif '<false>' in line2:
line2 = line2.replace('<false>', '')
line2 = line2.replace(', O);', ', O, false);')
line2 = line2.replace('STI, ', '')
elif '<true>' in line:
line2 = line2.replace('<true>', '')
line2 = line2.replace(', O);', ', O, true);')
line2 = line2.replace('STI, ', '')
elif 'printAdrLabelOperand' in line:
# C++ template
if '<0>' in line:
line2 = line2.replace('<0>', '')
line2 = line2.replace(', O);', ', O, 0);')
elif '<1>' in line:
line2 = line2.replace('<1>', '')
line2 = line2.replace(', O);', ', O, 1);')
elif '<2>' in line:
line2 = line2.replace('<2>', '')
line2 = line2.replace(', O);', ', O, 2);')
elif 'printImm8OptLsl' in line2:
param = extract_brackets(line2)
line2 = del_brackets(line2)
if '8' in param or '16' in param or '32' in param:
line2 = line2.replace('printImm8OptLsl', 'printImm8OptLsl32')
elif '64' in param:
line2 = line2.replace('printImm8OptLsl', 'printImm8OptLsl64')
elif 'printLogicalImm' in line2:
param = extract_brackets(line2)
line2 = del_brackets(line2)
if '8' in param or '16' in param or '32' in param:
line2 = line2.replace('printLogicalImm', 'printLogicalImm32')
elif '64' in param:
line2 = line2.replace('printLogicalImm', 'printLogicalImm64')
elif 'printSVERegOp' in line2 or 'printGPRSeqPairsClassOperand' in line2 or 'printTypedVectorList' in line2 or 'printPostIncOperand' in line2 or 'printImmScale' in line2 or 'printRegWithShiftExtend' in line2 or 'printUImm12Offset' in line2 or 'printExactFPImm' in line2 or 'printMemExtend' in line2 or 'printZPRasFPR' in line2:
param = extract_brackets(line2)
if param == '':
param = '0'
line2 = del_brackets(line2)
line2 = line2.replace(', O);', ', O, %s);' %param)
line2 = line2.replace(', OS);', ', OS, %s);' %param)
elif 'printComplexRotationOp' in line:
# printComplexRotationOp<90, 0>(MI, 5, STI, O);
bracket_content = line2[line2.index('<') + 1 : line2.index('>')]
line2 = line2.replace('<' + bracket_content + '>', '')
line2 = line2.replace(' O);', ' O, %s);' %bracket_content)
print_line(line2)
elif "static const char AsmStrs[]" in line:
print_line("#ifndef CAPSTONE_DIET")
print_line(" static const char AsmStrs[] = {")
need_endif = True
elif "static const char AsmStrsNoRegAltName[]" in line:
print_line("#ifndef CAPSTONE_DIET")
print_line(" static const char AsmStrsNoRegAltName[] = {")
need_endif = True
elif line == ' O << "\\t";':
print_line(" unsigned int opcode = MCInst_getOpcode(MI);")
print_line(' // printf("opcode = %u\\n", opcode);');
elif 'MI->getOpcode()' in line:
if 'switch' in line:
line2 = line.replace('MI->getOpcode()', 'MCInst_getOpcode(MI)')
else:
line2 = line.replace('MI->getOpcode()', 'opcode')
print_line(line2)
elif 'O << ' in line:
if '"' in line:
line2 = line.lower()
line2 = line2.replace('o << ', 'SStream_concat0(O, ');
else:
line2 = line.replace('O << ', 'SStream_concat0(O, ');
line2 = line2.replace("'", '"')
line2 = line2.replace(';', ');')
if '" : "' in line2: # "segment : offset" in X86
line2 = line2.replace('" : "', '":"')
# ARM
print_line(line2)
if '", #0"' in line2:
print_line(' op_addImm(MI, 0);')
if '", #1"' in line2:
print_line(' op_addImm(MI, 1);')
# PowerPC
if '", 268"' in line2:
print_line(' op_addImm(MI, 268);')
elif '", 256"' in line2:
print_line(' op_addImm(MI, 256);')
elif '", 0, "' in line2 or '", 0"' in line2:
print_line(' op_addImm(MI, 0);')
elif '", -1"' in line2:
print_line(' op_addImm(MI, -1);')
if '[' in line2:
if not '[]' in line2:
print_line(' set_mem_access(MI, true);')
if ']' in line2:
if not '[]' in line2:
print_line(' set_mem_access(MI, false);')
if '".f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64);')
elif '".f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32);')
elif '".f16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16);')
elif '".s64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S64);')
elif '".s32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32);')
elif '".s16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16);')
elif '".s8\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S8);')
elif '".u64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U64);')
elif '".u32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32);')
elif '".u16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16);')
elif '".u8\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U8);')
elif '".i64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I64);')
elif '".i32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I32);')
elif '".i16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I16);')
elif '".i8\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_I8);')
elif '".f16.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64);')
elif '".f64.f16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16);')
elif '".f16.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32);')
elif '".f32.f16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16);')
elif '".f64.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32);')
elif '".f32.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64);')
elif '".s32.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32);')
elif '".f32.s32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32);')
elif '".u32.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32);')
elif '".f32.u32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32);')
elif '".p8\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_P8);')
elif '".f64.s16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16);')
elif '".s16.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64);')
elif '".f32.s16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16);')
elif '".s16.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32);')
elif '".f64.s32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32);')
elif '".s32.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64);')
elif '".f64.u16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16);')
elif '".u16.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64);')
elif '".f32.u16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16);')
elif '".u16.f32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32);')
elif '".f64.u32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32);')
elif '".u32.f64\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64);')
elif '".f16.u32\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32);')
elif '".u32.f16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16);')
elif '".f16.u16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16);')
elif '".u16.f16\\t"' in line2:
print_line(' ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16);')
elif '"\\tlr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_LR);')
elif '"\\tapsr_nzcv, fpscr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_APSR_NZCV);')
print_line(' ARM_addReg(MI, ARM_REG_FPSCR);')
elif '"\\tpc, lr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_PC);')
print_line(' ARM_addReg(MI, ARM_REG_LR);')
elif '"\\tfpscr, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPSCR);')
elif '"\\tfpexc, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPEXC);')
elif '"\\tfpinst, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPINST);')
elif '"\\tfpinst2, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPINST2);')
elif '"\\tfpsid, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPSID);')
elif '"\\tsp, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_SP);')
elif '"\\tsp!, "' in line2:
print_line(' ARM_addReg(MI, ARM_REG_SP);')
elif '", apsr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_APSR);')
elif '", spsr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_SPSR);')
elif '", fpscr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPSCR);')
elif '", fpscr"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPSCR);')
elif '", fpexc"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPEXC);')
elif '", fpinst"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPINST);')
elif '", fpinst2"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPINST2);')
elif '", fpsid"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_FPSID);')
elif '", mvfr0"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_MVFR0);')
elif '", mvfr1"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_MVFR1);')
elif '", mvfr2"' in line2:
print_line(' ARM_addReg(MI, ARM_REG_MVFR2);')
elif '.8\\t' in line2:
print_line(' ARM_addVectorDataSize(MI, 8);')
elif '.16\\t' in line2:
print_line(' ARM_addVectorDataSize(MI, 16);')
elif '.32\\t' in line2:
print_line(' ARM_addVectorDataSize(MI, 32);')
elif '.64\\t' in line2:
print_line(' ARM_addVectorDataSize(MI, 64);')
elif '" ^"' in line2:
print_line(' ARM_addUserMode(MI);')
if '.16b' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B);')
elif '.8b' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B);')
elif '.4b' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4B);')
elif '.b' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B);')
elif '.8h' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H);')
elif '.4h' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H);')
elif '.2h' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H);')
elif '.h' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H);')
elif '.4s' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S);')
elif '.2s' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S);')
elif '.s' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S);')
elif '.2d' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D);')
elif '.1d' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D);')
elif '.1q' in line2:
print_line(' arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q);')
if '#0.0' in line2:
print_line(' arm64_op_addFP(MI, 0);')
elif '#0' in line2:
print_line(' arm64_op_addImm(MI, 0);')
elif '#8' in line2:
print_line(' arm64_op_addImm(MI, 8);')
elif '#16' in line2:
print_line(' arm64_op_addImm(MI, 16);')
elif '#32' in line2:
print_line(' arm64_op_addImm(MI, 32);')
# X86
if '", %rax"' in line2 or '", rax"' in line2:
print_line(' op_addReg(MI, X86_REG_RAX);')
elif '", %eax"' in line2 or '", eax"' in line2:
print_line(' op_addReg(MI, X86_REG_EAX);')
elif '", %ax"' in line2 or '", ax"' in line2:
print_line(' op_addReg(MI, X86_REG_AX);')
elif '", %al"' in line2 or '", al"' in line2:
print_line(' op_addReg(MI, X86_REG_AL);')
elif '", %dx"' in line2 or '", dx"' in line2:
print_line(' op_addReg(MI, X86_REG_DX);')
elif '", %st(0)"' in line2 or '", st(0)"' in line2:
print_line(' op_addReg(MI, X86_REG_ST0);')
elif '", 1"' in line2:
print_line(' op_addImm(MI, 1);')
elif '", cl"' in line2:
print_line(' op_addReg(MI, X86_REG_CL);')
elif '"{1to2}, "' in line2:
print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_2);')
elif '"{1to4}, "' in line2:
print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_4);')
elif '"{1to8}, "' in line2:
print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_8);')
elif '"{1to16}, "' in line2:
print_line(' op_addAvxBroadcast(MI, X86_AVX_BCAST_16);')
elif '{z}{sae}' in line2:
print_line(' op_addAvxSae(MI);')
print_line(' op_addAvxZeroOpmask(MI);')
elif ('{z}' in line2):
print_line(' op_addAvxZeroOpmask(MI);')
elif '{sae}' in line2:
print_line(' op_addAvxSae(MI);')
elif 'llvm_unreachable("Invalid command number.");' in line:
line2 = line.replace('llvm_unreachable("Invalid command number.");', '// unreachable')
print_line(line2)
elif ('assert(' in line) or ('assert (' in line):
pass
elif 'Invalid alt name index' in line:
pass
elif '::' in line and 'case ' in line:
#print_line(line2)
print_line(line)
elif 'MI->getNumOperands()' in line:
line2 = line.replace('MI->getNumOperands()', 'MCInst_getNumOperands(MI)')
print_line(line2)
elif 'const MCOperand &MCOp' in line:
line2 = line.replace('const MCOperand &MCOp', 'MCOperand *MCOp')
print_line(line2)
elif 'MI->getOperand(0).isImm()' in line:
line2 = line.replace('MI->getOperand(0).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 0))')
print_line(line2)
elif 'MI->getOperand(1).isImm()' in line:
line2 = line.replace('MI->getOperand(1).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 1))')
print_line(line2)
elif 'MI->getOperand(2).isImm()' in line:
line2 = line.replace('MI->getOperand(2).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 2))')
print_line(line2)
elif 'MI->getOperand(3).isImm()' in line:
line2 = line.replace('MI->getOperand(3).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 3))')
print_line(line2)
elif 'MI->getOperand(4).isImm()' in line:
line2 = line.replace('MI->getOperand(4).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 4))')
print_line(line2)
elif 'MI->getOperand(5).isImm()' in line:
line2 = line.replace('MI->getOperand(5).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 5))')
print_line(line2)
elif 'MI->getOperand(6).isImm()' in line:
line2 = line.replace('MI->getOperand(6).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 6))')
print_line(line2)
elif 'MI->getOperand(7).isImm()' in line:
line2 = line.replace('MI->getOperand(7).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 7))')
print_line(line2)
elif 'MI->getOperand(8).isImm()' in line:
line2 = line.replace('MI->getOperand(8).isImm()', 'MCOperand_isImm(MCInst_getOperand(MI, 8))')
print_line(line2)
elif 'MI->getOperand(0).getImm()' in line:
line2 = line.replace('MI->getOperand(0).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 0))')
print_line(line2)
elif 'MI->getOperand(1).getImm()' in line:
line2 = line.replace('MI->getOperand(1).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 1))')
print_line(line2)
elif 'MI->getOperand(2).getImm()' in line:
line2 = line.replace('MI->getOperand(2).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 2))')
print_line(line2)
elif 'MI->getOperand(3).getImm()' in line:
line2 = line.replace('MI->getOperand(3).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 3))')
print_line(line2)
elif 'MI->getOperand(4).getImm()' in line:
line2 = line.replace('MI->getOperand(4).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 4))')
print_line(line2)
elif 'MI->getOperand(5).getImm()' in line:
line2 = line.replace('MI->getOperand(5).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 5))')
print_line(line2)
elif 'MI->getOperand(6).getImm()' in line:
line2 = line.replace('MI->getOperand(6).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 6))')
print_line(line2)
elif 'MI->getOperand(7).getImm()' in line:
line2 = line.replace('MI->getOperand(7).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 7))')
print_line(line2)
elif 'MI->getOperand(8).getImm()' in line:
line2 = line.replace('MI->getOperand(8).getImm()', 'MCOperand_getImm(MCInst_getOperand(MI, 8))')
print_line(line2)
elif 'MRI.getRegClass(' in line:
classid = extract_paren(line, 'getRegClass(')
operand = extract_paren(line, 'getOperand')
line2 = line.replace('MI->getNumOperands()', 'MCInst_getNumOperands(MI)')
line2 = ' GETREGCLASS_CONTAIN(%s, %s)' %(classid, operand)
if line.endswith('())) {'):
line2 += ') {'
elif line.endswith(' {'):
line2 += ' {'
elif line.endswith(' &&'):
line2 += ' &&'
print_line(line2)
elif 'MI->getOperand(' in line and 'isReg' in line:
operand = extract_paren(line, 'getOperand')
line2 = ' MCOperand_isReg(MCInst_getOperand(MI, %s))' %(operand)
# MI->getOperand(1).isReg() &&
if line.endswith(' {'):
line2 += ' {'
elif line.endswith(' &&'):
line2 += ' &&'
print_line(line2)
elif 'MI->getOperand(' in line and 'getReg' in line:
line2 = replace_getReg(line)
# one more time
line2 = replace_getReg(line2)
print_line(line2)
elif ' return false;' in line and in_printAliasInstr:
print_line(' return NULL;')
elif 'MCOp.isImm()' in line:
line2 = line.replace('MCOp.isImm()', 'MCOperand_isImm(MCOp)')
print_line(line2)
elif 'MCOp.getImm()' in line:
line2 = line.replace('MCOp.getImm()', 'MCOperand_getImm(MCOp)')
if 'int64_t Val =' in line:
line2 = line2.replace('int64_t Val =', 'Val =')
print_line(line2)
elif 'isSVEMaskOfIdenticalElements<' in line:
if 'int8' in line:
line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements8')
line2 = line2.replace('<int8_t>', '')
elif 'int16' in line:
line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements16')
line2 = line2.replace('<int16_t>', '')
elif 'int32' in line:
line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements32')
line2 = line2.replace('<int32_t>', '')
else:
line2 = line.replace('isSVEMaskOfIdenticalElements', 'isSVEMaskOfIdenticalElements64')
line2 = line2.replace('<int64_t>', '')
print_line(line2)
elif 'switch (PredicateIndex) {' in line:
print_line(' int64_t Val;')
print_line(line)
elif 'unsigned I = 0;' in line and in_printAliasInstr:
print_line("""
tmpString = cs_strdup(AsmString);
while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&
AsmString[I] != '$' && AsmString[I] != '\\0')
++I;
tmpString[I] = 0;
SStream_concat0(OS, tmpString);
if (AsmString[I] != '\\0') {
if (AsmString[I] == ' ' || AsmString[I] == '\\t') {
SStream_concat0(OS, " ");
++I;
}
do {
if (AsmString[I] == '$') {
++I;
if (AsmString[I] == (char)0xff) {
++I;
OpIdx = AsmString[I++] - 1;
PrintMethodIdx = AsmString[I++] - 1;
printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
} else
printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
} else {
SStream_concat1(OS, AsmString[I++]);
}
} while (AsmString[I] != '\\0');
}
return tmpString;
}
""")
in_printAliasInstr = False
# skip next few lines
skip_printing = True
elif '::printCustomAliasOperand' in line:
# print again
skip_printing = False
print_line('static void printCustomAliasOperand(')
elif 'const MCSubtargetInfo &STI' in line:
pass
elif 'const MCInst *MI' in line:
line2 = line.replace('const MCInst *MI', 'MCInst *MI')
print_line(line2)
elif 'llvm_unreachable("' in line:
if 'default: ' in line:
print_line(' default:')
elif 'llvm_unreachable("Unknown MCOperandPredicate kind")' in line:
print_line(' return false; // never reach')
else:
pass
elif 'raw_ostream &' in line:
line2 = line.replace('raw_ostream &', 'SStream *')
if line2.endswith(' {'):
line2 = line2.replace(' {', '\n{')
print_line(line2)
elif 'printPredicateOperand(' in line and 'STI, ' in line:
line2 = line.replace('STI, ', '')
print_line(line2)
elif '// Fragment ' in line:
# // Fragment 0 encoded into 6 bits for 51 unique commands.
tmp = line.strip().split(' ')
fragment_no = tmp[2]
print_line(line)
elif ('switch ((' in line or 'if ((' in line) and 'Bits' in line:
# switch ((Bits >> 14) & 63) {
bits = line.strip()
bits = bits.replace('switch ', '')
bits = bits.replace('if ', '')
bits = bits.replace('{', '')
bits = bits.strip()
print_line(' // printf("Fragment %s: %%"PRIu64"\\n", %s);' %(fragment_no, bits))
print_line(line)
elif not skip_printing:
print_line(line)
if line == ' };':
if need_endif and not in_getRegisterName:
# endif only for AsmStrs when we are not inside getRegisterName()
print_line("#endif")
need_endif = False
elif 'return AsmStrs+RegAsmOffset[RegNo-1];' in line:
if in_getRegisterName:
# return NULL for register name on Diet mode
print_line("#else")
print_line(" return NULL;")
print_line("#endif")
print_line("}")
need_endif = False
in_getRegisterName = False
# skip 1 line
skip_line = 1
elif line == ' }':
# ARM64
if in_getRegisterName:
# return NULL for register name on Diet mode
print_line("#else")
print_line(" return NULL;")
print_line("#endif")
print_line("}")
need_endif = False
in_getRegisterName = False
# skip 1 line
skip_line = 1
elif 'default:' in line:
# ARM64
if in_getRegisterName:
# get the size of RegAsmOffsetvreg[]
print_line(" return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0]));")
f1.close()
f2.close()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/asmwriter.py
|
#!/usr/bin/python
# convert LLVM GenDisassemblerTables.inc for Capstone disassembler.
# this just adds a header
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenDisassemblerTables.inc> <arch>" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[1])
lines = f.readlines()
f.close()
print("/* Capstone Disassembly Engine, http://www.capstone-engine.org */")
print("/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */")
print("/* Automatically generated file, do not edit! */\n")
print('#include "../../MCInst.h"')
print('#include "../../LEB128.h"')
print("")
print("""
// Helper function for extracting fields from encoded instructions.
//#if defined(_MSC_VER) && !defined(__clang__)
//__declspec(noinline)
//#endif
#define FieldFromInstruction(fname, InsnType) \\
static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \\
{ \\
InsnType fieldMask; \\
if (numBits == sizeof(InsnType) * 8) \\
fieldMask = (InsnType)(-1LL); \\
else \\
fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \\
return (insn & fieldMask) >> startBit; \\
}
""")
# extract text between <>
# printSVERegOp<'q'>
def extract_brackets(line):
return line[line.index('<')+1 : line.index('>')]
# delete text between <>, including <>
# printSVERegOp<'q'>
def del_brackets(line):
return line[:line.index('<')] + line[line.index('>') + 1:]
# skip printing some lines?
skip_print = True
# adding slash at the end of the line for C macro?
adding_slash = False
# skip LLVM_DEBUG
llvm_debug = False
def print_line(line):
if skip_print is True:
return
if adding_slash:
# skip blank line
if (len(line.strip()) == 0):
return
# // must be handled
if '//' in line:
line = line.replace('//', '/*')
line += ' */'
print(line + ' \\')
else:
print(line)
for line in lines:
line2 = line.rstrip()
if '#include ' in line2:
continue
# skip until the first decoder table
elif skip_print and 'static const uint8_t DecoderTable' in line2:
skip_print = False
elif 'End llvm namespace' in line2:
# done
break
elif 'llvm_unreachable' in line2:
line2 = line2.replace('llvm_unreachable', '/* llvm_unreachable')
line2 += '*/ '
if '"Invalid index!"' in line2:
pass
#line2 += '\n return true;'
elif 'Bits[' in line2:
if sys.argv[2] == 'ARM':
line2 = line2.replace('Bits[', 'ARM_getFeatureBits(MI->csh->mode, ')
line2 = line2.replace(']', ')')
elif sys.argv[2] == 'AArch64':
line2 = line2.replace('Bits[', 'AArch64_getFeatureBits(')
line2 = line2.replace(']', ')')
elif 'static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset& Bits) {' in line2:
line2 = 'static bool checkDecoderPredicate(unsigned Idx, MCInst *MI)\n{'
elif 'checkDecoderPredicate(PIdx, ' in line2:
line2 = line2.replace(', Bits)', ', MI)')
elif 'template<typename InsnType>' in line2:
continue
elif 'static DecodeStatus decodeToMCInst' in line2:
line2 = '#define DecodeToMCInst(fname, fieldname, InsnType) \\\n' + \
'static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \\\n' + \
'\t\tuint64_t Address, bool *Decoder) \\\n{'
adding_slash = True
elif 'fieldFromInstruction' in line2:
line2 = line2.replace('fieldFromInstruction', 'fieldname')
if 'InsnType FieldValue' in line2:
line2 = line2.replace('InsnType ', '')
elif 'DecodeComplete = true;' in line2:
# dead code
continue
elif 'bool &DecodeComplete) {' in line2:
continue
elif line2 == '}':
if adding_slash:
adding_slash = False
elif 'static DecodeStatus decodeInstruction' in line2:
line2 = '#define DecodeInstruction(fname, fieldname, decoder, InsnType) \\\n' + \
'static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \\\n' + \
'\t\tInsnType insn, uint64_t Address) \\\n{ \\\n' + \
' unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \\\n' + \
' InsnType Val, FieldValue, PositiveMask, NegativeMask; \\\n' + \
' bool Pred, Fail, DecodeComplete = true; \\\n' + \
' uint32_t ExpectedValue;'
adding_slash = True
print_line(line2)
# skip printing few lines
skip_print = True
elif 'const MCSubtargetInfo &STI' in line2:
skip_print = False
# skip this line
continue
elif 'Bits = STI.getFeatureBits()' in line2:
# skip this line
continue
elif 'errs() << ' in line2:
continue
elif 'unsigned Start =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'unsigned Len =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'unsigned Len;' in line2:
continue
elif 'MCInst TmpMI;' in line2:
continue
elif 'bool Pred;' in line2:
continue
elif 'bool DecodeComplete;' in line2:
continue
elif 'unsigned NumToSkip =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'unsigned PIdx =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'unsigned Opc =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'unsigned DecodeIdx =' in line2:
line2 = line2.replace('unsigned ', '')
elif 'InsnType Val =' in line2:
line2 = line2.replace('InsnType ', '')
elif 'bool Fail' in line2:
line2 = line2.replace('bool ', '')
elif 'InsnType PositiveMask =' in line2:
line2 = line2.replace('InsnType ', '')
elif 'InsnType NegativeMask =' in line2:
line2 = line2.replace('InsnType ', '')
elif 'uint32_t ExpectedValue' in line2:
line2 = line2.replace('uint32_t ', '')
elif 'ptrdiff_t Loc = ' in line2:
continue
elif 'LLVM_DEBUG(' in line2:
# just this line?
if ');' in line2:
continue
skip_print = True
llvm_debug = True
continue
elif skip_print and llvm_debug and ');' in line2:
llvm_debug = False
skip_print = False
continue
elif 'decodeToMCInst(' in line2:
line2 = line2.replace('decodeToMCInst', 'decoder')
line2 = line2.replace('DecodeComplete);', '&DecodeComplete);')
line2 = line2.replace(', DisAsm', '')
line2 = line2.replace(', TmpMI', ', MI')
elif 'TmpMI.setOpcode(Opc);' in line2:
line2 = ' MCInst_setOpcode(MI, Opc);'
elif 'MI.setOpcode(Opc);' in line2:
line2 = ' MCInst_setOpcode(MI, Opc);'
elif 'MI.clear();' in line2:
line2 = ' MCInst_clear(MI);'
elif 'assert(' in line2:
line2 = line2.replace('assert(', '/* assert(')
line2 += ' */'
elif 'Check(S, ' in line2:
line2 = line2.replace('Check(S, ', 'Check(&S, ')
if 'DecodeImm8OptLsl<' in line2:
param = extract_brackets(line2)
line2 = del_brackets(line2)
line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param)
elif 'DecodeSImm<' in line2:
param = extract_brackets(line2)
line2 = del_brackets(line2)
line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param)
if 'DecodeComplete = false; ' in line2:
line2 = line2.replace('DecodeComplete = false; ', '')
elif 'decodeUImmOperand<' in line2 or 'decodeSImmOperand<' in line2 :
# decodeUImmOperand<5>(MI, tmp, Address, Decoder)
param = extract_brackets(line2)
line2 = del_brackets(line2)
line2 = line2.replace(', Decoder)', ', Decoder, %s)' %param)
elif 'MI.addOperand(MCOperand::createImm(tmp));' in line2:
line2 = ' MCOperand_CreateImm0(MI, tmp);'
elif 'MI = TmpMI;' in line2:
line2 = ''
#line2 = line2.replace('TmpMI', '&TmpMI')
line2 = line2.replace('::', '_')
print_line(line2)
if sys.argv[2] == 'ARM':
print("""
FieldFromInstruction(fieldFromInstruction_2, uint16_t)
DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
""")
if sys.argv[2] in ('AArch64', 'PPC'):
print("""
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
""")
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/disassemblertables-arch.py
|
#!/usr/bin/python
# print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenAsmMatcher.inc> <GenInstrInfo.inc> MappingInsn.inc" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[3])
mapping = f.readlines()
f.close()
print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
""")
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# extract insn from GenAsmMatcher Table
# return (arch, mnem, insn_id)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
if arch.upper() == 'AARCH64':
arch = 'ARM64'
return (arch, insn_mnem, tmp[1])
# extract all insn lines from GenAsmMatcher
# return arch, insn_id_list, insn_lines
def extract_matcher(filename):
f = open(filename)
lines = f.readlines()
f.close()
match_count = 0
count = 0
#insn_lines = []
insn_id_list = {}
arch = None
first_insn = None
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if 'MatchEntry MatchTable1[] = {' in line.strip():
match_count += 1
#print(line.strip())
continue
line = line.strip()
if match_count == 1:
count += 1
if line == '};':
# done with first enum
break
else:
_arch, mnem, insn_id = extract_insn(line)
if count == 1:
arch, first_insn = _arch, insn_id
if not insn_id in insn_id_list:
# print("***", arch, mnem, insn_id)
insn_id_list[insn_id] = mnem
#insn_lines.append(line)
#return arch, first_insn, insn_id_list, insn_lines
return arch, first_insn, insn_id_list
#arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1])
arch, first_insn, insn_id_list = extract_matcher(sys.argv[1])
arch = arch.upper()
#for line in insn_id_list:
# print(line)
#{
# X86_AAA, X86_INS_AAA,
##ifndef CAPSTONE_DIET
# { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
##endif
#},
def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong):
insn = "%s_%s" %(arch.upper(), insn_id)
if '64' in insn_id:
is64bit = '1'
else:
is64bit = '0'
# first, try to find this entry in old MappingInsn.inc file
for i in range(len(mapping)):
tmp = mapping[i].split(',')
if tmp[0].strip() == insn:
if not mnem_can_be_wrong:
print('''
{
\t%s_%s, %s_INS_%s, %s,
#ifndef CAPSTONE_DIET
\t%s
#endif
},'''% (arch, insn_id, arch, mnem, is64bit, mapping[i + 2].strip()))
else:
if not tmp[1].endswith(mnem):
#print("======== cannot find %s, mapping to %s (instead of %s)" %(insn, tmp[1].strip(), mnem))
pass
print('''
{
\t%s_%s, %s, %s,
#ifndef CAPSTONE_DIET
\t%s
#endif
},'''% (arch, insn_id, tmp[1].strip(), is64bit, mapping[i + 2].strip()))
return
if mnem_can_be_wrong:
#print("======== CANNOT FIND %s, mapping to %s" %(insn, mnem))
pass
print('''
{
\t%s_%s, %s_INS_%s, %s,
#ifndef CAPSTONE_DIET
\t{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},'''% (arch, insn_id, arch, mnem, is64bit))
# extract from GenInstrInfo.inc, because the insn id is in order
enum_count = 0
meet_insn = False
f = open(sys.argv[2])
lines = f.readlines()
f.close()
count = 0
last_mnem = None
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
#print(line.strip())
continue
line = line.strip()
if enum_count == 1:
if 'INSTRUCTION_LIST_END' in line:
break
else:
insn = None
if meet_insn:
# enum items
insn = line.split('=')[0].strip()
if 'CALLSTACK' in insn or 'TAILJUMP' in insn:
# pseudo instruction
insn = None
elif line.startswith(first_insn):
insn = line.split('=')[0].strip()
meet_insn = True
if insn:
count += 1
if insn == 'BSWAP16r_BAD':
last_mnem = 'BSWAP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp32':
last_mnem = 'FCMOVNP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVP_Fp3':
last_mnem = 'FCMOVP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrm_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVSX16rm16':
last_mnem = 'MOVSX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVZX16rm16':
last_mnem = 'MOVZX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'ST_Fp32m':
last_mnem = 'FST'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp64':
last_mnem = 'FCMOVNU'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrr_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSSrm_Int':
last_mnem = 'CMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSDrm_Int':
last_mnem = 'VCMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSSrm_Int':
last_mnem = 'VCMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPCMOVYrrr_REV':
last_mnem = 'VPCMOV'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESDZm':
last_mnem = 'VRNDSCALESD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESSZm':
last_mnem = 'VRNDSCALESS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPDZ128rm':
last_mnem = 'VMAXPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPSZ128rm':
last_mnem = 'VMAXPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSDZrm':
last_mnem = 'VMAXSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSSZrm':
last_mnem = 'VMAXSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPDZ128rm':
last_mnem = 'VMINPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPSZ128rm':
last_mnem = 'VMINPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSDZrm':
last_mnem = 'VMINSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSSZrm':
last_mnem = 'VMINSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMOV64toPQIZrm':
last_mnem = 'VMOVQ'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PDYrr_REV':
last_mnem = 'VPERMILPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PSYrr_REV':
last_mnem = 'VPERMILPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SI64Zrm_Int':
last_mnem = 'VCVTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SSrm_Int':
last_mnem = 'VCVTSD2SS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSS2SI64Zrm_Int':
last_mnem = 'VCVTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSD2SI64Zrm_Int':
last_mnem = 'VCVTTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSS2SI64Zrm_Int':
last_mnem = 'VCVTTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUBADD'):
if insn[len('VFMSUBADD')].isdigit():
last_mnem = insn[:len('VFMSUBADD123xy')]
else:
last_mnem = insn[:len('VFMSUBADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADDSUB'):
if insn[len('VFMADDSUB')].isdigit():
last_mnem = insn[:len('VFMADDSUB123xy')]
else:
last_mnem = insn[:len('VFMADDSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADD'):
if insn[len('VFMADD')].isdigit():
last_mnem = insn[:len('VFMADD123PD')]
else:
last_mnem = insn[:len('VFMADDPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUB'):
if insn[len('VFMSUB')].isdigit():
last_mnem = insn[:len('VFMSUB123PD')]
else:
last_mnem = insn[:len('VFMSUBPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMADD'):
if insn[len('VFNMADD')].isdigit():
last_mnem = insn[:len('VFNMADD123xy')]
else:
last_mnem = insn[:len('VFNMADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMSUB'):
if insn[len('VFNMSUB')].isdigit():
last_mnem = insn[:len('VFNMSUB123xy')]
else:
last_mnem = insn[:len('VFNMSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn in insn_id_list:
# trust old mapping table
last_mnem = insn_id_list[insn].upper()
print_entry(arch.upper(), insn, insn_id_list[insn].upper(), mapping, False)
else:
# the last option when we cannot find mnem: use the last good mnem
print_entry(arch.upper(), insn, last_mnem, mapping, True)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/mapping_insn.py
|
#!/usr/bin/python
# convert LLVM GenDisassemblerTables.inc for Capstone disassembler.
# this just adds a header
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenDisassemblerTables.inc> <X86GenDisassemblerTables.inc> <X86GenDisassemblerTables2.inc>" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[1])
lines = f.readlines()
f.close()
f1 = open(sys.argv[2], 'w+')
f2 = open(sys.argv[3], 'w+')
f1.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n")
f1.write("/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */\n")
f1.write("\n")
f2.write("/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n")
f2.write("/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */\n")
f2.write("\n")
# static const struct ContextDecision x86DisassemblerOneByteOpcodes = {
# static const struct ContextDecision x86DisassemblerXOP8Opcodes = {
write_to_f2 = False
for line in lines:
# ignore all tables from XOP onwards
if 'ContextDecision x86DisassemblerXOP8Opcodes = {' in line:
# done
break
if 'ContextDecision x86DisassemblerOneByteOpcodes = {' in line:
# done with f1, start writing to f2
write_to_f2 = True
if write_to_f2:
f2.write(line)
else:
f1.write(line)
f1.close()
f2.close()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/disassemblertables_reduce.py
|
#!/usr/bin/python
# convert LLVM GenSubtargetInfo.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenSubtargetInfo.inc> <architecture>" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[1])
lines = f.readlines()
f.close()
arch = sys.argv[2]
print("""
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
""")
count = 0
# 1st enum is subtarget enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
count += 1
print(line)
continue
if count == 1:
if line.strip() == '};':
# done with first enum
break
else:
# enum items
print(" %s_%s" %(arch, line.strip()))
print('};\n')
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/subtargetinfo.py
|
#!/usr/bin/python
# print MappingInsn.inc file from LLVM GenAsmMatcher.inc, for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenAsmMatcher.inc> <GenInstrInfo.inc> <MappingInsnOp.inc>" %sys.argv[0])
sys.exit(1)
f = open(sys.argv[3])
mapping = f.readlines()
f.close()
print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
""")
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# extract insn from GenAsmMatcher Table
# return (arch, mnem, insn_id)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
#if arch.upper() == 'AARCH64':
# arch = 'ARM64'
return (arch, insn_mnem, tmp[1])
# extract all insn lines from GenAsmMatcher
# return arch, first_insn, insn_id_list
def extract_matcher(filename):
f = open(filename)
lines = f.readlines()
f.close()
match_count = 0
insn_id_list = {}
arch = None
first_insn = None
pattern = None
# first we try to find Table1, or Table0
for line in lines:
if 'MatchEntry MatchTable0[] = {' in line.strip():
pattern = 'MatchEntry MatchTable0[] = {'
elif 'AArch64::' in line and pattern:
# We do not care about Apple Assembly
break
elif 'MatchEntry MatchTable1[] = {' in line.strip():
pattern = 'MatchEntry MatchTable1[] = {'
# last pattern, done
break
for line in lines:
line = line.rstrip()
# skip empty line
if len(line.strip()) == 0:
continue
if pattern in line.strip():
match_count += 1
#print(line.strip())
continue
line = line.strip()
if match_count == 1:
if line == '};':
# done with first enum
break
else:
_arch, mnem, insn_id = extract_insn(line)
# skip pseudo instructions
if not mnem.startswith('__'):
if not first_insn:
arch, first_insn = _arch, insn_id
if not insn_id in insn_id_list:
# save this
insn_id_list[insn_id] = mnem
#return arch, first_insn, insn_id_list
return arch, first_insn, insn_id_list
#arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1])
arch, first_insn, insn_id_list = extract_matcher(sys.argv[1])
#arch = arch.upper()
#for line in insn_id_list:
# print(line)
#{ /* X86_AAA, X86_INS_AAA: aaa */
# X86_EFLAGS_UNDEFINED_OF | X86_EFLAGS_UNDEFINED_SF | X86_EFLAGS_UNDEFINED_ZF | X86_EFLAGS_MODIFY_AF | X86_EFLAGS_UNDEFINED_PF | X86_EFLAGS_MODIFY_CF,
# { 0 }
#},
#{ /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */
# { CS_AC_WRITE, CS_AC_READ, 0 }
#},
def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong):
insn = "%s_%s" %(arch, insn_id)
arch1 = arch
if arch.upper() == 'AARCH64':
arch1 = 'ARM64'
# first, try to find this entry in old MappingInsn.inc file
for i in range(len(mapping)):
if mapping[i].startswith('{') and '/*' in mapping[i]:
#print(mapping[i])
tmp = mapping[i].split('/*')
tmp = tmp[1].strip()
tmp = tmp.split(',')
#print("insn2 = |%s|" %tmp.strip())
if tmp[0].strip() == insn:
if not mnem_can_be_wrong:
if arch.upper() == 'ARM':
print('''
{\t/* %s, %s_INS_%s: %s */
\t%s
},'''% (insn, arch1, mnem, mnem.lower(), mapping[i + 1].strip()))
else: # ARM64
print('''
{\t/* %s, %s_INS_%s: %s */
\t%s
\t%s
},'''% (insn, arch, mnem, mnem.lower(), mapping[i + 1].strip(), mapping[i + 2].strip()))
else:
if arch.upper() == 'ARM':
print('''
{\t/* %s, %s
\t%s
},'''% (insn, ''.join(tmp[1:]), mapping[i + 1].strip()))
else: # ARM64
print('''
{\t/* %s, %s
\t%s
\t%s
},'''% (insn, ''.join(tmp[1:]), mapping[i + 1].strip(), mapping[i + 2].strip()))
return
if mnem_can_be_wrong:
#print("======== CANNOT FIND %s, mapping to %s" %(insn, mnem))
return
pass
# this insn does not exist in mapping table
if arch.upper() == 'ARM':
print('''
{\t/* %s, %s_INS_%s: %s */
\t{ 0 }
},'''% (insn, arch1, mnem, mnem.lower()))
else:
print('''
{\t/* %s, %s_INS_%s: %s */
\t0,
\t{ 0 }
},'''% (insn, arch, mnem, mnem.lower()))
# extract from GenInstrInfo.inc, because the insn id is in order
enum_count = 0
meet_insn = False
f = open(sys.argv[2])
lines = f.readlines()
f.close()
count = 0
last_mnem = None
def is_pseudo_insn(insn, lines):
return False
for line in lines:
tmp = '= %s' %insn
if tmp in line and 'MCID::Pseudo' in line:
return True
return False
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
#print(line.strip())
continue
line = line.strip()
if enum_count == 1:
# skip pseudo instructions
if '__' in line or 'setjmp' in line or 'longjmp' in line or 'Pseudo' in line:
continue
elif 'INSTRUCTION_LIST_END' in line:
break
else:
insn = line.split('=')[0].strip()
# skip more pseudo instruction
if is_pseudo_insn(insn, lines):
continue
'''
insn = None
if meet_insn:
# enum items
insn = line.split('=')[0].strip()
if 'CALLSTACK' in insn or 'TAILJUMP' in insn:
# pseudo instruction
insn = None
elif line.startswith(first_insn):
insn = line.split('=')[0].strip()
meet_insn = True
if insn:
count += 1
if insn == 'BSWAP16r_BAD':
last_mnem = 'BSWAP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp32':
last_mnem = 'FCMOVNP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVP_Fp3':
last_mnem = 'FCMOVP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrm_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVSX16rm16':
last_mnem = 'MOVSX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVZX16rm16':
last_mnem = 'MOVZX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'ST_Fp32m':
last_mnem = 'FST'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp64':
last_mnem = 'FCMOVNU'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrr_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSSrm_Int':
last_mnem = 'CMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSDrm_Int':
last_mnem = 'VCMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSSrm_Int':
last_mnem = 'VCMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPCMOVYrrr_REV':
last_mnem = 'VPCMOV'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESDZm':
last_mnem = 'VRNDSCALESD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESSZm':
last_mnem = 'VRNDSCALESS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPDZ128rm':
last_mnem = 'VMAXPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPSZ128rm':
last_mnem = 'VMAXPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSDZrm':
last_mnem = 'VMAXSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSSZrm':
last_mnem = 'VMAXSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPDZ128rm':
last_mnem = 'VMINPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPSZ128rm':
last_mnem = 'VMINPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSDZrm':
last_mnem = 'VMINSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSSZrm':
last_mnem = 'VMINSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMOV64toPQIZrm':
last_mnem = 'VMOVQ'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PDYrr_REV':
last_mnem = 'VPERMILPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PSYrr_REV':
last_mnem = 'VPERMILPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SI64Zrm_Int':
last_mnem = 'VCVTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SSrm_Int':
last_mnem = 'VCVTSD2SS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSS2SI64Zrm_Int':
last_mnem = 'VCVTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSD2SI64Zrm_Int':
last_mnem = 'VCVTTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSS2SI64Zrm_Int':
last_mnem = 'VCVTTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUBADD'):
if insn[len('VFMSUBADD')].isdigit():
last_mnem = insn[:len('VFMSUBADD123xy')]
else:
last_mnem = insn[:len('VFMSUBADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADDSUB'):
if insn[len('VFMADDSUB')].isdigit():
last_mnem = insn[:len('VFMADDSUB123xy')]
else:
last_mnem = insn[:len('VFMADDSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADD'):
if insn[len('VFMADD')].isdigit():
last_mnem = insn[:len('VFMADD123PD')]
else:
last_mnem = insn[:len('VFMADDPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUB'):
if insn[len('VFMSUB')].isdigit():
last_mnem = insn[:len('VFMSUB123PD')]
else:
last_mnem = insn[:len('VFMSUBPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMADD'):
if insn[len('VFNMADD')].isdigit():
last_mnem = insn[:len('VFNMADD123xy')]
else:
last_mnem = insn[:len('VFNMADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMSUB'):
if insn[len('VFNMSUB')].isdigit():
last_mnem = insn[:len('VFNMSUB123xy')]
else:
last_mnem = insn[:len('VFNMSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
'''
if insn in insn_id_list:
# trust old mapping table
last_mnem = insn_id_list[insn].upper()
print_entry(arch, insn, insn_id_list[insn].upper(), mapping, False)
else:
#pass
# the last option when we cannot find mnem: use the last good mnem
print_entry(arch, insn, last_mnem, mapping, True)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/mapping_insn_op-arch.py
|
#!/usr/bin/python
# convert LLVM GenInstrInfo.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenInstrInfo.inc> <AsmMatcher.info>" %sys.argv[0])
sys.exit(1)
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# return (arch, mnem)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
if arch.upper() == 'AArch64':
arch = 'ARM64'
return (arch, insn_mnem)
# get (arch, first insn) from MatchTable
def get_first_insn(filename):
f = open(filename)
lines = f.readlines()
f.close()
count = 0
for line in lines:
line = line.strip()
if len(line) == 0:
continue
# Intel syntax in Table1
if 'MatchEntry MatchTable1[] = {' in line:
count += 1
#print(line.strip())
continue
if count == 1:
arch, mnem = extract_insn(line)
return (arch, mnem)
return (None, None)
arch, first_insn = get_first_insn(sys.argv[2])
first_insn = first_insn.upper()
arch = arch.upper()
#print(arch, first_insn)
print("""
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Instruction Enum Values and Descriptors *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
""")
enum_count = 0
meet_insn = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
print(line.strip())
continue
line = line.strip()
if enum_count == 1:
if line == '};':
# done with first enum
break
else:
insn = None
if meet_insn:
# enum items
insn = line
elif line.startswith(first_insn):
insn = line
meet_insn = True
if insn:
print("\t%s_%s" %(arch, line))
print('};\n')
print("#endif // GET_INSTRINFO_ENUM")
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/instrinfo.py
|
#!/usr/bin/python
# print list of instructions LLVM inc files, for Capstone disassembler.
# this will be put into capstone/<arch>.h
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenAsmMatcher.inc> <GenInstrInfo.inc> MappingInsn.inc" %sys.argv[0])
sys.exit(1)
# MappingInsn.inc
f = open(sys.argv[3])
mapping = f.readlines()
f.close()
print("""/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
""")
# lib/Target/X86/X86GenAsmMatcher.inc
# static const MatchEntry MatchTable1[] = {
# { 0 /* aaa */, X86::AAA, Convert_NoOperands, Feature_Not64BitMode, { }, },
# extract insn from GenAsmMatcher Table
# return (arch, mnem, insn_id)
def extract_insn(line):
tmp = line.split(',')
insn_raw = tmp[1].strip()
insn_mnem = tmp[0].split(' ')[3]
# X86 mov.s
if '.' in insn_mnem:
tmp = insn_mnem.split('.')
insn_mnem = tmp[0]
tmp = insn_raw.split('::')
arch = tmp[0]
# AArch64 -> ARM64
if arch.upper() == 'AArch64':
arch = 'ARM64'
return (arch, insn_mnem, tmp[1])
# extract all insn lines from GenAsmMatcher
# return arch, insn_id_list, insn_lines
def extract_matcher(filename):
f = open(filename)
lines = f.readlines()
f.close()
match_count = 0
#insn_lines = []
insn_id_list = {}
arch = None
first_insn = None
pattern = None
# first we try to find Table1, or Table0
for line in lines:
if 'MatchEntry MatchTable0[] = {' in line.strip():
pattern = 'MatchEntry MatchTable0[] = {'
elif 'MatchEntry MatchTable1[] = {' in line.strip():
pattern = 'MatchEntry MatchTable1[] = {'
# last pattern, done
break
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if pattern in line.strip():
match_count += 1
#print(line.strip())
continue
line = line.strip()
if match_count == 1:
if line == '};':
# done with first enum
break
else:
_arch, mnem, insn_id = extract_insn(line)
if not mnem.startswith('__'):
if not first_insn:
arch, first_insn = _arch, insn_id
if not insn_id in insn_id_list:
# print("***", arch, mnem, insn_id)
insn_id_list[insn_id] = mnem
#insn_lines.append(line)
#return arch, first_insn, insn_id_list, insn_lines
return arch, first_insn, insn_id_list
# GenAsmMatcher.inc
#arch, first_insn, insn_id_list, match_lines = extract_matcher(sys.argv[1])
arch, first_insn, insn_id_list = extract_matcher(sys.argv[1])
arch = arch.upper()
#for line in insn_id_list:
# print(line)
insn_list = []
#{
# X86_AAA, X86_INS_AAA,
##ifndef CAPSTONE_DIET
# { 0 }, { 0 }, { X86_GRP_NOT64BITMODE, 0 }, 0, 0
##endif
#},
def print_entry(arch, insn_id, mnem, mapping, mnem_can_be_wrong):
print(arch, insn_id, mnem, mnem_can_be_wrong)
if not mnem_can_be_wrong:
insn = "%s_INS_%s" %(arch.upper(), mnem.upper())
if insn in insn_list:
return
print("%s," %insn)
insn_list.append(insn)
return
insn = "%s_%s" %(arch.upper(), insn_id)
# so mnem can be wrong, we need to verify with MappingInsn.inc
# first, try to find this entry in old MappingInsn.inc file
for i in range(len(mapping)):
tmp = mapping[i].split(',')
if tmp[0].strip() == insn:
insn = tmp[1].strip()
if insn in insn_list:
return
#print("==== get below from MappingInsn.inc file: %s" %insn)
print("%s," %insn)
insn_list.append(insn)
return
# extract from GenInstrInfo.inc, because the insn id is in order
enum_count = 0
meet_insn = False
# GenInstrInfo.inc
f = open(sys.argv[2])
lines = f.readlines()
f.close()
count = 0
last_mnem = None
# 1st enum is register enum
for line in lines:
line = line.rstrip()
if len(line.strip()) == 0:
continue
if line.strip() == 'enum {':
enum_count += 1
#print(line.strip())
continue
line = line.strip()
if enum_count == 1:
if 'INSTRUCTION_LIST_END' in line:
break
else:
insn = None
if meet_insn:
# enum items
insn = line.split('=')[0].strip()
if 'CALLSTACK' in insn or 'TAILJUMP' in insn:
# pseudo instruction
insn = None
elif line.startswith(first_insn):
insn = line.split('=')[0].strip()
meet_insn = True
if insn:
count += 1
if insn == 'BSWAP16r_BAD':
last_mnem = 'BSWAP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp32':
last_mnem = 'FCMOVNP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVP_Fp3':
last_mnem = 'FCMOVP'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrm_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVSX16rm16':
last_mnem = 'MOVSX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'MOVZX16rm16':
last_mnem = 'MOVZX'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'ST_Fp32m':
last_mnem = 'FST'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMOVNP_Fp64':
last_mnem = 'FCMOVNU'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSDrr_Int':
last_mnem = 'CMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'CMPSSrm_Int':
last_mnem = 'CMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSDrm_Int':
last_mnem = 'VCMPSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCMPSSrm_Int':
last_mnem = 'VCMPSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPCMOVYrrr_REV':
last_mnem = 'VPCMOV'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESDZm':
last_mnem = 'VRNDSCALESD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VRNDSCALESSZm':
last_mnem = 'VRNDSCALESS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPDZ128rm':
last_mnem = 'VMAXPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCPSZ128rm':
last_mnem = 'VMAXPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSDZrm':
last_mnem = 'VMAXSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMAXCSSZrm':
last_mnem = 'VMAXSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPDZ128rm':
last_mnem = 'VMINPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCPSZ128rm':
last_mnem = 'VMINPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSDZrm':
last_mnem = 'VMINSD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMINCSSZrm':
last_mnem = 'VMINSS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VMOV64toPQIZrm':
last_mnem = 'VMOVQ'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PDYrr_REV':
last_mnem = 'VPERMILPD'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VPERMIL2PSYrr_REV':
last_mnem = 'VPERMILPS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SI64Zrm_Int':
last_mnem = 'VCVTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSD2SSrm_Int':
last_mnem = 'VCVTSD2SS'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTSS2SI64Zrm_Int':
last_mnem = 'VCVTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSD2SI64Zrm_Int':
last_mnem = 'VCVTTSD2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn == 'VCVTTSS2SI64Zrm_Int':
last_mnem = 'VCVTTSS2SI'
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUBADD'):
if insn[len('VFMSUBADD')].isdigit():
last_mnem = insn[:len('VFMSUBADD123xy')]
else:
last_mnem = insn[:len('VFMSUBADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADDSUB'):
if insn[len('VFMADDSUB')].isdigit():
last_mnem = insn[:len('VFMADDSUB123xy')]
else:
last_mnem = insn[:len('VFMADDSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMADD'):
if insn[len('VFMADD')].isdigit():
last_mnem = insn[:len('VFMADD123PD')]
else:
last_mnem = insn[:len('VFMADDPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFMSUB'):
if insn[len('VFMSUB')].isdigit():
last_mnem = insn[:len('VFMSUB123PD')]
else:
last_mnem = insn[:len('VFMSUBPD')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMADD'):
if insn[len('VFNMADD')].isdigit():
last_mnem = insn[:len('VFNMADD123xy')]
else:
last_mnem = insn[:len('VFNMADDSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn.startswith('VFNMSUB'):
if insn[len('VFNMSUB')].isdigit():
last_mnem = insn[:len('VFNMSUB123xy')]
else:
last_mnem = insn[:len('VFNMSUBSS')]
print_entry(arch.upper(), insn, last_mnem, mapping, False)
elif insn in insn_id_list:
# trust old mapping table
last_mnem = insn_id_list[insn].upper()
print_entry(arch.upper(), insn, last_mnem, mapping, False)
else:
# the last option when we cannot find mnem: use the last good mnem
print_entry(arch.upper(), insn, last_mnem, mapping, True)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/insn.py
|
#!/usr/bin/python
# convert LLVM GenInstrInfo.inc for Capstone disassembler.
# by Nguyen Anh Quynh, 2019
import sys
if len(sys.argv) == 1:
print("Syntax: %s <GenInstrInfo.inc>" %sys.argv[0])
sys.exit(1)
count = 0
last_line = None
f = open(sys.argv[1])
lines = f.readlines()
f.close()
# 1st enum is register enum
for line in lines:
line = line.rstrip()
# skip all MCPhysReg line
if 'static const MCPhysReg ' in line:
continue
# skip all MCOperandInfo line
if 'static const MCOperandInfo ' in line:
continue
# skip InitX86MCInstrInfo()
if 'static inline void InitX86MCInstrInfo' in line:
continue
if 'II->InitMCInstrInfo' in line:
last_line = line
continue
# skip the next line after II->InitMCInstrInfo
if last_line:
last_line = None
continue
if 'extern const MCInstrDesc ' in line:
count += 1
continue
if count == 1:
if line == '};':
# done with first enum
count += 1
continue
else:
print(line)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/synctools/strinforeduce/instrinfo2.py
|
#!/usr/bin/python
import re
import sys
import getopt
from subprocess import Popen, PIPE
from pprint import pprint as ppr
import os
def Usage(s):
print 'Usage: {} -t <cstest_path> [-f <file_name.cs>] [-d <directory>]'.format(s)
sys.exit(-1)
def get_report_file(toolpath, filepath, getDetails, cmt_out):
cmd = [toolpath, '-f', filepath]
process = Popen(cmd, stdout=PIPE, stderr=PIPE)
stdout, stderr = process.communicate()
# stdout
failed_tests = []
# print '---> stdout\n', stdout
# print '---> stderr\n', stderr
matches = re.finditer(r'\[\s+RUN\s+\]\s+(.*)\n\[\s+FAILED\s+\]', stdout)
for match in matches:
failed_tests.append(match.group(1))
# stderr
counter = 0
details = []
for line in stderr.split('\n'):
if '[ PASSED ] 0 test(s).' in line:
break
elif 'LINE' in line:
continue
elif 'ERROR' in line and ' --- ' in line:
parts = line.split(' --- ')
try:
details.append((parts[1], failed_tests[counter], parts[2]))
except IndexError:
details.append(('', 'Unknown test', line.split(' --- ')[1]))
counter += 1
else:
continue
print '\n[-] There are/is {} failed test(s)'.format(len(details))
if len(details) > 0 and getDetails:
print '[-] Detailed report for {}:\n'.format(filepath)
for c, f, d in details:
print '\t[+] {}: {}\n\t\t{}\n'.format(f, c, d)
print '\n'
return 0
elif len(details) > 0:
for c, f, d in details:
if len(f) > 0 and cmt_out is True:
tmp_cmd = ['sed', '-E', '-i.bak', 's/({})(.*)/\/\/ \\1\\2/g'.format(c), filepath]
sed_proc = Popen(tmp_cmd, stdout=PIPE, stderr=PIPE)
sed_proc.communicate()
tmp_cmd2 = ['rm', '-f', filepath + '.bak']
rm_proc = Popen(tmp_cmd2, stdout=PIPE, stderr=PIPE)
rm_proc.communicate()
return 0;
return 1
def get_report_folder(toolpath, folderpath, details, cmt_out):
result = 1
for root, dirs, files in os.walk(folderpath):
path = root.split(os.sep)
for f in files:
if f.split('.')[-1] == 'cs':
print '[-] Target:', f,
result *= get_report_file(toolpath, os.sep.join(x for x in path) + os.sep + f, details, cmt_out)
sys.exit(result ^ 1)
if __name__ == '__main__':
Done = False
details = False
toolpath = ''
cmt_out = False
try:
opts, args = getopt.getopt(sys.argv[1:], "ct:f:d:D")
for opt, arg in opts:
if opt == '-f':
result = get_report_file(toolpath, arg, details, cmt_out)
if result == 0:
sys.exit(1)
Done = True
elif opt == '-d':
get_report_folder(toolpath, arg, details, cmt_out)
Done = True
elif opt == '-t':
toolpath = arg
elif opt == '-D':
details = True
elif opt == '-c':
cmt_out = True
except getopt.GetoptError:
Usage(sys.argv[0])
if Done is False:
Usage(sys.argv[0])
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/suite/cstest/cstest_report.py
|
# Capstone Disassembler Engine
# By Dang Hoang Vu, 2013
from __future__ import print_function
import sys, re
INCL_DIR = '../include/capstone/'
include = [ 'arm.h', 'arm64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h' ]
template = {
'java': {
'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT\npackage capstone;\n\npublic class %s_const {\n",
'footer': "}",
'line_format': '\tpublic static final int %s = %s;\n',
'out_file': './java/capstone/%s_const.java',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'Arm',
'arm64.h': 'Arm64',
'm68k.h': 'M68k',
'mips.h': 'Mips',
'x86.h': 'X86',
'ppc.h': 'Ppc',
'sparc.h': 'Sparc',
'systemz.h': 'Sysz',
'xcore.h': 'Xcore',
'tms320c64x.h': 'TMS320C64x',
'm680x.h': 'M680x',
'evm.h': 'Evm',
'wasm.h': 'Wasm',
'comment_open': '\t//',
'comment_close': '',
},
'python': {
'header': "# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.py]\n",
'footer': "",
'line_format': '%s = %s\n',
'out_file': './python/capstone/%s_const.py',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'arm64.h': 'arm64',
'm68k.h': 'm68k',
'mips.h': 'mips',
'x86.h': 'x86',
'ppc.h': 'ppc',
'sparc.h': 'sparc',
'systemz.h': 'sysz',
'xcore.h': 'xcore',
'tms320c64x.h': 'tms320c64x',
'm680x.h': 'm680x',
'evm.h': 'evm',
'wasm.h': 'wasm',
'mos65xx.h': 'mos65xx',
'bpf.h': 'bpf',
'riscv.h': 'riscv',
'comment_open': '#',
'comment_close': '',
},
'ocaml': {
'header': "(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [%s_const.ml] *)\n",
'footer': "",
'line_format': 'let _%s = %s;;\n',
'out_file': './ocaml/%s_const.ml',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'arm64.h': 'arm64',
'mips.h': 'mips',
'm68k.h': 'm68k',
'x86.h': 'x86',
'ppc.h': 'ppc',
'sparc.h': 'sparc',
'systemz.h': 'sysz',
'xcore.h': 'xcore',
'tms320c64x.h': 'tms320c64x',
'm680x.h': 'm680x',
'evm.h': 'evm',
'wasm.h': 'wasm',
'comment_open': '(*',
'comment_close': ' *)',
},
}
# markup for comments to be added to autogen files
MARKUP = '//>'
def gen(lang):
global include, INCL_DIR
print('Generating bindings for', lang)
templ = template[lang]
print('Generating bindings for', lang)
for target in include:
if target not in templ:
print("Warning: No binding found for %s" % target)
continue
prefix = templ[target]
outfile = open(templ['out_file'] %(prefix), 'wb') # open as binary prevents windows newlines
outfile.write((templ['header'] % (prefix)).encode("utf-8"))
lines = open(INCL_DIR + target).readlines()
count = 0
for line in lines:
line = line.strip()
if line.startswith(MARKUP): # markup for comments
outfile.write(("\n%s%s%s\n" %(templ['comment_open'], \
line.replace(MARKUP, ''), \
templ['comment_close']) ).encode("utf-8"))
continue
if line == '' or line.startswith('//'):
continue
if line.startswith('#define '):
line = line[8:] #cut off define
xline = re.split('\s+', line, 1) #split to at most 2 express
if len(xline) != 2:
continue
if '(' in xline[0] or ')' in xline[0]: #does it look like a function
continue
xline.insert(1, '=') # insert an = so the expression below can parse it
line = ' '.join(xline)
if not line.startswith(prefix.upper()):
continue
tmp = line.strip().split(',')
for t in tmp:
t = t.strip()
if not t or t.startswith('//'): continue
# hacky: remove type cast (uint64_t)
t = t.replace('(uint64_t)', '')
t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t) # (1ULL<<1) to 1 << 1
f = re.split('\s+', t)
if f[0].startswith(prefix.upper()):
if len(f) > 1 and f[1] not in ('//', '///<', '='):
print("Error: Unable to convert %s" % f)
continue
elif len(f) > 1 and f[1] == '=':
rhs = ''.join(f[2:])
else:
rhs = str(count)
count += 1
try:
count = int(rhs) + 1
if (count == 1):
outfile.write(("\n").encode("utf-8"))
except ValueError:
if lang == 'ocaml':
# ocaml uses lsl for '<<', lor for '|'
rhs = rhs.replace('<<', ' lsl ')
rhs = rhs.replace('|', ' lor ')
# ocaml variable has _ as prefix
if rhs[0].isalpha():
rhs = '_' + rhs
outfile.write((templ['line_format'] %(f[0].strip(), rhs)).encode("utf-8"))
outfile.write((templ['footer']).encode("utf-8"))
outfile.close()
def main():
try:
if sys.argv[1] == 'all':
for key in template.keys():
gen(key)
else:
gen(sys.argv[1])
except:
raise RuntimeError("Unsupported binding %s" % sys.argv[1])
if __name__ == "__main__":
if len(sys.argv) < 2:
print("Usage:", sys.argv[0], " <bindings: java|python|ocaml|all>")
sys.exit(1)
main()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/const_generator.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
import binascii
import sys
from xprint import to_hex
_python3 = sys.version_info.major == 3
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
RISCV_CODE64 = b"\x13\x04\xa8\x7a"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
(CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "riscv32", None),
(CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "riscv64", None),
)
# ## Test cs_disasm_quick()
def test_cs_disasm_quick():
for arch, mode, code, comment, syntax in all_tests:
print('*' * 40)
print("Platform: %s" % comment)
print("Disasm:"),
print(to_hex(code))
for insn in cs_disasm_quick(arch, mode, code, 0x1000):
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
print()
# ## Test class Cs
def test_class():
for arch, mode, code, comment, syntax in all_tests:
print('*' * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
for insn in md.disasm(code, 0x1000):
# bytes = binascii.hexlify(insn.bytes)
# print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes))
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
print("0x%x:" % (insn.address + insn.size))
print()
except CsError as e:
print("ERROR: %s" % e)
# test_cs_disasm_quick()
# print ("*" * 40)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_basic.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.ppc import *
from xprint import to_hex, to_x_32
PPC_CODE = b"\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
all_tests = (
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == PPC_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == PPC_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
if i.type == PPC_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if i.type == PPC_OP_CRX:
print("\t\toperands[%u].type: CRX" % c)
print("\t\t\toperands[%u].crx.scale: = %u" \
% (c, i.crx.scale))
if i.crx.reg != 0:
print("\t\t\toperands[%u].crx.reg: REG = %s" \
% (c, insn.reg_name(i.crx.reg)))
if i.crx.cond != 0:
print("\t\t\toperands[%u].crx.cond: 0x%x" \
% (c, i.crx.cond))
c += 1
if insn.bc:
print("\tBranch code: %u" % insn.bc)
if insn.bh:
print("\tBranch hint: %u" % insn.bh)
if insn.update_cr0:
print("\tUpdate-CR0: True")
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_ppc.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
)
def print_detail(insn):
print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \
% (insn.address, insn.mnemonic, insn.op_str, insn.id, \
insn.insn_name()))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.regs_read) > 0:
print("\tImplicit registers read: ", end=''),
for m in insn.regs_read:
print("%s " % insn.reg_name(m), end=''),
print()
if len(insn.regs_write) > 0:
print("\tImplicit registers modified: ", end=''),
for m in insn.regs_write:
print("%s " % insn.reg_name(m), end=''),
print()
if len(insn.groups) > 0:
print("\tThis instruction belongs to groups: ", end=''),
for m in insn.groups:
print("%s " % insn.group_name(m), end=''),
print()
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 40)
print("Platform: %s" % comment)
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
if syntax is not None:
md.syntax = syntax
for insn in md.disasm(code, 0x1000):
print_detail(insn)
print()
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_detail.py
|
#!/usr/bin/env python
import test_basic, test_arm, test_arm64, test_detail, test_lite, test_m68k, test_mips, \
test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \
test_m680x, test_mos65xx, test_xcore, test_riscv
test_basic.test_class()
test_arm.test_class()
test_arm64.test_class()
test_detail.test_class()
test_lite.test_class()
test_m68k.test_class()
test_mips.test_class()
test_mos65xx.test_class()
test_ppc.test_class()
test_sparc.test_class()
test_systemz.test_class()
test_x86.test_class()
test_tms320c64x.test_class()
test_m680x.test_class()
test_skipdata.test_class()
test_customized_mnem.test()
test_xcore.test_class()
test_riscv.test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_all.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Fotis Loukos <me@fotisl.com>
from __future__ import print_function
from capstone import *
from capstone.tms320c64x import *
from xprint import to_x, to_hex, to_x_32
TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
all_tests = (
(CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == TMS320C64X_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == TMS320C64X_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == TMS320C64X_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.disptype == TMS320C64X_MEM_DISP_INVALID:
print("\t\t\toperands[%u].mem.disptype: Invalid" % (c))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
if i.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT:
print("\t\t\toperands[%u].mem.disptype: Constant" % (c))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
if i.mem.disptype == TMS320C64X_MEM_DISP_REGISTER:
print("\t\t\toperands[%u].mem.disptype: Register" % (c))
print("\t\t\toperands[%u].mem.disp: %s" \
% (c, insn.reg_name(i.mem.disp)))
print("\t\t\toperands[%u].mem.unit: %u" % (c, i.mem.unit))
if i.mem.direction == TMS320C64X_MEM_DIR_INVALID:
print("\t\t\toperands[%u].mem.direction: Invalid" % (c))
if i.mem.direction == TMS320C64X_MEM_DIR_FW:
print("\t\t\toperands[%u].mem.direction: Forward" % (c))
if i.mem.direction == TMS320C64X_MEM_DIR_BW:
print("\t\t\toperands[%u].mem.direction: Backward" % (c))
if i.mem.modify == TMS320C64X_MEM_MOD_INVALID:
print("\t\t\toperands[%u].mem.modify: Invalid" % (c))
if i.mem.modify == TMS320C64X_MEM_MOD_NO:
print("\t\t\toperands[%u].mem.modify: No" % (c))
if i.mem.modify == TMS320C64X_MEM_MOD_PRE:
print("\t\t\toperands[%u].mem.modify: Pre" % (c))
if i.mem.modify == TMS320C64X_MEM_MOD_POST:
print("\t\t\toperands[%u].mem.modify: Post" % (c))
print("\t\t\toperands[%u].mem.scaled: %u" % (c, i.mem.scaled))
if i.type == TMS320C64X_OP_REGPAIR:
print("\t\toperands[%u].type: REGPAIR = %s:%s" % (c, insn.reg_name(i.reg + 1), insn.reg_name(i.reg)))
c += 1
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" %e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_tms320c64x.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
import binascii
from xprint import to_hex
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92"
RANDOM_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
all_tests = (
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, RANDOM_CODE, "Arm", None),
)
# Sample callback for SKIPDATA option
def testcb(buffer, size, offset, userdata):
# always skip 2 bytes of data
return 2
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
md.skipdata = True
# Default "data" instruction's name is ".byte". To rename it to "db", just use
# the code below.
md.skipdata_setup = ("db", None, None)
# NOTE: This example ignores SKIPDATA's callback (first None) & user_data (second None)
# Can also use dedicated setter
#md.skipdata_mnem = 'db'
# To customize the SKIPDATA callback, use the line below.
#md.skipdata_setup = (".db", testcb, None)
# Or use dedicated setter with custom parameter
#md.skipdata_callback = (testcb, 42)
# Or provide just a function
#md.skipdata_callback = testcb
# Note that reading this property will always return a tuple
#assert md.skipdata_callback == (testcb, None)
for insn in md.disasm(code, 0x1000):
#bytes = binascii.hexlify(insn.bytes)
#print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes))
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
print("0x%x:" % (insn.address + insn.size))
print
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_skipdata.py
|
#!/usr/bin/env python
# Capstone Python bindings
# BPF tests by david942j <david942j@gmail.com>, 2019
from __future__ import print_function
from capstone import *
from capstone.bpf import *
from xprint import to_hex, to_x_32
CBPF_CODE = b"\x94\x09\x00\x00\x37\x13\x03\x00\x87\x00\x00\x00\x00\x00\x00\x00\x07\x00\x00\x00\x00\x00\x00\x00\x16\x00\x00\x00\x00\x00\x00\x00\x80\x00\x00\x00\x00\x00\x00\x00"
EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
all_tests = (
(CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, CBPF_CODE, "cBPF Le", None),
(CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF Le", None),
)
ext_name = {}
ext_name[BPF_EXT_LEN] = '#len'
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.groups) > 0:
print('\tGroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups)))
print("\tOperand count: %u" % len(insn.operands))
for c, op in enumerate(insn.operands):
print("\t\toperands[%u].type: " % c, end='')
if op.type == BPF_OP_REG:
print("REG = " + insn.reg_name(op.reg))
elif op.type == BPF_OP_IMM:
print("IMM = " + hex(op.imm)[:-1])
elif op.type == BPF_OP_OFF:
print("OFF = +0x" + to_x_32(op.off))
elif op.type == BPF_OP_MEM:
print("MEM")
if op.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(op.mem.base)))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(op.mem.disp)))
elif op.type == BPF_OP_MMEM:
print("MMEM = 0x" + to_x_32(op.mmem))
elif op.type == BPF_OP_MSH:
print("MSH = 4*([0x%s]&0xf)" % to_x_32(op.msh))
elif op.type == BPF_OP_EXT:
print("EXT = " + ext_name[op.ext])
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" % insn.reg_name(r), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" % insn.reg_name(r), end="")
print("")
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
md.detail = True
for insn in md.disasm(code, 0x0):
print_insn_detail(insn)
print ()
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_bpf.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Sebastian Macke <Sebastian Macke>
from __future__ import print_function
from capstone import *
from capstone.mos65xx import *
from xprint import to_hex, to_x
MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
address_modes=[
"No address mode",
"implied",
"accumulator",
"immediate value",
"relative",
"interrupt signature",
"block move",
"zero page",
"zero page indexed with x",
"zero page indexed with y",
"relative bit branch",
"zero page indirect",
"zero page indexed with x indirect",
"zero page indirect indexed with y",
"zero page indirect long",
"zero page indirect long indexed with y",
"absolute",
"absolute indexed with x",
"absolute indexed with y",
"absolute indirect",
"absolute indexed with x indirect",
"absolute indirect long",
"absolute long",
"absolute long indexed with x",
"stack relative",
"stack relative indirect indexed with y",
];
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
print("\taddress mode: %s" % (address_modes[insn.am]))
print("\tmodifies flags: %s" % ('true' if insn.modifies_flags != 0 else 'false'))
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == MOS65XX_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == MOS65XX_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == MOS65XX_OP_MEM:
print("\t\toperands[%u].type: MEM = 0x%s" % (c, to_x(i.mem)))
# ## Test class Cs
def test_class():
print("*" * 16)
print("Platform: %s" % "MOS65XX")
print("Code: %s" % to_hex(MOS65XX_CODE))
print("Disasm:")
try:
md = Cs(CS_ARCH_MOS65XX, 0)
md.detail = True
for insn in md.disasm(MOS65XX_CODE, 0x1000):
print_insn_detail(insn)
print()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_mos65xx.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from xprint import to_hex
CODE = "\x60\x61\x50"
cs = Cs(CS_ARCH_EVM, 0)
cs.detail = True
print("Platform: EVM")
print("Code: %s" %to_hex(CODE))
print("Disasm:")
for i in cs.disasm(CODE, 0x80001000):
print("0x%x:\t%s\t%s" %(i.address, i.mnemonic, i.op_str))
if i.pop > 0:
print("\tPop: %u" %i.pop)
if i.push > 0:
print("\tPush: %u" %i.push)
if i.fee > 0:
print("\tGas fee: %u" %i.fee)
if len(i.groups) > 0:
print("\tGroups: ", end=''),
for m in i.groups:
print("%s " % i.group_name(m), end=''),
print()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_evm.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.x86 import *
from xprint import to_hex, to_x, to_x_32
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
)
def get_eflag_name(eflag):
if eflag == X86_EFLAGS_UNDEFINED_OF:
return "UNDEF_OF"
elif eflag == X86_EFLAGS_UNDEFINED_SF:
return "UNDEF_SF"
elif eflag == X86_EFLAGS_UNDEFINED_ZF:
return "UNDEF_ZF"
elif eflag == X86_EFLAGS_MODIFY_AF:
return "MOD_AF"
elif eflag == X86_EFLAGS_UNDEFINED_PF:
return "UNDEF_PF"
elif eflag == X86_EFLAGS_MODIFY_CF:
return "MOD_CF"
elif eflag == X86_EFLAGS_MODIFY_SF:
return "MOD_SF"
elif eflag == X86_EFLAGS_MODIFY_ZF:
return "MOD_ZF"
elif eflag == X86_EFLAGS_UNDEFINED_AF:
return "UNDEF_AF"
elif eflag == X86_EFLAGS_MODIFY_PF:
return "MOD_PF"
elif eflag == X86_EFLAGS_UNDEFINED_CF:
return "UNDEF_CF"
elif eflag == X86_EFLAGS_MODIFY_OF:
return "MOD_OF"
elif eflag == X86_EFLAGS_RESET_OF:
return "RESET_OF"
elif eflag == X86_EFLAGS_RESET_CF:
return "RESET_CF"
elif eflag == X86_EFLAGS_RESET_DF:
return "RESET_DF"
elif eflag == X86_EFLAGS_RESET_IF:
return "RESET_IF"
elif eflag == X86_EFLAGS_TEST_OF:
return "TEST_OF"
elif eflag == X86_EFLAGS_TEST_SF:
return "TEST_SF"
elif eflag == X86_EFLAGS_TEST_ZF:
return "TEST_ZF"
elif eflag == X86_EFLAGS_TEST_PF:
return "TEST_PF"
elif eflag == X86_EFLAGS_TEST_CF:
return "TEST_CF"
elif eflag == X86_EFLAGS_RESET_SF:
return "RESET_SF"
elif eflag == X86_EFLAGS_RESET_AF:
return "RESET_AF"
elif eflag == X86_EFLAGS_RESET_TF:
return "RESET_TF"
elif eflag == X86_EFLAGS_RESET_NT:
return "RESET_NT"
elif eflag == X86_EFLAGS_PRIOR_OF:
return "PRIOR_OF"
elif eflag == X86_EFLAGS_PRIOR_SF:
return "PRIOR_SF"
elif eflag == X86_EFLAGS_PRIOR_ZF:
return "PRIOR_ZF"
elif eflag == X86_EFLAGS_PRIOR_AF:
return "PRIOR_AF"
elif eflag == X86_EFLAGS_PRIOR_PF:
return "PRIOR_PF"
elif eflag == X86_EFLAGS_PRIOR_CF:
return "PRIOR_CF"
elif eflag == X86_EFLAGS_PRIOR_TF:
return "PRIOR_TF"
elif eflag == X86_EFLAGS_PRIOR_IF:
return "PRIOR_IF"
elif eflag == X86_EFLAGS_PRIOR_DF:
return "PRIOR_DF"
elif eflag == X86_EFLAGS_TEST_NT:
return "TEST_NT"
elif eflag == X86_EFLAGS_TEST_DF:
return "TEST_DF"
elif eflag == X86_EFLAGS_RESET_PF:
return "RESET_PF"
elif eflag == X86_EFLAGS_PRIOR_NT:
return "PRIOR_NT"
elif eflag == X86_EFLAGS_MODIFY_TF:
return "MOD_TF"
elif eflag == X86_EFLAGS_MODIFY_IF:
return "MOD_IF"
elif eflag == X86_EFLAGS_MODIFY_DF:
return "MOD_DF"
elif eflag == X86_EFLAGS_MODIFY_NT:
return "MOD_NT"
elif eflag == X86_EFLAGS_MODIFY_RF:
return "MOD_RF"
elif eflag == X86_EFLAGS_SET_CF:
return "SET_CF"
elif eflag == X86_EFLAGS_SET_DF:
return "SET_DF"
elif eflag == X86_EFLAGS_SET_IF:
return "SET_IF"
else:
return None
def print_insn_detail(mode, insn):
def print_string_hex(comment, str):
print(comment, end=' '),
for c in str:
print("0x%02x " % c, end=''),
print()
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
# print instruction prefix
print_string_hex("\tPrefix:", insn.prefix)
# print instruction's opcode
print_string_hex("\tOpcode:", insn.opcode)
# print operand's REX prefix (non-zero value is relavant for x86_64 instructions)
print("\trex: 0x%x" % (insn.rex))
# print operand's address size
print("\taddr_size: %u" % (insn.addr_size))
# print modRM byte
print("\tmodrm: 0x%x" % (insn.modrm))
# print modRM offset
if insn.modrm_offset != 0:
print("\tmodrm_offset: 0x%x" % (insn.modrm_offset))
# print displacement value
print("\tdisp: 0x%s" % to_x_32(insn.disp))
# print displacement offset (offset into instruction bytes)
if insn.disp_offset != 0:
print("\tdisp_offset: 0x%x" % (insn.disp_offset))
# print displacement size
if insn.disp_size != 0:
print("\tdisp_size: 0x%x" % (insn.disp_size))
# SIB is not available in 16-bit mode
if (mode & CS_MODE_16 == 0):
# print SIB byte
print("\tsib: 0x%x" % (insn.sib))
if (insn.sib):
if insn.sib_base != 0:
print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base)))
if insn.sib_index != 0:
print("\t\tsib_index: %s" % (insn.reg_name(insn.sib_index)))
if insn.sib_scale != 0:
print("\t\tsib_scale: %d" % (insn.sib_scale))
# XOP CC type
if insn.xop_cc != X86_XOP_CC_INVALID:
print("\txop_cc: %u" % (insn.xop_cc))
# SSE CC type
if insn.sse_cc != X86_SSE_CC_INVALID:
print("\tsse_cc: %u" % (insn.sse_cc))
# AVX CC type
if insn.avx_cc != X86_AVX_CC_INVALID:
print("\tavx_cc: %u" % (insn.avx_cc))
# AVX Suppress All Exception
if insn.avx_sae:
print("\tavx_sae: TRUE")
# AVX Rounding Mode type
if insn.avx_rm != X86_AVX_RM_INVALID:
print("\tavx_rm: %u" % (insn.avx_rm))
count = insn.op_count(X86_OP_IMM)
if count > 0:
print("\timm_count: %u" % count)
for i in range(count):
op = insn.op_find(X86_OP_IMM, i + 1)
print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
if insn.imm_offset != 0:
print("\timm_offset: 0x%x" % (insn.imm_offset))
if insn.imm_size != 0:
print("\timm_size: 0x%x" % (insn.imm_size))
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == X86_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == X86_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == X86_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.segment != 0:
print("\t\t\toperands[%u].mem.segment: REG = %s" % (c, insn.reg_name(i.mem.segment)))
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index)))
if i.mem.scale != 1:
print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp)))
# AVX broadcast type
if i.avx_bcast != X86_AVX_BCAST_INVALID:
print("\t\toperands[%u].avx_bcast: %u" % (c, i.avx_bcast))
# AVX zero opmask {z}
if i.avx_zero_opmask:
print("\t\toperands[%u].avx_zero_opmask: TRUE" % (c))
print("\t\toperands[%u].size: %u" % (c, i.size))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if insn.eflags:
updated_flags = []
for i in range(0,46):
if insn.eflags & (1 << i):
updated_flags.append(get_eflag_name(1 << i))
print("\tEFLAGS: %s" % (','.join(p for p in updated_flags)))
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
if syntax is not None:
md.syntax = syntax
for insn in md.disasm(code, 0x1000):
print_insn_detail(mode, insn)
print ()
print ("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_x86.py
|
#!/usr/bin/env python
import glob
import os
import shutil
import sys
import platform
from distutils import log
from setuptools import setup
from distutils.util import get_platform
from distutils.command.build import build
from distutils.command.sdist import sdist
from setuptools.command.bdist_egg import bdist_egg
SYSTEM = sys.platform
# adapted from commit e504b81 of Nguyen Tan Cong
# Reference: https://docs.python.org/2/library/platform.html#cross-platform
IS_64BITS = sys.maxsize > 2**32
# are we building from the repository or from a source distribution?
ROOT_DIR = os.path.dirname(os.path.realpath(__file__))
LIBS_DIR = os.path.join(ROOT_DIR, 'capstone', 'lib')
HEADERS_DIR = os.path.join(ROOT_DIR, 'capstone', 'include')
SRC_DIR = os.path.join(ROOT_DIR, 'src')
BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..')
# Parse version from pkgconfig.mk
VERSION_DATA = {}
with open(os.path.join(BUILD_DIR, 'pkgconfig.mk')) as fp:
lines = fp.readlines()
for line in lines:
line = line.strip()
if len(line) == 0:
continue
if line.startswith('#'):
continue
if '=' not in line:
continue
k, v = line.split('=', 1)
k = k.strip()
v = v.strip()
if len(k) == 0 or len(v) == 0:
continue
VERSION_DATA[k] = v
if 'PKG_MAJOR' not in VERSION_DATA or \
'PKG_MINOR' not in VERSION_DATA or \
'PKG_EXTRA' not in VERSION_DATA:
raise Exception("Malformed pkgconfig.mk")
if 'PKG_TAG' in VERSION_DATA:
VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}.{PKG_TAG}'.format(**VERSION_DATA)
else:
VERSION = '{PKG_MAJOR}.{PKG_MINOR}.{PKG_EXTRA}'.format(**VERSION_DATA)
if SYSTEM == 'darwin':
VERSIONED_LIBRARY_FILE = "libcapstone.{PKG_MAJOR}.dylib".format(**VERSION_DATA)
LIBRARY_FILE = "libcapstone.dylib"
STATIC_LIBRARY_FILE = 'libcapstone.a'
elif SYSTEM in ('win32', 'cygwin'):
VERSIONED_LIBRARY_FILE = "capstone.dll"
LIBRARY_FILE = "capstone.dll"
STATIC_LIBRARY_FILE = None
else:
VERSIONED_LIBRARY_FILE = "libcapstone.so.{PKG_MAJOR}".format(**VERSION_DATA)
LIBRARY_FILE = "libcapstone.so"
STATIC_LIBRARY_FILE = 'libcapstone.a'
def clean_bins():
shutil.rmtree(LIBS_DIR, ignore_errors=True)
shutil.rmtree(HEADERS_DIR, ignore_errors=True)
def copy_sources():
"""Copy the C sources into the source directory.
This rearranges the source files under the python distribution
directory.
"""
src = []
try:
shutil.rmtree("src/")
except (IOError, OSError):
pass
shutil.copytree(os.path.join(BUILD_DIR, "arch"), os.path.join(SRC_DIR, "arch"))
shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include"))
src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "*.mk")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "Makefile")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSE*")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "README")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "make.sh")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt")))
src.extend(glob.glob(os.path.join(BUILD_DIR, "pkgconfig.mk")))
for filename in src:
outpath = os.path.join(SRC_DIR, os.path.basename(filename))
log.info("%s -> %s" % (filename, outpath))
shutil.copy(filename, outpath)
def build_libraries():
"""
Prepare the capstone directory for a binary distribution or installation.
Builds shared libraries and copies header files.
Will use a src/ dir if one exists in the current directory, otherwise assumes it's in the repo
"""
cwd = os.getcwd()
clean_bins()
os.mkdir(HEADERS_DIR)
os.mkdir(LIBS_DIR)
# copy public headers
shutil.copytree(os.path.join(BUILD_DIR, 'include', 'capstone'), os.path.join(HEADERS_DIR, 'capstone'))
# if prebuilt libraries are available, use those and cancel build
if os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE)) and \
(not STATIC_LIBRARY_FILE or os.path.exists(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE))):
shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', LIBRARY_FILE), LIBS_DIR)
if STATIC_LIBRARY_FILE is not None:
shutil.copy(os.path.join(ROOT_DIR, 'prebuilt', STATIC_LIBRARY_FILE), LIBS_DIR)
return
os.chdir(BUILD_DIR)
# platform description refers at https://docs.python.org/2/library/sys.html#sys.platform
if SYSTEM == "win32":
# Windows build: this process requires few things:
# - CMake + MSVC installed
# - Run this command in an environment setup for MSVC
if not os.path.exists("build"): os.mkdir("build")
os.chdir("build")
# Do not build tests & static library
os.system('cmake -DCMAKE_BUILD_TYPE=RELEASE -DCAPSTONE_BUILD_TESTS=0 -DCAPSTONE_BUILD_STATIC=0 -G "NMake Makefiles" ..')
os.system("nmake")
else: # Unix incl. cygwin
os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh")
shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE))
# only copy static library if it exists (it's a build option)
if STATIC_LIBRARY_FILE and os.path.exists(STATIC_LIBRARY_FILE):
shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR)
os.chdir(cwd)
class custom_sdist(sdist):
def run(self):
clean_bins()
copy_sources()
return sdist.run(self)
class custom_build(build):
def run(self):
if 'LIBCAPSTONE_PATH' in os.environ:
log.info('Skipping building C extensions since LIBCAPSTONE_PATH is set')
else:
log.info('Building C extensions')
build_libraries()
return build.run(self)
class custom_bdist_egg(bdist_egg):
def run(self):
self.run_command('build')
return bdist_egg.run(self)
def dummy_src():
return []
cmdclass = {}
cmdclass['build'] = custom_build
cmdclass['sdist'] = custom_sdist
cmdclass['bdist_egg'] = custom_bdist_egg
try:
from setuptools.command.develop import develop
class custom_develop(develop):
def run(self):
log.info("Building C extensions")
build_libraries()
return develop.run(self)
cmdclass['develop'] = custom_develop
except ImportError:
print("Proper 'develop' support unavailable.")
if 'bdist_wheel' in sys.argv and '--plat-name' not in sys.argv:
idx = sys.argv.index('bdist_wheel') + 1
sys.argv.insert(idx, '--plat-name')
name = get_platform()
if 'linux' in name:
# linux_* platform tags are disallowed because the python ecosystem is fubar
# linux builds should be built in the centos 5 vm for maximum compatibility
# see https://github.com/pypa/manylinux
# see also https://github.com/angr/angr-dev/blob/master/bdist.sh
sys.argv.insert(idx + 1, 'manylinux1_' + platform.machine())
else:
# https://www.python.org/dev/peps/pep-0425/
sys.argv.insert(idx + 1, name.replace('.', '_').replace('-', '_'))
setup(
provides=['capstone'],
packages=['capstone'],
name='capstone',
version=VERSION,
author='Nguyen Anh Quynh',
author_email='aquynh@gmail.com',
description='Capstone disassembly engine',
url='http://www.capstone-engine.org',
python_requires='>=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*',
classifiers=[
'License :: OSI Approved :: BSD License',
'Programming Language :: Python :: 2',
'Programming Language :: Python :: 2.7',
'Programming Language :: Python :: 3',
],
requires=['ctypes'],
cmdclass=cmdclass,
zip_safe=True,
include_package_data=True,
package_data={
"capstone": ["lib/*", "include/capstone/*"],
}
)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/setup.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from xprint import to_hex
X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
)
# ## Test cs_disasm_quick()
def test_cs_disasm_quick():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 40)
print("Platform: %s" % comment)
print("Disasm:"),
print(to_hex(code))
for (addr, size, mnemonic, op_str) in cs_disasm_lite(arch, mode, code, 0x1000):
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
print()
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print('*' * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
for (addr, size, mnemonic, op_str) in md.disasm_lite(code, 0x1000):
print("0x%x:\t%s\t%s" % (addr, mnemonic, op_str))
print("0x%x:" % (addr + size))
print()
except CsError as e:
print("ERROR: %s" % e)
# test_cs_disasm_quick()
# print "*" * 40
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_lite.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.sparc import *
from xprint import to_hex, to_x_32
SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
all_tests = (
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc"),
(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN+CS_MODE_V9, SPARCV9_CODE, "SparcV9"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == SPARC_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == SPARC_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
if i.type == SPARC_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
c += 1
if insn.cc:
print("\tCode condition: %u" % insn.cc)
if insn.hint:
print("\tHint code: %u" % insn.hint)
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" %e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_sparc.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.systemz import *
from xprint import to_x, to_hex
SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f"
all_tests = (
(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == SYSZ_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == SYSZ_OP_ACREG:
print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg))
if i.type == SYSZ_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == SYSZ_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.length != 0:
print("\t\t\toperands[%u].mem.length: 0x%s" \
% (c, to_x(i.mem.length)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
c += 1
if insn.cc:
print("\tConditional code: %u" % insn.cc)
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" %e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_systemz.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
import sys
_python3 = sys.version_info.major == 3
def to_hex(s, prefix_0x = True):
if _python3:
if prefix_0x:
return " ".join("0x{0:02x}".format(c) for c in s) # <-- Python 3 is OK
else:
return " ".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK
else:
if prefix_0x:
return " ".join("0x{0:02x}".format(ord(c)) for c in s)
else:
return " ".join("{0:02x}".format(ord(c)) for c in s)
def to_hex2(s):
if _python3:
r = "".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK
else:
r = "".join("{0:02x}".format(ord(c)) for c in s)
while r[0] == '0': r = r[1:]
return r
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s)
while x[0] in ('\0', 0): x = x[1:]
return to_hex2(x)
def to_x_32(s):
from struct import pack
if not s: return '0'
x = pack(">i", s)
while x[0] in ('\0', 0): x = x[1:]
return to_hex2(x)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/xprint.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.mips import *
from xprint import to_hex, to_x
MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
all_tests = (
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == MIPS_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == MIPS_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == MIPS_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_mips.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.xcore import *
from xprint import to_x, to_hex
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
all_tests = (
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == XCORE_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == XCORE_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == XCORE_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
if i.mem.direct != 1:
print("\t\t\toperands[%u].mem.direct: -1" % c)
c += 1
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" %e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_xcore.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.arm import *
from xprint import to_hex, to_x_32
ARM_CODE = b"\x86\x48\x60\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
THUMB_CODE = b"\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
THUMB_MCLASS = b"\xef\xf3\x02\x80"
ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
all_tests = (
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None),
(CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME),
(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == ARM_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == ARM_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
if i.type == ARM_OP_PIMM:
print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
if i.type == ARM_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
if i.type == ARM_OP_FP:
print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == ARM_OP_SYSREG:
print("\t\toperands[%u].type: SYSREG = %u" % (c, i.reg))
if i.type == ARM_OP_SETEND:
if i.setend == ARM_SETEND_BE:
print("\t\toperands[%u].type: SETEND = be" % c)
else:
print("\t\toperands[%u].type: SETEND = le" % c)
if i.type == ARM_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.scale != 1:
print("\t\t\toperands[%u].mem.scale: %u" \
% (c, i.mem.scale))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
if i.mem.lshift != 0:
print("\t\t\toperands[%u].mem.lshift: 0x%s" \
% (c, to_x_32(i.mem.lshift)))
if i.neon_lane != -1:
print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane))
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
if i.shift.type != ARM_SFT_INVALID and i.shift.value:
print("\t\t\tShift: %u = %u" \
% (i.shift.type, i.shift.value))
if i.vector_index != -1:
print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index))
if i.subtracted:
print("\t\t\toperands[%u].subtracted = True" %c)
c += 1
if insn.update_flags:
print("\tUpdate-flags: True")
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
print("\tCode condition: %u" % insn.cc)
if insn.cps_mode:
print("\tCPSI-mode: %u" %(insn.cps_mode))
if insn.cps_flag:
print("\tCPSI-flag: %u" %(insn.cps_flag))
if insn.vector_data:
print("\tVector-data: %u" %(insn.vector_data))
if insn.vector_size:
print("\tVector-size: %u" %(insn.vector_size))
if insn.usermode:
print("\tUser-mode: True")
if insn.mem_barrier:
print("\tMemory-barrier: %u" %(insn.mem_barrier))
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
md.detail = True
for insn in md.disasm(code, 0x80001000):
print_insn_detail(insn)
print ()
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_arm.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.arm64 import *
from xprint import to_hex, to_x
ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
all_tests = (
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = -1
for i in insn.operands:
c += 1
if i.type == ARM64_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == ARM64_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == ARM64_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
if i.type == ARM64_OP_FP:
print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
if i.type == ARM64_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
if i.type == ARM64_OP_REG_MRS:
print("\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg))
if i.type == ARM64_OP_REG_MSR:
print("\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg))
if i.type == ARM64_OP_PSTATE:
print("\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate))
if i.type == ARM64_OP_SYS:
print("\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
if i.type == ARM64_OP_PREFETCH:
print("\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch))
if i.type == ARM64_OP_BARRIER:
print("\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier))
if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
if i.ext != ARM64_EXT_INVALID:
print("\t\t\tExt: %u" % i.ext)
if i.vas != ARM64_VAS_INVALID:
print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
if i.vector_index != -1:
print("\t\t\tVector Index: %u" % i.vector_index)
if i.access == CS_AC_READ:
print("\t\toperands[%u].access: READ\n" % (c))
elif i.access == CS_AC_WRITE:
print("\t\toperands[%u].access: WRITE\n" % (c))
elif i.access == CS_AC_READ | CS_AC_WRITE:
print("\t\toperands[%u].access: READ | WRITE\n" % (c))
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x2c):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_arm64.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net>
from __future__ import print_function
import sys
from capstone import *
from capstone.m680x import *
_python3 = sys.version_info.major == 3
s_access = (
"UNCHANGED", "READ", "WRITE", "READ | WRITE",
)
M6800_CODE = b"\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39"
M6801_CODE = b"\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39"
M6805_CODE = b"\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe"
M6808_CODE = b"\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f"
HCS08_CODE = b"\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82"
HD6301_CODE = b"\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39"
M6809_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00"
M6811_CODE = b"\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f"
CPU12_CODE = b"\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00"
HD6309_CODE = b"\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00"
all_tests = (
(CS_ARCH_M680X, CS_MODE_M680X_6301, HD6301_CODE, "M680X_HD6301", None),
(CS_ARCH_M680X, CS_MODE_M680X_6309, HD6309_CODE, "M680X_HD6309", None),
(CS_ARCH_M680X, CS_MODE_M680X_6800, M6800_CODE, "M680X_M6800", None),
(CS_ARCH_M680X, CS_MODE_M680X_6801, M6801_CODE, "M680X_M6801", None),
(CS_ARCH_M680X, CS_MODE_M680X_6805, M6805_CODE, "M680X_M68HC05", None),
(CS_ARCH_M680X, CS_MODE_M680X_6808, M6808_CODE, "M680X_M68HC08", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M6809_CODE, "M680X_M6809", None),
(CS_ARCH_M680X, CS_MODE_M680X_6811, M6811_CODE, "M680X_M68HC11", None),
(CS_ARCH_M680X, CS_MODE_M680X_CPU12, CPU12_CODE, "M680X_CPU12", None),
(CS_ARCH_M680X, CS_MODE_M680X_HCS08, HCS08_CODE, "M680X_HCS08", None),
)
# print hex dump from string all upper case
def to_hex_uc(string):
if _python3:
return " ".join("0x%02x" % c for c in string)
else:
return " ".join("0x%02x" % ord(c) for c in string)
# print short hex dump from byte array all upper case
def to_hex_short_uc(byte_array):
return "".join("%02x" % b for b in byte_array)
def print_insn_detail(insn):
# print address, mnemonic and operands
#print("0x%x:\t%s\t%s\t%s" % (insn.address, binascii.hexlify(bytearray(insn.bytes)), \
print("0x%04x: %s\t%s\t%s" % (insn.address, to_hex_short_uc(insn.bytes), \
insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == M680X_OP_REGISTER:
comment = "";
if (((c == 0) and (insn.flags & M680X_FIRST_OP_IN_MNEM)) or
((c == 1) and (insn.flags & M680X_SECOND_OP_IN_MNEM))):
comment = " (in mnemonic)";
print("\t\toperands[%u].type: REGISTER = %s%s" % (c,
insn.reg_name(i.reg), comment))
if i.type == M680X_OP_CONSTANT:
print("\t\toperands[%u].type: CONSTANT = %u" % (c, i.const_val))
if i.type == M680X_OP_IMMEDIATE:
print("\t\toperands[%u].type: IMMEDIATE = #%d" % (c, i.imm))
if i.type == M680X_OP_DIRECT:
print("\t\toperands[%u].type: DIRECT = 0x%02x" % (c, i.direct_addr))
if i.type == M680X_OP_EXTENDED:
if i.ext.indirect:
indirect = "INDIRECT"
else:
indirect = ""
print("\t\toperands[%u].type: EXTENDED %s = 0x%04x" % (c, indirect, i.ext.address))
if i.type == M680X_OP_RELATIVE:
print("\t\toperands[%u].type: RELATIVE = 0x%04x" % (c, i.rel.address))
if i.type == M680X_OP_INDEXED:
if (i.idx.flags & M680X_IDX_INDIRECT):
indirect = " INDIRECT"
else:
indirect = ""
print("\t\toperands[%u].type: INDEXED%s" % (c, indirect))
if i.idx.base_reg != M680X_REG_INVALID:
print("\t\t\tbase register: %s" % insn.reg_name(i.idx.base_reg))
if i.idx.offset_reg != M680X_REG_INVALID:
print("\t\t\toffset register: %s" % insn.reg_name(i.idx.offset_reg))
if (i.idx.offset_bits != 0) and (i.idx.offset_reg == M680X_REG_INVALID) and (i.idx.inc_dec == 0):
print("\t\t\toffset: %u" % i.idx.offset)
if i.idx.base_reg == M680X_REG_PC:
print("\t\t\toffset address: 0x%04x" % i.idx.offset_addr)
print("\t\t\toffset bits: %u" % i.idx.offset_bits)
if i.idx.inc_dec != 0:
if i.idx.flags & M680X_IDX_POST_INC_DEC:
s_post_pre = "post"
else:
s_post_pre = "pre"
if i.idx.inc_dec > 0:
s_inc_dec = "increment"
else:
s_inc_dec = "decrement"
print("\t\t\t%s %s: %d" %
(s_post_pre, s_inc_dec, abs(i.idx.inc_dec)))
if (i.size != 0):
print("\t\t\tsize: %d" % i.size)
if (i.access != CS_AC_INVALID):
print("\t\t\taccess: %s" % s_access[i.access])
c += 1
(regs_read, regs_write) = insn.regs_access()
if len(regs_read) > 0:
print("\tRegisters read:", end="")
for r in regs_read:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(regs_write) > 0:
print("\tRegisters modified:", end="")
for r in regs_write:
print(" %s" %(insn.reg_name(r)), end="")
print("")
if len(insn.groups) > 0:
print("\tgroups_count: %u" % len(insn.groups))
# ## Test class Cs
def test_class():
for (arch, mode, code, comment, syntax) in all_tests:
print("*" * 20)
print("Platform: %s" % comment)
print("Code: %s" % to_hex_uc(code))
print("Disasm:")
try:
md = Cs(arch, mode)
if syntax is not None:
md.syntax = syntax
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_m680x.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.riscv import *
from xprint import to_x, to_hex
RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
RISCV_CODE64 = b"\x13\x04\xa8\x7a"
all_tests = (
(CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "riscv32"),
(CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "riscv64"),
)
def print_insn_detail(insn):
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0:
return
if len(insn.operands) > 0:
print("\top_count: %u" % len(insn.operands))
c = 0
for i in insn.operands:
if i.type == RISCV_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
if i.type == RISCV_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
if i.type == RISCV_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
c += 1
# ## Test class Cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
print ()
print("0x%x:\n" % (insn.address + insn.size))
except CsError as e:
print("ERROR: %s" %e)
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_riscv.py
|
import os
import sys
import shutil
from distutils import log
from distutils.core import setup
from distutils.extension import Extension
from distutils.command.build import build
from Cython.Distutils import build_ext
SYSTEM = sys.platform
VERSION = '4.0.0'
# adapted from commit e504b81 of Nguyen Tan Cong
# Reference: https://docs.python.org/2/library/platform.html#cross-platform
IS_64BITS = sys.maxsize > 2**32
# are we building from the repository or from a source distribution?
ROOT_DIR = os.path.dirname(os.path.realpath(__file__))
LIBS_DIR = os.path.join(ROOT_DIR, 'pyx', 'lib')
HEADERS_DIR = os.path.join(ROOT_DIR, 'pyx', 'include')
SRC_DIR = os.path.join(ROOT_DIR, 'src')
BUILD_DIR = SRC_DIR if os.path.exists(SRC_DIR) else os.path.join(ROOT_DIR, '../..')
PYPACKAGE_DIR = os.path.join(ROOT_DIR, 'capstone')
CYPACKAGE_DIR = os.path.join(ROOT_DIR, 'pyx')
if SYSTEM == 'darwin':
VERSIONED_LIBRARY_FILE = "libcapstone.4.dylib"
LIBRARY_FILE = "libcapstone.dylib"
STATIC_LIBRARY_FILE = 'libcapstone.a'
elif SYSTEM in ('win32', 'cygwin'):
VERSIONED_LIBRARY_FILE = "capstone.dll"
LIBRARY_FILE = "capstone.dll"
STATIC_LIBRARY_FILE = None
else:
VERSIONED_LIBRARY_FILE = "libcapstone.so.4"
LIBRARY_FILE = "libcapstone.so"
STATIC_LIBRARY_FILE = 'libcapstone.a'
compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR]
link_args = ['-L' + LIBS_DIR]
ext_module_names = ['arm', 'arm_const', 'arm64', 'arm64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const' ]
ext_modules = [Extension("capstone.ccapstone",
["pyx/ccapstone.pyx"],
libraries=["capstone"],
extra_compile_args=compile_args,
extra_link_args=link_args)]
ext_modules += [Extension("capstone.%s" % name,
["pyx/%s.pyx" % name],
extra_compile_args=compile_args,
extra_link_args=link_args)
for name in ext_module_names]
def clean_bins():
shutil.rmtree(LIBS_DIR, ignore_errors=True)
shutil.rmtree(HEADERS_DIR, ignore_errors=True)
def copy_pysources():
for fname in os.listdir(PYPACKAGE_DIR):
if not fname.endswith('.py'):
continue
if fname == '__init__.py':
shutil.copy(os.path.join(PYPACKAGE_DIR, fname), os.path.join(CYPACKAGE_DIR, fname))
else:
shutil.copy(os.path.join(PYPACKAGE_DIR, fname), os.path.join(CYPACKAGE_DIR, fname + 'x'))
def build_libraries():
"""
Prepare the capstone directory for a binary distribution or installation.
Builds shared libraries and copies header files.
Will use a src/ dir if one exists in the current directory, otherwise assumes it's in the repo
"""
cwd = os.getcwd()
clean_bins()
os.mkdir(HEADERS_DIR)
os.mkdir(LIBS_DIR)
# copy public headers
shutil.copytree(os.path.join(BUILD_DIR, 'include', 'capstone'), os.path.join(HEADERS_DIR, 'capstone'))
os.chdir(BUILD_DIR)
# platform description refers at https://docs.python.org/2/library/sys.html#sys.platform
if SYSTEM == "win32":
# Windows build: this process requires few things:
# - CMake + MSVC installed
# - Run this command in an environment setup for MSVC
if not os.path.exists("build"): os.mkdir("build")
os.chdir("build")
# Do not build tests & static library
os.system('cmake -DCMAKE_BUILD_TYPE=RELEASE -DCAPSTONE_BUILD_TESTS=0 -DCAPSTONE_BUILD_STATIC=0 -G "NMake Makefiles" ..')
os.system("nmake")
else: # Unix incl. cygwin
os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh")
shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE))
if STATIC_LIBRARY_FILE: shutil.copy(STATIC_LIBRARY_FILE, LIBS_DIR)
os.chdir(cwd)
class custom_build(build):
def run(self):
log.info('Copying python sources')
copy_pysources()
log.info('Building C extensions')
build_libraries()
return build.run(self)
# clean package directory first
#import os.path, shutil, sys
#for f in sys.path:
# if f.endswith('packages'):
# pkgdir = os.path.join(f, 'capstone')
# #print(pkgdir)
# try:
# shutil.rmtree(pkgdir)
# except:
# pass
setup(
provides = ['capstone'],
package_dir = {'capstone' : 'pyx'},
packages = ['capstone'],
name = 'capstone',
version = VERSION,
cmdclass = {'build_ext': build_ext, 'build': custom_build},
ext_modules = ext_modules,
author = 'Nguyen Anh Quynh',
author_email = 'aquynh@gmail.com',
description = 'Capstone disassembly engine',
url = 'http://www.capstone-engine.org',
classifiers = [
'License :: OSI Approved :: BSD License',
'Programming Language :: Python :: 2',
],
include_package_data=True,
package_data={
"capstone": ["lib/*", "include/capstone/*"],
}
)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/setup_cython.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.x86 import *
from xprint import to_hex
X86_CODE32 = b"\x75\x01"
def print_insn(md, code):
print("%s\t" % to_hex(code, False), end="")
for insn in md.disasm(code, 0x1000):
print("\t%s\t%s\n" % (insn.mnemonic, insn.op_str))
def test():
try:
md = Cs(CS_ARCH_X86, CS_MODE_32)
print("Disassemble X86 code with default instruction mnemonic")
print_insn(md, X86_CODE32)
print("Now customize engine to change mnemonic from 'JNE' to 'JNZ'")
md.mnemonic_setup(X86_INS_JNE, "jnz")
print_insn(md, X86_CODE32)
print("Reset engine to use the default mnemonic")
md.mnemonic_setup(X86_INS_JNE, None)
print_insn(md, X86_CODE32)
except CsError as e:
print("ERROR: %s" % e)
if __name__ == '__main__':
test()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_customized_mnem.py
|
#!/usr/bin/env python
# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
from __future__ import print_function
from capstone import *
from capstone.m68k import *
from xprint import to_hex, to_x
M68K_CODE = b"\x4c\x00\x54\x04\x48\xe7\xe0\x30\x4c\xdf\x0c\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4e\xb9\x00\x00\x00\x12\x4e\x75"
all_tests = (
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"),
)
s_addressing_modes = {
0: "<invalid mode>",
1: "Register Direct - Data",
2: "Register Direct - Address",
3: "Register Indirect - Address",
4: "Register Indirect - Address with Postincrement",
5: "Register Indirect - Address with Predecrement",
6: "Register Indirect - Address with Displacement",
7: "Address Register Indirect With Index - 8-bit displacement",
8: "Address Register Indirect With Index - Base displacement",
9: "Memory indirect - Postindex",
10: "Memory indirect - Preindex",
11: "Program Counter Indirect - with Displacement",
12: "Program Counter Indirect with Index - with 8-Bit Displacement",
13: "Program Counter Indirect with Index - with Base Displacement",
14: "Program Counter Memory Indirect - Postindexed",
15: "Program Counter Memory Indirect - Preindexed",
16: "Absolute Data Addressing - Short",
17: "Absolute Data Addressing - Long",
18: "Immediate value",
19: "Branch Displacement",
}
def print_read_write_regs(insn):
for m in insn.regs_read:
print("\treading from reg: %s" % insn.reg_name(m))
for m in insn.regs_write:
print("\twriting to reg: %s" % insn.reg_name(m))
def print_insn_detail(insn):
if len(insn.operands) > 0:
print("\top_count: %u" % (len(insn.operands)))
print("\tgroups_count: %u" % len(insn.groups))
print_read_write_regs(insn)
for i, op in enumerate(insn.operands):
if op.type == M68K_OP_REG:
print("\t\toperands[%u].type: REG = %s" % (i, insn.reg_name(op.reg)))
elif op.type == M68K_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%x" % (i, op.imm & 0xffffffff))
elif op.type == M68K_OP_MEM:
print("\t\toperands[%u].type: MEM" % (i))
if op.mem.base_reg != M68K_REG_INVALID:
print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg)))
if op.mem.index_reg != M68K_REG_INVALID:
print("\t\t\toperands[%u].mem.index: REG = %s" % (i, insn.reg_name(op.mem.index_reg)))
mem_index_str = "w"
if op.mem.index_size > 0:
mem_index_str = "l"
print("\t\t\toperands[%u].mem.index: size = %s" % (i, mem_index_str))
if op.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%x" % (i, op.mem.disp))
if op.mem.scale != 0:
print("\t\t\toperands[%u].mem.scale: %d" % (i, op.mem.scale))
print("\t\taddress mode: %s" % (s_addressing_modes[op.address_mode]))
elif op.type == M68K_OP_FP_SINGLE:
print("\t\toperands[%u].type: FP_SINGLE" % i)
print("\t\toperands[%u].simm: %f", i, op.simm)
elif op.type == M68K_OP_FP_DOUBLE:
print("\t\toperands[%u].type: FP_DOUBLE" % i)
print("\t\toperands[%u].dimm: %lf", i, op.dimm)
elif op.type == M68K_OP_BR_DISP:
print("\t\toperands[%u].br_disp.disp: 0x%x" % (i, op.br_disp.disp))
print("\t\toperands[%u].br_disp.disp_size: %d" % (i, op.br_disp.disp_size))
print()
# ## Test class Cs
def test_class():
address = 0x01000
for (arch, mode, code, comment) in all_tests:
print("*" * 16)
print("Platform: %s" % comment)
print("Code: %s " % to_hex(code))
print("Disasm:")
try:
md = Cs(arch, mode)
md.detail = True
last_address = 0
for insn in md.disasm(code, address):
last_address = insn.address + insn.size
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
print_insn_detail(insn)
print("0x%x:\n" % (last_address))
except CsError as e:
print("ERROR: %s" % e.__str__())
if __name__ == '__main__':
test_class()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/test_m68k.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py]
M680X_OPERAND_COUNT = 9
M680X_REG_INVALID = 0
M680X_REG_A = 1
M680X_REG_B = 2
M680X_REG_E = 3
M680X_REG_F = 4
M680X_REG_0 = 5
M680X_REG_D = 6
M680X_REG_W = 7
M680X_REG_CC = 8
M680X_REG_DP = 9
M680X_REG_MD = 10
M680X_REG_HX = 11
M680X_REG_H = 12
M680X_REG_X = 13
M680X_REG_Y = 14
M680X_REG_S = 15
M680X_REG_U = 16
M680X_REG_V = 17
M680X_REG_Q = 18
M680X_REG_PC = 19
M680X_REG_TMP2 = 20
M680X_REG_TMP3 = 21
M680X_REG_ENDING = 22
M680X_OP_INVALID = 0
M680X_OP_REGISTER = 1
M680X_OP_IMMEDIATE = 2
M680X_OP_INDEXED = 3
M680X_OP_EXTENDED = 4
M680X_OP_DIRECT = 5
M680X_OP_RELATIVE = 6
M680X_OP_CONSTANT = 7
M680X_OFFSET_NONE = 0
M680X_OFFSET_BITS_5 = 5
M680X_OFFSET_BITS_8 = 8
M680X_OFFSET_BITS_9 = 9
M680X_OFFSET_BITS_16 = 16
M680X_IDX_INDIRECT = 1
M680X_IDX_NO_COMMA = 2
M680X_IDX_POST_INC_DEC = 4
M680X_GRP_INVALID = 0
M680X_GRP_JUMP = 1
M680X_GRP_CALL = 2
M680X_GRP_RET = 3
M680X_GRP_INT = 4
M680X_GRP_IRET = 5
M680X_GRP_PRIV = 6
M680X_GRP_BRAREL = 7
M680X_GRP_ENDING = 8
M680X_FIRST_OP_IN_MNEM = 1
M680X_SECOND_OP_IN_MNEM = 2
M680X_INS_INVLD = 0
M680X_INS_ABA = 1
M680X_INS_ABX = 2
M680X_INS_ABY = 3
M680X_INS_ADC = 4
M680X_INS_ADCA = 5
M680X_INS_ADCB = 6
M680X_INS_ADCD = 7
M680X_INS_ADCR = 8
M680X_INS_ADD = 9
M680X_INS_ADDA = 10
M680X_INS_ADDB = 11
M680X_INS_ADDD = 12
M680X_INS_ADDE = 13
M680X_INS_ADDF = 14
M680X_INS_ADDR = 15
M680X_INS_ADDW = 16
M680X_INS_AIM = 17
M680X_INS_AIS = 18
M680X_INS_AIX = 19
M680X_INS_AND = 20
M680X_INS_ANDA = 21
M680X_INS_ANDB = 22
M680X_INS_ANDCC = 23
M680X_INS_ANDD = 24
M680X_INS_ANDR = 25
M680X_INS_ASL = 26
M680X_INS_ASLA = 27
M680X_INS_ASLB = 28
M680X_INS_ASLD = 29
M680X_INS_ASR = 30
M680X_INS_ASRA = 31
M680X_INS_ASRB = 32
M680X_INS_ASRD = 33
M680X_INS_ASRX = 34
M680X_INS_BAND = 35
M680X_INS_BCC = 36
M680X_INS_BCLR = 37
M680X_INS_BCS = 38
M680X_INS_BEOR = 39
M680X_INS_BEQ = 40
M680X_INS_BGE = 41
M680X_INS_BGND = 42
M680X_INS_BGT = 43
M680X_INS_BHCC = 44
M680X_INS_BHCS = 45
M680X_INS_BHI = 46
M680X_INS_BIAND = 47
M680X_INS_BIEOR = 48
M680X_INS_BIH = 49
M680X_INS_BIL = 50
M680X_INS_BIOR = 51
M680X_INS_BIT = 52
M680X_INS_BITA = 53
M680X_INS_BITB = 54
M680X_INS_BITD = 55
M680X_INS_BITMD = 56
M680X_INS_BLE = 57
M680X_INS_BLS = 58
M680X_INS_BLT = 59
M680X_INS_BMC = 60
M680X_INS_BMI = 61
M680X_INS_BMS = 62
M680X_INS_BNE = 63
M680X_INS_BOR = 64
M680X_INS_BPL = 65
M680X_INS_BRCLR = 66
M680X_INS_BRSET = 67
M680X_INS_BRA = 68
M680X_INS_BRN = 69
M680X_INS_BSET = 70
M680X_INS_BSR = 71
M680X_INS_BVC = 72
M680X_INS_BVS = 73
M680X_INS_CALL = 74
M680X_INS_CBA = 75
M680X_INS_CBEQ = 76
M680X_INS_CBEQA = 77
M680X_INS_CBEQX = 78
M680X_INS_CLC = 79
M680X_INS_CLI = 80
M680X_INS_CLR = 81
M680X_INS_CLRA = 82
M680X_INS_CLRB = 83
M680X_INS_CLRD = 84
M680X_INS_CLRE = 85
M680X_INS_CLRF = 86
M680X_INS_CLRH = 87
M680X_INS_CLRW = 88
M680X_INS_CLRX = 89
M680X_INS_CLV = 90
M680X_INS_CMP = 91
M680X_INS_CMPA = 92
M680X_INS_CMPB = 93
M680X_INS_CMPD = 94
M680X_INS_CMPE = 95
M680X_INS_CMPF = 96
M680X_INS_CMPR = 97
M680X_INS_CMPS = 98
M680X_INS_CMPU = 99
M680X_INS_CMPW = 100
M680X_INS_CMPX = 101
M680X_INS_CMPY = 102
M680X_INS_COM = 103
M680X_INS_COMA = 104
M680X_INS_COMB = 105
M680X_INS_COMD = 106
M680X_INS_COME = 107
M680X_INS_COMF = 108
M680X_INS_COMW = 109
M680X_INS_COMX = 110
M680X_INS_CPD = 111
M680X_INS_CPHX = 112
M680X_INS_CPS = 113
M680X_INS_CPX = 114
M680X_INS_CPY = 115
M680X_INS_CWAI = 116
M680X_INS_DAA = 117
M680X_INS_DBEQ = 118
M680X_INS_DBNE = 119
M680X_INS_DBNZ = 120
M680X_INS_DBNZA = 121
M680X_INS_DBNZX = 122
M680X_INS_DEC = 123
M680X_INS_DECA = 124
M680X_INS_DECB = 125
M680X_INS_DECD = 126
M680X_INS_DECE = 127
M680X_INS_DECF = 128
M680X_INS_DECW = 129
M680X_INS_DECX = 130
M680X_INS_DES = 131
M680X_INS_DEX = 132
M680X_INS_DEY = 133
M680X_INS_DIV = 134
M680X_INS_DIVD = 135
M680X_INS_DIVQ = 136
M680X_INS_EDIV = 137
M680X_INS_EDIVS = 138
M680X_INS_EIM = 139
M680X_INS_EMACS = 140
M680X_INS_EMAXD = 141
M680X_INS_EMAXM = 142
M680X_INS_EMIND = 143
M680X_INS_EMINM = 144
M680X_INS_EMUL = 145
M680X_INS_EMULS = 146
M680X_INS_EOR = 147
M680X_INS_EORA = 148
M680X_INS_EORB = 149
M680X_INS_EORD = 150
M680X_INS_EORR = 151
M680X_INS_ETBL = 152
M680X_INS_EXG = 153
M680X_INS_FDIV = 154
M680X_INS_IBEQ = 155
M680X_INS_IBNE = 156
M680X_INS_IDIV = 157
M680X_INS_IDIVS = 158
M680X_INS_ILLGL = 159
M680X_INS_INC = 160
M680X_INS_INCA = 161
M680X_INS_INCB = 162
M680X_INS_INCD = 163
M680X_INS_INCE = 164
M680X_INS_INCF = 165
M680X_INS_INCW = 166
M680X_INS_INCX = 167
M680X_INS_INS = 168
M680X_INS_INX = 169
M680X_INS_INY = 170
M680X_INS_JMP = 171
M680X_INS_JSR = 172
M680X_INS_LBCC = 173
M680X_INS_LBCS = 174
M680X_INS_LBEQ = 175
M680X_INS_LBGE = 176
M680X_INS_LBGT = 177
M680X_INS_LBHI = 178
M680X_INS_LBLE = 179
M680X_INS_LBLS = 180
M680X_INS_LBLT = 181
M680X_INS_LBMI = 182
M680X_INS_LBNE = 183
M680X_INS_LBPL = 184
M680X_INS_LBRA = 185
M680X_INS_LBRN = 186
M680X_INS_LBSR = 187
M680X_INS_LBVC = 188
M680X_INS_LBVS = 189
M680X_INS_LDA = 190
M680X_INS_LDAA = 191
M680X_INS_LDAB = 192
M680X_INS_LDB = 193
M680X_INS_LDBT = 194
M680X_INS_LDD = 195
M680X_INS_LDE = 196
M680X_INS_LDF = 197
M680X_INS_LDHX = 198
M680X_INS_LDMD = 199
M680X_INS_LDQ = 200
M680X_INS_LDS = 201
M680X_INS_LDU = 202
M680X_INS_LDW = 203
M680X_INS_LDX = 204
M680X_INS_LDY = 205
M680X_INS_LEAS = 206
M680X_INS_LEAU = 207
M680X_INS_LEAX = 208
M680X_INS_LEAY = 209
M680X_INS_LSL = 210
M680X_INS_LSLA = 211
M680X_INS_LSLB = 212
M680X_INS_LSLD = 213
M680X_INS_LSLX = 214
M680X_INS_LSR = 215
M680X_INS_LSRA = 216
M680X_INS_LSRB = 217
M680X_INS_LSRD = 218
M680X_INS_LSRW = 219
M680X_INS_LSRX = 220
M680X_INS_MAXA = 221
M680X_INS_MAXM = 222
M680X_INS_MEM = 223
M680X_INS_MINA = 224
M680X_INS_MINM = 225
M680X_INS_MOV = 226
M680X_INS_MOVB = 227
M680X_INS_MOVW = 228
M680X_INS_MUL = 229
M680X_INS_MULD = 230
M680X_INS_NEG = 231
M680X_INS_NEGA = 232
M680X_INS_NEGB = 233
M680X_INS_NEGD = 234
M680X_INS_NEGX = 235
M680X_INS_NOP = 236
M680X_INS_NSA = 237
M680X_INS_OIM = 238
M680X_INS_ORA = 239
M680X_INS_ORAA = 240
M680X_INS_ORAB = 241
M680X_INS_ORB = 242
M680X_INS_ORCC = 243
M680X_INS_ORD = 244
M680X_INS_ORR = 245
M680X_INS_PSHA = 246
M680X_INS_PSHB = 247
M680X_INS_PSHC = 248
M680X_INS_PSHD = 249
M680X_INS_PSHH = 250
M680X_INS_PSHS = 251
M680X_INS_PSHSW = 252
M680X_INS_PSHU = 253
M680X_INS_PSHUW = 254
M680X_INS_PSHX = 255
M680X_INS_PSHY = 256
M680X_INS_PULA = 257
M680X_INS_PULB = 258
M680X_INS_PULC = 259
M680X_INS_PULD = 260
M680X_INS_PULH = 261
M680X_INS_PULS = 262
M680X_INS_PULSW = 263
M680X_INS_PULU = 264
M680X_INS_PULUW = 265
M680X_INS_PULX = 266
M680X_INS_PULY = 267
M680X_INS_REV = 268
M680X_INS_REVW = 269
M680X_INS_ROL = 270
M680X_INS_ROLA = 271
M680X_INS_ROLB = 272
M680X_INS_ROLD = 273
M680X_INS_ROLW = 274
M680X_INS_ROLX = 275
M680X_INS_ROR = 276
M680X_INS_RORA = 277
M680X_INS_RORB = 278
M680X_INS_RORD = 279
M680X_INS_RORW = 280
M680X_INS_RORX = 281
M680X_INS_RSP = 282
M680X_INS_RTC = 283
M680X_INS_RTI = 284
M680X_INS_RTS = 285
M680X_INS_SBA = 286
M680X_INS_SBC = 287
M680X_INS_SBCA = 288
M680X_INS_SBCB = 289
M680X_INS_SBCD = 290
M680X_INS_SBCR = 291
M680X_INS_SEC = 292
M680X_INS_SEI = 293
M680X_INS_SEV = 294
M680X_INS_SEX = 295
M680X_INS_SEXW = 296
M680X_INS_SLP = 297
M680X_INS_STA = 298
M680X_INS_STAA = 299
M680X_INS_STAB = 300
M680X_INS_STB = 301
M680X_INS_STBT = 302
M680X_INS_STD = 303
M680X_INS_STE = 304
M680X_INS_STF = 305
M680X_INS_STOP = 306
M680X_INS_STHX = 307
M680X_INS_STQ = 308
M680X_INS_STS = 309
M680X_INS_STU = 310
M680X_INS_STW = 311
M680X_INS_STX = 312
M680X_INS_STY = 313
M680X_INS_SUB = 314
M680X_INS_SUBA = 315
M680X_INS_SUBB = 316
M680X_INS_SUBD = 317
M680X_INS_SUBE = 318
M680X_INS_SUBF = 319
M680X_INS_SUBR = 320
M680X_INS_SUBW = 321
M680X_INS_SWI = 322
M680X_INS_SWI2 = 323
M680X_INS_SWI3 = 324
M680X_INS_SYNC = 325
M680X_INS_TAB = 326
M680X_INS_TAP = 327
M680X_INS_TAX = 328
M680X_INS_TBA = 329
M680X_INS_TBEQ = 330
M680X_INS_TBL = 331
M680X_INS_TBNE = 332
M680X_INS_TEST = 333
M680X_INS_TFM = 334
M680X_INS_TFR = 335
M680X_INS_TIM = 336
M680X_INS_TPA = 337
M680X_INS_TST = 338
M680X_INS_TSTA = 339
M680X_INS_TSTB = 340
M680X_INS_TSTD = 341
M680X_INS_TSTE = 342
M680X_INS_TSTF = 343
M680X_INS_TSTW = 344
M680X_INS_TSTX = 345
M680X_INS_TSX = 346
M680X_INS_TSY = 347
M680X_INS_TXA = 348
M680X_INS_TXS = 349
M680X_INS_TYS = 350
M680X_INS_WAI = 351
M680X_INS_WAIT = 352
M680X_INS_WAV = 353
M680X_INS_WAVR = 354
M680X_INS_XGDX = 355
M680X_INS_XGDY = 356
M680X_INS_ENDING = 357
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/m680x_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sysz_const.py]
SYSZ_CC_INVALID = 0
SYSZ_CC_O = 1
SYSZ_CC_H = 2
SYSZ_CC_NLE = 3
SYSZ_CC_L = 4
SYSZ_CC_NHE = 5
SYSZ_CC_LH = 6
SYSZ_CC_NE = 7
SYSZ_CC_E = 8
SYSZ_CC_NLH = 9
SYSZ_CC_HE = 10
SYSZ_CC_NL = 11
SYSZ_CC_LE = 12
SYSZ_CC_NH = 13
SYSZ_CC_NO = 14
SYSZ_OP_INVALID = 0
SYSZ_OP_REG = 1
SYSZ_OP_IMM = 2
SYSZ_OP_MEM = 3
SYSZ_OP_ACREG = 64
SYSZ_REG_INVALID = 0
SYSZ_REG_0 = 1
SYSZ_REG_1 = 2
SYSZ_REG_2 = 3
SYSZ_REG_3 = 4
SYSZ_REG_4 = 5
SYSZ_REG_5 = 6
SYSZ_REG_6 = 7
SYSZ_REG_7 = 8
SYSZ_REG_8 = 9
SYSZ_REG_9 = 10
SYSZ_REG_10 = 11
SYSZ_REG_11 = 12
SYSZ_REG_12 = 13
SYSZ_REG_13 = 14
SYSZ_REG_14 = 15
SYSZ_REG_15 = 16
SYSZ_REG_CC = 17
SYSZ_REG_F0 = 18
SYSZ_REG_F1 = 19
SYSZ_REG_F2 = 20
SYSZ_REG_F3 = 21
SYSZ_REG_F4 = 22
SYSZ_REG_F5 = 23
SYSZ_REG_F6 = 24
SYSZ_REG_F7 = 25
SYSZ_REG_F8 = 26
SYSZ_REG_F9 = 27
SYSZ_REG_F10 = 28
SYSZ_REG_F11 = 29
SYSZ_REG_F12 = 30
SYSZ_REG_F13 = 31
SYSZ_REG_F14 = 32
SYSZ_REG_F15 = 33
SYSZ_REG_R0L = 34
SYSZ_REG_A0 = 35
SYSZ_REG_A1 = 36
SYSZ_REG_A2 = 37
SYSZ_REG_A3 = 38
SYSZ_REG_A4 = 39
SYSZ_REG_A5 = 40
SYSZ_REG_A6 = 41
SYSZ_REG_A7 = 42
SYSZ_REG_A8 = 43
SYSZ_REG_A9 = 44
SYSZ_REG_A10 = 45
SYSZ_REG_A11 = 46
SYSZ_REG_A12 = 47
SYSZ_REG_A13 = 48
SYSZ_REG_A14 = 49
SYSZ_REG_A15 = 50
SYSZ_REG_C0 = 51
SYSZ_REG_C1 = 52
SYSZ_REG_C2 = 53
SYSZ_REG_C3 = 54
SYSZ_REG_C4 = 55
SYSZ_REG_C5 = 56
SYSZ_REG_C6 = 57
SYSZ_REG_C7 = 58
SYSZ_REG_C8 = 59
SYSZ_REG_C9 = 60
SYSZ_REG_C10 = 61
SYSZ_REG_C11 = 62
SYSZ_REG_C12 = 63
SYSZ_REG_C13 = 64
SYSZ_REG_C14 = 65
SYSZ_REG_C15 = 66
SYSZ_REG_V0 = 67
SYSZ_REG_V1 = 68
SYSZ_REG_V2 = 69
SYSZ_REG_V3 = 70
SYSZ_REG_V4 = 71
SYSZ_REG_V5 = 72
SYSZ_REG_V6 = 73
SYSZ_REG_V7 = 74
SYSZ_REG_V8 = 75
SYSZ_REG_V9 = 76
SYSZ_REG_V10 = 77
SYSZ_REG_V11 = 78
SYSZ_REG_V12 = 79
SYSZ_REG_V13 = 80
SYSZ_REG_V14 = 81
SYSZ_REG_V15 = 82
SYSZ_REG_V16 = 83
SYSZ_REG_V17 = 84
SYSZ_REG_V18 = 85
SYSZ_REG_V19 = 86
SYSZ_REG_V20 = 87
SYSZ_REG_V21 = 88
SYSZ_REG_V22 = 89
SYSZ_REG_V23 = 90
SYSZ_REG_V24 = 91
SYSZ_REG_V25 = 92
SYSZ_REG_V26 = 93
SYSZ_REG_V27 = 94
SYSZ_REG_V28 = 95
SYSZ_REG_V29 = 96
SYSZ_REG_V30 = 97
SYSZ_REG_V31 = 98
SYSZ_REG_F16 = 99
SYSZ_REG_F17 = 100
SYSZ_REG_F18 = 101
SYSZ_REG_F19 = 102
SYSZ_REG_F20 = 103
SYSZ_REG_F21 = 104
SYSZ_REG_F22 = 105
SYSZ_REG_F23 = 106
SYSZ_REG_F24 = 107
SYSZ_REG_F25 = 108
SYSZ_REG_F26 = 109
SYSZ_REG_F27 = 110
SYSZ_REG_F28 = 111
SYSZ_REG_F29 = 112
SYSZ_REG_F30 = 113
SYSZ_REG_F31 = 114
SYSZ_REG_F0Q = 115
SYSZ_REG_F4Q = 116
SYSZ_REG_ENDING = 117
SYSZ_INS_INVALID = 0
SYSZ_INS_A = 1
SYSZ_INS_ADB = 2
SYSZ_INS_ADBR = 3
SYSZ_INS_AEB = 4
SYSZ_INS_AEBR = 5
SYSZ_INS_AFI = 6
SYSZ_INS_AG = 7
SYSZ_INS_AGF = 8
SYSZ_INS_AGFI = 9
SYSZ_INS_AGFR = 10
SYSZ_INS_AGHI = 11
SYSZ_INS_AGHIK = 12
SYSZ_INS_AGR = 13
SYSZ_INS_AGRK = 14
SYSZ_INS_AGSI = 15
SYSZ_INS_AH = 16
SYSZ_INS_AHI = 17
SYSZ_INS_AHIK = 18
SYSZ_INS_AHY = 19
SYSZ_INS_AIH = 20
SYSZ_INS_AL = 21
SYSZ_INS_ALC = 22
SYSZ_INS_ALCG = 23
SYSZ_INS_ALCGR = 24
SYSZ_INS_ALCR = 25
SYSZ_INS_ALFI = 26
SYSZ_INS_ALG = 27
SYSZ_INS_ALGF = 28
SYSZ_INS_ALGFI = 29
SYSZ_INS_ALGFR = 30
SYSZ_INS_ALGHSIK = 31
SYSZ_INS_ALGR = 32
SYSZ_INS_ALGRK = 33
SYSZ_INS_ALHSIK = 34
SYSZ_INS_ALR = 35
SYSZ_INS_ALRK = 36
SYSZ_INS_ALY = 37
SYSZ_INS_AR = 38
SYSZ_INS_ARK = 39
SYSZ_INS_ASI = 40
SYSZ_INS_AXBR = 41
SYSZ_INS_AY = 42
SYSZ_INS_BCR = 43
SYSZ_INS_BRC = 44
SYSZ_INS_BRCL = 45
SYSZ_INS_CGIJ = 46
SYSZ_INS_CGRJ = 47
SYSZ_INS_CIJ = 48
SYSZ_INS_CLGIJ = 49
SYSZ_INS_CLGRJ = 50
SYSZ_INS_CLIJ = 51
SYSZ_INS_CLRJ = 52
SYSZ_INS_CRJ = 53
SYSZ_INS_BER = 54
SYSZ_INS_JE = 55
SYSZ_INS_JGE = 56
SYSZ_INS_LOCE = 57
SYSZ_INS_LOCGE = 58
SYSZ_INS_LOCGRE = 59
SYSZ_INS_LOCRE = 60
SYSZ_INS_STOCE = 61
SYSZ_INS_STOCGE = 62
SYSZ_INS_BHR = 63
SYSZ_INS_BHER = 64
SYSZ_INS_JHE = 65
SYSZ_INS_JGHE = 66
SYSZ_INS_LOCHE = 67
SYSZ_INS_LOCGHE = 68
SYSZ_INS_LOCGRHE = 69
SYSZ_INS_LOCRHE = 70
SYSZ_INS_STOCHE = 71
SYSZ_INS_STOCGHE = 72
SYSZ_INS_JH = 73
SYSZ_INS_JGH = 74
SYSZ_INS_LOCH = 75
SYSZ_INS_LOCGH = 76
SYSZ_INS_LOCGRH = 77
SYSZ_INS_LOCRH = 78
SYSZ_INS_STOCH = 79
SYSZ_INS_STOCGH = 80
SYSZ_INS_CGIJNLH = 81
SYSZ_INS_CGRJNLH = 82
SYSZ_INS_CIJNLH = 83
SYSZ_INS_CLGIJNLH = 84
SYSZ_INS_CLGRJNLH = 85
SYSZ_INS_CLIJNLH = 86
SYSZ_INS_CLRJNLH = 87
SYSZ_INS_CRJNLH = 88
SYSZ_INS_CGIJE = 89
SYSZ_INS_CGRJE = 90
SYSZ_INS_CIJE = 91
SYSZ_INS_CLGIJE = 92
SYSZ_INS_CLGRJE = 93
SYSZ_INS_CLIJE = 94
SYSZ_INS_CLRJE = 95
SYSZ_INS_CRJE = 96
SYSZ_INS_CGIJNLE = 97
SYSZ_INS_CGRJNLE = 98
SYSZ_INS_CIJNLE = 99
SYSZ_INS_CLGIJNLE = 100
SYSZ_INS_CLGRJNLE = 101
SYSZ_INS_CLIJNLE = 102
SYSZ_INS_CLRJNLE = 103
SYSZ_INS_CRJNLE = 104
SYSZ_INS_CGIJH = 105
SYSZ_INS_CGRJH = 106
SYSZ_INS_CIJH = 107
SYSZ_INS_CLGIJH = 108
SYSZ_INS_CLGRJH = 109
SYSZ_INS_CLIJH = 110
SYSZ_INS_CLRJH = 111
SYSZ_INS_CRJH = 112
SYSZ_INS_CGIJNL = 113
SYSZ_INS_CGRJNL = 114
SYSZ_INS_CIJNL = 115
SYSZ_INS_CLGIJNL = 116
SYSZ_INS_CLGRJNL = 117
SYSZ_INS_CLIJNL = 118
SYSZ_INS_CLRJNL = 119
SYSZ_INS_CRJNL = 120
SYSZ_INS_CGIJHE = 121
SYSZ_INS_CGRJHE = 122
SYSZ_INS_CIJHE = 123
SYSZ_INS_CLGIJHE = 124
SYSZ_INS_CLGRJHE = 125
SYSZ_INS_CLIJHE = 126
SYSZ_INS_CLRJHE = 127
SYSZ_INS_CRJHE = 128
SYSZ_INS_CGIJNHE = 129
SYSZ_INS_CGRJNHE = 130
SYSZ_INS_CIJNHE = 131
SYSZ_INS_CLGIJNHE = 132
SYSZ_INS_CLGRJNHE = 133
SYSZ_INS_CLIJNHE = 134
SYSZ_INS_CLRJNHE = 135
SYSZ_INS_CRJNHE = 136
SYSZ_INS_CGIJL = 137
SYSZ_INS_CGRJL = 138
SYSZ_INS_CIJL = 139
SYSZ_INS_CLGIJL = 140
SYSZ_INS_CLGRJL = 141
SYSZ_INS_CLIJL = 142
SYSZ_INS_CLRJL = 143
SYSZ_INS_CRJL = 144
SYSZ_INS_CGIJNH = 145
SYSZ_INS_CGRJNH = 146
SYSZ_INS_CIJNH = 147
SYSZ_INS_CLGIJNH = 148
SYSZ_INS_CLGRJNH = 149
SYSZ_INS_CLIJNH = 150
SYSZ_INS_CLRJNH = 151
SYSZ_INS_CRJNH = 152
SYSZ_INS_CGIJLE = 153
SYSZ_INS_CGRJLE = 154
SYSZ_INS_CIJLE = 155
SYSZ_INS_CLGIJLE = 156
SYSZ_INS_CLGRJLE = 157
SYSZ_INS_CLIJLE = 158
SYSZ_INS_CLRJLE = 159
SYSZ_INS_CRJLE = 160
SYSZ_INS_CGIJNE = 161
SYSZ_INS_CGRJNE = 162
SYSZ_INS_CIJNE = 163
SYSZ_INS_CLGIJNE = 164
SYSZ_INS_CLGRJNE = 165
SYSZ_INS_CLIJNE = 166
SYSZ_INS_CLRJNE = 167
SYSZ_INS_CRJNE = 168
SYSZ_INS_CGIJLH = 169
SYSZ_INS_CGRJLH = 170
SYSZ_INS_CIJLH = 171
SYSZ_INS_CLGIJLH = 172
SYSZ_INS_CLGRJLH = 173
SYSZ_INS_CLIJLH = 174
SYSZ_INS_CLRJLH = 175
SYSZ_INS_CRJLH = 176
SYSZ_INS_BLR = 177
SYSZ_INS_BLER = 178
SYSZ_INS_JLE = 179
SYSZ_INS_JGLE = 180
SYSZ_INS_LOCLE = 181
SYSZ_INS_LOCGLE = 182
SYSZ_INS_LOCGRLE = 183
SYSZ_INS_LOCRLE = 184
SYSZ_INS_STOCLE = 185
SYSZ_INS_STOCGLE = 186
SYSZ_INS_BLHR = 187
SYSZ_INS_JLH = 188
SYSZ_INS_JGLH = 189
SYSZ_INS_LOCLH = 190
SYSZ_INS_LOCGLH = 191
SYSZ_INS_LOCGRLH = 192
SYSZ_INS_LOCRLH = 193
SYSZ_INS_STOCLH = 194
SYSZ_INS_STOCGLH = 195
SYSZ_INS_JL = 196
SYSZ_INS_JGL = 197
SYSZ_INS_LOCL = 198
SYSZ_INS_LOCGL = 199
SYSZ_INS_LOCGRL = 200
SYSZ_INS_LOCRL = 201
SYSZ_INS_LOC = 202
SYSZ_INS_LOCG = 203
SYSZ_INS_LOCGR = 204
SYSZ_INS_LOCR = 205
SYSZ_INS_STOCL = 206
SYSZ_INS_STOCGL = 207
SYSZ_INS_BNER = 208
SYSZ_INS_JNE = 209
SYSZ_INS_JGNE = 210
SYSZ_INS_LOCNE = 211
SYSZ_INS_LOCGNE = 212
SYSZ_INS_LOCGRNE = 213
SYSZ_INS_LOCRNE = 214
SYSZ_INS_STOCNE = 215
SYSZ_INS_STOCGNE = 216
SYSZ_INS_BNHR = 217
SYSZ_INS_BNHER = 218
SYSZ_INS_JNHE = 219
SYSZ_INS_JGNHE = 220
SYSZ_INS_LOCNHE = 221
SYSZ_INS_LOCGNHE = 222
SYSZ_INS_LOCGRNHE = 223
SYSZ_INS_LOCRNHE = 224
SYSZ_INS_STOCNHE = 225
SYSZ_INS_STOCGNHE = 226
SYSZ_INS_JNH = 227
SYSZ_INS_JGNH = 228
SYSZ_INS_LOCNH = 229
SYSZ_INS_LOCGNH = 230
SYSZ_INS_LOCGRNH = 231
SYSZ_INS_LOCRNH = 232
SYSZ_INS_STOCNH = 233
SYSZ_INS_STOCGNH = 234
SYSZ_INS_BNLR = 235
SYSZ_INS_BNLER = 236
SYSZ_INS_JNLE = 237
SYSZ_INS_JGNLE = 238
SYSZ_INS_LOCNLE = 239
SYSZ_INS_LOCGNLE = 240
SYSZ_INS_LOCGRNLE = 241
SYSZ_INS_LOCRNLE = 242
SYSZ_INS_STOCNLE = 243
SYSZ_INS_STOCGNLE = 244
SYSZ_INS_BNLHR = 245
SYSZ_INS_JNLH = 246
SYSZ_INS_JGNLH = 247
SYSZ_INS_LOCNLH = 248
SYSZ_INS_LOCGNLH = 249
SYSZ_INS_LOCGRNLH = 250
SYSZ_INS_LOCRNLH = 251
SYSZ_INS_STOCNLH = 252
SYSZ_INS_STOCGNLH = 253
SYSZ_INS_JNL = 254
SYSZ_INS_JGNL = 255
SYSZ_INS_LOCNL = 256
SYSZ_INS_LOCGNL = 257
SYSZ_INS_LOCGRNL = 258
SYSZ_INS_LOCRNL = 259
SYSZ_INS_STOCNL = 260
SYSZ_INS_STOCGNL = 261
SYSZ_INS_BNOR = 262
SYSZ_INS_JNO = 263
SYSZ_INS_JGNO = 264
SYSZ_INS_LOCNO = 265
SYSZ_INS_LOCGNO = 266
SYSZ_INS_LOCGRNO = 267
SYSZ_INS_LOCRNO = 268
SYSZ_INS_STOCNO = 269
SYSZ_INS_STOCGNO = 270
SYSZ_INS_BOR = 271
SYSZ_INS_JO = 272
SYSZ_INS_JGO = 273
SYSZ_INS_LOCO = 274
SYSZ_INS_LOCGO = 275
SYSZ_INS_LOCGRO = 276
SYSZ_INS_LOCRO = 277
SYSZ_INS_STOCO = 278
SYSZ_INS_STOCGO = 279
SYSZ_INS_STOC = 280
SYSZ_INS_STOCG = 281
SYSZ_INS_BASR = 282
SYSZ_INS_BR = 283
SYSZ_INS_BRAS = 284
SYSZ_INS_BRASL = 285
SYSZ_INS_J = 286
SYSZ_INS_JG = 287
SYSZ_INS_BRCT = 288
SYSZ_INS_BRCTG = 289
SYSZ_INS_C = 290
SYSZ_INS_CDB = 291
SYSZ_INS_CDBR = 292
SYSZ_INS_CDFBR = 293
SYSZ_INS_CDGBR = 294
SYSZ_INS_CDLFBR = 295
SYSZ_INS_CDLGBR = 296
SYSZ_INS_CEB = 297
SYSZ_INS_CEBR = 298
SYSZ_INS_CEFBR = 299
SYSZ_INS_CEGBR = 300
SYSZ_INS_CELFBR = 301
SYSZ_INS_CELGBR = 302
SYSZ_INS_CFDBR = 303
SYSZ_INS_CFEBR = 304
SYSZ_INS_CFI = 305
SYSZ_INS_CFXBR = 306
SYSZ_INS_CG = 307
SYSZ_INS_CGDBR = 308
SYSZ_INS_CGEBR = 309
SYSZ_INS_CGF = 310
SYSZ_INS_CGFI = 311
SYSZ_INS_CGFR = 312
SYSZ_INS_CGFRL = 313
SYSZ_INS_CGH = 314
SYSZ_INS_CGHI = 315
SYSZ_INS_CGHRL = 316
SYSZ_INS_CGHSI = 317
SYSZ_INS_CGR = 318
SYSZ_INS_CGRL = 319
SYSZ_INS_CGXBR = 320
SYSZ_INS_CH = 321
SYSZ_INS_CHF = 322
SYSZ_INS_CHHSI = 323
SYSZ_INS_CHI = 324
SYSZ_INS_CHRL = 325
SYSZ_INS_CHSI = 326
SYSZ_INS_CHY = 327
SYSZ_INS_CIH = 328
SYSZ_INS_CL = 329
SYSZ_INS_CLC = 330
SYSZ_INS_CLFDBR = 331
SYSZ_INS_CLFEBR = 332
SYSZ_INS_CLFHSI = 333
SYSZ_INS_CLFI = 334
SYSZ_INS_CLFXBR = 335
SYSZ_INS_CLG = 336
SYSZ_INS_CLGDBR = 337
SYSZ_INS_CLGEBR = 338
SYSZ_INS_CLGF = 339
SYSZ_INS_CLGFI = 340
SYSZ_INS_CLGFR = 341
SYSZ_INS_CLGFRL = 342
SYSZ_INS_CLGHRL = 343
SYSZ_INS_CLGHSI = 344
SYSZ_INS_CLGR = 345
SYSZ_INS_CLGRL = 346
SYSZ_INS_CLGXBR = 347
SYSZ_INS_CLHF = 348
SYSZ_INS_CLHHSI = 349
SYSZ_INS_CLHRL = 350
SYSZ_INS_CLI = 351
SYSZ_INS_CLIH = 352
SYSZ_INS_CLIY = 353
SYSZ_INS_CLR = 354
SYSZ_INS_CLRL = 355
SYSZ_INS_CLST = 356
SYSZ_INS_CLY = 357
SYSZ_INS_CPSDR = 358
SYSZ_INS_CR = 359
SYSZ_INS_CRL = 360
SYSZ_INS_CS = 361
SYSZ_INS_CSG = 362
SYSZ_INS_CSY = 363
SYSZ_INS_CXBR = 364
SYSZ_INS_CXFBR = 365
SYSZ_INS_CXGBR = 366
SYSZ_INS_CXLFBR = 367
SYSZ_INS_CXLGBR = 368
SYSZ_INS_CY = 369
SYSZ_INS_DDB = 370
SYSZ_INS_DDBR = 371
SYSZ_INS_DEB = 372
SYSZ_INS_DEBR = 373
SYSZ_INS_DL = 374
SYSZ_INS_DLG = 375
SYSZ_INS_DLGR = 376
SYSZ_INS_DLR = 377
SYSZ_INS_DSG = 378
SYSZ_INS_DSGF = 379
SYSZ_INS_DSGFR = 380
SYSZ_INS_DSGR = 381
SYSZ_INS_DXBR = 382
SYSZ_INS_EAR = 383
SYSZ_INS_FIDBR = 384
SYSZ_INS_FIDBRA = 385
SYSZ_INS_FIEBR = 386
SYSZ_INS_FIEBRA = 387
SYSZ_INS_FIXBR = 388
SYSZ_INS_FIXBRA = 389
SYSZ_INS_FLOGR = 390
SYSZ_INS_IC = 391
SYSZ_INS_ICY = 392
SYSZ_INS_IIHF = 393
SYSZ_INS_IIHH = 394
SYSZ_INS_IIHL = 395
SYSZ_INS_IILF = 396
SYSZ_INS_IILH = 397
SYSZ_INS_IILL = 398
SYSZ_INS_IPM = 399
SYSZ_INS_L = 400
SYSZ_INS_LA = 401
SYSZ_INS_LAA = 402
SYSZ_INS_LAAG = 403
SYSZ_INS_LAAL = 404
SYSZ_INS_LAALG = 405
SYSZ_INS_LAN = 406
SYSZ_INS_LANG = 407
SYSZ_INS_LAO = 408
SYSZ_INS_LAOG = 409
SYSZ_INS_LARL = 410
SYSZ_INS_LAX = 411
SYSZ_INS_LAXG = 412
SYSZ_INS_LAY = 413
SYSZ_INS_LB = 414
SYSZ_INS_LBH = 415
SYSZ_INS_LBR = 416
SYSZ_INS_LCDBR = 417
SYSZ_INS_LCEBR = 418
SYSZ_INS_LCGFR = 419
SYSZ_INS_LCGR = 420
SYSZ_INS_LCR = 421
SYSZ_INS_LCXBR = 422
SYSZ_INS_LD = 423
SYSZ_INS_LDEB = 424
SYSZ_INS_LDEBR = 425
SYSZ_INS_LDGR = 426
SYSZ_INS_LDR = 427
SYSZ_INS_LDXBR = 428
SYSZ_INS_LDXBRA = 429
SYSZ_INS_LDY = 430
SYSZ_INS_LE = 431
SYSZ_INS_LEDBR = 432
SYSZ_INS_LEDBRA = 433
SYSZ_INS_LER = 434
SYSZ_INS_LEXBR = 435
SYSZ_INS_LEXBRA = 436
SYSZ_INS_LEY = 437
SYSZ_INS_LFH = 438
SYSZ_INS_LG = 439
SYSZ_INS_LGB = 440
SYSZ_INS_LGBR = 441
SYSZ_INS_LGDR = 442
SYSZ_INS_LGF = 443
SYSZ_INS_LGFI = 444
SYSZ_INS_LGFR = 445
SYSZ_INS_LGFRL = 446
SYSZ_INS_LGH = 447
SYSZ_INS_LGHI = 448
SYSZ_INS_LGHR = 449
SYSZ_INS_LGHRL = 450
SYSZ_INS_LGR = 451
SYSZ_INS_LGRL = 452
SYSZ_INS_LH = 453
SYSZ_INS_LHH = 454
SYSZ_INS_LHI = 455
SYSZ_INS_LHR = 456
SYSZ_INS_LHRL = 457
SYSZ_INS_LHY = 458
SYSZ_INS_LLC = 459
SYSZ_INS_LLCH = 460
SYSZ_INS_LLCR = 461
SYSZ_INS_LLGC = 462
SYSZ_INS_LLGCR = 463
SYSZ_INS_LLGF = 464
SYSZ_INS_LLGFR = 465
SYSZ_INS_LLGFRL = 466
SYSZ_INS_LLGH = 467
SYSZ_INS_LLGHR = 468
SYSZ_INS_LLGHRL = 469
SYSZ_INS_LLH = 470
SYSZ_INS_LLHH = 471
SYSZ_INS_LLHR = 472
SYSZ_INS_LLHRL = 473
SYSZ_INS_LLIHF = 474
SYSZ_INS_LLIHH = 475
SYSZ_INS_LLIHL = 476
SYSZ_INS_LLILF = 477
SYSZ_INS_LLILH = 478
SYSZ_INS_LLILL = 479
SYSZ_INS_LMG = 480
SYSZ_INS_LNDBR = 481
SYSZ_INS_LNEBR = 482
SYSZ_INS_LNGFR = 483
SYSZ_INS_LNGR = 484
SYSZ_INS_LNR = 485
SYSZ_INS_LNXBR = 486
SYSZ_INS_LPDBR = 487
SYSZ_INS_LPEBR = 488
SYSZ_INS_LPGFR = 489
SYSZ_INS_LPGR = 490
SYSZ_INS_LPR = 491
SYSZ_INS_LPXBR = 492
SYSZ_INS_LR = 493
SYSZ_INS_LRL = 494
SYSZ_INS_LRV = 495
SYSZ_INS_LRVG = 496
SYSZ_INS_LRVGR = 497
SYSZ_INS_LRVR = 498
SYSZ_INS_LT = 499
SYSZ_INS_LTDBR = 500
SYSZ_INS_LTEBR = 501
SYSZ_INS_LTG = 502
SYSZ_INS_LTGF = 503
SYSZ_INS_LTGFR = 504
SYSZ_INS_LTGR = 505
SYSZ_INS_LTR = 506
SYSZ_INS_LTXBR = 507
SYSZ_INS_LXDB = 508
SYSZ_INS_LXDBR = 509
SYSZ_INS_LXEB = 510
SYSZ_INS_LXEBR = 511
SYSZ_INS_LXR = 512
SYSZ_INS_LY = 513
SYSZ_INS_LZDR = 514
SYSZ_INS_LZER = 515
SYSZ_INS_LZXR = 516
SYSZ_INS_MADB = 517
SYSZ_INS_MADBR = 518
SYSZ_INS_MAEB = 519
SYSZ_INS_MAEBR = 520
SYSZ_INS_MDB = 521
SYSZ_INS_MDBR = 522
SYSZ_INS_MDEB = 523
SYSZ_INS_MDEBR = 524
SYSZ_INS_MEEB = 525
SYSZ_INS_MEEBR = 526
SYSZ_INS_MGHI = 527
SYSZ_INS_MH = 528
SYSZ_INS_MHI = 529
SYSZ_INS_MHY = 530
SYSZ_INS_MLG = 531
SYSZ_INS_MLGR = 532
SYSZ_INS_MS = 533
SYSZ_INS_MSDB = 534
SYSZ_INS_MSDBR = 535
SYSZ_INS_MSEB = 536
SYSZ_INS_MSEBR = 537
SYSZ_INS_MSFI = 538
SYSZ_INS_MSG = 539
SYSZ_INS_MSGF = 540
SYSZ_INS_MSGFI = 541
SYSZ_INS_MSGFR = 542
SYSZ_INS_MSGR = 543
SYSZ_INS_MSR = 544
SYSZ_INS_MSY = 545
SYSZ_INS_MVC = 546
SYSZ_INS_MVGHI = 547
SYSZ_INS_MVHHI = 548
SYSZ_INS_MVHI = 549
SYSZ_INS_MVI = 550
SYSZ_INS_MVIY = 551
SYSZ_INS_MVST = 552
SYSZ_INS_MXBR = 553
SYSZ_INS_MXDB = 554
SYSZ_INS_MXDBR = 555
SYSZ_INS_N = 556
SYSZ_INS_NC = 557
SYSZ_INS_NG = 558
SYSZ_INS_NGR = 559
SYSZ_INS_NGRK = 560
SYSZ_INS_NI = 561
SYSZ_INS_NIHF = 562
SYSZ_INS_NIHH = 563
SYSZ_INS_NIHL = 564
SYSZ_INS_NILF = 565
SYSZ_INS_NILH = 566
SYSZ_INS_NILL = 567
SYSZ_INS_NIY = 568
SYSZ_INS_NR = 569
SYSZ_INS_NRK = 570
SYSZ_INS_NY = 571
SYSZ_INS_O = 572
SYSZ_INS_OC = 573
SYSZ_INS_OG = 574
SYSZ_INS_OGR = 575
SYSZ_INS_OGRK = 576
SYSZ_INS_OI = 577
SYSZ_INS_OIHF = 578
SYSZ_INS_OIHH = 579
SYSZ_INS_OIHL = 580
SYSZ_INS_OILF = 581
SYSZ_INS_OILH = 582
SYSZ_INS_OILL = 583
SYSZ_INS_OIY = 584
SYSZ_INS_OR = 585
SYSZ_INS_ORK = 586
SYSZ_INS_OY = 587
SYSZ_INS_PFD = 588
SYSZ_INS_PFDRL = 589
SYSZ_INS_RISBG = 590
SYSZ_INS_RISBHG = 591
SYSZ_INS_RISBLG = 592
SYSZ_INS_RLL = 593
SYSZ_INS_RLLG = 594
SYSZ_INS_RNSBG = 595
SYSZ_INS_ROSBG = 596
SYSZ_INS_RXSBG = 597
SYSZ_INS_S = 598
SYSZ_INS_SDB = 599
SYSZ_INS_SDBR = 600
SYSZ_INS_SEB = 601
SYSZ_INS_SEBR = 602
SYSZ_INS_SG = 603
SYSZ_INS_SGF = 604
SYSZ_INS_SGFR = 605
SYSZ_INS_SGR = 606
SYSZ_INS_SGRK = 607
SYSZ_INS_SH = 608
SYSZ_INS_SHY = 609
SYSZ_INS_SL = 610
SYSZ_INS_SLB = 611
SYSZ_INS_SLBG = 612
SYSZ_INS_SLBR = 613
SYSZ_INS_SLFI = 614
SYSZ_INS_SLG = 615
SYSZ_INS_SLBGR = 616
SYSZ_INS_SLGF = 617
SYSZ_INS_SLGFI = 618
SYSZ_INS_SLGFR = 619
SYSZ_INS_SLGR = 620
SYSZ_INS_SLGRK = 621
SYSZ_INS_SLL = 622
SYSZ_INS_SLLG = 623
SYSZ_INS_SLLK = 624
SYSZ_INS_SLR = 625
SYSZ_INS_SLRK = 626
SYSZ_INS_SLY = 627
SYSZ_INS_SQDB = 628
SYSZ_INS_SQDBR = 629
SYSZ_INS_SQEB = 630
SYSZ_INS_SQEBR = 631
SYSZ_INS_SQXBR = 632
SYSZ_INS_SR = 633
SYSZ_INS_SRA = 634
SYSZ_INS_SRAG = 635
SYSZ_INS_SRAK = 636
SYSZ_INS_SRK = 637
SYSZ_INS_SRL = 638
SYSZ_INS_SRLG = 639
SYSZ_INS_SRLK = 640
SYSZ_INS_SRST = 641
SYSZ_INS_ST = 642
SYSZ_INS_STC = 643
SYSZ_INS_STCH = 644
SYSZ_INS_STCY = 645
SYSZ_INS_STD = 646
SYSZ_INS_STDY = 647
SYSZ_INS_STE = 648
SYSZ_INS_STEY = 649
SYSZ_INS_STFH = 650
SYSZ_INS_STG = 651
SYSZ_INS_STGRL = 652
SYSZ_INS_STH = 653
SYSZ_INS_STHH = 654
SYSZ_INS_STHRL = 655
SYSZ_INS_STHY = 656
SYSZ_INS_STMG = 657
SYSZ_INS_STRL = 658
SYSZ_INS_STRV = 659
SYSZ_INS_STRVG = 660
SYSZ_INS_STY = 661
SYSZ_INS_SXBR = 662
SYSZ_INS_SY = 663
SYSZ_INS_TM = 664
SYSZ_INS_TMHH = 665
SYSZ_INS_TMHL = 666
SYSZ_INS_TMLH = 667
SYSZ_INS_TMLL = 668
SYSZ_INS_TMY = 669
SYSZ_INS_X = 670
SYSZ_INS_XC = 671
SYSZ_INS_XG = 672
SYSZ_INS_XGR = 673
SYSZ_INS_XGRK = 674
SYSZ_INS_XI = 675
SYSZ_INS_XIHF = 676
SYSZ_INS_XILF = 677
SYSZ_INS_XIY = 678
SYSZ_INS_XR = 679
SYSZ_INS_XRK = 680
SYSZ_INS_XY = 681
SYSZ_INS_AD = 682
SYSZ_INS_ADR = 683
SYSZ_INS_ADTR = 684
SYSZ_INS_ADTRA = 685
SYSZ_INS_AE = 686
SYSZ_INS_AER = 687
SYSZ_INS_AGH = 688
SYSZ_INS_AHHHR = 689
SYSZ_INS_AHHLR = 690
SYSZ_INS_ALGSI = 691
SYSZ_INS_ALHHHR = 692
SYSZ_INS_ALHHLR = 693
SYSZ_INS_ALSI = 694
SYSZ_INS_ALSIH = 695
SYSZ_INS_ALSIHN = 696
SYSZ_INS_AP = 697
SYSZ_INS_AU = 698
SYSZ_INS_AUR = 699
SYSZ_INS_AW = 700
SYSZ_INS_AWR = 701
SYSZ_INS_AXR = 702
SYSZ_INS_AXTR = 703
SYSZ_INS_AXTRA = 704
SYSZ_INS_B = 705
SYSZ_INS_BAKR = 706
SYSZ_INS_BAL = 707
SYSZ_INS_BALR = 708
SYSZ_INS_BAS = 709
SYSZ_INS_BASSM = 710
SYSZ_INS_BC = 711
SYSZ_INS_BCT = 712
SYSZ_INS_BCTG = 713
SYSZ_INS_BCTGR = 714
SYSZ_INS_BCTR = 715
SYSZ_INS_BE = 716
SYSZ_INS_BH = 717
SYSZ_INS_BHE = 718
SYSZ_INS_BI = 719
SYSZ_INS_BIC = 720
SYSZ_INS_BIE = 721
SYSZ_INS_BIH = 722
SYSZ_INS_BIHE = 723
SYSZ_INS_BIL = 724
SYSZ_INS_BILE = 725
SYSZ_INS_BILH = 726
SYSZ_INS_BIM = 727
SYSZ_INS_BINE = 728
SYSZ_INS_BINH = 729
SYSZ_INS_BINHE = 730
SYSZ_INS_BINL = 731
SYSZ_INS_BINLE = 732
SYSZ_INS_BINLH = 733
SYSZ_INS_BINM = 734
SYSZ_INS_BINO = 735
SYSZ_INS_BINP = 736
SYSZ_INS_BINZ = 737
SYSZ_INS_BIO = 738
SYSZ_INS_BIP = 739
SYSZ_INS_BIZ = 740
SYSZ_INS_BL = 741
SYSZ_INS_BLE = 742
SYSZ_INS_BLH = 743
SYSZ_INS_BM = 744
SYSZ_INS_BMR = 745
SYSZ_INS_BNE = 746
SYSZ_INS_BNH = 747
SYSZ_INS_BNHE = 748
SYSZ_INS_BNL = 749
SYSZ_INS_BNLE = 750
SYSZ_INS_BNLH = 751
SYSZ_INS_BNM = 752
SYSZ_INS_BNMR = 753
SYSZ_INS_BNO = 754
SYSZ_INS_BNP = 755
SYSZ_INS_BNPR = 756
SYSZ_INS_BNZ = 757
SYSZ_INS_BNZR = 758
SYSZ_INS_BO = 759
SYSZ_INS_BP = 760
SYSZ_INS_BPP = 761
SYSZ_INS_BPR = 762
SYSZ_INS_BPRP = 763
SYSZ_INS_BRCTH = 764
SYSZ_INS_BRXH = 765
SYSZ_INS_BRXHG = 766
SYSZ_INS_BRXLE = 767
SYSZ_INS_BRXLG = 768
SYSZ_INS_BSA = 769
SYSZ_INS_BSG = 770
SYSZ_INS_BSM = 771
SYSZ_INS_BXH = 772
SYSZ_INS_BXHG = 773
SYSZ_INS_BXLE = 774
SYSZ_INS_BXLEG = 775
SYSZ_INS_BZ = 776
SYSZ_INS_BZR = 777
SYSZ_INS_CD = 778
SYSZ_INS_CDFBRA = 779
SYSZ_INS_CDFR = 780
SYSZ_INS_CDFTR = 781
SYSZ_INS_CDGBRA = 782
SYSZ_INS_CDGR = 783
SYSZ_INS_CDGTR = 784
SYSZ_INS_CDGTRA = 785
SYSZ_INS_CDLFTR = 786
SYSZ_INS_CDLGTR = 787
SYSZ_INS_CDPT = 788
SYSZ_INS_CDR = 789
SYSZ_INS_CDS = 790
SYSZ_INS_CDSG = 791
SYSZ_INS_CDSTR = 792
SYSZ_INS_CDSY = 793
SYSZ_INS_CDTR = 794
SYSZ_INS_CDUTR = 795
SYSZ_INS_CDZT = 796
SYSZ_INS_CE = 797
SYSZ_INS_CEDTR = 798
SYSZ_INS_CEFBRA = 799
SYSZ_INS_CEFR = 800
SYSZ_INS_CEGBRA = 801
SYSZ_INS_CEGR = 802
SYSZ_INS_CER = 803
SYSZ_INS_CEXTR = 804
SYSZ_INS_CFC = 805
SYSZ_INS_CFDBRA = 806
SYSZ_INS_CFDR = 807
SYSZ_INS_CFDTR = 808
SYSZ_INS_CFEBRA = 809
SYSZ_INS_CFER = 810
SYSZ_INS_CFXBRA = 811
SYSZ_INS_CFXR = 812
SYSZ_INS_CFXTR = 813
SYSZ_INS_CGDBRA = 814
SYSZ_INS_CGDR = 815
SYSZ_INS_CGDTR = 816
SYSZ_INS_CGDTRA = 817
SYSZ_INS_CGEBRA = 818
SYSZ_INS_CGER = 819
SYSZ_INS_CGIB = 820
SYSZ_INS_CGIBE = 821
SYSZ_INS_CGIBH = 822
SYSZ_INS_CGIBHE = 823
SYSZ_INS_CGIBL = 824
SYSZ_INS_CGIBLE = 825
SYSZ_INS_CGIBLH = 826
SYSZ_INS_CGIBNE = 827
SYSZ_INS_CGIBNH = 828
SYSZ_INS_CGIBNHE = 829
SYSZ_INS_CGIBNL = 830
SYSZ_INS_CGIBNLE = 831
SYSZ_INS_CGIBNLH = 832
SYSZ_INS_CGIT = 833
SYSZ_INS_CGITE = 834
SYSZ_INS_CGITH = 835
SYSZ_INS_CGITHE = 836
SYSZ_INS_CGITL = 837
SYSZ_INS_CGITLE = 838
SYSZ_INS_CGITLH = 839
SYSZ_INS_CGITNE = 840
SYSZ_INS_CGITNH = 841
SYSZ_INS_CGITNHE = 842
SYSZ_INS_CGITNL = 843
SYSZ_INS_CGITNLE = 844
SYSZ_INS_CGITNLH = 845
SYSZ_INS_CGRB = 846
SYSZ_INS_CGRBE = 847
SYSZ_INS_CGRBH = 848
SYSZ_INS_CGRBHE = 849
SYSZ_INS_CGRBL = 850
SYSZ_INS_CGRBLE = 851
SYSZ_INS_CGRBLH = 852
SYSZ_INS_CGRBNE = 853
SYSZ_INS_CGRBNH = 854
SYSZ_INS_CGRBNHE = 855
SYSZ_INS_CGRBNL = 856
SYSZ_INS_CGRBNLE = 857
SYSZ_INS_CGRBNLH = 858
SYSZ_INS_CGRT = 859
SYSZ_INS_CGRTE = 860
SYSZ_INS_CGRTH = 861
SYSZ_INS_CGRTHE = 862
SYSZ_INS_CGRTL = 863
SYSZ_INS_CGRTLE = 864
SYSZ_INS_CGRTLH = 865
SYSZ_INS_CGRTNE = 866
SYSZ_INS_CGRTNH = 867
SYSZ_INS_CGRTNHE = 868
SYSZ_INS_CGRTNL = 869
SYSZ_INS_CGRTNLE = 870
SYSZ_INS_CGRTNLH = 871
SYSZ_INS_CGXBRA = 872
SYSZ_INS_CGXR = 873
SYSZ_INS_CGXTR = 874
SYSZ_INS_CGXTRA = 875
SYSZ_INS_CHHR = 876
SYSZ_INS_CHLR = 877
SYSZ_INS_CIB = 878
SYSZ_INS_CIBE = 879
SYSZ_INS_CIBH = 880
SYSZ_INS_CIBHE = 881
SYSZ_INS_CIBL = 882
SYSZ_INS_CIBLE = 883
SYSZ_INS_CIBLH = 884
SYSZ_INS_CIBNE = 885
SYSZ_INS_CIBNH = 886
SYSZ_INS_CIBNHE = 887
SYSZ_INS_CIBNL = 888
SYSZ_INS_CIBNLE = 889
SYSZ_INS_CIBNLH = 890
SYSZ_INS_CIT = 891
SYSZ_INS_CITE = 892
SYSZ_INS_CITH = 893
SYSZ_INS_CITHE = 894
SYSZ_INS_CITL = 895
SYSZ_INS_CITLE = 896
SYSZ_INS_CITLH = 897
SYSZ_INS_CITNE = 898
SYSZ_INS_CITNH = 899
SYSZ_INS_CITNHE = 900
SYSZ_INS_CITNL = 901
SYSZ_INS_CITNLE = 902
SYSZ_INS_CITNLH = 903
SYSZ_INS_CKSM = 904
SYSZ_INS_CLCL = 905
SYSZ_INS_CLCLE = 906
SYSZ_INS_CLCLU = 907
SYSZ_INS_CLFDTR = 908
SYSZ_INS_CLFIT = 909
SYSZ_INS_CLFITE = 910
SYSZ_INS_CLFITH = 911
SYSZ_INS_CLFITHE = 912
SYSZ_INS_CLFITL = 913
SYSZ_INS_CLFITLE = 914
SYSZ_INS_CLFITLH = 915
SYSZ_INS_CLFITNE = 916
SYSZ_INS_CLFITNH = 917
SYSZ_INS_CLFITNHE = 918
SYSZ_INS_CLFITNL = 919
SYSZ_INS_CLFITNLE = 920
SYSZ_INS_CLFITNLH = 921
SYSZ_INS_CLFXTR = 922
SYSZ_INS_CLGDTR = 923
SYSZ_INS_CLGIB = 924
SYSZ_INS_CLGIBE = 925
SYSZ_INS_CLGIBH = 926
SYSZ_INS_CLGIBHE = 927
SYSZ_INS_CLGIBL = 928
SYSZ_INS_CLGIBLE = 929
SYSZ_INS_CLGIBLH = 930
SYSZ_INS_CLGIBNE = 931
SYSZ_INS_CLGIBNH = 932
SYSZ_INS_CLGIBNHE = 933
SYSZ_INS_CLGIBNL = 934
SYSZ_INS_CLGIBNLE = 935
SYSZ_INS_CLGIBNLH = 936
SYSZ_INS_CLGIT = 937
SYSZ_INS_CLGITE = 938
SYSZ_INS_CLGITH = 939
SYSZ_INS_CLGITHE = 940
SYSZ_INS_CLGITL = 941
SYSZ_INS_CLGITLE = 942
SYSZ_INS_CLGITLH = 943
SYSZ_INS_CLGITNE = 944
SYSZ_INS_CLGITNH = 945
SYSZ_INS_CLGITNHE = 946
SYSZ_INS_CLGITNL = 947
SYSZ_INS_CLGITNLE = 948
SYSZ_INS_CLGITNLH = 949
SYSZ_INS_CLGRB = 950
SYSZ_INS_CLGRBE = 951
SYSZ_INS_CLGRBH = 952
SYSZ_INS_CLGRBHE = 953
SYSZ_INS_CLGRBL = 954
SYSZ_INS_CLGRBLE = 955
SYSZ_INS_CLGRBLH = 956
SYSZ_INS_CLGRBNE = 957
SYSZ_INS_CLGRBNH = 958
SYSZ_INS_CLGRBNHE = 959
SYSZ_INS_CLGRBNL = 960
SYSZ_INS_CLGRBNLE = 961
SYSZ_INS_CLGRBNLH = 962
SYSZ_INS_CLGRT = 963
SYSZ_INS_CLGRTE = 964
SYSZ_INS_CLGRTH = 965
SYSZ_INS_CLGRTHE = 966
SYSZ_INS_CLGRTL = 967
SYSZ_INS_CLGRTLE = 968
SYSZ_INS_CLGRTLH = 969
SYSZ_INS_CLGRTNE = 970
SYSZ_INS_CLGRTNH = 971
SYSZ_INS_CLGRTNHE = 972
SYSZ_INS_CLGRTNL = 973
SYSZ_INS_CLGRTNLE = 974
SYSZ_INS_CLGRTNLH = 975
SYSZ_INS_CLGT = 976
SYSZ_INS_CLGTE = 977
SYSZ_INS_CLGTH = 978
SYSZ_INS_CLGTHE = 979
SYSZ_INS_CLGTL = 980
SYSZ_INS_CLGTLE = 981
SYSZ_INS_CLGTLH = 982
SYSZ_INS_CLGTNE = 983
SYSZ_INS_CLGTNH = 984
SYSZ_INS_CLGTNHE = 985
SYSZ_INS_CLGTNL = 986
SYSZ_INS_CLGTNLE = 987
SYSZ_INS_CLGTNLH = 988
SYSZ_INS_CLGXTR = 989
SYSZ_INS_CLHHR = 990
SYSZ_INS_CLHLR = 991
SYSZ_INS_CLIB = 992
SYSZ_INS_CLIBE = 993
SYSZ_INS_CLIBH = 994
SYSZ_INS_CLIBHE = 995
SYSZ_INS_CLIBL = 996
SYSZ_INS_CLIBLE = 997
SYSZ_INS_CLIBLH = 998
SYSZ_INS_CLIBNE = 999
SYSZ_INS_CLIBNH = 1000
SYSZ_INS_CLIBNHE = 1001
SYSZ_INS_CLIBNL = 1002
SYSZ_INS_CLIBNLE = 1003
SYSZ_INS_CLIBNLH = 1004
SYSZ_INS_CLM = 1005
SYSZ_INS_CLMH = 1006
SYSZ_INS_CLMY = 1007
SYSZ_INS_CLRB = 1008
SYSZ_INS_CLRBE = 1009
SYSZ_INS_CLRBH = 1010
SYSZ_INS_CLRBHE = 1011
SYSZ_INS_CLRBL = 1012
SYSZ_INS_CLRBLE = 1013
SYSZ_INS_CLRBLH = 1014
SYSZ_INS_CLRBNE = 1015
SYSZ_INS_CLRBNH = 1016
SYSZ_INS_CLRBNHE = 1017
SYSZ_INS_CLRBNL = 1018
SYSZ_INS_CLRBNLE = 1019
SYSZ_INS_CLRBNLH = 1020
SYSZ_INS_CLRT = 1021
SYSZ_INS_CLRTE = 1022
SYSZ_INS_CLRTH = 1023
SYSZ_INS_CLRTHE = 1024
SYSZ_INS_CLRTL = 1025
SYSZ_INS_CLRTLE = 1026
SYSZ_INS_CLRTLH = 1027
SYSZ_INS_CLRTNE = 1028
SYSZ_INS_CLRTNH = 1029
SYSZ_INS_CLRTNHE = 1030
SYSZ_INS_CLRTNL = 1031
SYSZ_INS_CLRTNLE = 1032
SYSZ_INS_CLRTNLH = 1033
SYSZ_INS_CLT = 1034
SYSZ_INS_CLTE = 1035
SYSZ_INS_CLTH = 1036
SYSZ_INS_CLTHE = 1037
SYSZ_INS_CLTL = 1038
SYSZ_INS_CLTLE = 1039
SYSZ_INS_CLTLH = 1040
SYSZ_INS_CLTNE = 1041
SYSZ_INS_CLTNH = 1042
SYSZ_INS_CLTNHE = 1043
SYSZ_INS_CLTNL = 1044
SYSZ_INS_CLTNLE = 1045
SYSZ_INS_CLTNLH = 1046
SYSZ_INS_CMPSC = 1047
SYSZ_INS_CP = 1048
SYSZ_INS_CPDT = 1049
SYSZ_INS_CPXT = 1050
SYSZ_INS_CPYA = 1051
SYSZ_INS_CRB = 1052
SYSZ_INS_CRBE = 1053
SYSZ_INS_CRBH = 1054
SYSZ_INS_CRBHE = 1055
SYSZ_INS_CRBL = 1056
SYSZ_INS_CRBLE = 1057
SYSZ_INS_CRBLH = 1058
SYSZ_INS_CRBNE = 1059
SYSZ_INS_CRBNH = 1060
SYSZ_INS_CRBNHE = 1061
SYSZ_INS_CRBNL = 1062
SYSZ_INS_CRBNLE = 1063
SYSZ_INS_CRBNLH = 1064
SYSZ_INS_CRDTE = 1065
SYSZ_INS_CRT = 1066
SYSZ_INS_CRTE = 1067
SYSZ_INS_CRTH = 1068
SYSZ_INS_CRTHE = 1069
SYSZ_INS_CRTL = 1070
SYSZ_INS_CRTLE = 1071
SYSZ_INS_CRTLH = 1072
SYSZ_INS_CRTNE = 1073
SYSZ_INS_CRTNH = 1074
SYSZ_INS_CRTNHE = 1075
SYSZ_INS_CRTNL = 1076
SYSZ_INS_CRTNLE = 1077
SYSZ_INS_CRTNLH = 1078
SYSZ_INS_CSCH = 1079
SYSZ_INS_CSDTR = 1080
SYSZ_INS_CSP = 1081
SYSZ_INS_CSPG = 1082
SYSZ_INS_CSST = 1083
SYSZ_INS_CSXTR = 1084
SYSZ_INS_CU12 = 1085
SYSZ_INS_CU14 = 1086
SYSZ_INS_CU21 = 1087
SYSZ_INS_CU24 = 1088
SYSZ_INS_CU41 = 1089
SYSZ_INS_CU42 = 1090
SYSZ_INS_CUDTR = 1091
SYSZ_INS_CUSE = 1092
SYSZ_INS_CUTFU = 1093
SYSZ_INS_CUUTF = 1094
SYSZ_INS_CUXTR = 1095
SYSZ_INS_CVB = 1096
SYSZ_INS_CVBG = 1097
SYSZ_INS_CVBY = 1098
SYSZ_INS_CVD = 1099
SYSZ_INS_CVDG = 1100
SYSZ_INS_CVDY = 1101
SYSZ_INS_CXFBRA = 1102
SYSZ_INS_CXFR = 1103
SYSZ_INS_CXFTR = 1104
SYSZ_INS_CXGBRA = 1105
SYSZ_INS_CXGR = 1106
SYSZ_INS_CXGTR = 1107
SYSZ_INS_CXGTRA = 1108
SYSZ_INS_CXLFTR = 1109
SYSZ_INS_CXLGTR = 1110
SYSZ_INS_CXPT = 1111
SYSZ_INS_CXR = 1112
SYSZ_INS_CXSTR = 1113
SYSZ_INS_CXTR = 1114
SYSZ_INS_CXUTR = 1115
SYSZ_INS_CXZT = 1116
SYSZ_INS_CZDT = 1117
SYSZ_INS_CZXT = 1118
SYSZ_INS_D = 1119
SYSZ_INS_DD = 1120
SYSZ_INS_DDR = 1121
SYSZ_INS_DDTR = 1122
SYSZ_INS_DDTRA = 1123
SYSZ_INS_DE = 1124
SYSZ_INS_DER = 1125
SYSZ_INS_DIAG = 1126
SYSZ_INS_DIDBR = 1127
SYSZ_INS_DIEBR = 1128
SYSZ_INS_DP = 1129
SYSZ_INS_DR = 1130
SYSZ_INS_DXR = 1131
SYSZ_INS_DXTR = 1132
SYSZ_INS_DXTRA = 1133
SYSZ_INS_ECAG = 1134
SYSZ_INS_ECCTR = 1135
SYSZ_INS_ECPGA = 1136
SYSZ_INS_ECTG = 1137
SYSZ_INS_ED = 1138
SYSZ_INS_EDMK = 1139
SYSZ_INS_EEDTR = 1140
SYSZ_INS_EEXTR = 1141
SYSZ_INS_EFPC = 1142
SYSZ_INS_EPAIR = 1143
SYSZ_INS_EPAR = 1144
SYSZ_INS_EPCTR = 1145
SYSZ_INS_EPSW = 1146
SYSZ_INS_EREG = 1147
SYSZ_INS_EREGG = 1148
SYSZ_INS_ESAIR = 1149
SYSZ_INS_ESAR = 1150
SYSZ_INS_ESDTR = 1151
SYSZ_INS_ESEA = 1152
SYSZ_INS_ESTA = 1153
SYSZ_INS_ESXTR = 1154
SYSZ_INS_ETND = 1155
SYSZ_INS_EX = 1156
SYSZ_INS_EXRL = 1157
SYSZ_INS_FIDR = 1158
SYSZ_INS_FIDTR = 1159
SYSZ_INS_FIER = 1160
SYSZ_INS_FIXR = 1161
SYSZ_INS_FIXTR = 1162
SYSZ_INS_HDR = 1163
SYSZ_INS_HER = 1164
SYSZ_INS_HSCH = 1165
SYSZ_INS_IAC = 1166
SYSZ_INS_ICM = 1167
SYSZ_INS_ICMH = 1168
SYSZ_INS_ICMY = 1169
SYSZ_INS_IDTE = 1170
SYSZ_INS_IEDTR = 1171
SYSZ_INS_IEXTR = 1172
SYSZ_INS_IPK = 1173
SYSZ_INS_IPTE = 1174
SYSZ_INS_IRBM = 1175
SYSZ_INS_ISKE = 1176
SYSZ_INS_IVSK = 1177
SYSZ_INS_JGM = 1178
SYSZ_INS_JGNM = 1179
SYSZ_INS_JGNP = 1180
SYSZ_INS_JGNZ = 1181
SYSZ_INS_JGP = 1182
SYSZ_INS_JGZ = 1183
SYSZ_INS_JM = 1184
SYSZ_INS_JNM = 1185
SYSZ_INS_JNP = 1186
SYSZ_INS_JNZ = 1187
SYSZ_INS_JP = 1188
SYSZ_INS_JZ = 1189
SYSZ_INS_KDB = 1190
SYSZ_INS_KDBR = 1191
SYSZ_INS_KDTR = 1192
SYSZ_INS_KEB = 1193
SYSZ_INS_KEBR = 1194
SYSZ_INS_KIMD = 1195
SYSZ_INS_KLMD = 1196
SYSZ_INS_KM = 1197
SYSZ_INS_KMA = 1198
SYSZ_INS_KMAC = 1199
SYSZ_INS_KMC = 1200
SYSZ_INS_KMCTR = 1201
SYSZ_INS_KMF = 1202
SYSZ_INS_KMO = 1203
SYSZ_INS_KXBR = 1204
SYSZ_INS_KXTR = 1205
SYSZ_INS_LAE = 1206
SYSZ_INS_LAEY = 1207
SYSZ_INS_LAM = 1208
SYSZ_INS_LAMY = 1209
SYSZ_INS_LASP = 1210
SYSZ_INS_LAT = 1211
SYSZ_INS_LCBB = 1212
SYSZ_INS_LCCTL = 1213
SYSZ_INS_LCDFR = 1214
SYSZ_INS_LCDR = 1215
SYSZ_INS_LCER = 1216
SYSZ_INS_LCTL = 1217
SYSZ_INS_LCTLG = 1218
SYSZ_INS_LCXR = 1219
SYSZ_INS_LDE = 1220
SYSZ_INS_LDER = 1221
SYSZ_INS_LDETR = 1222
SYSZ_INS_LDXR = 1223
SYSZ_INS_LDXTR = 1224
SYSZ_INS_LEDR = 1225
SYSZ_INS_LEDTR = 1226
SYSZ_INS_LEXR = 1227
SYSZ_INS_LFAS = 1228
SYSZ_INS_LFHAT = 1229
SYSZ_INS_LFPC = 1230
SYSZ_INS_LGAT = 1231
SYSZ_INS_LGG = 1232
SYSZ_INS_LGSC = 1233
SYSZ_INS_LLGFAT = 1234
SYSZ_INS_LLGFSG = 1235
SYSZ_INS_LLGT = 1236
SYSZ_INS_LLGTAT = 1237
SYSZ_INS_LLGTR = 1238
SYSZ_INS_LLZRGF = 1239
SYSZ_INS_LM = 1240
SYSZ_INS_LMD = 1241
SYSZ_INS_LMH = 1242
SYSZ_INS_LMY = 1243
SYSZ_INS_LNDFR = 1244
SYSZ_INS_LNDR = 1245
SYSZ_INS_LNER = 1246
SYSZ_INS_LNXR = 1247
SYSZ_INS_LOCFH = 1248
SYSZ_INS_LOCFHE = 1249
SYSZ_INS_LOCFHH = 1250
SYSZ_INS_LOCFHHE = 1251
SYSZ_INS_LOCFHL = 1252
SYSZ_INS_LOCFHLE = 1253
SYSZ_INS_LOCFHLH = 1254
SYSZ_INS_LOCFHM = 1255
SYSZ_INS_LOCFHNE = 1256
SYSZ_INS_LOCFHNH = 1257
SYSZ_INS_LOCFHNHE = 1258
SYSZ_INS_LOCFHNL = 1259
SYSZ_INS_LOCFHNLE = 1260
SYSZ_INS_LOCFHNLH = 1261
SYSZ_INS_LOCFHNM = 1262
SYSZ_INS_LOCFHNO = 1263
SYSZ_INS_LOCFHNP = 1264
SYSZ_INS_LOCFHNZ = 1265
SYSZ_INS_LOCFHO = 1266
SYSZ_INS_LOCFHP = 1267
SYSZ_INS_LOCFHR = 1268
SYSZ_INS_LOCFHRE = 1269
SYSZ_INS_LOCFHRH = 1270
SYSZ_INS_LOCFHRHE = 1271
SYSZ_INS_LOCFHRL = 1272
SYSZ_INS_LOCFHRLE = 1273
SYSZ_INS_LOCFHRLH = 1274
SYSZ_INS_LOCFHRM = 1275
SYSZ_INS_LOCFHRNE = 1276
SYSZ_INS_LOCFHRNH = 1277
SYSZ_INS_LOCFHRNHE = 1278
SYSZ_INS_LOCFHRNL = 1279
SYSZ_INS_LOCFHRNLE = 1280
SYSZ_INS_LOCFHRNLH = 1281
SYSZ_INS_LOCFHRNM = 1282
SYSZ_INS_LOCFHRNO = 1283
SYSZ_INS_LOCFHRNP = 1284
SYSZ_INS_LOCFHRNZ = 1285
SYSZ_INS_LOCFHRO = 1286
SYSZ_INS_LOCFHRP = 1287
SYSZ_INS_LOCFHRZ = 1288
SYSZ_INS_LOCFHZ = 1289
SYSZ_INS_LOCGHI = 1290
SYSZ_INS_LOCGHIE = 1291
SYSZ_INS_LOCGHIH = 1292
SYSZ_INS_LOCGHIHE = 1293
SYSZ_INS_LOCGHIL = 1294
SYSZ_INS_LOCGHILE = 1295
SYSZ_INS_LOCGHILH = 1296
SYSZ_INS_LOCGHIM = 1297
SYSZ_INS_LOCGHINE = 1298
SYSZ_INS_LOCGHINH = 1299
SYSZ_INS_LOCGHINHE = 1300
SYSZ_INS_LOCGHINL = 1301
SYSZ_INS_LOCGHINLE = 1302
SYSZ_INS_LOCGHINLH = 1303
SYSZ_INS_LOCGHINM = 1304
SYSZ_INS_LOCGHINO = 1305
SYSZ_INS_LOCGHINP = 1306
SYSZ_INS_LOCGHINZ = 1307
SYSZ_INS_LOCGHIO = 1308
SYSZ_INS_LOCGHIP = 1309
SYSZ_INS_LOCGHIZ = 1310
SYSZ_INS_LOCGM = 1311
SYSZ_INS_LOCGNM = 1312
SYSZ_INS_LOCGNP = 1313
SYSZ_INS_LOCGNZ = 1314
SYSZ_INS_LOCGP = 1315
SYSZ_INS_LOCGRM = 1316
SYSZ_INS_LOCGRNM = 1317
SYSZ_INS_LOCGRNP = 1318
SYSZ_INS_LOCGRNZ = 1319
SYSZ_INS_LOCGRP = 1320
SYSZ_INS_LOCGRZ = 1321
SYSZ_INS_LOCGZ = 1322
SYSZ_INS_LOCHHI = 1323
SYSZ_INS_LOCHHIE = 1324
SYSZ_INS_LOCHHIH = 1325
SYSZ_INS_LOCHHIHE = 1326
SYSZ_INS_LOCHHIL = 1327
SYSZ_INS_LOCHHILE = 1328
SYSZ_INS_LOCHHILH = 1329
SYSZ_INS_LOCHHIM = 1330
SYSZ_INS_LOCHHINE = 1331
SYSZ_INS_LOCHHINH = 1332
SYSZ_INS_LOCHHINHE = 1333
SYSZ_INS_LOCHHINL = 1334
SYSZ_INS_LOCHHINLE = 1335
SYSZ_INS_LOCHHINLH = 1336
SYSZ_INS_LOCHHINM = 1337
SYSZ_INS_LOCHHINO = 1338
SYSZ_INS_LOCHHINP = 1339
SYSZ_INS_LOCHHINZ = 1340
SYSZ_INS_LOCHHIO = 1341
SYSZ_INS_LOCHHIP = 1342
SYSZ_INS_LOCHHIZ = 1343
SYSZ_INS_LOCHI = 1344
SYSZ_INS_LOCHIE = 1345
SYSZ_INS_LOCHIH = 1346
SYSZ_INS_LOCHIHE = 1347
SYSZ_INS_LOCHIL = 1348
SYSZ_INS_LOCHILE = 1349
SYSZ_INS_LOCHILH = 1350
SYSZ_INS_LOCHIM = 1351
SYSZ_INS_LOCHINE = 1352
SYSZ_INS_LOCHINH = 1353
SYSZ_INS_LOCHINHE = 1354
SYSZ_INS_LOCHINL = 1355
SYSZ_INS_LOCHINLE = 1356
SYSZ_INS_LOCHINLH = 1357
SYSZ_INS_LOCHINM = 1358
SYSZ_INS_LOCHINO = 1359
SYSZ_INS_LOCHINP = 1360
SYSZ_INS_LOCHINZ = 1361
SYSZ_INS_LOCHIO = 1362
SYSZ_INS_LOCHIP = 1363
SYSZ_INS_LOCHIZ = 1364
SYSZ_INS_LOCM = 1365
SYSZ_INS_LOCNM = 1366
SYSZ_INS_LOCNP = 1367
SYSZ_INS_LOCNZ = 1368
SYSZ_INS_LOCP = 1369
SYSZ_INS_LOCRM = 1370
SYSZ_INS_LOCRNM = 1371
SYSZ_INS_LOCRNP = 1372
SYSZ_INS_LOCRNZ = 1373
SYSZ_INS_LOCRP = 1374
SYSZ_INS_LOCRZ = 1375
SYSZ_INS_LOCZ = 1376
SYSZ_INS_LPCTL = 1377
SYSZ_INS_LPD = 1378
SYSZ_INS_LPDFR = 1379
SYSZ_INS_LPDG = 1380
SYSZ_INS_LPDR = 1381
SYSZ_INS_LPER = 1382
SYSZ_INS_LPP = 1383
SYSZ_INS_LPQ = 1384
SYSZ_INS_LPSW = 1385
SYSZ_INS_LPSWE = 1386
SYSZ_INS_LPTEA = 1387
SYSZ_INS_LPXR = 1388
SYSZ_INS_LRA = 1389
SYSZ_INS_LRAG = 1390
SYSZ_INS_LRAY = 1391
SYSZ_INS_LRDR = 1392
SYSZ_INS_LRER = 1393
SYSZ_INS_LRVH = 1394
SYSZ_INS_LSCTL = 1395
SYSZ_INS_LTDR = 1396
SYSZ_INS_LTDTR = 1397
SYSZ_INS_LTER = 1398
SYSZ_INS_LTXR = 1399
SYSZ_INS_LTXTR = 1400
SYSZ_INS_LURA = 1401
SYSZ_INS_LURAG = 1402
SYSZ_INS_LXD = 1403
SYSZ_INS_LXDR = 1404
SYSZ_INS_LXDTR = 1405
SYSZ_INS_LXE = 1406
SYSZ_INS_LXER = 1407
SYSZ_INS_LZRF = 1408
SYSZ_INS_LZRG = 1409
SYSZ_INS_M = 1410
SYSZ_INS_MAD = 1411
SYSZ_INS_MADR = 1412
SYSZ_INS_MAE = 1413
SYSZ_INS_MAER = 1414
SYSZ_INS_MAY = 1415
SYSZ_INS_MAYH = 1416
SYSZ_INS_MAYHR = 1417
SYSZ_INS_MAYL = 1418
SYSZ_INS_MAYLR = 1419
SYSZ_INS_MAYR = 1420
SYSZ_INS_MC = 1421
SYSZ_INS_MD = 1422
SYSZ_INS_MDE = 1423
SYSZ_INS_MDER = 1424
SYSZ_INS_MDR = 1425
SYSZ_INS_MDTR = 1426
SYSZ_INS_MDTRA = 1427
SYSZ_INS_ME = 1428
SYSZ_INS_MEE = 1429
SYSZ_INS_MEER = 1430
SYSZ_INS_MER = 1431
SYSZ_INS_MFY = 1432
SYSZ_INS_MG = 1433
SYSZ_INS_MGH = 1434
SYSZ_INS_MGRK = 1435
SYSZ_INS_ML = 1436
SYSZ_INS_MLR = 1437
SYSZ_INS_MP = 1438
SYSZ_INS_MR = 1439
SYSZ_INS_MSC = 1440
SYSZ_INS_MSCH = 1441
SYSZ_INS_MSD = 1442
SYSZ_INS_MSDR = 1443
SYSZ_INS_MSE = 1444
SYSZ_INS_MSER = 1445
SYSZ_INS_MSGC = 1446
SYSZ_INS_MSGRKC = 1447
SYSZ_INS_MSRKC = 1448
SYSZ_INS_MSTA = 1449
SYSZ_INS_MVCDK = 1450
SYSZ_INS_MVCIN = 1451
SYSZ_INS_MVCK = 1452
SYSZ_INS_MVCL = 1453
SYSZ_INS_MVCLE = 1454
SYSZ_INS_MVCLU = 1455
SYSZ_INS_MVCOS = 1456
SYSZ_INS_MVCP = 1457
SYSZ_INS_MVCS = 1458
SYSZ_INS_MVCSK = 1459
SYSZ_INS_MVN = 1460
SYSZ_INS_MVO = 1461
SYSZ_INS_MVPG = 1462
SYSZ_INS_MVZ = 1463
SYSZ_INS_MXD = 1464
SYSZ_INS_MXDR = 1465
SYSZ_INS_MXR = 1466
SYSZ_INS_MXTR = 1467
SYSZ_INS_MXTRA = 1468
SYSZ_INS_MY = 1469
SYSZ_INS_MYH = 1470
SYSZ_INS_MYHR = 1471
SYSZ_INS_MYL = 1472
SYSZ_INS_MYLR = 1473
SYSZ_INS_MYR = 1474
SYSZ_INS_NIAI = 1475
SYSZ_INS_NTSTG = 1476
SYSZ_INS_PACK = 1477
SYSZ_INS_PALB = 1478
SYSZ_INS_PC = 1479
SYSZ_INS_PCC = 1480
SYSZ_INS_PCKMO = 1481
SYSZ_INS_PFMF = 1482
SYSZ_INS_PFPO = 1483
SYSZ_INS_PGIN = 1484
SYSZ_INS_PGOUT = 1485
SYSZ_INS_PKA = 1486
SYSZ_INS_PKU = 1487
SYSZ_INS_PLO = 1488
SYSZ_INS_POPCNT = 1489
SYSZ_INS_PPA = 1490
SYSZ_INS_PPNO = 1491
SYSZ_INS_PR = 1492
SYSZ_INS_PRNO = 1493
SYSZ_INS_PT = 1494
SYSZ_INS_PTF = 1495
SYSZ_INS_PTFF = 1496
SYSZ_INS_PTI = 1497
SYSZ_INS_PTLB = 1498
SYSZ_INS_QADTR = 1499
SYSZ_INS_QAXTR = 1500
SYSZ_INS_QCTRI = 1501
SYSZ_INS_QSI = 1502
SYSZ_INS_RCHP = 1503
SYSZ_INS_RISBGN = 1504
SYSZ_INS_RP = 1505
SYSZ_INS_RRBE = 1506
SYSZ_INS_RRBM = 1507
SYSZ_INS_RRDTR = 1508
SYSZ_INS_RRXTR = 1509
SYSZ_INS_RSCH = 1510
SYSZ_INS_SAC = 1511
SYSZ_INS_SACF = 1512
SYSZ_INS_SAL = 1513
SYSZ_INS_SAM24 = 1514
SYSZ_INS_SAM31 = 1515
SYSZ_INS_SAM64 = 1516
SYSZ_INS_SAR = 1517
SYSZ_INS_SCCTR = 1518
SYSZ_INS_SCHM = 1519
SYSZ_INS_SCK = 1520
SYSZ_INS_SCKC = 1521
SYSZ_INS_SCKPF = 1522
SYSZ_INS_SD = 1523
SYSZ_INS_SDR = 1524
SYSZ_INS_SDTR = 1525
SYSZ_INS_SDTRA = 1526
SYSZ_INS_SE = 1527
SYSZ_INS_SER = 1528
SYSZ_INS_SFASR = 1529
SYSZ_INS_SFPC = 1530
SYSZ_INS_SGH = 1531
SYSZ_INS_SHHHR = 1532
SYSZ_INS_SHHLR = 1533
SYSZ_INS_SIE = 1534
SYSZ_INS_SIGA = 1535
SYSZ_INS_SIGP = 1536
SYSZ_INS_SLA = 1537
SYSZ_INS_SLAG = 1538
SYSZ_INS_SLAK = 1539
SYSZ_INS_SLDA = 1540
SYSZ_INS_SLDL = 1541
SYSZ_INS_SLDT = 1542
SYSZ_INS_SLHHHR = 1543
SYSZ_INS_SLHHLR = 1544
SYSZ_INS_SLXT = 1545
SYSZ_INS_SP = 1546
SYSZ_INS_SPCTR = 1547
SYSZ_INS_SPKA = 1548
SYSZ_INS_SPM = 1549
SYSZ_INS_SPT = 1550
SYSZ_INS_SPX = 1551
SYSZ_INS_SQD = 1552
SYSZ_INS_SQDR = 1553
SYSZ_INS_SQE = 1554
SYSZ_INS_SQER = 1555
SYSZ_INS_SQXR = 1556
SYSZ_INS_SRDA = 1557
SYSZ_INS_SRDL = 1558
SYSZ_INS_SRDT = 1559
SYSZ_INS_SRNM = 1560
SYSZ_INS_SRNMB = 1561
SYSZ_INS_SRNMT = 1562
SYSZ_INS_SRP = 1563
SYSZ_INS_SRSTU = 1564
SYSZ_INS_SRXT = 1565
SYSZ_INS_SSAIR = 1566
SYSZ_INS_SSAR = 1567
SYSZ_INS_SSCH = 1568
SYSZ_INS_SSKE = 1569
SYSZ_INS_SSM = 1570
SYSZ_INS_STAM = 1571
SYSZ_INS_STAMY = 1572
SYSZ_INS_STAP = 1573
SYSZ_INS_STCK = 1574
SYSZ_INS_STCKC = 1575
SYSZ_INS_STCKE = 1576
SYSZ_INS_STCKF = 1577
SYSZ_INS_STCM = 1578
SYSZ_INS_STCMH = 1579
SYSZ_INS_STCMY = 1580
SYSZ_INS_STCPS = 1581
SYSZ_INS_STCRW = 1582
SYSZ_INS_STCTG = 1583
SYSZ_INS_STCTL = 1584
SYSZ_INS_STFL = 1585
SYSZ_INS_STFLE = 1586
SYSZ_INS_STFPC = 1587
SYSZ_INS_STGSC = 1588
SYSZ_INS_STIDP = 1589
SYSZ_INS_STM = 1590
SYSZ_INS_STMH = 1591
SYSZ_INS_STMY = 1592
SYSZ_INS_STNSM = 1593
SYSZ_INS_STOCFH = 1594
SYSZ_INS_STOCFHE = 1595
SYSZ_INS_STOCFHH = 1596
SYSZ_INS_STOCFHHE = 1597
SYSZ_INS_STOCFHL = 1598
SYSZ_INS_STOCFHLE = 1599
SYSZ_INS_STOCFHLH = 1600
SYSZ_INS_STOCFHM = 1601
SYSZ_INS_STOCFHNE = 1602
SYSZ_INS_STOCFHNH = 1603
SYSZ_INS_STOCFHNHE = 1604
SYSZ_INS_STOCFHNL = 1605
SYSZ_INS_STOCFHNLE = 1606
SYSZ_INS_STOCFHNLH = 1607
SYSZ_INS_STOCFHNM = 1608
SYSZ_INS_STOCFHNO = 1609
SYSZ_INS_STOCFHNP = 1610
SYSZ_INS_STOCFHNZ = 1611
SYSZ_INS_STOCFHO = 1612
SYSZ_INS_STOCFHP = 1613
SYSZ_INS_STOCFHZ = 1614
SYSZ_INS_STOCGM = 1615
SYSZ_INS_STOCGNM = 1616
SYSZ_INS_STOCGNP = 1617
SYSZ_INS_STOCGNZ = 1618
SYSZ_INS_STOCGP = 1619
SYSZ_INS_STOCGZ = 1620
SYSZ_INS_STOCM = 1621
SYSZ_INS_STOCNM = 1622
SYSZ_INS_STOCNP = 1623
SYSZ_INS_STOCNZ = 1624
SYSZ_INS_STOCP = 1625
SYSZ_INS_STOCZ = 1626
SYSZ_INS_STOSM = 1627
SYSZ_INS_STPQ = 1628
SYSZ_INS_STPT = 1629
SYSZ_INS_STPX = 1630
SYSZ_INS_STRAG = 1631
SYSZ_INS_STRVH = 1632
SYSZ_INS_STSCH = 1633
SYSZ_INS_STSI = 1634
SYSZ_INS_STURA = 1635
SYSZ_INS_STURG = 1636
SYSZ_INS_SU = 1637
SYSZ_INS_SUR = 1638
SYSZ_INS_SVC = 1639
SYSZ_INS_SW = 1640
SYSZ_INS_SWR = 1641
SYSZ_INS_SXR = 1642
SYSZ_INS_SXTR = 1643
SYSZ_INS_SXTRA = 1644
SYSZ_INS_TABORT = 1645
SYSZ_INS_TAM = 1646
SYSZ_INS_TAR = 1647
SYSZ_INS_TB = 1648
SYSZ_INS_TBDR = 1649
SYSZ_INS_TBEDR = 1650
SYSZ_INS_TBEGIN = 1651
SYSZ_INS_TBEGINC = 1652
SYSZ_INS_TCDB = 1653
SYSZ_INS_TCEB = 1654
SYSZ_INS_TCXB = 1655
SYSZ_INS_TDCDT = 1656
SYSZ_INS_TDCET = 1657
SYSZ_INS_TDCXT = 1658
SYSZ_INS_TDGDT = 1659
SYSZ_INS_TDGET = 1660
SYSZ_INS_TDGXT = 1661
SYSZ_INS_TEND = 1662
SYSZ_INS_THDER = 1663
SYSZ_INS_THDR = 1664
SYSZ_INS_TP = 1665
SYSZ_INS_TPI = 1666
SYSZ_INS_TPROT = 1667
SYSZ_INS_TR = 1668
SYSZ_INS_TRACE = 1669
SYSZ_INS_TRACG = 1670
SYSZ_INS_TRAP2 = 1671
SYSZ_INS_TRAP4 = 1672
SYSZ_INS_TRE = 1673
SYSZ_INS_TROO = 1674
SYSZ_INS_TROT = 1675
SYSZ_INS_TRT = 1676
SYSZ_INS_TRTE = 1677
SYSZ_INS_TRTO = 1678
SYSZ_INS_TRTR = 1679
SYSZ_INS_TRTRE = 1680
SYSZ_INS_TRTT = 1681
SYSZ_INS_TS = 1682
SYSZ_INS_TSCH = 1683
SYSZ_INS_UNPK = 1684
SYSZ_INS_UNPKA = 1685
SYSZ_INS_UNPKU = 1686
SYSZ_INS_UPT = 1687
SYSZ_INS_VA = 1688
SYSZ_INS_VAB = 1689
SYSZ_INS_VAC = 1690
SYSZ_INS_VACC = 1691
SYSZ_INS_VACCB = 1692
SYSZ_INS_VACCC = 1693
SYSZ_INS_VACCCQ = 1694
SYSZ_INS_VACCF = 1695
SYSZ_INS_VACCG = 1696
SYSZ_INS_VACCH = 1697
SYSZ_INS_VACCQ = 1698
SYSZ_INS_VACQ = 1699
SYSZ_INS_VAF = 1700
SYSZ_INS_VAG = 1701
SYSZ_INS_VAH = 1702
SYSZ_INS_VAP = 1703
SYSZ_INS_VAQ = 1704
SYSZ_INS_VAVG = 1705
SYSZ_INS_VAVGB = 1706
SYSZ_INS_VAVGF = 1707
SYSZ_INS_VAVGG = 1708
SYSZ_INS_VAVGH = 1709
SYSZ_INS_VAVGL = 1710
SYSZ_INS_VAVGLB = 1711
SYSZ_INS_VAVGLF = 1712
SYSZ_INS_VAVGLG = 1713
SYSZ_INS_VAVGLH = 1714
SYSZ_INS_VBPERM = 1715
SYSZ_INS_VCDG = 1716
SYSZ_INS_VCDGB = 1717
SYSZ_INS_VCDLG = 1718
SYSZ_INS_VCDLGB = 1719
SYSZ_INS_VCEQ = 1720
SYSZ_INS_VCEQB = 1721
SYSZ_INS_VCEQBS = 1722
SYSZ_INS_VCEQF = 1723
SYSZ_INS_VCEQFS = 1724
SYSZ_INS_VCEQG = 1725
SYSZ_INS_VCEQGS = 1726
SYSZ_INS_VCEQH = 1727
SYSZ_INS_VCEQHS = 1728
SYSZ_INS_VCGD = 1729
SYSZ_INS_VCGDB = 1730
SYSZ_INS_VCH = 1731
SYSZ_INS_VCHB = 1732
SYSZ_INS_VCHBS = 1733
SYSZ_INS_VCHF = 1734
SYSZ_INS_VCHFS = 1735
SYSZ_INS_VCHG = 1736
SYSZ_INS_VCHGS = 1737
SYSZ_INS_VCHH = 1738
SYSZ_INS_VCHHS = 1739
SYSZ_INS_VCHL = 1740
SYSZ_INS_VCHLB = 1741
SYSZ_INS_VCHLBS = 1742
SYSZ_INS_VCHLF = 1743
SYSZ_INS_VCHLFS = 1744
SYSZ_INS_VCHLG = 1745
SYSZ_INS_VCHLGS = 1746
SYSZ_INS_VCHLH = 1747
SYSZ_INS_VCHLHS = 1748
SYSZ_INS_VCKSM = 1749
SYSZ_INS_VCLGD = 1750
SYSZ_INS_VCLGDB = 1751
SYSZ_INS_VCLZ = 1752
SYSZ_INS_VCLZB = 1753
SYSZ_INS_VCLZF = 1754
SYSZ_INS_VCLZG = 1755
SYSZ_INS_VCLZH = 1756
SYSZ_INS_VCP = 1757
SYSZ_INS_VCTZ = 1758
SYSZ_INS_VCTZB = 1759
SYSZ_INS_VCTZF = 1760
SYSZ_INS_VCTZG = 1761
SYSZ_INS_VCTZH = 1762
SYSZ_INS_VCVB = 1763
SYSZ_INS_VCVBG = 1764
SYSZ_INS_VCVD = 1765
SYSZ_INS_VCVDG = 1766
SYSZ_INS_VDP = 1767
SYSZ_INS_VEC = 1768
SYSZ_INS_VECB = 1769
SYSZ_INS_VECF = 1770
SYSZ_INS_VECG = 1771
SYSZ_INS_VECH = 1772
SYSZ_INS_VECL = 1773
SYSZ_INS_VECLB = 1774
SYSZ_INS_VECLF = 1775
SYSZ_INS_VECLG = 1776
SYSZ_INS_VECLH = 1777
SYSZ_INS_VERIM = 1778
SYSZ_INS_VERIMB = 1779
SYSZ_INS_VERIMF = 1780
SYSZ_INS_VERIMG = 1781
SYSZ_INS_VERIMH = 1782
SYSZ_INS_VERLL = 1783
SYSZ_INS_VERLLB = 1784
SYSZ_INS_VERLLF = 1785
SYSZ_INS_VERLLG = 1786
SYSZ_INS_VERLLH = 1787
SYSZ_INS_VERLLV = 1788
SYSZ_INS_VERLLVB = 1789
SYSZ_INS_VERLLVF = 1790
SYSZ_INS_VERLLVG = 1791
SYSZ_INS_VERLLVH = 1792
SYSZ_INS_VESL = 1793
SYSZ_INS_VESLB = 1794
SYSZ_INS_VESLF = 1795
SYSZ_INS_VESLG = 1796
SYSZ_INS_VESLH = 1797
SYSZ_INS_VESLV = 1798
SYSZ_INS_VESLVB = 1799
SYSZ_INS_VESLVF = 1800
SYSZ_INS_VESLVG = 1801
SYSZ_INS_VESLVH = 1802
SYSZ_INS_VESRA = 1803
SYSZ_INS_VESRAB = 1804
SYSZ_INS_VESRAF = 1805
SYSZ_INS_VESRAG = 1806
SYSZ_INS_VESRAH = 1807
SYSZ_INS_VESRAV = 1808
SYSZ_INS_VESRAVB = 1809
SYSZ_INS_VESRAVF = 1810
SYSZ_INS_VESRAVG = 1811
SYSZ_INS_VESRAVH = 1812
SYSZ_INS_VESRL = 1813
SYSZ_INS_VESRLB = 1814
SYSZ_INS_VESRLF = 1815
SYSZ_INS_VESRLG = 1816
SYSZ_INS_VESRLH = 1817
SYSZ_INS_VESRLV = 1818
SYSZ_INS_VESRLVB = 1819
SYSZ_INS_VESRLVF = 1820
SYSZ_INS_VESRLVG = 1821
SYSZ_INS_VESRLVH = 1822
SYSZ_INS_VFA = 1823
SYSZ_INS_VFADB = 1824
SYSZ_INS_VFAE = 1825
SYSZ_INS_VFAEB = 1826
SYSZ_INS_VFAEBS = 1827
SYSZ_INS_VFAEF = 1828
SYSZ_INS_VFAEFS = 1829
SYSZ_INS_VFAEH = 1830
SYSZ_INS_VFAEHS = 1831
SYSZ_INS_VFAEZB = 1832
SYSZ_INS_VFAEZBS = 1833
SYSZ_INS_VFAEZF = 1834
SYSZ_INS_VFAEZFS = 1835
SYSZ_INS_VFAEZH = 1836
SYSZ_INS_VFAEZHS = 1837
SYSZ_INS_VFASB = 1838
SYSZ_INS_VFCE = 1839
SYSZ_INS_VFCEDB = 1840
SYSZ_INS_VFCEDBS = 1841
SYSZ_INS_VFCESB = 1842
SYSZ_INS_VFCESBS = 1843
SYSZ_INS_VFCH = 1844
SYSZ_INS_VFCHDB = 1845
SYSZ_INS_VFCHDBS = 1846
SYSZ_INS_VFCHE = 1847
SYSZ_INS_VFCHEDB = 1848
SYSZ_INS_VFCHEDBS = 1849
SYSZ_INS_VFCHESB = 1850
SYSZ_INS_VFCHESBS = 1851
SYSZ_INS_VFCHSB = 1852
SYSZ_INS_VFCHSBS = 1853
SYSZ_INS_VFD = 1854
SYSZ_INS_VFDDB = 1855
SYSZ_INS_VFDSB = 1856
SYSZ_INS_VFEE = 1857
SYSZ_INS_VFEEB = 1858
SYSZ_INS_VFEEBS = 1859
SYSZ_INS_VFEEF = 1860
SYSZ_INS_VFEEFS = 1861
SYSZ_INS_VFEEH = 1862
SYSZ_INS_VFEEHS = 1863
SYSZ_INS_VFEEZB = 1864
SYSZ_INS_VFEEZBS = 1865
SYSZ_INS_VFEEZF = 1866
SYSZ_INS_VFEEZFS = 1867
SYSZ_INS_VFEEZH = 1868
SYSZ_INS_VFEEZHS = 1869
SYSZ_INS_VFENE = 1870
SYSZ_INS_VFENEB = 1871
SYSZ_INS_VFENEBS = 1872
SYSZ_INS_VFENEF = 1873
SYSZ_INS_VFENEFS = 1874
SYSZ_INS_VFENEH = 1875
SYSZ_INS_VFENEHS = 1876
SYSZ_INS_VFENEZB = 1877
SYSZ_INS_VFENEZBS = 1878
SYSZ_INS_VFENEZF = 1879
SYSZ_INS_VFENEZFS = 1880
SYSZ_INS_VFENEZH = 1881
SYSZ_INS_VFENEZHS = 1882
SYSZ_INS_VFI = 1883
SYSZ_INS_VFIDB = 1884
SYSZ_INS_VFISB = 1885
SYSZ_INS_VFKEDB = 1886
SYSZ_INS_VFKEDBS = 1887
SYSZ_INS_VFKESB = 1888
SYSZ_INS_VFKESBS = 1889
SYSZ_INS_VFKHDB = 1890
SYSZ_INS_VFKHDBS = 1891
SYSZ_INS_VFKHEDB = 1892
SYSZ_INS_VFKHEDBS = 1893
SYSZ_INS_VFKHESB = 1894
SYSZ_INS_VFKHESBS = 1895
SYSZ_INS_VFKHSB = 1896
SYSZ_INS_VFKHSBS = 1897
SYSZ_INS_VFLCDB = 1898
SYSZ_INS_VFLCSB = 1899
SYSZ_INS_VFLL = 1900
SYSZ_INS_VFLLS = 1901
SYSZ_INS_VFLNDB = 1902
SYSZ_INS_VFLNSB = 1903
SYSZ_INS_VFLPDB = 1904
SYSZ_INS_VFLPSB = 1905
SYSZ_INS_VFLR = 1906
SYSZ_INS_VFLRD = 1907
SYSZ_INS_VFM = 1908
SYSZ_INS_VFMA = 1909
SYSZ_INS_VFMADB = 1910
SYSZ_INS_VFMASB = 1911
SYSZ_INS_VFMAX = 1912
SYSZ_INS_VFMAXDB = 1913
SYSZ_INS_VFMAXSB = 1914
SYSZ_INS_VFMDB = 1915
SYSZ_INS_VFMIN = 1916
SYSZ_INS_VFMINDB = 1917
SYSZ_INS_VFMINSB = 1918
SYSZ_INS_VFMS = 1919
SYSZ_INS_VFMSB = 1920
SYSZ_INS_VFMSDB = 1921
SYSZ_INS_VFMSSB = 1922
SYSZ_INS_VFNMA = 1923
SYSZ_INS_VFNMADB = 1924
SYSZ_INS_VFNMASB = 1925
SYSZ_INS_VFNMS = 1926
SYSZ_INS_VFNMSDB = 1927
SYSZ_INS_VFNMSSB = 1928
SYSZ_INS_VFPSO = 1929
SYSZ_INS_VFPSODB = 1930
SYSZ_INS_VFPSOSB = 1931
SYSZ_INS_VFS = 1932
SYSZ_INS_VFSDB = 1933
SYSZ_INS_VFSQ = 1934
SYSZ_INS_VFSQDB = 1935
SYSZ_INS_VFSQSB = 1936
SYSZ_INS_VFSSB = 1937
SYSZ_INS_VFTCI = 1938
SYSZ_INS_VFTCIDB = 1939
SYSZ_INS_VFTCISB = 1940
SYSZ_INS_VGBM = 1941
SYSZ_INS_VGEF = 1942
SYSZ_INS_VGEG = 1943
SYSZ_INS_VGFM = 1944
SYSZ_INS_VGFMA = 1945
SYSZ_INS_VGFMAB = 1946
SYSZ_INS_VGFMAF = 1947
SYSZ_INS_VGFMAG = 1948
SYSZ_INS_VGFMAH = 1949
SYSZ_INS_VGFMB = 1950
SYSZ_INS_VGFMF = 1951
SYSZ_INS_VGFMG = 1952
SYSZ_INS_VGFMH = 1953
SYSZ_INS_VGM = 1954
SYSZ_INS_VGMB = 1955
SYSZ_INS_VGMF = 1956
SYSZ_INS_VGMG = 1957
SYSZ_INS_VGMH = 1958
SYSZ_INS_VISTR = 1959
SYSZ_INS_VISTRB = 1960
SYSZ_INS_VISTRBS = 1961
SYSZ_INS_VISTRF = 1962
SYSZ_INS_VISTRFS = 1963
SYSZ_INS_VISTRH = 1964
SYSZ_INS_VISTRHS = 1965
SYSZ_INS_VL = 1966
SYSZ_INS_VLBB = 1967
SYSZ_INS_VLC = 1968
SYSZ_INS_VLCB = 1969
SYSZ_INS_VLCF = 1970
SYSZ_INS_VLCG = 1971
SYSZ_INS_VLCH = 1972
SYSZ_INS_VLDE = 1973
SYSZ_INS_VLDEB = 1974
SYSZ_INS_VLEB = 1975
SYSZ_INS_VLED = 1976
SYSZ_INS_VLEDB = 1977
SYSZ_INS_VLEF = 1978
SYSZ_INS_VLEG = 1979
SYSZ_INS_VLEH = 1980
SYSZ_INS_VLEIB = 1981
SYSZ_INS_VLEIF = 1982
SYSZ_INS_VLEIG = 1983
SYSZ_INS_VLEIH = 1984
SYSZ_INS_VLGV = 1985
SYSZ_INS_VLGVB = 1986
SYSZ_INS_VLGVF = 1987
SYSZ_INS_VLGVG = 1988
SYSZ_INS_VLGVH = 1989
SYSZ_INS_VLIP = 1990
SYSZ_INS_VLL = 1991
SYSZ_INS_VLLEZ = 1992
SYSZ_INS_VLLEZB = 1993
SYSZ_INS_VLLEZF = 1994
SYSZ_INS_VLLEZG = 1995
SYSZ_INS_VLLEZH = 1996
SYSZ_INS_VLLEZLF = 1997
SYSZ_INS_VLM = 1998
SYSZ_INS_VLP = 1999
SYSZ_INS_VLPB = 2000
SYSZ_INS_VLPF = 2001
SYSZ_INS_VLPG = 2002
SYSZ_INS_VLPH = 2003
SYSZ_INS_VLR = 2004
SYSZ_INS_VLREP = 2005
SYSZ_INS_VLREPB = 2006
SYSZ_INS_VLREPF = 2007
SYSZ_INS_VLREPG = 2008
SYSZ_INS_VLREPH = 2009
SYSZ_INS_VLRL = 2010
SYSZ_INS_VLRLR = 2011
SYSZ_INS_VLVG = 2012
SYSZ_INS_VLVGB = 2013
SYSZ_INS_VLVGF = 2014
SYSZ_INS_VLVGG = 2015
SYSZ_INS_VLVGH = 2016
SYSZ_INS_VLVGP = 2017
SYSZ_INS_VMAE = 2018
SYSZ_INS_VMAEB = 2019
SYSZ_INS_VMAEF = 2020
SYSZ_INS_VMAEH = 2021
SYSZ_INS_VMAH = 2022
SYSZ_INS_VMAHB = 2023
SYSZ_INS_VMAHF = 2024
SYSZ_INS_VMAHH = 2025
SYSZ_INS_VMAL = 2026
SYSZ_INS_VMALB = 2027
SYSZ_INS_VMALE = 2028
SYSZ_INS_VMALEB = 2029
SYSZ_INS_VMALEF = 2030
SYSZ_INS_VMALEH = 2031
SYSZ_INS_VMALF = 2032
SYSZ_INS_VMALH = 2033
SYSZ_INS_VMALHB = 2034
SYSZ_INS_VMALHF = 2035
SYSZ_INS_VMALHH = 2036
SYSZ_INS_VMALHW = 2037
SYSZ_INS_VMALO = 2038
SYSZ_INS_VMALOB = 2039
SYSZ_INS_VMALOF = 2040
SYSZ_INS_VMALOH = 2041
SYSZ_INS_VMAO = 2042
SYSZ_INS_VMAOB = 2043
SYSZ_INS_VMAOF = 2044
SYSZ_INS_VMAOH = 2045
SYSZ_INS_VME = 2046
SYSZ_INS_VMEB = 2047
SYSZ_INS_VMEF = 2048
SYSZ_INS_VMEH = 2049
SYSZ_INS_VMH = 2050
SYSZ_INS_VMHB = 2051
SYSZ_INS_VMHF = 2052
SYSZ_INS_VMHH = 2053
SYSZ_INS_VML = 2054
SYSZ_INS_VMLB = 2055
SYSZ_INS_VMLE = 2056
SYSZ_INS_VMLEB = 2057
SYSZ_INS_VMLEF = 2058
SYSZ_INS_VMLEH = 2059
SYSZ_INS_VMLF = 2060
SYSZ_INS_VMLH = 2061
SYSZ_INS_VMLHB = 2062
SYSZ_INS_VMLHF = 2063
SYSZ_INS_VMLHH = 2064
SYSZ_INS_VMLHW = 2065
SYSZ_INS_VMLO = 2066
SYSZ_INS_VMLOB = 2067
SYSZ_INS_VMLOF = 2068
SYSZ_INS_VMLOH = 2069
SYSZ_INS_VMN = 2070
SYSZ_INS_VMNB = 2071
SYSZ_INS_VMNF = 2072
SYSZ_INS_VMNG = 2073
SYSZ_INS_VMNH = 2074
SYSZ_INS_VMNL = 2075
SYSZ_INS_VMNLB = 2076
SYSZ_INS_VMNLF = 2077
SYSZ_INS_VMNLG = 2078
SYSZ_INS_VMNLH = 2079
SYSZ_INS_VMO = 2080
SYSZ_INS_VMOB = 2081
SYSZ_INS_VMOF = 2082
SYSZ_INS_VMOH = 2083
SYSZ_INS_VMP = 2084
SYSZ_INS_VMRH = 2085
SYSZ_INS_VMRHB = 2086
SYSZ_INS_VMRHF = 2087
SYSZ_INS_VMRHG = 2088
SYSZ_INS_VMRHH = 2089
SYSZ_INS_VMRL = 2090
SYSZ_INS_VMRLB = 2091
SYSZ_INS_VMRLF = 2092
SYSZ_INS_VMRLG = 2093
SYSZ_INS_VMRLH = 2094
SYSZ_INS_VMSL = 2095
SYSZ_INS_VMSLG = 2096
SYSZ_INS_VMSP = 2097
SYSZ_INS_VMX = 2098
SYSZ_INS_VMXB = 2099
SYSZ_INS_VMXF = 2100
SYSZ_INS_VMXG = 2101
SYSZ_INS_VMXH = 2102
SYSZ_INS_VMXL = 2103
SYSZ_INS_VMXLB = 2104
SYSZ_INS_VMXLF = 2105
SYSZ_INS_VMXLG = 2106
SYSZ_INS_VMXLH = 2107
SYSZ_INS_VN = 2108
SYSZ_INS_VNC = 2109
SYSZ_INS_VNN = 2110
SYSZ_INS_VNO = 2111
SYSZ_INS_VNX = 2112
SYSZ_INS_VO = 2113
SYSZ_INS_VOC = 2114
SYSZ_INS_VONE = 2115
SYSZ_INS_VPDI = 2116
SYSZ_INS_VPERM = 2117
SYSZ_INS_VPK = 2118
SYSZ_INS_VPKF = 2119
SYSZ_INS_VPKG = 2120
SYSZ_INS_VPKH = 2121
SYSZ_INS_VPKLS = 2122
SYSZ_INS_VPKLSF = 2123
SYSZ_INS_VPKLSFS = 2124
SYSZ_INS_VPKLSG = 2125
SYSZ_INS_VPKLSGS = 2126
SYSZ_INS_VPKLSH = 2127
SYSZ_INS_VPKLSHS = 2128
SYSZ_INS_VPKS = 2129
SYSZ_INS_VPKSF = 2130
SYSZ_INS_VPKSFS = 2131
SYSZ_INS_VPKSG = 2132
SYSZ_INS_VPKSGS = 2133
SYSZ_INS_VPKSH = 2134
SYSZ_INS_VPKSHS = 2135
SYSZ_INS_VPKZ = 2136
SYSZ_INS_VPOPCT = 2137
SYSZ_INS_VPOPCTB = 2138
SYSZ_INS_VPOPCTF = 2139
SYSZ_INS_VPOPCTG = 2140
SYSZ_INS_VPOPCTH = 2141
SYSZ_INS_VPSOP = 2142
SYSZ_INS_VREP = 2143
SYSZ_INS_VREPB = 2144
SYSZ_INS_VREPF = 2145
SYSZ_INS_VREPG = 2146
SYSZ_INS_VREPH = 2147
SYSZ_INS_VREPI = 2148
SYSZ_INS_VREPIB = 2149
SYSZ_INS_VREPIF = 2150
SYSZ_INS_VREPIG = 2151
SYSZ_INS_VREPIH = 2152
SYSZ_INS_VRP = 2153
SYSZ_INS_VS = 2154
SYSZ_INS_VSB = 2155
SYSZ_INS_VSBCBI = 2156
SYSZ_INS_VSBCBIQ = 2157
SYSZ_INS_VSBI = 2158
SYSZ_INS_VSBIQ = 2159
SYSZ_INS_VSCBI = 2160
SYSZ_INS_VSCBIB = 2161
SYSZ_INS_VSCBIF = 2162
SYSZ_INS_VSCBIG = 2163
SYSZ_INS_VSCBIH = 2164
SYSZ_INS_VSCBIQ = 2165
SYSZ_INS_VSCEF = 2166
SYSZ_INS_VSCEG = 2167
SYSZ_INS_VSDP = 2168
SYSZ_INS_VSEG = 2169
SYSZ_INS_VSEGB = 2170
SYSZ_INS_VSEGF = 2171
SYSZ_INS_VSEGH = 2172
SYSZ_INS_VSEL = 2173
SYSZ_INS_VSF = 2174
SYSZ_INS_VSG = 2175
SYSZ_INS_VSH = 2176
SYSZ_INS_VSL = 2177
SYSZ_INS_VSLB = 2178
SYSZ_INS_VSLDB = 2179
SYSZ_INS_VSP = 2180
SYSZ_INS_VSQ = 2181
SYSZ_INS_VSRA = 2182
SYSZ_INS_VSRAB = 2183
SYSZ_INS_VSRL = 2184
SYSZ_INS_VSRLB = 2185
SYSZ_INS_VSRP = 2186
SYSZ_INS_VST = 2187
SYSZ_INS_VSTEB = 2188
SYSZ_INS_VSTEF = 2189
SYSZ_INS_VSTEG = 2190
SYSZ_INS_VSTEH = 2191
SYSZ_INS_VSTL = 2192
SYSZ_INS_VSTM = 2193
SYSZ_INS_VSTRC = 2194
SYSZ_INS_VSTRCB = 2195
SYSZ_INS_VSTRCBS = 2196
SYSZ_INS_VSTRCF = 2197
SYSZ_INS_VSTRCFS = 2198
SYSZ_INS_VSTRCH = 2199
SYSZ_INS_VSTRCHS = 2200
SYSZ_INS_VSTRCZB = 2201
SYSZ_INS_VSTRCZBS = 2202
SYSZ_INS_VSTRCZF = 2203
SYSZ_INS_VSTRCZFS = 2204
SYSZ_INS_VSTRCZH = 2205
SYSZ_INS_VSTRCZHS = 2206
SYSZ_INS_VSTRL = 2207
SYSZ_INS_VSTRLR = 2208
SYSZ_INS_VSUM = 2209
SYSZ_INS_VSUMB = 2210
SYSZ_INS_VSUMG = 2211
SYSZ_INS_VSUMGF = 2212
SYSZ_INS_VSUMGH = 2213
SYSZ_INS_VSUMH = 2214
SYSZ_INS_VSUMQ = 2215
SYSZ_INS_VSUMQF = 2216
SYSZ_INS_VSUMQG = 2217
SYSZ_INS_VTM = 2218
SYSZ_INS_VTP = 2219
SYSZ_INS_VUPH = 2220
SYSZ_INS_VUPHB = 2221
SYSZ_INS_VUPHF = 2222
SYSZ_INS_VUPHH = 2223
SYSZ_INS_VUPKZ = 2224
SYSZ_INS_VUPL = 2225
SYSZ_INS_VUPLB = 2226
SYSZ_INS_VUPLF = 2227
SYSZ_INS_VUPLH = 2228
SYSZ_INS_VUPLHB = 2229
SYSZ_INS_VUPLHF = 2230
SYSZ_INS_VUPLHH = 2231
SYSZ_INS_VUPLHW = 2232
SYSZ_INS_VUPLL = 2233
SYSZ_INS_VUPLLB = 2234
SYSZ_INS_VUPLLF = 2235
SYSZ_INS_VUPLLH = 2236
SYSZ_INS_VX = 2237
SYSZ_INS_VZERO = 2238
SYSZ_INS_WCDGB = 2239
SYSZ_INS_WCDLGB = 2240
SYSZ_INS_WCGDB = 2241
SYSZ_INS_WCLGDB = 2242
SYSZ_INS_WFADB = 2243
SYSZ_INS_WFASB = 2244
SYSZ_INS_WFAXB = 2245
SYSZ_INS_WFC = 2246
SYSZ_INS_WFCDB = 2247
SYSZ_INS_WFCEDB = 2248
SYSZ_INS_WFCEDBS = 2249
SYSZ_INS_WFCESB = 2250
SYSZ_INS_WFCESBS = 2251
SYSZ_INS_WFCEXB = 2252
SYSZ_INS_WFCEXBS = 2253
SYSZ_INS_WFCHDB = 2254
SYSZ_INS_WFCHDBS = 2255
SYSZ_INS_WFCHEDB = 2256
SYSZ_INS_WFCHEDBS = 2257
SYSZ_INS_WFCHESB = 2258
SYSZ_INS_WFCHESBS = 2259
SYSZ_INS_WFCHEXB = 2260
SYSZ_INS_WFCHEXBS = 2261
SYSZ_INS_WFCHSB = 2262
SYSZ_INS_WFCHSBS = 2263
SYSZ_INS_WFCHXB = 2264
SYSZ_INS_WFCHXBS = 2265
SYSZ_INS_WFCSB = 2266
SYSZ_INS_WFCXB = 2267
SYSZ_INS_WFDDB = 2268
SYSZ_INS_WFDSB = 2269
SYSZ_INS_WFDXB = 2270
SYSZ_INS_WFIDB = 2271
SYSZ_INS_WFISB = 2272
SYSZ_INS_WFIXB = 2273
SYSZ_INS_WFK = 2274
SYSZ_INS_WFKDB = 2275
SYSZ_INS_WFKEDB = 2276
SYSZ_INS_WFKEDBS = 2277
SYSZ_INS_WFKESB = 2278
SYSZ_INS_WFKESBS = 2279
SYSZ_INS_WFKEXB = 2280
SYSZ_INS_WFKEXBS = 2281
SYSZ_INS_WFKHDB = 2282
SYSZ_INS_WFKHDBS = 2283
SYSZ_INS_WFKHEDB = 2284
SYSZ_INS_WFKHEDBS = 2285
SYSZ_INS_WFKHESB = 2286
SYSZ_INS_WFKHESBS = 2287
SYSZ_INS_WFKHEXB = 2288
SYSZ_INS_WFKHEXBS = 2289
SYSZ_INS_WFKHSB = 2290
SYSZ_INS_WFKHSBS = 2291
SYSZ_INS_WFKHXB = 2292
SYSZ_INS_WFKHXBS = 2293
SYSZ_INS_WFKSB = 2294
SYSZ_INS_WFKXB = 2295
SYSZ_INS_WFLCDB = 2296
SYSZ_INS_WFLCSB = 2297
SYSZ_INS_WFLCXB = 2298
SYSZ_INS_WFLLD = 2299
SYSZ_INS_WFLLS = 2300
SYSZ_INS_WFLNDB = 2301
SYSZ_INS_WFLNSB = 2302
SYSZ_INS_WFLNXB = 2303
SYSZ_INS_WFLPDB = 2304
SYSZ_INS_WFLPSB = 2305
SYSZ_INS_WFLPXB = 2306
SYSZ_INS_WFLRD = 2307
SYSZ_INS_WFLRX = 2308
SYSZ_INS_WFMADB = 2309
SYSZ_INS_WFMASB = 2310
SYSZ_INS_WFMAXB = 2311
SYSZ_INS_WFMAXDB = 2312
SYSZ_INS_WFMAXSB = 2313
SYSZ_INS_WFMAXXB = 2314
SYSZ_INS_WFMDB = 2315
SYSZ_INS_WFMINDB = 2316
SYSZ_INS_WFMINSB = 2317
SYSZ_INS_WFMINXB = 2318
SYSZ_INS_WFMSB = 2319
SYSZ_INS_WFMSDB = 2320
SYSZ_INS_WFMSSB = 2321
SYSZ_INS_WFMSXB = 2322
SYSZ_INS_WFMXB = 2323
SYSZ_INS_WFNMADB = 2324
SYSZ_INS_WFNMASB = 2325
SYSZ_INS_WFNMAXB = 2326
SYSZ_INS_WFNMSDB = 2327
SYSZ_INS_WFNMSSB = 2328
SYSZ_INS_WFNMSXB = 2329
SYSZ_INS_WFPSODB = 2330
SYSZ_INS_WFPSOSB = 2331
SYSZ_INS_WFPSOXB = 2332
SYSZ_INS_WFSDB = 2333
SYSZ_INS_WFSQDB = 2334
SYSZ_INS_WFSQSB = 2335
SYSZ_INS_WFSQXB = 2336
SYSZ_INS_WFSSB = 2337
SYSZ_INS_WFSXB = 2338
SYSZ_INS_WFTCIDB = 2339
SYSZ_INS_WFTCISB = 2340
SYSZ_INS_WFTCIXB = 2341
SYSZ_INS_WLDEB = 2342
SYSZ_INS_WLEDB = 2343
SYSZ_INS_XSCH = 2344
SYSZ_INS_ZAP = 2345
SYSZ_INS_ENDING = 2346
SYSZ_GRP_INVALID = 0
SYSZ_GRP_JUMP = 1
SYSZ_GRP_DISTINCTOPS = 128
SYSZ_GRP_FPEXTENSION = 129
SYSZ_GRP_HIGHWORD = 130
SYSZ_GRP_INTERLOCKEDACCESS1 = 131
SYSZ_GRP_LOADSTOREONCOND = 132
SYSZ_GRP_DFPPACKEDCONVERSION = 133
SYSZ_GRP_DFPZONEDCONVERSION = 134
SYSZ_GRP_ENHANCEDDAT2 = 135
SYSZ_GRP_EXECUTIONHINT = 136
SYSZ_GRP_GUARDEDSTORAGE = 137
SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE = 138
SYSZ_GRP_LOADANDTRAP = 139
SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE = 140
SYSZ_GRP_LOADSTOREONCOND2 = 141
SYSZ_GRP_MESSAGESECURITYASSIST3 = 142
SYSZ_GRP_MESSAGESECURITYASSIST4 = 143
SYSZ_GRP_MESSAGESECURITYASSIST5 = 144
SYSZ_GRP_MESSAGESECURITYASSIST7 = 145
SYSZ_GRP_MESSAGESECURITYASSIST8 = 146
SYSZ_GRP_MISCELLANEOUSEXTENSIONS = 147
SYSZ_GRP_MISCELLANEOUSEXTENSIONS2 = 148
SYSZ_GRP_NOVECTOR = 149
SYSZ_GRP_POPULATIONCOUNT = 150
SYSZ_GRP_PROCESSORASSIST = 151
SYSZ_GRP_RESETREFERENCEBITSMULTIPLE = 152
SYSZ_GRP_TRANSACTIONALEXECUTION = 153
SYSZ_GRP_VECTOR = 154
SYSZ_GRP_VECTORENHANCEMENTS1 = 155
SYSZ_GRP_VECTORPACKEDDECIMAL = 156
SYSZ_GRP_ENDING = 157
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/sysz_const.py
|
# Capstone Python bindings
# BPF by david942j <david942j@gmail.com>, 2019
import ctypes
from . import copy_ctypes_list
from .bpf_const import *
class BPFOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('disp', ctypes.c_int32),
)
class BPFOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint8),
('imm', ctypes.c_uint64),
('off', ctypes.c_uint32),
('mem', BPFOpMem),
('mmem', ctypes.c_uint32),
('msh', ctypes.c_uint32),
('ext', ctypes.c_uint32),
)
class BPFOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', BPFOpValue),
('access', ctypes.c_uint8),
)
@property
def reg(self):
return self.value.reg
@property
def imm(self):
return self.value.imm
@property
def off(self):
return self.value.off
@property
def mem(self):
return self.value.mem
@property
def mmem(self):
return self.value.mmem
@property
def msh(self):
return self.value.msh
@property
def ext(self):
return self.value.ext
class CsBPF(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', BPFOp * 4),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/bpf.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .evm_const import *
# define the API
class CsEvm(ctypes.Structure):
_fields_ = (
('pop', ctypes.c_byte),
('push', ctypes.c_byte),
('fee', ctypes.c_uint),
)
def get_arch_info(a):
return (a.pop, a.push, a.fee)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/evm.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
MIPS_OP_INVALID = 0
MIPS_OP_REG = 1
MIPS_OP_IMM = 2
MIPS_OP_MEM = 3
MIPS_REG_INVALID = 0
MIPS_REG_PC = 1
MIPS_REG_0 = 2
MIPS_REG_1 = 3
MIPS_REG_2 = 4
MIPS_REG_3 = 5
MIPS_REG_4 = 6
MIPS_REG_5 = 7
MIPS_REG_6 = 8
MIPS_REG_7 = 9
MIPS_REG_8 = 10
MIPS_REG_9 = 11
MIPS_REG_10 = 12
MIPS_REG_11 = 13
MIPS_REG_12 = 14
MIPS_REG_13 = 15
MIPS_REG_14 = 16
MIPS_REG_15 = 17
MIPS_REG_16 = 18
MIPS_REG_17 = 19
MIPS_REG_18 = 20
MIPS_REG_19 = 21
MIPS_REG_20 = 22
MIPS_REG_21 = 23
MIPS_REG_22 = 24
MIPS_REG_23 = 25
MIPS_REG_24 = 26
MIPS_REG_25 = 27
MIPS_REG_26 = 28
MIPS_REG_27 = 29
MIPS_REG_28 = 30
MIPS_REG_29 = 31
MIPS_REG_30 = 32
MIPS_REG_31 = 33
MIPS_REG_DSPCCOND = 34
MIPS_REG_DSPCARRY = 35
MIPS_REG_DSPEFI = 36
MIPS_REG_DSPOUTFLAG = 37
MIPS_REG_DSPOUTFLAG16_19 = 38
MIPS_REG_DSPOUTFLAG20 = 39
MIPS_REG_DSPOUTFLAG21 = 40
MIPS_REG_DSPOUTFLAG22 = 41
MIPS_REG_DSPOUTFLAG23 = 42
MIPS_REG_DSPPOS = 43
MIPS_REG_DSPSCOUNT = 44
MIPS_REG_AC0 = 45
MIPS_REG_AC1 = 46
MIPS_REG_AC2 = 47
MIPS_REG_AC3 = 48
MIPS_REG_CC0 = 49
MIPS_REG_CC1 = 50
MIPS_REG_CC2 = 51
MIPS_REG_CC3 = 52
MIPS_REG_CC4 = 53
MIPS_REG_CC5 = 54
MIPS_REG_CC6 = 55
MIPS_REG_CC7 = 56
MIPS_REG_F0 = 57
MIPS_REG_F1 = 58
MIPS_REG_F2 = 59
MIPS_REG_F3 = 60
MIPS_REG_F4 = 61
MIPS_REG_F5 = 62
MIPS_REG_F6 = 63
MIPS_REG_F7 = 64
MIPS_REG_F8 = 65
MIPS_REG_F9 = 66
MIPS_REG_F10 = 67
MIPS_REG_F11 = 68
MIPS_REG_F12 = 69
MIPS_REG_F13 = 70
MIPS_REG_F14 = 71
MIPS_REG_F15 = 72
MIPS_REG_F16 = 73
MIPS_REG_F17 = 74
MIPS_REG_F18 = 75
MIPS_REG_F19 = 76
MIPS_REG_F20 = 77
MIPS_REG_F21 = 78
MIPS_REG_F22 = 79
MIPS_REG_F23 = 80
MIPS_REG_F24 = 81
MIPS_REG_F25 = 82
MIPS_REG_F26 = 83
MIPS_REG_F27 = 84
MIPS_REG_F28 = 85
MIPS_REG_F29 = 86
MIPS_REG_F30 = 87
MIPS_REG_F31 = 88
MIPS_REG_FCC0 = 89
MIPS_REG_FCC1 = 90
MIPS_REG_FCC2 = 91
MIPS_REG_FCC3 = 92
MIPS_REG_FCC4 = 93
MIPS_REG_FCC5 = 94
MIPS_REG_FCC6 = 95
MIPS_REG_FCC7 = 96
MIPS_REG_W0 = 97
MIPS_REG_W1 = 98
MIPS_REG_W2 = 99
MIPS_REG_W3 = 100
MIPS_REG_W4 = 101
MIPS_REG_W5 = 102
MIPS_REG_W6 = 103
MIPS_REG_W7 = 104
MIPS_REG_W8 = 105
MIPS_REG_W9 = 106
MIPS_REG_W10 = 107
MIPS_REG_W11 = 108
MIPS_REG_W12 = 109
MIPS_REG_W13 = 110
MIPS_REG_W14 = 111
MIPS_REG_W15 = 112
MIPS_REG_W16 = 113
MIPS_REG_W17 = 114
MIPS_REG_W18 = 115
MIPS_REG_W19 = 116
MIPS_REG_W20 = 117
MIPS_REG_W21 = 118
MIPS_REG_W22 = 119
MIPS_REG_W23 = 120
MIPS_REG_W24 = 121
MIPS_REG_W25 = 122
MIPS_REG_W26 = 123
MIPS_REG_W27 = 124
MIPS_REG_W28 = 125
MIPS_REG_W29 = 126
MIPS_REG_W30 = 127
MIPS_REG_W31 = 128
MIPS_REG_HI = 129
MIPS_REG_LO = 130
MIPS_REG_P0 = 131
MIPS_REG_P1 = 132
MIPS_REG_P2 = 133
MIPS_REG_MPL0 = 134
MIPS_REG_MPL1 = 135
MIPS_REG_MPL2 = 136
MIPS_REG_ENDING = 137
MIPS_REG_ZERO = MIPS_REG_0
MIPS_REG_AT = MIPS_REG_1
MIPS_REG_V0 = MIPS_REG_2
MIPS_REG_V1 = MIPS_REG_3
MIPS_REG_A0 = MIPS_REG_4
MIPS_REG_A1 = MIPS_REG_5
MIPS_REG_A2 = MIPS_REG_6
MIPS_REG_A3 = MIPS_REG_7
MIPS_REG_T0 = MIPS_REG_8
MIPS_REG_T1 = MIPS_REG_9
MIPS_REG_T2 = MIPS_REG_10
MIPS_REG_T3 = MIPS_REG_11
MIPS_REG_T4 = MIPS_REG_12
MIPS_REG_T5 = MIPS_REG_13
MIPS_REG_T6 = MIPS_REG_14
MIPS_REG_T7 = MIPS_REG_15
MIPS_REG_S0 = MIPS_REG_16
MIPS_REG_S1 = MIPS_REG_17
MIPS_REG_S2 = MIPS_REG_18
MIPS_REG_S3 = MIPS_REG_19
MIPS_REG_S4 = MIPS_REG_20
MIPS_REG_S5 = MIPS_REG_21
MIPS_REG_S6 = MIPS_REG_22
MIPS_REG_S7 = MIPS_REG_23
MIPS_REG_T8 = MIPS_REG_24
MIPS_REG_T9 = MIPS_REG_25
MIPS_REG_K0 = MIPS_REG_26
MIPS_REG_K1 = MIPS_REG_27
MIPS_REG_GP = MIPS_REG_28
MIPS_REG_SP = MIPS_REG_29
MIPS_REG_FP = MIPS_REG_30
MIPS_REG_S8 = MIPS_REG_30
MIPS_REG_RA = MIPS_REG_31
MIPS_REG_HI0 = MIPS_REG_AC0
MIPS_REG_HI1 = MIPS_REG_AC1
MIPS_REG_HI2 = MIPS_REG_AC2
MIPS_REG_HI3 = MIPS_REG_AC3
MIPS_REG_LO0 = MIPS_REG_HI0
MIPS_REG_LO1 = MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3
MIPS_INS_INVALID = 0
MIPS_INS_ABSQ_S = 1
MIPS_INS_ADD = 2
MIPS_INS_ADDIUPC = 3
MIPS_INS_ADDIUR1SP = 4
MIPS_INS_ADDIUR2 = 5
MIPS_INS_ADDIUS5 = 6
MIPS_INS_ADDIUSP = 7
MIPS_INS_ADDQH = 8
MIPS_INS_ADDQH_R = 9
MIPS_INS_ADDQ = 10
MIPS_INS_ADDQ_S = 11
MIPS_INS_ADDSC = 12
MIPS_INS_ADDS_A = 13
MIPS_INS_ADDS_S = 14
MIPS_INS_ADDS_U = 15
MIPS_INS_ADDU16 = 16
MIPS_INS_ADDUH = 17
MIPS_INS_ADDUH_R = 18
MIPS_INS_ADDU = 19
MIPS_INS_ADDU_S = 20
MIPS_INS_ADDVI = 21
MIPS_INS_ADDV = 22
MIPS_INS_ADDWC = 23
MIPS_INS_ADD_A = 24
MIPS_INS_ADDI = 25
MIPS_INS_ADDIU = 26
MIPS_INS_ALIGN = 27
MIPS_INS_ALUIPC = 28
MIPS_INS_AND = 29
MIPS_INS_AND16 = 30
MIPS_INS_ANDI16 = 31
MIPS_INS_ANDI = 32
MIPS_INS_APPEND = 33
MIPS_INS_ASUB_S = 34
MIPS_INS_ASUB_U = 35
MIPS_INS_AUI = 36
MIPS_INS_AUIPC = 37
MIPS_INS_AVER_S = 38
MIPS_INS_AVER_U = 39
MIPS_INS_AVE_S = 40
MIPS_INS_AVE_U = 41
MIPS_INS_B16 = 42
MIPS_INS_BADDU = 43
MIPS_INS_BAL = 44
MIPS_INS_BALC = 45
MIPS_INS_BALIGN = 46
MIPS_INS_BBIT0 = 47
MIPS_INS_BBIT032 = 48
MIPS_INS_BBIT1 = 49
MIPS_INS_BBIT132 = 50
MIPS_INS_BC = 51
MIPS_INS_BC0F = 52
MIPS_INS_BC0FL = 53
MIPS_INS_BC0T = 54
MIPS_INS_BC0TL = 55
MIPS_INS_BC1EQZ = 56
MIPS_INS_BC1F = 57
MIPS_INS_BC1FL = 58
MIPS_INS_BC1NEZ = 59
MIPS_INS_BC1T = 60
MIPS_INS_BC1TL = 61
MIPS_INS_BC2EQZ = 62
MIPS_INS_BC2F = 63
MIPS_INS_BC2FL = 64
MIPS_INS_BC2NEZ = 65
MIPS_INS_BC2T = 66
MIPS_INS_BC2TL = 67
MIPS_INS_BC3F = 68
MIPS_INS_BC3FL = 69
MIPS_INS_BC3T = 70
MIPS_INS_BC3TL = 71
MIPS_INS_BCLRI = 72
MIPS_INS_BCLR = 73
MIPS_INS_BEQ = 74
MIPS_INS_BEQC = 75
MIPS_INS_BEQL = 76
MIPS_INS_BEQZ16 = 77
MIPS_INS_BEQZALC = 78
MIPS_INS_BEQZC = 79
MIPS_INS_BGEC = 80
MIPS_INS_BGEUC = 81
MIPS_INS_BGEZ = 82
MIPS_INS_BGEZAL = 83
MIPS_INS_BGEZALC = 84
MIPS_INS_BGEZALL = 85
MIPS_INS_BGEZALS = 86
MIPS_INS_BGEZC = 87
MIPS_INS_BGEZL = 88
MIPS_INS_BGTZ = 89
MIPS_INS_BGTZALC = 90
MIPS_INS_BGTZC = 91
MIPS_INS_BGTZL = 92
MIPS_INS_BINSLI = 93
MIPS_INS_BINSL = 94
MIPS_INS_BINSRI = 95
MIPS_INS_BINSR = 96
MIPS_INS_BITREV = 97
MIPS_INS_BITSWAP = 98
MIPS_INS_BLEZ = 99
MIPS_INS_BLEZALC = 100
MIPS_INS_BLEZC = 101
MIPS_INS_BLEZL = 102
MIPS_INS_BLTC = 103
MIPS_INS_BLTUC = 104
MIPS_INS_BLTZ = 105
MIPS_INS_BLTZAL = 106
MIPS_INS_BLTZALC = 107
MIPS_INS_BLTZALL = 108
MIPS_INS_BLTZALS = 109
MIPS_INS_BLTZC = 110
MIPS_INS_BLTZL = 111
MIPS_INS_BMNZI = 112
MIPS_INS_BMNZ = 113
MIPS_INS_BMZI = 114
MIPS_INS_BMZ = 115
MIPS_INS_BNE = 116
MIPS_INS_BNEC = 117
MIPS_INS_BNEGI = 118
MIPS_INS_BNEG = 119
MIPS_INS_BNEL = 120
MIPS_INS_BNEZ16 = 121
MIPS_INS_BNEZALC = 122
MIPS_INS_BNEZC = 123
MIPS_INS_BNVC = 124
MIPS_INS_BNZ = 125
MIPS_INS_BOVC = 126
MIPS_INS_BPOSGE32 = 127
MIPS_INS_BREAK = 128
MIPS_INS_BREAK16 = 129
MIPS_INS_BSELI = 130
MIPS_INS_BSEL = 131
MIPS_INS_BSETI = 132
MIPS_INS_BSET = 133
MIPS_INS_BZ = 134
MIPS_INS_BEQZ = 135
MIPS_INS_B = 136
MIPS_INS_BNEZ = 137
MIPS_INS_BTEQZ = 138
MIPS_INS_BTNEZ = 139
MIPS_INS_CACHE = 140
MIPS_INS_CEIL = 141
MIPS_INS_CEQI = 142
MIPS_INS_CEQ = 143
MIPS_INS_CFC1 = 144
MIPS_INS_CFCMSA = 145
MIPS_INS_CINS = 146
MIPS_INS_CINS32 = 147
MIPS_INS_CLASS = 148
MIPS_INS_CLEI_S = 149
MIPS_INS_CLEI_U = 150
MIPS_INS_CLE_S = 151
MIPS_INS_CLE_U = 152
MIPS_INS_CLO = 153
MIPS_INS_CLTI_S = 154
MIPS_INS_CLTI_U = 155
MIPS_INS_CLT_S = 156
MIPS_INS_CLT_U = 157
MIPS_INS_CLZ = 158
MIPS_INS_CMPGDU = 159
MIPS_INS_CMPGU = 160
MIPS_INS_CMPU = 161
MIPS_INS_CMP = 162
MIPS_INS_COPY_S = 163
MIPS_INS_COPY_U = 164
MIPS_INS_CTC1 = 165
MIPS_INS_CTCMSA = 166
MIPS_INS_CVT = 167
MIPS_INS_C = 168
MIPS_INS_CMPI = 169
MIPS_INS_DADD = 170
MIPS_INS_DADDI = 171
MIPS_INS_DADDIU = 172
MIPS_INS_DADDU = 173
MIPS_INS_DAHI = 174
MIPS_INS_DALIGN = 175
MIPS_INS_DATI = 176
MIPS_INS_DAUI = 177
MIPS_INS_DBITSWAP = 178
MIPS_INS_DCLO = 179
MIPS_INS_DCLZ = 180
MIPS_INS_DDIV = 181
MIPS_INS_DDIVU = 182
MIPS_INS_DERET = 183
MIPS_INS_DEXT = 184
MIPS_INS_DEXTM = 185
MIPS_INS_DEXTU = 186
MIPS_INS_DI = 187
MIPS_INS_DINS = 188
MIPS_INS_DINSM = 189
MIPS_INS_DINSU = 190
MIPS_INS_DIV = 191
MIPS_INS_DIVU = 192
MIPS_INS_DIV_S = 193
MIPS_INS_DIV_U = 194
MIPS_INS_DLSA = 195
MIPS_INS_DMFC0 = 196
MIPS_INS_DMFC1 = 197
MIPS_INS_DMFC2 = 198
MIPS_INS_DMOD = 199
MIPS_INS_DMODU = 200
MIPS_INS_DMTC0 = 201
MIPS_INS_DMTC1 = 202
MIPS_INS_DMTC2 = 203
MIPS_INS_DMUH = 204
MIPS_INS_DMUHU = 205
MIPS_INS_DMUL = 206
MIPS_INS_DMULT = 207
MIPS_INS_DMULTU = 208
MIPS_INS_DMULU = 209
MIPS_INS_DOTP_S = 210
MIPS_INS_DOTP_U = 211
MIPS_INS_DPADD_S = 212
MIPS_INS_DPADD_U = 213
MIPS_INS_DPAQX_SA = 214
MIPS_INS_DPAQX_S = 215
MIPS_INS_DPAQ_SA = 216
MIPS_INS_DPAQ_S = 217
MIPS_INS_DPAU = 218
MIPS_INS_DPAX = 219
MIPS_INS_DPA = 220
MIPS_INS_DPOP = 221
MIPS_INS_DPSQX_SA = 222
MIPS_INS_DPSQX_S = 223
MIPS_INS_DPSQ_SA = 224
MIPS_INS_DPSQ_S = 225
MIPS_INS_DPSUB_S = 226
MIPS_INS_DPSUB_U = 227
MIPS_INS_DPSU = 228
MIPS_INS_DPSX = 229
MIPS_INS_DPS = 230
MIPS_INS_DROTR = 231
MIPS_INS_DROTR32 = 232
MIPS_INS_DROTRV = 233
MIPS_INS_DSBH = 234
MIPS_INS_DSHD = 235
MIPS_INS_DSLL = 236
MIPS_INS_DSLL32 = 237
MIPS_INS_DSLLV = 238
MIPS_INS_DSRA = 239
MIPS_INS_DSRA32 = 240
MIPS_INS_DSRAV = 241
MIPS_INS_DSRL = 242
MIPS_INS_DSRL32 = 243
MIPS_INS_DSRLV = 244
MIPS_INS_DSUB = 245
MIPS_INS_DSUBU = 246
MIPS_INS_EHB = 247
MIPS_INS_EI = 248
MIPS_INS_ERET = 249
MIPS_INS_EXT = 250
MIPS_INS_EXTP = 251
MIPS_INS_EXTPDP = 252
MIPS_INS_EXTPDPV = 253
MIPS_INS_EXTPV = 254
MIPS_INS_EXTRV_RS = 255
MIPS_INS_EXTRV_R = 256
MIPS_INS_EXTRV_S = 257
MIPS_INS_EXTRV = 258
MIPS_INS_EXTR_RS = 259
MIPS_INS_EXTR_R = 260
MIPS_INS_EXTR_S = 261
MIPS_INS_EXTR = 262
MIPS_INS_EXTS = 263
MIPS_INS_EXTS32 = 264
MIPS_INS_ABS = 265
MIPS_INS_FADD = 266
MIPS_INS_FCAF = 267
MIPS_INS_FCEQ = 268
MIPS_INS_FCLASS = 269
MIPS_INS_FCLE = 270
MIPS_INS_FCLT = 271
MIPS_INS_FCNE = 272
MIPS_INS_FCOR = 273
MIPS_INS_FCUEQ = 274
MIPS_INS_FCULE = 275
MIPS_INS_FCULT = 276
MIPS_INS_FCUNE = 277
MIPS_INS_FCUN = 278
MIPS_INS_FDIV = 279
MIPS_INS_FEXDO = 280
MIPS_INS_FEXP2 = 281
MIPS_INS_FEXUPL = 282
MIPS_INS_FEXUPR = 283
MIPS_INS_FFINT_S = 284
MIPS_INS_FFINT_U = 285
MIPS_INS_FFQL = 286
MIPS_INS_FFQR = 287
MIPS_INS_FILL = 288
MIPS_INS_FLOG2 = 289
MIPS_INS_FLOOR = 290
MIPS_INS_FMADD = 291
MIPS_INS_FMAX_A = 292
MIPS_INS_FMAX = 293
MIPS_INS_FMIN_A = 294
MIPS_INS_FMIN = 295
MIPS_INS_MOV = 296
MIPS_INS_FMSUB = 297
MIPS_INS_FMUL = 298
MIPS_INS_MUL = 299
MIPS_INS_NEG = 300
MIPS_INS_FRCP = 301
MIPS_INS_FRINT = 302
MIPS_INS_FRSQRT = 303
MIPS_INS_FSAF = 304
MIPS_INS_FSEQ = 305
MIPS_INS_FSLE = 306
MIPS_INS_FSLT = 307
MIPS_INS_FSNE = 308
MIPS_INS_FSOR = 309
MIPS_INS_FSQRT = 310
MIPS_INS_SQRT = 311
MIPS_INS_FSUB = 312
MIPS_INS_SUB = 313
MIPS_INS_FSUEQ = 314
MIPS_INS_FSULE = 315
MIPS_INS_FSULT = 316
MIPS_INS_FSUNE = 317
MIPS_INS_FSUN = 318
MIPS_INS_FTINT_S = 319
MIPS_INS_FTINT_U = 320
MIPS_INS_FTQ = 321
MIPS_INS_FTRUNC_S = 322
MIPS_INS_FTRUNC_U = 323
MIPS_INS_HADD_S = 324
MIPS_INS_HADD_U = 325
MIPS_INS_HSUB_S = 326
MIPS_INS_HSUB_U = 327
MIPS_INS_ILVEV = 328
MIPS_INS_ILVL = 329
MIPS_INS_ILVOD = 330
MIPS_INS_ILVR = 331
MIPS_INS_INS = 332
MIPS_INS_INSERT = 333
MIPS_INS_INSV = 334
MIPS_INS_INSVE = 335
MIPS_INS_J = 336
MIPS_INS_JAL = 337
MIPS_INS_JALR = 338
MIPS_INS_JALRS16 = 339
MIPS_INS_JALRS = 340
MIPS_INS_JALS = 341
MIPS_INS_JALX = 342
MIPS_INS_JIALC = 343
MIPS_INS_JIC = 344
MIPS_INS_JR = 345
MIPS_INS_JR16 = 346
MIPS_INS_JRADDIUSP = 347
MIPS_INS_JRC = 348
MIPS_INS_JALRC = 349
MIPS_INS_LB = 350
MIPS_INS_LBU16 = 351
MIPS_INS_LBUX = 352
MIPS_INS_LBU = 353
MIPS_INS_LD = 354
MIPS_INS_LDC1 = 355
MIPS_INS_LDC2 = 356
MIPS_INS_LDC3 = 357
MIPS_INS_LDI = 358
MIPS_INS_LDL = 359
MIPS_INS_LDPC = 360
MIPS_INS_LDR = 361
MIPS_INS_LDXC1 = 362
MIPS_INS_LH = 363
MIPS_INS_LHU16 = 364
MIPS_INS_LHX = 365
MIPS_INS_LHU = 366
MIPS_INS_LI16 = 367
MIPS_INS_LL = 368
MIPS_INS_LLD = 369
MIPS_INS_LSA = 370
MIPS_INS_LUXC1 = 371
MIPS_INS_LUI = 372
MIPS_INS_LW = 373
MIPS_INS_LW16 = 374
MIPS_INS_LWC1 = 375
MIPS_INS_LWC2 = 376
MIPS_INS_LWC3 = 377
MIPS_INS_LWL = 378
MIPS_INS_LWM16 = 379
MIPS_INS_LWM32 = 380
MIPS_INS_LWPC = 381
MIPS_INS_LWP = 382
MIPS_INS_LWR = 383
MIPS_INS_LWUPC = 384
MIPS_INS_LWU = 385
MIPS_INS_LWX = 386
MIPS_INS_LWXC1 = 387
MIPS_INS_LWXS = 388
MIPS_INS_LI = 389
MIPS_INS_MADD = 390
MIPS_INS_MADDF = 391
MIPS_INS_MADDR_Q = 392
MIPS_INS_MADDU = 393
MIPS_INS_MADDV = 394
MIPS_INS_MADD_Q = 395
MIPS_INS_MAQ_SA = 396
MIPS_INS_MAQ_S = 397
MIPS_INS_MAXA = 398
MIPS_INS_MAXI_S = 399
MIPS_INS_MAXI_U = 400
MIPS_INS_MAX_A = 401
MIPS_INS_MAX = 402
MIPS_INS_MAX_S = 403
MIPS_INS_MAX_U = 404
MIPS_INS_MFC0 = 405
MIPS_INS_MFC1 = 406
MIPS_INS_MFC2 = 407
MIPS_INS_MFHC1 = 408
MIPS_INS_MFHI = 409
MIPS_INS_MFLO = 410
MIPS_INS_MINA = 411
MIPS_INS_MINI_S = 412
MIPS_INS_MINI_U = 413
MIPS_INS_MIN_A = 414
MIPS_INS_MIN = 415
MIPS_INS_MIN_S = 416
MIPS_INS_MIN_U = 417
MIPS_INS_MOD = 418
MIPS_INS_MODSUB = 419
MIPS_INS_MODU = 420
MIPS_INS_MOD_S = 421
MIPS_INS_MOD_U = 422
MIPS_INS_MOVE = 423
MIPS_INS_MOVEP = 424
MIPS_INS_MOVF = 425
MIPS_INS_MOVN = 426
MIPS_INS_MOVT = 427
MIPS_INS_MOVZ = 428
MIPS_INS_MSUB = 429
MIPS_INS_MSUBF = 430
MIPS_INS_MSUBR_Q = 431
MIPS_INS_MSUBU = 432
MIPS_INS_MSUBV = 433
MIPS_INS_MSUB_Q = 434
MIPS_INS_MTC0 = 435
MIPS_INS_MTC1 = 436
MIPS_INS_MTC2 = 437
MIPS_INS_MTHC1 = 438
MIPS_INS_MTHI = 439
MIPS_INS_MTHLIP = 440
MIPS_INS_MTLO = 441
MIPS_INS_MTM0 = 442
MIPS_INS_MTM1 = 443
MIPS_INS_MTM2 = 444
MIPS_INS_MTP0 = 445
MIPS_INS_MTP1 = 446
MIPS_INS_MTP2 = 447
MIPS_INS_MUH = 448
MIPS_INS_MUHU = 449
MIPS_INS_MULEQ_S = 450
MIPS_INS_MULEU_S = 451
MIPS_INS_MULQ_RS = 452
MIPS_INS_MULQ_S = 453
MIPS_INS_MULR_Q = 454
MIPS_INS_MULSAQ_S = 455
MIPS_INS_MULSA = 456
MIPS_INS_MULT = 457
MIPS_INS_MULTU = 458
MIPS_INS_MULU = 459
MIPS_INS_MULV = 460
MIPS_INS_MUL_Q = 461
MIPS_INS_MUL_S = 462
MIPS_INS_NLOC = 463
MIPS_INS_NLZC = 464
MIPS_INS_NMADD = 465
MIPS_INS_NMSUB = 466
MIPS_INS_NOR = 467
MIPS_INS_NORI = 468
MIPS_INS_NOT16 = 469
MIPS_INS_NOT = 470
MIPS_INS_OR = 471
MIPS_INS_OR16 = 472
MIPS_INS_ORI = 473
MIPS_INS_PACKRL = 474
MIPS_INS_PAUSE = 475
MIPS_INS_PCKEV = 476
MIPS_INS_PCKOD = 477
MIPS_INS_PCNT = 478
MIPS_INS_PICK = 479
MIPS_INS_POP = 480
MIPS_INS_PRECEQU = 481
MIPS_INS_PRECEQ = 482
MIPS_INS_PRECEU = 483
MIPS_INS_PRECRQU_S = 484
MIPS_INS_PRECRQ = 485
MIPS_INS_PRECRQ_RS = 486
MIPS_INS_PRECR = 487
MIPS_INS_PRECR_SRA = 488
MIPS_INS_PRECR_SRA_R = 489
MIPS_INS_PREF = 490
MIPS_INS_PREPEND = 491
MIPS_INS_RADDU = 492
MIPS_INS_RDDSP = 493
MIPS_INS_RDHWR = 494
MIPS_INS_REPLV = 495
MIPS_INS_REPL = 496
MIPS_INS_RINT = 497
MIPS_INS_ROTR = 498
MIPS_INS_ROTRV = 499
MIPS_INS_ROUND = 500
MIPS_INS_SAT_S = 501
MIPS_INS_SAT_U = 502
MIPS_INS_SB = 503
MIPS_INS_SB16 = 504
MIPS_INS_SC = 505
MIPS_INS_SCD = 506
MIPS_INS_SD = 507
MIPS_INS_SDBBP = 508
MIPS_INS_SDBBP16 = 509
MIPS_INS_SDC1 = 510
MIPS_INS_SDC2 = 511
MIPS_INS_SDC3 = 512
MIPS_INS_SDL = 513
MIPS_INS_SDR = 514
MIPS_INS_SDXC1 = 515
MIPS_INS_SEB = 516
MIPS_INS_SEH = 517
MIPS_INS_SELEQZ = 518
MIPS_INS_SELNEZ = 519
MIPS_INS_SEL = 520
MIPS_INS_SEQ = 521
MIPS_INS_SEQI = 522
MIPS_INS_SH = 523
MIPS_INS_SH16 = 524
MIPS_INS_SHF = 525
MIPS_INS_SHILO = 526
MIPS_INS_SHILOV = 527
MIPS_INS_SHLLV = 528
MIPS_INS_SHLLV_S = 529
MIPS_INS_SHLL = 530
MIPS_INS_SHLL_S = 531
MIPS_INS_SHRAV = 532
MIPS_INS_SHRAV_R = 533
MIPS_INS_SHRA = 534
MIPS_INS_SHRA_R = 535
MIPS_INS_SHRLV = 536
MIPS_INS_SHRL = 537
MIPS_INS_SLDI = 538
MIPS_INS_SLD = 539
MIPS_INS_SLL = 540
MIPS_INS_SLL16 = 541
MIPS_INS_SLLI = 542
MIPS_INS_SLLV = 543
MIPS_INS_SLT = 544
MIPS_INS_SLTI = 545
MIPS_INS_SLTIU = 546
MIPS_INS_SLTU = 547
MIPS_INS_SNE = 548
MIPS_INS_SNEI = 549
MIPS_INS_SPLATI = 550
MIPS_INS_SPLAT = 551
MIPS_INS_SRA = 552
MIPS_INS_SRAI = 553
MIPS_INS_SRARI = 554
MIPS_INS_SRAR = 555
MIPS_INS_SRAV = 556
MIPS_INS_SRL = 557
MIPS_INS_SRL16 = 558
MIPS_INS_SRLI = 559
MIPS_INS_SRLRI = 560
MIPS_INS_SRLR = 561
MIPS_INS_SRLV = 562
MIPS_INS_SSNOP = 563
MIPS_INS_ST = 564
MIPS_INS_SUBQH = 565
MIPS_INS_SUBQH_R = 566
MIPS_INS_SUBQ = 567
MIPS_INS_SUBQ_S = 568
MIPS_INS_SUBSUS_U = 569
MIPS_INS_SUBSUU_S = 570
MIPS_INS_SUBS_S = 571
MIPS_INS_SUBS_U = 572
MIPS_INS_SUBU16 = 573
MIPS_INS_SUBUH = 574
MIPS_INS_SUBUH_R = 575
MIPS_INS_SUBU = 576
MIPS_INS_SUBU_S = 577
MIPS_INS_SUBVI = 578
MIPS_INS_SUBV = 579
MIPS_INS_SUXC1 = 580
MIPS_INS_SW = 581
MIPS_INS_SW16 = 582
MIPS_INS_SWC1 = 583
MIPS_INS_SWC2 = 584
MIPS_INS_SWC3 = 585
MIPS_INS_SWL = 586
MIPS_INS_SWM16 = 587
MIPS_INS_SWM32 = 588
MIPS_INS_SWP = 589
MIPS_INS_SWR = 590
MIPS_INS_SWXC1 = 591
MIPS_INS_SYNC = 592
MIPS_INS_SYNCI = 593
MIPS_INS_SYSCALL = 594
MIPS_INS_TEQ = 595
MIPS_INS_TEQI = 596
MIPS_INS_TGE = 597
MIPS_INS_TGEI = 598
MIPS_INS_TGEIU = 599
MIPS_INS_TGEU = 600
MIPS_INS_TLBP = 601
MIPS_INS_TLBR = 602
MIPS_INS_TLBWI = 603
MIPS_INS_TLBWR = 604
MIPS_INS_TLT = 605
MIPS_INS_TLTI = 606
MIPS_INS_TLTIU = 607
MIPS_INS_TLTU = 608
MIPS_INS_TNE = 609
MIPS_INS_TNEI = 610
MIPS_INS_TRUNC = 611
MIPS_INS_V3MULU = 612
MIPS_INS_VMM0 = 613
MIPS_INS_VMULU = 614
MIPS_INS_VSHF = 615
MIPS_INS_WAIT = 616
MIPS_INS_WRDSP = 617
MIPS_INS_WSBH = 618
MIPS_INS_XOR = 619
MIPS_INS_XOR16 = 620
MIPS_INS_XORI = 621
# some alias instructions
MIPS_INS_NOP = 622
MIPS_INS_NEGU = 623
# special instructions
MIPS_INS_JALR_HB = 624
MIPS_INS_JR_HB = 625
MIPS_INS_ENDING = 626
MIPS_GRP_INVALID = 0
MIPS_GRP_JUMP = 1
MIPS_GRP_CALL = 2
MIPS_GRP_RET = 3
MIPS_GRP_INT = 4
MIPS_GRP_IRET = 5
MIPS_GRP_PRIVILEGE = 6
MIPS_GRP_BRANCH_RELATIVE = 7
MIPS_GRP_BITCOUNT = 128
MIPS_GRP_DSP = 129
MIPS_GRP_DSPR2 = 130
MIPS_GRP_FPIDX = 131
MIPS_GRP_MSA = 132
MIPS_GRP_MIPS32R2 = 133
MIPS_GRP_MIPS64 = 134
MIPS_GRP_MIPS64R2 = 135
MIPS_GRP_SEINREG = 136
MIPS_GRP_STDENC = 137
MIPS_GRP_SWAP = 138
MIPS_GRP_MICROMIPS = 139
MIPS_GRP_MIPS16MODE = 140
MIPS_GRP_FP64BIT = 141
MIPS_GRP_NONANSFPMATH = 142
MIPS_GRP_NOTFP64BIT = 143
MIPS_GRP_NOTINMICROMIPS = 144
MIPS_GRP_NOTNACL = 145
MIPS_GRP_NOTMIPS32R6 = 146
MIPS_GRP_NOTMIPS64R6 = 147
MIPS_GRP_CNMIPS = 148
MIPS_GRP_MIPS32 = 149
MIPS_GRP_MIPS32R6 = 150
MIPS_GRP_MIPS64R6 = 151
MIPS_GRP_MIPS2 = 152
MIPS_GRP_MIPS3 = 153
MIPS_GRP_MIPS3_32 = 154
MIPS_GRP_MIPS3_32R2 = 155
MIPS_GRP_MIPS4_32 = 156
MIPS_GRP_MIPS4_32R2 = 157
MIPS_GRP_MIPS5_32R2 = 158
MIPS_GRP_GP32BIT = 159
MIPS_GRP_GP64BIT = 160
MIPS_GRP_ENDING = 161
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/mips_const.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .sparc_const import *
# define the API
class SparcOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('disp', ctypes.c_int32),
)
class SparcOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', SparcOpMem),
)
class SparcOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', SparcOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsSparc(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('hint', ctypes.c_uint),
('op_count', ctypes.c_uint8),
('operands', SparcOp * 4),
)
def get_arch_info(a):
return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/sparc.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
SPARC_CC_INVALID = 0
SPARC_CC_ICC_A = 8+256
SPARC_CC_ICC_N = 0+256
SPARC_CC_ICC_NE = 9+256
SPARC_CC_ICC_E = 1+256
SPARC_CC_ICC_G = 10+256
SPARC_CC_ICC_LE = 2+256
SPARC_CC_ICC_GE = 11+256
SPARC_CC_ICC_L = 3+256
SPARC_CC_ICC_GU = 12+256
SPARC_CC_ICC_LEU = 4+256
SPARC_CC_ICC_CC = 13+256
SPARC_CC_ICC_CS = 5+256
SPARC_CC_ICC_POS = 14+256
SPARC_CC_ICC_NEG = 6+256
SPARC_CC_ICC_VC = 15+256
SPARC_CC_ICC_VS = 7+256
SPARC_CC_FCC_A = 8+16+256
SPARC_CC_FCC_N = 0+16+256
SPARC_CC_FCC_U = 7+16+256
SPARC_CC_FCC_G = 6+16+256
SPARC_CC_FCC_UG = 5+16+256
SPARC_CC_FCC_L = 4+16+256
SPARC_CC_FCC_UL = 3+16+256
SPARC_CC_FCC_LG = 2+16+256
SPARC_CC_FCC_NE = 1+16+256
SPARC_CC_FCC_E = 9+16+256
SPARC_CC_FCC_UE = 10+16+256
SPARC_CC_FCC_GE = 11+16+256
SPARC_CC_FCC_UGE = 12+16+256
SPARC_CC_FCC_LE = 13+16+256
SPARC_CC_FCC_ULE = 14+16+256
SPARC_CC_FCC_O = 15+16+256
SPARC_HINT_INVALID = 0
SPARC_HINT_A = 1<<0
SPARC_HINT_PT = 1<<1
SPARC_HINT_PN = 1<<2
SPARC_OP_INVALID = 0
SPARC_OP_REG = 1
SPARC_OP_IMM = 2
SPARC_OP_MEM = 3
SPARC_REG_INVALID = 0
SPARC_REG_F0 = 1
SPARC_REG_F1 = 2
SPARC_REG_F2 = 3
SPARC_REG_F3 = 4
SPARC_REG_F4 = 5
SPARC_REG_F5 = 6
SPARC_REG_F6 = 7
SPARC_REG_F7 = 8
SPARC_REG_F8 = 9
SPARC_REG_F9 = 10
SPARC_REG_F10 = 11
SPARC_REG_F11 = 12
SPARC_REG_F12 = 13
SPARC_REG_F13 = 14
SPARC_REG_F14 = 15
SPARC_REG_F15 = 16
SPARC_REG_F16 = 17
SPARC_REG_F17 = 18
SPARC_REG_F18 = 19
SPARC_REG_F19 = 20
SPARC_REG_F20 = 21
SPARC_REG_F21 = 22
SPARC_REG_F22 = 23
SPARC_REG_F23 = 24
SPARC_REG_F24 = 25
SPARC_REG_F25 = 26
SPARC_REG_F26 = 27
SPARC_REG_F27 = 28
SPARC_REG_F28 = 29
SPARC_REG_F29 = 30
SPARC_REG_F30 = 31
SPARC_REG_F31 = 32
SPARC_REG_F32 = 33
SPARC_REG_F34 = 34
SPARC_REG_F36 = 35
SPARC_REG_F38 = 36
SPARC_REG_F40 = 37
SPARC_REG_F42 = 38
SPARC_REG_F44 = 39
SPARC_REG_F46 = 40
SPARC_REG_F48 = 41
SPARC_REG_F50 = 42
SPARC_REG_F52 = 43
SPARC_REG_F54 = 44
SPARC_REG_F56 = 45
SPARC_REG_F58 = 46
SPARC_REG_F60 = 47
SPARC_REG_F62 = 48
SPARC_REG_FCC0 = 49
SPARC_REG_FCC1 = 50
SPARC_REG_FCC2 = 51
SPARC_REG_FCC3 = 52
SPARC_REG_FP = 53
SPARC_REG_G0 = 54
SPARC_REG_G1 = 55
SPARC_REG_G2 = 56
SPARC_REG_G3 = 57
SPARC_REG_G4 = 58
SPARC_REG_G5 = 59
SPARC_REG_G6 = 60
SPARC_REG_G7 = 61
SPARC_REG_I0 = 62
SPARC_REG_I1 = 63
SPARC_REG_I2 = 64
SPARC_REG_I3 = 65
SPARC_REG_I4 = 66
SPARC_REG_I5 = 67
SPARC_REG_I7 = 68
SPARC_REG_ICC = 69
SPARC_REG_L0 = 70
SPARC_REG_L1 = 71
SPARC_REG_L2 = 72
SPARC_REG_L3 = 73
SPARC_REG_L4 = 74
SPARC_REG_L5 = 75
SPARC_REG_L6 = 76
SPARC_REG_L7 = 77
SPARC_REG_O0 = 78
SPARC_REG_O1 = 79
SPARC_REG_O2 = 80
SPARC_REG_O3 = 81
SPARC_REG_O4 = 82
SPARC_REG_O5 = 83
SPARC_REG_O7 = 84
SPARC_REG_SP = 85
SPARC_REG_Y = 86
SPARC_REG_XCC = 87
SPARC_REG_ENDING = 88
SPARC_REG_O6 = SPARC_REG_SP
SPARC_REG_I6 = SPARC_REG_FP
SPARC_INS_INVALID = 0
SPARC_INS_ADDCC = 1
SPARC_INS_ADDX = 2
SPARC_INS_ADDXCC = 3
SPARC_INS_ADDXC = 4
SPARC_INS_ADDXCCC = 5
SPARC_INS_ADD = 6
SPARC_INS_ALIGNADDR = 7
SPARC_INS_ALIGNADDRL = 8
SPARC_INS_ANDCC = 9
SPARC_INS_ANDNCC = 10
SPARC_INS_ANDN = 11
SPARC_INS_AND = 12
SPARC_INS_ARRAY16 = 13
SPARC_INS_ARRAY32 = 14
SPARC_INS_ARRAY8 = 15
SPARC_INS_B = 16
SPARC_INS_JMP = 17
SPARC_INS_BMASK = 18
SPARC_INS_FB = 19
SPARC_INS_BRGEZ = 20
SPARC_INS_BRGZ = 21
SPARC_INS_BRLEZ = 22
SPARC_INS_BRLZ = 23
SPARC_INS_BRNZ = 24
SPARC_INS_BRZ = 25
SPARC_INS_BSHUFFLE = 26
SPARC_INS_CALL = 27
SPARC_INS_CASX = 28
SPARC_INS_CAS = 29
SPARC_INS_CMASK16 = 30
SPARC_INS_CMASK32 = 31
SPARC_INS_CMASK8 = 32
SPARC_INS_CMP = 33
SPARC_INS_EDGE16 = 34
SPARC_INS_EDGE16L = 35
SPARC_INS_EDGE16LN = 36
SPARC_INS_EDGE16N = 37
SPARC_INS_EDGE32 = 38
SPARC_INS_EDGE32L = 39
SPARC_INS_EDGE32LN = 40
SPARC_INS_EDGE32N = 41
SPARC_INS_EDGE8 = 42
SPARC_INS_EDGE8L = 43
SPARC_INS_EDGE8LN = 44
SPARC_INS_EDGE8N = 45
SPARC_INS_FABSD = 46
SPARC_INS_FABSQ = 47
SPARC_INS_FABSS = 48
SPARC_INS_FADDD = 49
SPARC_INS_FADDQ = 50
SPARC_INS_FADDS = 51
SPARC_INS_FALIGNDATA = 52
SPARC_INS_FAND = 53
SPARC_INS_FANDNOT1 = 54
SPARC_INS_FANDNOT1S = 55
SPARC_INS_FANDNOT2 = 56
SPARC_INS_FANDNOT2S = 57
SPARC_INS_FANDS = 58
SPARC_INS_FCHKSM16 = 59
SPARC_INS_FCMPD = 60
SPARC_INS_FCMPEQ16 = 61
SPARC_INS_FCMPEQ32 = 62
SPARC_INS_FCMPGT16 = 63
SPARC_INS_FCMPGT32 = 64
SPARC_INS_FCMPLE16 = 65
SPARC_INS_FCMPLE32 = 66
SPARC_INS_FCMPNE16 = 67
SPARC_INS_FCMPNE32 = 68
SPARC_INS_FCMPQ = 69
SPARC_INS_FCMPS = 70
SPARC_INS_FDIVD = 71
SPARC_INS_FDIVQ = 72
SPARC_INS_FDIVS = 73
SPARC_INS_FDMULQ = 74
SPARC_INS_FDTOI = 75
SPARC_INS_FDTOQ = 76
SPARC_INS_FDTOS = 77
SPARC_INS_FDTOX = 78
SPARC_INS_FEXPAND = 79
SPARC_INS_FHADDD = 80
SPARC_INS_FHADDS = 81
SPARC_INS_FHSUBD = 82
SPARC_INS_FHSUBS = 83
SPARC_INS_FITOD = 84
SPARC_INS_FITOQ = 85
SPARC_INS_FITOS = 86
SPARC_INS_FLCMPD = 87
SPARC_INS_FLCMPS = 88
SPARC_INS_FLUSHW = 89
SPARC_INS_FMEAN16 = 90
SPARC_INS_FMOVD = 91
SPARC_INS_FMOVQ = 92
SPARC_INS_FMOVRDGEZ = 93
SPARC_INS_FMOVRQGEZ = 94
SPARC_INS_FMOVRSGEZ = 95
SPARC_INS_FMOVRDGZ = 96
SPARC_INS_FMOVRQGZ = 97
SPARC_INS_FMOVRSGZ = 98
SPARC_INS_FMOVRDLEZ = 99
SPARC_INS_FMOVRQLEZ = 100
SPARC_INS_FMOVRSLEZ = 101
SPARC_INS_FMOVRDLZ = 102
SPARC_INS_FMOVRQLZ = 103
SPARC_INS_FMOVRSLZ = 104
SPARC_INS_FMOVRDNZ = 105
SPARC_INS_FMOVRQNZ = 106
SPARC_INS_FMOVRSNZ = 107
SPARC_INS_FMOVRDZ = 108
SPARC_INS_FMOVRQZ = 109
SPARC_INS_FMOVRSZ = 110
SPARC_INS_FMOVS = 111
SPARC_INS_FMUL8SUX16 = 112
SPARC_INS_FMUL8ULX16 = 113
SPARC_INS_FMUL8X16 = 114
SPARC_INS_FMUL8X16AL = 115
SPARC_INS_FMUL8X16AU = 116
SPARC_INS_FMULD = 117
SPARC_INS_FMULD8SUX16 = 118
SPARC_INS_FMULD8ULX16 = 119
SPARC_INS_FMULQ = 120
SPARC_INS_FMULS = 121
SPARC_INS_FNADDD = 122
SPARC_INS_FNADDS = 123
SPARC_INS_FNAND = 124
SPARC_INS_FNANDS = 125
SPARC_INS_FNEGD = 126
SPARC_INS_FNEGQ = 127
SPARC_INS_FNEGS = 128
SPARC_INS_FNHADDD = 129
SPARC_INS_FNHADDS = 130
SPARC_INS_FNOR = 131
SPARC_INS_FNORS = 132
SPARC_INS_FNOT1 = 133
SPARC_INS_FNOT1S = 134
SPARC_INS_FNOT2 = 135
SPARC_INS_FNOT2S = 136
SPARC_INS_FONE = 137
SPARC_INS_FONES = 138
SPARC_INS_FOR = 139
SPARC_INS_FORNOT1 = 140
SPARC_INS_FORNOT1S = 141
SPARC_INS_FORNOT2 = 142
SPARC_INS_FORNOT2S = 143
SPARC_INS_FORS = 144
SPARC_INS_FPACK16 = 145
SPARC_INS_FPACK32 = 146
SPARC_INS_FPACKFIX = 147
SPARC_INS_FPADD16 = 148
SPARC_INS_FPADD16S = 149
SPARC_INS_FPADD32 = 150
SPARC_INS_FPADD32S = 151
SPARC_INS_FPADD64 = 152
SPARC_INS_FPMERGE = 153
SPARC_INS_FPSUB16 = 154
SPARC_INS_FPSUB16S = 155
SPARC_INS_FPSUB32 = 156
SPARC_INS_FPSUB32S = 157
SPARC_INS_FQTOD = 158
SPARC_INS_FQTOI = 159
SPARC_INS_FQTOS = 160
SPARC_INS_FQTOX = 161
SPARC_INS_FSLAS16 = 162
SPARC_INS_FSLAS32 = 163
SPARC_INS_FSLL16 = 164
SPARC_INS_FSLL32 = 165
SPARC_INS_FSMULD = 166
SPARC_INS_FSQRTD = 167
SPARC_INS_FSQRTQ = 168
SPARC_INS_FSQRTS = 169
SPARC_INS_FSRA16 = 170
SPARC_INS_FSRA32 = 171
SPARC_INS_FSRC1 = 172
SPARC_INS_FSRC1S = 173
SPARC_INS_FSRC2 = 174
SPARC_INS_FSRC2S = 175
SPARC_INS_FSRL16 = 176
SPARC_INS_FSRL32 = 177
SPARC_INS_FSTOD = 178
SPARC_INS_FSTOI = 179
SPARC_INS_FSTOQ = 180
SPARC_INS_FSTOX = 181
SPARC_INS_FSUBD = 182
SPARC_INS_FSUBQ = 183
SPARC_INS_FSUBS = 184
SPARC_INS_FXNOR = 185
SPARC_INS_FXNORS = 186
SPARC_INS_FXOR = 187
SPARC_INS_FXORS = 188
SPARC_INS_FXTOD = 189
SPARC_INS_FXTOQ = 190
SPARC_INS_FXTOS = 191
SPARC_INS_FZERO = 192
SPARC_INS_FZEROS = 193
SPARC_INS_JMPL = 194
SPARC_INS_LDD = 195
SPARC_INS_LD = 196
SPARC_INS_LDQ = 197
SPARC_INS_LDSB = 198
SPARC_INS_LDSH = 199
SPARC_INS_LDSW = 200
SPARC_INS_LDUB = 201
SPARC_INS_LDUH = 202
SPARC_INS_LDX = 203
SPARC_INS_LZCNT = 204
SPARC_INS_MEMBAR = 205
SPARC_INS_MOVDTOX = 206
SPARC_INS_MOV = 207
SPARC_INS_MOVRGEZ = 208
SPARC_INS_MOVRGZ = 209
SPARC_INS_MOVRLEZ = 210
SPARC_INS_MOVRLZ = 211
SPARC_INS_MOVRNZ = 212
SPARC_INS_MOVRZ = 213
SPARC_INS_MOVSTOSW = 214
SPARC_INS_MOVSTOUW = 215
SPARC_INS_MULX = 216
SPARC_INS_NOP = 217
SPARC_INS_ORCC = 218
SPARC_INS_ORNCC = 219
SPARC_INS_ORN = 220
SPARC_INS_OR = 221
SPARC_INS_PDIST = 222
SPARC_INS_PDISTN = 223
SPARC_INS_POPC = 224
SPARC_INS_RD = 225
SPARC_INS_RESTORE = 226
SPARC_INS_RETT = 227
SPARC_INS_SAVE = 228
SPARC_INS_SDIVCC = 229
SPARC_INS_SDIVX = 230
SPARC_INS_SDIV = 231
SPARC_INS_SETHI = 232
SPARC_INS_SHUTDOWN = 233
SPARC_INS_SIAM = 234
SPARC_INS_SLLX = 235
SPARC_INS_SLL = 236
SPARC_INS_SMULCC = 237
SPARC_INS_SMUL = 238
SPARC_INS_SRAX = 239
SPARC_INS_SRA = 240
SPARC_INS_SRLX = 241
SPARC_INS_SRL = 242
SPARC_INS_STBAR = 243
SPARC_INS_STB = 244
SPARC_INS_STD = 245
SPARC_INS_ST = 246
SPARC_INS_STH = 247
SPARC_INS_STQ = 248
SPARC_INS_STX = 249
SPARC_INS_SUBCC = 250
SPARC_INS_SUBX = 251
SPARC_INS_SUBXCC = 252
SPARC_INS_SUB = 253
SPARC_INS_SWAP = 254
SPARC_INS_TADDCCTV = 255
SPARC_INS_TADDCC = 256
SPARC_INS_T = 257
SPARC_INS_TSUBCCTV = 258
SPARC_INS_TSUBCC = 259
SPARC_INS_UDIVCC = 260
SPARC_INS_UDIVX = 261
SPARC_INS_UDIV = 262
SPARC_INS_UMULCC = 263
SPARC_INS_UMULXHI = 264
SPARC_INS_UMUL = 265
SPARC_INS_UNIMP = 266
SPARC_INS_FCMPED = 267
SPARC_INS_FCMPEQ = 268
SPARC_INS_FCMPES = 269
SPARC_INS_WR = 270
SPARC_INS_XMULX = 271
SPARC_INS_XMULXHI = 272
SPARC_INS_XNORCC = 273
SPARC_INS_XNOR = 274
SPARC_INS_XORCC = 275
SPARC_INS_XOR = 276
SPARC_INS_RET = 277
SPARC_INS_RETL = 278
SPARC_INS_ENDING = 279
SPARC_GRP_INVALID = 0
SPARC_GRP_JUMP = 1
SPARC_GRP_HARDQUAD = 128
SPARC_GRP_V9 = 129
SPARC_GRP_VIS = 130
SPARC_GRP_VIS2 = 131
SPARC_GRP_VIS3 = 132
SPARC_GRP_32BIT = 133
SPARC_GRP_64BIT = 134
SPARC_GRP_ENDING = 135
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/sparc_const.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .xcore_const import *
# define the API
class XcoreOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('disp', ctypes.c_int32),
('direct', ctypes.c_int),
)
class XcoreOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('mem', XcoreOpMem),
)
class XcoreOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', XcoreOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsXcore(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', XcoreOp * 8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/xcore.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py]
MOS65XX_REG_INVALID = 0
MOS65XX_REG_ACC = 1
MOS65XX_REG_X = 2
MOS65XX_REG_Y = 3
MOS65XX_REG_P = 4
MOS65XX_REG_SP = 5
MOS65XX_REG_DP = 6
MOS65XX_REG_B = 7
MOS65XX_REG_K = 8
MOS65XX_REG_ENDING = 9
MOS65XX_AM_NONE = 0
MOS65XX_AM_IMP = 1
MOS65XX_AM_ACC = 2
MOS65XX_AM_IMM = 3
MOS65XX_AM_REL = 4
MOS65XX_AM_INT = 5
MOS65XX_AM_BLOCK = 6
MOS65XX_AM_ZP = 7
MOS65XX_AM_ZP_X = 8
MOS65XX_AM_ZP_Y = 9
MOS65XX_AM_ZP_REL = 10
MOS65XX_AM_ZP_IND = 11
MOS65XX_AM_ZP_X_IND = 12
MOS65XX_AM_ZP_IND_Y = 13
MOS65XX_AM_ZP_IND_LONG = 14
MOS65XX_AM_ZP_IND_LONG_Y = 15
MOS65XX_AM_ABS = 16
MOS65XX_AM_ABS_X = 17
MOS65XX_AM_ABS_Y = 18
MOS65XX_AM_ABS_IND = 19
MOS65XX_AM_ABS_X_IND = 20
MOS65XX_AM_ABS_IND_LONG = 21
MOS65XX_AM_ABS_LONG = 22
MOS65XX_AM_ABS_LONG_X = 23
MOS65XX_AM_SR = 24
MOS65XX_AM_SR_IND_Y = 25
MOS65XX_INS_INVALID = 0
MOS65XX_INS_ADC = 1
MOS65XX_INS_AND = 2
MOS65XX_INS_ASL = 3
MOS65XX_INS_BBR = 4
MOS65XX_INS_BBS = 5
MOS65XX_INS_BCC = 6
MOS65XX_INS_BCS = 7
MOS65XX_INS_BEQ = 8
MOS65XX_INS_BIT = 9
MOS65XX_INS_BMI = 10
MOS65XX_INS_BNE = 11
MOS65XX_INS_BPL = 12
MOS65XX_INS_BRA = 13
MOS65XX_INS_BRK = 14
MOS65XX_INS_BRL = 15
MOS65XX_INS_BVC = 16
MOS65XX_INS_BVS = 17
MOS65XX_INS_CLC = 18
MOS65XX_INS_CLD = 19
MOS65XX_INS_CLI = 20
MOS65XX_INS_CLV = 21
MOS65XX_INS_CMP = 22
MOS65XX_INS_COP = 23
MOS65XX_INS_CPX = 24
MOS65XX_INS_CPY = 25
MOS65XX_INS_DEC = 26
MOS65XX_INS_DEX = 27
MOS65XX_INS_DEY = 28
MOS65XX_INS_EOR = 29
MOS65XX_INS_INC = 30
MOS65XX_INS_INX = 31
MOS65XX_INS_INY = 32
MOS65XX_INS_JML = 33
MOS65XX_INS_JMP = 34
MOS65XX_INS_JSL = 35
MOS65XX_INS_JSR = 36
MOS65XX_INS_LDA = 37
MOS65XX_INS_LDX = 38
MOS65XX_INS_LDY = 39
MOS65XX_INS_LSR = 40
MOS65XX_INS_MVN = 41
MOS65XX_INS_MVP = 42
MOS65XX_INS_NOP = 43
MOS65XX_INS_ORA = 44
MOS65XX_INS_PEA = 45
MOS65XX_INS_PEI = 46
MOS65XX_INS_PER = 47
MOS65XX_INS_PHA = 48
MOS65XX_INS_PHB = 49
MOS65XX_INS_PHD = 50
MOS65XX_INS_PHK = 51
MOS65XX_INS_PHP = 52
MOS65XX_INS_PHX = 53
MOS65XX_INS_PHY = 54
MOS65XX_INS_PLA = 55
MOS65XX_INS_PLB = 56
MOS65XX_INS_PLD = 57
MOS65XX_INS_PLP = 58
MOS65XX_INS_PLX = 59
MOS65XX_INS_PLY = 60
MOS65XX_INS_REP = 61
MOS65XX_INS_RMB = 62
MOS65XX_INS_ROL = 63
MOS65XX_INS_ROR = 64
MOS65XX_INS_RTI = 65
MOS65XX_INS_RTL = 66
MOS65XX_INS_RTS = 67
MOS65XX_INS_SBC = 68
MOS65XX_INS_SEC = 69
MOS65XX_INS_SED = 70
MOS65XX_INS_SEI = 71
MOS65XX_INS_SEP = 72
MOS65XX_INS_SMB = 73
MOS65XX_INS_STA = 74
MOS65XX_INS_STP = 75
MOS65XX_INS_STX = 76
MOS65XX_INS_STY = 77
MOS65XX_INS_STZ = 78
MOS65XX_INS_TAX = 79
MOS65XX_INS_TAY = 80
MOS65XX_INS_TCD = 81
MOS65XX_INS_TCS = 82
MOS65XX_INS_TDC = 83
MOS65XX_INS_TRB = 84
MOS65XX_INS_TSB = 85
MOS65XX_INS_TSC = 86
MOS65XX_INS_TSX = 87
MOS65XX_INS_TXA = 88
MOS65XX_INS_TXS = 89
MOS65XX_INS_TXY = 90
MOS65XX_INS_TYA = 91
MOS65XX_INS_TYX = 92
MOS65XX_INS_WAI = 93
MOS65XX_INS_WDM = 94
MOS65XX_INS_XBA = 95
MOS65XX_INS_XCE = 96
MOS65XX_INS_ENDING = 97
MOS65XX_GRP_INVALID = 0
MOS65XX_GRP_JUMP = 1
MOS65XX_GRP_CALL = 2
MOS65XX_GRP_RET = 3
MOS65XX_GRP_INT = 4
MOS65XX_GRP_IRET = 5
MOS65XX_GRP_BRANCH_RELATIVE = 6
MOS65XX_GRP_ENDING = 7
MOS65XX_OP_INVALID = 0
MOS65XX_OP_REG = 1
MOS65XX_OP_IMM = 2
MOS65XX_OP_MEM = 3
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/mos65xx_const.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .arm64_const import *
# define the API
class Arm64OpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class Arm64OpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class Arm64OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('fp', ctypes.c_double),
('mem', Arm64OpMem),
('pstate', ctypes.c_int),
('sys', ctypes.c_uint),
('prefetch', ctypes.c_int),
('barrier', ctypes.c_int),
)
class Arm64Op(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('vas', ctypes.c_int),
('shift', Arm64OpShift),
('ext', ctypes.c_uint),
('type', ctypes.c_uint),
('value', Arm64OpValue),
('access', ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def pstate(self):
return self.value.pstate
@property
def sys(self):
return self.value.sys
@property
def prefetch(self):
return self.value.prefetch
@property
def barrier(self):
return self.value.barrier
class CsArm64(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('writeback', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', Arm64Op * 8),
)
def get_arch_info(a):
return (a.cc, a.update_flags, a.writeback, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/arm64.py
|
# Capstone Python bindings, by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net>
import ctypes
from . import copy_ctypes_list
from .m680x_const import *
# define the API
class M680xOpIdx(ctypes.Structure):
_fields_ = (
('base_reg', ctypes.c_uint),
('offset_reg', ctypes.c_uint),
('offset', ctypes.c_int16),
('offset_addr', ctypes.c_uint16),
('offset_bits', ctypes.c_uint8),
('inc_dec', ctypes.c_int8),
('flags', ctypes.c_uint8),
)
class M680xOpRel(ctypes.Structure):
_fields_ = (
('address', ctypes.c_uint16),
('offset', ctypes.c_int16),
)
class M680xOpExt(ctypes.Structure):
_fields_ = (
('address', ctypes.c_uint16),
('indirect', ctypes.c_bool),
)
class M680xOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int32),
('reg', ctypes.c_uint),
('idx', M680xOpIdx),
('rel', M680xOpRel),
('ext', M680xOpExt),
('direct_addr', ctypes.c_uint8),
('const_val', ctypes.c_uint8),
)
class M680xOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', M680xOpValue),
('size', ctypes.c_uint8),
('access', ctypes.c_uint8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def idx(self):
return self.value.idx
@property
def rel(self):
return self.value.rel
@property
def ext(self):
return self.value.ext
@property
def direct_addr(self):
return self.value.direct_addr
@property
def const_val(self):
return self.value.const_val
class CsM680x(ctypes.Structure):
_fields_ = (
('flags', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', M680xOp * 9),
)
def get_arch_info(a):
return (a.flags, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/m680x.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .riscv_const import *
# define the API
class RISCVOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('disp', ctypes.c_int64),
)
class RISCVOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', RISCVOpMem),
)
class RISCVOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', RISCVOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsRISCV(ctypes.Structure):
_fields_ = (
('need_effective_addr', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', RISCVOp * 8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/riscv.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .ppc_const import *
# define the API
class PpcOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int32),
)
class PpcOpCrx(ctypes.Structure):
_fields_ = (
('scale', ctypes.c_uint),
('reg', ctypes.c_uint),
('cond', ctypes.c_uint),
)
class PpcOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', PpcOpMem),
('crx', PpcOpCrx),
)
class PpcOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', PpcOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
@property
def crx(self):
return self.value.crx
class CsPpc(ctypes.Structure):
_fields_ = (
('bc', ctypes.c_uint),
('bh', ctypes.c_uint),
('update_cr0', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', PpcOp * 8),
)
def get_arch_info(a):
return (a.bc, a.bh, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/ppc.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
# Operand type for instruction's operands
RISCV_OP_INVALID = 0
RISCV_OP_REG = 1
RISCV_OP_IMM = 2
RISCV_OP_MEM = 3
# RISCV registers
RISCV_REG_INVALID = 0
# General purpose registers
RISCV_REG_X0 = 1
RISCV_REG_ZERO = RISCV_REG_X0
RISCV_REG_X1 = 2
RISCV_REG_RA = RISCV_REG_X1
RISCV_REG_X2 = 3
RISCV_REG_SP = RISCV_REG_X2
RISCV_REG_X3 = 4
RISCV_REG_GP = RISCV_REG_X3
RISCV_REG_X4 = 5
RISCV_REG_TP = RISCV_REG_X4
RISCV_REG_X5 = 6
RISCV_REG_T0 = RISCV_REG_X5
RISCV_REG_X6 = 7
RISCV_REG_T1 = RISCV_REG_X6
RISCV_REG_X7 = 8
RISCV_REG_T2 = RISCV_REG_X7
RISCV_REG_X8 = 9
RISCV_REG_S0 = RISCV_REG_X8
RISCV_REG_FP = RISCV_REG_X8
RISCV_REG_X9 = 10
RISCV_REG_S1 = RISCV_REG_X9
RISCV_REG_X10 = 11
RISCV_REG_A0 = RISCV_REG_X10
RISCV_REG_X11 = 12
RISCV_REG_A1 = RISCV_REG_X11
RISCV_REG_X12 = 13
RISCV_REG_A2 = RISCV_REG_X12
RISCV_REG_X13 = 14
RISCV_REG_A3 = RISCV_REG_X13
RISCV_REG_X14 = 15
RISCV_REG_A4 = RISCV_REG_X14
RISCV_REG_X15 = 16
RISCV_REG_A5 = RISCV_REG_X15
RISCV_REG_X16 = 17
RISCV_REG_A6 = RISCV_REG_X16
RISCV_REG_X17 = 18
RISCV_REG_A7 = RISCV_REG_X17
RISCV_REG_X18 = 19
RISCV_REG_S2 = RISCV_REG_X18
RISCV_REG_X19 = 20
RISCV_REG_S3 = RISCV_REG_X19
RISCV_REG_X20 = 21
RISCV_REG_S4 = RISCV_REG_X20
RISCV_REG_X21 = 22
RISCV_REG_S5 = RISCV_REG_X21
RISCV_REG_X22 = 23
RISCV_REG_S6 = RISCV_REG_X22
RISCV_REG_X23 = 24
RISCV_REG_S7 = RISCV_REG_X23
RISCV_REG_X24 = 25
RISCV_REG_S8 = RISCV_REG_X24
RISCV_REG_X25 = 26
RISCV_REG_S9 = RISCV_REG_X25
RISCV_REG_X26 = 27
RISCV_REG_S10 = RISCV_REG_X26
RISCV_REG_X27 = 28
RISCV_REG_S11 = RISCV_REG_X27
RISCV_REG_X28 = 29
RISCV_REG_T3 = RISCV_REG_X28
RISCV_REG_X29 = 30
RISCV_REG_T4 = RISCV_REG_X29
RISCV_REG_X30 = 31
RISCV_REG_T5 = RISCV_REG_X30
RISCV_REG_X31 = 32
RISCV_REG_T6 = RISCV_REG_X31
# Floating-point registers
RISCV_REG_F0_32 = 33
RISCV_REG_F0_64 = 34
RISCV_REG_F1_32 = 35
RISCV_REG_F1_64 = 36
RISCV_REG_F2_32 = 37
RISCV_REG_F2_64 = 38
RISCV_REG_F3_32 = 39
RISCV_REG_F3_64 = 40
RISCV_REG_F4_32 = 41
RISCV_REG_F4_64 = 42
RISCV_REG_F5_32 = 43
RISCV_REG_F5_64 = 44
RISCV_REG_F6_32 = 45
RISCV_REG_F6_64 = 46
RISCV_REG_F7_32 = 47
RISCV_REG_F7_64 = 48
RISCV_REG_F8_32 = 49
RISCV_REG_F8_64 = 50
RISCV_REG_F9_32 = 51
RISCV_REG_F9_64 = 52
RISCV_REG_F10_32 = 53
RISCV_REG_F10_64 = 54
RISCV_REG_F11_32 = 55
RISCV_REG_F11_64 = 56
RISCV_REG_F12_32 = 57
RISCV_REG_F12_64 = 58
RISCV_REG_F13_32 = 59
RISCV_REG_F13_64 = 60
RISCV_REG_F14_32 = 61
RISCV_REG_F14_64 = 62
RISCV_REG_F15_32 = 63
RISCV_REG_F15_64 = 64
RISCV_REG_F16_32 = 65
RISCV_REG_F16_64 = 66
RISCV_REG_F17_32 = 67
RISCV_REG_F17_64 = 68
RISCV_REG_F18_32 = 69
RISCV_REG_F18_64 = 70
RISCV_REG_F19_32 = 71
RISCV_REG_F19_64 = 72
RISCV_REG_F20_32 = 73
RISCV_REG_F20_64 = 74
RISCV_REG_F21_32 = 75
RISCV_REG_F21_64 = 76
RISCV_REG_F22_32 = 77
RISCV_REG_F22_64 = 78
RISCV_REG_F23_32 = 79
RISCV_REG_F23_64 = 80
RISCV_REG_F24_32 = 81
RISCV_REG_F24_64 = 82
RISCV_REG_F25_32 = 83
RISCV_REG_F25_64 = 84
RISCV_REG_F26_32 = 85
RISCV_REG_F26_64 = 86
RISCV_REG_F27_32 = 87
RISCV_REG_F27_64 = 88
RISCV_REG_F28_32 = 89
RISCV_REG_F28_64 = 90
RISCV_REG_F29_32 = 91
RISCV_REG_F29_64 = 92
RISCV_REG_F30_32 = 93
RISCV_REG_F30_64 = 94
RISCV_REG_F31_32 = 95
RISCV_REG_F31_64 = 96
RISCV_REG_ENDING = 97
# RISCV instruction
RISCV_INS_INVALID = 0
RISCV_INS_ADD = 1
RISCV_INS_ADDI = 2
RISCV_INS_ADDIW = 3
RISCV_INS_ADDW = 4
RISCV_INS_AMOADD_D = 5
RISCV_INS_AMOADD_D_AQ = 6
RISCV_INS_AMOADD_D_AQ_RL = 7
RISCV_INS_AMOADD_D_RL = 8
RISCV_INS_AMOADD_W = 9
RISCV_INS_AMOADD_W_AQ = 10
RISCV_INS_AMOADD_W_AQ_RL = 11
RISCV_INS_AMOADD_W_RL = 12
RISCV_INS_AMOAND_D = 13
RISCV_INS_AMOAND_D_AQ = 14
RISCV_INS_AMOAND_D_AQ_RL = 15
RISCV_INS_AMOAND_D_RL = 16
RISCV_INS_AMOAND_W = 17
RISCV_INS_AMOAND_W_AQ = 18
RISCV_INS_AMOAND_W_AQ_RL = 19
RISCV_INS_AMOAND_W_RL = 20
RISCV_INS_AMOMAXU_D = 21
RISCV_INS_AMOMAXU_D_AQ = 22
RISCV_INS_AMOMAXU_D_AQ_RL = 23
RISCV_INS_AMOMAXU_D_RL = 24
RISCV_INS_AMOMAXU_W = 25
RISCV_INS_AMOMAXU_W_AQ = 26
RISCV_INS_AMOMAXU_W_AQ_RL = 27
RISCV_INS_AMOMAXU_W_RL = 28
RISCV_INS_AMOMAX_D = 29
RISCV_INS_AMOMAX_D_AQ = 30
RISCV_INS_AMOMAX_D_AQ_RL = 31
RISCV_INS_AMOMAX_D_RL = 32
RISCV_INS_AMOMAX_W = 33
RISCV_INS_AMOMAX_W_AQ = 34
RISCV_INS_AMOMAX_W_AQ_RL = 35
RISCV_INS_AMOMAX_W_RL = 36
RISCV_INS_AMOMINU_D = 37
RISCV_INS_AMOMINU_D_AQ = 38
RISCV_INS_AMOMINU_D_AQ_RL = 39
RISCV_INS_AMOMINU_D_RL = 40
RISCV_INS_AMOMINU_W = 41
RISCV_INS_AMOMINU_W_AQ = 42
RISCV_INS_AMOMINU_W_AQ_RL = 43
RISCV_INS_AMOMINU_W_RL = 44
RISCV_INS_AMOMIN_D = 45
RISCV_INS_AMOMIN_D_AQ = 46
RISCV_INS_AMOMIN_D_AQ_RL = 47
RISCV_INS_AMOMIN_D_RL = 48
RISCV_INS_AMOMIN_W = 49
RISCV_INS_AMOMIN_W_AQ = 50
RISCV_INS_AMOMIN_W_AQ_RL = 51
RISCV_INS_AMOMIN_W_RL = 52
RISCV_INS_AMOOR_D = 53
RISCV_INS_AMOOR_D_AQ = 54
RISCV_INS_AMOOR_D_AQ_RL = 55
RISCV_INS_AMOOR_D_RL = 56
RISCV_INS_AMOOR_W = 57
RISCV_INS_AMOOR_W_AQ = 58
RISCV_INS_AMOOR_W_AQ_RL = 59
RISCV_INS_AMOOR_W_RL = 60
RISCV_INS_AMOSWAP_D = 61
RISCV_INS_AMOSWAP_D_AQ = 62
RISCV_INS_AMOSWAP_D_AQ_RL = 63
RISCV_INS_AMOSWAP_D_RL = 64
RISCV_INS_AMOSWAP_W = 65
RISCV_INS_AMOSWAP_W_AQ = 66
RISCV_INS_AMOSWAP_W_AQ_RL = 67
RISCV_INS_AMOSWAP_W_RL = 68
RISCV_INS_AMOXOR_D = 69
RISCV_INS_AMOXOR_D_AQ = 70
RISCV_INS_AMOXOR_D_AQ_RL = 71
RISCV_INS_AMOXOR_D_RL = 72
RISCV_INS_AMOXOR_W = 73
RISCV_INS_AMOXOR_W_AQ = 74
RISCV_INS_AMOXOR_W_AQ_RL = 75
RISCV_INS_AMOXOR_W_RL = 76
RISCV_INS_AND = 77
RISCV_INS_ANDI = 78
RISCV_INS_AUIPC = 79
RISCV_INS_BEQ = 80
RISCV_INS_BGE = 81
RISCV_INS_BGEU = 82
RISCV_INS_BLT = 83
RISCV_INS_BLTU = 84
RISCV_INS_BNE = 85
RISCV_INS_CSRRC = 86
RISCV_INS_CSRRCI = 87
RISCV_INS_CSRRS = 88
RISCV_INS_CSRRSI = 89
RISCV_INS_CSRRW = 90
RISCV_INS_CSRRWI = 91
RISCV_INS_C_ADD = 92
RISCV_INS_C_ADDI = 93
RISCV_INS_C_ADDI16SP = 94
RISCV_INS_C_ADDI4SPN = 95
RISCV_INS_C_ADDIW = 96
RISCV_INS_C_ADDW = 97
RISCV_INS_C_AND = 98
RISCV_INS_C_ANDI = 99
RISCV_INS_C_BEQZ = 100
RISCV_INS_C_BNEZ = 101
RISCV_INS_C_EBREAK = 102
RISCV_INS_C_FLD = 103
RISCV_INS_C_FLDSP = 104
RISCV_INS_C_FLW = 105
RISCV_INS_C_FLWSP = 106
RISCV_INS_C_FSD = 107
RISCV_INS_C_FSDSP = 108
RISCV_INS_C_FSW = 109
RISCV_INS_C_FSWSP = 110
RISCV_INS_C_J = 111
RISCV_INS_C_JAL = 112
RISCV_INS_C_JALR = 113
RISCV_INS_C_JR = 114
RISCV_INS_C_LD = 115
RISCV_INS_C_LDSP = 116
RISCV_INS_C_LI = 117
RISCV_INS_C_LUI = 118
RISCV_INS_C_LW = 119
RISCV_INS_C_LWSP = 120
RISCV_INS_C_MV = 121
RISCV_INS_C_NOP = 122
RISCV_INS_C_OR = 123
RISCV_INS_C_SD = 124
RISCV_INS_C_SDSP = 125
RISCV_INS_C_SLLI = 126
RISCV_INS_C_SRAI = 127
RISCV_INS_C_SRLI = 128
RISCV_INS_C_SUB = 129
RISCV_INS_C_SUBW = 130
RISCV_INS_C_SW = 131
RISCV_INS_C_SWSP = 132
RISCV_INS_C_UNIMP = 133
RISCV_INS_C_XOR = 134
RISCV_INS_DIV = 135
RISCV_INS_DIVU = 136
RISCV_INS_DIVUW = 137
RISCV_INS_DIVW = 138
RISCV_INS_EBREAK = 139
RISCV_INS_ECALL = 140
RISCV_INS_FADD_D = 141
RISCV_INS_FADD_S = 142
RISCV_INS_FCLASS_D = 143
RISCV_INS_FCLASS_S = 144
RISCV_INS_FCVT_D_L = 145
RISCV_INS_FCVT_D_LU = 146
RISCV_INS_FCVT_D_S = 147
RISCV_INS_FCVT_D_W = 148
RISCV_INS_FCVT_D_WU = 149
RISCV_INS_FCVT_LU_D = 150
RISCV_INS_FCVT_LU_S = 151
RISCV_INS_FCVT_L_D = 152
RISCV_INS_FCVT_L_S = 153
RISCV_INS_FCVT_S_D = 154
RISCV_INS_FCVT_S_L = 155
RISCV_INS_FCVT_S_LU = 156
RISCV_INS_FCVT_S_W = 157
RISCV_INS_FCVT_S_WU = 158
RISCV_INS_FCVT_WU_D = 159
RISCV_INS_FCVT_WU_S = 160
RISCV_INS_FCVT_W_D = 161
RISCV_INS_FCVT_W_S = 162
RISCV_INS_FDIV_D = 163
RISCV_INS_FDIV_S = 164
RISCV_INS_FENCE = 165
RISCV_INS_FENCE_I = 166
RISCV_INS_FENCE_TSO = 167
RISCV_INS_FEQ_D = 168
RISCV_INS_FEQ_S = 169
RISCV_INS_FLD = 170
RISCV_INS_FLE_D = 171
RISCV_INS_FLE_S = 172
RISCV_INS_FLT_D = 173
RISCV_INS_FLT_S = 174
RISCV_INS_FLW = 175
RISCV_INS_FMADD_D = 176
RISCV_INS_FMADD_S = 177
RISCV_INS_FMAX_D = 178
RISCV_INS_FMAX_S = 179
RISCV_INS_FMIN_D = 180
RISCV_INS_FMIN_S = 181
RISCV_INS_FMSUB_D = 182
RISCV_INS_FMSUB_S = 183
RISCV_INS_FMUL_D = 184
RISCV_INS_FMUL_S = 185
RISCV_INS_FMV_D_X = 186
RISCV_INS_FMV_W_X = 187
RISCV_INS_FMV_X_D = 188
RISCV_INS_FMV_X_W = 189
RISCV_INS_FNMADD_D = 190
RISCV_INS_FNMADD_S = 191
RISCV_INS_FNMSUB_D = 192
RISCV_INS_FNMSUB_S = 193
RISCV_INS_FSD = 194
RISCV_INS_FSGNJN_D = 195
RISCV_INS_FSGNJN_S = 196
RISCV_INS_FSGNJX_D = 197
RISCV_INS_FSGNJX_S = 198
RISCV_INS_FSGNJ_D = 199
RISCV_INS_FSGNJ_S = 200
RISCV_INS_FSQRT_D = 201
RISCV_INS_FSQRT_S = 202
RISCV_INS_FSUB_D = 203
RISCV_INS_FSUB_S = 204
RISCV_INS_FSW = 205
RISCV_INS_JAL = 206
RISCV_INS_JALR = 207
RISCV_INS_LB = 208
RISCV_INS_LBU = 209
RISCV_INS_LD = 210
RISCV_INS_LH = 211
RISCV_INS_LHU = 212
RISCV_INS_LR_D = 213
RISCV_INS_LR_D_AQ = 214
RISCV_INS_LR_D_AQ_RL = 215
RISCV_INS_LR_D_RL = 216
RISCV_INS_LR_W = 217
RISCV_INS_LR_W_AQ = 218
RISCV_INS_LR_W_AQ_RL = 219
RISCV_INS_LR_W_RL = 220
RISCV_INS_LUI = 221
RISCV_INS_LW = 222
RISCV_INS_LWU = 223
RISCV_INS_MRET = 224
RISCV_INS_MUL = 225
RISCV_INS_MULH = 226
RISCV_INS_MULHSU = 227
RISCV_INS_MULHU = 228
RISCV_INS_MULW = 229
RISCV_INS_OR = 230
RISCV_INS_ORI = 231
RISCV_INS_REM = 232
RISCV_INS_REMU = 233
RISCV_INS_REMUW = 234
RISCV_INS_REMW = 235
RISCV_INS_SB = 236
RISCV_INS_SC_D = 237
RISCV_INS_SC_D_AQ = 238
RISCV_INS_SC_D_AQ_RL = 239
RISCV_INS_SC_D_RL = 240
RISCV_INS_SC_W = 241
RISCV_INS_SC_W_AQ = 242
RISCV_INS_SC_W_AQ_RL = 243
RISCV_INS_SC_W_RL = 244
RISCV_INS_SD = 245
RISCV_INS_SFENCE_VMA = 246
RISCV_INS_SH = 247
RISCV_INS_SLL = 248
RISCV_INS_SLLI = 249
RISCV_INS_SLLIW = 250
RISCV_INS_SLLW = 251
RISCV_INS_SLT = 252
RISCV_INS_SLTI = 253
RISCV_INS_SLTIU = 254
RISCV_INS_SLTU = 255
RISCV_INS_SRA = 256
RISCV_INS_SRAI = 257
RISCV_INS_SRAIW = 258
RISCV_INS_SRAW = 259
RISCV_INS_SRET = 260
RISCV_INS_SRL = 261
RISCV_INS_SRLI = 262
RISCV_INS_SRLIW = 263
RISCV_INS_SRLW = 264
RISCV_INS_SUB = 265
RISCV_INS_SUBW = 266
RISCV_INS_SW = 267
RISCV_INS_UNIMP = 268
RISCV_INS_URET = 269
RISCV_INS_WFI = 270
RISCV_INS_XOR = 271
RISCV_INS_XORI = 272
RISCV_INS_ENDING = 273
# Group of RISCV instructions
RISCV_GRP_INVALID = 0
RISCV_GRP_JUMP = 1
RISCV_GRP_ISRV32 = 128
RISCV_GRP_ISRV64 = 129
RISCV_GRP_HASSTDEXTA = 130
RISCV_GRP_HASSTDEXTC = 131
RISCV_GRP_HASSTDEXTD = 132
RISCV_GRP_HASSTDEXTF = 133
RISCV_GRP_HASSTDEXTM = 134
RISCV_GRP_ISRVA = 135
RISCV_GRP_ISRVC = 136
RISCV_GRP_ISRVD = 137
RISCV_GRP_ISRVCD = 138
RISCV_GRP_ISRVF = 139
RISCV_GRP_ISRV32C = 140
RISCV_GRP_ISRV32CF = 141
RISCV_GRP_ISRVM = 142
RISCV_GRP_ISRV64A = 143
RISCV_GRP_ISRV64C = 144
RISCV_GRP_ISRV64D = 145
RISCV_GRP_ISRV64F = 146
RISCV_GRP_ISRV64M = 147
RISCV_GRP_ENDING = 148
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/riscv_const.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .mos65xx_const import *
# define the API
class MOS65xxOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_uint8),
('mem', ctypes.c_uint16),
)
class MOS65xxOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', MOS65xxOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsMOS65xx(ctypes.Structure):
_fields_ = (
('am', ctypes.c_uint),
('modifies_flags', ctypes.c_uint8),
('op_count', ctypes.c_uint8),
('operands', MOS65xxOp * 3),
)
def get_arch_info(a):
return (a.am, a.modifies_flags, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/mos65xx.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .arm_const import *
# define the API
class ArmOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('scale', ctypes.c_int),
('disp', ctypes.c_int),
('lshift', ctypes.c_int),
)
class ArmOpShift(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', ctypes.c_uint),
)
class ArmOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('fp', ctypes.c_double),
('mem', ArmOpMem),
('setend', ctypes.c_int),
)
class ArmOp(ctypes.Structure):
_fields_ = (
('vector_index', ctypes.c_int),
('shift', ArmOpShift),
('type', ctypes.c_uint),
('value', ArmOpValue),
('subtracted', ctypes.c_bool),
('access', ctypes.c_uint8),
('neon_lane', ctypes.c_int8),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def fp(self):
return self.value.fp
@property
def mem(self):
return self.value.mem
@property
def setend(self):
return self.value.setend
class CsArm(ctypes.Structure):
_fields_ = (
('usermode', ctypes.c_bool),
('vector_size', ctypes.c_int),
('vector_data', ctypes.c_int),
('cps_mode', ctypes.c_int),
('cps_flag', ctypes.c_int),
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('writeback', ctypes.c_bool),
('mem_barrier', ctypes.c_int),
('op_count', ctypes.c_uint8),
('operands', ArmOp * 36),
)
def get_arch_info(a):
return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.update_flags, \
a.writeback, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/arm.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .sysz_const import *
# define the API
class SyszOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint8),
('index', ctypes.c_uint8),
('length', ctypes.c_uint64),
('disp', ctypes.c_int64),
)
class SyszOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', SyszOpMem),
)
class SyszOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', SyszOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsSysz(ctypes.Structure):
_fields_ = (
('cc', ctypes.c_uint),
('op_count', ctypes.c_uint8),
('operands', SyszOp * 6),
)
def get_arch_info(a):
return (a.cc, copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/systemz.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .mips_const import *
# define the API
class MipsOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int64),
)
class MipsOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', MipsOpMem),
)
class MipsOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', MipsOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsMips(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', MipsOp * 10),
)
def get_arch_info(a):
return copy_ctypes_list(a.operands[:a.op_count])
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/mips.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
ARM64_SFT_INVALID = 0
ARM64_SFT_LSL = 1
ARM64_SFT_MSL = 2
ARM64_SFT_LSR = 3
ARM64_SFT_ASR = 4
ARM64_SFT_ROR = 5
ARM64_EXT_INVALID = 0
ARM64_EXT_UXTB = 1
ARM64_EXT_UXTH = 2
ARM64_EXT_UXTW = 3
ARM64_EXT_UXTX = 4
ARM64_EXT_SXTB = 5
ARM64_EXT_SXTH = 6
ARM64_EXT_SXTW = 7
ARM64_EXT_SXTX = 8
ARM64_CC_INVALID = 0
ARM64_CC_EQ = 1
ARM64_CC_NE = 2
ARM64_CC_HS = 3
ARM64_CC_LO = 4
ARM64_CC_MI = 5
ARM64_CC_PL = 6
ARM64_CC_VS = 7
ARM64_CC_VC = 8
ARM64_CC_HI = 9
ARM64_CC_LS = 10
ARM64_CC_GE = 11
ARM64_CC_LT = 12
ARM64_CC_GT = 13
ARM64_CC_LE = 14
ARM64_CC_AL = 15
ARM64_CC_NV = 16
ARM64_SYSREG_INVALID = 0
ARM64_SYSREG_MDCCSR_EL0 = 0x9808
ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828
ARM64_SYSREG_MDRAR_EL1 = 0x8080
ARM64_SYSREG_OSLSR_EL1 = 0x808C
ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6
ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6
ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7
ARM64_SYSREG_MIDR_EL1 = 0xC000
ARM64_SYSREG_CCSIDR_EL1 = 0xC800
ARM64_SYSREG_CCSIDR2_EL1 = 0xC802
ARM64_SYSREG_CLIDR_EL1 = 0xC801
ARM64_SYSREG_CTR_EL0 = 0xD801
ARM64_SYSREG_MPIDR_EL1 = 0xC005
ARM64_SYSREG_REVIDR_EL1 = 0xC006
ARM64_SYSREG_AIDR_EL1 = 0xC807
ARM64_SYSREG_DCZID_EL0 = 0xD807
ARM64_SYSREG_ID_PFR0_EL1 = 0xC008
ARM64_SYSREG_ID_PFR1_EL1 = 0xC009
ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A
ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B
ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C
ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D
ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E
ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F
ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010
ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011
ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012
ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013
ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014
ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015
ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017
ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020
ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021
ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028
ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029
ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C
ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D
ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030
ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031
ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038
ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039
ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A
ARM64_SYSREG_MVFR0_EL1 = 0xC018
ARM64_SYSREG_MVFR1_EL1 = 0xC019
ARM64_SYSREG_MVFR2_EL1 = 0xC01A
ARM64_SYSREG_RVBAR_EL1 = 0xC601
ARM64_SYSREG_RVBAR_EL2 = 0xE601
ARM64_SYSREG_RVBAR_EL3 = 0xF601
ARM64_SYSREG_ISR_EL1 = 0xC608
ARM64_SYSREG_CNTPCT_EL0 = 0xDF01
ARM64_SYSREG_CNTVCT_EL0 = 0xDF02
ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016
ARM64_SYSREG_TRCSTATR = 0x8818
ARM64_SYSREG_TRCIDR8 = 0x8806
ARM64_SYSREG_TRCIDR9 = 0x880E
ARM64_SYSREG_TRCIDR10 = 0x8816
ARM64_SYSREG_TRCIDR11 = 0x881E
ARM64_SYSREG_TRCIDR12 = 0x8826
ARM64_SYSREG_TRCIDR13 = 0x882E
ARM64_SYSREG_TRCIDR0 = 0x8847
ARM64_SYSREG_TRCIDR1 = 0x884F
ARM64_SYSREG_TRCIDR2 = 0x8857
ARM64_SYSREG_TRCIDR3 = 0x885F
ARM64_SYSREG_TRCIDR4 = 0x8867
ARM64_SYSREG_TRCIDR5 = 0x886F
ARM64_SYSREG_TRCIDR6 = 0x8877
ARM64_SYSREG_TRCIDR7 = 0x887F
ARM64_SYSREG_TRCOSLSR = 0x888C
ARM64_SYSREG_TRCPDSR = 0x88AC
ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6
ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE
ARM64_SYSREG_TRCLSR = 0x8BEE
ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6
ARM64_SYSREG_TRCDEVARCH = 0x8BFE
ARM64_SYSREG_TRCDEVID = 0x8B97
ARM64_SYSREG_TRCDEVTYPE = 0x8B9F
ARM64_SYSREG_TRCPIDR4 = 0x8BA7
ARM64_SYSREG_TRCPIDR5 = 0x8BAF
ARM64_SYSREG_TRCPIDR6 = 0x8BB7
ARM64_SYSREG_TRCPIDR7 = 0x8BBF
ARM64_SYSREG_TRCPIDR0 = 0x8BC7
ARM64_SYSREG_TRCPIDR1 = 0x8BCF
ARM64_SYSREG_TRCPIDR2 = 0x8BD7
ARM64_SYSREG_TRCPIDR3 = 0x8BDF
ARM64_SYSREG_TRCCIDR0 = 0x8BE7
ARM64_SYSREG_TRCCIDR1 = 0x8BEF
ARM64_SYSREG_TRCCIDR2 = 0x8BF7
ARM64_SYSREG_TRCCIDR3 = 0x8BFF
ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660
ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640
ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662
ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642
ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B
ARM64_SYSREG_ICH_VTR_EL2 = 0xE659
ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B
ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D
ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024
ARM64_SYSREG_LORID_EL1 = 0xC527
ARM64_SYSREG_ERRIDR_EL1 = 0xC298
ARM64_SYSREG_ERXFR_EL1 = 0xC2A0
ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828
ARM64_SYSREG_OSLAR_EL1 = 0x8084
ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4
ARM64_SYSREG_TRCOSLAR = 0x8884
ARM64_SYSREG_TRCLAR = 0x8BE6
ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661
ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641
ARM64_SYSREG_ICC_DIR_EL1 = 0xC659
ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D
ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E
ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F
ARM64_SYSREG_OSDTRRX_EL1 = 0x8002
ARM64_SYSREG_OSDTRTX_EL1 = 0x801A
ARM64_SYSREG_TEECR32_EL1 = 0x9000
ARM64_SYSREG_MDCCINT_EL1 = 0x8010
ARM64_SYSREG_MDSCR_EL1 = 0x8012
ARM64_SYSREG_DBGDTR_EL0 = 0x9820
ARM64_SYSREG_OSECCR_EL1 = 0x8032
ARM64_SYSREG_DBGVCR32_EL2 = 0xA038
ARM64_SYSREG_DBGBVR0_EL1 = 0x8004
ARM64_SYSREG_DBGBVR1_EL1 = 0x800C
ARM64_SYSREG_DBGBVR2_EL1 = 0x8014
ARM64_SYSREG_DBGBVR3_EL1 = 0x801C
ARM64_SYSREG_DBGBVR4_EL1 = 0x8024
ARM64_SYSREG_DBGBVR5_EL1 = 0x802C
ARM64_SYSREG_DBGBVR6_EL1 = 0x8034
ARM64_SYSREG_DBGBVR7_EL1 = 0x803C
ARM64_SYSREG_DBGBVR8_EL1 = 0x8044
ARM64_SYSREG_DBGBVR9_EL1 = 0x804C
ARM64_SYSREG_DBGBVR10_EL1 = 0x8054
ARM64_SYSREG_DBGBVR11_EL1 = 0x805C
ARM64_SYSREG_DBGBVR12_EL1 = 0x8064
ARM64_SYSREG_DBGBVR13_EL1 = 0x806C
ARM64_SYSREG_DBGBVR14_EL1 = 0x8074
ARM64_SYSREG_DBGBVR15_EL1 = 0x807C
ARM64_SYSREG_DBGBCR0_EL1 = 0x8005
ARM64_SYSREG_DBGBCR1_EL1 = 0x800D
ARM64_SYSREG_DBGBCR2_EL1 = 0x8015
ARM64_SYSREG_DBGBCR3_EL1 = 0x801D
ARM64_SYSREG_DBGBCR4_EL1 = 0x8025
ARM64_SYSREG_DBGBCR5_EL1 = 0x802D
ARM64_SYSREG_DBGBCR6_EL1 = 0x8035
ARM64_SYSREG_DBGBCR7_EL1 = 0x803D
ARM64_SYSREG_DBGBCR8_EL1 = 0x8045
ARM64_SYSREG_DBGBCR9_EL1 = 0x804D
ARM64_SYSREG_DBGBCR10_EL1 = 0x8055
ARM64_SYSREG_DBGBCR11_EL1 = 0x805D
ARM64_SYSREG_DBGBCR12_EL1 = 0x8065
ARM64_SYSREG_DBGBCR13_EL1 = 0x806D
ARM64_SYSREG_DBGBCR14_EL1 = 0x8075
ARM64_SYSREG_DBGBCR15_EL1 = 0x807D
ARM64_SYSREG_DBGWVR0_EL1 = 0x8006
ARM64_SYSREG_DBGWVR1_EL1 = 0x800E
ARM64_SYSREG_DBGWVR2_EL1 = 0x8016
ARM64_SYSREG_DBGWVR3_EL1 = 0x801E
ARM64_SYSREG_DBGWVR4_EL1 = 0x8026
ARM64_SYSREG_DBGWVR5_EL1 = 0x802E
ARM64_SYSREG_DBGWVR6_EL1 = 0x8036
ARM64_SYSREG_DBGWVR7_EL1 = 0x803E
ARM64_SYSREG_DBGWVR8_EL1 = 0x8046
ARM64_SYSREG_DBGWVR9_EL1 = 0x804E
ARM64_SYSREG_DBGWVR10_EL1 = 0x8056
ARM64_SYSREG_DBGWVR11_EL1 = 0x805E
ARM64_SYSREG_DBGWVR12_EL1 = 0x8066
ARM64_SYSREG_DBGWVR13_EL1 = 0x806E
ARM64_SYSREG_DBGWVR14_EL1 = 0x8076
ARM64_SYSREG_DBGWVR15_EL1 = 0x807E
ARM64_SYSREG_DBGWCR0_EL1 = 0x8007
ARM64_SYSREG_DBGWCR1_EL1 = 0x800F
ARM64_SYSREG_DBGWCR2_EL1 = 0x8017
ARM64_SYSREG_DBGWCR3_EL1 = 0x801F
ARM64_SYSREG_DBGWCR4_EL1 = 0x8027
ARM64_SYSREG_DBGWCR5_EL1 = 0x802F
ARM64_SYSREG_DBGWCR6_EL1 = 0x8037
ARM64_SYSREG_DBGWCR7_EL1 = 0x803F
ARM64_SYSREG_DBGWCR8_EL1 = 0x8047
ARM64_SYSREG_DBGWCR9_EL1 = 0x804F
ARM64_SYSREG_DBGWCR10_EL1 = 0x8057
ARM64_SYSREG_DBGWCR11_EL1 = 0x805F
ARM64_SYSREG_DBGWCR12_EL1 = 0x8067
ARM64_SYSREG_DBGWCR13_EL1 = 0x806F
ARM64_SYSREG_DBGWCR14_EL1 = 0x8077
ARM64_SYSREG_DBGWCR15_EL1 = 0x807F
ARM64_SYSREG_TEEHBR32_EL1 = 0x9080
ARM64_SYSREG_OSDLR_EL1 = 0x809C
ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4
ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6
ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE
ARM64_SYSREG_CSSELR_EL1 = 0xD000
ARM64_SYSREG_VPIDR_EL2 = 0xE000
ARM64_SYSREG_VMPIDR_EL2 = 0xE005
ARM64_SYSREG_CPACR_EL1 = 0xC082
ARM64_SYSREG_SCTLR_EL1 = 0xC080
ARM64_SYSREG_SCTLR_EL2 = 0xE080
ARM64_SYSREG_SCTLR_EL3 = 0xF080
ARM64_SYSREG_ACTLR_EL1 = 0xC081
ARM64_SYSREG_ACTLR_EL2 = 0xE081
ARM64_SYSREG_ACTLR_EL3 = 0xF081
ARM64_SYSREG_HCR_EL2 = 0xE088
ARM64_SYSREG_SCR_EL3 = 0xF088
ARM64_SYSREG_MDCR_EL2 = 0xE089
ARM64_SYSREG_SDER32_EL3 = 0xF089
ARM64_SYSREG_CPTR_EL2 = 0xE08A
ARM64_SYSREG_CPTR_EL3 = 0xF08A
ARM64_SYSREG_HSTR_EL2 = 0xE08B
ARM64_SYSREG_HACR_EL2 = 0xE08F
ARM64_SYSREG_MDCR_EL3 = 0xF099
ARM64_SYSREG_TTBR0_EL1 = 0xC100
ARM64_SYSREG_TTBR0_EL2 = 0xE100
ARM64_SYSREG_TTBR0_EL3 = 0xF100
ARM64_SYSREG_TTBR1_EL1 = 0xC101
ARM64_SYSREG_TCR_EL1 = 0xC102
ARM64_SYSREG_TCR_EL2 = 0xE102
ARM64_SYSREG_TCR_EL3 = 0xF102
ARM64_SYSREG_VTTBR_EL2 = 0xE108
ARM64_SYSREG_VTCR_EL2 = 0xE10A
ARM64_SYSREG_DACR32_EL2 = 0xE180
ARM64_SYSREG_SPSR_EL1 = 0xC200
ARM64_SYSREG_SPSR_EL2 = 0xE200
ARM64_SYSREG_SPSR_EL3 = 0xF200
ARM64_SYSREG_ELR_EL1 = 0xC201
ARM64_SYSREG_ELR_EL2 = 0xE201
ARM64_SYSREG_ELR_EL3 = 0xF201
ARM64_SYSREG_SP_EL0 = 0xC208
ARM64_SYSREG_SP_EL1 = 0xE208
ARM64_SYSREG_SP_EL2 = 0xF208
ARM64_SYSREG_SPSEL = 0xC210
ARM64_SYSREG_NZCV = 0xDA10
ARM64_SYSREG_DAIF = 0xDA11
ARM64_SYSREG_CURRENTEL = 0xC212
ARM64_SYSREG_SPSR_IRQ = 0xE218
ARM64_SYSREG_SPSR_ABT = 0xE219
ARM64_SYSREG_SPSR_UND = 0xE21A
ARM64_SYSREG_SPSR_FIQ = 0xE21B
ARM64_SYSREG_FPCR = 0xDA20
ARM64_SYSREG_FPSR = 0xDA21
ARM64_SYSREG_DSPSR_EL0 = 0xDA28
ARM64_SYSREG_DLR_EL0 = 0xDA29
ARM64_SYSREG_IFSR32_EL2 = 0xE281
ARM64_SYSREG_AFSR0_EL1 = 0xC288
ARM64_SYSREG_AFSR0_EL2 = 0xE288
ARM64_SYSREG_AFSR0_EL3 = 0xF288
ARM64_SYSREG_AFSR1_EL1 = 0xC289
ARM64_SYSREG_AFSR1_EL2 = 0xE289
ARM64_SYSREG_AFSR1_EL3 = 0xF289
ARM64_SYSREG_ESR_EL1 = 0xC290
ARM64_SYSREG_ESR_EL2 = 0xE290
ARM64_SYSREG_ESR_EL3 = 0xF290
ARM64_SYSREG_FPEXC32_EL2 = 0xE298
ARM64_SYSREG_FAR_EL1 = 0xC300
ARM64_SYSREG_FAR_EL2 = 0xE300
ARM64_SYSREG_FAR_EL3 = 0xF300
ARM64_SYSREG_HPFAR_EL2 = 0xE304
ARM64_SYSREG_PAR_EL1 = 0xC3A0
ARM64_SYSREG_PMCR_EL0 = 0xDCE0
ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1
ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2
ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3
ARM64_SYSREG_PMSELR_EL0 = 0xDCE5
ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8
ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9
ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA
ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0
ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1
ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2
ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3
ARM64_SYSREG_MAIR_EL1 = 0xC510
ARM64_SYSREG_MAIR_EL2 = 0xE510
ARM64_SYSREG_MAIR_EL3 = 0xF510
ARM64_SYSREG_AMAIR_EL1 = 0xC518
ARM64_SYSREG_AMAIR_EL2 = 0xE518
ARM64_SYSREG_AMAIR_EL3 = 0xF518
ARM64_SYSREG_VBAR_EL1 = 0xC600
ARM64_SYSREG_VBAR_EL2 = 0xE600
ARM64_SYSREG_VBAR_EL3 = 0xF600
ARM64_SYSREG_RMR_EL1 = 0xC602
ARM64_SYSREG_RMR_EL2 = 0xE602
ARM64_SYSREG_RMR_EL3 = 0xF602
ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681
ARM64_SYSREG_TPIDR_EL0 = 0xDE82
ARM64_SYSREG_TPIDR_EL2 = 0xE682
ARM64_SYSREG_TPIDR_EL3 = 0xF682
ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83
ARM64_SYSREG_TPIDR_EL1 = 0xC684
ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00
ARM64_SYSREG_CNTVOFF_EL2 = 0xE703
ARM64_SYSREG_CNTKCTL_EL1 = 0xC708
ARM64_SYSREG_CNTHCTL_EL2 = 0xE708
ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10
ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710
ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10
ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11
ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711
ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11
ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12
ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712
ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12
ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18
ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19
ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A
ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40
ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41
ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42
ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43
ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44
ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45
ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46
ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47
ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48
ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49
ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A
ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B
ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C
ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D
ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E
ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F
ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50
ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51
ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52
ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53
ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54
ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55
ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56
ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57
ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58
ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59
ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A
ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B
ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C
ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D
ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E
ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F
ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60
ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61
ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62
ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63
ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64
ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65
ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66
ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67
ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68
ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69
ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A
ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B
ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C
ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D
ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E
ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F
ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70
ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71
ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72
ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73
ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74
ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75
ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76
ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77
ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78
ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79
ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A
ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B
ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C
ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D
ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E
ARM64_SYSREG_TRCPRGCTLR = 0x8808
ARM64_SYSREG_TRCPROCSELR = 0x8810
ARM64_SYSREG_TRCCONFIGR = 0x8820
ARM64_SYSREG_TRCAUXCTLR = 0x8830
ARM64_SYSREG_TRCEVENTCTL0R = 0x8840
ARM64_SYSREG_TRCEVENTCTL1R = 0x8848
ARM64_SYSREG_TRCSTALLCTLR = 0x8858
ARM64_SYSREG_TRCTSCTLR = 0x8860
ARM64_SYSREG_TRCSYNCPR = 0x8868
ARM64_SYSREG_TRCCCCTLR = 0x8870
ARM64_SYSREG_TRCBBCTLR = 0x8878
ARM64_SYSREG_TRCTRACEIDR = 0x8801
ARM64_SYSREG_TRCQCTLR = 0x8809
ARM64_SYSREG_TRCVICTLR = 0x8802
ARM64_SYSREG_TRCVIIECTLR = 0x880A
ARM64_SYSREG_TRCVISSCTLR = 0x8812
ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A
ARM64_SYSREG_TRCVDCTLR = 0x8842
ARM64_SYSREG_TRCVDSACCTLR = 0x884A
ARM64_SYSREG_TRCVDARCCTLR = 0x8852
ARM64_SYSREG_TRCSEQEVR0 = 0x8804
ARM64_SYSREG_TRCSEQEVR1 = 0x880C
ARM64_SYSREG_TRCSEQEVR2 = 0x8814
ARM64_SYSREG_TRCSEQRSTEVR = 0x8834
ARM64_SYSREG_TRCSEQSTR = 0x883C
ARM64_SYSREG_TRCEXTINSELR = 0x8844
ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805
ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D
ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815
ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D
ARM64_SYSREG_TRCCNTCTLR0 = 0x8825
ARM64_SYSREG_TRCCNTCTLR1 = 0x882D
ARM64_SYSREG_TRCCNTCTLR2 = 0x8835
ARM64_SYSREG_TRCCNTCTLR3 = 0x883D
ARM64_SYSREG_TRCCNTVR0 = 0x8845
ARM64_SYSREG_TRCCNTVR1 = 0x884D
ARM64_SYSREG_TRCCNTVR2 = 0x8855
ARM64_SYSREG_TRCCNTVR3 = 0x885D
ARM64_SYSREG_TRCIMSPEC0 = 0x8807
ARM64_SYSREG_TRCIMSPEC1 = 0x880F
ARM64_SYSREG_TRCIMSPEC2 = 0x8817
ARM64_SYSREG_TRCIMSPEC3 = 0x881F
ARM64_SYSREG_TRCIMSPEC4 = 0x8827
ARM64_SYSREG_TRCIMSPEC5 = 0x882F
ARM64_SYSREG_TRCIMSPEC6 = 0x8837
ARM64_SYSREG_TRCIMSPEC7 = 0x883F
ARM64_SYSREG_TRCRSCTLR2 = 0x8890
ARM64_SYSREG_TRCRSCTLR3 = 0x8898
ARM64_SYSREG_TRCRSCTLR4 = 0x88A0
ARM64_SYSREG_TRCRSCTLR5 = 0x88A8
ARM64_SYSREG_TRCRSCTLR6 = 0x88B0
ARM64_SYSREG_TRCRSCTLR7 = 0x88B8
ARM64_SYSREG_TRCRSCTLR8 = 0x88C0
ARM64_SYSREG_TRCRSCTLR9 = 0x88C8
ARM64_SYSREG_TRCRSCTLR10 = 0x88D0
ARM64_SYSREG_TRCRSCTLR11 = 0x88D8
ARM64_SYSREG_TRCRSCTLR12 = 0x88E0
ARM64_SYSREG_TRCRSCTLR13 = 0x88E8
ARM64_SYSREG_TRCRSCTLR14 = 0x88F0
ARM64_SYSREG_TRCRSCTLR15 = 0x88F8
ARM64_SYSREG_TRCRSCTLR16 = 0x8881
ARM64_SYSREG_TRCRSCTLR17 = 0x8889
ARM64_SYSREG_TRCRSCTLR18 = 0x8891
ARM64_SYSREG_TRCRSCTLR19 = 0x8899
ARM64_SYSREG_TRCRSCTLR20 = 0x88A1
ARM64_SYSREG_TRCRSCTLR21 = 0x88A9
ARM64_SYSREG_TRCRSCTLR22 = 0x88B1
ARM64_SYSREG_TRCRSCTLR23 = 0x88B9
ARM64_SYSREG_TRCRSCTLR24 = 0x88C1
ARM64_SYSREG_TRCRSCTLR25 = 0x88C9
ARM64_SYSREG_TRCRSCTLR26 = 0x88D1
ARM64_SYSREG_TRCRSCTLR27 = 0x88D9
ARM64_SYSREG_TRCRSCTLR28 = 0x88E1
ARM64_SYSREG_TRCRSCTLR29 = 0x88E9
ARM64_SYSREG_TRCRSCTLR30 = 0x88F1
ARM64_SYSREG_TRCRSCTLR31 = 0x88F9
ARM64_SYSREG_TRCSSCCR0 = 0x8882
ARM64_SYSREG_TRCSSCCR1 = 0x888A
ARM64_SYSREG_TRCSSCCR2 = 0x8892
ARM64_SYSREG_TRCSSCCR3 = 0x889A
ARM64_SYSREG_TRCSSCCR4 = 0x88A2
ARM64_SYSREG_TRCSSCCR5 = 0x88AA
ARM64_SYSREG_TRCSSCCR6 = 0x88B2
ARM64_SYSREG_TRCSSCCR7 = 0x88BA
ARM64_SYSREG_TRCSSCSR0 = 0x88C2
ARM64_SYSREG_TRCSSCSR1 = 0x88CA
ARM64_SYSREG_TRCSSCSR2 = 0x88D2
ARM64_SYSREG_TRCSSCSR3 = 0x88DA
ARM64_SYSREG_TRCSSCSR4 = 0x88E2
ARM64_SYSREG_TRCSSCSR5 = 0x88EA
ARM64_SYSREG_TRCSSCSR6 = 0x88F2
ARM64_SYSREG_TRCSSCSR7 = 0x88FA
ARM64_SYSREG_TRCSSPCICR0 = 0x8883
ARM64_SYSREG_TRCSSPCICR1 = 0x888B
ARM64_SYSREG_TRCSSPCICR2 = 0x8893
ARM64_SYSREG_TRCSSPCICR3 = 0x889B
ARM64_SYSREG_TRCSSPCICR4 = 0x88A3
ARM64_SYSREG_TRCSSPCICR5 = 0x88AB
ARM64_SYSREG_TRCSSPCICR6 = 0x88B3
ARM64_SYSREG_TRCSSPCICR7 = 0x88BB
ARM64_SYSREG_TRCPDCR = 0x88A4
ARM64_SYSREG_TRCACVR0 = 0x8900
ARM64_SYSREG_TRCACVR1 = 0x8910
ARM64_SYSREG_TRCACVR2 = 0x8920
ARM64_SYSREG_TRCACVR3 = 0x8930
ARM64_SYSREG_TRCACVR4 = 0x8940
ARM64_SYSREG_TRCACVR5 = 0x8950
ARM64_SYSREG_TRCACVR6 = 0x8960
ARM64_SYSREG_TRCACVR7 = 0x8970
ARM64_SYSREG_TRCACVR8 = 0x8901
ARM64_SYSREG_TRCACVR9 = 0x8911
ARM64_SYSREG_TRCACVR10 = 0x8921
ARM64_SYSREG_TRCACVR11 = 0x8931
ARM64_SYSREG_TRCACVR12 = 0x8941
ARM64_SYSREG_TRCACVR13 = 0x8951
ARM64_SYSREG_TRCACVR14 = 0x8961
ARM64_SYSREG_TRCACVR15 = 0x8971
ARM64_SYSREG_TRCACATR0 = 0x8902
ARM64_SYSREG_TRCACATR1 = 0x8912
ARM64_SYSREG_TRCACATR2 = 0x8922
ARM64_SYSREG_TRCACATR3 = 0x8932
ARM64_SYSREG_TRCACATR4 = 0x8942
ARM64_SYSREG_TRCACATR5 = 0x8952
ARM64_SYSREG_TRCACATR6 = 0x8962
ARM64_SYSREG_TRCACATR7 = 0x8972
ARM64_SYSREG_TRCACATR8 = 0x8903
ARM64_SYSREG_TRCACATR9 = 0x8913
ARM64_SYSREG_TRCACATR10 = 0x8923
ARM64_SYSREG_TRCACATR11 = 0x8933
ARM64_SYSREG_TRCACATR12 = 0x8943
ARM64_SYSREG_TRCACATR13 = 0x8953
ARM64_SYSREG_TRCACATR14 = 0x8963
ARM64_SYSREG_TRCACATR15 = 0x8973
ARM64_SYSREG_TRCDVCVR0 = 0x8904
ARM64_SYSREG_TRCDVCVR1 = 0x8924
ARM64_SYSREG_TRCDVCVR2 = 0x8944
ARM64_SYSREG_TRCDVCVR3 = 0x8964
ARM64_SYSREG_TRCDVCVR4 = 0x8905
ARM64_SYSREG_TRCDVCVR5 = 0x8925
ARM64_SYSREG_TRCDVCVR6 = 0x8945
ARM64_SYSREG_TRCDVCVR7 = 0x8965
ARM64_SYSREG_TRCDVCMR0 = 0x8906
ARM64_SYSREG_TRCDVCMR1 = 0x8926
ARM64_SYSREG_TRCDVCMR2 = 0x8946
ARM64_SYSREG_TRCDVCMR3 = 0x8966
ARM64_SYSREG_TRCDVCMR4 = 0x8907
ARM64_SYSREG_TRCDVCMR5 = 0x8927
ARM64_SYSREG_TRCDVCMR6 = 0x8947
ARM64_SYSREG_TRCDVCMR7 = 0x8967
ARM64_SYSREG_TRCCIDCVR0 = 0x8980
ARM64_SYSREG_TRCCIDCVR1 = 0x8990
ARM64_SYSREG_TRCCIDCVR2 = 0x89A0
ARM64_SYSREG_TRCCIDCVR3 = 0x89B0
ARM64_SYSREG_TRCCIDCVR4 = 0x89C0
ARM64_SYSREG_TRCCIDCVR5 = 0x89D0
ARM64_SYSREG_TRCCIDCVR6 = 0x89E0
ARM64_SYSREG_TRCCIDCVR7 = 0x89F0
ARM64_SYSREG_TRCVMIDCVR0 = 0x8981
ARM64_SYSREG_TRCVMIDCVR1 = 0x8991
ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1
ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1
ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1
ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1
ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1
ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1
ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982
ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A
ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992
ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A
ARM64_SYSREG_TRCITCTRL = 0x8B84
ARM64_SYSREG_TRCCLAIMSET = 0x8BC6
ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE
ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663
ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643
ARM64_SYSREG_ICC_PMR_EL1 = 0xC230
ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664
ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664
ARM64_SYSREG_ICC_SRE_EL1 = 0xC665
ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D
ARM64_SYSREG_ICC_SRE_EL3 = 0xF665
ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666
ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667
ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667
ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668
ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644
ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645
ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646
ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647
ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648
ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649
ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A
ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B
ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640
ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641
ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642
ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643
ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648
ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649
ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A
ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B
ARM64_SYSREG_ICH_HCR_EL2 = 0xE658
ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A
ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F
ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C
ARM64_SYSREG_ICH_LR0_EL2 = 0xE660
ARM64_SYSREG_ICH_LR1_EL2 = 0xE661
ARM64_SYSREG_ICH_LR2_EL2 = 0xE662
ARM64_SYSREG_ICH_LR3_EL2 = 0xE663
ARM64_SYSREG_ICH_LR4_EL2 = 0xE664
ARM64_SYSREG_ICH_LR5_EL2 = 0xE665
ARM64_SYSREG_ICH_LR6_EL2 = 0xE666
ARM64_SYSREG_ICH_LR7_EL2 = 0xE667
ARM64_SYSREG_ICH_LR8_EL2 = 0xE668
ARM64_SYSREG_ICH_LR9_EL2 = 0xE669
ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A
ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B
ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C
ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D
ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E
ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F
ARM64_SYSREG_PAN = 0xC213
ARM64_SYSREG_LORSA_EL1 = 0xC520
ARM64_SYSREG_LOREA_EL1 = 0xC521
ARM64_SYSREG_LORN_EL1 = 0xC522
ARM64_SYSREG_LORC_EL1 = 0xC523
ARM64_SYSREG_TTBR1_EL2 = 0xE101
ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681
ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718
ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A
ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719
ARM64_SYSREG_SCTLR_EL12 = 0xE880
ARM64_SYSREG_CPACR_EL12 = 0xE882
ARM64_SYSREG_TTBR0_EL12 = 0xE900
ARM64_SYSREG_TTBR1_EL12 = 0xE901
ARM64_SYSREG_TCR_EL12 = 0xE902
ARM64_SYSREG_AFSR0_EL12 = 0xEA88
ARM64_SYSREG_AFSR1_EL12 = 0xEA89
ARM64_SYSREG_ESR_EL12 = 0xEA90
ARM64_SYSREG_FAR_EL12 = 0xEB00
ARM64_SYSREG_MAIR_EL12 = 0xED10
ARM64_SYSREG_AMAIR_EL12 = 0xED18
ARM64_SYSREG_VBAR_EL12 = 0xEE00
ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81
ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08
ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10
ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11
ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12
ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18
ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19
ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A
ARM64_SYSREG_SPSR_EL12 = 0xEA00
ARM64_SYSREG_ELR_EL12 = 0xEA01
ARM64_SYSREG_UAO = 0xC214
ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0
ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1
ARM64_SYSREG_PMBSR_EL1 = 0xC4D3
ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7
ARM64_SYSREG_PMSCR_EL2 = 0xE4C8
ARM64_SYSREG_PMSCR_EL12 = 0xECC8
ARM64_SYSREG_PMSCR_EL1 = 0xC4C8
ARM64_SYSREG_PMSICR_EL1 = 0xC4CA
ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB
ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC
ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD
ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE
ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF
ARM64_SYSREG_ERRSELR_EL1 = 0xC299
ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1
ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2
ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3
ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8
ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9
ARM64_SYSREG_DISR_EL1 = 0xC609
ARM64_SYSREG_VDISR_EL2 = 0xE609
ARM64_SYSREG_VSESR_EL2 = 0xE293
ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108
ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109
ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A
ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B
ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110
ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111
ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112
ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113
ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118
ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119
ARM64_SYSREG_VSTCR_EL2 = 0xE132
ARM64_SYSREG_VSTTBR_EL2 = 0xE130
ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720
ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722
ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721
ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728
ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A
ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729
ARM64_SYSREG_SDER32_EL2 = 0xE099
ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5
ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6
ARM64_SYSREG_ERXTS_EL1 = 0xC2AF
ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA
ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB
ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4
ARM64_SYSREG_MPAM0_EL1 = 0xC529
ARM64_SYSREG_MPAM1_EL1 = 0xC528
ARM64_SYSREG_MPAM2_EL2 = 0xE528
ARM64_SYSREG_MPAM3_EL3 = 0xF528
ARM64_SYSREG_MPAM1_EL12 = 0xED28
ARM64_SYSREG_MPAMHCR_EL2 = 0xE520
ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521
ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530
ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531
ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532
ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533
ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534
ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535
ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536
ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537
ARM64_SYSREG_MPAMIDR_EL1 = 0xC524
ARM64_SYSREG_AMCR_EL0 = 0xDE90
ARM64_SYSREG_AMCFGR_EL0 = 0xDE91
ARM64_SYSREG_AMCGCR_EL0 = 0xDE92
ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93
ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94
ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95
ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0
ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1
ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2
ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3
ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0
ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1
ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2
ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3
ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98
ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99
ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0
ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1
ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2
ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3
ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4
ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5
ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6
ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7
ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8
ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9
ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA
ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB
ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC
ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED
ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE
ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF
ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0
ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1
ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2
ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3
ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4
ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5
ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6
ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7
ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8
ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9
ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA
ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB
ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC
ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD
ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE
ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF
ARM64_SYSREG_TRFCR_EL1 = 0xC091
ARM64_SYSREG_TRFCR_EL2 = 0xE091
ARM64_SYSREG_TRFCR_EL12 = 0xE891
ARM64_SYSREG_DIT = 0xDA15
ARM64_SYSREG_VNCR_EL2 = 0xE110
ARM64_SYSREG_ZCR_EL1 = 0xC090
ARM64_SYSREG_ZCR_EL2 = 0xE090
ARM64_SYSREG_ZCR_EL3 = 0xF090
ARM64_SYSREG_ZCR_EL12 = 0xE890
ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90
ARM64_PSTATE_INVALID = 0
ARM64_PSTATE_SPSEL = 0x05
ARM64_PSTATE_DAIFSET = 0x1e
ARM64_PSTATE_DAIFCLR = 0x1f
ARM64_PSTATE_PAN = 0x4
ARM64_PSTATE_UAO = 0x3
ARM64_PSTATE_DIT = 0x1a
ARM64_VAS_INVALID = 0
ARM64_VAS_16B = 1
ARM64_VAS_8B = 2
ARM64_VAS_4B = 3
ARM64_VAS_1B = 4
ARM64_VAS_8H = 5
ARM64_VAS_4H = 6
ARM64_VAS_2H = 7
ARM64_VAS_1H = 8
ARM64_VAS_4S = 9
ARM64_VAS_2S = 10
ARM64_VAS_1S = 11
ARM64_VAS_2D = 12
ARM64_VAS_1D = 13
ARM64_VAS_1Q = 14
ARM64_BARRIER_INVALID = 0
ARM64_BARRIER_OSHLD = 0x1
ARM64_BARRIER_OSHST = 0x2
ARM64_BARRIER_OSH = 0x3
ARM64_BARRIER_NSHLD = 0x5
ARM64_BARRIER_NSHST = 0x6
ARM64_BARRIER_NSH = 0x7
ARM64_BARRIER_ISHLD = 0x9
ARM64_BARRIER_ISHST = 0xa
ARM64_BARRIER_ISH = 0xb
ARM64_BARRIER_LD = 0xd
ARM64_BARRIER_ST = 0xe
ARM64_BARRIER_SY = 0xf
ARM64_OP_INVALID = 0
ARM64_OP_REG = 1
ARM64_OP_IMM = 2
ARM64_OP_MEM = 3
ARM64_OP_FP = 4
ARM64_OP_CIMM = 64
ARM64_OP_REG_MRS = 65
ARM64_OP_REG_MSR = 66
ARM64_OP_PSTATE = 67
ARM64_OP_SYS = 68
ARM64_OP_PREFETCH = 69
ARM64_OP_BARRIER = 70
ARM64_TLBI_INVALID = 0
ARM64_TLBI_IPAS2E1IS = 1
ARM64_TLBI_IPAS2LE1IS = 2
ARM64_TLBI_VMALLE1IS = 3
ARM64_TLBI_ALLE2IS = 4
ARM64_TLBI_ALLE3IS = 5
ARM64_TLBI_VAE1IS = 6
ARM64_TLBI_VAE2IS = 7
ARM64_TLBI_VAE3IS = 8
ARM64_TLBI_ASIDE1IS = 9
ARM64_TLBI_VAAE1IS = 10
ARM64_TLBI_ALLE1IS = 11
ARM64_TLBI_VALE1IS = 12
ARM64_TLBI_VALE2IS = 13
ARM64_TLBI_VALE3IS = 14
ARM64_TLBI_VMALLS12E1IS = 15
ARM64_TLBI_VAALE1IS = 16
ARM64_TLBI_IPAS2E1 = 17
ARM64_TLBI_IPAS2LE1 = 18
ARM64_TLBI_VMALLE1 = 19
ARM64_TLBI_ALLE2 = 20
ARM64_TLBI_ALLE3 = 21
ARM64_TLBI_VAE1 = 22
ARM64_TLBI_VAE2 = 23
ARM64_TLBI_VAE3 = 24
ARM64_TLBI_ASIDE1 = 25
ARM64_TLBI_VAAE1 = 26
ARM64_TLBI_ALLE1 = 27
ARM64_TLBI_VALE1 = 28
ARM64_TLBI_VALE2 = 29
ARM64_TLBI_VALE3 = 30
ARM64_TLBI_VMALLS12E1 = 31
ARM64_TLBI_VAALE1 = 32
ARM64_TLBI_VMALLE1OS = 33
ARM64_TLBI_VAE1OS = 34
ARM64_TLBI_ASIDE1OS = 35
ARM64_TLBI_VAAE1OS = 36
ARM64_TLBI_VALE1OS = 37
ARM64_TLBI_VAALE1OS = 38
ARM64_TLBI_IPAS2E1OS = 39
ARM64_TLBI_IPAS2LE1OS = 40
ARM64_TLBI_VAE2OS = 41
ARM64_TLBI_VALE2OS = 42
ARM64_TLBI_VMALLS12E1OS = 43
ARM64_TLBI_VAE3OS = 44
ARM64_TLBI_VALE3OS = 45
ARM64_TLBI_ALLE2OS = 46
ARM64_TLBI_ALLE1OS = 47
ARM64_TLBI_ALLE3OS = 48
ARM64_TLBI_RVAE1 = 49
ARM64_TLBI_RVAAE1 = 50
ARM64_TLBI_RVALE1 = 51
ARM64_TLBI_RVAALE1 = 52
ARM64_TLBI_RVAE1IS = 53
ARM64_TLBI_RVAAE1IS = 54
ARM64_TLBI_RVALE1IS = 55
ARM64_TLBI_RVAALE1IS = 56
ARM64_TLBI_RVAE1OS = 57
ARM64_TLBI_RVAAE1OS = 58
ARM64_TLBI_RVALE1OS = 59
ARM64_TLBI_RVAALE1OS = 60
ARM64_TLBI_RIPAS2E1IS = 61
ARM64_TLBI_RIPAS2LE1IS = 62
ARM64_TLBI_RIPAS2E1 = 63
ARM64_TLBI_RIPAS2LE1 = 64
ARM64_TLBI_RIPAS2E1OS = 65
ARM64_TLBI_RIPAS2LE1OS = 66
ARM64_TLBI_RVAE2 = 67
ARM64_TLBI_RVALE2 = 68
ARM64_TLBI_RVAE2IS = 69
ARM64_TLBI_RVALE2IS = 70
ARM64_TLBI_RVAE2OS = 71
ARM64_TLBI_RVALE2OS = 72
ARM64_TLBI_RVAE3 = 73
ARM64_TLBI_RVALE3 = 74
ARM64_TLBI_RVAE3IS = 75
ARM64_TLBI_RVALE3IS = 76
ARM64_TLBI_RVAE3OS = 77
ARM64_TLBI_RVALE3OS = 78
ARM64_AT_S1E1R = 79
ARM64_AT_S1E2R = 80
ARM64_AT_S1E3R = 81
ARM64_AT_S1E1W = 82
ARM64_AT_S1E2W = 83
ARM64_AT_S1E3W = 84
ARM64_AT_S1E0R = 85
ARM64_AT_S1E0W = 86
ARM64_AT_S12E1R = 87
ARM64_AT_S12E1W = 88
ARM64_AT_S12E0R = 89
ARM64_AT_S12E0W = 90
ARM64_AT_S1E1RP = 91
ARM64_AT_S1E1WP = 92
ARM64_DC_INVALID = 0
ARM64_DC_ZVA = 1
ARM64_DC_IVAC = 2
ARM64_DC_ISW = 3
ARM64_DC_CVAC = 4
ARM64_DC_CSW = 5
ARM64_DC_CVAU = 6
ARM64_DC_CIVAC = 7
ARM64_DC_CISW = 8
ARM64_DC_CVAP = 9
ARM64_IC_INVALID = 0
ARM64_IC_IALLUIS = 1
ARM64_IC_IALLU = 2
ARM64_IC_IVAU = 3
ARM64_PRFM_INVALID = 0
ARM64_PRFM_PLDL1KEEP = 0x00+1
ARM64_PRFM_PLDL1STRM = 0x01+1
ARM64_PRFM_PLDL2KEEP = 0x02+1
ARM64_PRFM_PLDL2STRM = 0x03+1
ARM64_PRFM_PLDL3KEEP = 0x04+1
ARM64_PRFM_PLDL3STRM = 0x05+1
ARM64_PRFM_PLIL1KEEP = 0x08+1
ARM64_PRFM_PLIL1STRM = 0x09+1
ARM64_PRFM_PLIL2KEEP = 0x0a+1
ARM64_PRFM_PLIL2STRM = 0x0b+1
ARM64_PRFM_PLIL3KEEP = 0x0c+1
ARM64_PRFM_PLIL3STRM = 0x0d+1
ARM64_PRFM_PSTL1KEEP = 0x10+1
ARM64_PRFM_PSTL1STRM = 0x11+1
ARM64_PRFM_PSTL2KEEP = 0x12+1
ARM64_PRFM_PSTL2STRM = 0x13+1
ARM64_PRFM_PSTL3KEEP = 0x14+1
ARM64_PRFM_PSTL3STRM = 0x15+1
ARM64_REG_INVALID = 0
ARM64_REG_FFR = 1
ARM64_REG_FP = 2
ARM64_REG_LR = 3
ARM64_REG_NZCV = 4
ARM64_REG_SP = 5
ARM64_REG_WSP = 6
ARM64_REG_WZR = 7
ARM64_REG_XZR = 8
ARM64_REG_B0 = 9
ARM64_REG_B1 = 10
ARM64_REG_B2 = 11
ARM64_REG_B3 = 12
ARM64_REG_B4 = 13
ARM64_REG_B5 = 14
ARM64_REG_B6 = 15
ARM64_REG_B7 = 16
ARM64_REG_B8 = 17
ARM64_REG_B9 = 18
ARM64_REG_B10 = 19
ARM64_REG_B11 = 20
ARM64_REG_B12 = 21
ARM64_REG_B13 = 22
ARM64_REG_B14 = 23
ARM64_REG_B15 = 24
ARM64_REG_B16 = 25
ARM64_REG_B17 = 26
ARM64_REG_B18 = 27
ARM64_REG_B19 = 28
ARM64_REG_B20 = 29
ARM64_REG_B21 = 30
ARM64_REG_B22 = 31
ARM64_REG_B23 = 32
ARM64_REG_B24 = 33
ARM64_REG_B25 = 34
ARM64_REG_B26 = 35
ARM64_REG_B27 = 36
ARM64_REG_B28 = 37
ARM64_REG_B29 = 38
ARM64_REG_B30 = 39
ARM64_REG_B31 = 40
ARM64_REG_D0 = 41
ARM64_REG_D1 = 42
ARM64_REG_D2 = 43
ARM64_REG_D3 = 44
ARM64_REG_D4 = 45
ARM64_REG_D5 = 46
ARM64_REG_D6 = 47
ARM64_REG_D7 = 48
ARM64_REG_D8 = 49
ARM64_REG_D9 = 50
ARM64_REG_D10 = 51
ARM64_REG_D11 = 52
ARM64_REG_D12 = 53
ARM64_REG_D13 = 54
ARM64_REG_D14 = 55
ARM64_REG_D15 = 56
ARM64_REG_D16 = 57
ARM64_REG_D17 = 58
ARM64_REG_D18 = 59
ARM64_REG_D19 = 60
ARM64_REG_D20 = 61
ARM64_REG_D21 = 62
ARM64_REG_D22 = 63
ARM64_REG_D23 = 64
ARM64_REG_D24 = 65
ARM64_REG_D25 = 66
ARM64_REG_D26 = 67
ARM64_REG_D27 = 68
ARM64_REG_D28 = 69
ARM64_REG_D29 = 70
ARM64_REG_D30 = 71
ARM64_REG_D31 = 72
ARM64_REG_H0 = 73
ARM64_REG_H1 = 74
ARM64_REG_H2 = 75
ARM64_REG_H3 = 76
ARM64_REG_H4 = 77
ARM64_REG_H5 = 78
ARM64_REG_H6 = 79
ARM64_REG_H7 = 80
ARM64_REG_H8 = 81
ARM64_REG_H9 = 82
ARM64_REG_H10 = 83
ARM64_REG_H11 = 84
ARM64_REG_H12 = 85
ARM64_REG_H13 = 86
ARM64_REG_H14 = 87
ARM64_REG_H15 = 88
ARM64_REG_H16 = 89
ARM64_REG_H17 = 90
ARM64_REG_H18 = 91
ARM64_REG_H19 = 92
ARM64_REG_H20 = 93
ARM64_REG_H21 = 94
ARM64_REG_H22 = 95
ARM64_REG_H23 = 96
ARM64_REG_H24 = 97
ARM64_REG_H25 = 98
ARM64_REG_H26 = 99
ARM64_REG_H27 = 100
ARM64_REG_H28 = 101
ARM64_REG_H29 = 102
ARM64_REG_H30 = 103
ARM64_REG_H31 = 104
ARM64_REG_P0 = 105
ARM64_REG_P1 = 106
ARM64_REG_P2 = 107
ARM64_REG_P3 = 108
ARM64_REG_P4 = 109
ARM64_REG_P5 = 110
ARM64_REG_P6 = 111
ARM64_REG_P7 = 112
ARM64_REG_P8 = 113
ARM64_REG_P9 = 114
ARM64_REG_P10 = 115
ARM64_REG_P11 = 116
ARM64_REG_P12 = 117
ARM64_REG_P13 = 118
ARM64_REG_P14 = 119
ARM64_REG_P15 = 120
ARM64_REG_Q0 = 121
ARM64_REG_Q1 = 122
ARM64_REG_Q2 = 123
ARM64_REG_Q3 = 124
ARM64_REG_Q4 = 125
ARM64_REG_Q5 = 126
ARM64_REG_Q6 = 127
ARM64_REG_Q7 = 128
ARM64_REG_Q8 = 129
ARM64_REG_Q9 = 130
ARM64_REG_Q10 = 131
ARM64_REG_Q11 = 132
ARM64_REG_Q12 = 133
ARM64_REG_Q13 = 134
ARM64_REG_Q14 = 135
ARM64_REG_Q15 = 136
ARM64_REG_Q16 = 137
ARM64_REG_Q17 = 138
ARM64_REG_Q18 = 139
ARM64_REG_Q19 = 140
ARM64_REG_Q20 = 141
ARM64_REG_Q21 = 142
ARM64_REG_Q22 = 143
ARM64_REG_Q23 = 144
ARM64_REG_Q24 = 145
ARM64_REG_Q25 = 146
ARM64_REG_Q26 = 147
ARM64_REG_Q27 = 148
ARM64_REG_Q28 = 149
ARM64_REG_Q29 = 150
ARM64_REG_Q30 = 151
ARM64_REG_Q31 = 152
ARM64_REG_S0 = 153
ARM64_REG_S1 = 154
ARM64_REG_S2 = 155
ARM64_REG_S3 = 156
ARM64_REG_S4 = 157
ARM64_REG_S5 = 158
ARM64_REG_S6 = 159
ARM64_REG_S7 = 160
ARM64_REG_S8 = 161
ARM64_REG_S9 = 162
ARM64_REG_S10 = 163
ARM64_REG_S11 = 164
ARM64_REG_S12 = 165
ARM64_REG_S13 = 166
ARM64_REG_S14 = 167
ARM64_REG_S15 = 168
ARM64_REG_S16 = 169
ARM64_REG_S17 = 170
ARM64_REG_S18 = 171
ARM64_REG_S19 = 172
ARM64_REG_S20 = 173
ARM64_REG_S21 = 174
ARM64_REG_S22 = 175
ARM64_REG_S23 = 176
ARM64_REG_S24 = 177
ARM64_REG_S25 = 178
ARM64_REG_S26 = 179
ARM64_REG_S27 = 180
ARM64_REG_S28 = 181
ARM64_REG_S29 = 182
ARM64_REG_S30 = 183
ARM64_REG_S31 = 184
ARM64_REG_W0 = 185
ARM64_REG_W1 = 186
ARM64_REG_W2 = 187
ARM64_REG_W3 = 188
ARM64_REG_W4 = 189
ARM64_REG_W5 = 190
ARM64_REG_W6 = 191
ARM64_REG_W7 = 192
ARM64_REG_W8 = 193
ARM64_REG_W9 = 194
ARM64_REG_W10 = 195
ARM64_REG_W11 = 196
ARM64_REG_W12 = 197
ARM64_REG_W13 = 198
ARM64_REG_W14 = 199
ARM64_REG_W15 = 200
ARM64_REG_W16 = 201
ARM64_REG_W17 = 202
ARM64_REG_W18 = 203
ARM64_REG_W19 = 204
ARM64_REG_W20 = 205
ARM64_REG_W21 = 206
ARM64_REG_W22 = 207
ARM64_REG_W23 = 208
ARM64_REG_W24 = 209
ARM64_REG_W25 = 210
ARM64_REG_W26 = 211
ARM64_REG_W27 = 212
ARM64_REG_W28 = 213
ARM64_REG_W29 = 214
ARM64_REG_W30 = 215
ARM64_REG_X0 = 216
ARM64_REG_X1 = 217
ARM64_REG_X2 = 218
ARM64_REG_X3 = 219
ARM64_REG_X4 = 220
ARM64_REG_X5 = 221
ARM64_REG_X6 = 222
ARM64_REG_X7 = 223
ARM64_REG_X8 = 224
ARM64_REG_X9 = 225
ARM64_REG_X10 = 226
ARM64_REG_X11 = 227
ARM64_REG_X12 = 228
ARM64_REG_X13 = 229
ARM64_REG_X14 = 230
ARM64_REG_X15 = 231
ARM64_REG_X16 = 232
ARM64_REG_X17 = 233
ARM64_REG_X18 = 234
ARM64_REG_X19 = 235
ARM64_REG_X20 = 236
ARM64_REG_X21 = 237
ARM64_REG_X22 = 238
ARM64_REG_X23 = 239
ARM64_REG_X24 = 240
ARM64_REG_X25 = 241
ARM64_REG_X26 = 242
ARM64_REG_X27 = 243
ARM64_REG_X28 = 244
ARM64_REG_Z0 = 245
ARM64_REG_Z1 = 246
ARM64_REG_Z2 = 247
ARM64_REG_Z3 = 248
ARM64_REG_Z4 = 249
ARM64_REG_Z5 = 250
ARM64_REG_Z6 = 251
ARM64_REG_Z7 = 252
ARM64_REG_Z8 = 253
ARM64_REG_Z9 = 254
ARM64_REG_Z10 = 255
ARM64_REG_Z11 = 256
ARM64_REG_Z12 = 257
ARM64_REG_Z13 = 258
ARM64_REG_Z14 = 259
ARM64_REG_Z15 = 260
ARM64_REG_Z16 = 261
ARM64_REG_Z17 = 262
ARM64_REG_Z18 = 263
ARM64_REG_Z19 = 264
ARM64_REG_Z20 = 265
ARM64_REG_Z21 = 266
ARM64_REG_Z22 = 267
ARM64_REG_Z23 = 268
ARM64_REG_Z24 = 269
ARM64_REG_Z25 = 270
ARM64_REG_Z26 = 271
ARM64_REG_Z27 = 272
ARM64_REG_Z28 = 273
ARM64_REG_Z29 = 274
ARM64_REG_Z30 = 275
ARM64_REG_Z31 = 276
ARM64_REG_V0 = 277
ARM64_REG_V1 = 278
ARM64_REG_V2 = 279
ARM64_REG_V3 = 280
ARM64_REG_V4 = 281
ARM64_REG_V5 = 282
ARM64_REG_V6 = 283
ARM64_REG_V7 = 284
ARM64_REG_V8 = 285
ARM64_REG_V9 = 286
ARM64_REG_V10 = 287
ARM64_REG_V11 = 288
ARM64_REG_V12 = 289
ARM64_REG_V13 = 290
ARM64_REG_V14 = 291
ARM64_REG_V15 = 292
ARM64_REG_V16 = 293
ARM64_REG_V17 = 294
ARM64_REG_V18 = 295
ARM64_REG_V19 = 296
ARM64_REG_V20 = 297
ARM64_REG_V21 = 298
ARM64_REG_V22 = 299
ARM64_REG_V23 = 300
ARM64_REG_V24 = 301
ARM64_REG_V25 = 302
ARM64_REG_V26 = 303
ARM64_REG_V27 = 304
ARM64_REG_V28 = 305
ARM64_REG_V29 = 306
ARM64_REG_V30 = 307
ARM64_REG_V31 = 308
ARM64_REG_ENDING = 309
ARM64_REG_IP0 = ARM64_REG_X16
ARM64_REG_IP1 = ARM64_REG_X17
ARM64_REG_X29 = ARM64_REG_FP
ARM64_REG_X30 = ARM64_REG_LR
ARM64_INS_INVALID = 0
ARM64_INS_ABS = 1
ARM64_INS_ADC = 2
ARM64_INS_ADCS = 3
ARM64_INS_ADD = 4
ARM64_INS_ADDHN = 5
ARM64_INS_ADDHN2 = 6
ARM64_INS_ADDP = 7
ARM64_INS_ADDPL = 8
ARM64_INS_ADDS = 9
ARM64_INS_ADDV = 10
ARM64_INS_ADDVL = 11
ARM64_INS_ADR = 12
ARM64_INS_ADRP = 13
ARM64_INS_AESD = 14
ARM64_INS_AESE = 15
ARM64_INS_AESIMC = 16
ARM64_INS_AESMC = 17
ARM64_INS_AND = 18
ARM64_INS_ANDS = 19
ARM64_INS_ANDV = 20
ARM64_INS_ASR = 21
ARM64_INS_ASRD = 22
ARM64_INS_ASRR = 23
ARM64_INS_ASRV = 24
ARM64_INS_AUTDA = 25
ARM64_INS_AUTDB = 26
ARM64_INS_AUTDZA = 27
ARM64_INS_AUTDZB = 28
ARM64_INS_AUTIA = 29
ARM64_INS_AUTIA1716 = 30
ARM64_INS_AUTIASP = 31
ARM64_INS_AUTIAZ = 32
ARM64_INS_AUTIB = 33
ARM64_INS_AUTIB1716 = 34
ARM64_INS_AUTIBSP = 35
ARM64_INS_AUTIBZ = 36
ARM64_INS_AUTIZA = 37
ARM64_INS_AUTIZB = 38
ARM64_INS_B = 39
ARM64_INS_BCAX = 40
ARM64_INS_BFM = 41
ARM64_INS_BIC = 42
ARM64_INS_BICS = 43
ARM64_INS_BIF = 44
ARM64_INS_BIT = 45
ARM64_INS_BL = 46
ARM64_INS_BLR = 47
ARM64_INS_BLRAA = 48
ARM64_INS_BLRAAZ = 49
ARM64_INS_BLRAB = 50
ARM64_INS_BLRABZ = 51
ARM64_INS_BR = 52
ARM64_INS_BRAA = 53
ARM64_INS_BRAAZ = 54
ARM64_INS_BRAB = 55
ARM64_INS_BRABZ = 56
ARM64_INS_BRK = 57
ARM64_INS_BRKA = 58
ARM64_INS_BRKAS = 59
ARM64_INS_BRKB = 60
ARM64_INS_BRKBS = 61
ARM64_INS_BRKN = 62
ARM64_INS_BRKNS = 63
ARM64_INS_BRKPA = 64
ARM64_INS_BRKPAS = 65
ARM64_INS_BRKPB = 66
ARM64_INS_BRKPBS = 67
ARM64_INS_BSL = 68
ARM64_INS_CAS = 69
ARM64_INS_CASA = 70
ARM64_INS_CASAB = 71
ARM64_INS_CASAH = 72
ARM64_INS_CASAL = 73
ARM64_INS_CASALB = 74
ARM64_INS_CASALH = 75
ARM64_INS_CASB = 76
ARM64_INS_CASH = 77
ARM64_INS_CASL = 78
ARM64_INS_CASLB = 79
ARM64_INS_CASLH = 80
ARM64_INS_CASP = 81
ARM64_INS_CASPA = 82
ARM64_INS_CASPAL = 83
ARM64_INS_CASPL = 84
ARM64_INS_CBNZ = 85
ARM64_INS_CBZ = 86
ARM64_INS_CCMN = 87
ARM64_INS_CCMP = 88
ARM64_INS_CFINV = 89
ARM64_INS_CINC = 90
ARM64_INS_CINV = 91
ARM64_INS_CLASTA = 92
ARM64_INS_CLASTB = 93
ARM64_INS_CLREX = 94
ARM64_INS_CLS = 95
ARM64_INS_CLZ = 96
ARM64_INS_CMEQ = 97
ARM64_INS_CMGE = 98
ARM64_INS_CMGT = 99
ARM64_INS_CMHI = 100
ARM64_INS_CMHS = 101
ARM64_INS_CMLE = 102
ARM64_INS_CMLO = 103
ARM64_INS_CMLS = 104
ARM64_INS_CMLT = 105
ARM64_INS_CMN = 106
ARM64_INS_CMP = 107
ARM64_INS_CMPEQ = 108
ARM64_INS_CMPGE = 109
ARM64_INS_CMPGT = 110
ARM64_INS_CMPHI = 111
ARM64_INS_CMPHS = 112
ARM64_INS_CMPLE = 113
ARM64_INS_CMPLO = 114
ARM64_INS_CMPLS = 115
ARM64_INS_CMPLT = 116
ARM64_INS_CMPNE = 117
ARM64_INS_CMTST = 118
ARM64_INS_CNEG = 119
ARM64_INS_CNOT = 120
ARM64_INS_CNT = 121
ARM64_INS_CNTB = 122
ARM64_INS_CNTD = 123
ARM64_INS_CNTH = 124
ARM64_INS_CNTP = 125
ARM64_INS_CNTW = 126
ARM64_INS_COMPACT = 127
ARM64_INS_CPY = 128
ARM64_INS_CRC32B = 129
ARM64_INS_CRC32CB = 130
ARM64_INS_CRC32CH = 131
ARM64_INS_CRC32CW = 132
ARM64_INS_CRC32CX = 133
ARM64_INS_CRC32H = 134
ARM64_INS_CRC32W = 135
ARM64_INS_CRC32X = 136
ARM64_INS_CSDB = 137
ARM64_INS_CSEL = 138
ARM64_INS_CSET = 139
ARM64_INS_CSETM = 140
ARM64_INS_CSINC = 141
ARM64_INS_CSINV = 142
ARM64_INS_CSNEG = 143
ARM64_INS_CTERMEQ = 144
ARM64_INS_CTERMNE = 145
ARM64_INS_DCPS1 = 146
ARM64_INS_DCPS2 = 147
ARM64_INS_DCPS3 = 148
ARM64_INS_DECB = 149
ARM64_INS_DECD = 150
ARM64_INS_DECH = 151
ARM64_INS_DECP = 152
ARM64_INS_DECW = 153
ARM64_INS_DMB = 154
ARM64_INS_DRPS = 155
ARM64_INS_DSB = 156
ARM64_INS_DUP = 157
ARM64_INS_DUPM = 158
ARM64_INS_EON = 159
ARM64_INS_EOR = 160
ARM64_INS_EOR3 = 161
ARM64_INS_EORS = 162
ARM64_INS_EORV = 163
ARM64_INS_ERET = 164
ARM64_INS_ERETAA = 165
ARM64_INS_ERETAB = 166
ARM64_INS_ESB = 167
ARM64_INS_EXT = 168
ARM64_INS_EXTR = 169
ARM64_INS_FABD = 170
ARM64_INS_FABS = 171
ARM64_INS_FACGE = 172
ARM64_INS_FACGT = 173
ARM64_INS_FACLE = 174
ARM64_INS_FACLT = 175
ARM64_INS_FADD = 176
ARM64_INS_FADDA = 177
ARM64_INS_FADDP = 178
ARM64_INS_FADDV = 179
ARM64_INS_FCADD = 180
ARM64_INS_FCCMP = 181
ARM64_INS_FCCMPE = 182
ARM64_INS_FCMEQ = 183
ARM64_INS_FCMGE = 184
ARM64_INS_FCMGT = 185
ARM64_INS_FCMLA = 186
ARM64_INS_FCMLE = 187
ARM64_INS_FCMLT = 188
ARM64_INS_FCMNE = 189
ARM64_INS_FCMP = 190
ARM64_INS_FCMPE = 191
ARM64_INS_FCMUO = 192
ARM64_INS_FCPY = 193
ARM64_INS_FCSEL = 194
ARM64_INS_FCVT = 195
ARM64_INS_FCVTAS = 196
ARM64_INS_FCVTAU = 197
ARM64_INS_FCVTL = 198
ARM64_INS_FCVTL2 = 199
ARM64_INS_FCVTMS = 200
ARM64_INS_FCVTMU = 201
ARM64_INS_FCVTN = 202
ARM64_INS_FCVTN2 = 203
ARM64_INS_FCVTNS = 204
ARM64_INS_FCVTNU = 205
ARM64_INS_FCVTPS = 206
ARM64_INS_FCVTPU = 207
ARM64_INS_FCVTXN = 208
ARM64_INS_FCVTXN2 = 209
ARM64_INS_FCVTZS = 210
ARM64_INS_FCVTZU = 211
ARM64_INS_FDIV = 212
ARM64_INS_FDIVR = 213
ARM64_INS_FDUP = 214
ARM64_INS_FEXPA = 215
ARM64_INS_FJCVTZS = 216
ARM64_INS_FMAD = 217
ARM64_INS_FMADD = 218
ARM64_INS_FMAX = 219
ARM64_INS_FMAXNM = 220
ARM64_INS_FMAXNMP = 221
ARM64_INS_FMAXNMV = 222
ARM64_INS_FMAXP = 223
ARM64_INS_FMAXV = 224
ARM64_INS_FMIN = 225
ARM64_INS_FMINNM = 226
ARM64_INS_FMINNMP = 227
ARM64_INS_FMINNMV = 228
ARM64_INS_FMINP = 229
ARM64_INS_FMINV = 230
ARM64_INS_FMLA = 231
ARM64_INS_FMLS = 232
ARM64_INS_FMOV = 233
ARM64_INS_FMSB = 234
ARM64_INS_FMSUB = 235
ARM64_INS_FMUL = 236
ARM64_INS_FMULX = 237
ARM64_INS_FNEG = 238
ARM64_INS_FNMAD = 239
ARM64_INS_FNMADD = 240
ARM64_INS_FNMLA = 241
ARM64_INS_FNMLS = 242
ARM64_INS_FNMSB = 243
ARM64_INS_FNMSUB = 244
ARM64_INS_FNMUL = 245
ARM64_INS_FRECPE = 246
ARM64_INS_FRECPS = 247
ARM64_INS_FRECPX = 248
ARM64_INS_FRINTA = 249
ARM64_INS_FRINTI = 250
ARM64_INS_FRINTM = 251
ARM64_INS_FRINTN = 252
ARM64_INS_FRINTP = 253
ARM64_INS_FRINTX = 254
ARM64_INS_FRINTZ = 255
ARM64_INS_FRSQRTE = 256
ARM64_INS_FRSQRTS = 257
ARM64_INS_FSCALE = 258
ARM64_INS_FSQRT = 259
ARM64_INS_FSUB = 260
ARM64_INS_FSUBR = 261
ARM64_INS_FTMAD = 262
ARM64_INS_FTSMUL = 263
ARM64_INS_FTSSEL = 264
ARM64_INS_HINT = 265
ARM64_INS_HLT = 266
ARM64_INS_HVC = 267
ARM64_INS_INCB = 268
ARM64_INS_INCD = 269
ARM64_INS_INCH = 270
ARM64_INS_INCP = 271
ARM64_INS_INCW = 272
ARM64_INS_INDEX = 273
ARM64_INS_INS = 274
ARM64_INS_INSR = 275
ARM64_INS_ISB = 276
ARM64_INS_LASTA = 277
ARM64_INS_LASTB = 278
ARM64_INS_LD1 = 279
ARM64_INS_LD1B = 280
ARM64_INS_LD1D = 281
ARM64_INS_LD1H = 282
ARM64_INS_LD1R = 283
ARM64_INS_LD1RB = 284
ARM64_INS_LD1RD = 285
ARM64_INS_LD1RH = 286
ARM64_INS_LD1RQB = 287
ARM64_INS_LD1RQD = 288
ARM64_INS_LD1RQH = 289
ARM64_INS_LD1RQW = 290
ARM64_INS_LD1RSB = 291
ARM64_INS_LD1RSH = 292
ARM64_INS_LD1RSW = 293
ARM64_INS_LD1RW = 294
ARM64_INS_LD1SB = 295
ARM64_INS_LD1SH = 296
ARM64_INS_LD1SW = 297
ARM64_INS_LD1W = 298
ARM64_INS_LD2 = 299
ARM64_INS_LD2B = 300
ARM64_INS_LD2D = 301
ARM64_INS_LD2H = 302
ARM64_INS_LD2R = 303
ARM64_INS_LD2W = 304
ARM64_INS_LD3 = 305
ARM64_INS_LD3B = 306
ARM64_INS_LD3D = 307
ARM64_INS_LD3H = 308
ARM64_INS_LD3R = 309
ARM64_INS_LD3W = 310
ARM64_INS_LD4 = 311
ARM64_INS_LD4B = 312
ARM64_INS_LD4D = 313
ARM64_INS_LD4H = 314
ARM64_INS_LD4R = 315
ARM64_INS_LD4W = 316
ARM64_INS_LDADD = 317
ARM64_INS_LDADDA = 318
ARM64_INS_LDADDAB = 319
ARM64_INS_LDADDAH = 320
ARM64_INS_LDADDAL = 321
ARM64_INS_LDADDALB = 322
ARM64_INS_LDADDALH = 323
ARM64_INS_LDADDB = 324
ARM64_INS_LDADDH = 325
ARM64_INS_LDADDL = 326
ARM64_INS_LDADDLB = 327
ARM64_INS_LDADDLH = 328
ARM64_INS_LDAPR = 329
ARM64_INS_LDAPRB = 330
ARM64_INS_LDAPRH = 331
ARM64_INS_LDAPUR = 332
ARM64_INS_LDAPURB = 333
ARM64_INS_LDAPURH = 334
ARM64_INS_LDAPURSB = 335
ARM64_INS_LDAPURSH = 336
ARM64_INS_LDAPURSW = 337
ARM64_INS_LDAR = 338
ARM64_INS_LDARB = 339
ARM64_INS_LDARH = 340
ARM64_INS_LDAXP = 341
ARM64_INS_LDAXR = 342
ARM64_INS_LDAXRB = 343
ARM64_INS_LDAXRH = 344
ARM64_INS_LDCLR = 345
ARM64_INS_LDCLRA = 346
ARM64_INS_LDCLRAB = 347
ARM64_INS_LDCLRAH = 348
ARM64_INS_LDCLRAL = 349
ARM64_INS_LDCLRALB = 350
ARM64_INS_LDCLRALH = 351
ARM64_INS_LDCLRB = 352
ARM64_INS_LDCLRH = 353
ARM64_INS_LDCLRL = 354
ARM64_INS_LDCLRLB = 355
ARM64_INS_LDCLRLH = 356
ARM64_INS_LDEOR = 357
ARM64_INS_LDEORA = 358
ARM64_INS_LDEORAB = 359
ARM64_INS_LDEORAH = 360
ARM64_INS_LDEORAL = 361
ARM64_INS_LDEORALB = 362
ARM64_INS_LDEORALH = 363
ARM64_INS_LDEORB = 364
ARM64_INS_LDEORH = 365
ARM64_INS_LDEORL = 366
ARM64_INS_LDEORLB = 367
ARM64_INS_LDEORLH = 368
ARM64_INS_LDFF1B = 369
ARM64_INS_LDFF1D = 370
ARM64_INS_LDFF1H = 371
ARM64_INS_LDFF1SB = 372
ARM64_INS_LDFF1SH = 373
ARM64_INS_LDFF1SW = 374
ARM64_INS_LDFF1W = 375
ARM64_INS_LDLAR = 376
ARM64_INS_LDLARB = 377
ARM64_INS_LDLARH = 378
ARM64_INS_LDNF1B = 379
ARM64_INS_LDNF1D = 380
ARM64_INS_LDNF1H = 381
ARM64_INS_LDNF1SB = 382
ARM64_INS_LDNF1SH = 383
ARM64_INS_LDNF1SW = 384
ARM64_INS_LDNF1W = 385
ARM64_INS_LDNP = 386
ARM64_INS_LDNT1B = 387
ARM64_INS_LDNT1D = 388
ARM64_INS_LDNT1H = 389
ARM64_INS_LDNT1W = 390
ARM64_INS_LDP = 391
ARM64_INS_LDPSW = 392
ARM64_INS_LDR = 393
ARM64_INS_LDRAA = 394
ARM64_INS_LDRAB = 395
ARM64_INS_LDRB = 396
ARM64_INS_LDRH = 397
ARM64_INS_LDRSB = 398
ARM64_INS_LDRSH = 399
ARM64_INS_LDRSW = 400
ARM64_INS_LDSET = 401
ARM64_INS_LDSETA = 402
ARM64_INS_LDSETAB = 403
ARM64_INS_LDSETAH = 404
ARM64_INS_LDSETAL = 405
ARM64_INS_LDSETALB = 406
ARM64_INS_LDSETALH = 407
ARM64_INS_LDSETB = 408
ARM64_INS_LDSETH = 409
ARM64_INS_LDSETL = 410
ARM64_INS_LDSETLB = 411
ARM64_INS_LDSETLH = 412
ARM64_INS_LDSMAX = 413
ARM64_INS_LDSMAXA = 414
ARM64_INS_LDSMAXAB = 415
ARM64_INS_LDSMAXAH = 416
ARM64_INS_LDSMAXAL = 417
ARM64_INS_LDSMAXALB = 418
ARM64_INS_LDSMAXALH = 419
ARM64_INS_LDSMAXB = 420
ARM64_INS_LDSMAXH = 421
ARM64_INS_LDSMAXL = 422
ARM64_INS_LDSMAXLB = 423
ARM64_INS_LDSMAXLH = 424
ARM64_INS_LDSMIN = 425
ARM64_INS_LDSMINA = 426
ARM64_INS_LDSMINAB = 427
ARM64_INS_LDSMINAH = 428
ARM64_INS_LDSMINAL = 429
ARM64_INS_LDSMINALB = 430
ARM64_INS_LDSMINALH = 431
ARM64_INS_LDSMINB = 432
ARM64_INS_LDSMINH = 433
ARM64_INS_LDSMINL = 434
ARM64_INS_LDSMINLB = 435
ARM64_INS_LDSMINLH = 436
ARM64_INS_LDTR = 437
ARM64_INS_LDTRB = 438
ARM64_INS_LDTRH = 439
ARM64_INS_LDTRSB = 440
ARM64_INS_LDTRSH = 441
ARM64_INS_LDTRSW = 442
ARM64_INS_LDUMAX = 443
ARM64_INS_LDUMAXA = 444
ARM64_INS_LDUMAXAB = 445
ARM64_INS_LDUMAXAH = 446
ARM64_INS_LDUMAXAL = 447
ARM64_INS_LDUMAXALB = 448
ARM64_INS_LDUMAXALH = 449
ARM64_INS_LDUMAXB = 450
ARM64_INS_LDUMAXH = 451
ARM64_INS_LDUMAXL = 452
ARM64_INS_LDUMAXLB = 453
ARM64_INS_LDUMAXLH = 454
ARM64_INS_LDUMIN = 455
ARM64_INS_LDUMINA = 456
ARM64_INS_LDUMINAB = 457
ARM64_INS_LDUMINAH = 458
ARM64_INS_LDUMINAL = 459
ARM64_INS_LDUMINALB = 460
ARM64_INS_LDUMINALH = 461
ARM64_INS_LDUMINB = 462
ARM64_INS_LDUMINH = 463
ARM64_INS_LDUMINL = 464
ARM64_INS_LDUMINLB = 465
ARM64_INS_LDUMINLH = 466
ARM64_INS_LDUR = 467
ARM64_INS_LDURB = 468
ARM64_INS_LDURH = 469
ARM64_INS_LDURSB = 470
ARM64_INS_LDURSH = 471
ARM64_INS_LDURSW = 472
ARM64_INS_LDXP = 473
ARM64_INS_LDXR = 474
ARM64_INS_LDXRB = 475
ARM64_INS_LDXRH = 476
ARM64_INS_LSL = 477
ARM64_INS_LSLR = 478
ARM64_INS_LSLV = 479
ARM64_INS_LSR = 480
ARM64_INS_LSRR = 481
ARM64_INS_LSRV = 482
ARM64_INS_MAD = 483
ARM64_INS_MADD = 484
ARM64_INS_MLA = 485
ARM64_INS_MLS = 486
ARM64_INS_MNEG = 487
ARM64_INS_MOV = 488
ARM64_INS_MOVI = 489
ARM64_INS_MOVK = 490
ARM64_INS_MOVN = 491
ARM64_INS_MOVPRFX = 492
ARM64_INS_MOVS = 493
ARM64_INS_MOVZ = 494
ARM64_INS_MRS = 495
ARM64_INS_MSB = 496
ARM64_INS_MSR = 497
ARM64_INS_MSUB = 498
ARM64_INS_MUL = 499
ARM64_INS_MVN = 500
ARM64_INS_MVNI = 501
ARM64_INS_NAND = 502
ARM64_INS_NANDS = 503
ARM64_INS_NEG = 504
ARM64_INS_NEGS = 505
ARM64_INS_NGC = 506
ARM64_INS_NGCS = 507
ARM64_INS_NOP = 508
ARM64_INS_NOR = 509
ARM64_INS_NORS = 510
ARM64_INS_NOT = 511
ARM64_INS_NOTS = 512
ARM64_INS_ORN = 513
ARM64_INS_ORNS = 514
ARM64_INS_ORR = 515
ARM64_INS_ORRS = 516
ARM64_INS_ORV = 517
ARM64_INS_PACDA = 518
ARM64_INS_PACDB = 519
ARM64_INS_PACDZA = 520
ARM64_INS_PACDZB = 521
ARM64_INS_PACGA = 522
ARM64_INS_PACIA = 523
ARM64_INS_PACIA1716 = 524
ARM64_INS_PACIASP = 525
ARM64_INS_PACIAZ = 526
ARM64_INS_PACIB = 527
ARM64_INS_PACIB1716 = 528
ARM64_INS_PACIBSP = 529
ARM64_INS_PACIBZ = 530
ARM64_INS_PACIZA = 531
ARM64_INS_PACIZB = 532
ARM64_INS_PFALSE = 533
ARM64_INS_PFIRST = 534
ARM64_INS_PMUL = 535
ARM64_INS_PMULL = 536
ARM64_INS_PMULL2 = 537
ARM64_INS_PNEXT = 538
ARM64_INS_PRFB = 539
ARM64_INS_PRFD = 540
ARM64_INS_PRFH = 541
ARM64_INS_PRFM = 542
ARM64_INS_PRFUM = 543
ARM64_INS_PRFW = 544
ARM64_INS_PSB = 545
ARM64_INS_PTEST = 546
ARM64_INS_PTRUE = 547
ARM64_INS_PTRUES = 548
ARM64_INS_PUNPKHI = 549
ARM64_INS_PUNPKLO = 550
ARM64_INS_RADDHN = 551
ARM64_INS_RADDHN2 = 552
ARM64_INS_RAX1 = 553
ARM64_INS_RBIT = 554
ARM64_INS_RDFFR = 555
ARM64_INS_RDFFRS = 556
ARM64_INS_RDVL = 557
ARM64_INS_RET = 558
ARM64_INS_RETAA = 559
ARM64_INS_RETAB = 560
ARM64_INS_REV = 561
ARM64_INS_REV16 = 562
ARM64_INS_REV32 = 563
ARM64_INS_REV64 = 564
ARM64_INS_REVB = 565
ARM64_INS_REVH = 566
ARM64_INS_REVW = 567
ARM64_INS_RMIF = 568
ARM64_INS_ROR = 569
ARM64_INS_RORV = 570
ARM64_INS_RSHRN = 571
ARM64_INS_RSHRN2 = 572
ARM64_INS_RSUBHN = 573
ARM64_INS_RSUBHN2 = 574
ARM64_INS_SABA = 575
ARM64_INS_SABAL = 576
ARM64_INS_SABAL2 = 577
ARM64_INS_SABD = 578
ARM64_INS_SABDL = 579
ARM64_INS_SABDL2 = 580
ARM64_INS_SADALP = 581
ARM64_INS_SADDL = 582
ARM64_INS_SADDL2 = 583
ARM64_INS_SADDLP = 584
ARM64_INS_SADDLV = 585
ARM64_INS_SADDV = 586
ARM64_INS_SADDW = 587
ARM64_INS_SADDW2 = 588
ARM64_INS_SBC = 589
ARM64_INS_SBCS = 590
ARM64_INS_SBFM = 591
ARM64_INS_SCVTF = 592
ARM64_INS_SDIV = 593
ARM64_INS_SDIVR = 594
ARM64_INS_SDOT = 595
ARM64_INS_SEL = 596
ARM64_INS_SETF16 = 597
ARM64_INS_SETF8 = 598
ARM64_INS_SETFFR = 599
ARM64_INS_SEV = 600
ARM64_INS_SEVL = 601
ARM64_INS_SHA1C = 602
ARM64_INS_SHA1H = 603
ARM64_INS_SHA1M = 604
ARM64_INS_SHA1P = 605
ARM64_INS_SHA1SU0 = 606
ARM64_INS_SHA1SU1 = 607
ARM64_INS_SHA256H = 608
ARM64_INS_SHA256H2 = 609
ARM64_INS_SHA256SU0 = 610
ARM64_INS_SHA256SU1 = 611
ARM64_INS_SHA512H = 612
ARM64_INS_SHA512H2 = 613
ARM64_INS_SHA512SU0 = 614
ARM64_INS_SHA512SU1 = 615
ARM64_INS_SHADD = 616
ARM64_INS_SHL = 617
ARM64_INS_SHLL = 618
ARM64_INS_SHLL2 = 619
ARM64_INS_SHRN = 620
ARM64_INS_SHRN2 = 621
ARM64_INS_SHSUB = 622
ARM64_INS_SLI = 623
ARM64_INS_SM3PARTW1 = 624
ARM64_INS_SM3PARTW2 = 625
ARM64_INS_SM3SS1 = 626
ARM64_INS_SM3TT1A = 627
ARM64_INS_SM3TT1B = 628
ARM64_INS_SM3TT2A = 629
ARM64_INS_SM3TT2B = 630
ARM64_INS_SM4E = 631
ARM64_INS_SM4EKEY = 632
ARM64_INS_SMADDL = 633
ARM64_INS_SMAX = 634
ARM64_INS_SMAXP = 635
ARM64_INS_SMAXV = 636
ARM64_INS_SMC = 637
ARM64_INS_SMIN = 638
ARM64_INS_SMINP = 639
ARM64_INS_SMINV = 640
ARM64_INS_SMLAL = 641
ARM64_INS_SMLAL2 = 642
ARM64_INS_SMLSL = 643
ARM64_INS_SMLSL2 = 644
ARM64_INS_SMNEGL = 645
ARM64_INS_SMOV = 646
ARM64_INS_SMSUBL = 647
ARM64_INS_SMULH = 648
ARM64_INS_SMULL = 649
ARM64_INS_SMULL2 = 650
ARM64_INS_SPLICE = 651
ARM64_INS_SQABS = 652
ARM64_INS_SQADD = 653
ARM64_INS_SQDECB = 654
ARM64_INS_SQDECD = 655
ARM64_INS_SQDECH = 656
ARM64_INS_SQDECP = 657
ARM64_INS_SQDECW = 658
ARM64_INS_SQDMLAL = 659
ARM64_INS_SQDMLAL2 = 660
ARM64_INS_SQDMLSL = 661
ARM64_INS_SQDMLSL2 = 662
ARM64_INS_SQDMULH = 663
ARM64_INS_SQDMULL = 664
ARM64_INS_SQDMULL2 = 665
ARM64_INS_SQINCB = 666
ARM64_INS_SQINCD = 667
ARM64_INS_SQINCH = 668
ARM64_INS_SQINCP = 669
ARM64_INS_SQINCW = 670
ARM64_INS_SQNEG = 671
ARM64_INS_SQRDMLAH = 672
ARM64_INS_SQRDMLSH = 673
ARM64_INS_SQRDMULH = 674
ARM64_INS_SQRSHL = 675
ARM64_INS_SQRSHRN = 676
ARM64_INS_SQRSHRN2 = 677
ARM64_INS_SQRSHRUN = 678
ARM64_INS_SQRSHRUN2 = 679
ARM64_INS_SQSHL = 680
ARM64_INS_SQSHLU = 681
ARM64_INS_SQSHRN = 682
ARM64_INS_SQSHRN2 = 683
ARM64_INS_SQSHRUN = 684
ARM64_INS_SQSHRUN2 = 685
ARM64_INS_SQSUB = 686
ARM64_INS_SQXTN = 687
ARM64_INS_SQXTN2 = 688
ARM64_INS_SQXTUN = 689
ARM64_INS_SQXTUN2 = 690
ARM64_INS_SRHADD = 691
ARM64_INS_SRI = 692
ARM64_INS_SRSHL = 693
ARM64_INS_SRSHR = 694
ARM64_INS_SRSRA = 695
ARM64_INS_SSHL = 696
ARM64_INS_SSHLL = 697
ARM64_INS_SSHLL2 = 698
ARM64_INS_SSHR = 699
ARM64_INS_SSRA = 700
ARM64_INS_SSUBL = 701
ARM64_INS_SSUBL2 = 702
ARM64_INS_SSUBW = 703
ARM64_INS_SSUBW2 = 704
ARM64_INS_ST1 = 705
ARM64_INS_ST1B = 706
ARM64_INS_ST1D = 707
ARM64_INS_ST1H = 708
ARM64_INS_ST1W = 709
ARM64_INS_ST2 = 710
ARM64_INS_ST2B = 711
ARM64_INS_ST2D = 712
ARM64_INS_ST2H = 713
ARM64_INS_ST2W = 714
ARM64_INS_ST3 = 715
ARM64_INS_ST3B = 716
ARM64_INS_ST3D = 717
ARM64_INS_ST3H = 718
ARM64_INS_ST3W = 719
ARM64_INS_ST4 = 720
ARM64_INS_ST4B = 721
ARM64_INS_ST4D = 722
ARM64_INS_ST4H = 723
ARM64_INS_ST4W = 724
ARM64_INS_STADD = 725
ARM64_INS_STADDB = 726
ARM64_INS_STADDH = 727
ARM64_INS_STADDL = 728
ARM64_INS_STADDLB = 729
ARM64_INS_STADDLH = 730
ARM64_INS_STCLR = 731
ARM64_INS_STCLRB = 732
ARM64_INS_STCLRH = 733
ARM64_INS_STCLRL = 734
ARM64_INS_STCLRLB = 735
ARM64_INS_STCLRLH = 736
ARM64_INS_STEOR = 737
ARM64_INS_STEORB = 738
ARM64_INS_STEORH = 739
ARM64_INS_STEORL = 740
ARM64_INS_STEORLB = 741
ARM64_INS_STEORLH = 742
ARM64_INS_STLLR = 743
ARM64_INS_STLLRB = 744
ARM64_INS_STLLRH = 745
ARM64_INS_STLR = 746
ARM64_INS_STLRB = 747
ARM64_INS_STLRH = 748
ARM64_INS_STLUR = 749
ARM64_INS_STLURB = 750
ARM64_INS_STLURH = 751
ARM64_INS_STLXP = 752
ARM64_INS_STLXR = 753
ARM64_INS_STLXRB = 754
ARM64_INS_STLXRH = 755
ARM64_INS_STNP = 756
ARM64_INS_STNT1B = 757
ARM64_INS_STNT1D = 758
ARM64_INS_STNT1H = 759
ARM64_INS_STNT1W = 760
ARM64_INS_STP = 761
ARM64_INS_STR = 762
ARM64_INS_STRB = 763
ARM64_INS_STRH = 764
ARM64_INS_STSET = 765
ARM64_INS_STSETB = 766
ARM64_INS_STSETH = 767
ARM64_INS_STSETL = 768
ARM64_INS_STSETLB = 769
ARM64_INS_STSETLH = 770
ARM64_INS_STSMAX = 771
ARM64_INS_STSMAXB = 772
ARM64_INS_STSMAXH = 773
ARM64_INS_STSMAXL = 774
ARM64_INS_STSMAXLB = 775
ARM64_INS_STSMAXLH = 776
ARM64_INS_STSMIN = 777
ARM64_INS_STSMINB = 778
ARM64_INS_STSMINH = 779
ARM64_INS_STSMINL = 780
ARM64_INS_STSMINLB = 781
ARM64_INS_STSMINLH = 782
ARM64_INS_STTR = 783
ARM64_INS_STTRB = 784
ARM64_INS_STTRH = 785
ARM64_INS_STUMAX = 786
ARM64_INS_STUMAXB = 787
ARM64_INS_STUMAXH = 788
ARM64_INS_STUMAXL = 789
ARM64_INS_STUMAXLB = 790
ARM64_INS_STUMAXLH = 791
ARM64_INS_STUMIN = 792
ARM64_INS_STUMINB = 793
ARM64_INS_STUMINH = 794
ARM64_INS_STUMINL = 795
ARM64_INS_STUMINLB = 796
ARM64_INS_STUMINLH = 797
ARM64_INS_STUR = 798
ARM64_INS_STURB = 799
ARM64_INS_STURH = 800
ARM64_INS_STXP = 801
ARM64_INS_STXR = 802
ARM64_INS_STXRB = 803
ARM64_INS_STXRH = 804
ARM64_INS_SUB = 805
ARM64_INS_SUBHN = 806
ARM64_INS_SUBHN2 = 807
ARM64_INS_SUBR = 808
ARM64_INS_SUBS = 809
ARM64_INS_SUNPKHI = 810
ARM64_INS_SUNPKLO = 811
ARM64_INS_SUQADD = 812
ARM64_INS_SVC = 813
ARM64_INS_SWP = 814
ARM64_INS_SWPA = 815
ARM64_INS_SWPAB = 816
ARM64_INS_SWPAH = 817
ARM64_INS_SWPAL = 818
ARM64_INS_SWPALB = 819
ARM64_INS_SWPALH = 820
ARM64_INS_SWPB = 821
ARM64_INS_SWPH = 822
ARM64_INS_SWPL = 823
ARM64_INS_SWPLB = 824
ARM64_INS_SWPLH = 825
ARM64_INS_SXTB = 826
ARM64_INS_SXTH = 827
ARM64_INS_SXTL = 828
ARM64_INS_SXTL2 = 829
ARM64_INS_SXTW = 830
ARM64_INS_SYS = 831
ARM64_INS_SYSL = 832
ARM64_INS_TBL = 833
ARM64_INS_TBNZ = 834
ARM64_INS_TBX = 835
ARM64_INS_TBZ = 836
ARM64_INS_TRN1 = 837
ARM64_INS_TRN2 = 838
ARM64_INS_TSB = 839
ARM64_INS_TST = 840
ARM64_INS_UABA = 841
ARM64_INS_UABAL = 842
ARM64_INS_UABAL2 = 843
ARM64_INS_UABD = 844
ARM64_INS_UABDL = 845
ARM64_INS_UABDL2 = 846
ARM64_INS_UADALP = 847
ARM64_INS_UADDL = 848
ARM64_INS_UADDL2 = 849
ARM64_INS_UADDLP = 850
ARM64_INS_UADDLV = 851
ARM64_INS_UADDV = 852
ARM64_INS_UADDW = 853
ARM64_INS_UADDW2 = 854
ARM64_INS_UBFM = 855
ARM64_INS_UCVTF = 856
ARM64_INS_UDIV = 857
ARM64_INS_UDIVR = 858
ARM64_INS_UDOT = 859
ARM64_INS_UHADD = 860
ARM64_INS_UHSUB = 861
ARM64_INS_UMADDL = 862
ARM64_INS_UMAX = 863
ARM64_INS_UMAXP = 864
ARM64_INS_UMAXV = 865
ARM64_INS_UMIN = 866
ARM64_INS_UMINP = 867
ARM64_INS_UMINV = 868
ARM64_INS_UMLAL = 869
ARM64_INS_UMLAL2 = 870
ARM64_INS_UMLSL = 871
ARM64_INS_UMLSL2 = 872
ARM64_INS_UMNEGL = 873
ARM64_INS_UMOV = 874
ARM64_INS_UMSUBL = 875
ARM64_INS_UMULH = 876
ARM64_INS_UMULL = 877
ARM64_INS_UMULL2 = 878
ARM64_INS_UQADD = 879
ARM64_INS_UQDECB = 880
ARM64_INS_UQDECD = 881
ARM64_INS_UQDECH = 882
ARM64_INS_UQDECP = 883
ARM64_INS_UQDECW = 884
ARM64_INS_UQINCB = 885
ARM64_INS_UQINCD = 886
ARM64_INS_UQINCH = 887
ARM64_INS_UQINCP = 888
ARM64_INS_UQINCW = 889
ARM64_INS_UQRSHL = 890
ARM64_INS_UQRSHRN = 891
ARM64_INS_UQRSHRN2 = 892
ARM64_INS_UQSHL = 893
ARM64_INS_UQSHRN = 894
ARM64_INS_UQSHRN2 = 895
ARM64_INS_UQSUB = 896
ARM64_INS_UQXTN = 897
ARM64_INS_UQXTN2 = 898
ARM64_INS_URECPE = 899
ARM64_INS_URHADD = 900
ARM64_INS_URSHL = 901
ARM64_INS_URSHR = 902
ARM64_INS_URSQRTE = 903
ARM64_INS_URSRA = 904
ARM64_INS_USHL = 905
ARM64_INS_USHLL = 906
ARM64_INS_USHLL2 = 907
ARM64_INS_USHR = 908
ARM64_INS_USQADD = 909
ARM64_INS_USRA = 910
ARM64_INS_USUBL = 911
ARM64_INS_USUBL2 = 912
ARM64_INS_USUBW = 913
ARM64_INS_USUBW2 = 914
ARM64_INS_UUNPKHI = 915
ARM64_INS_UUNPKLO = 916
ARM64_INS_UXTB = 917
ARM64_INS_UXTH = 918
ARM64_INS_UXTL = 919
ARM64_INS_UXTL2 = 920
ARM64_INS_UXTW = 921
ARM64_INS_UZP1 = 922
ARM64_INS_UZP2 = 923
ARM64_INS_WFE = 924
ARM64_INS_WFI = 925
ARM64_INS_WHILELE = 926
ARM64_INS_WHILELO = 927
ARM64_INS_WHILELS = 928
ARM64_INS_WHILELT = 929
ARM64_INS_WRFFR = 930
ARM64_INS_XAR = 931
ARM64_INS_XPACD = 932
ARM64_INS_XPACI = 933
ARM64_INS_XPACLRI = 934
ARM64_INS_XTN = 935
ARM64_INS_XTN2 = 936
ARM64_INS_YIELD = 937
ARM64_INS_ZIP1 = 938
ARM64_INS_ZIP2 = 939
ARM64_INS_SBFIZ = 940
ARM64_INS_UBFIZ = 941
ARM64_INS_SBFX = 942
ARM64_INS_UBFX = 943
ARM64_INS_BFI = 944
ARM64_INS_BFXIL = 945
ARM64_INS_IC = 946
ARM64_INS_DC = 947
ARM64_INS_AT = 948
ARM64_INS_TLBI = 949
ARM64_INS_ENDING = 950
ARM64_GRP_INVALID = 0
ARM64_GRP_JUMP = 1
ARM64_GRP_CALL = 2
ARM64_GRP_RET = 3
ARM64_GRP_INT = 4
ARM64_GRP_PRIVILEGE = 6
ARM64_GRP_BRANCH_RELATIVE = 7
ARM64_GRP_CRYPTO = 128
ARM64_GRP_FPARMV8 = 129
ARM64_GRP_NEON = 130
ARM64_GRP_CRC = 131
ARM64_GRP_AES = 132
ARM64_GRP_DOTPROD = 133
ARM64_GRP_FULLFP16 = 134
ARM64_GRP_LSE = 135
ARM64_GRP_RCPC = 136
ARM64_GRP_RDM = 137
ARM64_GRP_SHA2 = 138
ARM64_GRP_SHA3 = 139
ARM64_GRP_SM4 = 140
ARM64_GRP_SVE = 141
ARM64_GRP_V8_1A = 142
ARM64_GRP_V8_3A = 143
ARM64_GRP_V8_4A = 144
ARM64_GRP_ENDING = 145
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/arm64_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
M68K_OPERAND_COUNT = 4
M68K_REG_INVALID = 0
M68K_REG_D0 = 1
M68K_REG_D1 = 2
M68K_REG_D2 = 3
M68K_REG_D3 = 4
M68K_REG_D4 = 5
M68K_REG_D5 = 6
M68K_REG_D6 = 7
M68K_REG_D7 = 8
M68K_REG_A0 = 9
M68K_REG_A1 = 10
M68K_REG_A2 = 11
M68K_REG_A3 = 12
M68K_REG_A4 = 13
M68K_REG_A5 = 14
M68K_REG_A6 = 15
M68K_REG_A7 = 16
M68K_REG_FP0 = 17
M68K_REG_FP1 = 18
M68K_REG_FP2 = 19
M68K_REG_FP3 = 20
M68K_REG_FP4 = 21
M68K_REG_FP5 = 22
M68K_REG_FP6 = 23
M68K_REG_FP7 = 24
M68K_REG_PC = 25
M68K_REG_SR = 26
M68K_REG_CCR = 27
M68K_REG_SFC = 28
M68K_REG_DFC = 29
M68K_REG_USP = 30
M68K_REG_VBR = 31
M68K_REG_CACR = 32
M68K_REG_CAAR = 33
M68K_REG_MSP = 34
M68K_REG_ISP = 35
M68K_REG_TC = 36
M68K_REG_ITT0 = 37
M68K_REG_ITT1 = 38
M68K_REG_DTT0 = 39
M68K_REG_DTT1 = 40
M68K_REG_MMUSR = 41
M68K_REG_URP = 42
M68K_REG_SRP = 43
M68K_REG_FPCR = 44
M68K_REG_FPSR = 45
M68K_REG_FPIAR = 46
M68K_REG_ENDING = 47
M68K_AM_NONE = 0
M68K_AM_REG_DIRECT_DATA = 1
M68K_AM_REG_DIRECT_ADDR = 2
M68K_AM_REGI_ADDR = 3
M68K_AM_REGI_ADDR_POST_INC = 4
M68K_AM_REGI_ADDR_PRE_DEC = 5
M68K_AM_REGI_ADDR_DISP = 6
M68K_AM_AREGI_INDEX_8_BIT_DISP = 7
M68K_AM_AREGI_INDEX_BASE_DISP = 8
M68K_AM_MEMI_POST_INDEX = 9
M68K_AM_MEMI_PRE_INDEX = 10
M68K_AM_PCI_DISP = 11
M68K_AM_PCI_INDEX_8_BIT_DISP = 12
M68K_AM_PCI_INDEX_BASE_DISP = 13
M68K_AM_PC_MEMI_POST_INDEX = 14
M68K_AM_PC_MEMI_PRE_INDEX = 15
M68K_AM_ABSOLUTE_DATA_SHORT = 16
M68K_AM_ABSOLUTE_DATA_LONG = 17
M68K_AM_IMMEDIATE = 18
M68K_AM_BRANCH_DISPLACEMENT = 19
M68K_OP_INVALID = 0
M68K_OP_REG = 1
M68K_OP_IMM = 2
M68K_OP_MEM = 3
M68K_OP_FP_SINGLE = 4
M68K_OP_FP_DOUBLE = 5
M68K_OP_REG_BITS = 6
M68K_OP_REG_PAIR = 7
M68K_OP_BR_DISP = 8
M68K_OP_BR_DISP_SIZE_INVALID = 0
M68K_OP_BR_DISP_SIZE_BYTE = 1
M68K_OP_BR_DISP_SIZE_WORD = 2
M68K_OP_BR_DISP_SIZE_LONG = 4
M68K_CPU_SIZE_NONE = 0
M68K_CPU_SIZE_BYTE = 1
M68K_CPU_SIZE_WORD = 2
M68K_CPU_SIZE_LONG = 4
M68K_FPU_SIZE_NONE = 0
M68K_FPU_SIZE_SINGLE = 4
M68K_FPU_SIZE_DOUBLE = 8
M68K_FPU_SIZE_EXTENDED = 12
M68K_SIZE_TYPE_INVALID = 0
M68K_SIZE_TYPE_CPU = 1
M68K_SIZE_TYPE_FPU = 2
M68K_INS_INVALID = 0
M68K_INS_ABCD = 1
M68K_INS_ADD = 2
M68K_INS_ADDA = 3
M68K_INS_ADDI = 4
M68K_INS_ADDQ = 5
M68K_INS_ADDX = 6
M68K_INS_AND = 7
M68K_INS_ANDI = 8
M68K_INS_ASL = 9
M68K_INS_ASR = 10
M68K_INS_BHS = 11
M68K_INS_BLO = 12
M68K_INS_BHI = 13
M68K_INS_BLS = 14
M68K_INS_BCC = 15
M68K_INS_BCS = 16
M68K_INS_BNE = 17
M68K_INS_BEQ = 18
M68K_INS_BVC = 19
M68K_INS_BVS = 20
M68K_INS_BPL = 21
M68K_INS_BMI = 22
M68K_INS_BGE = 23
M68K_INS_BLT = 24
M68K_INS_BGT = 25
M68K_INS_BLE = 26
M68K_INS_BRA = 27
M68K_INS_BSR = 28
M68K_INS_BCHG = 29
M68K_INS_BCLR = 30
M68K_INS_BSET = 31
M68K_INS_BTST = 32
M68K_INS_BFCHG = 33
M68K_INS_BFCLR = 34
M68K_INS_BFEXTS = 35
M68K_INS_BFEXTU = 36
M68K_INS_BFFFO = 37
M68K_INS_BFINS = 38
M68K_INS_BFSET = 39
M68K_INS_BFTST = 40
M68K_INS_BKPT = 41
M68K_INS_CALLM = 42
M68K_INS_CAS = 43
M68K_INS_CAS2 = 44
M68K_INS_CHK = 45
M68K_INS_CHK2 = 46
M68K_INS_CLR = 47
M68K_INS_CMP = 48
M68K_INS_CMPA = 49
M68K_INS_CMPI = 50
M68K_INS_CMPM = 51
M68K_INS_CMP2 = 52
M68K_INS_CINVL = 53
M68K_INS_CINVP = 54
M68K_INS_CINVA = 55
M68K_INS_CPUSHL = 56
M68K_INS_CPUSHP = 57
M68K_INS_CPUSHA = 58
M68K_INS_DBT = 59
M68K_INS_DBF = 60
M68K_INS_DBHI = 61
M68K_INS_DBLS = 62
M68K_INS_DBCC = 63
M68K_INS_DBCS = 64
M68K_INS_DBNE = 65
M68K_INS_DBEQ = 66
M68K_INS_DBVC = 67
M68K_INS_DBVS = 68
M68K_INS_DBPL = 69
M68K_INS_DBMI = 70
M68K_INS_DBGE = 71
M68K_INS_DBLT = 72
M68K_INS_DBGT = 73
M68K_INS_DBLE = 74
M68K_INS_DBRA = 75
M68K_INS_DIVS = 76
M68K_INS_DIVSL = 77
M68K_INS_DIVU = 78
M68K_INS_DIVUL = 79
M68K_INS_EOR = 80
M68K_INS_EORI = 81
M68K_INS_EXG = 82
M68K_INS_EXT = 83
M68K_INS_EXTB = 84
M68K_INS_FABS = 85
M68K_INS_FSABS = 86
M68K_INS_FDABS = 87
M68K_INS_FACOS = 88
M68K_INS_FADD = 89
M68K_INS_FSADD = 90
M68K_INS_FDADD = 91
M68K_INS_FASIN = 92
M68K_INS_FATAN = 93
M68K_INS_FATANH = 94
M68K_INS_FBF = 95
M68K_INS_FBEQ = 96
M68K_INS_FBOGT = 97
M68K_INS_FBOGE = 98
M68K_INS_FBOLT = 99
M68K_INS_FBOLE = 100
M68K_INS_FBOGL = 101
M68K_INS_FBOR = 102
M68K_INS_FBUN = 103
M68K_INS_FBUEQ = 104
M68K_INS_FBUGT = 105
M68K_INS_FBUGE = 106
M68K_INS_FBULT = 107
M68K_INS_FBULE = 108
M68K_INS_FBNE = 109
M68K_INS_FBT = 110
M68K_INS_FBSF = 111
M68K_INS_FBSEQ = 112
M68K_INS_FBGT = 113
M68K_INS_FBGE = 114
M68K_INS_FBLT = 115
M68K_INS_FBLE = 116
M68K_INS_FBGL = 117
M68K_INS_FBGLE = 118
M68K_INS_FBNGLE = 119
M68K_INS_FBNGL = 120
M68K_INS_FBNLE = 121
M68K_INS_FBNLT = 122
M68K_INS_FBNGE = 123
M68K_INS_FBNGT = 124
M68K_INS_FBSNE = 125
M68K_INS_FBST = 126
M68K_INS_FCMP = 127
M68K_INS_FCOS = 128
M68K_INS_FCOSH = 129
M68K_INS_FDBF = 130
M68K_INS_FDBEQ = 131
M68K_INS_FDBOGT = 132
M68K_INS_FDBOGE = 133
M68K_INS_FDBOLT = 134
M68K_INS_FDBOLE = 135
M68K_INS_FDBOGL = 136
M68K_INS_FDBOR = 137
M68K_INS_FDBUN = 138
M68K_INS_FDBUEQ = 139
M68K_INS_FDBUGT = 140
M68K_INS_FDBUGE = 141
M68K_INS_FDBULT = 142
M68K_INS_FDBULE = 143
M68K_INS_FDBNE = 144
M68K_INS_FDBT = 145
M68K_INS_FDBSF = 146
M68K_INS_FDBSEQ = 147
M68K_INS_FDBGT = 148
M68K_INS_FDBGE = 149
M68K_INS_FDBLT = 150
M68K_INS_FDBLE = 151
M68K_INS_FDBGL = 152
M68K_INS_FDBGLE = 153
M68K_INS_FDBNGLE = 154
M68K_INS_FDBNGL = 155
M68K_INS_FDBNLE = 156
M68K_INS_FDBNLT = 157
M68K_INS_FDBNGE = 158
M68K_INS_FDBNGT = 159
M68K_INS_FDBSNE = 160
M68K_INS_FDBST = 161
M68K_INS_FDIV = 162
M68K_INS_FSDIV = 163
M68K_INS_FDDIV = 164
M68K_INS_FETOX = 165
M68K_INS_FETOXM1 = 166
M68K_INS_FGETEXP = 167
M68K_INS_FGETMAN = 168
M68K_INS_FINT = 169
M68K_INS_FINTRZ = 170
M68K_INS_FLOG10 = 171
M68K_INS_FLOG2 = 172
M68K_INS_FLOGN = 173
M68K_INS_FLOGNP1 = 174
M68K_INS_FMOD = 175
M68K_INS_FMOVE = 176
M68K_INS_FSMOVE = 177
M68K_INS_FDMOVE = 178
M68K_INS_FMOVECR = 179
M68K_INS_FMOVEM = 180
M68K_INS_FMUL = 181
M68K_INS_FSMUL = 182
M68K_INS_FDMUL = 183
M68K_INS_FNEG = 184
M68K_INS_FSNEG = 185
M68K_INS_FDNEG = 186
M68K_INS_FNOP = 187
M68K_INS_FREM = 188
M68K_INS_FRESTORE = 189
M68K_INS_FSAVE = 190
M68K_INS_FSCALE = 191
M68K_INS_FSGLDIV = 192
M68K_INS_FSGLMUL = 193
M68K_INS_FSIN = 194
M68K_INS_FSINCOS = 195
M68K_INS_FSINH = 196
M68K_INS_FSQRT = 197
M68K_INS_FSSQRT = 198
M68K_INS_FDSQRT = 199
M68K_INS_FSF = 200
M68K_INS_FSBEQ = 201
M68K_INS_FSOGT = 202
M68K_INS_FSOGE = 203
M68K_INS_FSOLT = 204
M68K_INS_FSOLE = 205
M68K_INS_FSOGL = 206
M68K_INS_FSOR = 207
M68K_INS_FSUN = 208
M68K_INS_FSUEQ = 209
M68K_INS_FSUGT = 210
M68K_INS_FSUGE = 211
M68K_INS_FSULT = 212
M68K_INS_FSULE = 213
M68K_INS_FSNE = 214
M68K_INS_FST = 215
M68K_INS_FSSF = 216
M68K_INS_FSSEQ = 217
M68K_INS_FSGT = 218
M68K_INS_FSGE = 219
M68K_INS_FSLT = 220
M68K_INS_FSLE = 221
M68K_INS_FSGL = 222
M68K_INS_FSGLE = 223
M68K_INS_FSNGLE = 224
M68K_INS_FSNGL = 225
M68K_INS_FSNLE = 226
M68K_INS_FSNLT = 227
M68K_INS_FSNGE = 228
M68K_INS_FSNGT = 229
M68K_INS_FSSNE = 230
M68K_INS_FSST = 231
M68K_INS_FSUB = 232
M68K_INS_FSSUB = 233
M68K_INS_FDSUB = 234
M68K_INS_FTAN = 235
M68K_INS_FTANH = 236
M68K_INS_FTENTOX = 237
M68K_INS_FTRAPF = 238
M68K_INS_FTRAPEQ = 239
M68K_INS_FTRAPOGT = 240
M68K_INS_FTRAPOGE = 241
M68K_INS_FTRAPOLT = 242
M68K_INS_FTRAPOLE = 243
M68K_INS_FTRAPOGL = 244
M68K_INS_FTRAPOR = 245
M68K_INS_FTRAPUN = 246
M68K_INS_FTRAPUEQ = 247
M68K_INS_FTRAPUGT = 248
M68K_INS_FTRAPUGE = 249
M68K_INS_FTRAPULT = 250
M68K_INS_FTRAPULE = 251
M68K_INS_FTRAPNE = 252
M68K_INS_FTRAPT = 253
M68K_INS_FTRAPSF = 254
M68K_INS_FTRAPSEQ = 255
M68K_INS_FTRAPGT = 256
M68K_INS_FTRAPGE = 257
M68K_INS_FTRAPLT = 258
M68K_INS_FTRAPLE = 259
M68K_INS_FTRAPGL = 260
M68K_INS_FTRAPGLE = 261
M68K_INS_FTRAPNGLE = 262
M68K_INS_FTRAPNGL = 263
M68K_INS_FTRAPNLE = 264
M68K_INS_FTRAPNLT = 265
M68K_INS_FTRAPNGE = 266
M68K_INS_FTRAPNGT = 267
M68K_INS_FTRAPSNE = 268
M68K_INS_FTRAPST = 269
M68K_INS_FTST = 270
M68K_INS_FTWOTOX = 271
M68K_INS_HALT = 272
M68K_INS_ILLEGAL = 273
M68K_INS_JMP = 274
M68K_INS_JSR = 275
M68K_INS_LEA = 276
M68K_INS_LINK = 277
M68K_INS_LPSTOP = 278
M68K_INS_LSL = 279
M68K_INS_LSR = 280
M68K_INS_MOVE = 281
M68K_INS_MOVEA = 282
M68K_INS_MOVEC = 283
M68K_INS_MOVEM = 284
M68K_INS_MOVEP = 285
M68K_INS_MOVEQ = 286
M68K_INS_MOVES = 287
M68K_INS_MOVE16 = 288
M68K_INS_MULS = 289
M68K_INS_MULU = 290
M68K_INS_NBCD = 291
M68K_INS_NEG = 292
M68K_INS_NEGX = 293
M68K_INS_NOP = 294
M68K_INS_NOT = 295
M68K_INS_OR = 296
M68K_INS_ORI = 297
M68K_INS_PACK = 298
M68K_INS_PEA = 299
M68K_INS_PFLUSH = 300
M68K_INS_PFLUSHA = 301
M68K_INS_PFLUSHAN = 302
M68K_INS_PFLUSHN = 303
M68K_INS_PLOADR = 304
M68K_INS_PLOADW = 305
M68K_INS_PLPAR = 306
M68K_INS_PLPAW = 307
M68K_INS_PMOVE = 308
M68K_INS_PMOVEFD = 309
M68K_INS_PTESTR = 310
M68K_INS_PTESTW = 311
M68K_INS_PULSE = 312
M68K_INS_REMS = 313
M68K_INS_REMU = 314
M68K_INS_RESET = 315
M68K_INS_ROL = 316
M68K_INS_ROR = 317
M68K_INS_ROXL = 318
M68K_INS_ROXR = 319
M68K_INS_RTD = 320
M68K_INS_RTE = 321
M68K_INS_RTM = 322
M68K_INS_RTR = 323
M68K_INS_RTS = 324
M68K_INS_SBCD = 325
M68K_INS_ST = 326
M68K_INS_SF = 327
M68K_INS_SHI = 328
M68K_INS_SLS = 329
M68K_INS_SCC = 330
M68K_INS_SHS = 331
M68K_INS_SCS = 332
M68K_INS_SLO = 333
M68K_INS_SNE = 334
M68K_INS_SEQ = 335
M68K_INS_SVC = 336
M68K_INS_SVS = 337
M68K_INS_SPL = 338
M68K_INS_SMI = 339
M68K_INS_SGE = 340
M68K_INS_SLT = 341
M68K_INS_SGT = 342
M68K_INS_SLE = 343
M68K_INS_STOP = 344
M68K_INS_SUB = 345
M68K_INS_SUBA = 346
M68K_INS_SUBI = 347
M68K_INS_SUBQ = 348
M68K_INS_SUBX = 349
M68K_INS_SWAP = 350
M68K_INS_TAS = 351
M68K_INS_TRAP = 352
M68K_INS_TRAPV = 353
M68K_INS_TRAPT = 354
M68K_INS_TRAPF = 355
M68K_INS_TRAPHI = 356
M68K_INS_TRAPLS = 357
M68K_INS_TRAPCC = 358
M68K_INS_TRAPHS = 359
M68K_INS_TRAPCS = 360
M68K_INS_TRAPLO = 361
M68K_INS_TRAPNE = 362
M68K_INS_TRAPEQ = 363
M68K_INS_TRAPVC = 364
M68K_INS_TRAPVS = 365
M68K_INS_TRAPPL = 366
M68K_INS_TRAPMI = 367
M68K_INS_TRAPGE = 368
M68K_INS_TRAPLT = 369
M68K_INS_TRAPGT = 370
M68K_INS_TRAPLE = 371
M68K_INS_TST = 372
M68K_INS_UNLK = 373
M68K_INS_UNPK = 374
M68K_INS_ENDING = 375
M68K_GRP_INVALID = 0
M68K_GRP_JUMP = 1
M68K_GRP_RET = 3
M68K_GRP_IRET = 5
M68K_GRP_BRANCH_RELATIVE = 7
M68K_GRP_ENDING = 8
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/m68k_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
BPF_OP_INVALID = 0
BPF_OP_REG = 1
BPF_OP_IMM = 2
BPF_OP_OFF = 3
BPF_OP_MEM = 4
BPF_OP_MMEM = 5
BPF_OP_MSH = 6
BPF_OP_EXT = 7
BPF_REG_INVALID = 0
BPF_REG_A = 1
BPF_REG_X = 2
BPF_REG_R0 = 3
BPF_REG_R1 = 4
BPF_REG_R2 = 5
BPF_REG_R3 = 6
BPF_REG_R4 = 7
BPF_REG_R5 = 8
BPF_REG_R6 = 9
BPF_REG_R7 = 10
BPF_REG_R8 = 11
BPF_REG_R9 = 12
BPF_REG_R10 = 13
BPF_REG_ENDING = 14
BPF_EXT_INVALID = 0
BPF_EXT_LEN = 1
BPF_INS_INVALID = 0
BPF_INS_ADD = 1
BPF_INS_SUB = 2
BPF_INS_MUL = 3
BPF_INS_DIV = 4
BPF_INS_OR = 5
BPF_INS_AND = 6
BPF_INS_LSH = 7
BPF_INS_RSH = 8
BPF_INS_NEG = 9
BPF_INS_MOD = 10
BPF_INS_XOR = 11
BPF_INS_MOV = 12
BPF_INS_ARSH = 13
BPF_INS_ADD64 = 14
BPF_INS_SUB64 = 15
BPF_INS_MUL64 = 16
BPF_INS_DIV64 = 17
BPF_INS_OR64 = 18
BPF_INS_AND64 = 19
BPF_INS_LSH64 = 20
BPF_INS_RSH64 = 21
BPF_INS_NEG64 = 22
BPF_INS_MOD64 = 23
BPF_INS_XOR64 = 24
BPF_INS_MOV64 = 25
BPF_INS_ARSH64 = 26
BPF_INS_LE16 = 27
BPF_INS_LE32 = 28
BPF_INS_LE64 = 29
BPF_INS_BE16 = 30
BPF_INS_BE32 = 31
BPF_INS_BE64 = 32
BPF_INS_LDW = 33
BPF_INS_LDH = 34
BPF_INS_LDB = 35
BPF_INS_LDDW = 36
BPF_INS_LDXW = 37
BPF_INS_LDXH = 38
BPF_INS_LDXB = 39
BPF_INS_LDXDW = 40
BPF_INS_STW = 41
BPF_INS_STH = 42
BPF_INS_STB = 43
BPF_INS_STDW = 44
BPF_INS_STXW = 45
BPF_INS_STXH = 46
BPF_INS_STXB = 47
BPF_INS_STXDW = 48
BPF_INS_XADDW = 49
BPF_INS_XADDDW = 50
BPF_INS_JMP = 51
BPF_INS_JEQ = 52
BPF_INS_JGT = 53
BPF_INS_JGE = 54
BPF_INS_JSET = 55
BPF_INS_JNE = 56
BPF_INS_JSGT = 57
BPF_INS_JSGE = 58
BPF_INS_CALL = 59
BPF_INS_EXIT = 60
BPF_INS_JLT = 61
BPF_INS_JLE = 62
BPF_INS_JSLT = 63
BPF_INS_JSLE = 64
BPF_INS_RET = 65
BPF_INS_TAX = 66
BPF_INS_TXA = 67
BPF_INS_ENDING = 68
BPF_INS_LD = BPF_INS_LDW
BPF_INS_LDX = BPF_INS_LDXW
BPF_INS_ST = BPF_INS_STW
BPF_INS_STX = BPF_INS_STXW
BPF_GRP_INVALID = 0
BPF_GRP_LOAD = 1
BPF_GRP_STORE = 2
BPF_GRP_ALU = 3
BPF_GRP_JUMP = 4
BPF_GRP_CALL = 5
BPF_GRP_RETURN = 6
BPF_GRP_MISC = 7
BPF_GRP_ENDING = 8
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/bpf_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
X86_REG_INVALID = 0
X86_REG_AH = 1
X86_REG_AL = 2
X86_REG_AX = 3
X86_REG_BH = 4
X86_REG_BL = 5
X86_REG_BP = 6
X86_REG_BPL = 7
X86_REG_BX = 8
X86_REG_CH = 9
X86_REG_CL = 10
X86_REG_CS = 11
X86_REG_CX = 12
X86_REG_DH = 13
X86_REG_DI = 14
X86_REG_DIL = 15
X86_REG_DL = 16
X86_REG_DS = 17
X86_REG_DX = 18
X86_REG_EAX = 19
X86_REG_EBP = 20
X86_REG_EBX = 21
X86_REG_ECX = 22
X86_REG_EDI = 23
X86_REG_EDX = 24
X86_REG_EFLAGS = 25
X86_REG_EIP = 26
X86_REG_EIZ = 27
X86_REG_ES = 28
X86_REG_ESI = 29
X86_REG_ESP = 30
X86_REG_FPSW = 31
X86_REG_FS = 32
X86_REG_GS = 33
X86_REG_IP = 34
X86_REG_RAX = 35
X86_REG_RBP = 36
X86_REG_RBX = 37
X86_REG_RCX = 38
X86_REG_RDI = 39
X86_REG_RDX = 40
X86_REG_RIP = 41
X86_REG_RIZ = 42
X86_REG_RSI = 43
X86_REG_RSP = 44
X86_REG_SI = 45
X86_REG_SIL = 46
X86_REG_SP = 47
X86_REG_SPL = 48
X86_REG_SS = 49
X86_REG_CR0 = 50
X86_REG_CR1 = 51
X86_REG_CR2 = 52
X86_REG_CR3 = 53
X86_REG_CR4 = 54
X86_REG_CR5 = 55
X86_REG_CR6 = 56
X86_REG_CR7 = 57
X86_REG_CR8 = 58
X86_REG_CR9 = 59
X86_REG_CR10 = 60
X86_REG_CR11 = 61
X86_REG_CR12 = 62
X86_REG_CR13 = 63
X86_REG_CR14 = 64
X86_REG_CR15 = 65
X86_REG_DR0 = 66
X86_REG_DR1 = 67
X86_REG_DR2 = 68
X86_REG_DR3 = 69
X86_REG_DR4 = 70
X86_REG_DR5 = 71
X86_REG_DR6 = 72
X86_REG_DR7 = 73
X86_REG_DR8 = 74
X86_REG_DR9 = 75
X86_REG_DR10 = 76
X86_REG_DR11 = 77
X86_REG_DR12 = 78
X86_REG_DR13 = 79
X86_REG_DR14 = 80
X86_REG_DR15 = 81
X86_REG_FP0 = 82
X86_REG_FP1 = 83
X86_REG_FP2 = 84
X86_REG_FP3 = 85
X86_REG_FP4 = 86
X86_REG_FP5 = 87
X86_REG_FP6 = 88
X86_REG_FP7 = 89
X86_REG_K0 = 90
X86_REG_K1 = 91
X86_REG_K2 = 92
X86_REG_K3 = 93
X86_REG_K4 = 94
X86_REG_K5 = 95
X86_REG_K6 = 96
X86_REG_K7 = 97
X86_REG_MM0 = 98
X86_REG_MM1 = 99
X86_REG_MM2 = 100
X86_REG_MM3 = 101
X86_REG_MM4 = 102
X86_REG_MM5 = 103
X86_REG_MM6 = 104
X86_REG_MM7 = 105
X86_REG_R8 = 106
X86_REG_R9 = 107
X86_REG_R10 = 108
X86_REG_R11 = 109
X86_REG_R12 = 110
X86_REG_R13 = 111
X86_REG_R14 = 112
X86_REG_R15 = 113
X86_REG_ST0 = 114
X86_REG_ST1 = 115
X86_REG_ST2 = 116
X86_REG_ST3 = 117
X86_REG_ST4 = 118
X86_REG_ST5 = 119
X86_REG_ST6 = 120
X86_REG_ST7 = 121
X86_REG_XMM0 = 122
X86_REG_XMM1 = 123
X86_REG_XMM2 = 124
X86_REG_XMM3 = 125
X86_REG_XMM4 = 126
X86_REG_XMM5 = 127
X86_REG_XMM6 = 128
X86_REG_XMM7 = 129
X86_REG_XMM8 = 130
X86_REG_XMM9 = 131
X86_REG_XMM10 = 132
X86_REG_XMM11 = 133
X86_REG_XMM12 = 134
X86_REG_XMM13 = 135
X86_REG_XMM14 = 136
X86_REG_XMM15 = 137
X86_REG_XMM16 = 138
X86_REG_XMM17 = 139
X86_REG_XMM18 = 140
X86_REG_XMM19 = 141
X86_REG_XMM20 = 142
X86_REG_XMM21 = 143
X86_REG_XMM22 = 144
X86_REG_XMM23 = 145
X86_REG_XMM24 = 146
X86_REG_XMM25 = 147
X86_REG_XMM26 = 148
X86_REG_XMM27 = 149
X86_REG_XMM28 = 150
X86_REG_XMM29 = 151
X86_REG_XMM30 = 152
X86_REG_XMM31 = 153
X86_REG_YMM0 = 154
X86_REG_YMM1 = 155
X86_REG_YMM2 = 156
X86_REG_YMM3 = 157
X86_REG_YMM4 = 158
X86_REG_YMM5 = 159
X86_REG_YMM6 = 160
X86_REG_YMM7 = 161
X86_REG_YMM8 = 162
X86_REG_YMM9 = 163
X86_REG_YMM10 = 164
X86_REG_YMM11 = 165
X86_REG_YMM12 = 166
X86_REG_YMM13 = 167
X86_REG_YMM14 = 168
X86_REG_YMM15 = 169
X86_REG_YMM16 = 170
X86_REG_YMM17 = 171
X86_REG_YMM18 = 172
X86_REG_YMM19 = 173
X86_REG_YMM20 = 174
X86_REG_YMM21 = 175
X86_REG_YMM22 = 176
X86_REG_YMM23 = 177
X86_REG_YMM24 = 178
X86_REG_YMM25 = 179
X86_REG_YMM26 = 180
X86_REG_YMM27 = 181
X86_REG_YMM28 = 182
X86_REG_YMM29 = 183
X86_REG_YMM30 = 184
X86_REG_YMM31 = 185
X86_REG_ZMM0 = 186
X86_REG_ZMM1 = 187
X86_REG_ZMM2 = 188
X86_REG_ZMM3 = 189
X86_REG_ZMM4 = 190
X86_REG_ZMM5 = 191
X86_REG_ZMM6 = 192
X86_REG_ZMM7 = 193
X86_REG_ZMM8 = 194
X86_REG_ZMM9 = 195
X86_REG_ZMM10 = 196
X86_REG_ZMM11 = 197
X86_REG_ZMM12 = 198
X86_REG_ZMM13 = 199
X86_REG_ZMM14 = 200
X86_REG_ZMM15 = 201
X86_REG_ZMM16 = 202
X86_REG_ZMM17 = 203
X86_REG_ZMM18 = 204
X86_REG_ZMM19 = 205
X86_REG_ZMM20 = 206
X86_REG_ZMM21 = 207
X86_REG_ZMM22 = 208
X86_REG_ZMM23 = 209
X86_REG_ZMM24 = 210
X86_REG_ZMM25 = 211
X86_REG_ZMM26 = 212
X86_REG_ZMM27 = 213
X86_REG_ZMM28 = 214
X86_REG_ZMM29 = 215
X86_REG_ZMM30 = 216
X86_REG_ZMM31 = 217
X86_REG_R8B = 218
X86_REG_R9B = 219
X86_REG_R10B = 220
X86_REG_R11B = 221
X86_REG_R12B = 222
X86_REG_R13B = 223
X86_REG_R14B = 224
X86_REG_R15B = 225
X86_REG_R8D = 226
X86_REG_R9D = 227
X86_REG_R10D = 228
X86_REG_R11D = 229
X86_REG_R12D = 230
X86_REG_R13D = 231
X86_REG_R14D = 232
X86_REG_R15D = 233
X86_REG_R8W = 234
X86_REG_R9W = 235
X86_REG_R10W = 236
X86_REG_R11W = 237
X86_REG_R12W = 238
X86_REG_R13W = 239
X86_REG_R14W = 240
X86_REG_R15W = 241
X86_REG_BND0 = 242
X86_REG_BND1 = 243
X86_REG_BND2 = 244
X86_REG_BND3 = 245
X86_REG_ENDING = 246
X86_EFLAGS_MODIFY_AF = 1<<0
X86_EFLAGS_MODIFY_CF = 1<<1
X86_EFLAGS_MODIFY_SF = 1<<2
X86_EFLAGS_MODIFY_ZF = 1<<3
X86_EFLAGS_MODIFY_PF = 1<<4
X86_EFLAGS_MODIFY_OF = 1<<5
X86_EFLAGS_MODIFY_TF = 1<<6
X86_EFLAGS_MODIFY_IF = 1<<7
X86_EFLAGS_MODIFY_DF = 1<<8
X86_EFLAGS_MODIFY_NT = 1<<9
X86_EFLAGS_MODIFY_RF = 1<<10
X86_EFLAGS_PRIOR_OF = 1<<11
X86_EFLAGS_PRIOR_SF = 1<<12
X86_EFLAGS_PRIOR_ZF = 1<<13
X86_EFLAGS_PRIOR_AF = 1<<14
X86_EFLAGS_PRIOR_PF = 1<<15
X86_EFLAGS_PRIOR_CF = 1<<16
X86_EFLAGS_PRIOR_TF = 1<<17
X86_EFLAGS_PRIOR_IF = 1<<18
X86_EFLAGS_PRIOR_DF = 1<<19
X86_EFLAGS_PRIOR_NT = 1<<20
X86_EFLAGS_RESET_OF = 1<<21
X86_EFLAGS_RESET_CF = 1<<22
X86_EFLAGS_RESET_DF = 1<<23
X86_EFLAGS_RESET_IF = 1<<24
X86_EFLAGS_RESET_SF = 1<<25
X86_EFLAGS_RESET_AF = 1<<26
X86_EFLAGS_RESET_TF = 1<<27
X86_EFLAGS_RESET_NT = 1<<28
X86_EFLAGS_RESET_PF = 1<<29
X86_EFLAGS_SET_CF = 1<<30
X86_EFLAGS_SET_DF = 1<<31
X86_EFLAGS_SET_IF = 1<<32
X86_EFLAGS_TEST_OF = 1<<33
X86_EFLAGS_TEST_SF = 1<<34
X86_EFLAGS_TEST_ZF = 1<<35
X86_EFLAGS_TEST_PF = 1<<36
X86_EFLAGS_TEST_CF = 1<<37
X86_EFLAGS_TEST_NT = 1<<38
X86_EFLAGS_TEST_DF = 1<<39
X86_EFLAGS_UNDEFINED_OF = 1<<40
X86_EFLAGS_UNDEFINED_SF = 1<<41
X86_EFLAGS_UNDEFINED_ZF = 1<<42
X86_EFLAGS_UNDEFINED_PF = 1<<43
X86_EFLAGS_UNDEFINED_AF = 1<<44
X86_EFLAGS_UNDEFINED_CF = 1<<45
X86_EFLAGS_RESET_RF = 1<<46
X86_EFLAGS_TEST_RF = 1<<47
X86_EFLAGS_TEST_IF = 1<<48
X86_EFLAGS_TEST_TF = 1<<49
X86_EFLAGS_TEST_AF = 1<<50
X86_EFLAGS_RESET_ZF = 1<<51
X86_EFLAGS_SET_OF = 1<<52
X86_EFLAGS_SET_SF = 1<<53
X86_EFLAGS_SET_ZF = 1<<54
X86_EFLAGS_SET_AF = 1<<55
X86_EFLAGS_SET_PF = 1<<56
X86_EFLAGS_RESET_0F = 1<<57
X86_EFLAGS_RESET_AC = 1<<58
X86_FPU_FLAGS_MODIFY_C0 = 1<<0
X86_FPU_FLAGS_MODIFY_C1 = 1<<1
X86_FPU_FLAGS_MODIFY_C2 = 1<<2
X86_FPU_FLAGS_MODIFY_C3 = 1<<3
X86_FPU_FLAGS_RESET_C0 = 1<<4
X86_FPU_FLAGS_RESET_C1 = 1<<5
X86_FPU_FLAGS_RESET_C2 = 1<<6
X86_FPU_FLAGS_RESET_C3 = 1<<7
X86_FPU_FLAGS_SET_C0 = 1<<8
X86_FPU_FLAGS_SET_C1 = 1<<9
X86_FPU_FLAGS_SET_C2 = 1<<10
X86_FPU_FLAGS_SET_C3 = 1<<11
X86_FPU_FLAGS_UNDEFINED_C0 = 1<<12
X86_FPU_FLAGS_UNDEFINED_C1 = 1<<13
X86_FPU_FLAGS_UNDEFINED_C2 = 1<<14
X86_FPU_FLAGS_UNDEFINED_C3 = 1<<15
X86_FPU_FLAGS_TEST_C0 = 1<<16
X86_FPU_FLAGS_TEST_C1 = 1<<17
X86_FPU_FLAGS_TEST_C2 = 1<<18
X86_FPU_FLAGS_TEST_C3 = 1<<19
X86_OP_INVALID = 0
X86_OP_REG = 1
X86_OP_IMM = 2
X86_OP_MEM = 3
X86_XOP_CC_INVALID = 0
X86_XOP_CC_LT = 1
X86_XOP_CC_LE = 2
X86_XOP_CC_GT = 3
X86_XOP_CC_GE = 4
X86_XOP_CC_EQ = 5
X86_XOP_CC_NEQ = 6
X86_XOP_CC_FALSE = 7
X86_XOP_CC_TRUE = 8
X86_AVX_BCAST_INVALID = 0
X86_AVX_BCAST_2 = 1
X86_AVX_BCAST_4 = 2
X86_AVX_BCAST_8 = 3
X86_AVX_BCAST_16 = 4
X86_SSE_CC_INVALID = 0
X86_SSE_CC_EQ = 1
X86_SSE_CC_LT = 2
X86_SSE_CC_LE = 3
X86_SSE_CC_UNORD = 4
X86_SSE_CC_NEQ = 5
X86_SSE_CC_NLT = 6
X86_SSE_CC_NLE = 7
X86_SSE_CC_ORD = 8
X86_AVX_CC_INVALID = 0
X86_AVX_CC_EQ = 1
X86_AVX_CC_LT = 2
X86_AVX_CC_LE = 3
X86_AVX_CC_UNORD = 4
X86_AVX_CC_NEQ = 5
X86_AVX_CC_NLT = 6
X86_AVX_CC_NLE = 7
X86_AVX_CC_ORD = 8
X86_AVX_CC_EQ_UQ = 9
X86_AVX_CC_NGE = 10
X86_AVX_CC_NGT = 11
X86_AVX_CC_FALSE = 12
X86_AVX_CC_NEQ_OQ = 13
X86_AVX_CC_GE = 14
X86_AVX_CC_GT = 15
X86_AVX_CC_TRUE = 16
X86_AVX_CC_EQ_OS = 17
X86_AVX_CC_LT_OQ = 18
X86_AVX_CC_LE_OQ = 19
X86_AVX_CC_UNORD_S = 20
X86_AVX_CC_NEQ_US = 21
X86_AVX_CC_NLT_UQ = 22
X86_AVX_CC_NLE_UQ = 23
X86_AVX_CC_ORD_S = 24
X86_AVX_CC_EQ_US = 25
X86_AVX_CC_NGE_UQ = 26
X86_AVX_CC_NGT_UQ = 27
X86_AVX_CC_FALSE_OS = 28
X86_AVX_CC_NEQ_OS = 29
X86_AVX_CC_GE_OQ = 30
X86_AVX_CC_GT_OQ = 31
X86_AVX_CC_TRUE_US = 32
X86_AVX_RM_INVALID = 0
X86_AVX_RM_RN = 1
X86_AVX_RM_RD = 2
X86_AVX_RM_RU = 3
X86_AVX_RM_RZ = 4
X86_PREFIX_LOCK = 0xf0
X86_PREFIX_REP = 0xf3
X86_PREFIX_REPE = 0xf3
X86_PREFIX_REPNE = 0xf2
X86_PREFIX_CS = 0x2e
X86_PREFIX_SS = 0x36
X86_PREFIX_DS = 0x3e
X86_PREFIX_ES = 0x26
X86_PREFIX_FS = 0x64
X86_PREFIX_GS = 0x65
X86_PREFIX_OPSIZE = 0x66
X86_PREFIX_ADDRSIZE = 0x67
X86_INS_INVALID = 0
X86_INS_AAA = 1
X86_INS_AAD = 2
X86_INS_AAM = 3
X86_INS_AAS = 4
X86_INS_FABS = 5
X86_INS_ADC = 6
X86_INS_ADCX = 7
X86_INS_ADD = 8
X86_INS_ADDPD = 9
X86_INS_ADDPS = 10
X86_INS_ADDSD = 11
X86_INS_ADDSS = 12
X86_INS_ADDSUBPD = 13
X86_INS_ADDSUBPS = 14
X86_INS_FADD = 15
X86_INS_FIADD = 16
X86_INS_ADOX = 17
X86_INS_AESDECLAST = 18
X86_INS_AESDEC = 19
X86_INS_AESENCLAST = 20
X86_INS_AESENC = 21
X86_INS_AESIMC = 22
X86_INS_AESKEYGENASSIST = 23
X86_INS_AND = 24
X86_INS_ANDN = 25
X86_INS_ANDNPD = 26
X86_INS_ANDNPS = 27
X86_INS_ANDPD = 28
X86_INS_ANDPS = 29
X86_INS_ARPL = 30
X86_INS_BEXTR = 31
X86_INS_BLCFILL = 32
X86_INS_BLCI = 33
X86_INS_BLCIC = 34
X86_INS_BLCMSK = 35
X86_INS_BLCS = 36
X86_INS_BLENDPD = 37
X86_INS_BLENDPS = 38
X86_INS_BLENDVPD = 39
X86_INS_BLENDVPS = 40
X86_INS_BLSFILL = 41
X86_INS_BLSI = 42
X86_INS_BLSIC = 43
X86_INS_BLSMSK = 44
X86_INS_BLSR = 45
X86_INS_BNDCL = 46
X86_INS_BNDCN = 47
X86_INS_BNDCU = 48
X86_INS_BNDLDX = 49
X86_INS_BNDMK = 50
X86_INS_BNDMOV = 51
X86_INS_BNDSTX = 52
X86_INS_BOUND = 53
X86_INS_BSF = 54
X86_INS_BSR = 55
X86_INS_BSWAP = 56
X86_INS_BT = 57
X86_INS_BTC = 58
X86_INS_BTR = 59
X86_INS_BTS = 60
X86_INS_BZHI = 61
X86_INS_CALL = 62
X86_INS_CBW = 63
X86_INS_CDQ = 64
X86_INS_CDQE = 65
X86_INS_FCHS = 66
X86_INS_CLAC = 67
X86_INS_CLC = 68
X86_INS_CLD = 69
X86_INS_CLDEMOTE = 70
X86_INS_CLFLUSH = 71
X86_INS_CLFLUSHOPT = 72
X86_INS_CLGI = 73
X86_INS_CLI = 74
X86_INS_CLRSSBSY = 75
X86_INS_CLTS = 76
X86_INS_CLWB = 77
X86_INS_CLZERO = 78
X86_INS_CMC = 79
X86_INS_CMOVA = 80
X86_INS_CMOVAE = 81
X86_INS_CMOVB = 82
X86_INS_CMOVBE = 83
X86_INS_FCMOVBE = 84
X86_INS_FCMOVB = 85
X86_INS_CMOVE = 86
X86_INS_FCMOVE = 87
X86_INS_CMOVG = 88
X86_INS_CMOVGE = 89
X86_INS_CMOVL = 90
X86_INS_CMOVLE = 91
X86_INS_FCMOVNBE = 92
X86_INS_FCMOVNB = 93
X86_INS_CMOVNE = 94
X86_INS_FCMOVNE = 95
X86_INS_CMOVNO = 96
X86_INS_CMOVNP = 97
X86_INS_FCMOVNU = 98
X86_INS_FCMOVNP = 99
X86_INS_CMOVNS = 100
X86_INS_CMOVO = 101
X86_INS_CMOVP = 102
X86_INS_FCMOVU = 103
X86_INS_CMOVS = 104
X86_INS_CMP = 105
X86_INS_CMPPD = 106
X86_INS_CMPPS = 107
X86_INS_CMPSB = 108
X86_INS_CMPSD = 109
X86_INS_CMPSQ = 110
X86_INS_CMPSS = 111
X86_INS_CMPSW = 112
X86_INS_CMPXCHG16B = 113
X86_INS_CMPXCHG = 114
X86_INS_CMPXCHG8B = 115
X86_INS_COMISD = 116
X86_INS_COMISS = 117
X86_INS_FCOMP = 118
X86_INS_FCOMPI = 119
X86_INS_FCOMI = 120
X86_INS_FCOM = 121
X86_INS_FCOS = 122
X86_INS_CPUID = 123
X86_INS_CQO = 124
X86_INS_CRC32 = 125
X86_INS_CVTDQ2PD = 126
X86_INS_CVTDQ2PS = 127
X86_INS_CVTPD2DQ = 128
X86_INS_CVTPD2PS = 129
X86_INS_CVTPS2DQ = 130
X86_INS_CVTPS2PD = 131
X86_INS_CVTSD2SI = 132
X86_INS_CVTSD2SS = 133
X86_INS_CVTSI2SD = 134
X86_INS_CVTSI2SS = 135
X86_INS_CVTSS2SD = 136
X86_INS_CVTSS2SI = 137
X86_INS_CVTTPD2DQ = 138
X86_INS_CVTTPS2DQ = 139
X86_INS_CVTTSD2SI = 140
X86_INS_CVTTSS2SI = 141
X86_INS_CWD = 142
X86_INS_CWDE = 143
X86_INS_DAA = 144
X86_INS_DAS = 145
X86_INS_DATA16 = 146
X86_INS_DEC = 147
X86_INS_DIV = 148
X86_INS_DIVPD = 149
X86_INS_DIVPS = 150
X86_INS_FDIVR = 151
X86_INS_FIDIVR = 152
X86_INS_FDIVRP = 153
X86_INS_DIVSD = 154
X86_INS_DIVSS = 155
X86_INS_FDIV = 156
X86_INS_FIDIV = 157
X86_INS_FDIVP = 158
X86_INS_DPPD = 159
X86_INS_DPPS = 160
X86_INS_ENCLS = 161
X86_INS_ENCLU = 162
X86_INS_ENCLV = 163
X86_INS_ENDBR32 = 164
X86_INS_ENDBR64 = 165
X86_INS_ENTER = 166
X86_INS_EXTRACTPS = 167
X86_INS_EXTRQ = 168
X86_INS_F2XM1 = 169
X86_INS_LCALL = 170
X86_INS_LJMP = 171
X86_INS_JMP = 172
X86_INS_FBLD = 173
X86_INS_FBSTP = 174
X86_INS_FCOMPP = 175
X86_INS_FDECSTP = 176
X86_INS_FDISI8087_NOP = 177
X86_INS_FEMMS = 178
X86_INS_FENI8087_NOP = 179
X86_INS_FFREE = 180
X86_INS_FFREEP = 181
X86_INS_FICOM = 182
X86_INS_FICOMP = 183
X86_INS_FINCSTP = 184
X86_INS_FLDCW = 185
X86_INS_FLDENV = 186
X86_INS_FLDL2E = 187
X86_INS_FLDL2T = 188
X86_INS_FLDLG2 = 189
X86_INS_FLDLN2 = 190
X86_INS_FLDPI = 191
X86_INS_FNCLEX = 192
X86_INS_FNINIT = 193
X86_INS_FNOP = 194
X86_INS_FNSTCW = 195
X86_INS_FNSTSW = 196
X86_INS_FPATAN = 197
X86_INS_FSTPNCE = 198
X86_INS_FPREM = 199
X86_INS_FPREM1 = 200
X86_INS_FPTAN = 201
X86_INS_FRNDINT = 202
X86_INS_FRSTOR = 203
X86_INS_FNSAVE = 204
X86_INS_FSCALE = 205
X86_INS_FSETPM = 206
X86_INS_FSINCOS = 207
X86_INS_FNSTENV = 208
X86_INS_FXAM = 209
X86_INS_FXRSTOR = 210
X86_INS_FXRSTOR64 = 211
X86_INS_FXSAVE = 212
X86_INS_FXSAVE64 = 213
X86_INS_FXTRACT = 214
X86_INS_FYL2X = 215
X86_INS_FYL2XP1 = 216
X86_INS_GETSEC = 217
X86_INS_GF2P8AFFINEINVQB = 218
X86_INS_GF2P8AFFINEQB = 219
X86_INS_GF2P8MULB = 220
X86_INS_HADDPD = 221
X86_INS_HADDPS = 222
X86_INS_HLT = 223
X86_INS_HSUBPD = 224
X86_INS_HSUBPS = 225
X86_INS_IDIV = 226
X86_INS_FILD = 227
X86_INS_IMUL = 228
X86_INS_IN = 229
X86_INS_INC = 230
X86_INS_INCSSPD = 231
X86_INS_INCSSPQ = 232
X86_INS_INSB = 233
X86_INS_INSERTPS = 234
X86_INS_INSERTQ = 235
X86_INS_INSD = 236
X86_INS_INSW = 237
X86_INS_INT = 238
X86_INS_INT1 = 239
X86_INS_INT3 = 240
X86_INS_INTO = 241
X86_INS_INVD = 242
X86_INS_INVEPT = 243
X86_INS_INVLPG = 244
X86_INS_INVLPGA = 245
X86_INS_INVPCID = 246
X86_INS_INVVPID = 247
X86_INS_IRET = 248
X86_INS_IRETD = 249
X86_INS_IRETQ = 250
X86_INS_FISTTP = 251
X86_INS_FIST = 252
X86_INS_FISTP = 253
X86_INS_JAE = 254
X86_INS_JA = 255
X86_INS_JBE = 256
X86_INS_JB = 257
X86_INS_JCXZ = 258
X86_INS_JECXZ = 259
X86_INS_JE = 260
X86_INS_JGE = 261
X86_INS_JG = 262
X86_INS_JLE = 263
X86_INS_JL = 264
X86_INS_JNE = 265
X86_INS_JNO = 266
X86_INS_JNP = 267
X86_INS_JNS = 268
X86_INS_JO = 269
X86_INS_JP = 270
X86_INS_JRCXZ = 271
X86_INS_JS = 272
X86_INS_KADDB = 273
X86_INS_KADDD = 274
X86_INS_KADDQ = 275
X86_INS_KADDW = 276
X86_INS_KANDB = 277
X86_INS_KANDD = 278
X86_INS_KANDNB = 279
X86_INS_KANDND = 280
X86_INS_KANDNQ = 281
X86_INS_KANDNW = 282
X86_INS_KANDQ = 283
X86_INS_KANDW = 284
X86_INS_KMOVB = 285
X86_INS_KMOVD = 286
X86_INS_KMOVQ = 287
X86_INS_KMOVW = 288
X86_INS_KNOTB = 289
X86_INS_KNOTD = 290
X86_INS_KNOTQ = 291
X86_INS_KNOTW = 292
X86_INS_KORB = 293
X86_INS_KORD = 294
X86_INS_KORQ = 295
X86_INS_KORTESTB = 296
X86_INS_KORTESTD = 297
X86_INS_KORTESTQ = 298
X86_INS_KORTESTW = 299
X86_INS_KORW = 300
X86_INS_KSHIFTLB = 301
X86_INS_KSHIFTLD = 302
X86_INS_KSHIFTLQ = 303
X86_INS_KSHIFTLW = 304
X86_INS_KSHIFTRB = 305
X86_INS_KSHIFTRD = 306
X86_INS_KSHIFTRQ = 307
X86_INS_KSHIFTRW = 308
X86_INS_KTESTB = 309
X86_INS_KTESTD = 310
X86_INS_KTESTQ = 311
X86_INS_KTESTW = 312
X86_INS_KUNPCKBW = 313
X86_INS_KUNPCKDQ = 314
X86_INS_KUNPCKWD = 315
X86_INS_KXNORB = 316
X86_INS_KXNORD = 317
X86_INS_KXNORQ = 318
X86_INS_KXNORW = 319
X86_INS_KXORB = 320
X86_INS_KXORD = 321
X86_INS_KXORQ = 322
X86_INS_KXORW = 323
X86_INS_LAHF = 324
X86_INS_LAR = 325
X86_INS_LDDQU = 326
X86_INS_LDMXCSR = 327
X86_INS_LDS = 328
X86_INS_FLDZ = 329
X86_INS_FLD1 = 330
X86_INS_FLD = 331
X86_INS_LEA = 332
X86_INS_LEAVE = 333
X86_INS_LES = 334
X86_INS_LFENCE = 335
X86_INS_LFS = 336
X86_INS_LGDT = 337
X86_INS_LGS = 338
X86_INS_LIDT = 339
X86_INS_LLDT = 340
X86_INS_LLWPCB = 341
X86_INS_LMSW = 342
X86_INS_LOCK = 343
X86_INS_LODSB = 344
X86_INS_LODSD = 345
X86_INS_LODSQ = 346
X86_INS_LODSW = 347
X86_INS_LOOP = 348
X86_INS_LOOPE = 349
X86_INS_LOOPNE = 350
X86_INS_RETF = 351
X86_INS_RETFQ = 352
X86_INS_LSL = 353
X86_INS_LSS = 354
X86_INS_LTR = 355
X86_INS_LWPINS = 356
X86_INS_LWPVAL = 357
X86_INS_LZCNT = 358
X86_INS_MASKMOVDQU = 359
X86_INS_MAXPD = 360
X86_INS_MAXPS = 361
X86_INS_MAXSD = 362
X86_INS_MAXSS = 363
X86_INS_MFENCE = 364
X86_INS_MINPD = 365
X86_INS_MINPS = 366
X86_INS_MINSD = 367
X86_INS_MINSS = 368
X86_INS_CVTPD2PI = 369
X86_INS_CVTPI2PD = 370
X86_INS_CVTPI2PS = 371
X86_INS_CVTPS2PI = 372
X86_INS_CVTTPD2PI = 373
X86_INS_CVTTPS2PI = 374
X86_INS_EMMS = 375
X86_INS_MASKMOVQ = 376
X86_INS_MOVD = 377
X86_INS_MOVQ = 378
X86_INS_MOVDQ2Q = 379
X86_INS_MOVNTQ = 380
X86_INS_MOVQ2DQ = 381
X86_INS_PABSB = 382
X86_INS_PABSD = 383
X86_INS_PABSW = 384
X86_INS_PACKSSDW = 385
X86_INS_PACKSSWB = 386
X86_INS_PACKUSWB = 387
X86_INS_PADDB = 388
X86_INS_PADDD = 389
X86_INS_PADDQ = 390
X86_INS_PADDSB = 391
X86_INS_PADDSW = 392
X86_INS_PADDUSB = 393
X86_INS_PADDUSW = 394
X86_INS_PADDW = 395
X86_INS_PALIGNR = 396
X86_INS_PANDN = 397
X86_INS_PAND = 398
X86_INS_PAVGB = 399
X86_INS_PAVGW = 400
X86_INS_PCMPEQB = 401
X86_INS_PCMPEQD = 402
X86_INS_PCMPEQW = 403
X86_INS_PCMPGTB = 404
X86_INS_PCMPGTD = 405
X86_INS_PCMPGTW = 406
X86_INS_PEXTRW = 407
X86_INS_PHADDD = 408
X86_INS_PHADDSW = 409
X86_INS_PHADDW = 410
X86_INS_PHSUBD = 411
X86_INS_PHSUBSW = 412
X86_INS_PHSUBW = 413
X86_INS_PINSRW = 414
X86_INS_PMADDUBSW = 415
X86_INS_PMADDWD = 416
X86_INS_PMAXSW = 417
X86_INS_PMAXUB = 418
X86_INS_PMINSW = 419
X86_INS_PMINUB = 420
X86_INS_PMOVMSKB = 421
X86_INS_PMULHRSW = 422
X86_INS_PMULHUW = 423
X86_INS_PMULHW = 424
X86_INS_PMULLW = 425
X86_INS_PMULUDQ = 426
X86_INS_POR = 427
X86_INS_PSADBW = 428
X86_INS_PSHUFB = 429
X86_INS_PSHUFW = 430
X86_INS_PSIGNB = 431
X86_INS_PSIGND = 432
X86_INS_PSIGNW = 433
X86_INS_PSLLD = 434
X86_INS_PSLLQ = 435
X86_INS_PSLLW = 436
X86_INS_PSRAD = 437
X86_INS_PSRAW = 438
X86_INS_PSRLD = 439
X86_INS_PSRLQ = 440
X86_INS_PSRLW = 441
X86_INS_PSUBB = 442
X86_INS_PSUBD = 443
X86_INS_PSUBQ = 444
X86_INS_PSUBSB = 445
X86_INS_PSUBSW = 446
X86_INS_PSUBUSB = 447
X86_INS_PSUBUSW = 448
X86_INS_PSUBW = 449
X86_INS_PUNPCKHBW = 450
X86_INS_PUNPCKHDQ = 451
X86_INS_PUNPCKHWD = 452
X86_INS_PUNPCKLBW = 453
X86_INS_PUNPCKLDQ = 454
X86_INS_PUNPCKLWD = 455
X86_INS_PXOR = 456
X86_INS_MONITORX = 457
X86_INS_MONITOR = 458
X86_INS_MONTMUL = 459
X86_INS_MOV = 460
X86_INS_MOVABS = 461
X86_INS_MOVAPD = 462
X86_INS_MOVAPS = 463
X86_INS_MOVBE = 464
X86_INS_MOVDDUP = 465
X86_INS_MOVDIR64B = 466
X86_INS_MOVDIRI = 467
X86_INS_MOVDQA = 468
X86_INS_MOVDQU = 469
X86_INS_MOVHLPS = 470
X86_INS_MOVHPD = 471
X86_INS_MOVHPS = 472
X86_INS_MOVLHPS = 473
X86_INS_MOVLPD = 474
X86_INS_MOVLPS = 475
X86_INS_MOVMSKPD = 476
X86_INS_MOVMSKPS = 477
X86_INS_MOVNTDQA = 478
X86_INS_MOVNTDQ = 479
X86_INS_MOVNTI = 480
X86_INS_MOVNTPD = 481
X86_INS_MOVNTPS = 482
X86_INS_MOVNTSD = 483
X86_INS_MOVNTSS = 484
X86_INS_MOVSB = 485
X86_INS_MOVSD = 486
X86_INS_MOVSHDUP = 487
X86_INS_MOVSLDUP = 488
X86_INS_MOVSQ = 489
X86_INS_MOVSS = 490
X86_INS_MOVSW = 491
X86_INS_MOVSX = 492
X86_INS_MOVSXD = 493
X86_INS_MOVUPD = 494
X86_INS_MOVUPS = 495
X86_INS_MOVZX = 496
X86_INS_MPSADBW = 497
X86_INS_MUL = 498
X86_INS_MULPD = 499
X86_INS_MULPS = 500
X86_INS_MULSD = 501
X86_INS_MULSS = 502
X86_INS_MULX = 503
X86_INS_FMUL = 504
X86_INS_FIMUL = 505
X86_INS_FMULP = 506
X86_INS_MWAITX = 507
X86_INS_MWAIT = 508
X86_INS_NEG = 509
X86_INS_NOP = 510
X86_INS_NOT = 511
X86_INS_OR = 512
X86_INS_ORPD = 513
X86_INS_ORPS = 514
X86_INS_OUT = 515
X86_INS_OUTSB = 516
X86_INS_OUTSD = 517
X86_INS_OUTSW = 518
X86_INS_PACKUSDW = 519
X86_INS_PAUSE = 520
X86_INS_PAVGUSB = 521
X86_INS_PBLENDVB = 522
X86_INS_PBLENDW = 523
X86_INS_PCLMULQDQ = 524
X86_INS_PCMPEQQ = 525
X86_INS_PCMPESTRI = 526
X86_INS_PCMPESTRM = 527
X86_INS_PCMPGTQ = 528
X86_INS_PCMPISTRI = 529
X86_INS_PCMPISTRM = 530
X86_INS_PCONFIG = 531
X86_INS_PDEP = 532
X86_INS_PEXT = 533
X86_INS_PEXTRB = 534
X86_INS_PEXTRD = 535
X86_INS_PEXTRQ = 536
X86_INS_PF2ID = 537
X86_INS_PF2IW = 538
X86_INS_PFACC = 539
X86_INS_PFADD = 540
X86_INS_PFCMPEQ = 541
X86_INS_PFCMPGE = 542
X86_INS_PFCMPGT = 543
X86_INS_PFMAX = 544
X86_INS_PFMIN = 545
X86_INS_PFMUL = 546
X86_INS_PFNACC = 547
X86_INS_PFPNACC = 548
X86_INS_PFRCPIT1 = 549
X86_INS_PFRCPIT2 = 550
X86_INS_PFRCP = 551
X86_INS_PFRSQIT1 = 552
X86_INS_PFRSQRT = 553
X86_INS_PFSUBR = 554
X86_INS_PFSUB = 555
X86_INS_PHMINPOSUW = 556
X86_INS_PI2FD = 557
X86_INS_PI2FW = 558
X86_INS_PINSRB = 559
X86_INS_PINSRD = 560
X86_INS_PINSRQ = 561
X86_INS_PMAXSB = 562
X86_INS_PMAXSD = 563
X86_INS_PMAXUD = 564
X86_INS_PMAXUW = 565
X86_INS_PMINSB = 566
X86_INS_PMINSD = 567
X86_INS_PMINUD = 568
X86_INS_PMINUW = 569
X86_INS_PMOVSXBD = 570
X86_INS_PMOVSXBQ = 571
X86_INS_PMOVSXBW = 572
X86_INS_PMOVSXDQ = 573
X86_INS_PMOVSXWD = 574
X86_INS_PMOVSXWQ = 575
X86_INS_PMOVZXBD = 576
X86_INS_PMOVZXBQ = 577
X86_INS_PMOVZXBW = 578
X86_INS_PMOVZXDQ = 579
X86_INS_PMOVZXWD = 580
X86_INS_PMOVZXWQ = 581
X86_INS_PMULDQ = 582
X86_INS_PMULHRW = 583
X86_INS_PMULLD = 584
X86_INS_POP = 585
X86_INS_POPAW = 586
X86_INS_POPAL = 587
X86_INS_POPCNT = 588
X86_INS_POPF = 589
X86_INS_POPFD = 590
X86_INS_POPFQ = 591
X86_INS_PREFETCH = 592
X86_INS_PREFETCHNTA = 593
X86_INS_PREFETCHT0 = 594
X86_INS_PREFETCHT1 = 595
X86_INS_PREFETCHT2 = 596
X86_INS_PREFETCHW = 597
X86_INS_PREFETCHWT1 = 598
X86_INS_PSHUFD = 599
X86_INS_PSHUFHW = 600
X86_INS_PSHUFLW = 601
X86_INS_PSLLDQ = 602
X86_INS_PSRLDQ = 603
X86_INS_PSWAPD = 604
X86_INS_PTEST = 605
X86_INS_PTWRITE = 606
X86_INS_PUNPCKHQDQ = 607
X86_INS_PUNPCKLQDQ = 608
X86_INS_PUSH = 609
X86_INS_PUSHAW = 610
X86_INS_PUSHAL = 611
X86_INS_PUSHF = 612
X86_INS_PUSHFD = 613
X86_INS_PUSHFQ = 614
X86_INS_RCL = 615
X86_INS_RCPPS = 616
X86_INS_RCPSS = 617
X86_INS_RCR = 618
X86_INS_RDFSBASE = 619
X86_INS_RDGSBASE = 620
X86_INS_RDMSR = 621
X86_INS_RDPID = 622
X86_INS_RDPKRU = 623
X86_INS_RDPMC = 624
X86_INS_RDRAND = 625
X86_INS_RDSEED = 626
X86_INS_RDSSPD = 627
X86_INS_RDSSPQ = 628
X86_INS_RDTSC = 629
X86_INS_RDTSCP = 630
X86_INS_REPNE = 631
X86_INS_REP = 632
X86_INS_RET = 633
X86_INS_REX64 = 634
X86_INS_ROL = 635
X86_INS_ROR = 636
X86_INS_RORX = 637
X86_INS_ROUNDPD = 638
X86_INS_ROUNDPS = 639
X86_INS_ROUNDSD = 640
X86_INS_ROUNDSS = 641
X86_INS_RSM = 642
X86_INS_RSQRTPS = 643
X86_INS_RSQRTSS = 644
X86_INS_RSTORSSP = 645
X86_INS_SAHF = 646
X86_INS_SAL = 647
X86_INS_SALC = 648
X86_INS_SAR = 649
X86_INS_SARX = 650
X86_INS_SAVEPREVSSP = 651
X86_INS_SBB = 652
X86_INS_SCASB = 653
X86_INS_SCASD = 654
X86_INS_SCASQ = 655
X86_INS_SCASW = 656
X86_INS_SETAE = 657
X86_INS_SETA = 658
X86_INS_SETBE = 659
X86_INS_SETB = 660
X86_INS_SETE = 661
X86_INS_SETGE = 662
X86_INS_SETG = 663
X86_INS_SETLE = 664
X86_INS_SETL = 665
X86_INS_SETNE = 666
X86_INS_SETNO = 667
X86_INS_SETNP = 668
X86_INS_SETNS = 669
X86_INS_SETO = 670
X86_INS_SETP = 671
X86_INS_SETSSBSY = 672
X86_INS_SETS = 673
X86_INS_SFENCE = 674
X86_INS_SGDT = 675
X86_INS_SHA1MSG1 = 676
X86_INS_SHA1MSG2 = 677
X86_INS_SHA1NEXTE = 678
X86_INS_SHA1RNDS4 = 679
X86_INS_SHA256MSG1 = 680
X86_INS_SHA256MSG2 = 681
X86_INS_SHA256RNDS2 = 682
X86_INS_SHL = 683
X86_INS_SHLD = 684
X86_INS_SHLX = 685
X86_INS_SHR = 686
X86_INS_SHRD = 687
X86_INS_SHRX = 688
X86_INS_SHUFPD = 689
X86_INS_SHUFPS = 690
X86_INS_SIDT = 691
X86_INS_FSIN = 692
X86_INS_SKINIT = 693
X86_INS_SLDT = 694
X86_INS_SLWPCB = 695
X86_INS_SMSW = 696
X86_INS_SQRTPD = 697
X86_INS_SQRTPS = 698
X86_INS_SQRTSD = 699
X86_INS_SQRTSS = 700
X86_INS_FSQRT = 701
X86_INS_STAC = 702
X86_INS_STC = 703
X86_INS_STD = 704
X86_INS_STGI = 705
X86_INS_STI = 706
X86_INS_STMXCSR = 707
X86_INS_STOSB = 708
X86_INS_STOSD = 709
X86_INS_STOSQ = 710
X86_INS_STOSW = 711
X86_INS_STR = 712
X86_INS_FST = 713
X86_INS_FSTP = 714
X86_INS_SUB = 715
X86_INS_SUBPD = 716
X86_INS_SUBPS = 717
X86_INS_FSUBR = 718
X86_INS_FISUBR = 719
X86_INS_FSUBRP = 720
X86_INS_SUBSD = 721
X86_INS_SUBSS = 722
X86_INS_FSUB = 723
X86_INS_FISUB = 724
X86_INS_FSUBP = 725
X86_INS_SWAPGS = 726
X86_INS_SYSCALL = 727
X86_INS_SYSENTER = 728
X86_INS_SYSEXIT = 729
X86_INS_SYSEXITQ = 730
X86_INS_SYSRET = 731
X86_INS_SYSRETQ = 732
X86_INS_T1MSKC = 733
X86_INS_TEST = 734
X86_INS_TPAUSE = 735
X86_INS_FTST = 736
X86_INS_TZCNT = 737
X86_INS_TZMSK = 738
X86_INS_UCOMISD = 739
X86_INS_UCOMISS = 740
X86_INS_FUCOMPI = 741
X86_INS_FUCOMI = 742
X86_INS_FUCOMPP = 743
X86_INS_FUCOMP = 744
X86_INS_FUCOM = 745
X86_INS_UD0 = 746
X86_INS_UD1 = 747
X86_INS_UD2 = 748
X86_INS_UMONITOR = 749
X86_INS_UMWAIT = 750
X86_INS_UNPCKHPD = 751
X86_INS_UNPCKHPS = 752
X86_INS_UNPCKLPD = 753
X86_INS_UNPCKLPS = 754
X86_INS_V4FMADDPS = 755
X86_INS_V4FMADDSS = 756
X86_INS_V4FNMADDPS = 757
X86_INS_V4FNMADDSS = 758
X86_INS_VADDPD = 759
X86_INS_VADDPS = 760
X86_INS_VADDSD = 761
X86_INS_VADDSS = 762
X86_INS_VADDSUBPD = 763
X86_INS_VADDSUBPS = 764
X86_INS_VAESDECLAST = 765
X86_INS_VAESDEC = 766
X86_INS_VAESENCLAST = 767
X86_INS_VAESENC = 768
X86_INS_VAESIMC = 769
X86_INS_VAESKEYGENASSIST = 770
X86_INS_VALIGND = 771
X86_INS_VALIGNQ = 772
X86_INS_VANDNPD = 773
X86_INS_VANDNPS = 774
X86_INS_VANDPD = 775
X86_INS_VANDPS = 776
X86_INS_VBLENDMPD = 777
X86_INS_VBLENDMPS = 778
X86_INS_VBLENDPD = 779
X86_INS_VBLENDPS = 780
X86_INS_VBLENDVPD = 781
X86_INS_VBLENDVPS = 782
X86_INS_VBROADCASTF128 = 783
X86_INS_VBROADCASTF32X2 = 784
X86_INS_VBROADCASTF32X4 = 785
X86_INS_VBROADCASTF32X8 = 786
X86_INS_VBROADCASTF64X2 = 787
X86_INS_VBROADCASTF64X4 = 788
X86_INS_VBROADCASTI128 = 789
X86_INS_VBROADCASTI32X2 = 790
X86_INS_VBROADCASTI32X4 = 791
X86_INS_VBROADCASTI32X8 = 792
X86_INS_VBROADCASTI64X2 = 793
X86_INS_VBROADCASTI64X4 = 794
X86_INS_VBROADCASTSD = 795
X86_INS_VBROADCASTSS = 796
X86_INS_VCMP = 797
X86_INS_VCMPPD = 798
X86_INS_VCMPPS = 799
X86_INS_VCMPSD = 800
X86_INS_VCMPSS = 801
X86_INS_VCOMISD = 802
X86_INS_VCOMISS = 803
X86_INS_VCOMPRESSPD = 804
X86_INS_VCOMPRESSPS = 805
X86_INS_VCVTDQ2PD = 806
X86_INS_VCVTDQ2PS = 807
X86_INS_VCVTPD2DQ = 808
X86_INS_VCVTPD2PS = 809
X86_INS_VCVTPD2QQ = 810
X86_INS_VCVTPD2UDQ = 811
X86_INS_VCVTPD2UQQ = 812
X86_INS_VCVTPH2PS = 813
X86_INS_VCVTPS2DQ = 814
X86_INS_VCVTPS2PD = 815
X86_INS_VCVTPS2PH = 816
X86_INS_VCVTPS2QQ = 817
X86_INS_VCVTPS2UDQ = 818
X86_INS_VCVTPS2UQQ = 819
X86_INS_VCVTQQ2PD = 820
X86_INS_VCVTQQ2PS = 821
X86_INS_VCVTSD2SI = 822
X86_INS_VCVTSD2SS = 823
X86_INS_VCVTSD2USI = 824
X86_INS_VCVTSI2SD = 825
X86_INS_VCVTSI2SS = 826
X86_INS_VCVTSS2SD = 827
X86_INS_VCVTSS2SI = 828
X86_INS_VCVTSS2USI = 829
X86_INS_VCVTTPD2DQ = 830
X86_INS_VCVTTPD2QQ = 831
X86_INS_VCVTTPD2UDQ = 832
X86_INS_VCVTTPD2UQQ = 833
X86_INS_VCVTTPS2DQ = 834
X86_INS_VCVTTPS2QQ = 835
X86_INS_VCVTTPS2UDQ = 836
X86_INS_VCVTTPS2UQQ = 837
X86_INS_VCVTTSD2SI = 838
X86_INS_VCVTTSD2USI = 839
X86_INS_VCVTTSS2SI = 840
X86_INS_VCVTTSS2USI = 841
X86_INS_VCVTUDQ2PD = 842
X86_INS_VCVTUDQ2PS = 843
X86_INS_VCVTUQQ2PD = 844
X86_INS_VCVTUQQ2PS = 845
X86_INS_VCVTUSI2SD = 846
X86_INS_VCVTUSI2SS = 847
X86_INS_VDBPSADBW = 848
X86_INS_VDIVPD = 849
X86_INS_VDIVPS = 850
X86_INS_VDIVSD = 851
X86_INS_VDIVSS = 852
X86_INS_VDPPD = 853
X86_INS_VDPPS = 854
X86_INS_VERR = 855
X86_INS_VERW = 856
X86_INS_VEXP2PD = 857
X86_INS_VEXP2PS = 858
X86_INS_VEXPANDPD = 859
X86_INS_VEXPANDPS = 860
X86_INS_VEXTRACTF128 = 861
X86_INS_VEXTRACTF32X4 = 862
X86_INS_VEXTRACTF32X8 = 863
X86_INS_VEXTRACTF64X2 = 864
X86_INS_VEXTRACTF64X4 = 865
X86_INS_VEXTRACTI128 = 866
X86_INS_VEXTRACTI32X4 = 867
X86_INS_VEXTRACTI32X8 = 868
X86_INS_VEXTRACTI64X2 = 869
X86_INS_VEXTRACTI64X4 = 870
X86_INS_VEXTRACTPS = 871
X86_INS_VFIXUPIMMPD = 872
X86_INS_VFIXUPIMMPS = 873
X86_INS_VFIXUPIMMSD = 874
X86_INS_VFIXUPIMMSS = 875
X86_INS_VFMADD132PD = 876
X86_INS_VFMADD132PS = 877
X86_INS_VFMADD132SD = 878
X86_INS_VFMADD132SS = 879
X86_INS_VFMADD213PD = 880
X86_INS_VFMADD213PS = 881
X86_INS_VFMADD213SD = 882
X86_INS_VFMADD213SS = 883
X86_INS_VFMADD231PD = 884
X86_INS_VFMADD231PS = 885
X86_INS_VFMADD231SD = 886
X86_INS_VFMADD231SS = 887
X86_INS_VFMADDPD = 888
X86_INS_VFMADDPS = 889
X86_INS_VFMADDSD = 890
X86_INS_VFMADDSS = 891
X86_INS_VFMADDSUB132PD = 892
X86_INS_VFMADDSUB132PS = 893
X86_INS_VFMADDSUB213PD = 894
X86_INS_VFMADDSUB213PS = 895
X86_INS_VFMADDSUB231PD = 896
X86_INS_VFMADDSUB231PS = 897
X86_INS_VFMADDSUBPD = 898
X86_INS_VFMADDSUBPS = 899
X86_INS_VFMSUB132PD = 900
X86_INS_VFMSUB132PS = 901
X86_INS_VFMSUB132SD = 902
X86_INS_VFMSUB132SS = 903
X86_INS_VFMSUB213PD = 904
X86_INS_VFMSUB213PS = 905
X86_INS_VFMSUB213SD = 906
X86_INS_VFMSUB213SS = 907
X86_INS_VFMSUB231PD = 908
X86_INS_VFMSUB231PS = 909
X86_INS_VFMSUB231SD = 910
X86_INS_VFMSUB231SS = 911
X86_INS_VFMSUBADD132PD = 912
X86_INS_VFMSUBADD132PS = 913
X86_INS_VFMSUBADD213PD = 914
X86_INS_VFMSUBADD213PS = 915
X86_INS_VFMSUBADD231PD = 916
X86_INS_VFMSUBADD231PS = 917
X86_INS_VFMSUBADDPD = 918
X86_INS_VFMSUBADDPS = 919
X86_INS_VFMSUBPD = 920
X86_INS_VFMSUBPS = 921
X86_INS_VFMSUBSD = 922
X86_INS_VFMSUBSS = 923
X86_INS_VFNMADD132PD = 924
X86_INS_VFNMADD132PS = 925
X86_INS_VFNMADD132SD = 926
X86_INS_VFNMADD132SS = 927
X86_INS_VFNMADD213PD = 928
X86_INS_VFNMADD213PS = 929
X86_INS_VFNMADD213SD = 930
X86_INS_VFNMADD213SS = 931
X86_INS_VFNMADD231PD = 932
X86_INS_VFNMADD231PS = 933
X86_INS_VFNMADD231SD = 934
X86_INS_VFNMADD231SS = 935
X86_INS_VFNMADDPD = 936
X86_INS_VFNMADDPS = 937
X86_INS_VFNMADDSD = 938
X86_INS_VFNMADDSS = 939
X86_INS_VFNMSUB132PD = 940
X86_INS_VFNMSUB132PS = 941
X86_INS_VFNMSUB132SD = 942
X86_INS_VFNMSUB132SS = 943
X86_INS_VFNMSUB213PD = 944
X86_INS_VFNMSUB213PS = 945
X86_INS_VFNMSUB213SD = 946
X86_INS_VFNMSUB213SS = 947
X86_INS_VFNMSUB231PD = 948
X86_INS_VFNMSUB231PS = 949
X86_INS_VFNMSUB231SD = 950
X86_INS_VFNMSUB231SS = 951
X86_INS_VFNMSUBPD = 952
X86_INS_VFNMSUBPS = 953
X86_INS_VFNMSUBSD = 954
X86_INS_VFNMSUBSS = 955
X86_INS_VFPCLASSPD = 956
X86_INS_VFPCLASSPS = 957
X86_INS_VFPCLASSSD = 958
X86_INS_VFPCLASSSS = 959
X86_INS_VFRCZPD = 960
X86_INS_VFRCZPS = 961
X86_INS_VFRCZSD = 962
X86_INS_VFRCZSS = 963
X86_INS_VGATHERDPD = 964
X86_INS_VGATHERDPS = 965
X86_INS_VGATHERPF0DPD = 966
X86_INS_VGATHERPF0DPS = 967
X86_INS_VGATHERPF0QPD = 968
X86_INS_VGATHERPF0QPS = 969
X86_INS_VGATHERPF1DPD = 970
X86_INS_VGATHERPF1DPS = 971
X86_INS_VGATHERPF1QPD = 972
X86_INS_VGATHERPF1QPS = 973
X86_INS_VGATHERQPD = 974
X86_INS_VGATHERQPS = 975
X86_INS_VGETEXPPD = 976
X86_INS_VGETEXPPS = 977
X86_INS_VGETEXPSD = 978
X86_INS_VGETEXPSS = 979
X86_INS_VGETMANTPD = 980
X86_INS_VGETMANTPS = 981
X86_INS_VGETMANTSD = 982
X86_INS_VGETMANTSS = 983
X86_INS_VGF2P8AFFINEINVQB = 984
X86_INS_VGF2P8AFFINEQB = 985
X86_INS_VGF2P8MULB = 986
X86_INS_VHADDPD = 987
X86_INS_VHADDPS = 988
X86_INS_VHSUBPD = 989
X86_INS_VHSUBPS = 990
X86_INS_VINSERTF128 = 991
X86_INS_VINSERTF32X4 = 992
X86_INS_VINSERTF32X8 = 993
X86_INS_VINSERTF64X2 = 994
X86_INS_VINSERTF64X4 = 995
X86_INS_VINSERTI128 = 996
X86_INS_VINSERTI32X4 = 997
X86_INS_VINSERTI32X8 = 998
X86_INS_VINSERTI64X2 = 999
X86_INS_VINSERTI64X4 = 1000
X86_INS_VINSERTPS = 1001
X86_INS_VLDDQU = 1002
X86_INS_VLDMXCSR = 1003
X86_INS_VMASKMOVDQU = 1004
X86_INS_VMASKMOVPD = 1005
X86_INS_VMASKMOVPS = 1006
X86_INS_VMAXPD = 1007
X86_INS_VMAXPS = 1008
X86_INS_VMAXSD = 1009
X86_INS_VMAXSS = 1010
X86_INS_VMCALL = 1011
X86_INS_VMCLEAR = 1012
X86_INS_VMFUNC = 1013
X86_INS_VMINPD = 1014
X86_INS_VMINPS = 1015
X86_INS_VMINSD = 1016
X86_INS_VMINSS = 1017
X86_INS_VMLAUNCH = 1018
X86_INS_VMLOAD = 1019
X86_INS_VMMCALL = 1020
X86_INS_VMOVQ = 1021
X86_INS_VMOVAPD = 1022
X86_INS_VMOVAPS = 1023
X86_INS_VMOVDDUP = 1024
X86_INS_VMOVD = 1025
X86_INS_VMOVDQA32 = 1026
X86_INS_VMOVDQA64 = 1027
X86_INS_VMOVDQA = 1028
X86_INS_VMOVDQU16 = 1029
X86_INS_VMOVDQU32 = 1030
X86_INS_VMOVDQU64 = 1031
X86_INS_VMOVDQU8 = 1032
X86_INS_VMOVDQU = 1033
X86_INS_VMOVHLPS = 1034
X86_INS_VMOVHPD = 1035
X86_INS_VMOVHPS = 1036
X86_INS_VMOVLHPS = 1037
X86_INS_VMOVLPD = 1038
X86_INS_VMOVLPS = 1039
X86_INS_VMOVMSKPD = 1040
X86_INS_VMOVMSKPS = 1041
X86_INS_VMOVNTDQA = 1042
X86_INS_VMOVNTDQ = 1043
X86_INS_VMOVNTPD = 1044
X86_INS_VMOVNTPS = 1045
X86_INS_VMOVSD = 1046
X86_INS_VMOVSHDUP = 1047
X86_INS_VMOVSLDUP = 1048
X86_INS_VMOVSS = 1049
X86_INS_VMOVUPD = 1050
X86_INS_VMOVUPS = 1051
X86_INS_VMPSADBW = 1052
X86_INS_VMPTRLD = 1053
X86_INS_VMPTRST = 1054
X86_INS_VMREAD = 1055
X86_INS_VMRESUME = 1056
X86_INS_VMRUN = 1057
X86_INS_VMSAVE = 1058
X86_INS_VMULPD = 1059
X86_INS_VMULPS = 1060
X86_INS_VMULSD = 1061
X86_INS_VMULSS = 1062
X86_INS_VMWRITE = 1063
X86_INS_VMXOFF = 1064
X86_INS_VMXON = 1065
X86_INS_VORPD = 1066
X86_INS_VORPS = 1067
X86_INS_VP4DPWSSDS = 1068
X86_INS_VP4DPWSSD = 1069
X86_INS_VPABSB = 1070
X86_INS_VPABSD = 1071
X86_INS_VPABSQ = 1072
X86_INS_VPABSW = 1073
X86_INS_VPACKSSDW = 1074
X86_INS_VPACKSSWB = 1075
X86_INS_VPACKUSDW = 1076
X86_INS_VPACKUSWB = 1077
X86_INS_VPADDB = 1078
X86_INS_VPADDD = 1079
X86_INS_VPADDQ = 1080
X86_INS_VPADDSB = 1081
X86_INS_VPADDSW = 1082
X86_INS_VPADDUSB = 1083
X86_INS_VPADDUSW = 1084
X86_INS_VPADDW = 1085
X86_INS_VPALIGNR = 1086
X86_INS_VPANDD = 1087
X86_INS_VPANDND = 1088
X86_INS_VPANDNQ = 1089
X86_INS_VPANDN = 1090
X86_INS_VPANDQ = 1091
X86_INS_VPAND = 1092
X86_INS_VPAVGB = 1093
X86_INS_VPAVGW = 1094
X86_INS_VPBLENDD = 1095
X86_INS_VPBLENDMB = 1096
X86_INS_VPBLENDMD = 1097
X86_INS_VPBLENDMQ = 1098
X86_INS_VPBLENDMW = 1099
X86_INS_VPBLENDVB = 1100
X86_INS_VPBLENDW = 1101
X86_INS_VPBROADCASTB = 1102
X86_INS_VPBROADCASTD = 1103
X86_INS_VPBROADCASTMB2Q = 1104
X86_INS_VPBROADCASTMW2D = 1105
X86_INS_VPBROADCASTQ = 1106
X86_INS_VPBROADCASTW = 1107
X86_INS_VPCLMULQDQ = 1108
X86_INS_VPCMOV = 1109
X86_INS_VPCMP = 1110
X86_INS_VPCMPB = 1111
X86_INS_VPCMPD = 1112
X86_INS_VPCMPEQB = 1113
X86_INS_VPCMPEQD = 1114
X86_INS_VPCMPEQQ = 1115
X86_INS_VPCMPEQW = 1116
X86_INS_VPCMPESTRI = 1117
X86_INS_VPCMPESTRM = 1118
X86_INS_VPCMPGTB = 1119
X86_INS_VPCMPGTD = 1120
X86_INS_VPCMPGTQ = 1121
X86_INS_VPCMPGTW = 1122
X86_INS_VPCMPISTRI = 1123
X86_INS_VPCMPISTRM = 1124
X86_INS_VPCMPQ = 1125
X86_INS_VPCMPUB = 1126
X86_INS_VPCMPUD = 1127
X86_INS_VPCMPUQ = 1128
X86_INS_VPCMPUW = 1129
X86_INS_VPCMPW = 1130
X86_INS_VPCOM = 1131
X86_INS_VPCOMB = 1132
X86_INS_VPCOMD = 1133
X86_INS_VPCOMPRESSB = 1134
X86_INS_VPCOMPRESSD = 1135
X86_INS_VPCOMPRESSQ = 1136
X86_INS_VPCOMPRESSW = 1137
X86_INS_VPCOMQ = 1138
X86_INS_VPCOMUB = 1139
X86_INS_VPCOMUD = 1140
X86_INS_VPCOMUQ = 1141
X86_INS_VPCOMUW = 1142
X86_INS_VPCOMW = 1143
X86_INS_VPCONFLICTD = 1144
X86_INS_VPCONFLICTQ = 1145
X86_INS_VPDPBUSDS = 1146
X86_INS_VPDPBUSD = 1147
X86_INS_VPDPWSSDS = 1148
X86_INS_VPDPWSSD = 1149
X86_INS_VPERM2F128 = 1150
X86_INS_VPERM2I128 = 1151
X86_INS_VPERMB = 1152
X86_INS_VPERMD = 1153
X86_INS_VPERMI2B = 1154
X86_INS_VPERMI2D = 1155
X86_INS_VPERMI2PD = 1156
X86_INS_VPERMI2PS = 1157
X86_INS_VPERMI2Q = 1158
X86_INS_VPERMI2W = 1159
X86_INS_VPERMIL2PD = 1160
X86_INS_VPERMILPD = 1161
X86_INS_VPERMIL2PS = 1162
X86_INS_VPERMILPS = 1163
X86_INS_VPERMPD = 1164
X86_INS_VPERMPS = 1165
X86_INS_VPERMQ = 1166
X86_INS_VPERMT2B = 1167
X86_INS_VPERMT2D = 1168
X86_INS_VPERMT2PD = 1169
X86_INS_VPERMT2PS = 1170
X86_INS_VPERMT2Q = 1171
X86_INS_VPERMT2W = 1172
X86_INS_VPERMW = 1173
X86_INS_VPEXPANDB = 1174
X86_INS_VPEXPANDD = 1175
X86_INS_VPEXPANDQ = 1176
X86_INS_VPEXPANDW = 1177
X86_INS_VPEXTRB = 1178
X86_INS_VPEXTRD = 1179
X86_INS_VPEXTRQ = 1180
X86_INS_VPEXTRW = 1181
X86_INS_VPGATHERDD = 1182
X86_INS_VPGATHERDQ = 1183
X86_INS_VPGATHERQD = 1184
X86_INS_VPGATHERQQ = 1185
X86_INS_VPHADDBD = 1186
X86_INS_VPHADDBQ = 1187
X86_INS_VPHADDBW = 1188
X86_INS_VPHADDDQ = 1189
X86_INS_VPHADDD = 1190
X86_INS_VPHADDSW = 1191
X86_INS_VPHADDUBD = 1192
X86_INS_VPHADDUBQ = 1193
X86_INS_VPHADDUBW = 1194
X86_INS_VPHADDUDQ = 1195
X86_INS_VPHADDUWD = 1196
X86_INS_VPHADDUWQ = 1197
X86_INS_VPHADDWD = 1198
X86_INS_VPHADDWQ = 1199
X86_INS_VPHADDW = 1200
X86_INS_VPHMINPOSUW = 1201
X86_INS_VPHSUBBW = 1202
X86_INS_VPHSUBDQ = 1203
X86_INS_VPHSUBD = 1204
X86_INS_VPHSUBSW = 1205
X86_INS_VPHSUBWD = 1206
X86_INS_VPHSUBW = 1207
X86_INS_VPINSRB = 1208
X86_INS_VPINSRD = 1209
X86_INS_VPINSRQ = 1210
X86_INS_VPINSRW = 1211
X86_INS_VPLZCNTD = 1212
X86_INS_VPLZCNTQ = 1213
X86_INS_VPMACSDD = 1214
X86_INS_VPMACSDQH = 1215
X86_INS_VPMACSDQL = 1216
X86_INS_VPMACSSDD = 1217
X86_INS_VPMACSSDQH = 1218
X86_INS_VPMACSSDQL = 1219
X86_INS_VPMACSSWD = 1220
X86_INS_VPMACSSWW = 1221
X86_INS_VPMACSWD = 1222
X86_INS_VPMACSWW = 1223
X86_INS_VPMADCSSWD = 1224
X86_INS_VPMADCSWD = 1225
X86_INS_VPMADD52HUQ = 1226
X86_INS_VPMADD52LUQ = 1227
X86_INS_VPMADDUBSW = 1228
X86_INS_VPMADDWD = 1229
X86_INS_VPMASKMOVD = 1230
X86_INS_VPMASKMOVQ = 1231
X86_INS_VPMAXSB = 1232
X86_INS_VPMAXSD = 1233
X86_INS_VPMAXSQ = 1234
X86_INS_VPMAXSW = 1235
X86_INS_VPMAXUB = 1236
X86_INS_VPMAXUD = 1237
X86_INS_VPMAXUQ = 1238
X86_INS_VPMAXUW = 1239
X86_INS_VPMINSB = 1240
X86_INS_VPMINSD = 1241
X86_INS_VPMINSQ = 1242
X86_INS_VPMINSW = 1243
X86_INS_VPMINUB = 1244
X86_INS_VPMINUD = 1245
X86_INS_VPMINUQ = 1246
X86_INS_VPMINUW = 1247
X86_INS_VPMOVB2M = 1248
X86_INS_VPMOVD2M = 1249
X86_INS_VPMOVDB = 1250
X86_INS_VPMOVDW = 1251
X86_INS_VPMOVM2B = 1252
X86_INS_VPMOVM2D = 1253
X86_INS_VPMOVM2Q = 1254
X86_INS_VPMOVM2W = 1255
X86_INS_VPMOVMSKB = 1256
X86_INS_VPMOVQ2M = 1257
X86_INS_VPMOVQB = 1258
X86_INS_VPMOVQD = 1259
X86_INS_VPMOVQW = 1260
X86_INS_VPMOVSDB = 1261
X86_INS_VPMOVSDW = 1262
X86_INS_VPMOVSQB = 1263
X86_INS_VPMOVSQD = 1264
X86_INS_VPMOVSQW = 1265
X86_INS_VPMOVSWB = 1266
X86_INS_VPMOVSXBD = 1267
X86_INS_VPMOVSXBQ = 1268
X86_INS_VPMOVSXBW = 1269
X86_INS_VPMOVSXDQ = 1270
X86_INS_VPMOVSXWD = 1271
X86_INS_VPMOVSXWQ = 1272
X86_INS_VPMOVUSDB = 1273
X86_INS_VPMOVUSDW = 1274
X86_INS_VPMOVUSQB = 1275
X86_INS_VPMOVUSQD = 1276
X86_INS_VPMOVUSQW = 1277
X86_INS_VPMOVUSWB = 1278
X86_INS_VPMOVW2M = 1279
X86_INS_VPMOVWB = 1280
X86_INS_VPMOVZXBD = 1281
X86_INS_VPMOVZXBQ = 1282
X86_INS_VPMOVZXBW = 1283
X86_INS_VPMOVZXDQ = 1284
X86_INS_VPMOVZXWD = 1285
X86_INS_VPMOVZXWQ = 1286
X86_INS_VPMULDQ = 1287
X86_INS_VPMULHRSW = 1288
X86_INS_VPMULHUW = 1289
X86_INS_VPMULHW = 1290
X86_INS_VPMULLD = 1291
X86_INS_VPMULLQ = 1292
X86_INS_VPMULLW = 1293
X86_INS_VPMULTISHIFTQB = 1294
X86_INS_VPMULUDQ = 1295
X86_INS_VPOPCNTB = 1296
X86_INS_VPOPCNTD = 1297
X86_INS_VPOPCNTQ = 1298
X86_INS_VPOPCNTW = 1299
X86_INS_VPORD = 1300
X86_INS_VPORQ = 1301
X86_INS_VPOR = 1302
X86_INS_VPPERM = 1303
X86_INS_VPROLD = 1304
X86_INS_VPROLQ = 1305
X86_INS_VPROLVD = 1306
X86_INS_VPROLVQ = 1307
X86_INS_VPRORD = 1308
X86_INS_VPRORQ = 1309
X86_INS_VPRORVD = 1310
X86_INS_VPRORVQ = 1311
X86_INS_VPROTB = 1312
X86_INS_VPROTD = 1313
X86_INS_VPROTQ = 1314
X86_INS_VPROTW = 1315
X86_INS_VPSADBW = 1316
X86_INS_VPSCATTERDD = 1317
X86_INS_VPSCATTERDQ = 1318
X86_INS_VPSCATTERQD = 1319
X86_INS_VPSCATTERQQ = 1320
X86_INS_VPSHAB = 1321
X86_INS_VPSHAD = 1322
X86_INS_VPSHAQ = 1323
X86_INS_VPSHAW = 1324
X86_INS_VPSHLB = 1325
X86_INS_VPSHLDD = 1326
X86_INS_VPSHLDQ = 1327
X86_INS_VPSHLDVD = 1328
X86_INS_VPSHLDVQ = 1329
X86_INS_VPSHLDVW = 1330
X86_INS_VPSHLDW = 1331
X86_INS_VPSHLD = 1332
X86_INS_VPSHLQ = 1333
X86_INS_VPSHLW = 1334
X86_INS_VPSHRDD = 1335
X86_INS_VPSHRDQ = 1336
X86_INS_VPSHRDVD = 1337
X86_INS_VPSHRDVQ = 1338
X86_INS_VPSHRDVW = 1339
X86_INS_VPSHRDW = 1340
X86_INS_VPSHUFBITQMB = 1341
X86_INS_VPSHUFB = 1342
X86_INS_VPSHUFD = 1343
X86_INS_VPSHUFHW = 1344
X86_INS_VPSHUFLW = 1345
X86_INS_VPSIGNB = 1346
X86_INS_VPSIGND = 1347
X86_INS_VPSIGNW = 1348
X86_INS_VPSLLDQ = 1349
X86_INS_VPSLLD = 1350
X86_INS_VPSLLQ = 1351
X86_INS_VPSLLVD = 1352
X86_INS_VPSLLVQ = 1353
X86_INS_VPSLLVW = 1354
X86_INS_VPSLLW = 1355
X86_INS_VPSRAD = 1356
X86_INS_VPSRAQ = 1357
X86_INS_VPSRAVD = 1358
X86_INS_VPSRAVQ = 1359
X86_INS_VPSRAVW = 1360
X86_INS_VPSRAW = 1361
X86_INS_VPSRLDQ = 1362
X86_INS_VPSRLD = 1363
X86_INS_VPSRLQ = 1364
X86_INS_VPSRLVD = 1365
X86_INS_VPSRLVQ = 1366
X86_INS_VPSRLVW = 1367
X86_INS_VPSRLW = 1368
X86_INS_VPSUBB = 1369
X86_INS_VPSUBD = 1370
X86_INS_VPSUBQ = 1371
X86_INS_VPSUBSB = 1372
X86_INS_VPSUBSW = 1373
X86_INS_VPSUBUSB = 1374
X86_INS_VPSUBUSW = 1375
X86_INS_VPSUBW = 1376
X86_INS_VPTERNLOGD = 1377
X86_INS_VPTERNLOGQ = 1378
X86_INS_VPTESTMB = 1379
X86_INS_VPTESTMD = 1380
X86_INS_VPTESTMQ = 1381
X86_INS_VPTESTMW = 1382
X86_INS_VPTESTNMB = 1383
X86_INS_VPTESTNMD = 1384
X86_INS_VPTESTNMQ = 1385
X86_INS_VPTESTNMW = 1386
X86_INS_VPTEST = 1387
X86_INS_VPUNPCKHBW = 1388
X86_INS_VPUNPCKHDQ = 1389
X86_INS_VPUNPCKHQDQ = 1390
X86_INS_VPUNPCKHWD = 1391
X86_INS_VPUNPCKLBW = 1392
X86_INS_VPUNPCKLDQ = 1393
X86_INS_VPUNPCKLQDQ = 1394
X86_INS_VPUNPCKLWD = 1395
X86_INS_VPXORD = 1396
X86_INS_VPXORQ = 1397
X86_INS_VPXOR = 1398
X86_INS_VRANGEPD = 1399
X86_INS_VRANGEPS = 1400
X86_INS_VRANGESD = 1401
X86_INS_VRANGESS = 1402
X86_INS_VRCP14PD = 1403
X86_INS_VRCP14PS = 1404
X86_INS_VRCP14SD = 1405
X86_INS_VRCP14SS = 1406
X86_INS_VRCP28PD = 1407
X86_INS_VRCP28PS = 1408
X86_INS_VRCP28SD = 1409
X86_INS_VRCP28SS = 1410
X86_INS_VRCPPS = 1411
X86_INS_VRCPSS = 1412
X86_INS_VREDUCEPD = 1413
X86_INS_VREDUCEPS = 1414
X86_INS_VREDUCESD = 1415
X86_INS_VREDUCESS = 1416
X86_INS_VRNDSCALEPD = 1417
X86_INS_VRNDSCALEPS = 1418
X86_INS_VRNDSCALESD = 1419
X86_INS_VRNDSCALESS = 1420
X86_INS_VROUNDPD = 1421
X86_INS_VROUNDPS = 1422
X86_INS_VROUNDSD = 1423
X86_INS_VROUNDSS = 1424
X86_INS_VRSQRT14PD = 1425
X86_INS_VRSQRT14PS = 1426
X86_INS_VRSQRT14SD = 1427
X86_INS_VRSQRT14SS = 1428
X86_INS_VRSQRT28PD = 1429
X86_INS_VRSQRT28PS = 1430
X86_INS_VRSQRT28SD = 1431
X86_INS_VRSQRT28SS = 1432
X86_INS_VRSQRTPS = 1433
X86_INS_VRSQRTSS = 1434
X86_INS_VSCALEFPD = 1435
X86_INS_VSCALEFPS = 1436
X86_INS_VSCALEFSD = 1437
X86_INS_VSCALEFSS = 1438
X86_INS_VSCATTERDPD = 1439
X86_INS_VSCATTERDPS = 1440
X86_INS_VSCATTERPF0DPD = 1441
X86_INS_VSCATTERPF0DPS = 1442
X86_INS_VSCATTERPF0QPD = 1443
X86_INS_VSCATTERPF0QPS = 1444
X86_INS_VSCATTERPF1DPD = 1445
X86_INS_VSCATTERPF1DPS = 1446
X86_INS_VSCATTERPF1QPD = 1447
X86_INS_VSCATTERPF1QPS = 1448
X86_INS_VSCATTERQPD = 1449
X86_INS_VSCATTERQPS = 1450
X86_INS_VSHUFF32X4 = 1451
X86_INS_VSHUFF64X2 = 1452
X86_INS_VSHUFI32X4 = 1453
X86_INS_VSHUFI64X2 = 1454
X86_INS_VSHUFPD = 1455
X86_INS_VSHUFPS = 1456
X86_INS_VSQRTPD = 1457
X86_INS_VSQRTPS = 1458
X86_INS_VSQRTSD = 1459
X86_INS_VSQRTSS = 1460
X86_INS_VSTMXCSR = 1461
X86_INS_VSUBPD = 1462
X86_INS_VSUBPS = 1463
X86_INS_VSUBSD = 1464
X86_INS_VSUBSS = 1465
X86_INS_VTESTPD = 1466
X86_INS_VTESTPS = 1467
X86_INS_VUCOMISD = 1468
X86_INS_VUCOMISS = 1469
X86_INS_VUNPCKHPD = 1470
X86_INS_VUNPCKHPS = 1471
X86_INS_VUNPCKLPD = 1472
X86_INS_VUNPCKLPS = 1473
X86_INS_VXORPD = 1474
X86_INS_VXORPS = 1475
X86_INS_VZEROALL = 1476
X86_INS_VZEROUPPER = 1477
X86_INS_WAIT = 1478
X86_INS_WBINVD = 1479
X86_INS_WBNOINVD = 1480
X86_INS_WRFSBASE = 1481
X86_INS_WRGSBASE = 1482
X86_INS_WRMSR = 1483
X86_INS_WRPKRU = 1484
X86_INS_WRSSD = 1485
X86_INS_WRSSQ = 1486
X86_INS_WRUSSD = 1487
X86_INS_WRUSSQ = 1488
X86_INS_XABORT = 1489
X86_INS_XACQUIRE = 1490
X86_INS_XADD = 1491
X86_INS_XBEGIN = 1492
X86_INS_XCHG = 1493
X86_INS_FXCH = 1494
X86_INS_XCRYPTCBC = 1495
X86_INS_XCRYPTCFB = 1496
X86_INS_XCRYPTCTR = 1497
X86_INS_XCRYPTECB = 1498
X86_INS_XCRYPTOFB = 1499
X86_INS_XEND = 1500
X86_INS_XGETBV = 1501
X86_INS_XLATB = 1502
X86_INS_XOR = 1503
X86_INS_XORPD = 1504
X86_INS_XORPS = 1505
X86_INS_XRELEASE = 1506
X86_INS_XRSTOR = 1507
X86_INS_XRSTOR64 = 1508
X86_INS_XRSTORS = 1509
X86_INS_XRSTORS64 = 1510
X86_INS_XSAVE = 1511
X86_INS_XSAVE64 = 1512
X86_INS_XSAVEC = 1513
X86_INS_XSAVEC64 = 1514
X86_INS_XSAVEOPT = 1515
X86_INS_XSAVEOPT64 = 1516
X86_INS_XSAVES = 1517
X86_INS_XSAVES64 = 1518
X86_INS_XSETBV = 1519
X86_INS_XSHA1 = 1520
X86_INS_XSHA256 = 1521
X86_INS_XSTORE = 1522
X86_INS_XTEST = 1523
X86_INS_ENDING = 1524
X86_GRP_INVALID = 0
X86_GRP_JUMP = 1
X86_GRP_CALL = 2
X86_GRP_RET = 3
X86_GRP_INT = 4
X86_GRP_IRET = 5
X86_GRP_PRIVILEGE = 6
X86_GRP_BRANCH_RELATIVE = 7
X86_GRP_VM = 128
X86_GRP_3DNOW = 129
X86_GRP_AES = 130
X86_GRP_ADX = 131
X86_GRP_AVX = 132
X86_GRP_AVX2 = 133
X86_GRP_AVX512 = 134
X86_GRP_BMI = 135
X86_GRP_BMI2 = 136
X86_GRP_CMOV = 137
X86_GRP_F16C = 138
X86_GRP_FMA = 139
X86_GRP_FMA4 = 140
X86_GRP_FSGSBASE = 141
X86_GRP_HLE = 142
X86_GRP_MMX = 143
X86_GRP_MODE32 = 144
X86_GRP_MODE64 = 145
X86_GRP_RTM = 146
X86_GRP_SHA = 147
X86_GRP_SSE1 = 148
X86_GRP_SSE2 = 149
X86_GRP_SSE3 = 150
X86_GRP_SSE41 = 151
X86_GRP_SSE42 = 152
X86_GRP_SSE4A = 153
X86_GRP_SSSE3 = 154
X86_GRP_PCLMUL = 155
X86_GRP_XOP = 156
X86_GRP_CDI = 157
X86_GRP_ERI = 158
X86_GRP_TBM = 159
X86_GRP_16BITMODE = 160
X86_GRP_NOT64BITMODE = 161
X86_GRP_SGX = 162
X86_GRP_DQI = 163
X86_GRP_BWI = 164
X86_GRP_PFI = 165
X86_GRP_VLX = 166
X86_GRP_SMAP = 167
X86_GRP_NOVLX = 168
X86_GRP_FPU = 169
X86_GRP_ENDING = 170
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/x86_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
TMS320C64X_OP_INVALID = 0
TMS320C64X_OP_REG = 1
TMS320C64X_OP_IMM = 2
TMS320C64X_OP_MEM = 3
TMS320C64X_OP_REGPAIR = 64
TMS320C64X_MEM_DISP_INVALID = 0
TMS320C64X_MEM_DISP_CONSTANT = 1
TMS320C64X_MEM_DISP_REGISTER = 2
TMS320C64X_MEM_DIR_INVALID = 0
TMS320C64X_MEM_DIR_FW = 1
TMS320C64X_MEM_DIR_BW = 2
TMS320C64X_MEM_MOD_INVALID = 0
TMS320C64X_MEM_MOD_NO = 1
TMS320C64X_MEM_MOD_PRE = 2
TMS320C64X_MEM_MOD_POST = 3
TMS320C64X_REG_INVALID = 0
TMS320C64X_REG_AMR = 1
TMS320C64X_REG_CSR = 2
TMS320C64X_REG_DIER = 3
TMS320C64X_REG_DNUM = 4
TMS320C64X_REG_ECR = 5
TMS320C64X_REG_GFPGFR = 6
TMS320C64X_REG_GPLYA = 7
TMS320C64X_REG_GPLYB = 8
TMS320C64X_REG_ICR = 9
TMS320C64X_REG_IER = 10
TMS320C64X_REG_IERR = 11
TMS320C64X_REG_ILC = 12
TMS320C64X_REG_IRP = 13
TMS320C64X_REG_ISR = 14
TMS320C64X_REG_ISTP = 15
TMS320C64X_REG_ITSR = 16
TMS320C64X_REG_NRP = 17
TMS320C64X_REG_NTSR = 18
TMS320C64X_REG_REP = 19
TMS320C64X_REG_RILC = 20
TMS320C64X_REG_SSR = 21
TMS320C64X_REG_TSCH = 22
TMS320C64X_REG_TSCL = 23
TMS320C64X_REG_TSR = 24
TMS320C64X_REG_A0 = 25
TMS320C64X_REG_A1 = 26
TMS320C64X_REG_A2 = 27
TMS320C64X_REG_A3 = 28
TMS320C64X_REG_A4 = 29
TMS320C64X_REG_A5 = 30
TMS320C64X_REG_A6 = 31
TMS320C64X_REG_A7 = 32
TMS320C64X_REG_A8 = 33
TMS320C64X_REG_A9 = 34
TMS320C64X_REG_A10 = 35
TMS320C64X_REG_A11 = 36
TMS320C64X_REG_A12 = 37
TMS320C64X_REG_A13 = 38
TMS320C64X_REG_A14 = 39
TMS320C64X_REG_A15 = 40
TMS320C64X_REG_A16 = 41
TMS320C64X_REG_A17 = 42
TMS320C64X_REG_A18 = 43
TMS320C64X_REG_A19 = 44
TMS320C64X_REG_A20 = 45
TMS320C64X_REG_A21 = 46
TMS320C64X_REG_A22 = 47
TMS320C64X_REG_A23 = 48
TMS320C64X_REG_A24 = 49
TMS320C64X_REG_A25 = 50
TMS320C64X_REG_A26 = 51
TMS320C64X_REG_A27 = 52
TMS320C64X_REG_A28 = 53
TMS320C64X_REG_A29 = 54
TMS320C64X_REG_A30 = 55
TMS320C64X_REG_A31 = 56
TMS320C64X_REG_B0 = 57
TMS320C64X_REG_B1 = 58
TMS320C64X_REG_B2 = 59
TMS320C64X_REG_B3 = 60
TMS320C64X_REG_B4 = 61
TMS320C64X_REG_B5 = 62
TMS320C64X_REG_B6 = 63
TMS320C64X_REG_B7 = 64
TMS320C64X_REG_B8 = 65
TMS320C64X_REG_B9 = 66
TMS320C64X_REG_B10 = 67
TMS320C64X_REG_B11 = 68
TMS320C64X_REG_B12 = 69
TMS320C64X_REG_B13 = 70
TMS320C64X_REG_B14 = 71
TMS320C64X_REG_B15 = 72
TMS320C64X_REG_B16 = 73
TMS320C64X_REG_B17 = 74
TMS320C64X_REG_B18 = 75
TMS320C64X_REG_B19 = 76
TMS320C64X_REG_B20 = 77
TMS320C64X_REG_B21 = 78
TMS320C64X_REG_B22 = 79
TMS320C64X_REG_B23 = 80
TMS320C64X_REG_B24 = 81
TMS320C64X_REG_B25 = 82
TMS320C64X_REG_B26 = 83
TMS320C64X_REG_B27 = 84
TMS320C64X_REG_B28 = 85
TMS320C64X_REG_B29 = 86
TMS320C64X_REG_B30 = 87
TMS320C64X_REG_B31 = 88
TMS320C64X_REG_PCE1 = 89
TMS320C64X_REG_ENDING = 90
TMS320C64X_REG_EFR = TMS320C64X_REG_ECR
TMS320C64X_REG_IFR = TMS320C64X_REG_ISR
TMS320C64X_INS_INVALID = 0
TMS320C64X_INS_ABS = 1
TMS320C64X_INS_ABS2 = 2
TMS320C64X_INS_ADD = 3
TMS320C64X_INS_ADD2 = 4
TMS320C64X_INS_ADD4 = 5
TMS320C64X_INS_ADDAB = 6
TMS320C64X_INS_ADDAD = 7
TMS320C64X_INS_ADDAH = 8
TMS320C64X_INS_ADDAW = 9
TMS320C64X_INS_ADDK = 10
TMS320C64X_INS_ADDKPC = 11
TMS320C64X_INS_ADDU = 12
TMS320C64X_INS_AND = 13
TMS320C64X_INS_ANDN = 14
TMS320C64X_INS_AVG2 = 15
TMS320C64X_INS_AVGU4 = 16
TMS320C64X_INS_B = 17
TMS320C64X_INS_BDEC = 18
TMS320C64X_INS_BITC4 = 19
TMS320C64X_INS_BNOP = 20
TMS320C64X_INS_BPOS = 21
TMS320C64X_INS_CLR = 22
TMS320C64X_INS_CMPEQ = 23
TMS320C64X_INS_CMPEQ2 = 24
TMS320C64X_INS_CMPEQ4 = 25
TMS320C64X_INS_CMPGT = 26
TMS320C64X_INS_CMPGT2 = 27
TMS320C64X_INS_CMPGTU4 = 28
TMS320C64X_INS_CMPLT = 29
TMS320C64X_INS_CMPLTU = 30
TMS320C64X_INS_DEAL = 31
TMS320C64X_INS_DOTP2 = 32
TMS320C64X_INS_DOTPN2 = 33
TMS320C64X_INS_DOTPNRSU2 = 34
TMS320C64X_INS_DOTPRSU2 = 35
TMS320C64X_INS_DOTPSU4 = 36
TMS320C64X_INS_DOTPU4 = 37
TMS320C64X_INS_EXT = 38
TMS320C64X_INS_EXTU = 39
TMS320C64X_INS_GMPGTU = 40
TMS320C64X_INS_GMPY4 = 41
TMS320C64X_INS_LDB = 42
TMS320C64X_INS_LDBU = 43
TMS320C64X_INS_LDDW = 44
TMS320C64X_INS_LDH = 45
TMS320C64X_INS_LDHU = 46
TMS320C64X_INS_LDNDW = 47
TMS320C64X_INS_LDNW = 48
TMS320C64X_INS_LDW = 49
TMS320C64X_INS_LMBD = 50
TMS320C64X_INS_MAX2 = 51
TMS320C64X_INS_MAXU4 = 52
TMS320C64X_INS_MIN2 = 53
TMS320C64X_INS_MINU4 = 54
TMS320C64X_INS_MPY = 55
TMS320C64X_INS_MPY2 = 56
TMS320C64X_INS_MPYH = 57
TMS320C64X_INS_MPYHI = 58
TMS320C64X_INS_MPYHIR = 59
TMS320C64X_INS_MPYHL = 60
TMS320C64X_INS_MPYHLU = 61
TMS320C64X_INS_MPYHSLU = 62
TMS320C64X_INS_MPYHSU = 63
TMS320C64X_INS_MPYHU = 64
TMS320C64X_INS_MPYHULS = 65
TMS320C64X_INS_MPYHUS = 66
TMS320C64X_INS_MPYLH = 67
TMS320C64X_INS_MPYLHU = 68
TMS320C64X_INS_MPYLI = 69
TMS320C64X_INS_MPYLIR = 70
TMS320C64X_INS_MPYLSHU = 71
TMS320C64X_INS_MPYLUHS = 72
TMS320C64X_INS_MPYSU = 73
TMS320C64X_INS_MPYSU4 = 74
TMS320C64X_INS_MPYU = 75
TMS320C64X_INS_MPYU4 = 76
TMS320C64X_INS_MPYUS = 77
TMS320C64X_INS_MVC = 78
TMS320C64X_INS_MVD = 79
TMS320C64X_INS_MVK = 80
TMS320C64X_INS_MVKL = 81
TMS320C64X_INS_MVKLH = 82
TMS320C64X_INS_NOP = 83
TMS320C64X_INS_NORM = 84
TMS320C64X_INS_OR = 85
TMS320C64X_INS_PACK2 = 86
TMS320C64X_INS_PACKH2 = 87
TMS320C64X_INS_PACKH4 = 88
TMS320C64X_INS_PACKHL2 = 89
TMS320C64X_INS_PACKL4 = 90
TMS320C64X_INS_PACKLH2 = 91
TMS320C64X_INS_ROTL = 92
TMS320C64X_INS_SADD = 93
TMS320C64X_INS_SADD2 = 94
TMS320C64X_INS_SADDU4 = 95
TMS320C64X_INS_SADDUS2 = 96
TMS320C64X_INS_SAT = 97
TMS320C64X_INS_SET = 98
TMS320C64X_INS_SHFL = 99
TMS320C64X_INS_SHL = 100
TMS320C64X_INS_SHLMB = 101
TMS320C64X_INS_SHR = 102
TMS320C64X_INS_SHR2 = 103
TMS320C64X_INS_SHRMB = 104
TMS320C64X_INS_SHRU = 105
TMS320C64X_INS_SHRU2 = 106
TMS320C64X_INS_SMPY = 107
TMS320C64X_INS_SMPY2 = 108
TMS320C64X_INS_SMPYH = 109
TMS320C64X_INS_SMPYHL = 110
TMS320C64X_INS_SMPYLH = 111
TMS320C64X_INS_SPACK2 = 112
TMS320C64X_INS_SPACKU4 = 113
TMS320C64X_INS_SSHL = 114
TMS320C64X_INS_SSHVL = 115
TMS320C64X_INS_SSHVR = 116
TMS320C64X_INS_SSUB = 117
TMS320C64X_INS_STB = 118
TMS320C64X_INS_STDW = 119
TMS320C64X_INS_STH = 120
TMS320C64X_INS_STNDW = 121
TMS320C64X_INS_STNW = 122
TMS320C64X_INS_STW = 123
TMS320C64X_INS_SUB = 124
TMS320C64X_INS_SUB2 = 125
TMS320C64X_INS_SUB4 = 126
TMS320C64X_INS_SUBAB = 127
TMS320C64X_INS_SUBABS4 = 128
TMS320C64X_INS_SUBAH = 129
TMS320C64X_INS_SUBAW = 130
TMS320C64X_INS_SUBC = 131
TMS320C64X_INS_SUBU = 132
TMS320C64X_INS_SWAP4 = 133
TMS320C64X_INS_UNPKHU4 = 134
TMS320C64X_INS_UNPKLU4 = 135
TMS320C64X_INS_XOR = 136
TMS320C64X_INS_XPND2 = 137
TMS320C64X_INS_XPND4 = 138
TMS320C64X_INS_IDLE = 139
TMS320C64X_INS_MV = 140
TMS320C64X_INS_NEG = 141
TMS320C64X_INS_NOT = 142
TMS320C64X_INS_SWAP2 = 143
TMS320C64X_INS_ZERO = 144
TMS320C64X_INS_ENDING = 145
TMS320C64X_GRP_INVALID = 0
TMS320C64X_GRP_JUMP = 1
TMS320C64X_GRP_FUNIT_D = 128
TMS320C64X_GRP_FUNIT_L = 129
TMS320C64X_GRP_FUNIT_M = 130
TMS320C64X_GRP_FUNIT_S = 131
TMS320C64X_GRP_FUNIT_NO = 132
TMS320C64X_GRP_ENDING = 133
TMS320C64X_FUNIT_INVALID = 0
TMS320C64X_FUNIT_D = 1
TMS320C64X_FUNIT_L = 2
TMS320C64X_FUNIT_M = 3
TMS320C64X_FUNIT_S = 4
TMS320C64X_FUNIT_NO = 5
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/tms320c64x_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
XCORE_OP_INVALID = 0
XCORE_OP_REG = 1
XCORE_OP_IMM = 2
XCORE_OP_MEM = 3
XCORE_REG_INVALID = 0
XCORE_REG_CP = 1
XCORE_REG_DP = 2
XCORE_REG_LR = 3
XCORE_REG_SP = 4
XCORE_REG_R0 = 5
XCORE_REG_R1 = 6
XCORE_REG_R2 = 7
XCORE_REG_R3 = 8
XCORE_REG_R4 = 9
XCORE_REG_R5 = 10
XCORE_REG_R6 = 11
XCORE_REG_R7 = 12
XCORE_REG_R8 = 13
XCORE_REG_R9 = 14
XCORE_REG_R10 = 15
XCORE_REG_R11 = 16
XCORE_REG_PC = 17
XCORE_REG_SCP = 18
XCORE_REG_SSR = 19
XCORE_REG_ET = 20
XCORE_REG_ED = 21
XCORE_REG_SED = 22
XCORE_REG_KEP = 23
XCORE_REG_KSP = 24
XCORE_REG_ID = 25
XCORE_REG_ENDING = 26
XCORE_INS_INVALID = 0
XCORE_INS_ADD = 1
XCORE_INS_ANDNOT = 2
XCORE_INS_AND = 3
XCORE_INS_ASHR = 4
XCORE_INS_BAU = 5
XCORE_INS_BITREV = 6
XCORE_INS_BLA = 7
XCORE_INS_BLAT = 8
XCORE_INS_BL = 9
XCORE_INS_BF = 10
XCORE_INS_BT = 11
XCORE_INS_BU = 12
XCORE_INS_BRU = 13
XCORE_INS_BYTEREV = 14
XCORE_INS_CHKCT = 15
XCORE_INS_CLRE = 16
XCORE_INS_CLRPT = 17
XCORE_INS_CLRSR = 18
XCORE_INS_CLZ = 19
XCORE_INS_CRC8 = 20
XCORE_INS_CRC32 = 21
XCORE_INS_DCALL = 22
XCORE_INS_DENTSP = 23
XCORE_INS_DGETREG = 24
XCORE_INS_DIVS = 25
XCORE_INS_DIVU = 26
XCORE_INS_DRESTSP = 27
XCORE_INS_DRET = 28
XCORE_INS_ECALLF = 29
XCORE_INS_ECALLT = 30
XCORE_INS_EDU = 31
XCORE_INS_EEF = 32
XCORE_INS_EET = 33
XCORE_INS_EEU = 34
XCORE_INS_ENDIN = 35
XCORE_INS_ENTSP = 36
XCORE_INS_EQ = 37
XCORE_INS_EXTDP = 38
XCORE_INS_EXTSP = 39
XCORE_INS_FREER = 40
XCORE_INS_FREET = 41
XCORE_INS_GETD = 42
XCORE_INS_GET = 43
XCORE_INS_GETN = 44
XCORE_INS_GETR = 45
XCORE_INS_GETSR = 46
XCORE_INS_GETST = 47
XCORE_INS_GETTS = 48
XCORE_INS_INCT = 49
XCORE_INS_INIT = 50
XCORE_INS_INPW = 51
XCORE_INS_INSHR = 52
XCORE_INS_INT = 53
XCORE_INS_IN = 54
XCORE_INS_KCALL = 55
XCORE_INS_KENTSP = 56
XCORE_INS_KRESTSP = 57
XCORE_INS_KRET = 58
XCORE_INS_LADD = 59
XCORE_INS_LD16S = 60
XCORE_INS_LD8U = 61
XCORE_INS_LDA16 = 62
XCORE_INS_LDAP = 63
XCORE_INS_LDAW = 64
XCORE_INS_LDC = 65
XCORE_INS_LDW = 66
XCORE_INS_LDIVU = 67
XCORE_INS_LMUL = 68
XCORE_INS_LSS = 69
XCORE_INS_LSUB = 70
XCORE_INS_LSU = 71
XCORE_INS_MACCS = 72
XCORE_INS_MACCU = 73
XCORE_INS_MJOIN = 74
XCORE_INS_MKMSK = 75
XCORE_INS_MSYNC = 76
XCORE_INS_MUL = 77
XCORE_INS_NEG = 78
XCORE_INS_NOT = 79
XCORE_INS_OR = 80
XCORE_INS_OUTCT = 81
XCORE_INS_OUTPW = 82
XCORE_INS_OUTSHR = 83
XCORE_INS_OUTT = 84
XCORE_INS_OUT = 85
XCORE_INS_PEEK = 86
XCORE_INS_REMS = 87
XCORE_INS_REMU = 88
XCORE_INS_RETSP = 89
XCORE_INS_SETCLK = 90
XCORE_INS_SET = 91
XCORE_INS_SETC = 92
XCORE_INS_SETD = 93
XCORE_INS_SETEV = 94
XCORE_INS_SETN = 95
XCORE_INS_SETPSC = 96
XCORE_INS_SETPT = 97
XCORE_INS_SETRDY = 98
XCORE_INS_SETSR = 99
XCORE_INS_SETTW = 100
XCORE_INS_SETV = 101
XCORE_INS_SEXT = 102
XCORE_INS_SHL = 103
XCORE_INS_SHR = 104
XCORE_INS_SSYNC = 105
XCORE_INS_ST16 = 106
XCORE_INS_ST8 = 107
XCORE_INS_STW = 108
XCORE_INS_SUB = 109
XCORE_INS_SYNCR = 110
XCORE_INS_TESTCT = 111
XCORE_INS_TESTLCL = 112
XCORE_INS_TESTWCT = 113
XCORE_INS_TSETMR = 114
XCORE_INS_START = 115
XCORE_INS_WAITEF = 116
XCORE_INS_WAITET = 117
XCORE_INS_WAITEU = 118
XCORE_INS_XOR = 119
XCORE_INS_ZEXT = 120
XCORE_INS_ENDING = 121
XCORE_GRP_INVALID = 0
XCORE_GRP_JUMP = 1
XCORE_GRP_ENDING = 2
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/xcore_const.py
|
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
import ctypes
from . import copy_ctypes_list
from .x86_const import *
# define the API
class X86OpMem(ctypes.Structure):
_fields_ = (
('segment', ctypes.c_uint),
('base', ctypes.c_uint),
('index', ctypes.c_uint),
('scale', ctypes.c_int),
('disp', ctypes.c_int64),
)
class X86OpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', X86OpMem),
)
class X86Op(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', X86OpValue),
('size', ctypes.c_uint8),
('access', ctypes.c_uint8),
('avx_bcast', ctypes.c_uint),
('avx_zero_opmask', ctypes.c_bool),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsX86Encoding(ctypes.Structure):
_fields_ = (
('modrm_offset', ctypes.c_uint8),
('disp_offset', ctypes.c_uint8),
('disp_size', ctypes.c_uint8),
('imm_offset', ctypes.c_uint8),
('imm_size', ctypes.c_uint8),
)
class CsX86(ctypes.Structure):
_fields_ = (
('prefix', ctypes.c_uint8 * 4),
('opcode', ctypes.c_uint8 * 4),
('rex', ctypes.c_uint8),
('addr_size', ctypes.c_uint8),
('modrm', ctypes.c_uint8),
('sib', ctypes.c_uint8),
('disp', ctypes.c_int64),
('sib_index', ctypes.c_uint),
('sib_scale', ctypes.c_int8),
('sib_base', ctypes.c_uint),
('xop_cc', ctypes.c_uint),
('sse_cc', ctypes.c_uint),
('avx_cc', ctypes.c_uint),
('avx_sae', ctypes.c_bool),
('avx_rm', ctypes.c_uint),
('eflags', ctypes.c_uint64),
('op_count', ctypes.c_uint8),
('operands', X86Op * 8),
('encoding', CsX86Encoding),
)
def get_arch_info(a):
return (a.prefix[:], a.opcode[:], a.rex, a.addr_size, \
a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, \
a.sib_base, a.xop_cc, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, a.eflags, \
a.encoding.modrm_offset, a.encoding.disp_offset, a.encoding.disp_size, a.encoding.imm_offset, a.encoding.imm_size, \
copy_ctypes_list(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/x86.py
|
# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
import ctypes
from . import copy_ctypes_list
from .m68k_const import *
# define the API
class M68KOpMem(ctypes.Structure):
_fields_ = (
('base_reg', ctypes.c_uint),
('index_reg', ctypes.c_uint),
('in_base_reg', ctypes.c_uint),
('in_disp', ctypes.c_uint),
('out_disp', ctypes.c_uint),
('disp', ctypes.c_short),
('scale', ctypes.c_ubyte),
('bitfield', ctypes.c_ubyte),
('width', ctypes.c_ubyte),
('offset', ctypes.c_ubyte),
('index_size', ctypes.c_ubyte),
)
class M68KOpRegPair(ctypes.Structure):
_fields_ = (
('reg_0', ctypes.c_uint),
('reg_1', ctypes.c_uint),
)
class M68KOpValue(ctypes.Union):
_fields_ = (
('imm', ctypes.c_int64),
('dimm', ctypes.c_double),
('simm', ctypes.c_float),
('reg', ctypes.c_uint),
('reg_pair', M68KOpRegPair),
)
class M68KOpBrDisp(ctypes.Structure):
_fields_ = (
('disp', ctypes.c_int),
('disp_size', ctypes.c_ubyte),
)
class M68KOp(ctypes.Structure):
_fields_ = (
('value', M68KOpValue),
('mem', M68KOpMem),
('br_disp', M68KOpBrDisp),
('register_bits', ctypes.c_uint),
('type', ctypes.c_uint),
('address_mode', ctypes.c_uint),
)
@property
def imm(self):
return self.value.imm
@property
def dimm(self):
return self.value.dimm
@property
def simm(self):
return self.value.simm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.mem
@property
def register_bits(self):
return self.register_bits
class M68KOpSize(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('size', ctypes.c_uint),
)
def get(a):
return copy_ctypes_list(type, size)
class CsM68K(ctypes.Structure):
M68K_OPERAND_COUNT = 4
_fields_ = (
('operands', M68KOp * M68K_OPERAND_COUNT),
('op_size', M68KOpSize),
('op_count', ctypes.c_uint8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/m68k.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py]
WASM_OP_INVALID = 0
WASM_OP_NONE = 1
WASM_OP_INT7 = 2
WASM_OP_VARUINT32 = 3
WASM_OP_VARUINT64 = 4
WASM_OP_UINT32 = 5
WASM_OP_UINT64 = 6
WASM_OP_IMM = 7
WASM_OP_BRTABLE = 8
WASM_INS_UNREACHABLE = 0x0
WASM_INS_NOP = 0x1
WASM_INS_BLOCK = 0x2
WASM_INS_LOOP = 0x3
WASM_INS_IF = 0x4
WASM_INS_ELSE = 0x5
WASM_INS_END = 0xb
WASM_INS_BR = 0xc
WASM_INS_BR_IF = 0xd
WASM_INS_BR_TABLE = 0xe
WASM_INS_RETURN = 0xf
WASM_INS_CALL = 0x10
WASM_INS_CALL_INDIRECT = 0x11
WASM_INS_DROP = 0x1a
WASM_INS_SELECT = 0x1b
WASM_INS_GET_LOCAL = 0x20
WASM_INS_SET_LOCAL = 0x21
WASM_INS_TEE_LOCAL = 0x22
WASM_INS_GET_GLOBAL = 0x23
WASM_INS_SET_GLOBAL = 0x24
WASM_INS_I32_LOAD = 0x28
WASM_INS_I64_LOAD = 0x29
WASM_INS_F32_LOAD = 0x2a
WASM_INS_F64_LOAD = 0x2b
WASM_INS_I32_LOAD8_S = 0x2c
WASM_INS_I32_LOAD8_U = 0x2d
WASM_INS_I32_LOAD16_S = 0x2e
WASM_INS_I32_LOAD16_U = 0x2f
WASM_INS_I64_LOAD8_S = 0x30
WASM_INS_I64_LOAD8_U = 0x31
WASM_INS_I64_LOAD16_S = 0x32
WASM_INS_I64_LOAD16_U = 0x33
WASM_INS_I64_LOAD32_S = 0x34
WASM_INS_I64_LOAD32_U = 0x35
WASM_INS_I32_STORE = 0x36
WASM_INS_I64_STORE = 0x37
WASM_INS_F32_STORE = 0x38
WASM_INS_F64_STORE = 0x39
WASM_INS_I32_STORE8 = 0x3a
WASM_INS_I32_STORE16 = 0x3b
WASM_INS_I64_STORE8 = 0x3c
WASM_INS_I64_STORE16 = 0x3d
WASM_INS_I64_STORE32 = 0x3e
WASM_INS_CURRENT_MEMORY = 0x3f
WASM_INS_GROW_MEMORY = 0x40
WASM_INS_I32_CONST = 0x41
WASM_INS_I64_CONST = 0x42
WASM_INS_F32_CONST = 0x43
WASM_INS_F64_CONST = 0x44
WASM_INS_I32_EQZ = 0x45
WASM_INS_I32_EQ = 0x46
WASM_INS_I32_NE = 0x47
WASM_INS_I32_LT_S = 0x48
WASM_INS_I32_LT_U = 0x49
WASM_INS_I32_GT_S = 0x4a
WASM_INS_I32_GT_U = 0x4b
WASM_INS_I32_LE_S = 0x4c
WASM_INS_I32_LE_U = 0x4d
WASM_INS_I32_GE_S = 0x4e
WASM_INS_I32_GE_U = 0x4f
WASM_INS_I64_EQZ = 0x50
WASM_INS_I64_EQ = 0x51
WASM_INS_I64_NE = 0x52
WASM_INS_I64_LT_S = 0x53
WASM_INS_I64_LT_U = 0x54
WASM_INS_I64_GT_U = 0x56
WASM_INS_I64_LE_S = 0x57
WASM_INS_I64_LE_U = 0x58
WASM_INS_I64_GE_S = 0x59
WASM_INS_I64_GE_U = 0x5a
WASM_INS_F32_EQ = 0x5b
WASM_INS_F32_NE = 0x5c
WASM_INS_F32_LT = 0x5d
WASM_INS_F32_GT = 0x5e
WASM_INS_F32_LE = 0x5f
WASM_INS_F32_GE = 0x60
WASM_INS_F64_EQ = 0x61
WASM_INS_F64_NE = 0x62
WASM_INS_F64_LT = 0x63
WASM_INS_F64_GT = 0x64
WASM_INS_F64_LE = 0x65
WASM_INS_F64_GE = 0x66
WASM_INS_I32_CLZ = 0x67
WASM_INS_I32_CTZ = 0x68
WASM_INS_I32_POPCNT = 0x69
WASM_INS_I32_ADD = 0x6a
WASM_INS_I32_SUB = 0x6b
WASM_INS_I32_MUL = 0x6c
WASM_INS_I32_DIV_S = 0x6d
WASM_INS_I32_DIV_U = 0x6e
WASM_INS_I32_REM_S = 0x6f
WASM_INS_I32_REM_U = 0x70
WASM_INS_I32_AND = 0x71
WASM_INS_I32_OR = 0x72
WASM_INS_I32_XOR = 0x73
WASM_INS_I32_SHL = 0x74
WASM_INS_I32_SHR_S = 0x75
WASM_INS_I32_SHR_U = 0x76
WASM_INS_I32_ROTL = 0x77
WASM_INS_I32_ROTR = 0x78
WASM_INS_I64_CLZ = 0x79
WASM_INS_I64_CTZ = 0x7a
WASM_INS_I64_POPCNT = 0x7b
WASM_INS_I64_ADD = 0x7c
WASM_INS_I64_SUB = 0x7d
WASM_INS_I64_MUL = 0x7e
WASM_INS_I64_DIV_S = 0x7f
WASM_INS_I64_DIV_U = 0x80
WASM_INS_I64_REM_S = 0x81
WASM_INS_I64_REM_U = 0x82
WASM_INS_I64_AND = 0x83
WASM_INS_I64_OR = 0x84
WASM_INS_I64_XOR = 0x85
WASM_INS_I64_SHL = 0x86
WASM_INS_I64_SHR_S = 0x87
WASM_INS_I64_SHR_U = 0x88
WASM_INS_I64_ROTL = 0x89
WASM_INS_I64_ROTR = 0x8a
WASM_INS_F32_ABS = 0x8b
WASM_INS_F32_NEG = 0x8c
WASM_INS_F32_CEIL = 0x8d
WASM_INS_F32_FLOOR = 0x8e
WASM_INS_F32_TRUNC = 0x8f
WASM_INS_F32_NEAREST = 0x90
WASM_INS_F32_SQRT = 0x91
WASM_INS_F32_ADD = 0x92
WASM_INS_F32_SUB = 0x93
WASM_INS_F32_MUL = 0x94
WASM_INS_F32_DIV = 0x95
WASM_INS_F32_MIN = 0x96
WASM_INS_F32_MAX = 0x97
WASM_INS_F32_COPYSIGN = 0x98
WASM_INS_F64_ABS = 0x99
WASM_INS_F64_NEG = 0x9a
WASM_INS_F64_CEIL = 0x9b
WASM_INS_F64_FLOOR = 0x9c
WASM_INS_F64_TRUNC = 0x9d
WASM_INS_F64_NEAREST = 0x9e
WASM_INS_F64_SQRT = 0x9f
WASM_INS_F64_ADD = 0xa0
WASM_INS_F64_SUB = 0xa1
WASM_INS_F64_MUL = 0xa2
WASM_INS_F64_DIV = 0xa3
WASM_INS_F64_MIN = 0xa4
WASM_INS_F64_MAX = 0xa5
WASM_INS_F64_COPYSIGN = 0xa6
WASM_INS_I32_WARP_I64 = 0xa7
WASM_INS_I32_TRUNC_U_F32 = 0xa9
WASM_INS_I32_TRUNC_S_F64 = 0xaa
WASM_INS_I32_TRUNC_U_F64 = 0xab
WASM_INS_I64_EXTEND_S_I32 = 0xac
WASM_INS_I64_EXTEND_U_I32 = 0xad
WASM_INS_I64_TRUNC_S_F32 = 0xae
WASM_INS_I64_TRUNC_U_F32 = 0xaf
WASM_INS_I64_TRUNC_S_F64 = 0xb0
WASM_INS_I64_TRUNC_U_F64 = 0xb1
WASM_INS_F32_CONVERT_S_I32 = 0xb2
WASM_INS_F32_CONVERT_U_I32 = 0xb3
WASM_INS_F32_CONVERT_S_I64 = 0xb4
WASM_INS_F32_CONVERT_U_I64 = 0xb5
WASM_INS_F32_DEMOTE_F64 = 0xb6
WASM_INS_F64_CONVERT_S_I32 = 0xb7
WASM_INS_F64_CONVERT_U_I32 = 0xb8
WASM_INS_F64_CONVERT_S_I64 = 0xb9
WASM_INS_F64_CONVERT_U_I64 = 0xba
WASM_INS_F64_PROMOTE_F32 = 0xbb
WASM_INS_I32_REINTERPRET_F32 = 0xbc
WASM_INS_I64_REINTERPRET_F64 = 0xbd
WASM_INS_F32_REINTERPRET_I32 = 0xbe
WASM_INS_F64_REINTERPRET_I64 = 0xbf
WASM_INS_INVALID = 512
WASM_INS_ENDING = 513
WASM_GRP_INVALID = 0
WASM_GRP_NUMBERIC = 8
WASM_GRP_PARAMETRIC = 9
WASM_GRP_VARIABLE = 10
WASM_GRP_MEMORY = 11
WASM_GRP_CONTROL = 12
WASM_GRP_ENDING = 13
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/wasm_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py]
PPC_BC_INVALID = 0
PPC_BC_LT = (0<<5)|12
PPC_BC_LE = (1<<5)|4
PPC_BC_EQ = (2<<5)|12
PPC_BC_GE = (0<<5)|4
PPC_BC_GT = (1<<5)|12
PPC_BC_NE = (2<<5)|4
PPC_BC_UN = (3<<5)|12
PPC_BC_NU = (3<<5)|4
PPC_BC_SO = (4<<5)|12
PPC_BC_NS = (4<<5)|4
PPC_BH_INVALID = 0
PPC_BH_PLUS = 1
PPC_BH_MINUS = 2
PPC_OP_INVALID = 0
PPC_OP_REG = 1
PPC_OP_IMM = 2
PPC_OP_MEM = 3
PPC_OP_CRX = 64
PPC_REG_INVALID = 0
PPC_REG_CARRY = 2
PPC_REG_CTR = 3
PPC_REG_LR = 5
PPC_REG_RM = 6
PPC_REG_VRSAVE = 8
PPC_REG_XER = 9
PPC_REG_ZERO = 10
PPC_REG_CR0 = 12
PPC_REG_CR1 = 13
PPC_REG_CR2 = 14
PPC_REG_CR3 = 15
PPC_REG_CR4 = 16
PPC_REG_CR5 = 17
PPC_REG_CR6 = 18
PPC_REG_CR7 = 19
PPC_REG_CTR8 = 20
PPC_REG_F0 = 21
PPC_REG_F1 = 22
PPC_REG_F2 = 23
PPC_REG_F3 = 24
PPC_REG_F4 = 25
PPC_REG_F5 = 26
PPC_REG_F6 = 27
PPC_REG_F7 = 28
PPC_REG_F8 = 29
PPC_REG_F9 = 30
PPC_REG_F10 = 31
PPC_REG_F11 = 32
PPC_REG_F12 = 33
PPC_REG_F13 = 34
PPC_REG_F14 = 35
PPC_REG_F15 = 36
PPC_REG_F16 = 37
PPC_REG_F17 = 38
PPC_REG_F18 = 39
PPC_REG_F19 = 40
PPC_REG_F20 = 41
PPC_REG_F21 = 42
PPC_REG_F22 = 43
PPC_REG_F23 = 44
PPC_REG_F24 = 45
PPC_REG_F25 = 46
PPC_REG_F26 = 47
PPC_REG_F27 = 48
PPC_REG_F28 = 49
PPC_REG_F29 = 50
PPC_REG_F30 = 51
PPC_REG_F31 = 52
PPC_REG_LR8 = 54
PPC_REG_Q0 = 55
PPC_REG_Q1 = 56
PPC_REG_Q2 = 57
PPC_REG_Q3 = 58
PPC_REG_Q4 = 59
PPC_REG_Q5 = 60
PPC_REG_Q6 = 61
PPC_REG_Q7 = 62
PPC_REG_Q8 = 63
PPC_REG_Q9 = 64
PPC_REG_Q10 = 65
PPC_REG_Q11 = 66
PPC_REG_Q12 = 67
PPC_REG_Q13 = 68
PPC_REG_Q14 = 69
PPC_REG_Q15 = 70
PPC_REG_Q16 = 71
PPC_REG_Q17 = 72
PPC_REG_Q18 = 73
PPC_REG_Q19 = 74
PPC_REG_Q20 = 75
PPC_REG_Q21 = 76
PPC_REG_Q22 = 77
PPC_REG_Q23 = 78
PPC_REG_Q24 = 79
PPC_REG_Q25 = 80
PPC_REG_Q26 = 81
PPC_REG_Q27 = 82
PPC_REG_Q28 = 83
PPC_REG_Q29 = 84
PPC_REG_Q30 = 85
PPC_REG_Q31 = 86
PPC_REG_R0 = 87
PPC_REG_R1 = 88
PPC_REG_R2 = 89
PPC_REG_R3 = 90
PPC_REG_R4 = 91
PPC_REG_R5 = 92
PPC_REG_R6 = 93
PPC_REG_R7 = 94
PPC_REG_R8 = 95
PPC_REG_R9 = 96
PPC_REG_R10 = 97
PPC_REG_R11 = 98
PPC_REG_R12 = 99
PPC_REG_R13 = 100
PPC_REG_R14 = 101
PPC_REG_R15 = 102
PPC_REG_R16 = 103
PPC_REG_R17 = 104
PPC_REG_R18 = 105
PPC_REG_R19 = 106
PPC_REG_R20 = 107
PPC_REG_R21 = 108
PPC_REG_R22 = 109
PPC_REG_R23 = 110
PPC_REG_R24 = 111
PPC_REG_R25 = 112
PPC_REG_R26 = 113
PPC_REG_R27 = 114
PPC_REG_R28 = 115
PPC_REG_R29 = 116
PPC_REG_R30 = 117
PPC_REG_R31 = 118
PPC_REG_V0 = 151
PPC_REG_V1 = 152
PPC_REG_V2 = 153
PPC_REG_V3 = 154
PPC_REG_V4 = 155
PPC_REG_V5 = 156
PPC_REG_V6 = 157
PPC_REG_V7 = 158
PPC_REG_V8 = 159
PPC_REG_V9 = 160
PPC_REG_V10 = 161
PPC_REG_V11 = 162
PPC_REG_V12 = 163
PPC_REG_V13 = 164
PPC_REG_V14 = 165
PPC_REG_V15 = 166
PPC_REG_V16 = 167
PPC_REG_V17 = 168
PPC_REG_V18 = 169
PPC_REG_V19 = 170
PPC_REG_V20 = 171
PPC_REG_V21 = 172
PPC_REG_V22 = 173
PPC_REG_V23 = 174
PPC_REG_V24 = 175
PPC_REG_V25 = 176
PPC_REG_V26 = 177
PPC_REG_V27 = 178
PPC_REG_V28 = 179
PPC_REG_V29 = 180
PPC_REG_V30 = 181
PPC_REG_V31 = 182
PPC_REG_VS0 = 215
PPC_REG_VS1 = 216
PPC_REG_VS2 = 217
PPC_REG_VS3 = 218
PPC_REG_VS4 = 219
PPC_REG_VS5 = 220
PPC_REG_VS6 = 221
PPC_REG_VS7 = 222
PPC_REG_VS8 = 223
PPC_REG_VS9 = 224
PPC_REG_VS10 = 225
PPC_REG_VS11 = 226
PPC_REG_VS12 = 227
PPC_REG_VS13 = 228
PPC_REG_VS14 = 229
PPC_REG_VS15 = 230
PPC_REG_VS16 = 231
PPC_REG_VS17 = 232
PPC_REG_VS18 = 233
PPC_REG_VS19 = 234
PPC_REG_VS20 = 235
PPC_REG_VS21 = 236
PPC_REG_VS22 = 237
PPC_REG_VS23 = 238
PPC_REG_VS24 = 239
PPC_REG_VS25 = 240
PPC_REG_VS26 = 241
PPC_REG_VS27 = 242
PPC_REG_VS28 = 243
PPC_REG_VS29 = 244
PPC_REG_VS30 = 245
PPC_REG_VS31 = 246
PPC_REG_VS32 = 247
PPC_REG_VS33 = 248
PPC_REG_VS34 = 249
PPC_REG_VS35 = 250
PPC_REG_VS36 = 251
PPC_REG_VS37 = 252
PPC_REG_VS38 = 253
PPC_REG_VS39 = 254
PPC_REG_VS40 = 255
PPC_REG_VS41 = 256
PPC_REG_VS42 = 257
PPC_REG_VS43 = 258
PPC_REG_VS44 = 259
PPC_REG_VS45 = 260
PPC_REG_VS46 = 261
PPC_REG_VS47 = 262
PPC_REG_VS48 = 263
PPC_REG_VS49 = 264
PPC_REG_VS50 = 265
PPC_REG_VS51 = 266
PPC_REG_VS52 = 267
PPC_REG_VS53 = 268
PPC_REG_VS54 = 269
PPC_REG_VS55 = 270
PPC_REG_VS56 = 271
PPC_REG_VS57 = 272
PPC_REG_VS58 = 273
PPC_REG_VS59 = 274
PPC_REG_VS60 = 275
PPC_REG_VS61 = 276
PPC_REG_VS62 = 277
PPC_REG_VS63 = 278
PPC_REG_CR0EQ = 312
PPC_REG_CR1EQ = 313
PPC_REG_CR2EQ = 314
PPC_REG_CR3EQ = 315
PPC_REG_CR4EQ = 316
PPC_REG_CR5EQ = 317
PPC_REG_CR6EQ = 318
PPC_REG_CR7EQ = 319
PPC_REG_CR0GT = 320
PPC_REG_CR1GT = 321
PPC_REG_CR2GT = 322
PPC_REG_CR3GT = 323
PPC_REG_CR4GT = 324
PPC_REG_CR5GT = 325
PPC_REG_CR6GT = 326
PPC_REG_CR7GT = 327
PPC_REG_CR0LT = 328
PPC_REG_CR1LT = 329
PPC_REG_CR2LT = 330
PPC_REG_CR3LT = 331
PPC_REG_CR4LT = 332
PPC_REG_CR5LT = 333
PPC_REG_CR6LT = 334
PPC_REG_CR7LT = 335
PPC_REG_CR0UN = 336
PPC_REG_CR1UN = 337
PPC_REG_CR2UN = 338
PPC_REG_CR3UN = 339
PPC_REG_CR4UN = 340
PPC_REG_CR5UN = 341
PPC_REG_CR6UN = 342
PPC_REG_CR7UN = 343
PPC_REG_ENDING = 344
PPC_INS_INVALID = 0
PPC_INS_ADD = 1
PPC_INS_ADDC = 2
PPC_INS_ADDE = 3
PPC_INS_ADDI = 4
PPC_INS_ADDIC = 5
PPC_INS_ADDIS = 6
PPC_INS_ADDME = 7
PPC_INS_ADDPCIS = 8
PPC_INS_ADDZE = 9
PPC_INS_AND = 10
PPC_INS_ANDC = 11
PPC_INS_ANDI = 12
PPC_INS_ANDIS = 13
PPC_INS_ATTN = 14
PPC_INS_B = 15
PPC_INS_BA = 16
PPC_INS_BC = 17
PPC_INS_BCA = 18
PPC_INS_BCCTR = 19
PPC_INS_BCCTRL = 20
PPC_INS_BCDCFN = 21
PPC_INS_BCDCFSQ = 22
PPC_INS_BCDCFZ = 23
PPC_INS_BCDCPSGN = 24
PPC_INS_BCDCTN = 25
PPC_INS_BCDCTSQ = 26
PPC_INS_BCDCTZ = 27
PPC_INS_BCDS = 28
PPC_INS_BCDSETSGN = 29
PPC_INS_BCDSR = 30
PPC_INS_BCDTRUNC = 31
PPC_INS_BCDUS = 32
PPC_INS_BCDUTRUNC = 33
PPC_INS_BCL = 34
PPC_INS_BCLA = 35
PPC_INS_BCLR = 36
PPC_INS_BCLRL = 37
PPC_INS_BCTR = 38
PPC_INS_BCTRL = 39
PPC_INS_BDNZ = 40
PPC_INS_BDNZA = 41
PPC_INS_BDNZF = 42
PPC_INS_BDNZFA = 43
PPC_INS_BDNZFL = 44
PPC_INS_BDNZFLA = 45
PPC_INS_BDNZFLR = 46
PPC_INS_BDNZFLRL = 47
PPC_INS_BDNZL = 48
PPC_INS_BDNZLA = 49
PPC_INS_BDNZLR = 50
PPC_INS_BDNZLRL = 51
PPC_INS_BDNZT = 52
PPC_INS_BDNZTA = 53
PPC_INS_BDNZTL = 54
PPC_INS_BDNZTLA = 55
PPC_INS_BDNZTLR = 56
PPC_INS_BDNZTLRL = 57
PPC_INS_BDZ = 58
PPC_INS_BDZA = 59
PPC_INS_BDZF = 60
PPC_INS_BDZFA = 61
PPC_INS_BDZFL = 62
PPC_INS_BDZFLA = 63
PPC_INS_BDZFLR = 64
PPC_INS_BDZFLRL = 65
PPC_INS_BDZL = 66
PPC_INS_BDZLA = 67
PPC_INS_BDZLR = 68
PPC_INS_BDZLRL = 69
PPC_INS_BDZT = 70
PPC_INS_BDZTA = 71
PPC_INS_BDZTL = 72
PPC_INS_BDZTLA = 73
PPC_INS_BDZTLR = 74
PPC_INS_BDZTLRL = 75
PPC_INS_BEQ = 76
PPC_INS_BEQA = 77
PPC_INS_BEQCTR = 78
PPC_INS_BEQCTRL = 79
PPC_INS_BEQL = 80
PPC_INS_BEQLA = 81
PPC_INS_BEQLR = 82
PPC_INS_BEQLRL = 83
PPC_INS_BF = 84
PPC_INS_BFA = 85
PPC_INS_BFCTR = 86
PPC_INS_BFCTRL = 87
PPC_INS_BFL = 88
PPC_INS_BFLA = 89
PPC_INS_BFLR = 90
PPC_INS_BFLRL = 91
PPC_INS_BGE = 92
PPC_INS_BGEA = 93
PPC_INS_BGECTR = 94
PPC_INS_BGECTRL = 95
PPC_INS_BGEL = 96
PPC_INS_BGELA = 97
PPC_INS_BGELR = 98
PPC_INS_BGELRL = 99
PPC_INS_BGT = 100
PPC_INS_BGTA = 101
PPC_INS_BGTCTR = 102
PPC_INS_BGTCTRL = 103
PPC_INS_BGTL = 104
PPC_INS_BGTLA = 105
PPC_INS_BGTLR = 106
PPC_INS_BGTLRL = 107
PPC_INS_BL = 108
PPC_INS_BLA = 109
PPC_INS_BLE = 110
PPC_INS_BLEA = 111
PPC_INS_BLECTR = 112
PPC_INS_BLECTRL = 113
PPC_INS_BLEL = 114
PPC_INS_BLELA = 115
PPC_INS_BLELR = 116
PPC_INS_BLELRL = 117
PPC_INS_BLR = 118
PPC_INS_BLRL = 119
PPC_INS_BLT = 120
PPC_INS_BLTA = 121
PPC_INS_BLTCTR = 122
PPC_INS_BLTCTRL = 123
PPC_INS_BLTL = 124
PPC_INS_BLTLA = 125
PPC_INS_BLTLR = 126
PPC_INS_BLTLRL = 127
PPC_INS_BNE = 128
PPC_INS_BNEA = 129
PPC_INS_BNECTR = 130
PPC_INS_BNECTRL = 131
PPC_INS_BNEL = 132
PPC_INS_BNELA = 133
PPC_INS_BNELR = 134
PPC_INS_BNELRL = 135
PPC_INS_BNG = 136
PPC_INS_BNGA = 137
PPC_INS_BNGCTR = 138
PPC_INS_BNGCTRL = 139
PPC_INS_BNGL = 140
PPC_INS_BNGLA = 141
PPC_INS_BNGLR = 142
PPC_INS_BNGLRL = 143
PPC_INS_BNL = 144
PPC_INS_BNLA = 145
PPC_INS_BNLCTR = 146
PPC_INS_BNLCTRL = 147
PPC_INS_BNLL = 148
PPC_INS_BNLLA = 149
PPC_INS_BNLLR = 150
PPC_INS_BNLLRL = 151
PPC_INS_BNS = 152
PPC_INS_BNSA = 153
PPC_INS_BNSCTR = 154
PPC_INS_BNSCTRL = 155
PPC_INS_BNSL = 156
PPC_INS_BNSLA = 157
PPC_INS_BNSLR = 158
PPC_INS_BNSLRL = 159
PPC_INS_BNU = 160
PPC_INS_BNUA = 161
PPC_INS_BNUCTR = 162
PPC_INS_BNUCTRL = 163
PPC_INS_BNUL = 164
PPC_INS_BNULA = 165
PPC_INS_BNULR = 166
PPC_INS_BNULRL = 167
PPC_INS_BPERMD = 168
PPC_INS_BRINC = 169
PPC_INS_BSO = 170
PPC_INS_BSOA = 171
PPC_INS_BSOCTR = 172
PPC_INS_BSOCTRL = 173
PPC_INS_BSOL = 174
PPC_INS_BSOLA = 175
PPC_INS_BSOLR = 176
PPC_INS_BSOLRL = 177
PPC_INS_BT = 178
PPC_INS_BTA = 179
PPC_INS_BTCTR = 180
PPC_INS_BTCTRL = 181
PPC_INS_BTL = 182
PPC_INS_BTLA = 183
PPC_INS_BTLR = 184
PPC_INS_BTLRL = 185
PPC_INS_BUN = 186
PPC_INS_BUNA = 187
PPC_INS_BUNCTR = 188
PPC_INS_BUNCTRL = 189
PPC_INS_BUNL = 190
PPC_INS_BUNLA = 191
PPC_INS_BUNLR = 192
PPC_INS_BUNLRL = 193
PPC_INS_CLRBHRB = 194
PPC_INS_CLRLDI = 195
PPC_INS_CLRLSLDI = 196
PPC_INS_CLRLSLWI = 197
PPC_INS_CLRLWI = 198
PPC_INS_CLRRDI = 199
PPC_INS_CLRRWI = 200
PPC_INS_CMP = 201
PPC_INS_CMPB = 202
PPC_INS_CMPD = 203
PPC_INS_CMPDI = 204
PPC_INS_CMPEQB = 205
PPC_INS_CMPI = 206
PPC_INS_CMPL = 207
PPC_INS_CMPLD = 208
PPC_INS_CMPLDI = 209
PPC_INS_CMPLI = 210
PPC_INS_CMPLW = 211
PPC_INS_CMPLWI = 212
PPC_INS_CMPRB = 213
PPC_INS_CMPW = 214
PPC_INS_CMPWI = 215
PPC_INS_CNTLZD = 216
PPC_INS_CNTLZW = 217
PPC_INS_CNTTZD = 218
PPC_INS_CNTTZW = 219
PPC_INS_COPY = 220
PPC_INS_COPY_FIRST = 221
PPC_INS_CP_ABORT = 222
PPC_INS_CRAND = 223
PPC_INS_CRANDC = 224
PPC_INS_CRCLR = 225
PPC_INS_CREQV = 226
PPC_INS_CRMOVE = 227
PPC_INS_CRNAND = 228
PPC_INS_CRNOR = 229
PPC_INS_CRNOT = 230
PPC_INS_CROR = 231
PPC_INS_CRORC = 232
PPC_INS_CRSET = 233
PPC_INS_CRXOR = 234
PPC_INS_DARN = 235
PPC_INS_DCBA = 236
PPC_INS_DCBF = 237
PPC_INS_DCBFEP = 238
PPC_INS_DCBFL = 239
PPC_INS_DCBFLP = 240
PPC_INS_DCBI = 241
PPC_INS_DCBST = 242
PPC_INS_DCBSTEP = 243
PPC_INS_DCBT = 244
PPC_INS_DCBTCT = 245
PPC_INS_DCBTDS = 246
PPC_INS_DCBTEP = 247
PPC_INS_DCBTST = 248
PPC_INS_DCBTSTCT = 249
PPC_INS_DCBTSTDS = 250
PPC_INS_DCBTSTEP = 251
PPC_INS_DCBTSTT = 252
PPC_INS_DCBTT = 253
PPC_INS_DCBZ = 254
PPC_INS_DCBZEP = 255
PPC_INS_DCBZL = 256
PPC_INS_DCBZLEP = 257
PPC_INS_DCCCI = 258
PPC_INS_DCI = 259
PPC_INS_DIVD = 260
PPC_INS_DIVDE = 261
PPC_INS_DIVDEU = 262
PPC_INS_DIVDU = 263
PPC_INS_DIVW = 264
PPC_INS_DIVWE = 265
PPC_INS_DIVWEU = 266
PPC_INS_DIVWU = 267
PPC_INS_DSS = 268
PPC_INS_DSSALL = 269
PPC_INS_DST = 270
PPC_INS_DSTST = 271
PPC_INS_DSTSTT = 272
PPC_INS_DSTT = 273
PPC_INS_EFDABS = 274
PPC_INS_EFDADD = 275
PPC_INS_EFDCFS = 276
PPC_INS_EFDCFSF = 277
PPC_INS_EFDCFSI = 278
PPC_INS_EFDCFSID = 279
PPC_INS_EFDCFUF = 280
PPC_INS_EFDCFUI = 281
PPC_INS_EFDCFUID = 282
PPC_INS_EFDCMPEQ = 283
PPC_INS_EFDCMPGT = 284
PPC_INS_EFDCMPLT = 285
PPC_INS_EFDCTSF = 286
PPC_INS_EFDCTSI = 287
PPC_INS_EFDCTSIDZ = 288
PPC_INS_EFDCTSIZ = 289
PPC_INS_EFDCTUF = 290
PPC_INS_EFDCTUI = 291
PPC_INS_EFDCTUIDZ = 292
PPC_INS_EFDCTUIZ = 293
PPC_INS_EFDDIV = 294
PPC_INS_EFDMUL = 295
PPC_INS_EFDNABS = 296
PPC_INS_EFDNEG = 297
PPC_INS_EFDSUB = 298
PPC_INS_EFDTSTEQ = 299
PPC_INS_EFDTSTGT = 300
PPC_INS_EFDTSTLT = 301
PPC_INS_EFSABS = 302
PPC_INS_EFSADD = 303
PPC_INS_EFSCFD = 304
PPC_INS_EFSCFSF = 305
PPC_INS_EFSCFSI = 306
PPC_INS_EFSCFUF = 307
PPC_INS_EFSCFUI = 308
PPC_INS_EFSCMPEQ = 309
PPC_INS_EFSCMPGT = 310
PPC_INS_EFSCMPLT = 311
PPC_INS_EFSCTSF = 312
PPC_INS_EFSCTSI = 313
PPC_INS_EFSCTSIZ = 314
PPC_INS_EFSCTUF = 315
PPC_INS_EFSCTUI = 316
PPC_INS_EFSCTUIZ = 317
PPC_INS_EFSDIV = 318
PPC_INS_EFSMUL = 319
PPC_INS_EFSNABS = 320
PPC_INS_EFSNEG = 321
PPC_INS_EFSSUB = 322
PPC_INS_EFSTSTEQ = 323
PPC_INS_EFSTSTGT = 324
PPC_INS_EFSTSTLT = 325
PPC_INS_EIEIO = 326
PPC_INS_EQV = 327
PPC_INS_EVABS = 328
PPC_INS_EVADDIW = 329
PPC_INS_EVADDSMIAAW = 330
PPC_INS_EVADDSSIAAW = 331
PPC_INS_EVADDUMIAAW = 332
PPC_INS_EVADDUSIAAW = 333
PPC_INS_EVADDW = 334
PPC_INS_EVAND = 335
PPC_INS_EVANDC = 336
PPC_INS_EVCMPEQ = 337
PPC_INS_EVCMPGTS = 338
PPC_INS_EVCMPGTU = 339
PPC_INS_EVCMPLTS = 340
PPC_INS_EVCMPLTU = 341
PPC_INS_EVCNTLSW = 342
PPC_INS_EVCNTLZW = 343
PPC_INS_EVDIVWS = 344
PPC_INS_EVDIVWU = 345
PPC_INS_EVEQV = 346
PPC_INS_EVEXTSB = 347
PPC_INS_EVEXTSH = 348
PPC_INS_EVFSABS = 349
PPC_INS_EVFSADD = 350
PPC_INS_EVFSCFSF = 351
PPC_INS_EVFSCFSI = 352
PPC_INS_EVFSCFUF = 353
PPC_INS_EVFSCFUI = 354
PPC_INS_EVFSCMPEQ = 355
PPC_INS_EVFSCMPGT = 356
PPC_INS_EVFSCMPLT = 357
PPC_INS_EVFSCTSF = 358
PPC_INS_EVFSCTSI = 359
PPC_INS_EVFSCTSIZ = 360
PPC_INS_EVFSCTUI = 361
PPC_INS_EVFSDIV = 362
PPC_INS_EVFSMUL = 363
PPC_INS_EVFSNABS = 364
PPC_INS_EVFSNEG = 365
PPC_INS_EVFSSUB = 366
PPC_INS_EVFSTSTEQ = 367
PPC_INS_EVFSTSTGT = 368
PPC_INS_EVFSTSTLT = 369
PPC_INS_EVLDD = 370
PPC_INS_EVLDDX = 371
PPC_INS_EVLDH = 372
PPC_INS_EVLDHX = 373
PPC_INS_EVLDW = 374
PPC_INS_EVLDWX = 375
PPC_INS_EVLHHESPLAT = 376
PPC_INS_EVLHHESPLATX = 377
PPC_INS_EVLHHOSSPLAT = 378
PPC_INS_EVLHHOSSPLATX = 379
PPC_INS_EVLHHOUSPLAT = 380
PPC_INS_EVLHHOUSPLATX = 381
PPC_INS_EVLWHE = 382
PPC_INS_EVLWHEX = 383
PPC_INS_EVLWHOS = 384
PPC_INS_EVLWHOSX = 385
PPC_INS_EVLWHOU = 386
PPC_INS_EVLWHOUX = 387
PPC_INS_EVLWHSPLAT = 388
PPC_INS_EVLWHSPLATX = 389
PPC_INS_EVLWWSPLAT = 390
PPC_INS_EVLWWSPLATX = 391
PPC_INS_EVMERGEHI = 392
PPC_INS_EVMERGEHILO = 393
PPC_INS_EVMERGELO = 394
PPC_INS_EVMERGELOHI = 395
PPC_INS_EVMHEGSMFAA = 396
PPC_INS_EVMHEGSMFAN = 397
PPC_INS_EVMHEGSMIAA = 398
PPC_INS_EVMHEGSMIAN = 399
PPC_INS_EVMHEGUMIAA = 400
PPC_INS_EVMHEGUMIAN = 401
PPC_INS_EVMHESMF = 402
PPC_INS_EVMHESMFA = 403
PPC_INS_EVMHESMFAAW = 404
PPC_INS_EVMHESMFANW = 405
PPC_INS_EVMHESMI = 406
PPC_INS_EVMHESMIA = 407
PPC_INS_EVMHESMIAAW = 408
PPC_INS_EVMHESMIANW = 409
PPC_INS_EVMHESSF = 410
PPC_INS_EVMHESSFA = 411
PPC_INS_EVMHESSFAAW = 412
PPC_INS_EVMHESSFANW = 413
PPC_INS_EVMHESSIAAW = 414
PPC_INS_EVMHESSIANW = 415
PPC_INS_EVMHEUMI = 416
PPC_INS_EVMHEUMIA = 417
PPC_INS_EVMHEUMIAAW = 418
PPC_INS_EVMHEUMIANW = 419
PPC_INS_EVMHEUSIAAW = 420
PPC_INS_EVMHEUSIANW = 421
PPC_INS_EVMHOGSMFAA = 422
PPC_INS_EVMHOGSMFAN = 423
PPC_INS_EVMHOGSMIAA = 424
PPC_INS_EVMHOGSMIAN = 425
PPC_INS_EVMHOGUMIAA = 426
PPC_INS_EVMHOGUMIAN = 427
PPC_INS_EVMHOSMF = 428
PPC_INS_EVMHOSMFA = 429
PPC_INS_EVMHOSMFAAW = 430
PPC_INS_EVMHOSMFANW = 431
PPC_INS_EVMHOSMI = 432
PPC_INS_EVMHOSMIA = 433
PPC_INS_EVMHOSMIAAW = 434
PPC_INS_EVMHOSMIANW = 435
PPC_INS_EVMHOSSF = 436
PPC_INS_EVMHOSSFA = 437
PPC_INS_EVMHOSSFAAW = 438
PPC_INS_EVMHOSSFANW = 439
PPC_INS_EVMHOSSIAAW = 440
PPC_INS_EVMHOSSIANW = 441
PPC_INS_EVMHOUMI = 442
PPC_INS_EVMHOUMIA = 443
PPC_INS_EVMHOUMIAAW = 444
PPC_INS_EVMHOUMIANW = 445
PPC_INS_EVMHOUSIAAW = 446
PPC_INS_EVMHOUSIANW = 447
PPC_INS_EVMRA = 448
PPC_INS_EVMWHSMF = 449
PPC_INS_EVMWHSMFA = 450
PPC_INS_EVMWHSMI = 451
PPC_INS_EVMWHSMIA = 452
PPC_INS_EVMWHSSF = 453
PPC_INS_EVMWHSSFA = 454
PPC_INS_EVMWHUMI = 455
PPC_INS_EVMWHUMIA = 456
PPC_INS_EVMWLSMIAAW = 457
PPC_INS_EVMWLSMIANW = 458
PPC_INS_EVMWLSSIAAW = 459
PPC_INS_EVMWLSSIANW = 460
PPC_INS_EVMWLUMI = 461
PPC_INS_EVMWLUMIA = 462
PPC_INS_EVMWLUMIAAW = 463
PPC_INS_EVMWLUMIANW = 464
PPC_INS_EVMWLUSIAAW = 465
PPC_INS_EVMWLUSIANW = 466
PPC_INS_EVMWSMF = 467
PPC_INS_EVMWSMFA = 468
PPC_INS_EVMWSMFAA = 469
PPC_INS_EVMWSMFAN = 470
PPC_INS_EVMWSMI = 471
PPC_INS_EVMWSMIA = 472
PPC_INS_EVMWSMIAA = 473
PPC_INS_EVMWSMIAN = 474
PPC_INS_EVMWSSF = 475
PPC_INS_EVMWSSFA = 476
PPC_INS_EVMWSSFAA = 477
PPC_INS_EVMWSSFAN = 478
PPC_INS_EVMWUMI = 479
PPC_INS_EVMWUMIA = 480
PPC_INS_EVMWUMIAA = 481
PPC_INS_EVMWUMIAN = 482
PPC_INS_EVNAND = 483
PPC_INS_EVNEG = 484
PPC_INS_EVNOR = 485
PPC_INS_EVOR = 486
PPC_INS_EVORC = 487
PPC_INS_EVRLW = 488
PPC_INS_EVRLWI = 489
PPC_INS_EVRNDW = 490
PPC_INS_EVSEL = 491
PPC_INS_EVSLW = 492
PPC_INS_EVSLWI = 493
PPC_INS_EVSPLATFI = 494
PPC_INS_EVSPLATI = 495
PPC_INS_EVSRWIS = 496
PPC_INS_EVSRWIU = 497
PPC_INS_EVSRWS = 498
PPC_INS_EVSRWU = 499
PPC_INS_EVSTDD = 500
PPC_INS_EVSTDDX = 501
PPC_INS_EVSTDH = 502
PPC_INS_EVSTDHX = 503
PPC_INS_EVSTDW = 504
PPC_INS_EVSTDWX = 505
PPC_INS_EVSTWHE = 506
PPC_INS_EVSTWHEX = 507
PPC_INS_EVSTWHO = 508
PPC_INS_EVSTWHOX = 509
PPC_INS_EVSTWWE = 510
PPC_INS_EVSTWWEX = 511
PPC_INS_EVSTWWO = 512
PPC_INS_EVSTWWOX = 513
PPC_INS_EVSUBFSMIAAW = 514
PPC_INS_EVSUBFSSIAAW = 515
PPC_INS_EVSUBFUMIAAW = 516
PPC_INS_EVSUBFUSIAAW = 517
PPC_INS_EVSUBFW = 518
PPC_INS_EVSUBIFW = 519
PPC_INS_EVXOR = 520
PPC_INS_EXTLDI = 521
PPC_INS_EXTLWI = 522
PPC_INS_EXTRDI = 523
PPC_INS_EXTRWI = 524
PPC_INS_EXTSB = 525
PPC_INS_EXTSH = 526
PPC_INS_EXTSW = 527
PPC_INS_EXTSWSLI = 528
PPC_INS_FABS = 529
PPC_INS_FADD = 530
PPC_INS_FADDS = 531
PPC_INS_FCFID = 532
PPC_INS_FCFIDS = 533
PPC_INS_FCFIDU = 534
PPC_INS_FCFIDUS = 535
PPC_INS_FCMPU = 536
PPC_INS_FCPSGN = 537
PPC_INS_FCTID = 538
PPC_INS_FCTIDU = 539
PPC_INS_FCTIDUZ = 540
PPC_INS_FCTIDZ = 541
PPC_INS_FCTIW = 542
PPC_INS_FCTIWU = 543
PPC_INS_FCTIWUZ = 544
PPC_INS_FCTIWZ = 545
PPC_INS_FDIV = 546
PPC_INS_FDIVS = 547
PPC_INS_FMADD = 548
PPC_INS_FMADDS = 549
PPC_INS_FMR = 550
PPC_INS_FMSUB = 551
PPC_INS_FMSUBS = 552
PPC_INS_FMUL = 553
PPC_INS_FMULS = 554
PPC_INS_FNABS = 555
PPC_INS_FNEG = 556
PPC_INS_FNMADD = 557
PPC_INS_FNMADDS = 558
PPC_INS_FNMSUB = 559
PPC_INS_FNMSUBS = 560
PPC_INS_FRE = 561
PPC_INS_FRES = 562
PPC_INS_FRIM = 563
PPC_INS_FRIN = 564
PPC_INS_FRIP = 565
PPC_INS_FRIZ = 566
PPC_INS_FRSP = 567
PPC_INS_FRSQRTE = 568
PPC_INS_FRSQRTES = 569
PPC_INS_FSEL = 570
PPC_INS_FSQRT = 571
PPC_INS_FSQRTS = 572
PPC_INS_FSUB = 573
PPC_INS_FSUBS = 574
PPC_INS_FTDIV = 575
PPC_INS_FTSQRT = 576
PPC_INS_HRFID = 577
PPC_INS_ICBI = 578
PPC_INS_ICBIEP = 579
PPC_INS_ICBLC = 580
PPC_INS_ICBLQ = 581
PPC_INS_ICBT = 582
PPC_INS_ICBTLS = 583
PPC_INS_ICCCI = 584
PPC_INS_ICI = 585
PPC_INS_INSLWI = 586
PPC_INS_INSRDI = 587
PPC_INS_INSRWI = 588
PPC_INS_ISEL = 589
PPC_INS_ISYNC = 590
PPC_INS_LA = 591
PPC_INS_LBARX = 592
PPC_INS_LBEPX = 593
PPC_INS_LBZ = 594
PPC_INS_LBZCIX = 595
PPC_INS_LBZU = 596
PPC_INS_LBZUX = 597
PPC_INS_LBZX = 598
PPC_INS_LD = 599
PPC_INS_LDARX = 600
PPC_INS_LDAT = 601
PPC_INS_LDBRX = 602
PPC_INS_LDCIX = 603
PPC_INS_LDMX = 604
PPC_INS_LDU = 605
PPC_INS_LDUX = 606
PPC_INS_LDX = 607
PPC_INS_LFD = 608
PPC_INS_LFDEPX = 609
PPC_INS_LFDU = 610
PPC_INS_LFDUX = 611
PPC_INS_LFDX = 612
PPC_INS_LFIWAX = 613
PPC_INS_LFIWZX = 614
PPC_INS_LFS = 615
PPC_INS_LFSU = 616
PPC_INS_LFSUX = 617
PPC_INS_LFSX = 618
PPC_INS_LHA = 619
PPC_INS_LHARX = 620
PPC_INS_LHAU = 621
PPC_INS_LHAUX = 622
PPC_INS_LHAX = 623
PPC_INS_LHBRX = 624
PPC_INS_LHEPX = 625
PPC_INS_LHZ = 626
PPC_INS_LHZCIX = 627
PPC_INS_LHZU = 628
PPC_INS_LHZUX = 629
PPC_INS_LHZX = 630
PPC_INS_LI = 631
PPC_INS_LIS = 632
PPC_INS_LMW = 633
PPC_INS_LNIA = 634
PPC_INS_LSWI = 635
PPC_INS_LVEBX = 636
PPC_INS_LVEHX = 637
PPC_INS_LVEWX = 638
PPC_INS_LVSL = 639
PPC_INS_LVSR = 640
PPC_INS_LVX = 641
PPC_INS_LVXL = 642
PPC_INS_LWA = 643
PPC_INS_LWARX = 644
PPC_INS_LWAT = 645
PPC_INS_LWAUX = 646
PPC_INS_LWAX = 647
PPC_INS_LWBRX = 648
PPC_INS_LWEPX = 649
PPC_INS_LWSYNC = 650
PPC_INS_LWZ = 651
PPC_INS_LWZCIX = 652
PPC_INS_LWZU = 653
PPC_INS_LWZUX = 654
PPC_INS_LWZX = 655
PPC_INS_LXSD = 656
PPC_INS_LXSDX = 657
PPC_INS_LXSIBZX = 658
PPC_INS_LXSIHZX = 659
PPC_INS_LXSIWAX = 660
PPC_INS_LXSIWZX = 661
PPC_INS_LXSSP = 662
PPC_INS_LXSSPX = 663
PPC_INS_LXV = 664
PPC_INS_LXVB16X = 665
PPC_INS_LXVD2X = 666
PPC_INS_LXVDSX = 667
PPC_INS_LXVH8X = 668
PPC_INS_LXVL = 669
PPC_INS_LXVLL = 670
PPC_INS_LXVW4X = 671
PPC_INS_LXVWSX = 672
PPC_INS_LXVX = 673
PPC_INS_MADDHD = 674
PPC_INS_MADDHDU = 675
PPC_INS_MADDLD = 676
PPC_INS_MBAR = 677
PPC_INS_MCRF = 678
PPC_INS_MCRFS = 679
PPC_INS_MCRXRX = 680
PPC_INS_MFAMR = 681
PPC_INS_MFASR = 682
PPC_INS_MFBHRBE = 683
PPC_INS_MFBR0 = 684
PPC_INS_MFBR1 = 685
PPC_INS_MFBR2 = 686
PPC_INS_MFBR3 = 687
PPC_INS_MFBR4 = 688
PPC_INS_MFBR5 = 689
PPC_INS_MFBR6 = 690
PPC_INS_MFBR7 = 691
PPC_INS_MFCFAR = 692
PPC_INS_MFCR = 693
PPC_INS_MFCTR = 694
PPC_INS_MFDAR = 695
PPC_INS_MFDBATL = 696
PPC_INS_MFDBATU = 697
PPC_INS_MFDCCR = 698
PPC_INS_MFDCR = 699
PPC_INS_MFDEAR = 700
PPC_INS_MFDEC = 701
PPC_INS_MFDSCR = 702
PPC_INS_MFDSISR = 703
PPC_INS_MFESR = 704
PPC_INS_MFFPRD = 705
PPC_INS_MFFS = 706
PPC_INS_MFFSCDRN = 707
PPC_INS_MFFSCDRNI = 708
PPC_INS_MFFSCE = 709
PPC_INS_MFFSCRN = 710
PPC_INS_MFFSCRNI = 711
PPC_INS_MFFSL = 712
PPC_INS_MFIBATL = 713
PPC_INS_MFIBATU = 714
PPC_INS_MFICCR = 715
PPC_INS_MFLR = 716
PPC_INS_MFMSR = 717
PPC_INS_MFOCRF = 718
PPC_INS_MFPID = 719
PPC_INS_MFPMR = 720
PPC_INS_MFPVR = 721
PPC_INS_MFRTCL = 722
PPC_INS_MFRTCU = 723
PPC_INS_MFSDR1 = 724
PPC_INS_MFSPEFSCR = 725
PPC_INS_MFSPR = 726
PPC_INS_MFSPRG = 727
PPC_INS_MFSPRG0 = 728
PPC_INS_MFSPRG1 = 729
PPC_INS_MFSPRG2 = 730
PPC_INS_MFSPRG3 = 731
PPC_INS_MFSPRG4 = 732
PPC_INS_MFSPRG5 = 733
PPC_INS_MFSPRG6 = 734
PPC_INS_MFSPRG7 = 735
PPC_INS_MFSR = 736
PPC_INS_MFSRIN = 737
PPC_INS_MFSRR0 = 738
PPC_INS_MFSRR1 = 739
PPC_INS_MFSRR2 = 740
PPC_INS_MFSRR3 = 741
PPC_INS_MFTB = 742
PPC_INS_MFTBHI = 743
PPC_INS_MFTBL = 744
PPC_INS_MFTBLO = 745
PPC_INS_MFTBU = 746
PPC_INS_MFTCR = 747
PPC_INS_MFVRD = 748
PPC_INS_MFVRSAVE = 749
PPC_INS_MFVSCR = 750
PPC_INS_MFVSRD = 751
PPC_INS_MFVSRLD = 752
PPC_INS_MFVSRWZ = 753
PPC_INS_MFXER = 754
PPC_INS_MODSD = 755
PPC_INS_MODSW = 756
PPC_INS_MODUD = 757
PPC_INS_MODUW = 758
PPC_INS_MR = 759
PPC_INS_MSGSYNC = 760
PPC_INS_MSYNC = 761
PPC_INS_MTAMR = 762
PPC_INS_MTASR = 763
PPC_INS_MTBR0 = 764
PPC_INS_MTBR1 = 765
PPC_INS_MTBR2 = 766
PPC_INS_MTBR3 = 767
PPC_INS_MTBR4 = 768
PPC_INS_MTBR5 = 769
PPC_INS_MTBR6 = 770
PPC_INS_MTBR7 = 771
PPC_INS_MTCFAR = 772
PPC_INS_MTCR = 773
PPC_INS_MTCRF = 774
PPC_INS_MTCTR = 775
PPC_INS_MTDAR = 776
PPC_INS_MTDBATL = 777
PPC_INS_MTDBATU = 778
PPC_INS_MTDCCR = 779
PPC_INS_MTDCR = 780
PPC_INS_MTDEAR = 781
PPC_INS_MTDEC = 782
PPC_INS_MTDSCR = 783
PPC_INS_MTDSISR = 784
PPC_INS_MTESR = 785
PPC_INS_MTFSB0 = 786
PPC_INS_MTFSB1 = 787
PPC_INS_MTFSF = 788
PPC_INS_MTFSFI = 789
PPC_INS_MTIBATL = 790
PPC_INS_MTIBATU = 791
PPC_INS_MTICCR = 792
PPC_INS_MTLR = 793
PPC_INS_MTMSR = 794
PPC_INS_MTMSRD = 795
PPC_INS_MTOCRF = 796
PPC_INS_MTPID = 797
PPC_INS_MTPMR = 798
PPC_INS_MTSDR1 = 799
PPC_INS_MTSPEFSCR = 800
PPC_INS_MTSPR = 801
PPC_INS_MTSPRG = 802
PPC_INS_MTSPRG0 = 803
PPC_INS_MTSPRG1 = 804
PPC_INS_MTSPRG2 = 805
PPC_INS_MTSPRG3 = 806
PPC_INS_MTSPRG4 = 807
PPC_INS_MTSPRG5 = 808
PPC_INS_MTSPRG6 = 809
PPC_INS_MTSPRG7 = 810
PPC_INS_MTSR = 811
PPC_INS_MTSRIN = 812
PPC_INS_MTSRR0 = 813
PPC_INS_MTSRR1 = 814
PPC_INS_MTSRR2 = 815
PPC_INS_MTSRR3 = 816
PPC_INS_MTTBHI = 817
PPC_INS_MTTBL = 818
PPC_INS_MTTBLO = 819
PPC_INS_MTTBU = 820
PPC_INS_MTTCR = 821
PPC_INS_MTVRSAVE = 822
PPC_INS_MTVSCR = 823
PPC_INS_MTVSRD = 824
PPC_INS_MTVSRDD = 825
PPC_INS_MTVSRWA = 826
PPC_INS_MTVSRWS = 827
PPC_INS_MTVSRWZ = 828
PPC_INS_MTXER = 829
PPC_INS_MULHD = 830
PPC_INS_MULHDU = 831
PPC_INS_MULHW = 832
PPC_INS_MULHWU = 833
PPC_INS_MULLD = 834
PPC_INS_MULLI = 835
PPC_INS_MULLW = 836
PPC_INS_NAND = 837
PPC_INS_NAP = 838
PPC_INS_NEG = 839
PPC_INS_NOP = 840
PPC_INS_NOR = 841
PPC_INS_NOT = 842
PPC_INS_OR = 843
PPC_INS_ORC = 844
PPC_INS_ORI = 845
PPC_INS_ORIS = 846
PPC_INS_PASTE = 847
PPC_INS_PASTE_LAST = 848
PPC_INS_POPCNTB = 849
PPC_INS_POPCNTD = 850
PPC_INS_POPCNTW = 851
PPC_INS_PTESYNC = 852
PPC_INS_QVALIGNI = 853
PPC_INS_QVESPLATI = 854
PPC_INS_QVFABS = 855
PPC_INS_QVFADD = 856
PPC_INS_QVFADDS = 857
PPC_INS_QVFAND = 858
PPC_INS_QVFANDC = 859
PPC_INS_QVFCFID = 860
PPC_INS_QVFCFIDS = 861
PPC_INS_QVFCFIDU = 862
PPC_INS_QVFCFIDUS = 863
PPC_INS_QVFCLR = 864
PPC_INS_QVFCMPEQ = 865
PPC_INS_QVFCMPGT = 866
PPC_INS_QVFCMPLT = 867
PPC_INS_QVFCPSGN = 868
PPC_INS_QVFCTFB = 869
PPC_INS_QVFCTID = 870
PPC_INS_QVFCTIDU = 871
PPC_INS_QVFCTIDUZ = 872
PPC_INS_QVFCTIDZ = 873
PPC_INS_QVFCTIW = 874
PPC_INS_QVFCTIWU = 875
PPC_INS_QVFCTIWUZ = 876
PPC_INS_QVFCTIWZ = 877
PPC_INS_QVFEQU = 878
PPC_INS_QVFLOGICAL = 879
PPC_INS_QVFMADD = 880
PPC_INS_QVFMADDS = 881
PPC_INS_QVFMR = 882
PPC_INS_QVFMSUB = 883
PPC_INS_QVFMSUBS = 884
PPC_INS_QVFMUL = 885
PPC_INS_QVFMULS = 886
PPC_INS_QVFNABS = 887
PPC_INS_QVFNAND = 888
PPC_INS_QVFNEG = 889
PPC_INS_QVFNMADD = 890
PPC_INS_QVFNMADDS = 891
PPC_INS_QVFNMSUB = 892
PPC_INS_QVFNMSUBS = 893
PPC_INS_QVFNOR = 894
PPC_INS_QVFNOT = 895
PPC_INS_QVFOR = 896
PPC_INS_QVFORC = 897
PPC_INS_QVFPERM = 898
PPC_INS_QVFRE = 899
PPC_INS_QVFRES = 900
PPC_INS_QVFRIM = 901
PPC_INS_QVFRIN = 902
PPC_INS_QVFRIP = 903
PPC_INS_QVFRIZ = 904
PPC_INS_QVFRSP = 905
PPC_INS_QVFRSQRTE = 906
PPC_INS_QVFRSQRTES = 907
PPC_INS_QVFSEL = 908
PPC_INS_QVFSET = 909
PPC_INS_QVFSUB = 910
PPC_INS_QVFSUBS = 911
PPC_INS_QVFTSTNAN = 912
PPC_INS_QVFXMADD = 913
PPC_INS_QVFXMADDS = 914
PPC_INS_QVFXMUL = 915
PPC_INS_QVFXMULS = 916
PPC_INS_QVFXOR = 917
PPC_INS_QVFXXCPNMADD = 918
PPC_INS_QVFXXCPNMADDS = 919
PPC_INS_QVFXXMADD = 920
PPC_INS_QVFXXMADDS = 921
PPC_INS_QVFXXNPMADD = 922
PPC_INS_QVFXXNPMADDS = 923
PPC_INS_QVGPCI = 924
PPC_INS_QVLFCDUX = 925
PPC_INS_QVLFCDUXA = 926
PPC_INS_QVLFCDX = 927
PPC_INS_QVLFCDXA = 928
PPC_INS_QVLFCSUX = 929
PPC_INS_QVLFCSUXA = 930
PPC_INS_QVLFCSX = 931
PPC_INS_QVLFCSXA = 932
PPC_INS_QVLFDUX = 933
PPC_INS_QVLFDUXA = 934
PPC_INS_QVLFDX = 935
PPC_INS_QVLFDXA = 936
PPC_INS_QVLFIWAX = 937
PPC_INS_QVLFIWAXA = 938
PPC_INS_QVLFIWZX = 939
PPC_INS_QVLFIWZXA = 940
PPC_INS_QVLFSUX = 941
PPC_INS_QVLFSUXA = 942
PPC_INS_QVLFSX = 943
PPC_INS_QVLFSXA = 944
PPC_INS_QVLPCLDX = 945
PPC_INS_QVLPCLSX = 946
PPC_INS_QVLPCRDX = 947
PPC_INS_QVLPCRSX = 948
PPC_INS_QVSTFCDUX = 949
PPC_INS_QVSTFCDUXA = 950
PPC_INS_QVSTFCDUXI = 951
PPC_INS_QVSTFCDUXIA = 952
PPC_INS_QVSTFCDX = 953
PPC_INS_QVSTFCDXA = 954
PPC_INS_QVSTFCDXI = 955
PPC_INS_QVSTFCDXIA = 956
PPC_INS_QVSTFCSUX = 957
PPC_INS_QVSTFCSUXA = 958
PPC_INS_QVSTFCSUXI = 959
PPC_INS_QVSTFCSUXIA = 960
PPC_INS_QVSTFCSX = 961
PPC_INS_QVSTFCSXA = 962
PPC_INS_QVSTFCSXI = 963
PPC_INS_QVSTFCSXIA = 964
PPC_INS_QVSTFDUX = 965
PPC_INS_QVSTFDUXA = 966
PPC_INS_QVSTFDUXI = 967
PPC_INS_QVSTFDUXIA = 968
PPC_INS_QVSTFDX = 969
PPC_INS_QVSTFDXA = 970
PPC_INS_QVSTFDXI = 971
PPC_INS_QVSTFDXIA = 972
PPC_INS_QVSTFIWX = 973
PPC_INS_QVSTFIWXA = 974
PPC_INS_QVSTFSUX = 975
PPC_INS_QVSTFSUXA = 976
PPC_INS_QVSTFSUXI = 977
PPC_INS_QVSTFSUXIA = 978
PPC_INS_QVSTFSX = 979
PPC_INS_QVSTFSXA = 980
PPC_INS_QVSTFSXI = 981
PPC_INS_QVSTFSXIA = 982
PPC_INS_RFCI = 983
PPC_INS_RFDI = 984
PPC_INS_RFEBB = 985
PPC_INS_RFI = 986
PPC_INS_RFID = 987
PPC_INS_RFMCI = 988
PPC_INS_RLDCL = 989
PPC_INS_RLDCR = 990
PPC_INS_RLDIC = 991
PPC_INS_RLDICL = 992
PPC_INS_RLDICR = 993
PPC_INS_RLDIMI = 994
PPC_INS_RLWIMI = 995
PPC_INS_RLWINM = 996
PPC_INS_RLWNM = 997
PPC_INS_ROTLD = 998
PPC_INS_ROTLDI = 999
PPC_INS_ROTLW = 1000
PPC_INS_ROTLWI = 1001
PPC_INS_ROTRDI = 1002
PPC_INS_ROTRWI = 1003
PPC_INS_SC = 1004
PPC_INS_SETB = 1005
PPC_INS_SLBIA = 1006
PPC_INS_SLBIE = 1007
PPC_INS_SLBIEG = 1008
PPC_INS_SLBMFEE = 1009
PPC_INS_SLBMFEV = 1010
PPC_INS_SLBMTE = 1011
PPC_INS_SLBSYNC = 1012
PPC_INS_SLD = 1013
PPC_INS_SLDI = 1014
PPC_INS_SLW = 1015
PPC_INS_SLWI = 1016
PPC_INS_SRAD = 1017
PPC_INS_SRADI = 1018
PPC_INS_SRAW = 1019
PPC_INS_SRAWI = 1020
PPC_INS_SRD = 1021
PPC_INS_SRDI = 1022
PPC_INS_SRW = 1023
PPC_INS_SRWI = 1024
PPC_INS_STB = 1025
PPC_INS_STBCIX = 1026
PPC_INS_STBCX = 1027
PPC_INS_STBEPX = 1028
PPC_INS_STBU = 1029
PPC_INS_STBUX = 1030
PPC_INS_STBX = 1031
PPC_INS_STD = 1032
PPC_INS_STDAT = 1033
PPC_INS_STDBRX = 1034
PPC_INS_STDCIX = 1035
PPC_INS_STDCX = 1036
PPC_INS_STDU = 1037
PPC_INS_STDUX = 1038
PPC_INS_STDX = 1039
PPC_INS_STFD = 1040
PPC_INS_STFDEPX = 1041
PPC_INS_STFDU = 1042
PPC_INS_STFDUX = 1043
PPC_INS_STFDX = 1044
PPC_INS_STFIWX = 1045
PPC_INS_STFS = 1046
PPC_INS_STFSU = 1047
PPC_INS_STFSUX = 1048
PPC_INS_STFSX = 1049
PPC_INS_STH = 1050
PPC_INS_STHBRX = 1051
PPC_INS_STHCIX = 1052
PPC_INS_STHCX = 1053
PPC_INS_STHEPX = 1054
PPC_INS_STHU = 1055
PPC_INS_STHUX = 1056
PPC_INS_STHX = 1057
PPC_INS_STMW = 1058
PPC_INS_STOP = 1059
PPC_INS_STSWI = 1060
PPC_INS_STVEBX = 1061
PPC_INS_STVEHX = 1062
PPC_INS_STVEWX = 1063
PPC_INS_STVX = 1064
PPC_INS_STVXL = 1065
PPC_INS_STW = 1066
PPC_INS_STWAT = 1067
PPC_INS_STWBRX = 1068
PPC_INS_STWCIX = 1069
PPC_INS_STWCX = 1070
PPC_INS_STWEPX = 1071
PPC_INS_STWU = 1072
PPC_INS_STWUX = 1073
PPC_INS_STWX = 1074
PPC_INS_STXSD = 1075
PPC_INS_STXSDX = 1076
PPC_INS_STXSIBX = 1077
PPC_INS_STXSIHX = 1078
PPC_INS_STXSIWX = 1079
PPC_INS_STXSSP = 1080
PPC_INS_STXSSPX = 1081
PPC_INS_STXV = 1082
PPC_INS_STXVB16X = 1083
PPC_INS_STXVD2X = 1084
PPC_INS_STXVH8X = 1085
PPC_INS_STXVL = 1086
PPC_INS_STXVLL = 1087
PPC_INS_STXVW4X = 1088
PPC_INS_STXVX = 1089
PPC_INS_SUB = 1090
PPC_INS_SUBC = 1091
PPC_INS_SUBF = 1092
PPC_INS_SUBFC = 1093
PPC_INS_SUBFE = 1094
PPC_INS_SUBFIC = 1095
PPC_INS_SUBFME = 1096
PPC_INS_SUBFZE = 1097
PPC_INS_SUBI = 1098
PPC_INS_SUBIC = 1099
PPC_INS_SUBIS = 1100
PPC_INS_SUBPCIS = 1101
PPC_INS_SYNC = 1102
PPC_INS_TABORT = 1103
PPC_INS_TABORTDC = 1104
PPC_INS_TABORTDCI = 1105
PPC_INS_TABORTWC = 1106
PPC_INS_TABORTWCI = 1107
PPC_INS_TBEGIN = 1108
PPC_INS_TCHECK = 1109
PPC_INS_TD = 1110
PPC_INS_TDEQ = 1111
PPC_INS_TDEQI = 1112
PPC_INS_TDGE = 1113
PPC_INS_TDGEI = 1114
PPC_INS_TDGT = 1115
PPC_INS_TDGTI = 1116
PPC_INS_TDI = 1117
PPC_INS_TDLE = 1118
PPC_INS_TDLEI = 1119
PPC_INS_TDLGE = 1120
PPC_INS_TDLGEI = 1121
PPC_INS_TDLGT = 1122
PPC_INS_TDLGTI = 1123
PPC_INS_TDLLE = 1124
PPC_INS_TDLLEI = 1125
PPC_INS_TDLLT = 1126
PPC_INS_TDLLTI = 1127
PPC_INS_TDLNG = 1128
PPC_INS_TDLNGI = 1129
PPC_INS_TDLNL = 1130
PPC_INS_TDLNLI = 1131
PPC_INS_TDLT = 1132
PPC_INS_TDLTI = 1133
PPC_INS_TDNE = 1134
PPC_INS_TDNEI = 1135
PPC_INS_TDNG = 1136
PPC_INS_TDNGI = 1137
PPC_INS_TDNL = 1138
PPC_INS_TDNLI = 1139
PPC_INS_TDU = 1140
PPC_INS_TDUI = 1141
PPC_INS_TEND = 1142
PPC_INS_TLBIA = 1143
PPC_INS_TLBIE = 1144
PPC_INS_TLBIEL = 1145
PPC_INS_TLBIVAX = 1146
PPC_INS_TLBLD = 1147
PPC_INS_TLBLI = 1148
PPC_INS_TLBRE = 1149
PPC_INS_TLBREHI = 1150
PPC_INS_TLBRELO = 1151
PPC_INS_TLBSX = 1152
PPC_INS_TLBSYNC = 1153
PPC_INS_TLBWE = 1154
PPC_INS_TLBWEHI = 1155
PPC_INS_TLBWELO = 1156
PPC_INS_TRAP = 1157
PPC_INS_TRECHKPT = 1158
PPC_INS_TRECLAIM = 1159
PPC_INS_TSR = 1160
PPC_INS_TW = 1161
PPC_INS_TWEQ = 1162
PPC_INS_TWEQI = 1163
PPC_INS_TWGE = 1164
PPC_INS_TWGEI = 1165
PPC_INS_TWGT = 1166
PPC_INS_TWGTI = 1167
PPC_INS_TWI = 1168
PPC_INS_TWLE = 1169
PPC_INS_TWLEI = 1170
PPC_INS_TWLGE = 1171
PPC_INS_TWLGEI = 1172
PPC_INS_TWLGT = 1173
PPC_INS_TWLGTI = 1174
PPC_INS_TWLLE = 1175
PPC_INS_TWLLEI = 1176
PPC_INS_TWLLT = 1177
PPC_INS_TWLLTI = 1178
PPC_INS_TWLNG = 1179
PPC_INS_TWLNGI = 1180
PPC_INS_TWLNL = 1181
PPC_INS_TWLNLI = 1182
PPC_INS_TWLT = 1183
PPC_INS_TWLTI = 1184
PPC_INS_TWNE = 1185
PPC_INS_TWNEI = 1186
PPC_INS_TWNG = 1187
PPC_INS_TWNGI = 1188
PPC_INS_TWNL = 1189
PPC_INS_TWNLI = 1190
PPC_INS_TWU = 1191
PPC_INS_TWUI = 1192
PPC_INS_VABSDUB = 1193
PPC_INS_VABSDUH = 1194
PPC_INS_VABSDUW = 1195
PPC_INS_VADDCUQ = 1196
PPC_INS_VADDCUW = 1197
PPC_INS_VADDECUQ = 1198
PPC_INS_VADDEUQM = 1199
PPC_INS_VADDFP = 1200
PPC_INS_VADDSBS = 1201
PPC_INS_VADDSHS = 1202
PPC_INS_VADDSWS = 1203
PPC_INS_VADDUBM = 1204
PPC_INS_VADDUBS = 1205
PPC_INS_VADDUDM = 1206
PPC_INS_VADDUHM = 1207
PPC_INS_VADDUHS = 1208
PPC_INS_VADDUQM = 1209
PPC_INS_VADDUWM = 1210
PPC_INS_VADDUWS = 1211
PPC_INS_VAND = 1212
PPC_INS_VANDC = 1213
PPC_INS_VAVGSB = 1214
PPC_INS_VAVGSH = 1215
PPC_INS_VAVGSW = 1216
PPC_INS_VAVGUB = 1217
PPC_INS_VAVGUH = 1218
PPC_INS_VAVGUW = 1219
PPC_INS_VBPERMD = 1220
PPC_INS_VBPERMQ = 1221
PPC_INS_VCFSX = 1222
PPC_INS_VCFUX = 1223
PPC_INS_VCIPHER = 1224
PPC_INS_VCIPHERLAST = 1225
PPC_INS_VCLZB = 1226
PPC_INS_VCLZD = 1227
PPC_INS_VCLZH = 1228
PPC_INS_VCLZLSBB = 1229
PPC_INS_VCLZW = 1230
PPC_INS_VCMPBFP = 1231
PPC_INS_VCMPEQFP = 1232
PPC_INS_VCMPEQUB = 1233
PPC_INS_VCMPEQUD = 1234
PPC_INS_VCMPEQUH = 1235
PPC_INS_VCMPEQUW = 1236
PPC_INS_VCMPGEFP = 1237
PPC_INS_VCMPGTFP = 1238
PPC_INS_VCMPGTSB = 1239
PPC_INS_VCMPGTSD = 1240
PPC_INS_VCMPGTSH = 1241
PPC_INS_VCMPGTSW = 1242
PPC_INS_VCMPGTUB = 1243
PPC_INS_VCMPGTUD = 1244
PPC_INS_VCMPGTUH = 1245
PPC_INS_VCMPGTUW = 1246
PPC_INS_VCMPNEB = 1247
PPC_INS_VCMPNEH = 1248
PPC_INS_VCMPNEW = 1249
PPC_INS_VCMPNEZB = 1250
PPC_INS_VCMPNEZH = 1251
PPC_INS_VCMPNEZW = 1252
PPC_INS_VCTSXS = 1253
PPC_INS_VCTUXS = 1254
PPC_INS_VCTZB = 1255
PPC_INS_VCTZD = 1256
PPC_INS_VCTZH = 1257
PPC_INS_VCTZLSBB = 1258
PPC_INS_VCTZW = 1259
PPC_INS_VEQV = 1260
PPC_INS_VEXPTEFP = 1261
PPC_INS_VEXTRACTD = 1262
PPC_INS_VEXTRACTUB = 1263
PPC_INS_VEXTRACTUH = 1264
PPC_INS_VEXTRACTUW = 1265
PPC_INS_VEXTSB2D = 1266
PPC_INS_VEXTSB2W = 1267
PPC_INS_VEXTSH2D = 1268
PPC_INS_VEXTSH2W = 1269
PPC_INS_VEXTSW2D = 1270
PPC_INS_VEXTUBLX = 1271
PPC_INS_VEXTUBRX = 1272
PPC_INS_VEXTUHLX = 1273
PPC_INS_VEXTUHRX = 1274
PPC_INS_VEXTUWLX = 1275
PPC_INS_VEXTUWRX = 1276
PPC_INS_VGBBD = 1277
PPC_INS_VINSERTB = 1278
PPC_INS_VINSERTD = 1279
PPC_INS_VINSERTH = 1280
PPC_INS_VINSERTW = 1281
PPC_INS_VLOGEFP = 1282
PPC_INS_VMADDFP = 1283
PPC_INS_VMAXFP = 1284
PPC_INS_VMAXSB = 1285
PPC_INS_VMAXSD = 1286
PPC_INS_VMAXSH = 1287
PPC_INS_VMAXSW = 1288
PPC_INS_VMAXUB = 1289
PPC_INS_VMAXUD = 1290
PPC_INS_VMAXUH = 1291
PPC_INS_VMAXUW = 1292
PPC_INS_VMHADDSHS = 1293
PPC_INS_VMHRADDSHS = 1294
PPC_INS_VMINFP = 1295
PPC_INS_VMINSB = 1296
PPC_INS_VMINSD = 1297
PPC_INS_VMINSH = 1298
PPC_INS_VMINSW = 1299
PPC_INS_VMINUB = 1300
PPC_INS_VMINUD = 1301
PPC_INS_VMINUH = 1302
PPC_INS_VMINUW = 1303
PPC_INS_VMLADDUHM = 1304
PPC_INS_VMR = 1305
PPC_INS_VMRGEW = 1306
PPC_INS_VMRGHB = 1307
PPC_INS_VMRGHH = 1308
PPC_INS_VMRGHW = 1309
PPC_INS_VMRGLB = 1310
PPC_INS_VMRGLH = 1311
PPC_INS_VMRGLW = 1312
PPC_INS_VMRGOW = 1313
PPC_INS_VMSUMMBM = 1314
PPC_INS_VMSUMSHM = 1315
PPC_INS_VMSUMSHS = 1316
PPC_INS_VMSUMUBM = 1317
PPC_INS_VMSUMUHM = 1318
PPC_INS_VMSUMUHS = 1319
PPC_INS_VMUL10CUQ = 1320
PPC_INS_VMUL10ECUQ = 1321
PPC_INS_VMUL10EUQ = 1322
PPC_INS_VMUL10UQ = 1323
PPC_INS_VMULESB = 1324
PPC_INS_VMULESH = 1325
PPC_INS_VMULESW = 1326
PPC_INS_VMULEUB = 1327
PPC_INS_VMULEUH = 1328
PPC_INS_VMULEUW = 1329
PPC_INS_VMULOSB = 1330
PPC_INS_VMULOSH = 1331
PPC_INS_VMULOSW = 1332
PPC_INS_VMULOUB = 1333
PPC_INS_VMULOUH = 1334
PPC_INS_VMULOUW = 1335
PPC_INS_VMULUWM = 1336
PPC_INS_VNAND = 1337
PPC_INS_VNCIPHER = 1338
PPC_INS_VNCIPHERLAST = 1339
PPC_INS_VNEGD = 1340
PPC_INS_VNEGW = 1341
PPC_INS_VNMSUBFP = 1342
PPC_INS_VNOR = 1343
PPC_INS_VNOT = 1344
PPC_INS_VOR = 1345
PPC_INS_VORC = 1346
PPC_INS_VPERM = 1347
PPC_INS_VPERMR = 1348
PPC_INS_VPERMXOR = 1349
PPC_INS_VPKPX = 1350
PPC_INS_VPKSDSS = 1351
PPC_INS_VPKSDUS = 1352
PPC_INS_VPKSHSS = 1353
PPC_INS_VPKSHUS = 1354
PPC_INS_VPKSWSS = 1355
PPC_INS_VPKSWUS = 1356
PPC_INS_VPKUDUM = 1357
PPC_INS_VPKUDUS = 1358
PPC_INS_VPKUHUM = 1359
PPC_INS_VPKUHUS = 1360
PPC_INS_VPKUWUM = 1361
PPC_INS_VPKUWUS = 1362
PPC_INS_VPMSUMB = 1363
PPC_INS_VPMSUMD = 1364
PPC_INS_VPMSUMH = 1365
PPC_INS_VPMSUMW = 1366
PPC_INS_VPOPCNTB = 1367
PPC_INS_VPOPCNTD = 1368
PPC_INS_VPOPCNTH = 1369
PPC_INS_VPOPCNTW = 1370
PPC_INS_VPRTYBD = 1371
PPC_INS_VPRTYBQ = 1372
PPC_INS_VPRTYBW = 1373
PPC_INS_VREFP = 1374
PPC_INS_VRFIM = 1375
PPC_INS_VRFIN = 1376
PPC_INS_VRFIP = 1377
PPC_INS_VRFIZ = 1378
PPC_INS_VRLB = 1379
PPC_INS_VRLD = 1380
PPC_INS_VRLDMI = 1381
PPC_INS_VRLDNM = 1382
PPC_INS_VRLH = 1383
PPC_INS_VRLW = 1384
PPC_INS_VRLWMI = 1385
PPC_INS_VRLWNM = 1386
PPC_INS_VRSQRTEFP = 1387
PPC_INS_VSBOX = 1388
PPC_INS_VSEL = 1389
PPC_INS_VSHASIGMAD = 1390
PPC_INS_VSHASIGMAW = 1391
PPC_INS_VSL = 1392
PPC_INS_VSLB = 1393
PPC_INS_VSLD = 1394
PPC_INS_VSLDOI = 1395
PPC_INS_VSLH = 1396
PPC_INS_VSLO = 1397
PPC_INS_VSLV = 1398
PPC_INS_VSLW = 1399
PPC_INS_VSPLTB = 1400
PPC_INS_VSPLTH = 1401
PPC_INS_VSPLTISB = 1402
PPC_INS_VSPLTISH = 1403
PPC_INS_VSPLTISW = 1404
PPC_INS_VSPLTW = 1405
PPC_INS_VSR = 1406
PPC_INS_VSRAB = 1407
PPC_INS_VSRAD = 1408
PPC_INS_VSRAH = 1409
PPC_INS_VSRAW = 1410
PPC_INS_VSRB = 1411
PPC_INS_VSRD = 1412
PPC_INS_VSRH = 1413
PPC_INS_VSRO = 1414
PPC_INS_VSRV = 1415
PPC_INS_VSRW = 1416
PPC_INS_VSUBCUQ = 1417
PPC_INS_VSUBCUW = 1418
PPC_INS_VSUBECUQ = 1419
PPC_INS_VSUBEUQM = 1420
PPC_INS_VSUBFP = 1421
PPC_INS_VSUBSBS = 1422
PPC_INS_VSUBSHS = 1423
PPC_INS_VSUBSWS = 1424
PPC_INS_VSUBUBM = 1425
PPC_INS_VSUBUBS = 1426
PPC_INS_VSUBUDM = 1427
PPC_INS_VSUBUHM = 1428
PPC_INS_VSUBUHS = 1429
PPC_INS_VSUBUQM = 1430
PPC_INS_VSUBUWM = 1431
PPC_INS_VSUBUWS = 1432
PPC_INS_VSUM2SWS = 1433
PPC_INS_VSUM4SBS = 1434
PPC_INS_VSUM4SHS = 1435
PPC_INS_VSUM4UBS = 1436
PPC_INS_VSUMSWS = 1437
PPC_INS_VUPKHPX = 1438
PPC_INS_VUPKHSB = 1439
PPC_INS_VUPKHSH = 1440
PPC_INS_VUPKHSW = 1441
PPC_INS_VUPKLPX = 1442
PPC_INS_VUPKLSB = 1443
PPC_INS_VUPKLSH = 1444
PPC_INS_VUPKLSW = 1445
PPC_INS_VXOR = 1446
PPC_INS_WAIT = 1447
PPC_INS_WAITIMPL = 1448
PPC_INS_WAITRSV = 1449
PPC_INS_WRTEE = 1450
PPC_INS_WRTEEI = 1451
PPC_INS_XNOP = 1452
PPC_INS_XOR = 1453
PPC_INS_XORI = 1454
PPC_INS_XORIS = 1455
PPC_INS_XSABSDP = 1456
PPC_INS_XSABSQP = 1457
PPC_INS_XSADDDP = 1458
PPC_INS_XSADDQP = 1459
PPC_INS_XSADDQPO = 1460
PPC_INS_XSADDSP = 1461
PPC_INS_XSCMPEQDP = 1462
PPC_INS_XSCMPEXPDP = 1463
PPC_INS_XSCMPEXPQP = 1464
PPC_INS_XSCMPGEDP = 1465
PPC_INS_XSCMPGTDP = 1466
PPC_INS_XSCMPODP = 1467
PPC_INS_XSCMPOQP = 1468
PPC_INS_XSCMPUDP = 1469
PPC_INS_XSCMPUQP = 1470
PPC_INS_XSCPSGNDP = 1471
PPC_INS_XSCPSGNQP = 1472
PPC_INS_XSCVDPHP = 1473
PPC_INS_XSCVDPQP = 1474
PPC_INS_XSCVDPSP = 1475
PPC_INS_XSCVDPSPN = 1476
PPC_INS_XSCVDPSXDS = 1477
PPC_INS_XSCVDPSXWS = 1478
PPC_INS_XSCVDPUXDS = 1479
PPC_INS_XSCVDPUXWS = 1480
PPC_INS_XSCVHPDP = 1481
PPC_INS_XSCVQPDP = 1482
PPC_INS_XSCVQPDPO = 1483
PPC_INS_XSCVQPSDZ = 1484
PPC_INS_XSCVQPSWZ = 1485
PPC_INS_XSCVQPUDZ = 1486
PPC_INS_XSCVQPUWZ = 1487
PPC_INS_XSCVSDQP = 1488
PPC_INS_XSCVSPDP = 1489
PPC_INS_XSCVSPDPN = 1490
PPC_INS_XSCVSXDDP = 1491
PPC_INS_XSCVSXDSP = 1492
PPC_INS_XSCVUDQP = 1493
PPC_INS_XSCVUXDDP = 1494
PPC_INS_XSCVUXDSP = 1495
PPC_INS_XSDIVDP = 1496
PPC_INS_XSDIVQP = 1497
PPC_INS_XSDIVQPO = 1498
PPC_INS_XSDIVSP = 1499
PPC_INS_XSIEXPDP = 1500
PPC_INS_XSIEXPQP = 1501
PPC_INS_XSMADDADP = 1502
PPC_INS_XSMADDASP = 1503
PPC_INS_XSMADDMDP = 1504
PPC_INS_XSMADDMSP = 1505
PPC_INS_XSMADDQP = 1506
PPC_INS_XSMADDQPO = 1507
PPC_INS_XSMAXCDP = 1508
PPC_INS_XSMAXDP = 1509
PPC_INS_XSMAXJDP = 1510
PPC_INS_XSMINCDP = 1511
PPC_INS_XSMINDP = 1512
PPC_INS_XSMINJDP = 1513
PPC_INS_XSMSUBADP = 1514
PPC_INS_XSMSUBASP = 1515
PPC_INS_XSMSUBMDP = 1516
PPC_INS_XSMSUBMSP = 1517
PPC_INS_XSMSUBQP = 1518
PPC_INS_XSMSUBQPO = 1519
PPC_INS_XSMULDP = 1520
PPC_INS_XSMULQP = 1521
PPC_INS_XSMULQPO = 1522
PPC_INS_XSMULSP = 1523
PPC_INS_XSNABSDP = 1524
PPC_INS_XSNABSQP = 1525
PPC_INS_XSNEGDP = 1526
PPC_INS_XSNEGQP = 1527
PPC_INS_XSNMADDADP = 1528
PPC_INS_XSNMADDASP = 1529
PPC_INS_XSNMADDMDP = 1530
PPC_INS_XSNMADDMSP = 1531
PPC_INS_XSNMADDQP = 1532
PPC_INS_XSNMADDQPO = 1533
PPC_INS_XSNMSUBADP = 1534
PPC_INS_XSNMSUBASP = 1535
PPC_INS_XSNMSUBMDP = 1536
PPC_INS_XSNMSUBMSP = 1537
PPC_INS_XSNMSUBQP = 1538
PPC_INS_XSNMSUBQPO = 1539
PPC_INS_XSRDPI = 1540
PPC_INS_XSRDPIC = 1541
PPC_INS_XSRDPIM = 1542
PPC_INS_XSRDPIP = 1543
PPC_INS_XSRDPIZ = 1544
PPC_INS_XSREDP = 1545
PPC_INS_XSRESP = 1546
PPC_INS_XSRQPI = 1547
PPC_INS_XSRQPIX = 1548
PPC_INS_XSRQPXP = 1549
PPC_INS_XSRSP = 1550
PPC_INS_XSRSQRTEDP = 1551
PPC_INS_XSRSQRTESP = 1552
PPC_INS_XSSQRTDP = 1553
PPC_INS_XSSQRTQP = 1554
PPC_INS_XSSQRTQPO = 1555
PPC_INS_XSSQRTSP = 1556
PPC_INS_XSSUBDP = 1557
PPC_INS_XSSUBQP = 1558
PPC_INS_XSSUBQPO = 1559
PPC_INS_XSSUBSP = 1560
PPC_INS_XSTDIVDP = 1561
PPC_INS_XSTSQRTDP = 1562
PPC_INS_XSTSTDCDP = 1563
PPC_INS_XSTSTDCQP = 1564
PPC_INS_XSTSTDCSP = 1565
PPC_INS_XSXEXPDP = 1566
PPC_INS_XSXEXPQP = 1567
PPC_INS_XSXSIGDP = 1568
PPC_INS_XSXSIGQP = 1569
PPC_INS_XVABSDP = 1570
PPC_INS_XVABSSP = 1571
PPC_INS_XVADDDP = 1572
PPC_INS_XVADDSP = 1573
PPC_INS_XVCMPEQDP = 1574
PPC_INS_XVCMPEQSP = 1575
PPC_INS_XVCMPGEDP = 1576
PPC_INS_XVCMPGESP = 1577
PPC_INS_XVCMPGTDP = 1578
PPC_INS_XVCMPGTSP = 1579
PPC_INS_XVCPSGNDP = 1580
PPC_INS_XVCPSGNSP = 1581
PPC_INS_XVCVDPSP = 1582
PPC_INS_XVCVDPSXDS = 1583
PPC_INS_XVCVDPSXWS = 1584
PPC_INS_XVCVDPUXDS = 1585
PPC_INS_XVCVDPUXWS = 1586
PPC_INS_XVCVHPSP = 1587
PPC_INS_XVCVSPDP = 1588
PPC_INS_XVCVSPHP = 1589
PPC_INS_XVCVSPSXDS = 1590
PPC_INS_XVCVSPSXWS = 1591
PPC_INS_XVCVSPUXDS = 1592
PPC_INS_XVCVSPUXWS = 1593
PPC_INS_XVCVSXDDP = 1594
PPC_INS_XVCVSXDSP = 1595
PPC_INS_XVCVSXWDP = 1596
PPC_INS_XVCVSXWSP = 1597
PPC_INS_XVCVUXDDP = 1598
PPC_INS_XVCVUXDSP = 1599
PPC_INS_XVCVUXWDP = 1600
PPC_INS_XVCVUXWSP = 1601
PPC_INS_XVDIVDP = 1602
PPC_INS_XVDIVSP = 1603
PPC_INS_XVIEXPDP = 1604
PPC_INS_XVIEXPSP = 1605
PPC_INS_XVMADDADP = 1606
PPC_INS_XVMADDASP = 1607
PPC_INS_XVMADDMDP = 1608
PPC_INS_XVMADDMSP = 1609
PPC_INS_XVMAXDP = 1610
PPC_INS_XVMAXSP = 1611
PPC_INS_XVMINDP = 1612
PPC_INS_XVMINSP = 1613
PPC_INS_XVMOVDP = 1614
PPC_INS_XVMOVSP = 1615
PPC_INS_XVMSUBADP = 1616
PPC_INS_XVMSUBASP = 1617
PPC_INS_XVMSUBMDP = 1618
PPC_INS_XVMSUBMSP = 1619
PPC_INS_XVMULDP = 1620
PPC_INS_XVMULSP = 1621
PPC_INS_XVNABSDP = 1622
PPC_INS_XVNABSSP = 1623
PPC_INS_XVNEGDP = 1624
PPC_INS_XVNEGSP = 1625
PPC_INS_XVNMADDADP = 1626
PPC_INS_XVNMADDASP = 1627
PPC_INS_XVNMADDMDP = 1628
PPC_INS_XVNMADDMSP = 1629
PPC_INS_XVNMSUBADP = 1630
PPC_INS_XVNMSUBASP = 1631
PPC_INS_XVNMSUBMDP = 1632
PPC_INS_XVNMSUBMSP = 1633
PPC_INS_XVRDPI = 1634
PPC_INS_XVRDPIC = 1635
PPC_INS_XVRDPIM = 1636
PPC_INS_XVRDPIP = 1637
PPC_INS_XVRDPIZ = 1638
PPC_INS_XVREDP = 1639
PPC_INS_XVRESP = 1640
PPC_INS_XVRSPI = 1641
PPC_INS_XVRSPIC = 1642
PPC_INS_XVRSPIM = 1643
PPC_INS_XVRSPIP = 1644
PPC_INS_XVRSPIZ = 1645
PPC_INS_XVRSQRTEDP = 1646
PPC_INS_XVRSQRTESP = 1647
PPC_INS_XVSQRTDP = 1648
PPC_INS_XVSQRTSP = 1649
PPC_INS_XVSUBDP = 1650
PPC_INS_XVSUBSP = 1651
PPC_INS_XVTDIVDP = 1652
PPC_INS_XVTDIVSP = 1653
PPC_INS_XVTSQRTDP = 1654
PPC_INS_XVTSQRTSP = 1655
PPC_INS_XVTSTDCDP = 1656
PPC_INS_XVTSTDCSP = 1657
PPC_INS_XVXEXPDP = 1658
PPC_INS_XVXEXPSP = 1659
PPC_INS_XVXSIGDP = 1660
PPC_INS_XVXSIGSP = 1661
PPC_INS_XXBRD = 1662
PPC_INS_XXBRH = 1663
PPC_INS_XXBRQ = 1664
PPC_INS_XXBRW = 1665
PPC_INS_XXEXTRACTUW = 1666
PPC_INS_XXINSERTW = 1667
PPC_INS_XXLAND = 1668
PPC_INS_XXLANDC = 1669
PPC_INS_XXLEQV = 1670
PPC_INS_XXLNAND = 1671
PPC_INS_XXLNOR = 1672
PPC_INS_XXLOR = 1673
PPC_INS_XXLORC = 1674
PPC_INS_XXLXOR = 1675
PPC_INS_XXMRGHD = 1676
PPC_INS_XXMRGHW = 1677
PPC_INS_XXMRGLD = 1678
PPC_INS_XXMRGLW = 1679
PPC_INS_XXPERM = 1680
PPC_INS_XXPERMDI = 1681
PPC_INS_XXPERMR = 1682
PPC_INS_XXSEL = 1683
PPC_INS_XXSLDWI = 1684
PPC_INS_XXSPLTD = 1685
PPC_INS_XXSPLTIB = 1686
PPC_INS_XXSPLTW = 1687
PPC_INS_XXSWAPD = 1688
PPC_INS_ENDING = 1689
PPC_GRP_INVALID = 0
PPC_GRP_JUMP = 1
PPC_GRP_ALTIVEC = 128
PPC_GRP_MODE32 = 129
PPC_GRP_MODE64 = 130
PPC_GRP_BOOKE = 131
PPC_GRP_NOTBOOKE = 132
PPC_GRP_SPE = 133
PPC_GRP_VSX = 134
PPC_GRP_E500 = 135
PPC_GRP_PPC4XX = 136
PPC_GRP_PPC6XX = 137
PPC_GRP_ICBT = 138
PPC_GRP_P8ALTIVEC = 139
PPC_GRP_P8VECTOR = 140
PPC_GRP_QPX = 141
PPC_GRP_ENDING = 142
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/ppc_const.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
ARM_SFT_INVALID = 0
ARM_SFT_ASR = 1
ARM_SFT_LSL = 2
ARM_SFT_LSR = 3
ARM_SFT_ROR = 4
ARM_SFT_RRX = 5
ARM_SFT_ASR_REG = 6
ARM_SFT_LSL_REG = 7
ARM_SFT_LSR_REG = 8
ARM_SFT_ROR_REG = 9
ARM_SFT_RRX_REG = 10
ARM_CC_INVALID = 0
ARM_CC_EQ = 1
ARM_CC_NE = 2
ARM_CC_HS = 3
ARM_CC_LO = 4
ARM_CC_MI = 5
ARM_CC_PL = 6
ARM_CC_VS = 7
ARM_CC_VC = 8
ARM_CC_HI = 9
ARM_CC_LS = 10
ARM_CC_GE = 11
ARM_CC_LT = 12
ARM_CC_GT = 13
ARM_CC_LE = 14
ARM_CC_AL = 15
ARM_SYSREG_INVALID = 0
ARM_SYSREG_SPSR_C = 1
ARM_SYSREG_SPSR_X = 2
ARM_SYSREG_SPSR_S = 4
ARM_SYSREG_SPSR_F = 8
ARM_SYSREG_CPSR_C = 16
ARM_SYSREG_CPSR_X = 32
ARM_SYSREG_CPSR_S = 64
ARM_SYSREG_CPSR_F = 128
ARM_SYSREG_APSR = 256
ARM_SYSREG_APSR_G = 257
ARM_SYSREG_APSR_NZCVQ = 258
ARM_SYSREG_APSR_NZCVQG = 259
ARM_SYSREG_IAPSR = 260
ARM_SYSREG_IAPSR_G = 261
ARM_SYSREG_IAPSR_NZCVQG = 262
ARM_SYSREG_IAPSR_NZCVQ = 263
ARM_SYSREG_EAPSR = 264
ARM_SYSREG_EAPSR_G = 265
ARM_SYSREG_EAPSR_NZCVQG = 266
ARM_SYSREG_EAPSR_NZCVQ = 267
ARM_SYSREG_XPSR = 268
ARM_SYSREG_XPSR_G = 269
ARM_SYSREG_XPSR_NZCVQG = 270
ARM_SYSREG_XPSR_NZCVQ = 271
ARM_SYSREG_IPSR = 272
ARM_SYSREG_EPSR = 273
ARM_SYSREG_IEPSR = 274
ARM_SYSREG_MSP = 275
ARM_SYSREG_PSP = 276
ARM_SYSREG_PRIMASK = 277
ARM_SYSREG_BASEPRI = 278
ARM_SYSREG_BASEPRI_MAX = 279
ARM_SYSREG_FAULTMASK = 280
ARM_SYSREG_CONTROL = 281
ARM_SYSREG_MSPLIM = 282
ARM_SYSREG_PSPLIM = 283
ARM_SYSREG_MSP_NS = 284
ARM_SYSREG_PSP_NS = 285
ARM_SYSREG_MSPLIM_NS = 286
ARM_SYSREG_PSPLIM_NS = 287
ARM_SYSREG_PRIMASK_NS = 288
ARM_SYSREG_BASEPRI_NS = 289
ARM_SYSREG_FAULTMASK_NS = 290
ARM_SYSREG_CONTROL_NS = 291
ARM_SYSREG_SP_NS = 292
ARM_SYSREG_R8_USR = 293
ARM_SYSREG_R9_USR = 294
ARM_SYSREG_R10_USR = 295
ARM_SYSREG_R11_USR = 296
ARM_SYSREG_R12_USR = 297
ARM_SYSREG_SP_USR = 298
ARM_SYSREG_LR_USR = 299
ARM_SYSREG_R8_FIQ = 300
ARM_SYSREG_R9_FIQ = 301
ARM_SYSREG_R10_FIQ = 302
ARM_SYSREG_R11_FIQ = 303
ARM_SYSREG_R12_FIQ = 304
ARM_SYSREG_SP_FIQ = 305
ARM_SYSREG_LR_FIQ = 306
ARM_SYSREG_LR_IRQ = 307
ARM_SYSREG_SP_IRQ = 308
ARM_SYSREG_LR_SVC = 309
ARM_SYSREG_SP_SVC = 310
ARM_SYSREG_LR_ABT = 311
ARM_SYSREG_SP_ABT = 312
ARM_SYSREG_LR_UND = 313
ARM_SYSREG_SP_UND = 314
ARM_SYSREG_LR_MON = 315
ARM_SYSREG_SP_MON = 316
ARM_SYSREG_ELR_HYP = 317
ARM_SYSREG_SP_HYP = 318
ARM_SYSREG_SPSR_FIQ = 319
ARM_SYSREG_SPSR_IRQ = 320
ARM_SYSREG_SPSR_SVC = 321
ARM_SYSREG_SPSR_ABT = 322
ARM_SYSREG_SPSR_UND = 323
ARM_SYSREG_SPSR_MON = 324
ARM_SYSREG_SPSR_HYP = 325
ARM_MB_INVALID = 0
ARM_MB_RESERVED_0 = 1
ARM_MB_OSHLD = 2
ARM_MB_OSHST = 3
ARM_MB_OSH = 4
ARM_MB_RESERVED_4 = 5
ARM_MB_NSHLD = 6
ARM_MB_NSHST = 7
ARM_MB_NSH = 8
ARM_MB_RESERVED_8 = 9
ARM_MB_ISHLD = 10
ARM_MB_ISHST = 11
ARM_MB_ISH = 12
ARM_MB_RESERVED_12 = 13
ARM_MB_LD = 14
ARM_MB_ST = 15
ARM_MB_SY = 16
ARM_OP_INVALID = 0
ARM_OP_REG = 1
ARM_OP_IMM = 2
ARM_OP_MEM = 3
ARM_OP_FP = 4
ARM_OP_CIMM = 64
ARM_OP_PIMM = 65
ARM_OP_SETEND = 66
ARM_OP_SYSREG = 67
ARM_SETEND_INVALID = 0
ARM_SETEND_BE = 1
ARM_SETEND_LE = 2
ARM_CPSMODE_INVALID = 0
ARM_CPSMODE_IE = 2
ARM_CPSMODE_ID = 3
ARM_CPSFLAG_INVALID = 0
ARM_CPSFLAG_F = 1
ARM_CPSFLAG_I = 2
ARM_CPSFLAG_A = 4
ARM_CPSFLAG_NONE = 16
ARM_VECTORDATA_INVALID = 0
ARM_VECTORDATA_I8 = 1
ARM_VECTORDATA_I16 = 2
ARM_VECTORDATA_I32 = 3
ARM_VECTORDATA_I64 = 4
ARM_VECTORDATA_S8 = 5
ARM_VECTORDATA_S16 = 6
ARM_VECTORDATA_S32 = 7
ARM_VECTORDATA_S64 = 8
ARM_VECTORDATA_U8 = 9
ARM_VECTORDATA_U16 = 10
ARM_VECTORDATA_U32 = 11
ARM_VECTORDATA_U64 = 12
ARM_VECTORDATA_P8 = 13
ARM_VECTORDATA_F16 = 14
ARM_VECTORDATA_F32 = 15
ARM_VECTORDATA_F64 = 16
ARM_VECTORDATA_F16F64 = 17
ARM_VECTORDATA_F64F16 = 18
ARM_VECTORDATA_F32F16 = 19
ARM_VECTORDATA_F16F32 = 20
ARM_VECTORDATA_F64F32 = 21
ARM_VECTORDATA_F32F64 = 22
ARM_VECTORDATA_S32F32 = 23
ARM_VECTORDATA_U32F32 = 24
ARM_VECTORDATA_F32S32 = 25
ARM_VECTORDATA_F32U32 = 26
ARM_VECTORDATA_F64S16 = 27
ARM_VECTORDATA_F32S16 = 28
ARM_VECTORDATA_F64S32 = 29
ARM_VECTORDATA_S16F64 = 30
ARM_VECTORDATA_S16F32 = 31
ARM_VECTORDATA_S32F64 = 32
ARM_VECTORDATA_U16F64 = 33
ARM_VECTORDATA_U16F32 = 34
ARM_VECTORDATA_U32F64 = 35
ARM_VECTORDATA_F64U16 = 36
ARM_VECTORDATA_F32U16 = 37
ARM_VECTORDATA_F64U32 = 38
ARM_VECTORDATA_F16U16 = 39
ARM_VECTORDATA_U16F16 = 40
ARM_VECTORDATA_F16U32 = 41
ARM_VECTORDATA_U32F16 = 42
ARM_REG_INVALID = 0
ARM_REG_APSR = 1
ARM_REG_APSR_NZCV = 2
ARM_REG_CPSR = 3
ARM_REG_FPEXC = 4
ARM_REG_FPINST = 5
ARM_REG_FPSCR = 6
ARM_REG_FPSCR_NZCV = 7
ARM_REG_FPSID = 8
ARM_REG_ITSTATE = 9
ARM_REG_LR = 10
ARM_REG_PC = 11
ARM_REG_SP = 12
ARM_REG_SPSR = 13
ARM_REG_D0 = 14
ARM_REG_D1 = 15
ARM_REG_D2 = 16
ARM_REG_D3 = 17
ARM_REG_D4 = 18
ARM_REG_D5 = 19
ARM_REG_D6 = 20
ARM_REG_D7 = 21
ARM_REG_D8 = 22
ARM_REG_D9 = 23
ARM_REG_D10 = 24
ARM_REG_D11 = 25
ARM_REG_D12 = 26
ARM_REG_D13 = 27
ARM_REG_D14 = 28
ARM_REG_D15 = 29
ARM_REG_D16 = 30
ARM_REG_D17 = 31
ARM_REG_D18 = 32
ARM_REG_D19 = 33
ARM_REG_D20 = 34
ARM_REG_D21 = 35
ARM_REG_D22 = 36
ARM_REG_D23 = 37
ARM_REG_D24 = 38
ARM_REG_D25 = 39
ARM_REG_D26 = 40
ARM_REG_D27 = 41
ARM_REG_D28 = 42
ARM_REG_D29 = 43
ARM_REG_D30 = 44
ARM_REG_D31 = 45
ARM_REG_FPINST2 = 46
ARM_REG_MVFR0 = 47
ARM_REG_MVFR1 = 48
ARM_REG_MVFR2 = 49
ARM_REG_Q0 = 50
ARM_REG_Q1 = 51
ARM_REG_Q2 = 52
ARM_REG_Q3 = 53
ARM_REG_Q4 = 54
ARM_REG_Q5 = 55
ARM_REG_Q6 = 56
ARM_REG_Q7 = 57
ARM_REG_Q8 = 58
ARM_REG_Q9 = 59
ARM_REG_Q10 = 60
ARM_REG_Q11 = 61
ARM_REG_Q12 = 62
ARM_REG_Q13 = 63
ARM_REG_Q14 = 64
ARM_REG_Q15 = 65
ARM_REG_R0 = 66
ARM_REG_R1 = 67
ARM_REG_R2 = 68
ARM_REG_R3 = 69
ARM_REG_R4 = 70
ARM_REG_R5 = 71
ARM_REG_R6 = 72
ARM_REG_R7 = 73
ARM_REG_R8 = 74
ARM_REG_R9 = 75
ARM_REG_R10 = 76
ARM_REG_R11 = 77
ARM_REG_R12 = 78
ARM_REG_S0 = 79
ARM_REG_S1 = 80
ARM_REG_S2 = 81
ARM_REG_S3 = 82
ARM_REG_S4 = 83
ARM_REG_S5 = 84
ARM_REG_S6 = 85
ARM_REG_S7 = 86
ARM_REG_S8 = 87
ARM_REG_S9 = 88
ARM_REG_S10 = 89
ARM_REG_S11 = 90
ARM_REG_S12 = 91
ARM_REG_S13 = 92
ARM_REG_S14 = 93
ARM_REG_S15 = 94
ARM_REG_S16 = 95
ARM_REG_S17 = 96
ARM_REG_S18 = 97
ARM_REG_S19 = 98
ARM_REG_S20 = 99
ARM_REG_S21 = 100
ARM_REG_S22 = 101
ARM_REG_S23 = 102
ARM_REG_S24 = 103
ARM_REG_S25 = 104
ARM_REG_S26 = 105
ARM_REG_S27 = 106
ARM_REG_S28 = 107
ARM_REG_S29 = 108
ARM_REG_S30 = 109
ARM_REG_S31 = 110
ARM_REG_ENDING = 111
ARM_REG_R13 = ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC
ARM_REG_SB = ARM_REG_R9
ARM_REG_SL = ARM_REG_R10
ARM_REG_FP = ARM_REG_R11
ARM_REG_IP = ARM_REG_R12
ARM_INS_INVALID = 0
ARM_INS_ADC = 1
ARM_INS_ADD = 2
ARM_INS_ADDW = 3
ARM_INS_ADR = 4
ARM_INS_AESD = 5
ARM_INS_AESE = 6
ARM_INS_AESIMC = 7
ARM_INS_AESMC = 8
ARM_INS_AND = 9
ARM_INS_ASR = 10
ARM_INS_B = 11
ARM_INS_BFC = 12
ARM_INS_BFI = 13
ARM_INS_BIC = 14
ARM_INS_BKPT = 15
ARM_INS_BL = 16
ARM_INS_BLX = 17
ARM_INS_BLXNS = 18
ARM_INS_BX = 19
ARM_INS_BXJ = 20
ARM_INS_BXNS = 21
ARM_INS_CBNZ = 22
ARM_INS_CBZ = 23
ARM_INS_CDP = 24
ARM_INS_CDP2 = 25
ARM_INS_CLREX = 26
ARM_INS_CLZ = 27
ARM_INS_CMN = 28
ARM_INS_CMP = 29
ARM_INS_CPS = 30
ARM_INS_CRC32B = 31
ARM_INS_CRC32CB = 32
ARM_INS_CRC32CH = 33
ARM_INS_CRC32CW = 34
ARM_INS_CRC32H = 35
ARM_INS_CRC32W = 36
ARM_INS_CSDB = 37
ARM_INS_DBG = 38
ARM_INS_DCPS1 = 39
ARM_INS_DCPS2 = 40
ARM_INS_DCPS3 = 41
ARM_INS_DFB = 42
ARM_INS_DMB = 43
ARM_INS_DSB = 44
ARM_INS_EOR = 45
ARM_INS_ERET = 46
ARM_INS_ESB = 47
ARM_INS_FADDD = 48
ARM_INS_FADDS = 49
ARM_INS_FCMPZD = 50
ARM_INS_FCMPZS = 51
ARM_INS_FCONSTD = 52
ARM_INS_FCONSTS = 53
ARM_INS_FLDMDBX = 54
ARM_INS_FLDMIAX = 55
ARM_INS_FMDHR = 56
ARM_INS_FMDLR = 57
ARM_INS_FMSTAT = 58
ARM_INS_FSTMDBX = 59
ARM_INS_FSTMIAX = 60
ARM_INS_FSUBD = 61
ARM_INS_FSUBS = 62
ARM_INS_HINT = 63
ARM_INS_HLT = 64
ARM_INS_HVC = 65
ARM_INS_ISB = 66
ARM_INS_IT = 67
ARM_INS_LDA = 68
ARM_INS_LDAB = 69
ARM_INS_LDAEX = 70
ARM_INS_LDAEXB = 71
ARM_INS_LDAEXD = 72
ARM_INS_LDAEXH = 73
ARM_INS_LDAH = 74
ARM_INS_LDC = 75
ARM_INS_LDC2 = 76
ARM_INS_LDC2L = 77
ARM_INS_LDCL = 78
ARM_INS_LDM = 79
ARM_INS_LDMDA = 80
ARM_INS_LDMDB = 81
ARM_INS_LDMIB = 82
ARM_INS_LDR = 83
ARM_INS_LDRB = 84
ARM_INS_LDRBT = 85
ARM_INS_LDRD = 86
ARM_INS_LDREX = 87
ARM_INS_LDREXB = 88
ARM_INS_LDREXD = 89
ARM_INS_LDREXH = 90
ARM_INS_LDRH = 91
ARM_INS_LDRHT = 92
ARM_INS_LDRSB = 93
ARM_INS_LDRSBT = 94
ARM_INS_LDRSH = 95
ARM_INS_LDRSHT = 96
ARM_INS_LDRT = 97
ARM_INS_LSL = 98
ARM_INS_LSR = 99
ARM_INS_MCR = 100
ARM_INS_MCR2 = 101
ARM_INS_MCRR = 102
ARM_INS_MCRR2 = 103
ARM_INS_MLA = 104
ARM_INS_MLS = 105
ARM_INS_MOV = 106
ARM_INS_MOVS = 107
ARM_INS_MOVT = 108
ARM_INS_MOVW = 109
ARM_INS_MRC = 110
ARM_INS_MRC2 = 111
ARM_INS_MRRC = 112
ARM_INS_MRRC2 = 113
ARM_INS_MRS = 114
ARM_INS_MSR = 115
ARM_INS_MUL = 116
ARM_INS_MVN = 117
ARM_INS_NEG = 118
ARM_INS_NOP = 119
ARM_INS_ORN = 120
ARM_INS_ORR = 121
ARM_INS_PKHBT = 122
ARM_INS_PKHTB = 123
ARM_INS_PLD = 124
ARM_INS_PLDW = 125
ARM_INS_PLI = 126
ARM_INS_POP = 127
ARM_INS_PUSH = 128
ARM_INS_QADD = 129
ARM_INS_QADD16 = 130
ARM_INS_QADD8 = 131
ARM_INS_QASX = 132
ARM_INS_QDADD = 133
ARM_INS_QDSUB = 134
ARM_INS_QSAX = 135
ARM_INS_QSUB = 136
ARM_INS_QSUB16 = 137
ARM_INS_QSUB8 = 138
ARM_INS_RBIT = 139
ARM_INS_REV = 140
ARM_INS_REV16 = 141
ARM_INS_REVSH = 142
ARM_INS_RFEDA = 143
ARM_INS_RFEDB = 144
ARM_INS_RFEIA = 145
ARM_INS_RFEIB = 146
ARM_INS_ROR = 147
ARM_INS_RRX = 148
ARM_INS_RSB = 149
ARM_INS_RSC = 150
ARM_INS_SADD16 = 151
ARM_INS_SADD8 = 152
ARM_INS_SASX = 153
ARM_INS_SBC = 154
ARM_INS_SBFX = 155
ARM_INS_SDIV = 156
ARM_INS_SEL = 157
ARM_INS_SETEND = 158
ARM_INS_SETPAN = 159
ARM_INS_SEV = 160
ARM_INS_SEVL = 161
ARM_INS_SG = 162
ARM_INS_SHA1C = 163
ARM_INS_SHA1H = 164
ARM_INS_SHA1M = 165
ARM_INS_SHA1P = 166
ARM_INS_SHA1SU0 = 167
ARM_INS_SHA1SU1 = 168
ARM_INS_SHA256H = 169
ARM_INS_SHA256H2 = 170
ARM_INS_SHA256SU0 = 171
ARM_INS_SHA256SU1 = 172
ARM_INS_SHADD16 = 173
ARM_INS_SHADD8 = 174
ARM_INS_SHASX = 175
ARM_INS_SHSAX = 176
ARM_INS_SHSUB16 = 177
ARM_INS_SHSUB8 = 178
ARM_INS_SMC = 179
ARM_INS_SMLABB = 180
ARM_INS_SMLABT = 181
ARM_INS_SMLAD = 182
ARM_INS_SMLADX = 183
ARM_INS_SMLAL = 184
ARM_INS_SMLALBB = 185
ARM_INS_SMLALBT = 186
ARM_INS_SMLALD = 187
ARM_INS_SMLALDX = 188
ARM_INS_SMLALTB = 189
ARM_INS_SMLALTT = 190
ARM_INS_SMLATB = 191
ARM_INS_SMLATT = 192
ARM_INS_SMLAWB = 193
ARM_INS_SMLAWT = 194
ARM_INS_SMLSD = 195
ARM_INS_SMLSDX = 196
ARM_INS_SMLSLD = 197
ARM_INS_SMLSLDX = 198
ARM_INS_SMMLA = 199
ARM_INS_SMMLAR = 200
ARM_INS_SMMLS = 201
ARM_INS_SMMLSR = 202
ARM_INS_SMMUL = 203
ARM_INS_SMMULR = 204
ARM_INS_SMUAD = 205
ARM_INS_SMUADX = 206
ARM_INS_SMULBB = 207
ARM_INS_SMULBT = 208
ARM_INS_SMULL = 209
ARM_INS_SMULTB = 210
ARM_INS_SMULTT = 211
ARM_INS_SMULWB = 212
ARM_INS_SMULWT = 213
ARM_INS_SMUSD = 214
ARM_INS_SMUSDX = 215
ARM_INS_SRSDA = 216
ARM_INS_SRSDB = 217
ARM_INS_SRSIA = 218
ARM_INS_SRSIB = 219
ARM_INS_SSAT = 220
ARM_INS_SSAT16 = 221
ARM_INS_SSAX = 222
ARM_INS_SSUB16 = 223
ARM_INS_SSUB8 = 224
ARM_INS_STC = 225
ARM_INS_STC2 = 226
ARM_INS_STC2L = 227
ARM_INS_STCL = 228
ARM_INS_STL = 229
ARM_INS_STLB = 230
ARM_INS_STLEX = 231
ARM_INS_STLEXB = 232
ARM_INS_STLEXD = 233
ARM_INS_STLEXH = 234
ARM_INS_STLH = 235
ARM_INS_STM = 236
ARM_INS_STMDA = 237
ARM_INS_STMDB = 238
ARM_INS_STMIB = 239
ARM_INS_STR = 240
ARM_INS_STRB = 241
ARM_INS_STRBT = 242
ARM_INS_STRD = 243
ARM_INS_STREX = 244
ARM_INS_STREXB = 245
ARM_INS_STREXD = 246
ARM_INS_STREXH = 247
ARM_INS_STRH = 248
ARM_INS_STRHT = 249
ARM_INS_STRT = 250
ARM_INS_SUB = 251
ARM_INS_SUBS = 252
ARM_INS_SUBW = 253
ARM_INS_SVC = 254
ARM_INS_SWP = 255
ARM_INS_SWPB = 256
ARM_INS_SXTAB = 257
ARM_INS_SXTAB16 = 258
ARM_INS_SXTAH = 259
ARM_INS_SXTB = 260
ARM_INS_SXTB16 = 261
ARM_INS_SXTH = 262
ARM_INS_TBB = 263
ARM_INS_TBH = 264
ARM_INS_TEQ = 265
ARM_INS_TRAP = 266
ARM_INS_TSB = 267
ARM_INS_TST = 268
ARM_INS_TT = 269
ARM_INS_TTA = 270
ARM_INS_TTAT = 271
ARM_INS_TTT = 272
ARM_INS_UADD16 = 273
ARM_INS_UADD8 = 274
ARM_INS_UASX = 275
ARM_INS_UBFX = 276
ARM_INS_UDF = 277
ARM_INS_UDIV = 278
ARM_INS_UHADD16 = 279
ARM_INS_UHADD8 = 280
ARM_INS_UHASX = 281
ARM_INS_UHSAX = 282
ARM_INS_UHSUB16 = 283
ARM_INS_UHSUB8 = 284
ARM_INS_UMAAL = 285
ARM_INS_UMLAL = 286
ARM_INS_UMULL = 287
ARM_INS_UQADD16 = 288
ARM_INS_UQADD8 = 289
ARM_INS_UQASX = 290
ARM_INS_UQSAX = 291
ARM_INS_UQSUB16 = 292
ARM_INS_UQSUB8 = 293
ARM_INS_USAD8 = 294
ARM_INS_USADA8 = 295
ARM_INS_USAT = 296
ARM_INS_USAT16 = 297
ARM_INS_USAX = 298
ARM_INS_USUB16 = 299
ARM_INS_USUB8 = 300
ARM_INS_UXTAB = 301
ARM_INS_UXTAB16 = 302
ARM_INS_UXTAH = 303
ARM_INS_UXTB = 304
ARM_INS_UXTB16 = 305
ARM_INS_UXTH = 306
ARM_INS_VABA = 307
ARM_INS_VABAL = 308
ARM_INS_VABD = 309
ARM_INS_VABDL = 310
ARM_INS_VABS = 311
ARM_INS_VACGE = 312
ARM_INS_VACGT = 313
ARM_INS_VACLE = 314
ARM_INS_VACLT = 315
ARM_INS_VADD = 316
ARM_INS_VADDHN = 317
ARM_INS_VADDL = 318
ARM_INS_VADDW = 319
ARM_INS_VAND = 320
ARM_INS_VBIC = 321
ARM_INS_VBIF = 322
ARM_INS_VBIT = 323
ARM_INS_VBSL = 324
ARM_INS_VCADD = 325
ARM_INS_VCEQ = 326
ARM_INS_VCGE = 327
ARM_INS_VCGT = 328
ARM_INS_VCLE = 329
ARM_INS_VCLS = 330
ARM_INS_VCLT = 331
ARM_INS_VCLZ = 332
ARM_INS_VCMLA = 333
ARM_INS_VCMP = 334
ARM_INS_VCMPE = 335
ARM_INS_VCNT = 336
ARM_INS_VCVT = 337
ARM_INS_VCVTA = 338
ARM_INS_VCVTB = 339
ARM_INS_VCVTM = 340
ARM_INS_VCVTN = 341
ARM_INS_VCVTP = 342
ARM_INS_VCVTR = 343
ARM_INS_VCVTT = 344
ARM_INS_VDIV = 345
ARM_INS_VDUP = 346
ARM_INS_VEOR = 347
ARM_INS_VEXT = 348
ARM_INS_VFMA = 349
ARM_INS_VFMS = 350
ARM_INS_VFNMA = 351
ARM_INS_VFNMS = 352
ARM_INS_VHADD = 353
ARM_INS_VHSUB = 354
ARM_INS_VINS = 355
ARM_INS_VJCVT = 356
ARM_INS_VLD1 = 357
ARM_INS_VLD2 = 358
ARM_INS_VLD3 = 359
ARM_INS_VLD4 = 360
ARM_INS_VLDMDB = 361
ARM_INS_VLDMIA = 362
ARM_INS_VLDR = 363
ARM_INS_VLLDM = 364
ARM_INS_VLSTM = 365
ARM_INS_VMAX = 366
ARM_INS_VMAXNM = 367
ARM_INS_VMIN = 368
ARM_INS_VMINNM = 369
ARM_INS_VMLA = 370
ARM_INS_VMLAL = 371
ARM_INS_VMLS = 372
ARM_INS_VMLSL = 373
ARM_INS_VMOV = 374
ARM_INS_VMOVL = 375
ARM_INS_VMOVN = 376
ARM_INS_VMOVX = 377
ARM_INS_VMRS = 378
ARM_INS_VMSR = 379
ARM_INS_VMUL = 380
ARM_INS_VMULL = 381
ARM_INS_VMVN = 382
ARM_INS_VNEG = 383
ARM_INS_VNMLA = 384
ARM_INS_VNMLS = 385
ARM_INS_VNMUL = 386
ARM_INS_VORN = 387
ARM_INS_VORR = 388
ARM_INS_VPADAL = 389
ARM_INS_VPADD = 390
ARM_INS_VPADDL = 391
ARM_INS_VPMAX = 392
ARM_INS_VPMIN = 393
ARM_INS_VPOP = 394
ARM_INS_VPUSH = 395
ARM_INS_VQABS = 396
ARM_INS_VQADD = 397
ARM_INS_VQDMLAL = 398
ARM_INS_VQDMLSL = 399
ARM_INS_VQDMULH = 400
ARM_INS_VQDMULL = 401
ARM_INS_VQMOVN = 402
ARM_INS_VQMOVUN = 403
ARM_INS_VQNEG = 404
ARM_INS_VQRDMLAH = 405
ARM_INS_VQRDMLSH = 406
ARM_INS_VQRDMULH = 407
ARM_INS_VQRSHL = 408
ARM_INS_VQRSHRN = 409
ARM_INS_VQRSHRUN = 410
ARM_INS_VQSHL = 411
ARM_INS_VQSHLU = 412
ARM_INS_VQSHRN = 413
ARM_INS_VQSHRUN = 414
ARM_INS_VQSUB = 415
ARM_INS_VRADDHN = 416
ARM_INS_VRECPE = 417
ARM_INS_VRECPS = 418
ARM_INS_VREV16 = 419
ARM_INS_VREV32 = 420
ARM_INS_VREV64 = 421
ARM_INS_VRHADD = 422
ARM_INS_VRINTA = 423
ARM_INS_VRINTM = 424
ARM_INS_VRINTN = 425
ARM_INS_VRINTP = 426
ARM_INS_VRINTR = 427
ARM_INS_VRINTX = 428
ARM_INS_VRINTZ = 429
ARM_INS_VRSHL = 430
ARM_INS_VRSHR = 431
ARM_INS_VRSHRN = 432
ARM_INS_VRSQRTE = 433
ARM_INS_VRSQRTS = 434
ARM_INS_VRSRA = 435
ARM_INS_VRSUBHN = 436
ARM_INS_VSDOT = 437
ARM_INS_VSELEQ = 438
ARM_INS_VSELGE = 439
ARM_INS_VSELGT = 440
ARM_INS_VSELVS = 441
ARM_INS_VSHL = 442
ARM_INS_VSHLL = 443
ARM_INS_VSHR = 444
ARM_INS_VSHRN = 445
ARM_INS_VSLI = 446
ARM_INS_VSQRT = 447
ARM_INS_VSRA = 448
ARM_INS_VSRI = 449
ARM_INS_VST1 = 450
ARM_INS_VST2 = 451
ARM_INS_VST3 = 452
ARM_INS_VST4 = 453
ARM_INS_VSTMDB = 454
ARM_INS_VSTMIA = 455
ARM_INS_VSTR = 456
ARM_INS_VSUB = 457
ARM_INS_VSUBHN = 458
ARM_INS_VSUBL = 459
ARM_INS_VSUBW = 460
ARM_INS_VSWP = 461
ARM_INS_VTBL = 462
ARM_INS_VTBX = 463
ARM_INS_VTRN = 464
ARM_INS_VTST = 465
ARM_INS_VUDOT = 466
ARM_INS_VUZP = 467
ARM_INS_VZIP = 468
ARM_INS_WFE = 469
ARM_INS_WFI = 470
ARM_INS_YIELD = 471
ARM_INS_ENDING = 472
ARM_GRP_INVALID = 0
ARM_GRP_JUMP = 1
ARM_GRP_CALL = 2
ARM_GRP_INT = 4
ARM_GRP_PRIVILEGE = 6
ARM_GRP_BRANCH_RELATIVE = 7
ARM_GRP_CRYPTO = 128
ARM_GRP_DATABARRIER = 129
ARM_GRP_DIVIDE = 130
ARM_GRP_FPARMV8 = 131
ARM_GRP_MULTPRO = 132
ARM_GRP_NEON = 133
ARM_GRP_T2EXTRACTPACK = 134
ARM_GRP_THUMB2DSP = 135
ARM_GRP_TRUSTZONE = 136
ARM_GRP_V4T = 137
ARM_GRP_V5T = 138
ARM_GRP_V5TE = 139
ARM_GRP_V6 = 140
ARM_GRP_V6T2 = 141
ARM_GRP_V7 = 142
ARM_GRP_V8 = 143
ARM_GRP_VFP2 = 144
ARM_GRP_VFP3 = 145
ARM_GRP_VFP4 = 146
ARM_GRP_ARM = 147
ARM_GRP_MCLASS = 148
ARM_GRP_NOTMCLASS = 149
ARM_GRP_THUMB = 150
ARM_GRP_THUMB1ONLY = 151
ARM_GRP_THUMB2 = 152
ARM_GRP_PREV8 = 153
ARM_GRP_FPVMLX = 154
ARM_GRP_MULOPS = 155
ARM_GRP_CRC = 156
ARM_GRP_DPVFP = 157
ARM_GRP_V6M = 158
ARM_GRP_VIRTUALIZATION = 159
ARM_GRP_ENDING = 160
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/arm_const.py
|
# Capstone Python bindings, by Fotis Loukos <me@fotisl.com>
import ctypes, copy
from .tms320c64x_const import *
# define the API
class TMS320C64xOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_int),
('disp', ctypes.c_int),
('unit', ctypes.c_int),
('scaled', ctypes.c_int),
('disptype', ctypes.c_int),
('direction', ctypes.c_int),
('modify', ctypes.c_int),
)
class TMS320C64xOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int32),
('mem', TMS320C64xOpMem),
)
class TMS320C64xCondition(ctypes.Structure):
_fields_ = (
('reg', ctypes.c_uint),
('zero', ctypes.c_uint),
)
class TMS320C64xFunctionalUnit(ctypes.Structure):
_fields_ = (
('unit', ctypes.c_uint),
('side', ctypes.c_uint),
('crosspath', ctypes.c_uint),
)
class TMS320C64xOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', TMS320C64xOpValue),
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
@property
def mem(self):
return self.value.mem
class CsTMS320C64x(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', TMS320C64xOp * 8),
('condition', TMS320C64xCondition),
('funit', TMS320C64xFunctionalUnit),
('parallel', ctypes.c_uint),
)
def get_arch_info(a):
return (a.condition, a.funit, a.parallel, copy.deepcopy(a.operands[:a.op_count]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/tms320c64x.py
|
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py]
EVM_INS_STOP = 0
EVM_INS_ADD = 1
EVM_INS_MUL = 2
EVM_INS_SUB = 3
EVM_INS_DIV = 4
EVM_INS_SDIV = 5
EVM_INS_MOD = 6
EVM_INS_SMOD = 7
EVM_INS_ADDMOD = 8
EVM_INS_MULMOD = 9
EVM_INS_EXP = 10
EVM_INS_SIGNEXTEND = 11
EVM_INS_LT = 16
EVM_INS_GT = 17
EVM_INS_SLT = 18
EVM_INS_SGT = 19
EVM_INS_EQ = 20
EVM_INS_ISZERO = 21
EVM_INS_AND = 22
EVM_INS_OR = 23
EVM_INS_XOR = 24
EVM_INS_NOT = 25
EVM_INS_BYTE = 26
EVM_INS_SHA3 = 32
EVM_INS_ADDRESS = 48
EVM_INS_BALANCE = 49
EVM_INS_ORIGIN = 50
EVM_INS_CALLER = 51
EVM_INS_CALLVALUE = 52
EVM_INS_CALLDATALOAD = 53
EVM_INS_CALLDATASIZE = 54
EVM_INS_CALLDATACOPY = 55
EVM_INS_CODESIZE = 56
EVM_INS_CODECOPY = 57
EVM_INS_GASPRICE = 58
EVM_INS_EXTCODESIZE = 59
EVM_INS_EXTCODECOPY = 60
EVM_INS_RETURNDATASIZE = 61
EVM_INS_RETURNDATACOPY = 62
EVM_INS_BLOCKHASH = 64
EVM_INS_COINBASE = 65
EVM_INS_TIMESTAMP = 66
EVM_INS_NUMBER = 67
EVM_INS_DIFFICULTY = 68
EVM_INS_GASLIMIT = 69
EVM_INS_POP = 80
EVM_INS_MLOAD = 81
EVM_INS_MSTORE = 82
EVM_INS_MSTORE8 = 83
EVM_INS_SLOAD = 84
EVM_INS_SSTORE = 85
EVM_INS_JUMP = 86
EVM_INS_JUMPI = 87
EVM_INS_PC = 88
EVM_INS_MSIZE = 89
EVM_INS_GAS = 90
EVM_INS_JUMPDEST = 91
EVM_INS_PUSH1 = 96
EVM_INS_PUSH2 = 97
EVM_INS_PUSH3 = 98
EVM_INS_PUSH4 = 99
EVM_INS_PUSH5 = 100
EVM_INS_PUSH6 = 101
EVM_INS_PUSH7 = 102
EVM_INS_PUSH8 = 103
EVM_INS_PUSH9 = 104
EVM_INS_PUSH10 = 105
EVM_INS_PUSH11 = 106
EVM_INS_PUSH12 = 107
EVM_INS_PUSH13 = 108
EVM_INS_PUSH14 = 109
EVM_INS_PUSH15 = 110
EVM_INS_PUSH16 = 111
EVM_INS_PUSH17 = 112
EVM_INS_PUSH18 = 113
EVM_INS_PUSH19 = 114
EVM_INS_PUSH20 = 115
EVM_INS_PUSH21 = 116
EVM_INS_PUSH22 = 117
EVM_INS_PUSH23 = 118
EVM_INS_PUSH24 = 119
EVM_INS_PUSH25 = 120
EVM_INS_PUSH26 = 121
EVM_INS_PUSH27 = 122
EVM_INS_PUSH28 = 123
EVM_INS_PUSH29 = 124
EVM_INS_PUSH30 = 125
EVM_INS_PUSH31 = 126
EVM_INS_PUSH32 = 127
EVM_INS_DUP1 = 128
EVM_INS_DUP2 = 129
EVM_INS_DUP3 = 130
EVM_INS_DUP4 = 131
EVM_INS_DUP5 = 132
EVM_INS_DUP6 = 133
EVM_INS_DUP7 = 134
EVM_INS_DUP8 = 135
EVM_INS_DUP9 = 136
EVM_INS_DUP10 = 137
EVM_INS_DUP11 = 138
EVM_INS_DUP12 = 139
EVM_INS_DUP13 = 140
EVM_INS_DUP14 = 141
EVM_INS_DUP15 = 142
EVM_INS_DUP16 = 143
EVM_INS_SWAP1 = 144
EVM_INS_SWAP2 = 145
EVM_INS_SWAP3 = 146
EVM_INS_SWAP4 = 147
EVM_INS_SWAP5 = 148
EVM_INS_SWAP6 = 149
EVM_INS_SWAP7 = 150
EVM_INS_SWAP8 = 151
EVM_INS_SWAP9 = 152
EVM_INS_SWAP10 = 153
EVM_INS_SWAP11 = 154
EVM_INS_SWAP12 = 155
EVM_INS_SWAP13 = 156
EVM_INS_SWAP14 = 157
EVM_INS_SWAP15 = 158
EVM_INS_SWAP16 = 159
EVM_INS_LOG0 = 160
EVM_INS_LOG1 = 161
EVM_INS_LOG2 = 162
EVM_INS_LOG3 = 163
EVM_INS_LOG4 = 164
EVM_INS_CREATE = 240
EVM_INS_CALL = 241
EVM_INS_CALLCODE = 242
EVM_INS_RETURN = 243
EVM_INS_DELEGATECALL = 244
EVM_INS_CALLBLACKBOX = 245
EVM_INS_STATICCALL = 250
EVM_INS_REVERT = 253
EVM_INS_SUICIDE = 255
EVM_INS_INVALID = 512
EVM_INS_ENDING = 513
EVM_GRP_INVALID = 0
EVM_GRP_JUMP = 1
EVM_GRP_MATH = 8
EVM_GRP_STACK_WRITE = 9
EVM_GRP_STACK_READ = 10
EVM_GRP_MEM_WRITE = 11
EVM_GRP_MEM_READ = 12
EVM_GRP_STORE_WRITE = 13
EVM_GRP_STORE_READ = 14
EVM_GRP_HALT = 15
EVM_GRP_ENDING = 16
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/capstone/bindings/python/capstone/evm_const.py
|
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# pylibfdt - Tests for Flat Device Tree manipulation in Python
# Copyright (C) 2017 Google, Inc.
# Written by Simon Glass <sjg@chromium.org>
#
import struct
import sys
import types
import unittest
sys.path.insert(0, '../pylibfdt')
import libfdt
from libfdt import Fdt, FdtSw, FdtException, QUIET_NOTFOUND, QUIET_ALL
TEST_ADDR_1H = 0xdeadbeef
TEST_ADDR_1L = 0x00000000
TEST_ADDR_1 = (TEST_ADDR_1H << 32) | TEST_ADDR_1L
TEST_ADDR_1 = 0x8000000000000000
TEST_SIZE_1H = 0x00000000
TEST_SIZE_1L = 0x00100000
TEST_SIZE_1 = (TEST_SIZE_1H << 32) | TEST_SIZE_1L
TEST_ADDR_2H = 0
TEST_ADDR_2L = 123456789
TEST_ADDR_2 = (TEST_ADDR_2H << 32) | TEST_ADDR_2L
TEST_SIZE_2H = 0
TEST_SIZE_2L = 0o10000
TEST_SIZE_2 = (TEST_SIZE_2H << 32) | TEST_SIZE_2L
TEST_VALUE_1 = 0xdeadbeef
TEST_VALUE_2 = 123456789
TEST_VALUE64_1H = 0xdeadbeef
TEST_VALUE64_1L = 0x01abcdef
TEST_VALUE64_1 = (TEST_VALUE64_1H << 32) | TEST_VALUE64_1L
PHANDLE_1 = 0x2000
PHANDLE_2 = 0x2001
TEST_BYTES_1 = b'hello world'
TEST_STRING_1 = 'hello world'
TEST_STRING_2 = 'hi world'
TEST_STRING_3 = u'unicode \u01d3'
def get_err(err_code):
"""Convert an error code into an error message
Args:
err_code: Error code value (FDT_ERR_...)
Returns:
String error code
"""
return 'pylibfdt error %d: %s' % (-err_code, libfdt.strerror(-err_code))
def _ReadFdt(fname):
"""Read a device tree file into an Fdt object, ready for use
Args:
fname: Filename to read from
Returns:
Fdt bytearray suitable for passing to libfdt functions
"""
with open(fname, mode='rb') as f:
return libfdt.Fdt(f.read())
class PyLibfdtBasicTests(unittest.TestCase):
"""Test class for basic pylibfdt access functions
Properties:
fdt: Device tree file used for testing
"""
def setUp(self):
"""Read in the device tree we use for testing"""
self.fdt = _ReadFdt('test_tree1.dtb')
self.fdt2 = _ReadFdt('test_props.dtb')
self.fdt3 = _ReadFdt('aliases.dtb')
def GetPropList(self, node_path):
"""Read a list of properties from a node
Args:
node_path: Full path to node, e.g. '/subnode@1/subsubnode'
Returns:
List of property names for that node, e.g. ['compatible', 'reg']
"""
prop_list = []
node = self.fdt.path_offset(node_path)
poffset = self.fdt.first_property_offset(node, QUIET_NOTFOUND)
while poffset > 0:
prop = self.fdt.get_property_by_offset(poffset)
prop_list.append(prop.name)
poffset = self.fdt.next_property_offset(poffset, QUIET_NOTFOUND)
return prop_list
def GetSubnodes(self, node_path):
"""Read a list of subnodes from a node
Args:
node_path: Full path to node, e.g. '/subnode@1/subsubnode'
Returns:
List of subnode names for that node, e.g. ['subsubnode', 'ss1']
"""
subnode_list = []
node = self.fdt.path_offset(node_path)
offset = self.fdt.first_subnode(node, QUIET_NOTFOUND)
while offset > 0:
name = self.fdt.get_name(offset)
subnode_list.append(name)
offset = self.fdt.next_subnode(offset, QUIET_NOTFOUND)
return subnode_list
def testImport(self):
"""Check that we can import the library correctly"""
self.assertEqual(type(libfdt), types.ModuleType)
def testBadFdt(self):
"""Check that a filename provided accidentally is not accepted"""
with self.assertRaises(FdtException) as e:
fdt = libfdt.Fdt(b'a string')
self.assertEqual(e.exception.err, -libfdt.BADMAGIC)
def testSubnodeOffset(self):
"""check that we can locate a subnode by name"""
node1 = self.fdt.path_offset('/subnode@1')
self.assertEqual(self.fdt.subnode_offset(0, 'subnode@1'), node1)
with self.assertRaises(FdtException) as e:
self.fdt.subnode_offset(0, 'missing')
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
node2 = self.fdt.path_offset('/subnode@1/subsubnode')
self.assertEqual(self.fdt.subnode_offset(node1, 'subsubnode'), node2)
def testPathOffset(self):
"""Check that we can find the offset of a node"""
self.assertEqual(self.fdt.path_offset('/'), 0)
self.assertTrue(self.fdt.path_offset('/subnode@1') > 0)
with self.assertRaises(FdtException) as e:
self.fdt.path_offset('/wibble')
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
self.assertEqual(self.fdt.path_offset('/wibble', QUIET_NOTFOUND),
-libfdt.NOTFOUND)
def testPropertyOffset(self):
"""Walk through all the properties in the root node"""
offset = self.fdt.first_property_offset(0)
self.assertTrue(offset > 0)
for i in range(5):
next_offset = self.fdt.next_property_offset(offset)
self.assertTrue(next_offset > offset)
offset = next_offset
self.assertEqual(self.fdt.next_property_offset(offset, QUIET_NOTFOUND),
-libfdt.NOTFOUND)
def testPropertyOffsetExceptions(self):
"""Check that exceptions are raised as expected"""
with self.assertRaises(FdtException) as e:
self.fdt.first_property_offset(107)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
# Quieten the NOTFOUND exception and check that a BADOFFSET
# exception is still raised.
with self.assertRaises(FdtException) as e:
self.fdt.first_property_offset(107, QUIET_NOTFOUND)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
with self.assertRaises(FdtException) as e:
self.fdt.next_property_offset(107, QUIET_NOTFOUND)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
# Check that NOTFOUND can be quietened.
node = self.fdt.path_offset('/subnode@1/ss1')
self.assertEqual(self.fdt.first_property_offset(node, QUIET_NOTFOUND),
-libfdt.NOTFOUND)
with self.assertRaises(FdtException) as e:
self.fdt.first_property_offset(node)
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
def testGetName(self):
"""Check that we can get the name of a node"""
self.assertEqual(self.fdt.get_name(0), '')
node = self.fdt.path_offset('/subnode@1/subsubnode')
self.assertEqual(self.fdt.get_name(node), 'subsubnode')
with self.assertRaises(FdtException) as e:
self.fdt.get_name(-2)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
def testGetPropertyByOffset(self):
"""Check that we can read the name and contents of a property"""
root = 0
poffset = self.fdt.first_property_offset(root)
prop = self.fdt.get_property_by_offset(poffset)
self.assertEqual(prop.name, 'compatible')
self.assertEqual(prop, b'test_tree1\0')
with self.assertRaises(FdtException) as e:
self.fdt.get_property_by_offset(-2)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
self.assertEqual(
-libfdt.BADOFFSET,
self.fdt.get_property_by_offset(-2, [libfdt.BADOFFSET]))
def testGetProp(self):
"""Check that we can read the contents of a property by name"""
root = self.fdt.path_offset('/')
value = self.fdt.getprop(root, "compatible")
self.assertEqual(value, b'test_tree1\0')
self.assertEqual(-libfdt.NOTFOUND, self.fdt.getprop(root, 'missing',
QUIET_NOTFOUND))
with self.assertRaises(FdtException) as e:
self.fdt.getprop(root, 'missing')
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
node = self.fdt.path_offset('/subnode@1/subsubnode')
value = self.fdt.getprop(node, "compatible")
self.assertEqual(value, b'subsubnode1\0subsubnode\0')
def testStrError(self):
"""Check that we can get an error string"""
self.assertEqual(libfdt.strerror(-libfdt.NOTFOUND),
'FDT_ERR_NOTFOUND')
def testNextNodeOffset(self):
"""Check that we can walk through nodes"""
node_list = []
node = 0
depth = 0
while depth >= 0:
node_list.append([depth, self.fdt.get_name(node)])
node, depth = self.fdt.next_node(node, depth, (libfdt.BADOFFSET,))
self.assertEqual(node_list, [
[0, ''],
[1, 'subnode@1'],
[2, 'subsubnode'],
[2, 'ss1'],
[1, 'subnode@2'],
[2, 'subsubnode@0'],
[2, 'ss2'],
])
def testFirstNextSubnodeOffset(self):
"""Check that we can walk through subnodes"""
node_list = []
node = self.fdt.first_subnode(0, QUIET_NOTFOUND)
while node >= 0:
node_list.append(self.fdt.get_name(node))
node = self.fdt.next_subnode(node, QUIET_NOTFOUND)
self.assertEqual(node_list, ['subnode@1', 'subnode@2'])
def testFirstNextSubnodeOffsetExceptions(self):
"""Check except handling for first/next subnode functions"""
node = self.fdt.path_offset('/subnode@1/subsubnode', QUIET_NOTFOUND)
self.assertEqual(self.fdt.first_subnode(node, QUIET_NOTFOUND),
-libfdt.NOTFOUND)
with self.assertRaises(FdtException) as e:
self.fdt.first_subnode(node)
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
node = self.fdt.path_offset('/subnode@1/ss1', QUIET_NOTFOUND)
self.assertEqual(self.fdt.next_subnode(node, QUIET_NOTFOUND),
-libfdt.NOTFOUND)
with self.assertRaises(FdtException) as e:
self.fdt.next_subnode(node)
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
def testDeleteProperty(self):
"""Test that we can delete a property"""
node_name = '/subnode@1'
self.assertEqual(self.GetPropList(node_name),
['compatible', 'reg', 'prop-int'])
node = self.fdt.path_offset('/%s' % node_name)
self.assertEqual(self.fdt.delprop(node, 'reg'), 0)
self.assertEqual(self.GetPropList(node_name),
['compatible', 'prop-int'])
def testHeader(self):
"""Test that we can access the header values"""
self.assertEqual(self.fdt.magic(), 0xd00dfeed)
self.assertEqual(self.fdt.totalsize(), len(self.fdt._fdt))
self.assertEqual(self.fdt.off_dt_struct(), 88)
self.assertEqual(self.fdt.off_dt_strings(), 652)
self.assertEqual(self.fdt.off_mem_rsvmap(), 40)
self.assertEqual(self.fdt.version(), 17)
self.assertEqual(self.fdt.last_comp_version(), 16)
self.assertEqual(self.fdt.boot_cpuid_phys(), 0)
self.assertEqual(self.fdt.size_dt_strings(), 105)
self.assertEqual(self.fdt.size_dt_struct(), 564)
def testPack(self):
"""Test that we can pack the tree after deleting something"""
orig_size = self.fdt.totalsize()
node = self.fdt.path_offset('/subnode@2', QUIET_NOTFOUND)
self.assertEqual(self.fdt.delprop(node, 'prop-int'), 0)
self.assertEqual(orig_size, self.fdt.totalsize())
self.assertEqual(self.fdt.pack(), 0)
self.assertTrue(self.fdt.totalsize() < orig_size)
self.assertEqual(self.fdt.totalsize(), len(self.fdt.as_bytearray()))
def testBadPropertyOffset(self):
"""Test that bad property offsets are detected"""
with self.assertRaises(FdtException) as e:
self.fdt.get_property_by_offset(13)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
with self.assertRaises(FdtException) as e:
self.fdt.first_property_offset(3)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
with self.assertRaises(FdtException) as e:
self.fdt.next_property_offset(3)
self.assertEqual(e.exception.err, -libfdt.BADOFFSET)
def testBadPathOffset(self):
"""Test that bad path names are detected"""
with self.assertRaisesRegex(FdtException, get_err(libfdt.BADPATH)):
self.fdt.path_offset('not-present')
def testQuietAll(self):
"""Check that exceptions can be masked by QUIET_ALL"""
self.assertEqual(-libfdt.NOTFOUND,
self.fdt.path_offset('/missing', QUIET_ALL))
self.assertEqual(-libfdt.BADOFFSET,
self.fdt.get_property_by_offset(13, QUIET_ALL))
self.assertEqual(-libfdt.BADPATH,
self.fdt.path_offset('missing', QUIET_ALL))
def testIntegers(self):
"""Check that integers can be passed and returned"""
self.assertEqual(0, libfdt.fdt_get_phandle(self.fdt._fdt, 0))
node2 = self.fdt.path_offset('/subnode@2')
self.assertEqual(0x2000, libfdt.fdt_get_phandle(self.fdt._fdt, node2))
def testGetPhandle(self):
"""Test for the get_phandle() method"""
self.assertEqual(0, self.fdt.get_phandle(0))
node2 = self.fdt.path_offset('/subnode@2')
self.assertEqual(0x2000, self.fdt.get_phandle(node2))
def testGetAlias(self):
"""Test for the get_alias() method"""
self.assertEqual("/subnode@1", self.fdt3.get_alias('s1'))
self.assertEqual("/subnode@1/subsubnode", self.fdt3.get_alias('ss1'))
self.assertEqual("/subnode@1/subsubnode/subsubsubnode", self.fdt3.get_alias('sss1'))
def testParentOffset(self):
"""Test for the parent_offset() method"""
self.assertEqual(-libfdt.NOTFOUND,
self.fdt.parent_offset(0, QUIET_NOTFOUND))
with self.assertRaises(FdtException) as e:
self.fdt.parent_offset(0)
self.assertEqual(e.exception.err, -libfdt.NOTFOUND)
node1 = self.fdt.path_offset('/subnode@2')
self.assertEqual(0, self.fdt.parent_offset(node1))
node2 = self.fdt.path_offset('/subnode@2/subsubnode@0')
self.assertEqual(node1, self.fdt.parent_offset(node2))
def testNodeOffsetByPhandle(self):
"""Test for the node_offset_by_phandle() method"""
self.assertEqual(-libfdt.NOTFOUND,
self.fdt.node_offset_by_phandle(1, QUIET_NOTFOUND))
node1 = self.fdt.path_offset('/subnode@2')
self.assertEqual(node1, self.fdt.node_offset_by_phandle(0x2000))
node2 = self.fdt.path_offset('/subnode@2/subsubnode@0')
self.assertEqual(node2, self.fdt.node_offset_by_phandle(0x2001))
def get_prop(self, name):
return self.fdt2.getprop(0, name)
def testGetIntProperties(self):
"""Test that we can access properties as integers"""
self.assertEqual(0xdeadbeef, self.get_prop("prop-hex32").as_uint32())
self.assertEqual(123, self.get_prop("prop-uint32").as_uint32())
self.assertEqual(-2, self.get_prop("prop-int32").as_int32())
self.assertEqual(9223372036854775807,
self.get_prop("prop-uint64").as_uint64())
self.assertEqual(-2, self.get_prop("prop-int64").as_int64())
def testReserveMap(self):
"""Test that we can access the memory reserve map"""
self.assertEqual(2, self.fdt.num_mem_rsv())
self.assertEqual([ 0xdeadbeef00000000, 0x100000],
self.fdt.get_mem_rsv(0))
self.assertEqual([123456789, 0o10000], self.fdt.get_mem_rsv(1))
def testEmpty(self):
"""Test that we can create an empty tree"""
self.assertEqual(-libfdt.NOSPACE,
Fdt.create_empty_tree(1, (libfdt.NOSPACE,)))
fdt = Fdt.create_empty_tree(128)
self.assertEqual(128, fdt.totalsize())
def testOpenInto(self):
"""Test that we can resize a tree"""
fdt = Fdt.create_empty_tree(128)
self.assertEqual(128, fdt.totalsize())
fdt.resize(256)
self.assertEqual(256, fdt.totalsize())
fdt.pack()
self.assertTrue(fdt.totalsize() < 128)
def testSetProp(self):
"""Test that we can update and create properties"""
node = self.fdt.path_offset('/subnode@1')
self.fdt.setprop(node, 'compatible', TEST_BYTES_1)
self.assertEqual(TEST_BYTES_1, self.fdt.getprop(node, 'compatible'))
# Check that this property is missing, and that we don't have space to
# add it
self.assertEqual(-libfdt.NOTFOUND,
self.fdt.getprop(node, 'missing', QUIET_NOTFOUND))
self.assertEqual(-libfdt.NOSPACE,
self.fdt.setprop(node, 'missing', TEST_BYTES_1,
quiet=(libfdt.NOSPACE,)))
# Expand the device tree so we now have room
self.fdt.resize(self.fdt.totalsize() + 50)
self.fdt.setprop(node, 'missing', TEST_BYTES_1)
self.assertEqual(TEST_BYTES_1, self.fdt.getprop(node, 'missing'))
def testSetPropU32(self):
"""Test that we can update and create integer properties"""
node = 0
prop = 'prop-int'
self.fdt.setprop_u32(node, prop, TEST_VALUE_1)
self.assertEqual(struct.pack('>I', TEST_VALUE_1),
self.fdt.getprop(node, prop))
def testSetPropU64(self):
"""Test that we can update and create integer properties"""
node = 0
prop = 'prop-int64'
self.fdt.setprop_u64(node, prop, TEST_VALUE64_1)
self.assertEqual(struct.pack('>Q', TEST_VALUE64_1),
self.fdt.getprop(node, prop))
def testSetPropStr(self):
"""Test that we can set a property to a particular string"""
node = 0
prop = 'prop-str'
self.assertEqual(TEST_STRING_1, self.fdt.getprop(node, prop).as_str())
self.fdt.setprop_str(node, prop, TEST_STRING_2)
self.assertEqual(TEST_STRING_2, self.fdt.getprop(node, prop).as_str())
with self.assertRaises(ValueError) as e:
self.fdt.getprop(node, 'prop-int').as_str()
self.assertIn('lacks nul termination', str(e.exception))
node2 = self.fdt.path_offset('/subnode@1/subsubnode')
with self.assertRaises(ValueError) as e:
self.fdt.getprop(node2, 'compatible').as_str()
self.assertIn('embedded nul', str(e.exception))
# Expand the device tree so we now have room
self.fdt.resize(self.fdt.totalsize() + 50)
prop = 'prop-unicode'
self.fdt.setprop_str(node, prop, TEST_STRING_3)
self.assertEqual(TEST_STRING_3,
self.fdt.getprop(node, prop).as_str())
def testSetName(self):
"""Test that we can update a node name"""
node = self.fdt.path_offset('/subnode@1')
old_val = self.fdt.get_name(node)
self.fdt.set_name(node, 'test')
self.assertEqual('test', self.fdt.get_name(node))
with self.assertRaises(ValueError) as e:
self.fdt.set_name(node, 'some\0name')
self.assertIn('embedded nul', str(e.exception))
with self.assertRaises(ValueError) as e:
self.fdt.set_name(node, 'name\0')
self.assertIn('embedded nul', str(e.exception))
def testAddDeleteNodes(self):
"""Test that we can add and delete nodes"""
node_name = '/subnode@1'
self.assertEqual(self.GetSubnodes(node_name), ['subsubnode', 'ss1'])
node = self.fdt.path_offset('%s/subsubnode' % node_name)
self.assertEqual(self.fdt.del_node(node, 'subsubnode'), 0)
self.assertEqual(self.GetSubnodes(node_name), ['ss1'])
node = self.fdt.path_offset(node_name)
offset = self.fdt.add_subnode(node, 'more')
self.assertTrue(offset > 0)
self.assertEqual(self.GetSubnodes(node_name), ['more', 'ss1'])
class PyLibfdtSwTests(unittest.TestCase):
"""Test class for pylibfdt sequential-write DT creation
"""
def assertOk(self, err_code):
self.assertEqual(0, err_code)
def testCreate(self):
# First check the minimum size and also the FdtSw() constructor
with self.assertRaisesRegex(FdtException, get_err(libfdt.NOSPACE)):
self.assertEqual(-libfdt.NOSPACE, FdtSw(3))
sw = FdtSw()
sw.add_reservemap_entry(TEST_ADDR_1, TEST_SIZE_1)
sw.add_reservemap_entry(TEST_ADDR_2, TEST_SIZE_2)
sw.finish_reservemap()
sw.begin_node('')
sw.property_string('compatible', 'test_tree1')
sw.property_u32('prop-int', TEST_VALUE_1)
sw.property_u32('prop-int', TEST_VALUE_1)
sw.property_u64('prop-int64', TEST_VALUE64_1)
sw.property_string('prop-str', TEST_STRING_1)
sw.property_u32('#address-cells', 1)
sw.property_u32('#size-cells', 0)
sw.begin_node('subnode@1')
sw.property_string('compatible', 'subnode1')
sw.property_u32('reg', 1)
sw.property_cell('prop-int', TEST_VALUE_1)
sw.property('data', b'\x00data\x01')
sw.begin_node('subsubnode')
sw.property('compatible', b'subsubnode1\0subsubnode')
sw.property_cell('prop-int', TEST_VALUE_1)
sw.end_node()
sw.begin_node('ss1')
sw.end_node()
sw.end_node()
for i in range(2, 11):
with sw.add_node('subnode@%d' % i):
sw.property_u32('reg', 2)
sw.property_cell('linux,phandle', PHANDLE_1)
sw.property_cell('prop-int', TEST_VALUE_2)
sw.property_u32('#address-cells', 1)
sw.property_u32('#size-cells', 0)
with sw.add_node('subsubnode@0'):
sw.property_u32('reg', 0)
sw.property_cell('phandle', PHANDLE_2)
sw.property('compatible', b'subsubnode2\0subsubnode')
sw.property_cell('prop-int', TEST_VALUE_2)
with sw.add_node('ss2'):
pass
sw.end_node()
fdt = sw.as_fdt()
self.assertEqual(2, fdt.num_mem_rsv())
self.assertEqual([TEST_ADDR_1, TEST_SIZE_1], fdt.get_mem_rsv(0))
# Make sure we can add a few more things
with sw.add_node('another'):
sw.property_u32('reg', 3)
# Make sure we can read from the tree too
node = sw.path_offset('/subnode@1')
self.assertEqual(b'subnode1\0', sw.getprop(node, 'compatible'))
# Make sure we did at least two resizes
self.assertTrue(len(fdt.as_bytearray()) > FdtSw.INC_SIZE * 2)
class PyLibfdtRoTests(unittest.TestCase):
"""Test class for read-only pylibfdt access functions
This just tests a few simple cases. Most of the tests are in
PyLibfdtBasicTests.
Properties:
fdt: Device tree file used for testing
"""
def setUp(self):
"""Read in the device tree we use for testing"""
with open('test_tree1.dtb', mode='rb') as f:
self.fdt = libfdt.FdtRo(f.read())
def testAccess(self):
"""Basic sanity check for the FdtRo class"""
node = self.fdt.path_offset('/subnode@1')
self.assertEqual(b'subnode1\0',
self.fdt.getprop(node, 'compatible'))
node = self.fdt.first_subnode(node)
self.assertEqual(b'this is a placeholder string\0string2\0',
self.fdt.getprop(node, 'placeholder'))
if __name__ == "__main__":
unittest.main()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/dtc/tests/pylibfdt_tests.py
|
#!/usr/bin/env python3
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# While Python 3 is the default, it's also possible to invoke
# this setup.py script with Python 2.
"""
setup.py file for SWIG libfdt
Copyright (C) 2017 Google, Inc.
Written by Simon Glass <sjg@chromium.org>
"""
from distutils.core import setup, Extension
import os
import re
import sys
VERSION_PATTERN = '^#define DTC_VERSION "DTC ([^"]*)"$'
def get_version():
version_file = "../version_gen.h"
f = open(version_file, 'rt')
m = re.match(VERSION_PATTERN, f.readline())
return m.group(1)
setupdir = os.path.dirname(os.path.abspath(sys.argv[0]))
os.chdir(setupdir)
libfdt_module = Extension(
'_libfdt',
sources=['libfdt.i'],
include_dirs=['../libfdt'],
libraries=['fdt'],
library_dirs=['../libfdt'],
swig_opts=['-I../libfdt'],
)
setup(
name='libfdt',
version=get_version(),
author='Simon Glass <sjg@chromium.org>',
description='Python binding for libfdt',
ext_modules=[libfdt_module],
py_modules=['libfdt'],
)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/dtc/pylibfdt/setup.py
|
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Dump the contents of a recorded execution stream
#
# Copyright (c) 2017 Alex Bennée <alex.bennee@linaro.org>
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
import argparse
import struct
from collections import namedtuple
# This mirrors some of the global replay state which some of the
# stream loading refers to. Some decoders may read the next event so
# we need handle that case. Calling reuse_event will ensure the next
# event is read from the cache rather than advancing the file.
class ReplayState(object):
def __init__(self):
self.event = -1
self.event_count = 0
self.already_read = False
self.current_checkpoint = 0
self.checkpoint = 0
def set_event(self, ev):
self.event = ev
self.event_count += 1
def get_event(self):
self.already_read = False
return self.event
def reuse_event(self, ev):
self.event = ev
self.already_read = True
def set_checkpoint(self):
self.checkpoint = self.event - self.checkpoint_start
def get_checkpoint(self):
return self.checkpoint
replay_state = ReplayState()
# Simple read functions that mirror replay-internal.c
# The file-stream is big-endian and manually written out a byte at a time.
def read_byte(fin):
"Read a single byte"
return struct.unpack('>B', fin.read(1))[0]
def read_event(fin):
"Read a single byte event, but save some state"
if replay_state.already_read:
return replay_state.get_event()
else:
replay_state.set_event(read_byte(fin))
return replay_state.event
def read_word(fin):
"Read a 16 bit word"
return struct.unpack('>H', fin.read(2))[0]
def read_dword(fin):
"Read a 32 bit word"
return struct.unpack('>I', fin.read(4))[0]
def read_qword(fin):
"Read a 64 bit word"
return struct.unpack('>Q', fin.read(8))[0]
# Generic decoder structure
Decoder = namedtuple("Decoder", "eid name fn")
def call_decode(table, index, dumpfile):
"Search decode table for next step"
decoder = next((d for d in table if d.eid == index), None)
if not decoder:
print("Could not decode index: %d" % (index))
print("Entry is: %s" % (decoder))
print("Decode Table is:\n%s" % (table))
return False
else:
return decoder.fn(decoder.eid, decoder.name, dumpfile)
# Print event
def print_event(eid, name, string=None, event_count=None):
"Print event with count"
if not event_count:
event_count = replay_state.event_count
if string:
print("%d:%s(%d) %s" % (event_count, name, eid, string))
else:
print("%d:%s(%d)" % (event_count, name, eid))
# Decoders for each event type
def decode_unimp(eid, name, _unused_dumpfile):
"Unimplimented decoder, will trigger exit"
print("%s not handled - will now stop" % (name))
return False
# Checkpoint decoder
def swallow_async_qword(eid, name, dumpfile):
"Swallow a qword of data without looking at it"
step_id = read_qword(dumpfile)
print(" %s(%d) @ %d" % (name, eid, step_id))
return True
async_decode_table = [ Decoder(0, "REPLAY_ASYNC_EVENT_BH", swallow_async_qword),
Decoder(1, "REPLAY_ASYNC_INPUT", decode_unimp),
Decoder(2, "REPLAY_ASYNC_INPUT_SYNC", decode_unimp),
Decoder(3, "REPLAY_ASYNC_CHAR_READ", decode_unimp),
Decoder(4, "REPLAY_ASYNC_EVENT_BLOCK", decode_unimp),
Decoder(5, "REPLAY_ASYNC_EVENT_NET", decode_unimp),
]
# See replay_read_events/replay_read_event
def decode_async(eid, name, dumpfile):
"""Decode an ASYNC event"""
print_event(eid, name)
async_event_kind = read_byte(dumpfile)
async_event_checkpoint = read_byte(dumpfile)
if async_event_checkpoint != replay_state.current_checkpoint:
print(" mismatch between checkpoint %d and async data %d" % (
replay_state.current_checkpoint, async_event_checkpoint))
return True
return call_decode(async_decode_table, async_event_kind, dumpfile)
def decode_instruction(eid, name, dumpfile):
ins_diff = read_dword(dumpfile)
print_event(eid, name, "0x%x" % (ins_diff))
return True
def decode_audio_out(eid, name, dumpfile):
audio_data = read_dword(dumpfile)
print_event(eid, name, "%d" % (audio_data))
return True
def decode_checkpoint(eid, name, dumpfile):
"""Decode a checkpoint.
Checkpoints contain a series of async events with their own specific data.
"""
replay_state.set_checkpoint()
# save event count as we peek ahead
event_number = replay_state.event_count
next_event = read_event(dumpfile)
# if the next event is EVENT_ASYNC there are a bunch of
# async events to read, otherwise we are done
if next_event != 3:
print_event(eid, name, "no additional data", event_number)
else:
print_event(eid, name, "more data follows", event_number)
replay_state.reuse_event(next_event)
return True
def decode_checkpoint_init(eid, name, dumpfile):
print_event(eid, name)
return True
def decode_interrupt(eid, name, dumpfile):
print_event(eid, name)
return True
def decode_clock(eid, name, dumpfile):
clock_data = read_qword(dumpfile)
print_event(eid, name, "0x%x" % (clock_data))
return True
# pre-MTTCG merge
v5_event_table = [Decoder(0, "EVENT_INSTRUCTION", decode_instruction),
Decoder(1, "EVENT_INTERRUPT", decode_interrupt),
Decoder(2, "EVENT_EXCEPTION", decode_unimp),
Decoder(3, "EVENT_ASYNC", decode_async),
Decoder(4, "EVENT_SHUTDOWN", decode_unimp),
Decoder(5, "EVENT_CHAR_WRITE", decode_unimp),
Decoder(6, "EVENT_CHAR_READ_ALL", decode_unimp),
Decoder(7, "EVENT_CHAR_READ_ALL_ERROR", decode_unimp),
Decoder(8, "EVENT_CLOCK_HOST", decode_clock),
Decoder(9, "EVENT_CLOCK_VIRTUAL_RT", decode_clock),
Decoder(10, "EVENT_CP_CLOCK_WARP_START", decode_checkpoint),
Decoder(11, "EVENT_CP_CLOCK_WARP_ACCOUNT", decode_checkpoint),
Decoder(12, "EVENT_CP_RESET_REQUESTED", decode_checkpoint),
Decoder(13, "EVENT_CP_SUSPEND_REQUESTED", decode_checkpoint),
Decoder(14, "EVENT_CP_CLOCK_VIRTUAL", decode_checkpoint),
Decoder(15, "EVENT_CP_CLOCK_HOST", decode_checkpoint),
Decoder(16, "EVENT_CP_CLOCK_VIRTUAL_RT", decode_checkpoint),
Decoder(17, "EVENT_CP_INIT", decode_checkpoint_init),
Decoder(18, "EVENT_CP_RESET", decode_checkpoint),
]
# post-MTTCG merge, AUDIO support added
v6_event_table = [Decoder(0, "EVENT_INSTRUCTION", decode_instruction),
Decoder(1, "EVENT_INTERRUPT", decode_interrupt),
Decoder(2, "EVENT_EXCEPTION", decode_unimp),
Decoder(3, "EVENT_ASYNC", decode_async),
Decoder(4, "EVENT_SHUTDOWN", decode_unimp),
Decoder(5, "EVENT_CHAR_WRITE", decode_unimp),
Decoder(6, "EVENT_CHAR_READ_ALL", decode_unimp),
Decoder(7, "EVENT_CHAR_READ_ALL_ERROR", decode_unimp),
Decoder(8, "EVENT_AUDIO_OUT", decode_audio_out),
Decoder(9, "EVENT_AUDIO_IN", decode_unimp),
Decoder(10, "EVENT_CLOCK_HOST", decode_clock),
Decoder(11, "EVENT_CLOCK_VIRTUAL_RT", decode_clock),
Decoder(12, "EVENT_CP_CLOCK_WARP_START", decode_checkpoint),
Decoder(13, "EVENT_CP_CLOCK_WARP_ACCOUNT", decode_checkpoint),
Decoder(14, "EVENT_CP_RESET_REQUESTED", decode_checkpoint),
Decoder(15, "EVENT_CP_SUSPEND_REQUESTED", decode_checkpoint),
Decoder(16, "EVENT_CP_CLOCK_VIRTUAL", decode_checkpoint),
Decoder(17, "EVENT_CP_CLOCK_HOST", decode_checkpoint),
Decoder(18, "EVENT_CP_CLOCK_VIRTUAL_RT", decode_checkpoint),
Decoder(19, "EVENT_CP_INIT", decode_checkpoint_init),
Decoder(20, "EVENT_CP_RESET", decode_checkpoint),
]
# Shutdown cause added
v7_event_table = [Decoder(0, "EVENT_INSTRUCTION", decode_instruction),
Decoder(1, "EVENT_INTERRUPT", decode_interrupt),
Decoder(2, "EVENT_EXCEPTION", decode_unimp),
Decoder(3, "EVENT_ASYNC", decode_async),
Decoder(4, "EVENT_SHUTDOWN", decode_unimp),
Decoder(5, "EVENT_SHUTDOWN_HOST_ERR", decode_unimp),
Decoder(6, "EVENT_SHUTDOWN_HOST_QMP", decode_unimp),
Decoder(7, "EVENT_SHUTDOWN_HOST_SIGNAL", decode_unimp),
Decoder(8, "EVENT_SHUTDOWN_HOST_UI", decode_unimp),
Decoder(9, "EVENT_SHUTDOWN_GUEST_SHUTDOWN", decode_unimp),
Decoder(10, "EVENT_SHUTDOWN_GUEST_RESET", decode_unimp),
Decoder(11, "EVENT_SHUTDOWN_GUEST_PANIC", decode_unimp),
Decoder(12, "EVENT_SHUTDOWN___MAX", decode_unimp),
Decoder(13, "EVENT_CHAR_WRITE", decode_unimp),
Decoder(14, "EVENT_CHAR_READ_ALL", decode_unimp),
Decoder(15, "EVENT_CHAR_READ_ALL_ERROR", decode_unimp),
Decoder(16, "EVENT_AUDIO_OUT", decode_audio_out),
Decoder(17, "EVENT_AUDIO_IN", decode_unimp),
Decoder(18, "EVENT_CLOCK_HOST", decode_clock),
Decoder(19, "EVENT_CLOCK_VIRTUAL_RT", decode_clock),
Decoder(20, "EVENT_CP_CLOCK_WARP_START", decode_checkpoint),
Decoder(21, "EVENT_CP_CLOCK_WARP_ACCOUNT", decode_checkpoint),
Decoder(22, "EVENT_CP_RESET_REQUESTED", decode_checkpoint),
Decoder(23, "EVENT_CP_SUSPEND_REQUESTED", decode_checkpoint),
Decoder(24, "EVENT_CP_CLOCK_VIRTUAL", decode_checkpoint),
Decoder(25, "EVENT_CP_CLOCK_HOST", decode_checkpoint),
Decoder(26, "EVENT_CP_CLOCK_VIRTUAL_RT", decode_checkpoint),
Decoder(27, "EVENT_CP_INIT", decode_checkpoint_init),
Decoder(28, "EVENT_CP_RESET", decode_checkpoint),
]
def parse_arguments():
"Grab arguments for script"
parser = argparse.ArgumentParser()
parser.add_argument("-f", "--file", help='record/replay dump to read from',
required=True)
return parser.parse_args()
def decode_file(filename):
"Decode a record/replay dump"
dumpfile = open(filename, "rb")
# read and throwaway the header
version = read_dword(dumpfile)
junk = read_qword(dumpfile)
print("HEADER: version 0x%x" % (version))
if version == 0xe02007:
event_decode_table = v7_event_table
replay_state.checkpoint_start = 12
elif version == 0xe02006:
event_decode_table = v6_event_table
replay_state.checkpoint_start = 12
else:
event_decode_table = v5_event_table
replay_state.checkpoint_start = 10
try:
decode_ok = True
while decode_ok:
event = read_event(dumpfile)
decode_ok = call_decode(event_decode_table, event, dumpfile)
finally:
dumpfile.close()
if __name__ == "__main__":
args = parse_arguments()
decode_file(args.file)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/replay-dump.py
|
#!/usr/bin/env python3
# Copyright (c) 2018 Linaro Limited
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
#
# Generate a decoding tree from a specification file.
# See the syntax and semantics in docs/devel/decodetree.rst.
#
import io
import os
import re
import sys
import getopt
insnwidth = 32
bitop_width = 32
insnmask = 0xffffffff
variablewidth = False
fields = {}
arguments = {}
formats = {}
allpatterns = []
anyextern = False
translate_prefix = 'trans'
translate_scope = 'static '
input_file = ''
output_file = None
output_fd = None
insntype = 'uint32_t'
decode_function = 'decode'
# An identifier for C.
re_C_ident = '[a-zA-Z][a-zA-Z0-9_]*'
# Identifiers for Arguments, Fields, Formats and Patterns.
re_arg_ident = '&[a-zA-Z0-9_]*'
re_fld_ident = '%[a-zA-Z0-9_]*'
re_fmt_ident = '@[a-zA-Z0-9_]*'
re_pat_ident = '[a-zA-Z0-9_]*'
def error_with_file(file, lineno, *args):
"""Print an error message from file:line and args and exit."""
global output_file
global output_fd
prefix = ''
if file:
prefix += f'{file}:'
if lineno:
prefix += f'{lineno}:'
if prefix:
prefix += ' '
print(prefix, end='error: ', file=sys.stderr)
print(*args, file=sys.stderr)
if output_file and output_fd:
output_fd.close()
os.remove(output_file)
exit(1)
# end error_with_file
def error(lineno, *args):
error_with_file(input_file, lineno, *args)
# end error
def output(*args):
global output_fd
for a in args:
output_fd.write(a)
def output_autogen():
output('/* This file is autogenerated by scripts/decodetree.py. */\n\n')
def str_indent(c):
"""Return a string with C spaces"""
return ' ' * c
def str_fields(fields):
"""Return a string uniquely identifying FIELDS"""
r = ''
for n in sorted(fields.keys()):
r += '_' + n
return r[1:]
def whex(val):
"""Return a hex string for val padded for insnwidth"""
global insnwidth
return f'0x{val:0{insnwidth // 4}x}'
def whexC(val):
"""Return a hex string for val padded for insnwidth,
and with the proper suffix for a C constant."""
suffix = ''
if val >= 0x100000000:
suffix = 'ull'
elif val >= 0x80000000:
suffix = 'u'
return whex(val) + suffix
def str_match_bits(bits, mask):
"""Return a string pretty-printing BITS/MASK"""
global insnwidth
i = 1 << (insnwidth - 1)
space = 0x01010100
r = ''
while i != 0:
if i & mask:
if i & bits:
r += '1'
else:
r += '0'
else:
r += '.'
if i & space:
r += ' '
i >>= 1
return r
def is_pow2(x):
"""Return true iff X is equal to a power of 2."""
return (x & (x - 1)) == 0
def ctz(x):
"""Return the number of times 2 factors into X."""
assert x != 0
r = 0
while ((x >> r) & 1) == 0:
r += 1
return r
def is_contiguous(bits):
if bits == 0:
return -1
shift = ctz(bits)
if is_pow2((bits >> shift) + 1):
return shift
else:
return -1
def eq_fields_for_args(flds_a, arg):
if len(flds_a) != len(arg.fields):
return False
# Only allow inference on default types
for t in arg.types:
if t != 'int':
return False
for k, a in flds_a.items():
if k not in arg.fields:
return False
return True
def eq_fields_for_fmts(flds_a, flds_b):
if len(flds_a) != len(flds_b):
return False
for k, a in flds_a.items():
if k not in flds_b:
return False
b = flds_b[k]
if a.__class__ != b.__class__ or a != b:
return False
return True
class Field:
"""Class representing a simple instruction field"""
def __init__(self, sign, pos, len):
self.sign = sign
self.pos = pos
self.len = len
self.mask = ((1 << len) - 1) << pos
def __str__(self):
if self.sign:
s = 's'
else:
s = ''
return str(self.pos) + ':' + s + str(self.len)
def str_extract(self):
global bitop_width
s = 's' if self.sign else ''
return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
def __eq__(self, other):
return self.sign == other.sign and self.mask == other.mask
def __ne__(self, other):
return not self.__eq__(other)
# end Field
class MultiField:
"""Class representing a compound instruction field"""
def __init__(self, subs, mask):
self.subs = subs
self.sign = subs[0].sign
self.mask = mask
def __str__(self):
return str(self.subs)
def str_extract(self):
global bitop_width
ret = '0'
pos = 0
for f in reversed(self.subs):
ext = f.str_extract()
if pos == 0:
ret = ext
else:
ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
pos += f.len
return ret
def __ne__(self, other):
if len(self.subs) != len(other.subs):
return True
for a, b in zip(self.subs, other.subs):
if a.__class__ != b.__class__ or a != b:
return True
return False
def __eq__(self, other):
return not self.__ne__(other)
# end MultiField
class ConstField:
"""Class representing an argument field with constant value"""
def __init__(self, value):
self.value = value
self.mask = 0
self.sign = value < 0
def __str__(self):
return str(self.value)
def str_extract(self):
return str(self.value)
def __cmp__(self, other):
return self.value - other.value
# end ConstField
class FunctionField:
"""Class representing a field passed through a function"""
def __init__(self, func, base):
self.mask = base.mask
self.sign = base.sign
self.base = base
self.func = func
def __str__(self):
return self.func + '(' + str(self.base) + ')'
def str_extract(self):
return self.func + '(ctx, ' + self.base.str_extract() + ')'
def __eq__(self, other):
return self.func == other.func and self.base == other.base
def __ne__(self, other):
return not self.__eq__(other)
# end FunctionField
class ParameterField:
"""Class representing a pseudo-field read from a function"""
def __init__(self, func):
self.mask = 0
self.sign = 0
self.func = func
def __str__(self):
return self.func
def str_extract(self):
return self.func + '(ctx)'
def __eq__(self, other):
return self.func == other.func
def __ne__(self, other):
return not self.__eq__(other)
# end ParameterField
class Arguments:
"""Class representing the extracted fields of a format"""
def __init__(self, nm, flds, types, extern):
self.name = nm
self.extern = extern
self.fields = flds
self.types = types
def __str__(self):
return self.name + ' ' + str(self.fields)
def struct_name(self):
return 'arg_' + self.name
def output_def(self):
if not self.extern:
output('typedef struct {\n')
for (n, t) in zip(self.fields, self.types):
output(f' {t} {n};\n')
output('} ', self.struct_name(), ';\n\n')
# end Arguments
class General:
"""Common code between instruction formats and instruction patterns"""
def __init__(self, name, lineno, base, fixb, fixm, udfm, fldm, flds, w):
self.name = name
self.file = input_file
self.lineno = lineno
self.base = base
self.fixedbits = fixb
self.fixedmask = fixm
self.undefmask = udfm
self.fieldmask = fldm
self.fields = flds
self.width = w
def __str__(self):
return self.name + ' ' + str_match_bits(self.fixedbits, self.fixedmask)
def str1(self, i):
return str_indent(i) + self.__str__()
# end General
class Format(General):
"""Class representing an instruction format"""
def extract_name(self):
global decode_function
return decode_function + '_extract_' + self.name
def output_extract(self):
output('static void ', self.extract_name(), '(DisasContext *ctx, ',
self.base.struct_name(), ' *a, ', insntype, ' insn)\n{\n')
for n, f in self.fields.items():
output(' a->', n, ' = ', f.str_extract(), ';\n')
output('}\n\n')
# end Format
class Pattern(General):
"""Class representing an instruction pattern"""
def output_decl(self):
global translate_scope
global translate_prefix
output('typedef ', self.base.base.struct_name(),
' arg_', self.name, ';\n')
output(translate_scope, 'bool ', translate_prefix, '_', self.name,
'(DisasContext *ctx, arg_', self.name, ' *a);\n')
def output_code(self, i, extracted, outerbits, outermask):
global translate_prefix
ind = str_indent(i)
arg = self.base.base.name
output(ind, '/* ', self.file, ':', str(self.lineno), ' */\n')
if not extracted:
output(ind, self.base.extract_name(),
'(ctx, &u.f_', arg, ', insn);\n')
for n, f in self.fields.items():
output(ind, 'u.f_', arg, '.', n, ' = ', f.str_extract(), ';\n')
output(ind, 'if (', translate_prefix, '_', self.name,
'(ctx, &u.f_', arg, ')) return true;\n')
# Normal patterns do not have children.
def build_tree(self):
return
def prop_masks(self):
return
def prop_format(self):
return
def prop_width(self):
return
# end Pattern
class MultiPattern(General):
"""Class representing a set of instruction patterns"""
def __init__(self, lineno):
self.file = input_file
self.lineno = lineno
self.pats = []
self.base = None
self.fixedbits = 0
self.fixedmask = 0
self.undefmask = 0
self.width = None
def __str__(self):
r = 'group'
if self.fixedbits is not None:
r += ' ' + str_match_bits(self.fixedbits, self.fixedmask)
return r
def output_decl(self):
for p in self.pats:
p.output_decl()
def prop_masks(self):
global insnmask
fixedmask = insnmask
undefmask = insnmask
# Collect fixedmask/undefmask for all of the children.
for p in self.pats:
p.prop_masks()
fixedmask &= p.fixedmask
undefmask &= p.undefmask
# Widen fixedmask until all fixedbits match
repeat = True
fixedbits = 0
while repeat and fixedmask != 0:
fixedbits = None
for p in self.pats:
thisbits = p.fixedbits & fixedmask
if fixedbits is None:
fixedbits = thisbits
elif fixedbits != thisbits:
fixedmask &= ~(fixedbits ^ thisbits)
break
else:
repeat = False
self.fixedbits = fixedbits
self.fixedmask = fixedmask
self.undefmask = undefmask
def build_tree(self):
for p in self.pats:
p.build_tree()
def prop_format(self):
for p in self.pats:
p.build_tree()
def prop_width(self):
width = None
for p in self.pats:
p.prop_width()
if width is None:
width = p.width
elif width != p.width:
error_with_file(self.file, self.lineno,
'width mismatch in patterns within braces')
self.width = width
# end MultiPattern
class IncMultiPattern(MultiPattern):
"""Class representing an overlapping set of instruction patterns"""
def output_code(self, i, extracted, outerbits, outermask):
global translate_prefix
ind = str_indent(i)
for p in self.pats:
if outermask != p.fixedmask:
innermask = p.fixedmask & ~outermask
innerbits = p.fixedbits & ~outermask
output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
output(ind, f' /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
output(ind, '}\n')
else:
p.output_code(i, extracted, p.fixedbits, p.fixedmask)
#end IncMultiPattern
class Tree:
"""Class representing a node in a decode tree"""
def __init__(self, fm, tm):
self.fixedmask = fm
self.thismask = tm
self.subs = []
self.base = None
def str1(self, i):
ind = str_indent(i)
r = ind + whex(self.fixedmask)
if self.format:
r += ' ' + self.format.name
r += ' [\n'
for (b, s) in self.subs:
r += ind + f' {whex(b)}:\n'
r += s.str1(i + 4) + '\n'
r += ind + ']'
return r
def __str__(self):
return self.str1(0)
def output_code(self, i, extracted, outerbits, outermask):
ind = str_indent(i)
# If we identified all nodes below have the same format,
# extract the fields now.
if not extracted and self.base:
output(ind, self.base.extract_name(),
'(ctx, &u.f_', self.base.base.name, ', insn);\n')
extracted = True
# Attempt to aid the compiler in producing compact switch statements.
# If the bits in the mask are contiguous, extract them.
sh = is_contiguous(self.thismask)
if sh > 0:
# Propagate SH down into the local functions.
def str_switch(b, sh=sh):
return f'(insn >> {sh}) & {b >> sh:#x}'
def str_case(b, sh=sh):
return hex(b >> sh)
else:
def str_switch(b):
return f'insn & {whexC(b)}'
def str_case(b):
return whexC(b)
output(ind, 'switch (', str_switch(self.thismask), ') {\n')
for b, s in sorted(self.subs):
assert (self.thismask & ~s.fixedmask) == 0
innermask = outermask | self.thismask
innerbits = outerbits | b
output(ind, 'case ', str_case(b), ':\n')
output(ind, ' /* ',
str_match_bits(innerbits, innermask), ' */\n')
s.output_code(i + 4, extracted, innerbits, innermask)
output(ind, ' break;\n')
output(ind, '}\n')
# end Tree
class ExcMultiPattern(MultiPattern):
"""Class representing a non-overlapping set of instruction patterns"""
def output_code(self, i, extracted, outerbits, outermask):
# Defer everything to our decomposed Tree node
self.tree.output_code(i, extracted, outerbits, outermask)
@staticmethod
def __build_tree(pats, outerbits, outermask):
# Find the intersection of all remaining fixedmask.
innermask = ~outermask & insnmask
for i in pats:
innermask &= i.fixedmask
if innermask == 0:
# Edge condition: One pattern covers the entire insnmask
if len(pats) == 1:
t = Tree(outermask, innermask)
t.subs.append((0, pats[0]))
return t
text = 'overlapping patterns:'
for p in pats:
text += '\n' + p.file + ':' + str(p.lineno) + ': ' + str(p)
error_with_file(pats[0].file, pats[0].lineno, text)
fullmask = outermask | innermask
# Sort each element of pats into the bin selected by the mask.
bins = {}
for i in pats:
fb = i.fixedbits & innermask
if fb in bins:
bins[fb].append(i)
else:
bins[fb] = [i]
# We must recurse if any bin has more than one element or if
# the single element in the bin has not been fully matched.
t = Tree(fullmask, innermask)
for b, l in bins.items():
s = l[0]
if len(l) > 1 or s.fixedmask & ~fullmask != 0:
s = ExcMultiPattern.__build_tree(l, b | outerbits, fullmask)
t.subs.append((b, s))
return t
def build_tree(self):
super().prop_format()
self.tree = self.__build_tree(self.pats, self.fixedbits,
self.fixedmask)
@staticmethod
def __prop_format(tree):
"""Propagate Format objects into the decode tree"""
# Depth first search.
for (b, s) in tree.subs:
if isinstance(s, Tree):
ExcMultiPattern.__prop_format(s)
# If all entries in SUBS have the same format, then
# propagate that into the tree.
f = None
for (b, s) in tree.subs:
if f is None:
f = s.base
if f is None:
return
if f is not s.base:
return
tree.base = f
def prop_format(self):
super().prop_format()
self.__prop_format(self.tree)
# end ExcMultiPattern
def parse_field(lineno, name, toks):
"""Parse one instruction field from TOKS at LINENO"""
global fields
global insnwidth
# A "simple" field will have only one entry;
# a "multifield" will have several.
subs = []
width = 0
func = None
for t in toks:
if re.match('^!function=', t):
if func:
error(lineno, 'duplicate function')
func = t.split('=')
func = func[1]
continue
if re.fullmatch('[0-9]+:s[0-9]+', t):
# Signed field extract
subtoks = t.split(':s')
sign = True
elif re.fullmatch('[0-9]+:[0-9]+', t):
# Unsigned field extract
subtoks = t.split(':')
sign = False
else:
error(lineno, f'invalid field token "{t}"')
po = int(subtoks[0])
le = int(subtoks[1])
if po + le > insnwidth:
error(lineno, f'field {t} too large')
f = Field(sign, po, le)
subs.append(f)
width += le
if width > insnwidth:
error(lineno, 'field too large')
if len(subs) == 0:
if func:
f = ParameterField(func)
else:
error(lineno, 'field with no value')
else:
if len(subs) == 1:
f = subs[0]
else:
mask = 0
for s in subs:
if mask & s.mask:
error(lineno, 'field components overlap')
mask |= s.mask
f = MultiField(subs, mask)
if func:
f = FunctionField(func, f)
if name in fields:
error(lineno, 'duplicate field', name)
fields[name] = f
# end parse_field
def parse_arguments(lineno, name, toks):
"""Parse one argument set from TOKS at LINENO"""
global arguments
global re_C_ident
global anyextern
flds = []
types = []
extern = False
for n in toks:
if re.fullmatch('!extern', n):
extern = True
anyextern = True
continue
if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
(n, t) = n.split(':')
elif re.fullmatch(re_C_ident, n):
t = 'int'
else:
error(lineno, f'invalid argument set token "{n}"')
if n in flds:
error(lineno, f'duplicate argument "{n}"')
flds.append(n)
types.append(t)
if name in arguments:
error(lineno, 'duplicate argument set', name)
arguments[name] = Arguments(name, flds, types, extern)
# end parse_arguments
def lookup_field(lineno, name):
global fields
if name in fields:
return fields[name]
error(lineno, 'undefined field', name)
def add_field(lineno, flds, new_name, f):
if new_name in flds:
error(lineno, 'duplicate field', new_name)
flds[new_name] = f
return flds
def add_field_byname(lineno, flds, new_name, old_name):
return add_field(lineno, flds, new_name, lookup_field(lineno, old_name))
def infer_argument_set(flds):
global arguments
global decode_function
for arg in arguments.values():
if eq_fields_for_args(flds, arg):
return arg
name = decode_function + str(len(arguments))
arg = Arguments(name, flds.keys(), ['int'] * len(flds), False)
arguments[name] = arg
return arg
def infer_format(arg, fieldmask, flds, width):
global arguments
global formats
global decode_function
const_flds = {}
var_flds = {}
for n, c in flds.items():
if c is ConstField:
const_flds[n] = c
else:
var_flds[n] = c
# Look for an existing format with the same argument set and fields
for fmt in formats.values():
if arg and fmt.base != arg:
continue
if fieldmask != fmt.fieldmask:
continue
if width != fmt.width:
continue
if not eq_fields_for_fmts(flds, fmt.fields):
continue
return (fmt, const_flds)
name = decode_function + '_Fmt_' + str(len(formats))
if not arg:
arg = infer_argument_set(flds)
fmt = Format(name, 0, arg, 0, 0, 0, fieldmask, var_flds, width)
formats[name] = fmt
return (fmt, const_flds)
# end infer_format
def parse_generic(lineno, parent_pat, name, toks):
"""Parse one instruction format from TOKS at LINENO"""
global fields
global arguments
global formats
global allpatterns
global re_arg_ident
global re_fld_ident
global re_fmt_ident
global re_C_ident
global insnwidth
global insnmask
global variablewidth
is_format = parent_pat is None
fixedmask = 0
fixedbits = 0
undefmask = 0
width = 0
flds = {}
arg = None
fmt = None
for t in toks:
# '&Foo' gives a format an explicit argument set.
if re.fullmatch(re_arg_ident, t):
tt = t[1:]
if arg:
error(lineno, 'multiple argument sets')
if tt in arguments:
arg = arguments[tt]
else:
error(lineno, 'undefined argument set', t)
continue
# '@Foo' gives a pattern an explicit format.
if re.fullmatch(re_fmt_ident, t):
tt = t[1:]
if fmt:
error(lineno, 'multiple formats')
if tt in formats:
fmt = formats[tt]
else:
error(lineno, 'undefined format', t)
continue
# '%Foo' imports a field.
if re.fullmatch(re_fld_ident, t):
tt = t[1:]
flds = add_field_byname(lineno, flds, tt, tt)
continue
# 'Foo=%Bar' imports a field with a different name.
if re.fullmatch(re_C_ident + '=' + re_fld_ident, t):
(fname, iname) = t.split('=%')
flds = add_field_byname(lineno, flds, fname, iname)
continue
# 'Foo=number' sets an argument field to a constant value
if re.fullmatch(re_C_ident + '=[+-]?[0-9]+', t):
(fname, value) = t.split('=')
value = int(value)
flds = add_field(lineno, flds, fname, ConstField(value))
continue
# Pattern of 0s, 1s, dots and dashes indicate required zeros,
# required ones, or dont-cares.
if re.fullmatch('[01.-]+', t):
shift = len(t)
fms = t.replace('0', '1')
fms = fms.replace('.', '0')
fms = fms.replace('-', '0')
fbs = t.replace('.', '0')
fbs = fbs.replace('-', '0')
ubm = t.replace('1', '0')
ubm = ubm.replace('.', '0')
ubm = ubm.replace('-', '1')
fms = int(fms, 2)
fbs = int(fbs, 2)
ubm = int(ubm, 2)
fixedbits = (fixedbits << shift) | fbs
fixedmask = (fixedmask << shift) | fms
undefmask = (undefmask << shift) | ubm
# Otherwise, fieldname:fieldwidth
elif re.fullmatch(re_C_ident + ':s?[0-9]+', t):
(fname, flen) = t.split(':')
sign = False
if flen[0] == 's':
sign = True
flen = flen[1:]
shift = int(flen, 10)
if shift + width > insnwidth:
error(lineno, f'field {fname} exceeds insnwidth')
f = Field(sign, insnwidth - width - shift, shift)
flds = add_field(lineno, flds, fname, f)
fixedbits <<= shift
fixedmask <<= shift
undefmask <<= shift
else:
error(lineno, f'invalid token "{t}"')
width += shift
if variablewidth and width < insnwidth and width % 8 == 0:
shift = insnwidth - width
fixedbits <<= shift
fixedmask <<= shift
undefmask <<= shift
undefmask |= (1 << shift) - 1
# We should have filled in all of the bits of the instruction.
elif not (is_format and width == 0) and width != insnwidth:
error(lineno, f'definition has {width} bits')
# Do not check for fields overlapping fields; one valid usage
# is to be able to duplicate fields via import.
fieldmask = 0
for f in flds.values():
fieldmask |= f.mask
# Fix up what we've parsed to match either a format or a pattern.
if is_format:
# Formats cannot reference formats.
if fmt:
error(lineno, 'format referencing format')
# If an argument set is given, then there should be no fields
# without a place to store it.
if arg:
for f in flds.keys():
if f not in arg.fields:
error(lineno, f'field {f} not in argument set {arg.name}')
else:
arg = infer_argument_set(flds)
if name in formats:
error(lineno, 'duplicate format name', name)
fmt = Format(name, lineno, arg, fixedbits, fixedmask,
undefmask, fieldmask, flds, width)
formats[name] = fmt
else:
# Patterns can reference a format ...
if fmt:
# ... but not an argument simultaneously
if arg:
error(lineno, 'pattern specifies both format and argument set')
if fixedmask & fmt.fixedmask:
error(lineno, 'pattern fixed bits overlap format fixed bits')
if width != fmt.width:
error(lineno, 'pattern uses format of different width')
fieldmask |= fmt.fieldmask
fixedbits |= fmt.fixedbits
fixedmask |= fmt.fixedmask
undefmask |= fmt.undefmask
else:
(fmt, flds) = infer_format(arg, fieldmask, flds, width)
arg = fmt.base
for f in flds.keys():
if f not in arg.fields:
error(lineno, f'field {f} not in argument set {arg.name}')
if f in fmt.fields.keys():
error(lineno, f'field {f} set by format and pattern')
for f in arg.fields:
if f not in flds.keys() and f not in fmt.fields.keys():
error(lineno, f'field {f} not initialized')
pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
undefmask, fieldmask, flds, width)
parent_pat.pats.append(pat)
allpatterns.append(pat)
# Validate the masks that we have assembled.
if fieldmask & fixedmask:
error(lineno, 'fieldmask overlaps fixedmask ',
f'({whex(fieldmask)} & {whex(fixedmask)})')
if fieldmask & undefmask:
error(lineno, 'fieldmask overlaps undefmask ',
f'({whex(fieldmask)} & {whex(undefmask)})')
if fixedmask & undefmask:
error(lineno, 'fixedmask overlaps undefmask ',
f'({whex(fixedmask)} & {whex(undefmask)})')
if not is_format:
allbits = fieldmask | fixedmask | undefmask
if allbits != insnmask:
error(lineno, 'bits left unspecified ',
f'({whex(allbits ^ insnmask)})')
# end parse_general
def parse_file(f, parent_pat):
"""Parse all of the patterns within a file"""
global re_arg_ident
global re_fld_ident
global re_fmt_ident
global re_pat_ident
# Read all of the lines of the file. Concatenate lines
# ending in backslash; discard empty lines and comments.
toks = []
lineno = 0
nesting = 0
nesting_pats = []
for line in f:
lineno += 1
# Expand and strip spaces, to find indent.
line = line.rstrip()
line = line.expandtabs()
len1 = len(line)
line = line.lstrip()
len2 = len(line)
# Discard comments
end = line.find('#')
if end >= 0:
line = line[:end]
t = line.split()
if len(toks) != 0:
# Next line after continuation
toks.extend(t)
else:
# Allow completely blank lines.
if len1 == 0:
continue
indent = len1 - len2
# Empty line due to comment.
if len(t) == 0:
# Indentation must be correct, even for comment lines.
if indent != nesting:
error(lineno, 'indentation ', indent, ' != ', nesting)
continue
start_lineno = lineno
toks = t
# Continuation?
if toks[-1] == '\\':
toks.pop()
continue
name = toks[0]
del toks[0]
# End nesting?
if name == '}' or name == ']':
if len(toks) != 0:
error(start_lineno, 'extra tokens after close brace')
# Make sure { } and [ ] nest properly.
if (name == '}') != isinstance(parent_pat, IncMultiPattern):
error(lineno, 'mismatched close brace')
try:
parent_pat = nesting_pats.pop()
except:
error(lineno, 'extra close brace')
nesting -= 2
if indent != nesting:
error(lineno, 'indentation ', indent, ' != ', nesting)
toks = []
continue
# Everything else should have current indentation.
if indent != nesting:
error(start_lineno, 'indentation ', indent, ' != ', nesting)
# Start nesting?
if name == '{' or name == '[':
if len(toks) != 0:
error(start_lineno, 'extra tokens after open brace')
if name == '{':
nested_pat = IncMultiPattern(start_lineno)
else:
nested_pat = ExcMultiPattern(start_lineno)
parent_pat.pats.append(nested_pat)
nesting_pats.append(parent_pat)
parent_pat = nested_pat
nesting += 2
toks = []
continue
# Determine the type of object needing to be parsed.
if re.fullmatch(re_fld_ident, name):
parse_field(start_lineno, name[1:], toks)
elif re.fullmatch(re_arg_ident, name):
parse_arguments(start_lineno, name[1:], toks)
elif re.fullmatch(re_fmt_ident, name):
parse_generic(start_lineno, None, name[1:], toks)
elif re.fullmatch(re_pat_ident, name):
parse_generic(start_lineno, parent_pat, name, toks)
else:
error(lineno, f'invalid token "{name}"')
toks = []
if nesting != 0:
error(lineno, 'missing close brace')
# end parse_file
class SizeTree:
"""Class representing a node in a size decode tree"""
def __init__(self, m, w):
self.mask = m
self.subs = []
self.base = None
self.width = w
def str1(self, i):
ind = str_indent(i)
r = ind + whex(self.mask) + ' [\n'
for (b, s) in self.subs:
r += ind + f' {whex(b)}:\n'
r += s.str1(i + 4) + '\n'
r += ind + ']'
return r
def __str__(self):
return self.str1(0)
def output_code(self, i, extracted, outerbits, outermask):
ind = str_indent(i)
# If we need to load more bytes to test, do so now.
if extracted < self.width:
output(ind, f'insn = {decode_function}_load_bytes',
f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
extracted = self.width
# Attempt to aid the compiler in producing compact switch statements.
# If the bits in the mask are contiguous, extract them.
sh = is_contiguous(self.mask)
if sh > 0:
# Propagate SH down into the local functions.
def str_switch(b, sh=sh):
return f'(insn >> {sh}) & {b >> sh:#x}'
def str_case(b, sh=sh):
return hex(b >> sh)
else:
def str_switch(b):
return f'insn & {whexC(b)}'
def str_case(b):
return whexC(b)
output(ind, 'switch (', str_switch(self.mask), ') {\n')
for b, s in sorted(self.subs):
innermask = outermask | self.mask
innerbits = outerbits | b
output(ind, 'case ', str_case(b), ':\n')
output(ind, ' /* ',
str_match_bits(innerbits, innermask), ' */\n')
s.output_code(i + 4, extracted, innerbits, innermask)
output(ind, '}\n')
output(ind, 'return insn;\n')
# end SizeTree
class SizeLeaf:
"""Class representing a leaf node in a size decode tree"""
def __init__(self, m, w):
self.mask = m
self.width = w
def str1(self, i):
return str_indent(i) + whex(self.mask)
def __str__(self):
return self.str1(0)
def output_code(self, i, extracted, outerbits, outermask):
global decode_function
ind = str_indent(i)
# If we need to load more bytes, do so now.
if extracted < self.width:
output(ind, f'insn = {decode_function}_load_bytes',
f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
extracted = self.width
output(ind, 'return insn;\n')
# end SizeLeaf
def build_size_tree(pats, width, outerbits, outermask):
global insnwidth
# Collect the mask of bits that are fixed in this width
innermask = 0xff << (insnwidth - width)
innermask &= ~outermask
minwidth = None
onewidth = True
for i in pats:
innermask &= i.fixedmask
if minwidth is None:
minwidth = i.width
elif minwidth != i.width:
onewidth = False;
if minwidth < i.width:
minwidth = i.width
if onewidth:
return SizeLeaf(innermask, minwidth)
if innermask == 0:
if width < minwidth:
return build_size_tree(pats, width + 8, outerbits, outermask)
pnames = []
for p in pats:
pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
error_with_file(pats[0].file, pats[0].lineno,
f'overlapping patterns size {width}:', pnames)
bins = {}
for i in pats:
fb = i.fixedbits & innermask
if fb in bins:
bins[fb].append(i)
else:
bins[fb] = [i]
fullmask = outermask | innermask
lens = sorted(bins.keys())
if len(lens) == 1:
b = lens[0]
return build_size_tree(bins[b], width + 8, b | outerbits, fullmask)
r = SizeTree(innermask, width)
for b, l in bins.items():
s = build_size_tree(l, width, b | outerbits, fullmask)
r.subs.append((b, s))
return r
# end build_size_tree
def prop_size(tree):
"""Propagate minimum widths up the decode size tree"""
if isinstance(tree, SizeTree):
min = None
for (b, s) in tree.subs:
width = prop_size(s)
if min is None or min > width:
min = width
assert min >= tree.width
tree.width = min
else:
min = tree.width
return min
# end prop_size
def main():
global arguments
global formats
global allpatterns
global translate_scope
global translate_prefix
global output_fd
global output_file
global input_file
global insnwidth
global insntype
global insnmask
global decode_function
global bitop_width
global variablewidth
global anyextern
decode_scope = 'static '
long_opts = ['decode=', 'translate=', 'output=', 'insnwidth=',
'static-decode=', 'varinsnwidth=']
try:
(opts, args) = getopt.gnu_getopt(sys.argv[1:], 'o:vw:', long_opts)
except getopt.GetoptError as err:
error(0, err)
for o, a in opts:
if o in ('-o', '--output'):
output_file = a
elif o == '--decode':
decode_function = a
decode_scope = ''
elif o == '--static-decode':
decode_function = a
elif o == '--translate':
translate_prefix = a
translate_scope = ''
elif o in ('-w', '--insnwidth', '--varinsnwidth'):
if o == '--varinsnwidth':
variablewidth = True
insnwidth = int(a)
if insnwidth == 16:
insntype = 'uint16_t'
insnmask = 0xffff
elif insnwidth == 64:
insntype = 'uint64_t'
insnmask = 0xffffffffffffffff
bitop_width = 64
elif insnwidth != 32:
error(0, 'cannot handle insns of width', insnwidth)
else:
assert False, 'unhandled option'
if len(args) < 1:
error(0, 'missing input file')
toppat = ExcMultiPattern(0)
for filename in args:
input_file = filename
f = open(filename, 'rt', encoding='utf-8')
parse_file(f, toppat)
f.close()
# We do not want to compute masks for toppat, because those masks
# are used as a starting point for build_tree. For toppat, we must
# insist that decode begins from naught.
for i in toppat.pats:
i.prop_masks()
toppat.build_tree()
toppat.prop_format()
if variablewidth:
for i in toppat.pats:
i.prop_width()
stree = build_size_tree(toppat.pats, 8, 0, 0)
prop_size(stree)
if output_file:
output_fd = open(output_file, 'wt', encoding='utf-8')
else:
output_fd = io.TextIOWrapper(sys.stdout.buffer,
encoding=sys.stdout.encoding,
errors="ignore")
output_autogen()
for n in sorted(arguments.keys()):
f = arguments[n]
f.output_def()
# A single translate function can be invoked for different patterns.
# Make sure that the argument sets are the same, and declare the
# function only once.
#
# If we're sharing formats, we're likely also sharing trans_* functions,
# but we can't tell which ones. Prevent issues from the compiler by
# suppressing redundant declaration warnings.
if anyextern:
output("#pragma GCC diagnostic push\n",
"#pragma GCC diagnostic ignored \"-Wredundant-decls\"\n",
"#ifdef __clang__\n"
"# pragma GCC diagnostic ignored \"-Wtypedef-redefinition\"\n",
"#endif\n\n")
out_pats = {}
for i in allpatterns:
if i.name in out_pats:
p = out_pats[i.name]
if i.base.base != p.base.base:
error(0, i.name, ' has conflicting argument sets')
else:
i.output_decl()
out_pats[i.name] = i
output('\n')
if anyextern:
output("#pragma GCC diagnostic pop\n\n")
for n in sorted(formats.keys()):
f = formats[n]
f.output_extract()
output(decode_scope, 'bool ', decode_function,
'(DisasContext *ctx, ', insntype, ' insn)\n{\n')
i4 = str_indent(4)
if len(allpatterns) != 0:
output(i4, 'union {\n')
for n in sorted(arguments.keys()):
f = arguments[n]
output(i4, i4, f.struct_name(), ' f_', f.name, ';\n')
output(i4, '} u;\n\n')
toppat.output_code(4, False, 0, 0)
output(i4, 'return false;\n')
output('}\n')
if variablewidth:
output('\n', decode_scope, insntype, ' ', decode_function,
'_load(DisasContext *ctx)\n{\n',
' ', insntype, ' insn = 0;\n\n')
stree.output_code(4, 0, 0, 0)
output('}\n')
if output_file:
output_fd.close()
# end main
if __name__ == '__main__':
main()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/decodetree.py
|
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
import os
import sys
def print_array(name, values):
if len(values) == 0:
return
list = ", ".join(values)
print(" .%s = ((const char*[]){ %s, NULL })," % (name, list))
def parse_line(line):
kind = ""
data = ""
get_kind = False
get_data = False
for item in line.split():
if item == "MODINFO_START":
get_kind = True
continue
if item.startswith("MODINFO_END"):
get_data = False
continue
if get_kind:
kind = item
get_kind = False
get_data = True
continue
if get_data:
data += " " + item
continue
return (kind, data)
def generate(name, lines):
arch = ""
objs = []
deps = []
opts = []
for line in lines:
if line.find("MODINFO_START") != -1:
(kind, data) = parse_line(line)
if kind == 'obj':
objs.append(data)
elif kind == 'dep':
deps.append(data)
elif kind == 'opts':
opts.append(data)
elif kind == 'arch':
arch = data;
else:
print("unknown:", kind)
exit(1)
print(" .name = \"%s\"," % name)
if arch != "":
print(" .arch = %s," % arch)
print_array("objs", objs)
print_array("deps", deps)
print_array("opts", opts)
print("},{");
return deps
def print_pre():
print("/* generated by scripts/modinfo-generate.py */")
print("#include \"qemu/osdep.h\"")
print("#include \"qemu/module.h\"")
print("const QemuModinfo qemu_modinfo[] = {{")
def print_post():
print(" /* end of list */")
print("}};")
def main(args):
deps = {}
print_pre()
for modinfo in args:
with open(modinfo) as f:
lines = f.readlines()
print(" /* %s */" % modinfo)
(basename, ext) = os.path.splitext(modinfo)
deps[basename] = generate(basename, lines)
print_post()
flattened_deps = {flat.strip('" ') for dep in deps.values() for flat in dep}
error = False
for dep in flattened_deps:
if dep not in deps.keys():
print("Dependency {} cannot be satisfied".format(dep),
file=sys.stderr)
error = True
if error:
exit(1)
if __name__ == "__main__":
main(sys.argv[1:])
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/modinfo-generate.py
|
#!/usr/bin/env python3
#
# Pretty-printer for simple trace backend binary trace files
#
# Copyright IBM, Corp. 2010
#
# This work is licensed under the terms of the GNU GPL, version 2. See
# the COPYING file in the top-level directory.
#
# For help see docs/devel/tracing.rst
import struct
import inspect
from tracetool import read_events, Event
from tracetool.backend.simple import is_string
header_event_id = 0xffffffffffffffff
header_magic = 0xf2b177cb0aa429b4
dropped_event_id = 0xfffffffffffffffe
record_type_mapping = 0
record_type_event = 1
log_header_fmt = '=QQQ'
rec_header_fmt = '=QQII'
def read_header(fobj, hfmt):
'''Read a trace record header'''
hlen = struct.calcsize(hfmt)
hdr = fobj.read(hlen)
if len(hdr) != hlen:
return None
return struct.unpack(hfmt, hdr)
def get_record(edict, idtoname, rechdr, fobj):
"""Deserialize a trace record from a file into a tuple
(name, timestamp, pid, arg1, ..., arg6)."""
if rechdr is None:
return None
if rechdr[0] != dropped_event_id:
event_id = rechdr[0]
name = idtoname[event_id]
rec = (name, rechdr[1], rechdr[3])
try:
event = edict[name]
except KeyError as e:
import sys
sys.stderr.write('%s event is logged but is not declared ' \
'in the trace events file, try using ' \
'trace-events-all instead.\n' % str(e))
sys.exit(1)
for type, name in event.args:
if is_string(type):
l = fobj.read(4)
(len,) = struct.unpack('=L', l)
s = fobj.read(len)
rec = rec + (s,)
else:
(value,) = struct.unpack('=Q', fobj.read(8))
rec = rec + (value,)
else:
rec = ("dropped", rechdr[1], rechdr[3])
(value,) = struct.unpack('=Q', fobj.read(8))
rec = rec + (value,)
return rec
def get_mapping(fobj):
(event_id, ) = struct.unpack('=Q', fobj.read(8))
(len, ) = struct.unpack('=L', fobj.read(4))
name = fobj.read(len).decode()
return (event_id, name)
def read_record(edict, idtoname, fobj):
"""Deserialize a trace record from a file into a tuple (event_num, timestamp, pid, arg1, ..., arg6)."""
rechdr = read_header(fobj, rec_header_fmt)
return get_record(edict, idtoname, rechdr, fobj)
def read_trace_header(fobj):
"""Read and verify trace file header"""
header = read_header(fobj, log_header_fmt)
if header is None:
raise ValueError('Not a valid trace file!')
if header[0] != header_event_id:
raise ValueError('Not a valid trace file, header id %d != %d' %
(header[0], header_event_id))
if header[1] != header_magic:
raise ValueError('Not a valid trace file, header magic %d != %d' %
(header[1], header_magic))
log_version = header[2]
if log_version not in [0, 2, 3, 4]:
raise ValueError('Unknown version of tracelog format!')
if log_version != 4:
raise ValueError('Log format %d not supported with this QEMU release!'
% log_version)
def read_trace_records(edict, idtoname, fobj):
"""Deserialize trace records from a file, yielding record tuples (event_num, timestamp, pid, arg1, ..., arg6).
Note that `idtoname` is modified if the file contains mapping records.
Args:
edict (str -> Event): events dict, indexed by name
idtoname (int -> str): event names dict, indexed by event ID
fobj (file): input file
"""
while True:
t = fobj.read(8)
if len(t) == 0:
break
(rectype, ) = struct.unpack('=Q', t)
if rectype == record_type_mapping:
event_id, name = get_mapping(fobj)
idtoname[event_id] = name
else:
rec = read_record(edict, idtoname, fobj)
yield rec
class Analyzer(object):
"""A trace file analyzer which processes trace records.
An analyzer can be passed to run() or process(). The begin() method is
invoked, then each trace record is processed, and finally the end() method
is invoked.
If a method matching a trace event name exists, it is invoked to process
that trace record. Otherwise the catchall() method is invoked.
Example:
The following method handles the runstate_set(int new_state) trace event::
def runstate_set(self, new_state):
...
The method can also take a timestamp argument before the trace event
arguments::
def runstate_set(self, timestamp, new_state):
...
Timestamps have the uint64_t type and are in nanoseconds.
The pid can be included in addition to the timestamp and is useful when
dealing with traces from multiple processes::
def runstate_set(self, timestamp, pid, new_state):
...
"""
def begin(self):
"""Called at the start of the trace."""
pass
def catchall(self, event, rec):
"""Called if no specific method for processing a trace event has been found."""
pass
def end(self):
"""Called at the end of the trace."""
pass
def process(events, log, analyzer, read_header=True):
"""Invoke an analyzer on each event in a log."""
if isinstance(events, str):
events = read_events(open(events, 'r'), events)
if isinstance(log, str):
log = open(log, 'rb')
if read_header:
read_trace_header(log)
frameinfo = inspect.getframeinfo(inspect.currentframe())
dropped_event = Event.build("Dropped_Event(uint64_t num_events_dropped)",
frameinfo.lineno + 1, frameinfo.filename)
edict = {"dropped": dropped_event}
idtoname = {dropped_event_id: "dropped"}
for event in events:
edict[event.name] = event
# If there is no header assume event ID mapping matches events list
if not read_header:
for event_id, event in enumerate(events):
idtoname[event_id] = event.name
def build_fn(analyzer, event):
if isinstance(event, str):
return analyzer.catchall
fn = getattr(analyzer, event.name, None)
if fn is None:
return analyzer.catchall
event_argcount = len(event.args)
fn_argcount = len(inspect.getargspec(fn)[0]) - 1
if fn_argcount == event_argcount + 1:
# Include timestamp as first argument
return lambda _, rec: fn(*(rec[1:2] + rec[3:3 + event_argcount]))
elif fn_argcount == event_argcount + 2:
# Include timestamp and pid
return lambda _, rec: fn(*rec[1:3 + event_argcount])
else:
# Just arguments, no timestamp or pid
return lambda _, rec: fn(*rec[3:3 + event_argcount])
analyzer.begin()
fn_cache = {}
for rec in read_trace_records(edict, idtoname, log):
event_num = rec[0]
event = edict[event_num]
if event_num not in fn_cache:
fn_cache[event_num] = build_fn(analyzer, event)
fn_cache[event_num](event, rec)
analyzer.end()
def run(analyzer):
"""Execute an analyzer on a trace file given on the command-line.
This function is useful as a driver for simple analysis scripts. More
advanced scripts will want to call process() instead."""
import sys
read_header = True
if len(sys.argv) == 4 and sys.argv[1] == '--no-header':
read_header = False
del sys.argv[1]
elif len(sys.argv) != 3:
sys.stderr.write('usage: %s [--no-header] <trace-events> ' \
'<trace-file>\n' % sys.argv[0])
sys.exit(1)
events = read_events(open(sys.argv[1], 'r'), sys.argv[1])
process(events, sys.argv[2], analyzer, read_header=read_header)
if __name__ == '__main__':
class Formatter(Analyzer):
def __init__(self):
self.last_timestamp = None
def catchall(self, event, rec):
timestamp = rec[1]
if self.last_timestamp is None:
self.last_timestamp = timestamp
delta_ns = timestamp - self.last_timestamp
self.last_timestamp = timestamp
fields = [event.name, '%0.3f' % (delta_ns / 1000.0),
'pid=%d' % rec[2]]
i = 3
for type, name in event.args:
if is_string(type):
fields.append('%s=%s' % (name, rec[i]))
else:
fields.append('%s=0x%x' % (name, rec[i]))
i += 1
print(' '.join(fields))
run(Formatter())
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/simpletrace.py
|
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Analyse lock events and compute statistics
#
# Author: Alex Bennée <alex.bennee@linaro.org>
#
import simpletrace
import argparse
import numpy as np
class MutexAnalyser(simpletrace.Analyzer):
"A simpletrace Analyser for checking locks."
def __init__(self):
self.locks = 0
self.locked = 0
self.unlocks = 0
self.mutex_records = {}
def _get_mutex(self, mutex):
if not mutex in self.mutex_records:
self.mutex_records[mutex] = {"locks": 0,
"lock_time": 0,
"acquire_times": [],
"locked": 0,
"locked_time": 0,
"held_times": [],
"unlocked": 0}
return self.mutex_records[mutex]
def qemu_mutex_lock(self, timestamp, mutex, filename, line):
self.locks += 1
rec = self._get_mutex(mutex)
rec["locks"] += 1
rec["lock_time"] = timestamp[0]
rec["lock_loc"] = (filename, line)
def qemu_mutex_locked(self, timestamp, mutex, filename, line):
self.locked += 1
rec = self._get_mutex(mutex)
rec["locked"] += 1
rec["locked_time"] = timestamp[0]
acquire_time = rec["locked_time"] - rec["lock_time"]
rec["locked_loc"] = (filename, line)
rec["acquire_times"].append(acquire_time)
def qemu_mutex_unlock(self, timestamp, mutex, filename, line):
self.unlocks += 1
rec = self._get_mutex(mutex)
rec["unlocked"] += 1
held_time = timestamp[0] - rec["locked_time"]
rec["held_times"].append(held_time)
rec["unlock_loc"] = (filename, line)
def get_args():
"Grab options"
parser = argparse.ArgumentParser()
parser.add_argument("--output", "-o", type=str, help="Render plot to file")
parser.add_argument("events", type=str, help='trace file read from')
parser.add_argument("tracefile", type=str, help='trace file read from')
return parser.parse_args()
if __name__ == '__main__':
args = get_args()
# Gather data from the trace
analyser = MutexAnalyser()
simpletrace.process(args.events, args.tracefile, analyser)
print ("Total locks: %d, locked: %d, unlocked: %d" %
(analyser.locks, analyser.locked, analyser.unlocks))
# Now dump the individual lock stats
for key, val in sorted(analyser.mutex_records.iteritems(),
key=lambda k_v: k_v[1]["locks"]):
print ("Lock: %#x locks: %d, locked: %d, unlocked: %d" %
(key, val["locks"], val["locked"], val["unlocked"]))
acquire_times = np.array(val["acquire_times"])
if len(acquire_times) > 0:
print (" Acquire Time: min:%d median:%d avg:%.2f max:%d" %
(acquire_times.min(), np.median(acquire_times),
acquire_times.mean(), acquire_times.max()))
held_times = np.array(val["held_times"])
if len(held_times) > 0:
print (" Held Time: min:%d median:%d avg:%.2f max:%d" %
(held_times.min(), np.median(held_times),
held_times.mean(), held_times.max()))
# Check if any locks still held
if val["locks"] > val["locked"]:
print (" LOCK HELD (%s:%s)" % (val["locked_loc"]))
print (" BLOCKED (%s:%s)" % (val["lock_loc"]))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/analyse-locks-simpletrace.py
|
#!/usr/bin/env python3
#
# Render Qemu Block Graph
#
# Copyright (c) 2018 Virtuozzo International GmbH. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
import os
import sys
import subprocess
import json
from graphviz import Digraph
sys.path.append(os.path.join(os.path.dirname(__file__), '..', 'python'))
from qemu.qmp import (
QEMUMonitorProtocol,
QMPResponseError,
)
def perm(arr):
s = 'w' if 'write' in arr else '_'
s += 'r' if 'consistent-read' in arr else '_'
s += 'u' if 'write-unchanged' in arr else '_'
s += 'g' if 'graph-mod' in arr else '_'
s += 's' if 'resize' in arr else '_'
return s
def render_block_graph(qmp, filename, format='png'):
'''
Render graph in text (dot) representation into "@filename" and
representation in @format into "@filename.@format"
'''
bds_nodes = qmp.command('query-named-block-nodes')
bds_nodes = {n['node-name']: n for n in bds_nodes}
job_nodes = qmp.command('query-block-jobs')
job_nodes = {n['device']: n for n in job_nodes}
block_graph = qmp.command('x-debug-query-block-graph')
graph = Digraph(comment='Block Nodes Graph')
graph.format = format
graph.node('permission symbols:\l'
' w - Write\l'
' r - consistent-Read\l'
' u - write - Unchanged\l'
' g - Graph-mod\l'
' s - reSize\l'
'edge label scheme:\l'
' <child type>\l'
' <perm>\l'
' <shared_perm>\l', shape='none')
for n in block_graph['nodes']:
if n['type'] == 'block-driver':
info = bds_nodes[n['name']]
label = n['name'] + ' [' + info['drv'] + ']'
if info['drv'] == 'file':
label += '\n' + os.path.basename(info['file'])
shape = 'ellipse'
elif n['type'] == 'block-job':
info = job_nodes[n['name']]
label = info['type'] + ' job (' + n['name'] + ')'
shape = 'box'
else:
assert n['type'] == 'block-backend'
label = n['name'] if n['name'] else 'unnamed blk'
shape = 'box'
graph.node(str(n['id']), label, shape=shape)
for e in block_graph['edges']:
label = '%s\l%s\l%s\l' % (e['name'], perm(e['perm']),
perm(e['shared-perm']))
graph.edge(str(e['parent']), str(e['child']), label=label)
graph.render(filename)
class LibvirtGuest():
def __init__(self, name):
self.name = name
def command(self, cmd):
# only supports qmp commands without parameters
m = {'execute': cmd}
ar = ['virsh', 'qemu-monitor-command', self.name, json.dumps(m)]
reply = json.loads(subprocess.check_output(ar))
if 'error' in reply:
raise QMPResponseError(reply)
return reply['return']
if __name__ == '__main__':
obj = sys.argv[1]
out = sys.argv[2]
if os.path.exists(obj):
# assume unix socket
qmp = QEMUMonitorProtocol(obj)
qmp.connect()
else:
# assume libvirt guest name
qmp = LibvirtGuest(obj)
render_block_graph(qmp, out)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/render_block_graph.py
|
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
"""
Command-line wrapper for the tracetool machinery.
"""
__author__ = "Lluís Vilanova <vilanova@ac.upc.edu>"
__copyright__ = "Copyright 2012-2014, Lluís Vilanova <vilanova@ac.upc.edu>"
__license__ = "GPL version 2 or (at your option) any later version"
__maintainer__ = "Stefan Hajnoczi"
__email__ = "stefanha@redhat.com"
import sys
import getopt
from tracetool import error_write, out, out_open
import tracetool.backend
import tracetool.format
_SCRIPT = ""
def error_opt(msg = None):
if msg is not None:
error_write("Error: " + msg + "\n")
backend_descr = "\n".join([ " %-15s %s" % (n, d)
for n,d in tracetool.backend.get_list() ])
format_descr = "\n".join([ " %-15s %s" % (n, d)
for n,d in tracetool.format.get_list() ])
error_write("""\
Usage: %(script)s --format=<format> --backends=<backends> [<options>] <trace-events> ... <output>
Backends:
%(backends)s
Formats:
%(formats)s
Options:
--help This help message.
--list-backends Print list of available backends.
--check-backends Check if the given backend is valid.
--binary <path> Full path to QEMU binary.
--target-type <type> QEMU emulator target type ('system' or 'user').
--target-name <name> QEMU emulator target name.
--group <name> Name of the event group
--probe-prefix <prefix> Prefix for dtrace probe names
(default: qemu-<target-type>-<target-name>).\
""" % {
"script" : _SCRIPT,
"backends" : backend_descr,
"formats" : format_descr,
})
if msg is None:
sys.exit(0)
else:
sys.exit(1)
def main(args):
global _SCRIPT
_SCRIPT = args[0]
long_opts = ["backends=", "format=", "help", "list-backends",
"check-backends", "group="]
long_opts += ["binary=", "target-type=", "target-name=", "probe-prefix="]
try:
opts, args = getopt.getopt(args[1:], "", long_opts)
except getopt.GetoptError as err:
error_opt(str(err))
check_backends = False
arg_backends = []
arg_format = ""
arg_group = None
binary = None
target_type = None
target_name = None
probe_prefix = None
for opt, arg in opts:
if opt == "--help":
error_opt()
elif opt == "--backends":
arg_backends = arg.split(",")
elif opt == "--group":
arg_group = arg
elif opt == "--format":
arg_format = arg
elif opt == "--list-backends":
public_backends = tracetool.backend.get_list(only_public = True)
out(", ".join([ b for b,_ in public_backends ]))
sys.exit(0)
elif opt == "--check-backends":
check_backends = True
elif opt == "--binary":
binary = arg
elif opt == '--target-type':
target_type = arg
elif opt == '--target-name':
target_name = arg
elif opt == '--probe-prefix':
probe_prefix = arg
else:
error_opt("unhandled option: %s" % opt)
if len(arg_backends) == 0:
error_opt("no backends specified")
if check_backends:
for backend in arg_backends:
if not tracetool.backend.exists(backend):
sys.exit(1)
sys.exit(0)
if arg_group is None:
error_opt("group name is required")
if arg_format == "stap":
if binary is None:
error_opt("--binary is required for SystemTAP tapset generator")
if probe_prefix is None and target_type is None:
error_opt("--target-type is required for SystemTAP tapset generator")
if probe_prefix is None and target_name is None:
error_opt("--target-name is required for SystemTAP tapset generator")
if probe_prefix is None:
probe_prefix = ".".join(["qemu", target_type, target_name])
if len(args) < 2:
error_opt("missing trace-events and output filepaths")
events = []
for arg in args[:-1]:
with open(arg, "r") as fh:
events.extend(tracetool.read_events(fh, arg))
out_open(args[-1])
try:
tracetool.generate(events, arg_group, arg_format, arg_backends,
binary=binary, probe_prefix=probe_prefix)
except tracetool.TracetoolError as e:
error_opt(str(e))
if __name__ == "__main__":
main(sys.argv)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/tracetool.py
|
#!/usr/bin/env python3
#
# Compares vmstate information stored in JSON format, obtained from
# the -dump-vmstate QEMU command.
#
# Copyright 2014 Amit Shah <amit.shah@redhat.com>
# Copyright 2014 Red Hat, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, see <http://www.gnu.org/licenses/>.
import argparse
import json
import sys
# Count the number of errors found
taint = 0
def bump_taint():
global taint
# Ensure we don't wrap around or reset to 0 -- the shell only has
# an 8-bit return value.
if taint < 255:
taint = taint + 1
def check_fields_match(name, s_field, d_field):
if s_field == d_field:
return True
# Some fields changed names between qemu versions. This list
# is used to whitelist such changes in each section / description.
changed_names = {
'apic': ['timer', 'timer_expiry'],
'e1000': ['dev', 'parent_obj'],
'ehci': ['dev', 'pcidev'],
'I440FX': ['dev', 'parent_obj'],
'ich9_ahci': ['card', 'parent_obj'],
'ich9-ahci': ['ahci', 'ich9_ahci'],
'ioh3420': ['PCIDevice', 'PCIEDevice'],
'ioh-3240-express-root-port': ['port.br.dev',
'parent_obj.parent_obj.parent_obj',
'port.br.dev.exp.aer_log',
'parent_obj.parent_obj.parent_obj.exp.aer_log'],
'cirrus_vga': ['hw_cursor_x', 'vga.hw_cursor_x',
'hw_cursor_y', 'vga.hw_cursor_y'],
'lsiscsi': ['dev', 'parent_obj'],
'mch': ['d', 'parent_obj'],
'pci_bridge': ['bridge.dev', 'parent_obj', 'bridge.dev.shpc', 'shpc'],
'pcnet': ['pci_dev', 'parent_obj'],
'PIIX3': ['pci_irq_levels', 'pci_irq_levels_vmstate'],
'piix4_pm': ['dev', 'parent_obj', 'pci0_status',
'acpi_pci_hotplug.acpi_pcihp_pci_status[0x0]',
'pm1a.sts', 'ar.pm1.evt.sts', 'pm1a.en', 'ar.pm1.evt.en',
'pm1_cnt.cnt', 'ar.pm1.cnt.cnt',
'tmr.timer', 'ar.tmr.timer',
'tmr.overflow_time', 'ar.tmr.overflow_time',
'gpe', 'ar.gpe'],
'rtl8139': ['dev', 'parent_obj'],
'qxl': ['num_surfaces', 'ssd.num_surfaces'],
'usb-ccid': ['abProtocolDataStructure', 'abProtocolDataStructure.data'],
'usb-host': ['dev', 'parent_obj'],
'usb-mouse': ['usb-ptr-queue', 'HIDPointerEventQueue'],
'usb-tablet': ['usb-ptr-queue', 'HIDPointerEventQueue'],
'vmware_vga': ['card', 'parent_obj'],
'vmware_vga_internal': ['depth', 'new_depth'],
'xhci': ['pci_dev', 'parent_obj'],
'x3130-upstream': ['PCIDevice', 'PCIEDevice'],
'xio3130-express-downstream-port': ['port.br.dev',
'parent_obj.parent_obj.parent_obj',
'port.br.dev.exp.aer_log',
'parent_obj.parent_obj.parent_obj.exp.aer_log'],
'xio3130-downstream': ['PCIDevice', 'PCIEDevice'],
'xio3130-express-upstream-port': ['br.dev', 'parent_obj.parent_obj',
'br.dev.exp.aer_log',
'parent_obj.parent_obj.exp.aer_log'],
'spapr_pci': ['dma_liobn[0]', 'mig_liobn',
'mem_win_addr', 'mig_mem_win_addr',
'mem_win_size', 'mig_mem_win_size',
'io_win_addr', 'mig_io_win_addr',
'io_win_size', 'mig_io_win_size'],
}
if not name in changed_names:
return False
if s_field in changed_names[name] and d_field in changed_names[name]:
return True
return False
def get_changed_sec_name(sec):
# Section names can change -- see commit 292b1634 for an example.
changes = {
"ICH9 LPC": "ICH9-LPC",
"e1000-82540em": "e1000",
}
for item in changes:
if item == sec:
return changes[item]
if changes[item] == sec:
return item
return ""
def exists_in_substruct(fields, item):
# Some QEMU versions moved a few fields inside a substruct. This
# kept the on-wire format the same. This function checks if
# something got shifted inside a substruct. For example, the
# change in commit 1f42d22233b4f3d1a2933ff30e8d6a6d9ee2d08f
if not "Description" in fields:
return False
if not "Fields" in fields["Description"]:
return False
substruct_fields = fields["Description"]["Fields"]
if substruct_fields == []:
return False
return check_fields_match(fields["Description"]["name"],
substruct_fields[0]["field"], item)
def check_fields(src_fields, dest_fields, desc, sec):
# This function checks for all the fields in a section. If some
# fields got embedded into a substruct, this function will also
# attempt to check inside the substruct.
d_iter = iter(dest_fields)
s_iter = iter(src_fields)
# Using these lists as stacks to store previous value of s_iter
# and d_iter, so that when time comes to exit out of a substruct,
# we can go back one level up and continue from where we left off.
s_iter_list = []
d_iter_list = []
advance_src = True
advance_dest = True
unused_count = 0
while True:
if advance_src:
try:
s_item = next(s_iter)
except StopIteration:
if s_iter_list == []:
break
s_iter = s_iter_list.pop()
continue
else:
if unused_count == 0:
# We want to avoid advancing just once -- when entering a
# dest substruct, or when exiting one.
advance_src = True
if advance_dest:
try:
d_item = next(d_iter)
except StopIteration:
if d_iter_list == []:
# We were not in a substruct
print("Section \"" + sec + "\",", end=' ')
print("Description " + "\"" + desc + "\":", end=' ')
print("expected field \"" + s_item["field"] + "\",", end=' ')
print("while dest has no further fields")
bump_taint()
break
d_iter = d_iter_list.pop()
advance_src = False
continue
else:
if unused_count == 0:
advance_dest = True
if unused_count != 0:
if advance_dest == False:
unused_count = unused_count - s_item["size"]
if unused_count == 0:
advance_dest = True
continue
if unused_count < 0:
print("Section \"" + sec + "\",", end=' ')
print("Description \"" + desc + "\":", end=' ')
print("unused size mismatch near \"", end=' ')
print(s_item["field"] + "\"")
bump_taint()
break
continue
if advance_src == False:
unused_count = unused_count - d_item["size"]
if unused_count == 0:
advance_src = True
continue
if unused_count < 0:
print("Section \"" + sec + "\",", end=' ')
print("Description \"" + desc + "\":", end=' ')
print("unused size mismatch near \"", end=' ')
print(d_item["field"] + "\"")
bump_taint()
break
continue
if not check_fields_match(desc, s_item["field"], d_item["field"]):
# Some fields were put in substructs, keeping the
# on-wire format the same, but breaking static tools
# like this one.
# First, check if dest has a new substruct.
if exists_in_substruct(d_item, s_item["field"]):
# listiterators don't have a prev() function, so we
# have to store our current location, descend into the
# substruct, and ensure we come out as if nothing
# happened when the substruct is over.
#
# Essentially we're opening the substructs that got
# added which didn't change the wire format.
d_iter_list.append(d_iter)
substruct_fields = d_item["Description"]["Fields"]
d_iter = iter(substruct_fields)
advance_src = False
continue
# Next, check if src has substruct that dest removed
# (can happen in backward migration: 2.0 -> 1.5)
if exists_in_substruct(s_item, d_item["field"]):
s_iter_list.append(s_iter)
substruct_fields = s_item["Description"]["Fields"]
s_iter = iter(substruct_fields)
advance_dest = False
continue
if s_item["field"] == "unused" or d_item["field"] == "unused":
if s_item["size"] == d_item["size"]:
continue
if d_item["field"] == "unused":
advance_dest = False
unused_count = d_item["size"] - s_item["size"]
continue
if s_item["field"] == "unused":
advance_src = False
unused_count = s_item["size"] - d_item["size"]
continue
print("Section \"" + sec + "\",", end=' ')
print("Description \"" + desc + "\":", end=' ')
print("expected field \"" + s_item["field"] + "\",", end=' ')
print("got \"" + d_item["field"] + "\"; skipping rest")
bump_taint()
break
check_version(s_item, d_item, sec, desc)
if not "Description" in s_item:
# Check size of this field only if it's not a VMSTRUCT entry
check_size(s_item, d_item, sec, desc, s_item["field"])
check_description_in_list(s_item, d_item, sec, desc)
def check_subsections(src_sub, dest_sub, desc, sec):
for s_item in src_sub:
found = False
for d_item in dest_sub:
if s_item["name"] != d_item["name"]:
continue
found = True
check_descriptions(s_item, d_item, sec)
if not found:
print("Section \"" + sec + "\", Description \"" + desc + "\":", end=' ')
print("Subsection \"" + s_item["name"] + "\" not found")
bump_taint()
def check_description_in_list(s_item, d_item, sec, desc):
if not "Description" in s_item:
return
if not "Description" in d_item:
print("Section \"" + sec + "\", Description \"" + desc + "\",", end=' ')
print("Field \"" + s_item["field"] + "\": missing description")
bump_taint()
return
check_descriptions(s_item["Description"], d_item["Description"], sec)
def check_descriptions(src_desc, dest_desc, sec):
check_version(src_desc, dest_desc, sec, src_desc["name"])
if not check_fields_match(sec, src_desc["name"], dest_desc["name"]):
print("Section \"" + sec + "\":", end=' ')
print("Description \"" + src_desc["name"] + "\"", end=' ')
print("missing, got \"" + dest_desc["name"] + "\" instead; skipping")
bump_taint()
return
for f in src_desc:
if not f in dest_desc:
print("Section \"" + sec + "\"", end=' ')
print("Description \"" + src_desc["name"] + "\":", end=' ')
print("Entry \"" + f + "\" missing")
bump_taint()
continue
if f == 'Fields':
check_fields(src_desc[f], dest_desc[f], src_desc["name"], sec)
if f == 'Subsections':
check_subsections(src_desc[f], dest_desc[f], src_desc["name"], sec)
def check_version(s, d, sec, desc=None):
if s["version_id"] > d["version_id"]:
print("Section \"" + sec + "\"", end=' ')
if desc:
print("Description \"" + desc + "\":", end=' ')
print("version error:", s["version_id"], ">", d["version_id"])
bump_taint()
if not "minimum_version_id" in d:
return
if s["version_id"] < d["minimum_version_id"]:
print("Section \"" + sec + "\"", end=' ')
if desc:
print("Description \"" + desc + "\":", end=' ')
print("minimum version error:", s["version_id"], "<", end=' ')
print(d["minimum_version_id"])
bump_taint()
def check_size(s, d, sec, desc=None, field=None):
if s["size"] != d["size"]:
print("Section \"" + sec + "\"", end=' ')
if desc:
print("Description \"" + desc + "\"", end=' ')
if field:
print("Field \"" + field + "\"", end=' ')
print("size mismatch:", s["size"], ",", d["size"])
bump_taint()
def check_machine_type(s, d):
if s["Name"] != d["Name"]:
print("Warning: checking incompatible machine types:", end=' ')
print("\"" + s["Name"] + "\", \"" + d["Name"] + "\"")
return
def main():
help_text = "Parse JSON-formatted vmstate dumps from QEMU in files SRC and DEST. Checks whether migration from SRC to DEST QEMU versions would break based on the VMSTATE information contained within the JSON outputs. The JSON output is created from a QEMU invocation with the -dump-vmstate parameter and a filename argument to it. Other parameters to QEMU do not matter, except the -M (machine type) parameter."
parser = argparse.ArgumentParser(description=help_text)
parser.add_argument('-s', '--src', type=argparse.FileType('r'),
required=True,
help='json dump from src qemu')
parser.add_argument('-d', '--dest', type=argparse.FileType('r'),
required=True,
help='json dump from dest qemu')
parser.add_argument('--reverse', required=False, default=False,
action='store_true',
help='reverse the direction')
args = parser.parse_args()
src_data = json.load(args.src)
dest_data = json.load(args.dest)
args.src.close()
args.dest.close()
if args.reverse:
temp = src_data
src_data = dest_data
dest_data = temp
for sec in src_data:
dest_sec = sec
if not dest_sec in dest_data:
# Either the section name got changed, or the section
# doesn't exist in dest.
dest_sec = get_changed_sec_name(sec)
if not dest_sec in dest_data:
print("Section \"" + sec + "\" does not exist in dest")
bump_taint()
continue
s = src_data[sec]
d = dest_data[dest_sec]
if sec == "vmschkmachine":
check_machine_type(s, d)
continue
check_version(s, d, sec)
for entry in s:
if not entry in d:
print("Section \"" + sec + "\": Entry \"" + entry + "\"", end=' ')
print("missing")
bump_taint()
continue
if entry == "Description":
check_descriptions(s[entry], d[entry], sec)
return taint
if __name__ == '__main__':
sys.exit(main())
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/vmstate-static-checker.py
|
#!/usr/bin/env python3
#
# GDB debugging support
#
# Copyright 2012 Red Hat, Inc. and/or its affiliates
#
# Authors:
# Avi Kivity <avi@redhat.com>
#
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
# Usage:
# At the (gdb) prompt, type "source scripts/qemu-gdb.py".
# "help qemu" should then list the supported QEMU debug support commands.
import gdb
import os, sys
# Annoyingly, gdb doesn't put the directory of scripts onto the
# module search path. Do it manually.
sys.path.append(os.path.dirname(__file__))
from qemugdb import aio, mtree, coroutine, tcg, timers
class QemuCommand(gdb.Command):
'''Prefix for QEMU debug support commands'''
def __init__(self):
gdb.Command.__init__(self, 'qemu', gdb.COMMAND_DATA,
gdb.COMPLETE_NONE, True)
QemuCommand()
coroutine.CoroutineCommand()
mtree.MtreeCommand()
aio.HandlersCommand()
tcg.TCGLockStatusCommand()
timers.TimersCommand()
coroutine.CoroutineSPFunction()
coroutine.CoroutinePCFunction()
coroutine.CoroutineBt()
# Default to silently passing through SIGUSR1, because QEMU sends it
# to itself a lot.
gdb.execute('handle SIGUSR1 pass noprint nostop')
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qemu-gdb.py
|
#! /usr/bin/env python3
# Create Makefile targets to run tests, from Meson's test introspection data.
#
# Author: Paolo Bonzini <pbonzini@redhat.com>
from collections import defaultdict
import itertools
import json
import os
import shlex
import sys
class Suite(object):
def __init__(self):
self.tests = list()
self.slow_tests = list()
self.executables = set()
print('''
SPEED = quick
# $1 = environment, $2 = test command, $3 = test name, $4 = dir
.test-human-tap = $1 $(if $4,(cd $4 && $2),$2) -m $(SPEED) < /dev/null | ./scripts/tap-driver.pl --test-name="$3" $(if $(V),,--show-failures-only)
.test-human-exitcode = $1 $(PYTHON) scripts/test-driver.py $(if $4,-C$4) $(if $(V),--verbose) -- $2 < /dev/null
.test-tap-tap = $1 $(if $4,(cd $4 && $2),$2) < /dev/null | sed "s/^[a-z][a-z]* [0-9]*/& $3/" || true
.test-tap-exitcode = printf "%s\\n" 1..1 "`$1 $(if $4,(cd $4 && $2),$2) < /dev/null > /dev/null || echo "not "`ok 1 $3"
.test.human-print = echo $(if $(V),'$1 $2','Running test $3') &&
.test.env = MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))}
# $1 = test name, $2 = test target (human or tap)
.test.run = $(call .test.$2-print,$(.test.env.$1),$(.test.cmd.$1),$(.test.name.$1)) $(call .test-$2-$(.test.driver.$1),$(.test.env.$1),$(.test.cmd.$1),$(.test.name.$1),$(.test.dir.$1))
.test.output-format = human
''')
introspect = json.load(sys.stdin)
i = 0
def process_tests(test, targets, suites):
global i
env = ' '.join(('%s=%s' % (shlex.quote(k), shlex.quote(v))
for k, v in test['env'].items()))
executable = test['cmd'][0]
try:
executable = os.path.relpath(executable)
except:
pass
if test['workdir'] is not None:
try:
test['cmd'][0] = os.path.relpath(executable, test['workdir'])
except:
test['cmd'][0] = executable
else:
test['cmd'][0] = executable
cmd = ' '.join((shlex.quote(x) for x in test['cmd']))
driver = test['protocol'] if 'protocol' in test else 'exitcode'
i += 1
if test['workdir'] is not None:
print('.test.dir.%d := %s' % (i, shlex.quote(test['workdir'])))
deps = (targets.get(x, []) for x in test['depends'])
deps = itertools.chain.from_iterable(deps)
print('.test.name.%d := %s' % (i, test['name']))
print('.test.driver.%d := %s' % (i, driver))
print('.test.env.%d := $(.test.env) %s' % (i, env))
print('.test.cmd.%d := %s' % (i, cmd))
print('.test.deps.%d := %s' % (i, ' '.join(deps)))
print('.PHONY: run-test-%d' % (i,))
print('run-test-%d: $(.test.deps.%d)' % (i,i))
print('\t@$(call .test.run,%d,$(.test.output-format))' % (i,))
test_suites = test['suite'] or ['default']
is_slow = any(s.endswith('-slow') for s in test_suites)
for s in test_suites:
# The suite name in the introspection info is "PROJECT:SUITE"
s = s.split(':')[1]
if s.endswith('-slow'):
s = s[:-5]
if is_slow:
suites[s].slow_tests.append(i)
else:
suites[s].tests.append(i)
suites[s].executables.add(executable)
def emit_prolog(suites, prefix):
all_tap = ' '.join(('%s-report-%s.tap' % (prefix, k) for k in suites.keys()))
print('.PHONY: %s %s-report.tap %s' % (prefix, prefix, all_tap))
print('%s: run-tests' % (prefix,))
print('%s-report.tap %s: %s-report%%.tap: all' % (prefix, all_tap, prefix))
print('''\t$(MAKE) .test.output-format=tap --quiet -Otarget V=1 %s$* | ./scripts/tap-merge.pl | tee "$@" \\
| ./scripts/tap-driver.pl $(if $(V),, --show-failures-only)''' % (prefix, ))
def emit_suite(name, suite, prefix):
executables = ' '.join(suite.executables)
slow_test_numbers = ' '.join((str(x) for x in suite.slow_tests))
test_numbers = ' '.join((str(x) for x in suite.tests))
target = '%s-%s' % (prefix, name)
print('.test.quick.%s := %s' % (target, test_numbers))
print('.test.slow.%s := $(.test.quick.%s) %s' % (target, target, slow_test_numbers))
print('%s-build: %s' % (prefix, executables))
print('.PHONY: %s' % (target, ))
print('.PHONY: %s-report-%s.tap' % (prefix, name))
print('%s: run-tests' % (target, ))
print('ifneq ($(filter %s %s, $(MAKECMDGOALS)),)' % (target, prefix))
print('.tests += $(.test.$(SPEED).%s)' % (target, ))
print('endif')
print('all-%s-targets += %s' % (prefix, target))
targets = {t['id']: [os.path.relpath(f) for f in t['filename']]
for t in introspect['targets']}
testsuites = defaultdict(Suite)
for test in introspect['tests']:
process_tests(test, targets, testsuites)
emit_prolog(testsuites, 'check')
for name, suite in testsuites.items():
emit_suite(name, suite, 'check')
benchsuites = defaultdict(Suite)
for test in introspect['benchmarks']:
process_tests(test, targets, benchsuites)
emit_prolog(benchsuites, 'bench')
for name, suite in benchsuites.items():
emit_suite(name, suite, 'bench')
print('run-tests: $(patsubst %, run-test-%, $(.tests))')
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/mtest2make.py
|
#!/usr/bin/python3
#
# userfaultfd-wrlat Summarize userfaultfd write fault latencies.
# Events are continuously accumulated for the
# run, while latency distribution histogram is
# dumped each 'interval' seconds.
#
# For Linux, uses BCC, eBPF.
#
# USAGE: userfaultfd-lat [interval [count]]
#
# Copyright Virtuozzo GmbH, 2020
#
# Authors:
# Andrey Gruzdev <andrey.gruzdev@virtuozzo.com>
#
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
from __future__ import print_function
from bcc import BPF
from ctypes import c_ushort, c_int, c_ulonglong
from time import sleep
from sys import argv
def usage():
print("USAGE: %s [interval [count]]" % argv[0])
exit()
# define BPF program
bpf_text = """
#include <uapi/linux/ptrace.h>
#include <linux/mm.h>
BPF_HASH(ev_start, u32, u64);
BPF_HISTOGRAM(ev_delta_hist, u64);
/* Trace UFFD page fault start event. */
static void do_event_start()
{
/* Using "(u32)" to drop group ID which is upper 32 bits */
u32 tid = (u32) bpf_get_current_pid_tgid();
u64 ts = bpf_ktime_get_ns();
ev_start.update(&tid, &ts);
}
/* Trace UFFD page fault end event. */
static void do_event_end()
{
/* Using "(u32)" to drop group ID which is upper 32 bits */
u32 tid = (u32) bpf_get_current_pid_tgid();
u64 ts = bpf_ktime_get_ns();
u64 *tsp;
tsp = ev_start.lookup(&tid);
if (tsp) {
u64 delta = ts - (*tsp);
/* Transform time delta to milliseconds */
ev_delta_hist.increment(bpf_log2l(delta / 1000000));
ev_start.delete(&tid);
}
}
/* KPROBE for handle_userfault(). */
int probe_handle_userfault(struct pt_regs *ctx, struct vm_fault *vmf,
unsigned long reason)
{
/* Trace only UFFD write faults. */
if (reason & VM_UFFD_WP) {
do_event_start();
}
return 0;
}
/* KRETPROBE for handle_userfault(). */
int retprobe_handle_userfault(struct pt_regs *ctx)
{
do_event_end();
return 0;
}
"""
# arguments
interval = 10
count = -1
if len(argv) > 1:
try:
interval = int(argv[1])
if interval == 0:
raise
if len(argv) > 2:
count = int(argv[2])
except: # also catches -h, --help
usage()
# load BPF program
b = BPF(text=bpf_text)
# attach KRPOBEs
b.attach_kprobe(event="handle_userfault", fn_name="probe_handle_userfault")
b.attach_kretprobe(event="handle_userfault", fn_name="retprobe_handle_userfault")
# header
print("Tracing UFFD-WP write fault latency... Hit Ctrl-C to end.")
# output
loop = 0
do_exit = 0
while (1):
if count > 0:
loop += 1
if loop > count:
exit()
try:
sleep(interval)
except KeyboardInterrupt:
pass; do_exit = 1
print()
b["ev_delta_hist"].print_log2_hist("msecs")
if do_exit:
exit()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/userfaultfd-wrlat.py
|
#!/usr/bin/env python3
# This work is licensed under the terms of the GNU GPL, version 2 or later.
# See the COPYING file in the top-level directory.
"""
QAPI code generation execution shim.
This standalone script exists primarily to facilitate the running of the QAPI
code generator without needing to install the python module to the current
execution environment.
"""
import sys
from qapi import main
if __name__ == '__main__':
sys.exit(main.main())
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi-gen.py
|
#! /usr/bin/env python3
"""Generate coroutine wrappers for block subsystem.
The program parses one or several concatenated c files from stdin,
searches for functions with the 'generated_co_wrapper' specifier
and generates corresponding wrappers on stdout.
Usage: block-coroutine-wrapper.py generated-file.c FILE.[ch]...
Copyright (c) 2020 Virtuozzo International GmbH.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
"""
import sys
import re
from typing import Iterator
def gen_header():
copyright = re.sub('^.*Copyright', 'Copyright', __doc__, flags=re.DOTALL)
copyright = re.sub('^(?=.)', ' * ', copyright.strip(), flags=re.MULTILINE)
copyright = re.sub('^$', ' *', copyright, flags=re.MULTILINE)
return f"""\
/*
* File is generated by scripts/block-coroutine-wrapper.py
*
{copyright}
*/
#include "qemu/osdep.h"
#include "block/coroutines.h"
#include "block/block-gen.h"
#include "block/block_int.h"\
"""
class ParamDecl:
param_re = re.compile(r'(?P<decl>'
r'(?P<type>.*[ *])'
r'(?P<name>[a-z][a-z0-9_]*)'
r')')
def __init__(self, param_decl: str) -> None:
m = self.param_re.match(param_decl.strip())
if m is None:
raise ValueError(f'Wrong parameter declaration: "{param_decl}"')
self.decl = m.group('decl')
self.type = m.group('type')
self.name = m.group('name')
class FuncDecl:
def __init__(self, return_type: str, name: str, args: str) -> None:
self.return_type = return_type.strip()
self.name = name.strip()
self.args = [ParamDecl(arg.strip()) for arg in args.split(',')]
def gen_list(self, format: str) -> str:
return ', '.join(format.format_map(arg.__dict__) for arg in self.args)
def gen_block(self, format: str) -> str:
return '\n'.join(format.format_map(arg.__dict__) for arg in self.args)
# Match wrappers declared with a generated_co_wrapper mark
func_decl_re = re.compile(r'^int\s*generated_co_wrapper\s*'
r'(?P<wrapper_name>[a-z][a-z0-9_]*)'
r'\((?P<args>[^)]*)\);$', re.MULTILINE)
def func_decl_iter(text: str) -> Iterator:
for m in func_decl_re.finditer(text):
yield FuncDecl(return_type='int',
name=m.group('wrapper_name'),
args=m.group('args'))
def snake_to_camel(func_name: str) -> str:
"""
Convert underscore names like 'some_function_name' to camel-case like
'SomeFunctionName'
"""
words = func_name.split('_')
words = [w[0].upper() + w[1:] for w in words]
return ''.join(words)
def gen_wrapper(func: FuncDecl) -> str:
assert not '_co_' in func.name
assert func.return_type == 'int'
assert func.args[0].type in ['BlockDriverState *', 'BdrvChild *']
subsystem, subname = func.name.split('_', 1)
name = f'{subsystem}_co_{subname}'
bs = 'bs' if func.args[0].type == 'BlockDriverState *' else 'child->bs'
struct_name = snake_to_camel(name)
return f"""\
/*
* Wrappers for {name}
*/
typedef struct {struct_name} {{
BdrvPollCo poll_state;
{ func.gen_block(' {decl};') }
}} {struct_name};
static void coroutine_fn {name}_entry(void *opaque)
{{
{struct_name} *s = opaque;
s->poll_state.ret = {name}({ func.gen_list('s->{name}') });
s->poll_state.in_progress = false;
aio_wait_kick();
}}
int {func.name}({ func.gen_list('{decl}') })
{{
if (qemu_in_coroutine()) {{
return {name}({ func.gen_list('{name}') });
}} else {{
{struct_name} s = {{
.poll_state.bs = {bs},
.poll_state.in_progress = true,
{ func.gen_block(' .{name} = {name},') }
}};
s.poll_state.co = qemu_coroutine_create({name}_entry, &s);
return bdrv_poll_co(&s.poll_state);
}}
}}"""
def gen_wrappers(input_code: str) -> str:
res = ''
for func in func_decl_iter(input_code):
res += '\n\n\n'
res += gen_wrapper(func)
return res
if __name__ == '__main__':
if len(sys.argv) < 3:
exit(f'Usage: {sys.argv[0]} OUT_FILE.c IN_FILE.[ch]...')
with open(sys.argv[1], 'w', encoding='utf-8') as f_out:
f_out.write(gen_header())
for fname in sys.argv[2:]:
with open(fname, encoding='utf-8') as f_in:
f_out.write(gen_wrappers(f_in.read()))
f_out.write('\n')
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/block-coroutine-wrapper.py
|
#! /usr/bin/env python3
# Wrapper for tests that hides the output if they succeed.
# Used by "make check"
#
# Copyright (C) 2020 Red Hat, Inc.
#
# Author: Paolo Bonzini <pbonzini@redhat.com>
import subprocess
import sys
import os
import argparse
parser = argparse.ArgumentParser(description='Test driver for QEMU')
parser.add_argument('-C', metavar='DIR', dest='dir', default='.',
help='change to DIR before doing anything else')
parser.add_argument('-v', '--verbose', dest='verbose', action='store_true',
help='be more verbose')
parser.add_argument('test_args', nargs=argparse.REMAINDER)
args = parser.parse_args()
os.chdir(args.dir)
test_args = args.test_args
if test_args[0] == '--':
test_args = test_args[1:]
if args.verbose:
result = subprocess.run(test_args, stdout=None, stderr=None)
else:
result = subprocess.run(test_args, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
if result.returncode:
sys.stdout.buffer.write(result.stdout)
sys.exit(result.returncode)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/test-driver.py
|
#!/usr/bin/env python3
#
# Option ROM signing utility
#
# Authors:
# Jan Kiszka <jan.kiszka@siemens.com>
#
# This work is licensed under the terms of the GNU GPL, version 2 or later.
# See the COPYING file in the top-level directory.
import sys
import struct
if len(sys.argv) < 3:
print('usage: signrom.py input output')
sys.exit(1)
fin = open(sys.argv[1], 'rb')
fout = open(sys.argv[2], 'wb')
magic = fin.read(2)
if magic != b'\x55\xaa':
sys.exit("%s: option ROM does not begin with magic 55 aa" % sys.argv[1])
size_byte = ord(fin.read(1))
fin.seek(0)
data = fin.read()
size = size_byte * 512
if len(data) > size:
sys.stderr.write('error: ROM is too large (%d > %d)\n' % (len(data), size))
sys.exit(1)
elif len(data) < size:
# Add padding if necessary, rounding the whole input to a multiple of
# 512 bytes according to the third byte of the input.
# size-1 because a final byte is added below to store the checksum.
data = data.ljust(size-1, b'\0')
else:
if ord(data[-1:]) != 0:
sys.stderr.write('WARNING: ROM includes nonzero checksum\n')
data = data[:size-1]
fout.write(data)
checksum = 0
for b in data:
checksum = (checksum - b) & 255
fout.write(struct.pack('B', checksum))
fin.close()
fout.close()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/signrom.py
|
#!/usr/bin/env python3
#
# Libu2f-emu setup directory generator for USB U2F key emulation.
#
# Copyright (c) 2020 César Belley <cesar.belley@lse.epita.fr>
# Written by César Belley <cesar.belley@lse.epita.fr>
#
# This work is licensed under the terms of the GNU GPL, version 2
# or, at your option, any later version. See the COPYING file in
# the top-level directory.
import sys
import os
from random import randint
from typing import Tuple
from cryptography.hazmat.backends import default_backend
from cryptography.hazmat.primitives.asymmetric import ec
from cryptography.hazmat.primitives.serialization import Encoding, \
NoEncryption, PrivateFormat, PublicFormat
from OpenSSL import crypto
def write_setup_dir(dirpath: str, privkey_pem: bytes, cert_pem: bytes,
entropy: bytes, counter: int) -> None:
"""
Write the setup directory.
Args:
dirpath: The directory path.
key_pem: The private key PEM.
cert_pem: The certificate PEM.
entropy: The 48 bytes of entropy.
counter: The counter value.
"""
# Directory
os.mkdir(dirpath)
# Private key
with open(f'{dirpath}/private-key.pem', 'bw') as f:
f.write(privkey_pem)
# Certificate
with open(f'{dirpath}/certificate.pem', 'bw') as f:
f.write(cert_pem)
# Entropy
with open(f'{dirpath}/entropy', 'wb') as f:
f.write(entropy)
# Counter
with open(f'{dirpath}/counter', 'w') as f:
f.write(f'{str(counter)}\n')
def generate_ec_key_pair() -> Tuple[str, str]:
"""
Generate an ec key pair.
Returns:
The private and public key PEM.
"""
# Key generation
privkey = ec.generate_private_key(ec.SECP256R1, default_backend())
pubkey = privkey.public_key()
# PEM serialization
privkey_pem = privkey.private_bytes(encoding=Encoding.PEM,
format=PrivateFormat.TraditionalOpenSSL,
encryption_algorithm=NoEncryption())
pubkey_pem = pubkey.public_bytes(encoding=Encoding.PEM,
format=PublicFormat.SubjectPublicKeyInfo)
return privkey_pem, pubkey_pem
def generate_certificate(privkey_pem: str, pubkey_pem: str) -> str:
"""
Generate a x509 certificate from a key pair.
Args:
privkey_pem: The private key PEM.
pubkey_pem: The public key PEM.
Returns:
The certificate PEM.
"""
# Convert key pair
privkey = crypto.load_privatekey(crypto.FILETYPE_PEM, privkey_pem)
pubkey = crypto.load_publickey(crypto.FILETYPE_PEM, pubkey_pem)
# New x509v3 certificate
cert = crypto.X509()
cert.set_version(0x2)
# Serial number
cert.set_serial_number(randint(1, 2 ** 64))
# Before / After
cert.gmtime_adj_notBefore(0)
cert.gmtime_adj_notAfter(4 * (365 * 24 * 60 * 60))
# Public key
cert.set_pubkey(pubkey)
# Subject name and issueer
cert.get_subject().CN = "U2F emulated"
cert.set_issuer(cert.get_subject())
# Extensions
cert.add_extensions([
crypto.X509Extension(b"subjectKeyIdentifier",
False, b"hash", subject=cert),
])
cert.add_extensions([
crypto.X509Extension(b"authorityKeyIdentifier",
False, b"keyid:always", issuer=cert),
])
cert.add_extensions([
crypto.X509Extension(b"basicConstraints", True, b"CA:TRUE")
])
# Signature
cert.sign(privkey, 'sha256')
return crypto.dump_certificate(crypto.FILETYPE_PEM, cert)
def generate_setup_dir(dirpath: str) -> None:
"""
Generates the setup directory.
Args:
dirpath: The directory path.
"""
# Key pair
privkey_pem, pubkey_pem = generate_ec_key_pair()
# Certificate
certificate_pem = generate_certificate(privkey_pem, pubkey_pem)
# Entropy
entropy = os.urandom(48)
# Counter
counter = 0
# Write
write_setup_dir(dirpath, privkey_pem, certificate_pem, entropy, counter)
def main() -> None:
"""
Main function
"""
# Dir path
if len(sys.argv) != 2:
sys.stderr.write(f'Usage: {sys.argv[0]} <setup_dir>\n')
exit(2)
dirpath = sys.argv[1]
# Dir non existence
if os.path.exists(dirpath):
sys.stderr.write(f'Directory: {dirpath} already exists.\n')
exit(1)
generate_setup_dir(dirpath)
if __name__ == '__main__':
main()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/u2f-setup-gen.py
|
#!/usr/bin/env python3
#
# Mini-Kconfig parser
#
# Copyright (c) 2015 Red Hat Inc.
#
# Authors:
# Paolo Bonzini <pbonzini@redhat.com>
#
# This work is licensed under the terms of the GNU GPL, version 2
# or, at your option, any later version. See the COPYING file in
# the top-level directory.
import os
import sys
import re
import random
__all__ = [ 'KconfigDataError', 'KconfigParserError',
'KconfigData', 'KconfigParser' ,
'defconfig', 'allyesconfig', 'allnoconfig', 'randconfig' ]
def debug_print(*args):
#print('# ' + (' '.join(str(x) for x in args)))
pass
# -------------------------------------------
# KconfigData implements the Kconfig semantics. For now it can only
# detect undefined symbols, i.e. symbols that were referenced in
# assignments or dependencies but were not declared with "config FOO".
#
# Semantic actions are represented by methods called do_*. The do_var
# method return the semantic value of a variable (which right now is
# just its name).
# -------------------------------------------
class KconfigDataError(Exception):
def __init__(self, msg):
self.msg = msg
def __str__(self):
return self.msg
allyesconfig = lambda x: True
allnoconfig = lambda x: False
defconfig = lambda x: x
randconfig = lambda x: random.randint(0, 1) == 1
class KconfigData:
class Expr:
def __and__(self, rhs):
return KconfigData.AND(self, rhs)
def __or__(self, rhs):
return KconfigData.OR(self, rhs)
def __invert__(self):
return KconfigData.NOT(self)
# Abstract methods
def add_edges_to(self, var):
pass
def evaluate(self):
assert False
class AND(Expr):
def __init__(self, lhs, rhs):
self.lhs = lhs
self.rhs = rhs
def __str__(self):
return "(%s && %s)" % (self.lhs, self.rhs)
def add_edges_to(self, var):
self.lhs.add_edges_to(var)
self.rhs.add_edges_to(var)
def evaluate(self):
return self.lhs.evaluate() and self.rhs.evaluate()
class OR(Expr):
def __init__(self, lhs, rhs):
self.lhs = lhs
self.rhs = rhs
def __str__(self):
return "(%s || %s)" % (self.lhs, self.rhs)
def add_edges_to(self, var):
self.lhs.add_edges_to(var)
self.rhs.add_edges_to(var)
def evaluate(self):
return self.lhs.evaluate() or self.rhs.evaluate()
class NOT(Expr):
def __init__(self, lhs):
self.lhs = lhs
def __str__(self):
return "!%s" % (self.lhs)
def add_edges_to(self, var):
self.lhs.add_edges_to(var)
def evaluate(self):
return not self.lhs.evaluate()
class Var(Expr):
def __init__(self, name):
self.name = name
self.value = None
self.outgoing = set()
self.clauses_for_var = list()
def __str__(self):
return self.name
def has_value(self):
return not (self.value is None)
def set_value(self, val, clause):
self.clauses_for_var.append(clause)
if self.has_value() and self.value != val:
print("The following clauses were found for " + self.name)
for i in self.clauses_for_var:
print(" " + str(i), file=sys.stderr)
raise KconfigDataError('contradiction between clauses when setting %s' % self)
debug_print("=> %s is now %s" % (self.name, val))
self.value = val
# depth first search of the dependency graph
def dfs(self, visited, f):
if self in visited:
return
visited.add(self)
for v in self.outgoing:
v.dfs(visited, f)
f(self)
def add_edges_to(self, var):
self.outgoing.add(var)
def evaluate(self):
if not self.has_value():
raise KconfigDataError('cycle found including %s' % self)
return self.value
class Clause:
def __init__(self, dest):
self.dest = dest
def priority(self):
return 0
def process(self):
pass
class AssignmentClause(Clause):
def __init__(self, dest, value):
KconfigData.Clause.__init__(self, dest)
self.value = value
def __str__(self):
return "CONFIG_%s=%s" % (self.dest, 'y' if self.value else 'n')
def process(self):
self.dest.set_value(self.value, self)
class DefaultClause(Clause):
def __init__(self, dest, value, cond=None):
KconfigData.Clause.__init__(self, dest)
self.value = value
self.cond = cond
if not (self.cond is None):
self.cond.add_edges_to(self.dest)
def __str__(self):
value = 'y' if self.value else 'n'
if self.cond is None:
return "config %s default %s" % (self.dest, value)
else:
return "config %s default %s if %s" % (self.dest, value, self.cond)
def priority(self):
# Defaults are processed just before leaving the variable
return -1
def process(self):
if not self.dest.has_value() and \
(self.cond is None or self.cond.evaluate()):
self.dest.set_value(self.value, self)
class DependsOnClause(Clause):
def __init__(self, dest, expr):
KconfigData.Clause.__init__(self, dest)
self.expr = expr
self.expr.add_edges_to(self.dest)
def __str__(self):
return "config %s depends on %s" % (self.dest, self.expr)
def process(self):
if not self.expr.evaluate():
self.dest.set_value(False, self)
class SelectClause(Clause):
def __init__(self, dest, cond):
KconfigData.Clause.__init__(self, dest)
self.cond = cond
self.cond.add_edges_to(self.dest)
def __str__(self):
return "select %s if %s" % (self.dest, self.cond)
def process(self):
if self.cond.evaluate():
self.dest.set_value(True, self)
def __init__(self, value_mangler=defconfig):
self.value_mangler = value_mangler
self.previously_included = []
self.incl_info = None
self.defined_vars = set()
self.referenced_vars = dict()
self.clauses = list()
# semantic analysis -------------
def check_undefined(self):
undef = False
for i in self.referenced_vars:
if not (i in self.defined_vars):
print("undefined symbol %s" % (i), file=sys.stderr)
undef = True
return undef
def compute_config(self):
if self.check_undefined():
raise KconfigDataError("there were undefined symbols")
return None
debug_print("Input:")
for clause in self.clauses:
debug_print(clause)
debug_print("\nDependency graph:")
for i in self.referenced_vars:
debug_print(i, "->", [str(x) for x in self.referenced_vars[i].outgoing])
# The reverse of the depth-first order is the topological sort
dfo = dict()
visited = set()
debug_print("\n")
def visit_fn(var):
debug_print(var, "has DFS number", len(dfo))
dfo[var] = len(dfo)
for name, v in self.referenced_vars.items():
self.do_default(v, False)
v.dfs(visited, visit_fn)
# Put higher DFS numbers and higher priorities first. This
# places the clauses in topological order and places defaults
# after assignments and dependencies.
self.clauses.sort(key=lambda x: (-dfo[x.dest], -x.priority()))
debug_print("\nSorted clauses:")
for clause in self.clauses:
debug_print(clause)
clause.process()
debug_print("")
values = dict()
for name, v in self.referenced_vars.items():
debug_print("Evaluating", name)
values[name] = v.evaluate()
return values
# semantic actions -------------
def do_declaration(self, var):
if (var in self.defined_vars):
raise KconfigDataError('variable "' + var + '" defined twice')
self.defined_vars.add(var.name)
# var is a string with the variable's name.
def do_var(self, var):
if (var in self.referenced_vars):
return self.referenced_vars[var]
var_obj = self.referenced_vars[var] = KconfigData.Var(var)
return var_obj
def do_assignment(self, var, val):
self.clauses.append(KconfigData.AssignmentClause(var, val))
def do_default(self, var, val, cond=None):
val = self.value_mangler(val)
self.clauses.append(KconfigData.DefaultClause(var, val, cond))
def do_depends_on(self, var, expr):
self.clauses.append(KconfigData.DependsOnClause(var, expr))
def do_select(self, var, symbol, cond=None):
cond = (cond & var) if cond is not None else var
self.clauses.append(KconfigData.SelectClause(symbol, cond))
def do_imply(self, var, symbol, cond=None):
# "config X imply Y [if COND]" is the same as
# "config Y default y if X [&& COND]"
cond = (cond & var) if cond is not None else var
self.do_default(symbol, True, cond)
# -------------------------------------------
# KconfigParser implements a recursive descent parser for (simplified)
# Kconfig syntax.
# -------------------------------------------
# tokens table
TOKENS = {}
TOK_NONE = -1
TOK_LPAREN = 0; TOKENS[TOK_LPAREN] = '"("';
TOK_RPAREN = 1; TOKENS[TOK_RPAREN] = '")"';
TOK_EQUAL = 2; TOKENS[TOK_EQUAL] = '"="';
TOK_AND = 3; TOKENS[TOK_AND] = '"&&"';
TOK_OR = 4; TOKENS[TOK_OR] = '"||"';
TOK_NOT = 5; TOKENS[TOK_NOT] = '"!"';
TOK_DEPENDS = 6; TOKENS[TOK_DEPENDS] = '"depends"';
TOK_ON = 7; TOKENS[TOK_ON] = '"on"';
TOK_SELECT = 8; TOKENS[TOK_SELECT] = '"select"';
TOK_IMPLY = 9; TOKENS[TOK_IMPLY] = '"imply"';
TOK_CONFIG = 10; TOKENS[TOK_CONFIG] = '"config"';
TOK_DEFAULT = 11; TOKENS[TOK_DEFAULT] = '"default"';
TOK_Y = 12; TOKENS[TOK_Y] = '"y"';
TOK_N = 13; TOKENS[TOK_N] = '"n"';
TOK_SOURCE = 14; TOKENS[TOK_SOURCE] = '"source"';
TOK_BOOL = 15; TOKENS[TOK_BOOL] = '"bool"';
TOK_IF = 16; TOKENS[TOK_IF] = '"if"';
TOK_ID = 17; TOKENS[TOK_ID] = 'identifier';
TOK_EOF = 18; TOKENS[TOK_EOF] = 'end of file';
class KconfigParserError(Exception):
def __init__(self, parser, msg, tok=None):
self.loc = parser.location()
tok = tok or parser.tok
if tok != TOK_NONE:
location = TOKENS.get(tok, None) or ('"%s"' % tok)
msg = '%s before %s' % (msg, location)
self.msg = msg
def __str__(self):
return "%s: %s" % (self.loc, self.msg)
class KconfigParser:
@classmethod
def parse(self, fp, mode=None):
data = KconfigData(mode or KconfigParser.defconfig)
parser = KconfigParser(data)
parser.parse_file(fp)
return data
def __init__(self, data):
self.data = data
def parse_file(self, fp):
self.abs_fname = os.path.abspath(fp.name)
self.fname = fp.name
self.data.previously_included.append(self.abs_fname)
self.src = fp.read()
if self.src == '' or self.src[-1] != '\n':
self.src += '\n'
self.cursor = 0
self.line = 1
self.line_pos = 0
self.get_token()
self.parse_config()
def do_assignment(self, var, val):
if not var.startswith("CONFIG_"):
raise Error('assigned variable should start with CONFIG_')
var = self.data.do_var(var[7:])
self.data.do_assignment(var, val)
# file management -----
def error_path(self):
inf = self.data.incl_info
res = ""
while inf:
res = ("In file included from %s:%d:\n" % (inf['file'],
inf['line'])) + res
inf = inf['parent']
return res
def location(self):
col = 1
for ch in self.src[self.line_pos:self.pos]:
if ch == '\t':
col += 8 - ((col - 1) % 8)
else:
col += 1
return '%s%s:%d:%d' %(self.error_path(), self.fname, self.line, col)
def do_include(self, include):
incl_abs_fname = os.path.join(os.path.dirname(self.abs_fname),
include)
# catch inclusion cycle
inf = self.data.incl_info
while inf:
if incl_abs_fname == os.path.abspath(inf['file']):
raise KconfigParserError(self, "Inclusion loop for %s"
% include)
inf = inf['parent']
# skip multiple include of the same file
if incl_abs_fname in self.data.previously_included:
return
try:
fp = open(incl_abs_fname, 'rt', encoding='utf-8')
except IOError as e:
raise KconfigParserError(self,
'%s: %s' % (e.strerror, include))
inf = self.data.incl_info
self.data.incl_info = { 'file': self.fname, 'line': self.line,
'parent': inf }
KconfigParser(self.data).parse_file(fp)
self.data.incl_info = inf
# recursive descent parser -----
# y_or_n: Y | N
def parse_y_or_n(self):
if self.tok == TOK_Y:
self.get_token()
return True
if self.tok == TOK_N:
self.get_token()
return False
raise KconfigParserError(self, 'Expected "y" or "n"')
# var: ID
def parse_var(self):
if self.tok == TOK_ID:
val = self.val
self.get_token()
return self.data.do_var(val)
else:
raise KconfigParserError(self, 'Expected identifier')
# assignment_var: ID (starting with "CONFIG_")
def parse_assignment_var(self):
if self.tok == TOK_ID:
val = self.val
if not val.startswith("CONFIG_"):
raise KconfigParserError(self,
'Expected identifier starting with "CONFIG_"', TOK_NONE)
self.get_token()
return self.data.do_var(val[7:])
else:
raise KconfigParserError(self, 'Expected identifier')
# assignment: var EQUAL y_or_n
def parse_assignment(self):
var = self.parse_assignment_var()
if self.tok != TOK_EQUAL:
raise KconfigParserError(self, 'Expected "="')
self.get_token()
self.data.do_assignment(var, self.parse_y_or_n())
# primary: NOT primary
# | LPAREN expr RPAREN
# | var
def parse_primary(self):
if self.tok == TOK_NOT:
self.get_token()
val = ~self.parse_primary()
elif self.tok == TOK_LPAREN:
self.get_token()
val = self.parse_expr()
if self.tok != TOK_RPAREN:
raise KconfigParserError(self, 'Expected ")"')
self.get_token()
elif self.tok == TOK_ID:
val = self.parse_var()
else:
raise KconfigParserError(self, 'Expected "!" or "(" or identifier')
return val
# disj: primary (OR primary)*
def parse_disj(self):
lhs = self.parse_primary()
while self.tok == TOK_OR:
self.get_token()
lhs = lhs | self.parse_primary()
return lhs
# expr: disj (AND disj)*
def parse_expr(self):
lhs = self.parse_disj()
while self.tok == TOK_AND:
self.get_token()
lhs = lhs & self.parse_disj()
return lhs
# condition: IF expr
# | empty
def parse_condition(self):
if self.tok == TOK_IF:
self.get_token()
return self.parse_expr()
else:
return None
# property: DEFAULT y_or_n condition
# | DEPENDS ON expr
# | SELECT var condition
# | BOOL
def parse_property(self, var):
if self.tok == TOK_DEFAULT:
self.get_token()
val = self.parse_y_or_n()
cond = self.parse_condition()
self.data.do_default(var, val, cond)
elif self.tok == TOK_DEPENDS:
self.get_token()
if self.tok != TOK_ON:
raise KconfigParserError(self, 'Expected "on"')
self.get_token()
self.data.do_depends_on(var, self.parse_expr())
elif self.tok == TOK_SELECT:
self.get_token()
symbol = self.parse_var()
cond = self.parse_condition()
self.data.do_select(var, symbol, cond)
elif self.tok == TOK_IMPLY:
self.get_token()
symbol = self.parse_var()
cond = self.parse_condition()
self.data.do_imply(var, symbol, cond)
elif self.tok == TOK_BOOL:
self.get_token()
else:
raise KconfigParserError(self, 'Error in recursive descent?')
# properties: properties property
# | /* empty */
def parse_properties(self, var):
had_default = False
while self.tok == TOK_DEFAULT or self.tok == TOK_DEPENDS or \
self.tok == TOK_SELECT or self.tok == TOK_BOOL or \
self.tok == TOK_IMPLY:
self.parse_property(var)
# for nicer error message
if self.tok != TOK_SOURCE and self.tok != TOK_CONFIG and \
self.tok != TOK_ID and self.tok != TOK_EOF:
raise KconfigParserError(self, 'expected "source", "config", identifier, '
+ '"default", "depends on", "imply" or "select"')
# declaration: config var properties
def parse_declaration(self):
if self.tok == TOK_CONFIG:
self.get_token()
var = self.parse_var()
self.data.do_declaration(var)
self.parse_properties(var)
else:
raise KconfigParserError(self, 'Error in recursive descent?')
# clause: SOURCE
# | declaration
# | assignment
def parse_clause(self):
if self.tok == TOK_SOURCE:
val = self.val
self.get_token()
self.do_include(val)
elif self.tok == TOK_CONFIG:
self.parse_declaration()
elif self.tok == TOK_ID:
self.parse_assignment()
else:
raise KconfigParserError(self, 'expected "source", "config" or identifier')
# config: clause+ EOF
def parse_config(self):
while self.tok != TOK_EOF:
self.parse_clause()
return self.data
# scanner -----
def get_token(self):
while True:
self.tok = self.src[self.cursor]
self.pos = self.cursor
self.cursor += 1
self.val = None
self.tok = self.scan_token()
if self.tok is not None:
return
def check_keyword(self, rest):
if not self.src.startswith(rest, self.cursor):
return False
length = len(rest)
if self.src[self.cursor + length].isalnum() or self.src[self.cursor + length] == '_':
return False
self.cursor += length
return True
def scan_token(self):
if self.tok == '#':
self.cursor = self.src.find('\n', self.cursor)
return None
elif self.tok == '=':
return TOK_EQUAL
elif self.tok == '(':
return TOK_LPAREN
elif self.tok == ')':
return TOK_RPAREN
elif self.tok == '&' and self.src[self.pos+1] == '&':
self.cursor += 1
return TOK_AND
elif self.tok == '|' and self.src[self.pos+1] == '|':
self.cursor += 1
return TOK_OR
elif self.tok == '!':
return TOK_NOT
elif self.tok == 'd' and self.check_keyword("epends"):
return TOK_DEPENDS
elif self.tok == 'o' and self.check_keyword("n"):
return TOK_ON
elif self.tok == 's' and self.check_keyword("elect"):
return TOK_SELECT
elif self.tok == 'i' and self.check_keyword("mply"):
return TOK_IMPLY
elif self.tok == 'c' and self.check_keyword("onfig"):
return TOK_CONFIG
elif self.tok == 'd' and self.check_keyword("efault"):
return TOK_DEFAULT
elif self.tok == 'b' and self.check_keyword("ool"):
return TOK_BOOL
elif self.tok == 'i' and self.check_keyword("f"):
return TOK_IF
elif self.tok == 'y' and self.check_keyword(""):
return TOK_Y
elif self.tok == 'n' and self.check_keyword(""):
return TOK_N
elif (self.tok == 's' and self.check_keyword("ource")) or \
self.tok == 'i' and self.check_keyword("nclude"):
# source FILENAME
# include FILENAME
while self.src[self.cursor].isspace():
self.cursor += 1
start = self.cursor
self.cursor = self.src.find('\n', self.cursor)
self.val = self.src[start:self.cursor]
return TOK_SOURCE
elif self.tok.isalnum():
# identifier
while self.src[self.cursor].isalnum() or self.src[self.cursor] == '_':
self.cursor += 1
self.val = self.src[self.pos:self.cursor]
return TOK_ID
elif self.tok == '\n':
if self.cursor == len(self.src):
return TOK_EOF
self.line += 1
self.line_pos = self.cursor
elif not self.tok.isspace():
raise KconfigParserError(self, 'invalid input')
return None
if __name__ == '__main__':
argv = sys.argv
mode = defconfig
if len(sys.argv) > 1:
if argv[1] == '--defconfig':
del argv[1]
elif argv[1] == '--randconfig':
random.seed()
mode = randconfig
del argv[1]
elif argv[1] == '--allyesconfig':
mode = allyesconfig
del argv[1]
elif argv[1] == '--allnoconfig':
mode = allnoconfig
del argv[1]
if len(argv) == 1:
print ("%s: at least one argument is required" % argv[0], file=sys.stderr)
sys.exit(1)
if argv[1].startswith('-'):
print ("%s: invalid option %s" % (argv[0], argv[1]), file=sys.stderr)
sys.exit(1)
data = KconfigData(mode)
parser = KconfigParser(data)
external_vars = set()
for arg in argv[3:]:
m = re.match(r'^(CONFIG_[A-Z0-9_]+)=([yn]?)$', arg)
if m is not None:
name, value = m.groups()
parser.do_assignment(name, value == 'y')
external_vars.add(name[7:])
else:
fp = open(arg, 'rt', encoding='utf-8')
parser.parse_file(fp)
fp.close()
config = data.compute_config()
for key in sorted(config.keys()):
if key not in external_vars and config[key]:
print ('CONFIG_%s=y' % key)
deps = open(argv[2], 'wt', encoding='utf-8')
for fname in data.previously_included:
print ('%s: %s' % (argv[1], fname), file=deps)
deps.close()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/minikconf.py
|
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
import os
import sys
import json
import shlex
import subprocess
def find_command(src, target, compile_commands):
for command in compile_commands:
if command['file'] != src:
continue
if target != '' and command['command'].find(target) == -1:
continue
return command['command']
return 'false'
def process_command(src, command):
skip = False
arg = False
out = []
for item in shlex.split(command):
if arg:
out.append(x)
arg = False
continue
if skip:
skip = False
continue
if item == '-MF' or item == '-MQ' or item == '-o':
skip = True
continue
if item == '-c':
skip = True
continue
out.append(item)
out.append('-DQEMU_MODINFO')
out.append('-E')
out.append(src)
return out
def main(args):
target = ''
if args[0] == '--target':
args.pop(0)
target = args.pop(0)
print("MODINFO_DEBUG target %s" % target)
arch = target[:-8] # cut '-softmmu'
print("MODINFO_START arch \"%s\" MODINFO_END" % arch)
with open('compile_commands.json') as f:
compile_commands = json.load(f)
for src in args:
print("MODINFO_DEBUG src %s" % src)
command = find_command(src, target, compile_commands)
cmdline = process_command(src, command)
print("MODINFO_DEBUG cmd", cmdline)
result = subprocess.run(cmdline, stdout = subprocess.PIPE,
universal_newlines = True)
if result.returncode != 0:
sys.exit(result.returncode)
for line in result.stdout.split('\n'):
if line.find('MODINFO') != -1:
print(line)
if __name__ == "__main__":
main(sys.argv[1:])
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/modinfo-collect.py
|
"""
This python script adds a new gdb command, "dump-guest-memory". It
should be loaded with "source dump-guest-memory.py" at the (gdb)
prompt.
Copyright (C) 2013, Red Hat, Inc.
Authors:
Laszlo Ersek <lersek@redhat.com>
Janosch Frank <frankja@linux.vnet.ibm.com>
This work is licensed under the terms of the GNU GPL, version 2 or later. See
the COPYING file in the top-level directory.
"""
import ctypes
import struct
try:
UINTPTR_T = gdb.lookup_type("uintptr_t")
except Exception as inst:
raise gdb.GdbError("Symbols must be loaded prior to sourcing dump-guest-memory.\n"
"Symbols may be loaded by 'attach'ing a QEMU process id or by "
"'load'ing a QEMU binary.")
TARGET_PAGE_SIZE = 0x1000
TARGET_PAGE_MASK = 0xFFFFFFFFFFFFF000
# Special value for e_phnum. This indicates that the real number of
# program headers is too large to fit into e_phnum. Instead the real
# value is in the field sh_info of section 0.
PN_XNUM = 0xFFFF
EV_CURRENT = 1
ELFCLASS32 = 1
ELFCLASS64 = 2
ELFDATA2LSB = 1
ELFDATA2MSB = 2
ET_CORE = 4
PT_LOAD = 1
PT_NOTE = 4
EM_386 = 3
EM_PPC = 20
EM_PPC64 = 21
EM_S390 = 22
EM_AARCH = 183
EM_X86_64 = 62
VMCOREINFO_FORMAT_ELF = 1
def le16_to_cpu(val):
return struct.unpack("<H", struct.pack("=H", val))[0]
def le32_to_cpu(val):
return struct.unpack("<I", struct.pack("=I", val))[0]
def le64_to_cpu(val):
return struct.unpack("<Q", struct.pack("=Q", val))[0]
class ELF(object):
"""Representation of a ELF file."""
def __init__(self, arch):
self.ehdr = None
self.notes = []
self.segments = []
self.notes_size = 0
self.endianness = None
self.elfclass = ELFCLASS64
if arch == 'aarch64-le':
self.endianness = ELFDATA2LSB
self.elfclass = ELFCLASS64
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_AARCH
elif arch == 'aarch64-be':
self.endianness = ELFDATA2MSB
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_AARCH
elif arch == 'X86_64':
self.endianness = ELFDATA2LSB
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_X86_64
elif arch == '386':
self.endianness = ELFDATA2LSB
self.elfclass = ELFCLASS32
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_386
elif arch == 's390':
self.endianness = ELFDATA2MSB
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_S390
elif arch == 'ppc64-le':
self.endianness = ELFDATA2LSB
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_PPC64
elif arch == 'ppc64-be':
self.endianness = ELFDATA2MSB
self.ehdr = get_arch_ehdr(self.endianness, self.elfclass)
self.ehdr.e_machine = EM_PPC64
else:
raise gdb.GdbError("No valid arch type specified.\n"
"Currently supported types:\n"
"aarch64-be, aarch64-le, X86_64, 386, s390, "
"ppc64-be, ppc64-le")
self.add_segment(PT_NOTE, 0, 0)
def add_note(self, n_name, n_desc, n_type):
"""Adds a note to the ELF."""
note = get_arch_note(self.endianness, len(n_name), len(n_desc))
note.n_namesz = len(n_name) + 1
note.n_descsz = len(n_desc)
note.n_name = n_name.encode()
note.n_type = n_type
# Desc needs to be 4 byte aligned (although the 64bit spec
# specifies 8 byte). When defining n_desc as uint32 it will be
# automatically aligned but we need the memmove to copy the
# string into it.
ctypes.memmove(note.n_desc, n_desc.encode(), len(n_desc))
self.notes.append(note)
self.segments[0].p_filesz += ctypes.sizeof(note)
self.segments[0].p_memsz += ctypes.sizeof(note)
def add_vmcoreinfo_note(self, vmcoreinfo):
"""Adds a vmcoreinfo note to the ELF dump."""
# compute the header size, and copy that many bytes from the note
header = get_arch_note(self.endianness, 0, 0)
ctypes.memmove(ctypes.pointer(header),
vmcoreinfo, ctypes.sizeof(header))
if header.n_descsz > 1 << 20:
print('warning: invalid vmcoreinfo size')
return
# now get the full note
note = get_arch_note(self.endianness,
header.n_namesz - 1, header.n_descsz)
ctypes.memmove(ctypes.pointer(note), vmcoreinfo, ctypes.sizeof(note))
self.notes.append(note)
self.segments[0].p_filesz += ctypes.sizeof(note)
self.segments[0].p_memsz += ctypes.sizeof(note)
def add_segment(self, p_type, p_paddr, p_size):
"""Adds a segment to the elf."""
phdr = get_arch_phdr(self.endianness, self.elfclass)
phdr.p_type = p_type
phdr.p_paddr = p_paddr
phdr.p_vaddr = p_paddr
phdr.p_filesz = p_size
phdr.p_memsz = p_size
self.segments.append(phdr)
self.ehdr.e_phnum += 1
def to_file(self, elf_file):
"""Writes all ELF structures to the passed file.
Structure:
Ehdr
Segment 0:PT_NOTE
Segment 1:PT_LOAD
Segment N:PT_LOAD
Note 0..N
Dump contents
"""
elf_file.write(self.ehdr)
off = ctypes.sizeof(self.ehdr) + \
len(self.segments) * ctypes.sizeof(self.segments[0])
for phdr in self.segments:
phdr.p_offset = off
elf_file.write(phdr)
off += phdr.p_filesz
for note in self.notes:
elf_file.write(note)
def get_arch_note(endianness, len_name, len_desc):
"""Returns a Note class with the specified endianness."""
if endianness == ELFDATA2LSB:
superclass = ctypes.LittleEndianStructure
else:
superclass = ctypes.BigEndianStructure
len_name = len_name + 1
class Note(superclass):
"""Represents an ELF note, includes the content."""
_fields_ = [("n_namesz", ctypes.c_uint32),
("n_descsz", ctypes.c_uint32),
("n_type", ctypes.c_uint32),
("n_name", ctypes.c_char * len_name),
("n_desc", ctypes.c_uint32 * ((len_desc + 3) // 4))]
return Note()
class Ident(ctypes.Structure):
"""Represents the ELF ident array in the ehdr structure."""
_fields_ = [('ei_mag0', ctypes.c_ubyte),
('ei_mag1', ctypes.c_ubyte),
('ei_mag2', ctypes.c_ubyte),
('ei_mag3', ctypes.c_ubyte),
('ei_class', ctypes.c_ubyte),
('ei_data', ctypes.c_ubyte),
('ei_version', ctypes.c_ubyte),
('ei_osabi', ctypes.c_ubyte),
('ei_abiversion', ctypes.c_ubyte),
('ei_pad', ctypes.c_ubyte * 7)]
def __init__(self, endianness, elfclass):
self.ei_mag0 = 0x7F
self.ei_mag1 = ord('E')
self.ei_mag2 = ord('L')
self.ei_mag3 = ord('F')
self.ei_class = elfclass
self.ei_data = endianness
self.ei_version = EV_CURRENT
def get_arch_ehdr(endianness, elfclass):
"""Returns a EHDR64 class with the specified endianness."""
if endianness == ELFDATA2LSB:
superclass = ctypes.LittleEndianStructure
else:
superclass = ctypes.BigEndianStructure
class EHDR64(superclass):
"""Represents the 64 bit ELF header struct."""
_fields_ = [('e_ident', Ident),
('e_type', ctypes.c_uint16),
('e_machine', ctypes.c_uint16),
('e_version', ctypes.c_uint32),
('e_entry', ctypes.c_uint64),
('e_phoff', ctypes.c_uint64),
('e_shoff', ctypes.c_uint64),
('e_flags', ctypes.c_uint32),
('e_ehsize', ctypes.c_uint16),
('e_phentsize', ctypes.c_uint16),
('e_phnum', ctypes.c_uint16),
('e_shentsize', ctypes.c_uint16),
('e_shnum', ctypes.c_uint16),
('e_shstrndx', ctypes.c_uint16)]
def __init__(self):
super(superclass, self).__init__()
self.e_ident = Ident(endianness, elfclass)
self.e_type = ET_CORE
self.e_version = EV_CURRENT
self.e_ehsize = ctypes.sizeof(self)
self.e_phoff = ctypes.sizeof(self)
self.e_phentsize = ctypes.sizeof(get_arch_phdr(endianness, elfclass))
self.e_phnum = 0
class EHDR32(superclass):
"""Represents the 32 bit ELF header struct."""
_fields_ = [('e_ident', Ident),
('e_type', ctypes.c_uint16),
('e_machine', ctypes.c_uint16),
('e_version', ctypes.c_uint32),
('e_entry', ctypes.c_uint32),
('e_phoff', ctypes.c_uint32),
('e_shoff', ctypes.c_uint32),
('e_flags', ctypes.c_uint32),
('e_ehsize', ctypes.c_uint16),
('e_phentsize', ctypes.c_uint16),
('e_phnum', ctypes.c_uint16),
('e_shentsize', ctypes.c_uint16),
('e_shnum', ctypes.c_uint16),
('e_shstrndx', ctypes.c_uint16)]
def __init__(self):
super(superclass, self).__init__()
self.e_ident = Ident(endianness, elfclass)
self.e_type = ET_CORE
self.e_version = EV_CURRENT
self.e_ehsize = ctypes.sizeof(self)
self.e_phoff = ctypes.sizeof(self)
self.e_phentsize = ctypes.sizeof(get_arch_phdr(endianness, elfclass))
self.e_phnum = 0
# End get_arch_ehdr
if elfclass == ELFCLASS64:
return EHDR64()
else:
return EHDR32()
def get_arch_phdr(endianness, elfclass):
"""Returns a 32 or 64 bit PHDR class with the specified endianness."""
if endianness == ELFDATA2LSB:
superclass = ctypes.LittleEndianStructure
else:
superclass = ctypes.BigEndianStructure
class PHDR64(superclass):
"""Represents the 64 bit ELF program header struct."""
_fields_ = [('p_type', ctypes.c_uint32),
('p_flags', ctypes.c_uint32),
('p_offset', ctypes.c_uint64),
('p_vaddr', ctypes.c_uint64),
('p_paddr', ctypes.c_uint64),
('p_filesz', ctypes.c_uint64),
('p_memsz', ctypes.c_uint64),
('p_align', ctypes.c_uint64)]
class PHDR32(superclass):
"""Represents the 32 bit ELF program header struct."""
_fields_ = [('p_type', ctypes.c_uint32),
('p_offset', ctypes.c_uint32),
('p_vaddr', ctypes.c_uint32),
('p_paddr', ctypes.c_uint32),
('p_filesz', ctypes.c_uint32),
('p_memsz', ctypes.c_uint32),
('p_flags', ctypes.c_uint32),
('p_align', ctypes.c_uint32)]
# End get_arch_phdr
if elfclass == ELFCLASS64:
return PHDR64()
else:
return PHDR32()
def int128_get64(val):
"""Returns low 64bit part of Int128 struct."""
try:
assert val["hi"] == 0
return val["lo"]
except gdb.error:
u64t = gdb.lookup_type('uint64_t').array(2)
u64 = val.cast(u64t)
if sys.byteorder == 'little':
assert u64[1] == 0
return u64[0]
else:
assert u64[0] == 0
return u64[1]
def qlist_foreach(head, field_str):
"""Generator for qlists."""
var_p = head["lh_first"]
while var_p != 0:
var = var_p.dereference()
var_p = var[field_str]["le_next"]
yield var
def qemu_map_ram_ptr(block, offset):
"""Returns qemu vaddr for given guest physical address."""
return block["host"] + offset
def memory_region_get_ram_ptr(memory_region):
if memory_region["alias"] != 0:
return (memory_region_get_ram_ptr(memory_region["alias"].dereference())
+ memory_region["alias_offset"])
return qemu_map_ram_ptr(memory_region["ram_block"], 0)
def get_guest_phys_blocks():
"""Returns a list of ram blocks.
Each block entry contains:
'target_start': guest block phys start address
'target_end': guest block phys end address
'host_addr': qemu vaddr of the block's start
"""
guest_phys_blocks = []
print("guest RAM blocks:")
print("target_start target_end host_addr message "
"count")
print("---------------- ---------------- ---------------- ------- "
"-----")
current_map_p = gdb.parse_and_eval("address_space_memory.current_map")
current_map = current_map_p.dereference()
# Conversion to int is needed for python 3
# compatibility. Otherwise range doesn't cast the value itself and
# breaks.
for cur in range(int(current_map["nr"])):
flat_range = (current_map["ranges"] + cur).dereference()
memory_region = flat_range["mr"].dereference()
# we only care about RAM
if (not memory_region["ram"] or
memory_region["ram_device"] or
memory_region["nonvolatile"]):
continue
section_size = int128_get64(flat_range["addr"]["size"])
target_start = int128_get64(flat_range["addr"]["start"])
target_end = target_start + section_size
host_addr = (memory_region_get_ram_ptr(memory_region)
+ flat_range["offset_in_region"])
predecessor = None
# find continuity in guest physical address space
if len(guest_phys_blocks) > 0:
predecessor = guest_phys_blocks[-1]
predecessor_size = (predecessor["target_end"] -
predecessor["target_start"])
# the memory API guarantees monotonically increasing
# traversal
assert predecessor["target_end"] <= target_start
# we want continuity in both guest-physical and
# host-virtual memory
if (predecessor["target_end"] < target_start or
predecessor["host_addr"] + predecessor_size != host_addr):
predecessor = None
if predecessor is None:
# isolated mapping, add it to the list
guest_phys_blocks.append({"target_start": target_start,
"target_end": target_end,
"host_addr": host_addr})
message = "added"
else:
# expand predecessor until @target_end; predecessor's
# start doesn't change
predecessor["target_end"] = target_end
message = "joined"
print("%016x %016x %016x %-7s %5u" %
(target_start, target_end, host_addr.cast(UINTPTR_T),
message, len(guest_phys_blocks)))
return guest_phys_blocks
# The leading docstring doesn't have idiomatic Python formatting. It is
# printed by gdb's "help" command (the first line is printed in the
# "help data" summary), and it should match how other help texts look in
# gdb.
class DumpGuestMemory(gdb.Command):
"""Extract guest vmcore from qemu process coredump.
The two required arguments are FILE and ARCH:
FILE identifies the target file to write the guest vmcore to.
ARCH specifies the architecture for which the core will be generated.
This GDB command reimplements the dump-guest-memory QMP command in
python, using the representation of guest memory as captured in the qemu
coredump. The qemu process that has been dumped must have had the
command line option "-machine dump-guest-core=on" which is the default.
For simplicity, the "paging", "begin" and "end" parameters of the QMP
command are not supported -- no attempt is made to get the guest's
internal paging structures (ie. paging=false is hard-wired), and guest
memory is always fully dumped.
Currently aarch64-be, aarch64-le, X86_64, 386, s390, ppc64-be,
ppc64-le guests are supported.
The CORE/NT_PRSTATUS and QEMU notes (that is, the VCPUs' statuses) are
not written to the vmcore. Preparing these would require context that is
only present in the KVM host kernel module when the guest is alive. A
fake ELF note is written instead, only to keep the ELF parser of "crash"
happy.
Dependent on how busted the qemu process was at the time of the
coredump, this command might produce unpredictable results. If qemu
deliberately called abort(), or it was dumped in response to a signal at
a halfway fortunate point, then its coredump should be in reasonable
shape and this command should mostly work."""
def __init__(self):
super(DumpGuestMemory, self).__init__("dump-guest-memory",
gdb.COMMAND_DATA,
gdb.COMPLETE_FILENAME)
self.elf = None
self.guest_phys_blocks = None
def dump_init(self, vmcore):
"""Prepares and writes ELF structures to core file."""
# Needed to make crash happy, data for more useful notes is
# not available in a qemu core.
self.elf.add_note("NONE", "EMPTY", 0)
# We should never reach PN_XNUM for paging=false dumps,
# there's just a handful of discontiguous ranges after
# merging.
# The constant is needed to account for the PT_NOTE segment.
phdr_num = len(self.guest_phys_blocks) + 1
assert phdr_num < PN_XNUM
for block in self.guest_phys_blocks:
block_size = block["target_end"] - block["target_start"]
self.elf.add_segment(PT_LOAD, block["target_start"], block_size)
self.elf.to_file(vmcore)
def dump_iterate(self, vmcore):
"""Writes guest core to file."""
qemu_core = gdb.inferiors()[0]
for block in self.guest_phys_blocks:
cur = block["host_addr"]
left = block["target_end"] - block["target_start"]
print("dumping range at %016x for length %016x" %
(cur.cast(UINTPTR_T), left))
while left > 0:
chunk_size = min(TARGET_PAGE_SIZE, left)
chunk = qemu_core.read_memory(cur, chunk_size)
vmcore.write(chunk)
cur += chunk_size
left -= chunk_size
def phys_memory_read(self, addr, size):
qemu_core = gdb.inferiors()[0]
for block in self.guest_phys_blocks:
if block["target_start"] <= addr \
and addr + size <= block["target_end"]:
haddr = block["host_addr"] + (addr - block["target_start"])
return qemu_core.read_memory(haddr, size)
return None
def add_vmcoreinfo(self):
if gdb.lookup_symbol("vmcoreinfo_realize")[0] is None:
return
vmci = 'vmcoreinfo_realize::vmcoreinfo_state'
if not gdb.parse_and_eval("%s" % vmci) \
or not gdb.parse_and_eval("(%s)->has_vmcoreinfo" % vmci):
return
fmt = gdb.parse_and_eval("(%s)->vmcoreinfo.guest_format" % vmci)
addr = gdb.parse_and_eval("(%s)->vmcoreinfo.paddr" % vmci)
size = gdb.parse_and_eval("(%s)->vmcoreinfo.size" % vmci)
fmt = le16_to_cpu(fmt)
addr = le64_to_cpu(addr)
size = le32_to_cpu(size)
if fmt != VMCOREINFO_FORMAT_ELF:
return
vmcoreinfo = self.phys_memory_read(addr, size)
if vmcoreinfo:
self.elf.add_vmcoreinfo_note(bytes(vmcoreinfo))
def invoke(self, args, from_tty):
"""Handles command invocation from gdb."""
# Unwittingly pressing the Enter key after the command should
# not dump the same multi-gig coredump to the same file.
self.dont_repeat()
argv = gdb.string_to_argv(args)
if len(argv) != 2:
raise gdb.GdbError("usage: dump-guest-memory FILE ARCH")
self.elf = ELF(argv[1])
self.guest_phys_blocks = get_guest_phys_blocks()
self.add_vmcoreinfo()
with open(argv[0], "wb") as vmcore:
self.dump_init(vmcore)
self.dump_iterate(vmcore)
DumpGuestMemory()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/dump-guest-memory.py
|
#!/usr/bin/env python3
# Pretty print 9p simpletrace log
# Usage: ./analyse-9p-simpletrace <trace-events> <trace-pid>
#
# Author: Harsh Prateek Bora
import os
import simpletrace
symbol_9p = {
6 : 'TLERROR',
7 : 'RLERROR',
8 : 'TSTATFS',
9 : 'RSTATFS',
12 : 'TLOPEN',
13 : 'RLOPEN',
14 : 'TLCREATE',
15 : 'RLCREATE',
16 : 'TSYMLINK',
17 : 'RSYMLINK',
18 : 'TMKNOD',
19 : 'RMKNOD',
20 : 'TRENAME',
21 : 'RRENAME',
22 : 'TREADLINK',
23 : 'RREADLINK',
24 : 'TGETATTR',
25 : 'RGETATTR',
26 : 'TSETATTR',
27 : 'RSETATTR',
30 : 'TXATTRWALK',
31 : 'RXATTRWALK',
32 : 'TXATTRCREATE',
33 : 'RXATTRCREATE',
40 : 'TREADDIR',
41 : 'RREADDIR',
50 : 'TFSYNC',
51 : 'RFSYNC',
52 : 'TLOCK',
53 : 'RLOCK',
54 : 'TGETLOCK',
55 : 'RGETLOCK',
70 : 'TLINK',
71 : 'RLINK',
72 : 'TMKDIR',
73 : 'RMKDIR',
74 : 'TRENAMEAT',
75 : 'RRENAMEAT',
76 : 'TUNLINKAT',
77 : 'RUNLINKAT',
100 : 'TVERSION',
101 : 'RVERSION',
102 : 'TAUTH',
103 : 'RAUTH',
104 : 'TATTACH',
105 : 'RATTACH',
106 : 'TERROR',
107 : 'RERROR',
108 : 'TFLUSH',
109 : 'RFLUSH',
110 : 'TWALK',
111 : 'RWALK',
112 : 'TOPEN',
113 : 'ROPEN',
114 : 'TCREATE',
115 : 'RCREATE',
116 : 'TREAD',
117 : 'RREAD',
118 : 'TWRITE',
119 : 'RWRITE',
120 : 'TCLUNK',
121 : 'RCLUNK',
122 : 'TREMOVE',
123 : 'RREMOVE',
124 : 'TSTAT',
125 : 'RSTAT',
126 : 'TWSTAT',
127 : 'RWSTAT'
}
class VirtFSRequestTracker(simpletrace.Analyzer):
def begin(self):
print("Pretty printing 9p simpletrace log ...")
def v9fs_rerror(self, tag, id, err):
print("RERROR (tag =", tag, ", id =", symbol_9p[id], ", err = \"", os.strerror(err), "\")")
def v9fs_version(self, tag, id, msize, version):
print("TVERSION (tag =", tag, ", msize =", msize, ", version =", version, ")")
def v9fs_version_return(self, tag, id, msize, version):
print("RVERSION (tag =", tag, ", msize =", msize, ", version =", version, ")")
def v9fs_attach(self, tag, id, fid, afid, uname, aname):
print("TATTACH (tag =", tag, ", fid =", fid, ", afid =", afid, ", uname =", uname, ", aname =", aname, ")")
def v9fs_attach_return(self, tag, id, type, version, path):
print("RATTACH (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "})")
def v9fs_stat(self, tag, id, fid):
print("TSTAT (tag =", tag, ", fid =", fid, ")")
def v9fs_stat_return(self, tag, id, mode, atime, mtime, length):
print("RSTAT (tag =", tag, ", mode =", mode, ", atime =", atime, ", mtime =", mtime, ", length =", length, ")")
def v9fs_getattr(self, tag, id, fid, request_mask):
print("TGETATTR (tag =", tag, ", fid =", fid, ", request_mask =", hex(request_mask), ")")
def v9fs_getattr_return(self, tag, id, result_mask, mode, uid, gid):
print("RGETATTR (tag =", tag, ", result_mask =", hex(result_mask), ", mode =", oct(mode), ", uid =", uid, ", gid =", gid, ")")
def v9fs_walk(self, tag, id, fid, newfid, nwnames):
print("TWALK (tag =", tag, ", fid =", fid, ", newfid =", newfid, ", nwnames =", nwnames, ")")
def v9fs_walk_return(self, tag, id, nwnames, qids):
print("RWALK (tag =", tag, ", nwnames =", nwnames, ", qids =", hex(qids), ")")
def v9fs_open(self, tag, id, fid, mode):
print("TOPEN (tag =", tag, ", fid =", fid, ", mode =", oct(mode), ")")
def v9fs_open_return(self, tag, id, type, version, path, iounit):
print("ROPEN (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "}, iounit =", iounit, ")")
def v9fs_lcreate(self, tag, id, dfid, flags, mode, gid):
print("TLCREATE (tag =", tag, ", dfid =", dfid, ", flags =", oct(flags), ", mode =", oct(mode), ", gid =", gid, ")")
def v9fs_lcreate_return(self, tag, id, type, version, path, iounit):
print("RLCREATE (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "}, iounit =", iounit, ")")
def v9fs_fsync(self, tag, id, fid, datasync):
print("TFSYNC (tag =", tag, ", fid =", fid, ", datasync =", datasync, ")")
def v9fs_clunk(self, tag, id, fid):
print("TCLUNK (tag =", tag, ", fid =", fid, ")")
def v9fs_read(self, tag, id, fid, off, max_count):
print("TREAD (tag =", tag, ", fid =", fid, ", off =", off, ", max_count =", max_count, ")")
def v9fs_read_return(self, tag, id, count, err):
print("RREAD (tag =", tag, ", count =", count, ", err =", err, ")")
def v9fs_readdir(self, tag, id, fid, offset, max_count):
print("TREADDIR (tag =", tag, ", fid =", fid, ", offset =", offset, ", max_count =", max_count, ")")
def v9fs_readdir_return(self, tag, id, count, retval):
print("RREADDIR (tag =", tag, ", count =", count, ", retval =", retval, ")")
def v9fs_write(self, tag, id, fid, off, count, cnt):
print("TWRITE (tag =", tag, ", fid =", fid, ", off =", off, ", count =", count, ", cnt =", cnt, ")")
def v9fs_write_return(self, tag, id, total, err):
print("RWRITE (tag =", tag, ", total =", total, ", err =", err, ")")
def v9fs_create(self, tag, id, fid, name, perm, mode):
print("TCREATE (tag =", tag, ", fid =", fid, ", perm =", oct(perm), ", name =", name, ", mode =", oct(mode), ")")
def v9fs_create_return(self, tag, id, type, version, path, iounit):
print("RCREATE (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "}, iounit =", iounit, ")")
def v9fs_symlink(self, tag, id, fid, name, symname, gid):
print("TSYMLINK (tag =", tag, ", fid =", fid, ", name =", name, ", symname =", symname, ", gid =", gid, ")")
def v9fs_symlink_return(self, tag, id, type, version, path):
print("RSYMLINK (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "})")
def v9fs_flush(self, tag, id, flush_tag):
print("TFLUSH (tag =", tag, ", flush_tag =", flush_tag, ")")
def v9fs_link(self, tag, id, dfid, oldfid, name):
print("TLINK (tag =", tag, ", dfid =", dfid, ", oldfid =", oldfid, ", name =", name, ")")
def v9fs_remove(self, tag, id, fid):
print("TREMOVE (tag =", tag, ", fid =", fid, ")")
def v9fs_wstat(self, tag, id, fid, mode, atime, mtime):
print("TWSTAT (tag =", tag, ", fid =", fid, ", mode =", oct(mode), ", atime =", atime, "mtime =", mtime, ")")
def v9fs_mknod(self, tag, id, fid, mode, major, minor):
print("TMKNOD (tag =", tag, ", fid =", fid, ", mode =", oct(mode), ", major =", major, ", minor =", minor, ")")
def v9fs_lock(self, tag, id, fid, type, start, length):
print("TLOCK (tag =", tag, ", fid =", fid, "type =", type, ", start =", start, ", length =", length, ")")
def v9fs_lock_return(self, tag, id, status):
print("RLOCK (tag =", tag, ", status =", status, ")")
def v9fs_getlock(self, tag, id, fid, type, start, length):
print("TGETLOCK (tag =", tag, ", fid =", fid, "type =", type, ", start =", start, ", length =", length, ")")
def v9fs_getlock_return(self, tag, id, type, start, length, proc_id):
print("RGETLOCK (tag =", tag, "type =", type, ", start =", start, ", length =", length, ", proc_id =", proc_id, ")")
def v9fs_mkdir(self, tag, id, fid, name, mode, gid):
print("TMKDIR (tag =", tag, ", fid =", fid, ", name =", name, ", mode =", mode, ", gid =", gid, ")")
def v9fs_mkdir_return(self, tag, id, type, version, path, err):
print("RMKDIR (tag =", tag, ", qid={type =", type, ", version =", version, ", path =", path, "}, err =", err, ")")
def v9fs_xattrwalk(self, tag, id, fid, newfid, name):
print("TXATTRWALK (tag =", tag, ", fid =", fid, ", newfid =", newfid, ", xattr name =", name, ")")
def v9fs_xattrwalk_return(self, tag, id, size):
print("RXATTRWALK (tag =", tag, ", xattrsize =", size, ")")
def v9fs_xattrcreate(self, tag, id, fid, name, size, flags):
print("TXATTRCREATE (tag =", tag, ", fid =", fid, ", name =", name, ", xattrsize =", size, ", flags =", flags, ")")
def v9fs_readlink(self, tag, id, fid):
print("TREADLINK (tag =", tag, ", fid =", fid, ")")
def v9fs_readlink_return(self, tag, id, target):
print("RREADLINK (tag =", tag, ", target =", target, ")")
simpletrace.run(VirtFSRequestTracker())
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/analyse-9p-simpletrace.py
|
#!/usr/bin/env python3
# Before a shared module's DSO is produced, a static library is built for it
# and passed to this script. The script generates -Wl,-u options to force
# the inclusion of symbol from libqemuutil.a if the shared modules need them,
# This is necessary because the modules may use functions not needed by the
# executable itself, which would cause the function to not be linked in.
# Then the DSO loading would fail because of the missing symbol.
import sys
import subprocess
def filter_lines_set(stdout, from_staticlib):
linesSet = set()
for line in stdout.splitlines():
tokens = line.split(b' ')
if len(tokens) >= 2:
if from_staticlib and tokens[1] == b'U':
continue
if not from_staticlib and tokens[1] != b'U':
continue
new_line = b'-Wl,-u,' + tokens[0]
if not new_line in linesSet:
linesSet.add(new_line)
return linesSet
def main(args):
if len(args) <= 3:
sys.exit(0)
nm = args[1]
staticlib = args[2]
pc = subprocess.run([nm, "-P", "-g", staticlib], stdout=subprocess.PIPE)
if pc.returncode != 0:
sys.exit(1)
staticlib_syms = filter_lines_set(pc.stdout, True)
shared_modules = args[3:]
pc = subprocess.run([nm, "-P", "-g"] + shared_modules, stdout=subprocess.PIPE)
if pc.returncode != 0:
sys.exit(1)
modules_undef_syms = filter_lines_set(pc.stdout, False)
lines = sorted(staticlib_syms.intersection(modules_undef_syms))
sys.stdout.buffer.write(b'\n'.join(lines))
if __name__ == "__main__":
main(sys.argv)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/undefsym.py
|
#!/usr/bin/env python3
#
# Migration Stream Analyzer
#
# Copyright (c) 2015 Alexander Graf <agraf@suse.de>
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
import json
import os
import argparse
import collections
import struct
import sys
def mkdir_p(path):
try:
os.makedirs(path)
except OSError:
pass
class MigrationFile(object):
def __init__(self, filename):
self.filename = filename
self.file = open(self.filename, "rb")
def read64(self):
return int.from_bytes(self.file.read(8), byteorder='big', signed=True)
def read32(self):
return int.from_bytes(self.file.read(4), byteorder='big', signed=True)
def read16(self):
return int.from_bytes(self.file.read(2), byteorder='big', signed=True)
def read8(self):
return int.from_bytes(self.file.read(1), byteorder='big', signed=True)
def readstr(self, len = None):
return self.readvar(len).decode('utf-8')
def readvar(self, size = None):
if size is None:
size = self.read8()
if size == 0:
return ""
value = self.file.read(size)
if len(value) != size:
raise Exception("Unexpected end of %s at 0x%x" % (self.filename, self.file.tell()))
return value
def tell(self):
return self.file.tell()
# The VMSD description is at the end of the file, after EOF. Look for
# the last NULL byte, then for the beginning brace of JSON.
def read_migration_debug_json(self):
QEMU_VM_VMDESCRIPTION = 0x06
# Remember the offset in the file when we started
entrypos = self.file.tell()
# Read the last 10MB
self.file.seek(0, os.SEEK_END)
endpos = self.file.tell()
self.file.seek(max(-endpos, -10 * 1024 * 1024), os.SEEK_END)
datapos = self.file.tell()
data = self.file.read()
# The full file read closed the file as well, reopen it
self.file = open(self.filename, "rb")
# Find the last NULL byte, then the first brace after that. This should
# be the beginning of our JSON data.
nulpos = data.rfind(b'\0')
jsonpos = data.find(b'{', nulpos)
# Check backwards from there and see whether we guessed right
self.file.seek(datapos + jsonpos - 5, 0)
if self.read8() != QEMU_VM_VMDESCRIPTION:
raise Exception("No Debug Migration device found")
jsonlen = self.read32()
# Seek back to where we were at the beginning
self.file.seek(entrypos, 0)
# explicit decode() needed for Python 3.5 compatibility
return data[jsonpos:jsonpos + jsonlen].decode("utf-8")
def close(self):
self.file.close()
class RamSection(object):
RAM_SAVE_FLAG_COMPRESS = 0x02
RAM_SAVE_FLAG_MEM_SIZE = 0x04
RAM_SAVE_FLAG_PAGE = 0x08
RAM_SAVE_FLAG_EOS = 0x10
RAM_SAVE_FLAG_CONTINUE = 0x20
RAM_SAVE_FLAG_XBZRLE = 0x40
RAM_SAVE_FLAG_HOOK = 0x80
def __init__(self, file, version_id, ramargs, section_key):
if version_id != 4:
raise Exception("Unknown RAM version %d" % version_id)
self.file = file
self.section_key = section_key
self.TARGET_PAGE_SIZE = ramargs['page_size']
self.dump_memory = ramargs['dump_memory']
self.write_memory = ramargs['write_memory']
self.sizeinfo = collections.OrderedDict()
self.data = collections.OrderedDict()
self.data['section sizes'] = self.sizeinfo
self.name = ''
if self.write_memory:
self.files = { }
if self.dump_memory:
self.memory = collections.OrderedDict()
self.data['memory'] = self.memory
def __repr__(self):
return self.data.__repr__()
def __str__(self):
return self.data.__str__()
def getDict(self):
return self.data
def read(self):
# Read all RAM sections
while True:
addr = self.file.read64()
flags = addr & (self.TARGET_PAGE_SIZE - 1)
addr &= ~(self.TARGET_PAGE_SIZE - 1)
if flags & self.RAM_SAVE_FLAG_MEM_SIZE:
while True:
namelen = self.file.read8()
# We assume that no RAM chunk is big enough to ever
# hit the first byte of the address, so when we see
# a zero here we know it has to be an address, not the
# length of the next block.
if namelen == 0:
self.file.file.seek(-1, 1)
break
self.name = self.file.readstr(len = namelen)
len = self.file.read64()
self.sizeinfo[self.name] = '0x%016x' % len
if self.write_memory:
print(self.name)
mkdir_p('./' + os.path.dirname(self.name))
f = open('./' + self.name, "wb")
f.truncate(0)
f.truncate(len)
self.files[self.name] = f
flags &= ~self.RAM_SAVE_FLAG_MEM_SIZE
if flags & self.RAM_SAVE_FLAG_COMPRESS:
if flags & self.RAM_SAVE_FLAG_CONTINUE:
flags &= ~self.RAM_SAVE_FLAG_CONTINUE
else:
self.name = self.file.readstr()
fill_char = self.file.read8()
# The page in question is filled with fill_char now
if self.write_memory and fill_char != 0:
self.files[self.name].seek(addr, os.SEEK_SET)
self.files[self.name].write(chr(fill_char) * self.TARGET_PAGE_SIZE)
if self.dump_memory:
self.memory['%s (0x%016x)' % (self.name, addr)] = 'Filled with 0x%02x' % fill_char
flags &= ~self.RAM_SAVE_FLAG_COMPRESS
elif flags & self.RAM_SAVE_FLAG_PAGE:
if flags & self.RAM_SAVE_FLAG_CONTINUE:
flags &= ~self.RAM_SAVE_FLAG_CONTINUE
else:
self.name = self.file.readstr()
if self.write_memory or self.dump_memory:
data = self.file.readvar(size = self.TARGET_PAGE_SIZE)
else: # Just skip RAM data
self.file.file.seek(self.TARGET_PAGE_SIZE, 1)
if self.write_memory:
self.files[self.name].seek(addr, os.SEEK_SET)
self.files[self.name].write(data)
if self.dump_memory:
hexdata = " ".join("{0:02x}".format(ord(c)) for c in data)
self.memory['%s (0x%016x)' % (self.name, addr)] = hexdata
flags &= ~self.RAM_SAVE_FLAG_PAGE
elif flags & self.RAM_SAVE_FLAG_XBZRLE:
raise Exception("XBZRLE RAM compression is not supported yet")
elif flags & self.RAM_SAVE_FLAG_HOOK:
raise Exception("RAM hooks don't make sense with files")
# End of RAM section
if flags & self.RAM_SAVE_FLAG_EOS:
break
if flags != 0:
raise Exception("Unknown RAM flags: %x" % flags)
def __del__(self):
if self.write_memory:
for key in self.files:
self.files[key].close()
class HTABSection(object):
HASH_PTE_SIZE_64 = 16
def __init__(self, file, version_id, device, section_key):
if version_id != 1:
raise Exception("Unknown HTAB version %d" % version_id)
self.file = file
self.section_key = section_key
def read(self):
header = self.file.read32()
if (header == -1):
# "no HPT" encoding
return
if (header > 0):
# First section, just the hash shift
return
# Read until end marker
while True:
index = self.file.read32()
n_valid = self.file.read16()
n_invalid = self.file.read16()
if index == 0 and n_valid == 0 and n_invalid == 0:
break
self.file.readvar(n_valid * self.HASH_PTE_SIZE_64)
def getDict(self):
return ""
class ConfigurationSection(object):
def __init__(self, file):
self.file = file
def read(self):
name_len = self.file.read32()
name = self.file.readstr(len = name_len)
class VMSDFieldGeneric(object):
def __init__(self, desc, file):
self.file = file
self.desc = desc
self.data = ""
def __repr__(self):
return str(self.__str__())
def __str__(self):
return " ".join("{0:02x}".format(c) for c in self.data)
def getDict(self):
return self.__str__()
def read(self):
size = int(self.desc['size'])
self.data = self.file.readvar(size)
return self.data
class VMSDFieldInt(VMSDFieldGeneric):
def __init__(self, desc, file):
super(VMSDFieldInt, self).__init__(desc, file)
self.size = int(desc['size'])
self.format = '0x%%0%dx' % (self.size * 2)
self.sdtype = '>i%d' % self.size
self.udtype = '>u%d' % self.size
def __repr__(self):
if self.data < 0:
return ('%s (%d)' % ((self.format % self.udata), self.data))
else:
return self.format % self.data
def __str__(self):
return self.__repr__()
def getDict(self):
return self.__str__()
def read(self):
super(VMSDFieldInt, self).read()
self.sdata = int.from_bytes(self.data, byteorder='big', signed=True)
self.udata = int.from_bytes(self.data, byteorder='big', signed=False)
self.data = self.sdata
return self.data
class VMSDFieldUInt(VMSDFieldInt):
def __init__(self, desc, file):
super(VMSDFieldUInt, self).__init__(desc, file)
def read(self):
super(VMSDFieldUInt, self).read()
self.data = self.udata
return self.data
class VMSDFieldIntLE(VMSDFieldInt):
def __init__(self, desc, file):
super(VMSDFieldIntLE, self).__init__(desc, file)
self.dtype = '<i%d' % self.size
class VMSDFieldBool(VMSDFieldGeneric):
def __init__(self, desc, file):
super(VMSDFieldBool, self).__init__(desc, file)
def __repr__(self):
return self.data.__repr__()
def __str__(self):
return self.data.__str__()
def getDict(self):
return self.data
def read(self):
super(VMSDFieldBool, self).read()
if self.data[0] == 0:
self.data = False
else:
self.data = True
return self.data
class VMSDFieldStruct(VMSDFieldGeneric):
QEMU_VM_SUBSECTION = 0x05
def __init__(self, desc, file):
super(VMSDFieldStruct, self).__init__(desc, file)
self.data = collections.OrderedDict()
# When we see compressed array elements, unfold them here
new_fields = []
for field in self.desc['struct']['fields']:
if not 'array_len' in field:
new_fields.append(field)
continue
array_len = field.pop('array_len')
field['index'] = 0
new_fields.append(field)
for i in range(1, array_len):
c = field.copy()
c['index'] = i
new_fields.append(c)
self.desc['struct']['fields'] = new_fields
def __repr__(self):
return self.data.__repr__()
def __str__(self):
return self.data.__str__()
def read(self):
for field in self.desc['struct']['fields']:
try:
reader = vmsd_field_readers[field['type']]
except:
reader = VMSDFieldGeneric
field['data'] = reader(field, self.file)
field['data'].read()
if 'index' in field:
if field['name'] not in self.data:
self.data[field['name']] = []
a = self.data[field['name']]
if len(a) != int(field['index']):
raise Exception("internal index of data field unmatched (%d/%d)" % (len(a), int(field['index'])))
a.append(field['data'])
else:
self.data[field['name']] = field['data']
if 'subsections' in self.desc['struct']:
for subsection in self.desc['struct']['subsections']:
if self.file.read8() != self.QEMU_VM_SUBSECTION:
raise Exception("Subsection %s not found at offset %x" % ( subsection['vmsd_name'], self.file.tell()))
name = self.file.readstr()
version_id = self.file.read32()
self.data[name] = VMSDSection(self.file, version_id, subsection, (name, 0))
self.data[name].read()
def getDictItem(self, value):
# Strings would fall into the array category, treat
# them specially
if value.__class__ is ''.__class__:
return value
try:
return self.getDictOrderedDict(value)
except:
try:
return self.getDictArray(value)
except:
try:
return value.getDict()
except:
return value
def getDictArray(self, array):
r = []
for value in array:
r.append(self.getDictItem(value))
return r
def getDictOrderedDict(self, dict):
r = collections.OrderedDict()
for (key, value) in dict.items():
r[key] = self.getDictItem(value)
return r
def getDict(self):
return self.getDictOrderedDict(self.data)
vmsd_field_readers = {
"bool" : VMSDFieldBool,
"int8" : VMSDFieldInt,
"int16" : VMSDFieldInt,
"int32" : VMSDFieldInt,
"int32 equal" : VMSDFieldInt,
"int32 le" : VMSDFieldIntLE,
"int64" : VMSDFieldInt,
"uint8" : VMSDFieldUInt,
"uint16" : VMSDFieldUInt,
"uint32" : VMSDFieldUInt,
"uint32 equal" : VMSDFieldUInt,
"uint64" : VMSDFieldUInt,
"int64 equal" : VMSDFieldInt,
"uint8 equal" : VMSDFieldInt,
"uint16 equal" : VMSDFieldInt,
"float64" : VMSDFieldGeneric,
"timer" : VMSDFieldGeneric,
"buffer" : VMSDFieldGeneric,
"unused_buffer" : VMSDFieldGeneric,
"bitmap" : VMSDFieldGeneric,
"struct" : VMSDFieldStruct,
"unknown" : VMSDFieldGeneric,
}
class VMSDSection(VMSDFieldStruct):
def __init__(self, file, version_id, device, section_key):
self.file = file
self.data = ""
self.vmsd_name = ""
self.section_key = section_key
desc = device
if 'vmsd_name' in device:
self.vmsd_name = device['vmsd_name']
# A section really is nothing but a FieldStruct :)
super(VMSDSection, self).__init__({ 'struct' : desc }, file)
###############################################################################
class MigrationDump(object):
QEMU_VM_FILE_MAGIC = 0x5145564d
QEMU_VM_FILE_VERSION = 0x00000003
QEMU_VM_EOF = 0x00
QEMU_VM_SECTION_START = 0x01
QEMU_VM_SECTION_PART = 0x02
QEMU_VM_SECTION_END = 0x03
QEMU_VM_SECTION_FULL = 0x04
QEMU_VM_SUBSECTION = 0x05
QEMU_VM_VMDESCRIPTION = 0x06
QEMU_VM_CONFIGURATION = 0x07
QEMU_VM_SECTION_FOOTER= 0x7e
def __init__(self, filename):
self.section_classes = { ( 'ram', 0 ) : [ RamSection, None ],
( 'spapr/htab', 0) : ( HTABSection, None ) }
self.filename = filename
self.vmsd_desc = None
def read(self, desc_only = False, dump_memory = False, write_memory = False):
# Read in the whole file
file = MigrationFile(self.filename)
# File magic
data = file.read32()
if data != self.QEMU_VM_FILE_MAGIC:
raise Exception("Invalid file magic %x" % data)
# Version (has to be v3)
data = file.read32()
if data != self.QEMU_VM_FILE_VERSION:
raise Exception("Invalid version number %d" % data)
self.load_vmsd_json(file)
# Read sections
self.sections = collections.OrderedDict()
if desc_only:
return
ramargs = {}
ramargs['page_size'] = self.vmsd_desc['page_size']
ramargs['dump_memory'] = dump_memory
ramargs['write_memory'] = write_memory
self.section_classes[('ram',0)][1] = ramargs
while True:
section_type = file.read8()
if section_type == self.QEMU_VM_EOF:
break
elif section_type == self.QEMU_VM_CONFIGURATION:
section = ConfigurationSection(file)
section.read()
elif section_type == self.QEMU_VM_SECTION_START or section_type == self.QEMU_VM_SECTION_FULL:
section_id = file.read32()
name = file.readstr()
instance_id = file.read32()
version_id = file.read32()
section_key = (name, instance_id)
classdesc = self.section_classes[section_key]
section = classdesc[0](file, version_id, classdesc[1], section_key)
self.sections[section_id] = section
section.read()
elif section_type == self.QEMU_VM_SECTION_PART or section_type == self.QEMU_VM_SECTION_END:
section_id = file.read32()
self.sections[section_id].read()
elif section_type == self.QEMU_VM_SECTION_FOOTER:
read_section_id = file.read32()
if read_section_id != section_id:
raise Exception("Mismatched section footer: %x vs %x" % (read_section_id, section_id))
else:
raise Exception("Unknown section type: %d" % section_type)
file.close()
def load_vmsd_json(self, file):
vmsd_json = file.read_migration_debug_json()
self.vmsd_desc = json.loads(vmsd_json, object_pairs_hook=collections.OrderedDict)
for device in self.vmsd_desc['devices']:
key = (device['name'], device['instance_id'])
value = ( VMSDSection, device )
self.section_classes[key] = value
def getDict(self):
r = collections.OrderedDict()
for (key, value) in self.sections.items():
key = "%s (%d)" % ( value.section_key[0], key )
r[key] = value.getDict()
return r
###############################################################################
class JSONEncoder(json.JSONEncoder):
def default(self, o):
if isinstance(o, VMSDFieldGeneric):
return str(o)
return json.JSONEncoder.default(self, o)
parser = argparse.ArgumentParser()
parser.add_argument("-f", "--file", help='migration dump to read from', required=True)
parser.add_argument("-m", "--memory", help='dump RAM contents as well', action='store_true')
parser.add_argument("-d", "--dump", help='what to dump ("state" or "desc")', default='state')
parser.add_argument("-x", "--extract", help='extract contents into individual files', action='store_true')
args = parser.parse_args()
jsonenc = JSONEncoder(indent=4, separators=(',', ': '))
if args.extract:
dump = MigrationDump(args.file)
dump.read(desc_only = True)
print("desc.json")
f = open("desc.json", "wb")
f.truncate()
f.write(jsonenc.encode(dump.vmsd_desc))
f.close()
dump.read(write_memory = True)
dict = dump.getDict()
print("state.json")
f = open("state.json", "wb")
f.truncate()
f.write(jsonenc.encode(dict))
f.close()
elif args.dump == "state":
dump = MigrationDump(args.file)
dump.read(dump_memory = args.memory)
dict = dump.getDict()
print(jsonenc.encode(dict))
elif args.dump == "desc":
dump = MigrationDump(args.file)
dump.read(desc_only = True)
print(jsonenc.encode(dump.vmsd_desc))
else:
raise Exception("Please specify either -x, -d state or -d dump")
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/analyze-migration.py
|
#!/usr/bin/python3
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# A script to generate a CSV file showing the x86_64 ABI
# compatibility levels for each CPU model.
#
from qemu import qmp
import sys
if len(sys.argv) != 1:
print("syntax: %s QMP-SOCK\n\n" % __file__ +
"Where QMP-SOCK points to a QEMU process such as\n\n" +
" # qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait " +
"-display none -accel kvm", file=sys.stderr)
sys.exit(1)
# Mandatory CPUID features for each microarch ABI level
levels = [
[ # x86-64 baseline
"cmov",
"cx8",
"fpu",
"fxsr",
"mmx",
"syscall",
"sse",
"sse2",
],
[ # x86-64-v2
"cx16",
"lahf-lm",
"popcnt",
"pni",
"sse4.1",
"sse4.2",
"ssse3",
],
[ # x86-64-v3
"avx",
"avx2",
"bmi1",
"bmi2",
"f16c",
"fma",
"abm",
"movbe",
],
[ # x86-64-v4
"avx512f",
"avx512bw",
"avx512cd",
"avx512dq",
"avx512vl",
],
]
# Assumes externally launched process such as
#
# qemu-system-x86_64 -qmp unix:/tmp/qmp,server,nowait -display none -accel kvm
#
# Note different results will be obtained with TCG, as
# TCG masks out certain features otherwise present in
# the CPU model definitions, as does KVM.
sock = sys.argv[1]
cmd = sys.argv[2]
shell = qmp.QEMUMonitorProtocol(sock)
shell.connect()
models = shell.cmd("query-cpu-definitions")
# These QMP props don't correspond to CPUID fatures
# so ignore them
skip = [
"family",
"min-level",
"min-xlevel",
"vendor",
"model",
"model-id",
"stepping",
]
names = []
for model in models["return"]:
if "alias-of" in model:
continue
names.append(model["name"])
models = {}
for name in sorted(names):
cpu = shell.cmd("query-cpu-model-expansion",
{ "type": "static",
"model": { "name": name }})
got = {}
for (feature, present) in cpu["return"]["model"]["props"].items():
if present and feature not in skip:
got[feature] = True
if name in ["host", "max", "base"]:
continue
models[name] = {
# Dict of all present features in this CPU model
"features": got,
# Whether each x86-64 ABI level is satisfied
"levels": [False, False, False, False],
# Number of extra CPUID features compared to the x86-64 ABI level
"distance":[-1, -1, -1, -1],
# CPUID features present in model, but not in ABI level
"delta":[[], [], [], []],
# CPUID features in ABI level but not present in model
"missing": [[], [], [], []],
}
# Calculate whether the CPU models satisfy each ABI level
for name in models.keys():
for level in range(len(levels)):
got = set(models[name]["features"])
want = set(levels[level])
missing = want - got
match = True
if len(missing) > 0:
match = False
models[name]["levels"][level] = match
models[name]["missing"][level] = missing
# Cache list of CPU models satisfying each ABI level
abi_models = [
[],
[],
[],
[],
]
for name in models.keys():
for level in range(len(levels)):
if models[name]["levels"][level]:
abi_models[level].append(name)
for level in range(len(abi_models)):
# Find the union of features in all CPU models satisfying this ABI
allfeatures = {}
for name in abi_models[level]:
for feat in models[name]["features"]:
allfeatures[feat] = True
# Find the intersection of features in all CPU models satisfying this ABI
commonfeatures = []
for feat in allfeatures:
present = True
for name in models.keys():
if not models[name]["levels"][level]:
continue
if feat not in models[name]["features"]:
present = False
if present:
commonfeatures.append(feat)
# Determine how many extra features are present compared to the lowest
# common denominator
for name in models.keys():
if not models[name]["levels"][level]:
continue
delta = set(models[name]["features"].keys()) - set(commonfeatures)
models[name]["distance"][level] = len(delta)
models[name]["delta"][level] = delta
def print_uarch_abi_csv():
print("# Automatically generated from '%s'" % __file__)
print("Model,baseline,v2,v3,v4")
for name in models.keys():
print(name, end="")
for level in range(len(levels)):
if models[name]["levels"][level]:
print(",✅", end="")
else:
print(",", end="")
print()
print_uarch_abi_csv()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/cpu-x86-uarch-abi.py
|
#!/usr/bin/env python3
#
# Copyright (C) 2020 Red Hat, Inc.
#
# SPDX-License-Identifier: GPL-2.0-or-later
import argparse
import glob
import os
import shutil
import subprocess
import tempfile
def signcode(path):
cmd = os.environ.get("SIGNCODE")
if not cmd:
return
subprocess.run([cmd, path])
def main():
parser = argparse.ArgumentParser(description="QEMU NSIS build helper.")
parser.add_argument("outfile")
parser.add_argument("prefix")
parser.add_argument("srcdir")
parser.add_argument("cpu")
parser.add_argument("nsisargs", nargs="*")
args = parser.parse_args()
destdir = tempfile.mkdtemp()
try:
subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep])
with open(
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
) as nsh:
for exe in glob.glob(
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
):
exe = os.path.basename(exe)
arch = exe[12:-4]
nsh.write(
"""
Section "{0}" Section_{0}
SetOutPath "$INSTDIR"
File "${{BINDIR}}\\{1}"
SectionEnd
""".format(
arch, exe
)
)
for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")):
signcode(exe)
makensis = [
"makensis",
"-V2",
"-NOCD",
"-DSRCDIR=" + args.srcdir,
"-DBINDIR=" + destdir + args.prefix,
]
dlldir = "w32"
if args.cpu == "x86_64":
dlldir = "w64"
makensis += ["-DW64"]
if os.path.exists(os.path.join(args.srcdir, "dll")):
makensis += ["-DDLLDIR={0}/dll/{1}".format(args.srcdir, dlldir)]
makensis += ["-DOUTFILE=" + args.outfile] + args.nsisargs
subprocess.run(makensis)
signcode(args.outfile)
finally:
shutil.rmtree(destdir)
if __name__ == "__main__":
main()
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/nsis.py
|
#! /usr/bin/env python3
# Invoke sparse based on the contents of compile_commands.json,
# also working around several deficiencies in cgcc's command line
# parsing
import json
import subprocess
import os
import sys
import shlex
def cmdline_for_sparse(sparse, cmdline):
# Do not include the C compiler executable
skip = True
arg = False
out = sparse + ['-no-compile']
for x in cmdline:
if arg:
out.append(x)
arg = False
continue
if skip:
skip = False
continue
# prevent sparse from treating output files as inputs
if x == '-MF' or x == '-MQ' or x == '-o':
skip = True
continue
# cgcc ignores -no-compile if it sees -M or -MM?
if x.startswith('-M'):
continue
# sparse does not understand these!
if x == '-iquote' or x == '-isystem':
x = '-I'
if x == '-I':
arg = True
out.append(x)
return out
root_path = os.getenv('MESON_BUILD_ROOT')
def build_path(s):
return s if not root_path else os.path.join(root_path, s)
ccjson_path = build_path(sys.argv[1])
with open(ccjson_path, 'r') as fd:
compile_commands = json.load(fd)
sparse = sys.argv[2:]
sparse_env = os.environ.copy()
for cmd in compile_commands:
cmdline = shlex.split(cmd['command'])
cmd = cmdline_for_sparse(sparse, cmdline)
print('REAL_CC=%s' % shlex.quote(cmdline[0]),
' '.join((shlex.quote(x) for x in cmd)))
sparse_env['REAL_CC'] = cmdline[0]
r = subprocess.run(cmd, env=sparse_env, cwd=root_path)
if r.returncode != 0:
sys.exit(r.returncode)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/check_sparse.py
|
# -*- coding: utf-8 -*-
#
# Copyright (c) 2017-2019 Red Hat Inc.
#
# Authors:
# Markus Armbruster <armbru@redhat.com>
# Marc-André Lureau <marcandre.lureau@redhat.com>
#
# This work is licensed under the terms of the GNU GPL, version 2.
# See the COPYING file in the top-level directory.
"""
QAPI error classes
Common error classes used throughout the package. Additional errors may
be defined in other modules. At present, `QAPIParseError` is defined in
parser.py.
"""
from typing import Optional
from .source import QAPISourceInfo
class QAPIError(Exception):
"""Base class for all exceptions from the QAPI package."""
class QAPISourceError(QAPIError):
"""Error class for all exceptions identifying a source location."""
def __init__(self,
info: Optional[QAPISourceInfo],
msg: str,
col: Optional[int] = None):
super().__init__()
self.info = info
self.msg = msg
self.col = col
def __str__(self) -> str:
assert self.info is not None
loc = str(self.info)
if self.col is not None:
assert self.info.line is not None
loc += ':%s' % self.col
return loc + ': ' + self.msg
class QAPISemError(QAPISourceError):
"""Error class for semantic QAPI errors."""
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi/error.py
|
# -*- coding: utf-8 -*-
#
# QAPI code generation
#
# Copyright (c) 2015-2019 Red Hat Inc.
#
# Authors:
# Markus Armbruster <armbru@redhat.com>
# Marc-André Lureau <marcandre.lureau@redhat.com>
#
# This work is licensed under the terms of the GNU GPL, version 2.
# See the COPYING file in the top-level directory.
from contextlib import contextmanager
import os
import re
from typing import (
Dict,
Iterator,
Optional,
Tuple,
)
from .common import (
c_fname,
c_name,
guardend,
guardstart,
mcgen,
)
from .schema import (
QAPISchemaIfCond,
QAPISchemaModule,
QAPISchemaObjectType,
QAPISchemaVisitor,
)
from .source import QAPISourceInfo
class QAPIGen:
def __init__(self, fname: str):
self.fname = fname
self._preamble = ''
self._body = ''
def preamble_add(self, text: str) -> None:
self._preamble += text
def add(self, text: str) -> None:
self._body += text
def get_content(self) -> str:
return self._top() + self._preamble + self._body + self._bottom()
def _top(self) -> str:
# pylint: disable=no-self-use
return ''
def _bottom(self) -> str:
# pylint: disable=no-self-use
return ''
def write(self, output_dir: str) -> None:
# Include paths starting with ../ are used to reuse modules of the main
# schema in specialised schemas. Don't overwrite the files that are
# already generated for the main schema.
if self.fname.startswith('../'):
return
pathname = os.path.join(output_dir, self.fname)
odir = os.path.dirname(pathname)
if odir:
os.makedirs(odir, exist_ok=True)
# use os.open for O_CREAT to create and read a non-existant file
fd = os.open(pathname, os.O_RDWR | os.O_CREAT, 0o666)
with os.fdopen(fd, 'r+', encoding='utf-8') as fp:
text = self.get_content()
oldtext = fp.read(len(text) + 1)
if text != oldtext:
fp.seek(0)
fp.truncate(0)
fp.write(text)
def _wrap_ifcond(ifcond: QAPISchemaIfCond, before: str, after: str) -> str:
if before == after:
return after # suppress empty #if ... #endif
assert after.startswith(before)
out = before
added = after[len(before):]
if added[0] == '\n':
out += '\n'
added = added[1:]
out += ifcond.gen_if()
out += added
out += ifcond.gen_endif()
return out
def build_params(arg_type: Optional[QAPISchemaObjectType],
boxed: bool,
extra: Optional[str] = None) -> str:
ret = ''
sep = ''
if boxed:
assert arg_type
ret += '%s arg' % arg_type.c_param_type()
sep = ', '
elif arg_type:
assert not arg_type.variants
for memb in arg_type.members:
ret += sep
sep = ', '
if memb.optional:
ret += 'bool has_%s, ' % c_name(memb.name)
ret += '%s %s' % (memb.type.c_param_type(),
c_name(memb.name))
if extra:
ret += sep + extra
return ret if ret else 'void'
class QAPIGenCCode(QAPIGen):
def __init__(self, fname: str):
super().__init__(fname)
self._start_if: Optional[Tuple[QAPISchemaIfCond, str, str]] = None
def start_if(self, ifcond: QAPISchemaIfCond) -> None:
assert self._start_if is None
self._start_if = (ifcond, self._body, self._preamble)
def end_if(self) -> None:
assert self._start_if is not None
self._body = _wrap_ifcond(self._start_if[0],
self._start_if[1], self._body)
self._preamble = _wrap_ifcond(self._start_if[0],
self._start_if[2], self._preamble)
self._start_if = None
def get_content(self) -> str:
assert self._start_if is None
return super().get_content()
class QAPIGenC(QAPIGenCCode):
def __init__(self, fname: str, blurb: str, pydoc: str):
super().__init__(fname)
self._blurb = blurb
self._copyright = '\n * '.join(re.findall(r'^Copyright .*', pydoc,
re.MULTILINE))
def _top(self) -> str:
return mcgen('''
/* AUTOMATICALLY GENERATED, DO NOT MODIFY */
/*
%(blurb)s
*
* %(copyright)s
*
* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
* See the COPYING.LIB file in the top-level directory.
*/
''',
blurb=self._blurb, copyright=self._copyright)
def _bottom(self) -> str:
return mcgen('''
/* Dummy declaration to prevent empty .o file */
char qapi_dummy_%(name)s;
''',
name=c_fname(self.fname))
class QAPIGenH(QAPIGenC):
def _top(self) -> str:
return super()._top() + guardstart(self.fname)
def _bottom(self) -> str:
return guardend(self.fname)
@contextmanager
def ifcontext(ifcond: QAPISchemaIfCond, *args: QAPIGenCCode) -> Iterator[None]:
"""
A with-statement context manager that wraps with `start_if()` / `end_if()`.
:param ifcond: A sequence of conditionals, passed to `start_if()`.
:param args: any number of `QAPIGenCCode`.
Example::
with ifcontext(ifcond, self._genh, self._genc):
modify self._genh and self._genc ...
Is equivalent to calling::
self._genh.start_if(ifcond)
self._genc.start_if(ifcond)
modify self._genh and self._genc ...
self._genh.end_if()
self._genc.end_if()
"""
for arg in args:
arg.start_if(ifcond)
yield
for arg in args:
arg.end_if()
class QAPISchemaMonolithicCVisitor(QAPISchemaVisitor):
def __init__(self,
prefix: str,
what: str,
blurb: str,
pydoc: str):
self._prefix = prefix
self._what = what
self._genc = QAPIGenC(self._prefix + self._what + '.c',
blurb, pydoc)
self._genh = QAPIGenH(self._prefix + self._what + '.h',
blurb, pydoc)
def write(self, output_dir: str) -> None:
self._genc.write(output_dir)
self._genh.write(output_dir)
class QAPISchemaModularCVisitor(QAPISchemaVisitor):
def __init__(self,
prefix: str,
what: str,
user_blurb: str,
builtin_blurb: Optional[str],
pydoc: str):
self._prefix = prefix
self._what = what
self._user_blurb = user_blurb
self._builtin_blurb = builtin_blurb
self._pydoc = pydoc
self._current_module: Optional[str] = None
self._module: Dict[str, Tuple[QAPIGenC, QAPIGenH]] = {}
self._main_module: Optional[str] = None
@property
def _genc(self) -> QAPIGenC:
assert self._current_module is not None
return self._module[self._current_module][0]
@property
def _genh(self) -> QAPIGenH:
assert self._current_module is not None
return self._module[self._current_module][1]
@staticmethod
def _module_dirname(name: str) -> str:
if QAPISchemaModule.is_user_module(name):
return os.path.dirname(name)
return ''
def _module_basename(self, what: str, name: str) -> str:
ret = '' if QAPISchemaModule.is_builtin_module(name) else self._prefix
if QAPISchemaModule.is_user_module(name):
basename = os.path.basename(name)
ret += what
if name != self._main_module:
ret += '-' + os.path.splitext(basename)[0]
else:
assert QAPISchemaModule.is_system_module(name)
ret += re.sub(r'-', '-' + name[2:] + '-', what)
return ret
def _module_filename(self, what: str, name: str) -> str:
return os.path.join(self._module_dirname(name),
self._module_basename(what, name))
def _add_module(self, name: str, blurb: str) -> None:
if QAPISchemaModule.is_user_module(name):
if self._main_module is None:
self._main_module = name
basename = self._module_filename(self._what, name)
genc = QAPIGenC(basename + '.c', blurb, self._pydoc)
genh = QAPIGenH(basename + '.h', blurb, self._pydoc)
self._module[name] = (genc, genh)
self._current_module = name
@contextmanager
def _temp_module(self, name: str) -> Iterator[None]:
old_module = self._current_module
self._current_module = name
yield
self._current_module = old_module
def write(self, output_dir: str, opt_builtins: bool = False) -> None:
for name, (genc, genh) in self._module.items():
if QAPISchemaModule.is_builtin_module(name) and not opt_builtins:
continue
genc.write(output_dir)
genh.write(output_dir)
def _begin_builtin_module(self) -> None:
pass
def _begin_user_module(self, name: str) -> None:
pass
def visit_module(self, name: str) -> None:
if QAPISchemaModule.is_builtin_module(name):
if self._builtin_blurb:
self._add_module(name, self._builtin_blurb)
self._begin_builtin_module()
else:
# The built-in module has not been created. No code may
# be generated.
self._current_module = None
else:
assert QAPISchemaModule.is_user_module(name)
self._add_module(name, self._user_blurb)
self._begin_user_module(name)
def visit_include(self, name: str, info: Optional[QAPISourceInfo]) -> None:
relname = os.path.relpath(self._module_filename(self._what, name),
os.path.dirname(self._genh.fname))
self._genh.preamble_add(mcgen('''
#include "%(relname)s.h"
''',
relname=relname))
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi/gen.py
|
"""
QAPI visitor generator
Copyright IBM, Corp. 2011
Copyright (C) 2014-2018 Red Hat, Inc.
Authors:
Anthony Liguori <aliguori@us.ibm.com>
Michael Roth <mdroth@linux.vnet.ibm.com>
Markus Armbruster <armbru@redhat.com>
This work is licensed under the terms of the GNU GPL, version 2.
See the COPYING file in the top-level directory.
"""
from typing import List, Optional
from .common import (
c_enum_const,
c_name,
indent,
mcgen,
)
from .gen import QAPISchemaModularCVisitor, ifcontext
from .schema import (
QAPISchema,
QAPISchemaEnumMember,
QAPISchemaEnumType,
QAPISchemaFeature,
QAPISchemaIfCond,
QAPISchemaObjectType,
QAPISchemaObjectTypeMember,
QAPISchemaType,
QAPISchemaVariants,
)
from .source import QAPISourceInfo
def gen_visit_decl(name: str, scalar: bool = False) -> str:
c_type = c_name(name) + ' *'
if not scalar:
c_type += '*'
return mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
%(c_type)sobj, Error **errp);
''',
c_name=c_name(name), c_type=c_type)
def gen_visit_members_decl(name: str) -> str:
return mcgen('''
bool visit_type_%(c_name)s_members(Visitor *v, %(c_name)s *obj, Error **errp);
''',
c_name=c_name(name))
def gen_visit_object_members(name: str,
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
variants: Optional[QAPISchemaVariants]) -> str:
ret = mcgen('''
bool visit_type_%(c_name)s_members(Visitor *v, %(c_name)s *obj, Error **errp)
{
''',
c_name=c_name(name))
if base:
ret += mcgen('''
if (!visit_type_%(c_type)s_members(v, (%(c_type)s *)obj, errp)) {
return false;
}
''',
c_type=base.c_name())
for memb in members:
deprecated = 'deprecated' in [f.name for f in memb.features]
ret += memb.ifcond.gen_if()
if memb.optional:
ret += mcgen('''
if (visit_optional(v, "%(name)s", &obj->has_%(c_name)s)) {
''',
name=memb.name, c_name=c_name(memb.name))
indent.increase()
if deprecated:
ret += mcgen('''
if (!visit_deprecated_accept(v, "%(name)s", errp)) {
return false;
}
if (visit_deprecated(v, "%(name)s")) {
''',
name=memb.name)
indent.increase()
ret += mcgen('''
if (!visit_type_%(c_type)s(v, "%(name)s", &obj->%(c_name)s, errp)) {
return false;
}
''',
c_type=memb.type.c_name(), name=memb.name,
c_name=c_name(memb.name))
if deprecated:
indent.decrease()
ret += mcgen('''
}
''')
if memb.optional:
indent.decrease()
ret += mcgen('''
}
''')
ret += memb.ifcond.gen_endif()
if variants:
tag_member = variants.tag_member
assert isinstance(tag_member.type, QAPISchemaEnumType)
ret += mcgen('''
switch (obj->%(c_name)s) {
''',
c_name=c_name(tag_member.name))
for var in variants.variants:
case_str = c_enum_const(tag_member.type.name, var.name,
tag_member.type.prefix)
ret += var.ifcond.gen_if()
if var.type.name == 'q_empty':
# valid variant and nothing to do
ret += mcgen('''
case %(case)s:
break;
''',
case=case_str)
else:
ret += mcgen('''
case %(case)s:
return visit_type_%(c_type)s_members(v, &obj->u.%(c_name)s, errp);
''',
case=case_str,
c_type=var.type.c_name(), c_name=c_name(var.name))
ret += var.ifcond.gen_endif()
ret += mcgen('''
default:
abort();
}
''')
ret += mcgen('''
return true;
}
''')
return ret
def gen_visit_list(name: str, element_type: QAPISchemaType) -> str:
return mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
%(c_name)s **obj, Error **errp)
{
bool ok = false;
%(c_name)s *tail;
size_t size = sizeof(**obj);
if (!visit_start_list(v, name, (GenericList **)obj, size, errp)) {
return false;
}
for (tail = *obj; tail;
tail = (%(c_name)s *)visit_next_list(v, (GenericList *)tail, size)) {
if (!visit_type_%(c_elt_type)s(v, NULL, &tail->value, errp)) {
goto out_obj;
}
}
ok = visit_check_list(v, errp);
out_obj:
visit_end_list(v, (void **)obj);
if (!ok && visit_is_input(v)) {
qapi_free_%(c_name)s(*obj);
*obj = NULL;
}
return ok;
}
''',
c_name=c_name(name), c_elt_type=element_type.c_name())
def gen_visit_enum(name: str) -> str:
return mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
%(c_name)s *obj, Error **errp)
{
int value = *obj;
bool ok = visit_type_enum(v, name, &value, &%(c_name)s_lookup, errp);
*obj = value;
return ok;
}
''',
c_name=c_name(name))
def gen_visit_alternate(name: str, variants: QAPISchemaVariants) -> str:
ret = mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
%(c_name)s **obj, Error **errp)
{
bool ok = false;
if (!visit_start_alternate(v, name, (GenericAlternate **)obj,
sizeof(**obj), errp)) {
return false;
}
if (!*obj) {
/* incomplete */
assert(visit_is_dealloc(v));
ok = true;
goto out_obj;
}
switch ((*obj)->type) {
''',
c_name=c_name(name))
for var in variants.variants:
ret += var.ifcond.gen_if()
ret += mcgen('''
case %(case)s:
''',
case=var.type.alternate_qtype())
if isinstance(var.type, QAPISchemaObjectType):
ret += mcgen('''
if (!visit_start_struct(v, name, NULL, 0, errp)) {
break;
}
if (visit_type_%(c_type)s_members(v, &(*obj)->u.%(c_name)s, errp)) {
ok = visit_check_struct(v, errp);
}
visit_end_struct(v, NULL);
''',
c_type=var.type.c_name(),
c_name=c_name(var.name))
else:
ret += mcgen('''
ok = visit_type_%(c_type)s(v, name, &(*obj)->u.%(c_name)s, errp);
''',
c_type=var.type.c_name(),
c_name=c_name(var.name))
ret += mcgen('''
break;
''')
ret += var.ifcond.gen_endif()
ret += mcgen('''
case QTYPE_NONE:
abort();
default:
assert(visit_is_input(v));
error_setg(errp, QERR_INVALID_PARAMETER_TYPE, name ? name : "null",
"%(name)s");
/* Avoid passing invalid *obj to qapi_free_%(c_name)s() */
g_free(*obj);
*obj = NULL;
}
out_obj:
visit_end_alternate(v, (void **)obj);
if (!ok && visit_is_input(v)) {
qapi_free_%(c_name)s(*obj);
*obj = NULL;
}
return ok;
}
''',
name=name, c_name=c_name(name))
return ret
def gen_visit_object(name: str) -> str:
return mcgen('''
bool visit_type_%(c_name)s(Visitor *v, const char *name,
%(c_name)s **obj, Error **errp)
{
bool ok = false;
if (!visit_start_struct(v, name, (void **)obj, sizeof(%(c_name)s), errp)) {
return false;
}
if (!*obj) {
/* incomplete */
assert(visit_is_dealloc(v));
ok = true;
goto out_obj;
}
if (!visit_type_%(c_name)s_members(v, *obj, errp)) {
goto out_obj;
}
ok = visit_check_struct(v, errp);
out_obj:
visit_end_struct(v, (void **)obj);
if (!ok && visit_is_input(v)) {
qapi_free_%(c_name)s(*obj);
*obj = NULL;
}
return ok;
}
''',
c_name=c_name(name))
class QAPISchemaGenVisitVisitor(QAPISchemaModularCVisitor):
def __init__(self, prefix: str):
super().__init__(
prefix, 'qapi-visit', ' * Schema-defined QAPI visitors',
' * Built-in QAPI visitors', __doc__)
def _begin_builtin_module(self) -> None:
self._genc.preamble_add(mcgen('''
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/qapi-builtin-visit.h"
'''))
self._genh.preamble_add(mcgen('''
#include "qapi/visitor.h"
#include "qapi/qapi-builtin-types.h"
'''))
def _begin_user_module(self, name: str) -> None:
types = self._module_basename('qapi-types', name)
visit = self._module_basename('qapi-visit', name)
self._genc.preamble_add(mcgen('''
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "%(visit)s.h"
''',
visit=visit))
self._genh.preamble_add(mcgen('''
#include "qapi/qapi-builtin-visit.h"
#include "%(types)s.h"
''',
types=types))
def visit_enum_type(self,
name: str,
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
members: List[QAPISchemaEnumMember],
prefix: Optional[str]) -> None:
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_decl(name, scalar=True))
self._genc.add(gen_visit_enum(name))
def visit_array_type(self,
name: str,
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
element_type: QAPISchemaType) -> None:
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_decl(name))
self._genc.add(gen_visit_list(name, element_type))
def visit_object_type(self,
name: str,
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
base: Optional[QAPISchemaObjectType],
members: List[QAPISchemaObjectTypeMember],
variants: Optional[QAPISchemaVariants]) -> None:
# Nothing to do for the special empty builtin
if name == 'q_empty':
return
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_members_decl(name))
self._genc.add(gen_visit_object_members(name, base,
members, variants))
# TODO Worth changing the visitor signature, so we could
# directly use rather than repeat type.is_implicit()?
if not name.startswith('q_'):
# only explicit types need an allocating visit
self._genh.add(gen_visit_decl(name))
self._genc.add(gen_visit_object(name))
def visit_alternate_type(self,
name: str,
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
variants: QAPISchemaVariants) -> None:
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_visit_decl(name))
self._genc.add(gen_visit_alternate(name, variants))
def gen_visit(schema: QAPISchema,
output_dir: str,
prefix: str,
opt_builtins: bool) -> None:
vis = QAPISchemaGenVisitVisitor(prefix)
schema.visit(vis)
vis.write(output_dir, opt_builtins)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi/visit.py
|
"""
QAPI event generator
Copyright (c) 2014 Wenchao Xia
Copyright (c) 2015-2018 Red Hat Inc.
Authors:
Wenchao Xia <wenchaoqemu@gmail.com>
Markus Armbruster <armbru@redhat.com>
This work is licensed under the terms of the GNU GPL, version 2.
See the COPYING file in the top-level directory.
"""
from typing import List, Optional
from .common import c_enum_const, c_name, mcgen
from .gen import QAPISchemaModularCVisitor, build_params, ifcontext
from .schema import (
QAPISchema,
QAPISchemaEnumMember,
QAPISchemaFeature,
QAPISchemaIfCond,
QAPISchemaObjectType,
)
from .source import QAPISourceInfo
from .types import gen_enum, gen_enum_lookup
def build_event_send_proto(name: str,
arg_type: Optional[QAPISchemaObjectType],
boxed: bool) -> str:
return 'void qapi_event_send_%(c_name)s(%(param)s)' % {
'c_name': c_name(name.lower()),
'param': build_params(arg_type, boxed)}
def gen_event_send_decl(name: str,
arg_type: Optional[QAPISchemaObjectType],
boxed: bool) -> str:
return mcgen('''
%(proto)s;
''',
proto=build_event_send_proto(name, arg_type, boxed))
def gen_param_var(typ: QAPISchemaObjectType) -> str:
"""
Generate a struct variable holding the event parameters.
Initialize it with the function arguments defined in `gen_event_send`.
"""
assert not typ.variants
ret = mcgen('''
%(c_name)s param = {
''',
c_name=typ.c_name())
sep = ' '
for memb in typ.members:
ret += sep
sep = ', '
if memb.optional:
ret += 'has_' + c_name(memb.name) + sep
if memb.type.name == 'str':
# Cast away const added in build_params()
ret += '(char *)'
ret += c_name(memb.name)
ret += mcgen('''
};
''')
if not typ.is_implicit():
ret += mcgen('''
%(c_name)s *arg = ¶m;
''',
c_name=typ.c_name())
return ret
def gen_event_send(name: str,
arg_type: Optional[QAPISchemaObjectType],
features: List[QAPISchemaFeature],
boxed: bool,
event_enum_name: str,
event_emit: str) -> str:
# FIXME: Our declaration of local variables (and of 'errp' in the
# parameter list) can collide with exploded members of the event's
# data type passed in as parameters. If this collision ever hits in
# practice, we can rename our local variables with a leading _ prefix,
# or split the code into a wrapper function that creates a boxed
# 'param' object then calls another to do the real work.
have_args = boxed or (arg_type and not arg_type.is_empty())
ret = mcgen('''
%(proto)s
{
QDict *qmp;
''',
proto=build_event_send_proto(name, arg_type, boxed))
if have_args:
assert arg_type is not None
ret += mcgen('''
QObject *obj;
Visitor *v;
''')
if not boxed:
ret += gen_param_var(arg_type)
if 'deprecated' in [f.name for f in features]:
ret += mcgen('''
if (compat_policy.deprecated_output == COMPAT_POLICY_OUTPUT_HIDE) {
return;
}
''')
ret += mcgen('''
qmp = qmp_event_build_dict("%(name)s");
''',
name=name)
if have_args:
assert arg_type is not None
ret += mcgen('''
v = qobject_output_visitor_new_qmp(&obj);
''')
if not arg_type.is_implicit():
ret += mcgen('''
visit_type_%(c_name)s(v, "%(name)s", &arg, &error_abort);
''',
name=name, c_name=arg_type.c_name())
else:
ret += mcgen('''
visit_start_struct(v, "%(name)s", NULL, 0, &error_abort);
visit_type_%(c_name)s_members(v, ¶m, &error_abort);
visit_check_struct(v, &error_abort);
visit_end_struct(v, NULL);
''',
name=name, c_name=arg_type.c_name())
ret += mcgen('''
visit_complete(v, &obj);
if (qdict_size(qobject_to(QDict, obj))) {
qdict_put_obj(qmp, "data", obj);
} else {
qobject_unref(obj);
}
''')
ret += mcgen('''
%(event_emit)s(%(c_enum)s, qmp);
''',
event_emit=event_emit,
c_enum=c_enum_const(event_enum_name, name))
if have_args:
ret += mcgen('''
visit_free(v);
''')
ret += mcgen('''
qobject_unref(qmp);
}
''')
return ret
class QAPISchemaGenEventVisitor(QAPISchemaModularCVisitor):
def __init__(self, prefix: str):
super().__init__(
prefix, 'qapi-events',
' * Schema-defined QAPI/QMP events', None, __doc__)
self._event_enum_name = c_name(prefix + 'QAPIEvent', protect=False)
self._event_enum_members: List[QAPISchemaEnumMember] = []
self._event_emit_name = c_name(prefix + 'qapi_event_emit')
def _begin_user_module(self, name: str) -> None:
events = self._module_basename('qapi-events', name)
types = self._module_basename('qapi-types', name)
visit = self._module_basename('qapi-visit', name)
self._genc.add(mcgen('''
#include "qemu/osdep.h"
#include "%(prefix)sqapi-emit-events.h"
#include "%(events)s.h"
#include "%(visit)s.h"
#include "qapi/compat-policy.h"
#include "qapi/error.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qmp-event.h"
''',
events=events, visit=visit,
prefix=self._prefix))
self._genh.add(mcgen('''
#include "qapi/util.h"
#include "%(types)s.h"
''',
types=types))
def visit_end(self) -> None:
self._add_module('./emit', ' * QAPI Events emission')
self._genc.preamble_add(mcgen('''
#include "qemu/osdep.h"
#include "%(prefix)sqapi-emit-events.h"
''',
prefix=self._prefix))
self._genh.preamble_add(mcgen('''
#include "qapi/util.h"
'''))
self._genh.add(gen_enum(self._event_enum_name,
self._event_enum_members))
self._genc.add(gen_enum_lookup(self._event_enum_name,
self._event_enum_members))
self._genh.add(mcgen('''
void %(event_emit)s(%(event_enum)s event, QDict *qdict);
''',
event_emit=self._event_emit_name,
event_enum=self._event_enum_name))
def visit_event(self,
name: str,
info: Optional[QAPISourceInfo],
ifcond: QAPISchemaIfCond,
features: List[QAPISchemaFeature],
arg_type: Optional[QAPISchemaObjectType],
boxed: bool) -> None:
with ifcontext(ifcond, self._genh, self._genc):
self._genh.add(gen_event_send_decl(name, arg_type, boxed))
self._genc.add(gen_event_send(name, arg_type, features, boxed,
self._event_enum_name,
self._event_emit_name))
# Note: we generate the enum member regardless of @ifcond, to
# keep the enumeration usable in target-independent code.
self._event_enum_members.append(QAPISchemaEnumMember(name, None))
def gen_events(schema: QAPISchema,
output_dir: str,
prefix: str) -> None:
vis = QAPISchemaGenEventVisitor(prefix)
schema.visit(vis)
vis.write(output_dir)
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi/events.py
|
nvtrust-main
|
infrastructure/kvm/qemu/qemu_source/scripts/qapi/__init__.py
|
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