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application_number string	publication_number string	title string	decision string	date_produced string	date_published string	cpc_labels string	main_ipcr_label string	ipcr_labels string	patent_number string	filing_date string	patent_issue_date string	uspc_class string	uspc_subclass string	examiner_id string	examiner_name_last string	examiner_name_first string	inventor_list string	abstract string	claims string	background string	summary string	full_description string	ipcr_label_section string	ipcr_label_class class label	ipcr_label_subclass class label	ipcr_label_group string	ipcr_label_subgroup string
11899216	US20080004738A1-20080103	Systems and method providing for remote system design	ACCEPTED	20071218	20080103	[]	G06F1900	["G06F1900"]	7428441	20070905	20080923	700	097000	63121.0	VON BUHR	MARIA	[{"inventor_name_last": "Walters", "inventor_name_first": "Eric", "inventor_city": "Modesto", "inventor_state": "CA", "inventor_country": "US"}]	A two-way communication and data transfer system allows a field technician and a designer to work together to create a retrofit design for a flow system, make a cost estimate for the retrofit, and gather an approval from a customer all in a single visit to the customer site. The field technician can utilize a remote unit including a digital camera, data entry device, and communication device, which allows the technician to transfer images and dimension information about the existing system to a base unit. A designer can take this information from the base unit and generate a virtual design for a new system, allowing a virtual view and cost estimate to be generated for display to the customer. The technician and the designer can communicate during the process to improve the accuracy of the design and estimate.	1. A method of retrofitting elements of an existing circulation system for a pool in order to improve fluid flow comprising the steps of: obtaining a plurality of measurements at a pool site in order to characterize the existing circulation system; inputting the measurements into a data entry device; using the data entry device, transmitting the measurements to a technician at a remote design location; at the remote design location, creating a virtual design for the retrofit based on the measurements, said virtual design including new fittings and piping configured to improve fluid flow through the circulation system; and transmitting information related to the virtual design back to the pool site. 2. A method as recited in claim 1, further including the steps of: at the remote design location, generating pricing information sufficient to generate a cost estimate for the retrofit; and transmitting the pricing information to the pool site. 3. A method as recited in claim 1, further including the step of transmitting an image of the virtual design from the remote design location to the pool site for approval. 4. A method as recited in claim 1, further including the steps of: building a retrofit kit based on the virtual design including the new fittings and pipings; delivering the retrofit kit to the pool site; and installing the retrofit kit into the circulation system at the pool site. 5. A method as recited in claim 1, further including the step at the pool site of generating an image of the circulation system and transmitting said image to the remote design location for use in creating the virtual design. 6. A method as recited in claim 1, further including the step of establishing a verbal communication link between the remote technician and an installer at the pool site to facilitate transfer of additional information about the pool to the remote technician. 7. A method of retrofitting elements of an existing circulation system for a pool in order to improve fluid flow comprising the steps of: obtaining a plurality of measurements at a pool site in order to characterize the existing circulation system; obtaining an image of the existing fittings; transmitting the image and the measurements to a technician at a remote design location; at the remote design location, creating a virtual design for the retrofit based on the image and the measurements, said virtual design including new fittings and piping configured to improve fluid flow through the circulation system; transmitting information related to the virtual design back to the pool site. 8. A method as recited in claim 7, further including the steps of: at the remote design location, generating pricing information sufficient to generate a cost estimate for the retrofit; and transmitting the pricing information to the pool site. 9. A method as recited in claim 7, further including the step of transmitting an image of the virtual design from the remote design location to the pool site for approval. 10. A method as recited in claim 7, further including the steps of: building a retrofit kit based on the virtual design including the new fittings and pipings; delivering the retrofit kit to the pool site; and installing the retrofit kit into the circulation system at the pool site. 11. A method as recited in claim 7, further including the step of establishing a verbal communication link between the remote technician and an installer at the pool site to facilitate transfer of additional information about the pool to the remote technician. 12. A method as recited in claim 7, further including the step of inputting the measurements obtained at the pool site into a data entry device and using the data entry device to transmit the measurements to the remote design location. 13. A method of retrofitting elements of an existing circulation system for a pool in order to improve fluid flow comprising the steps of: obtaining a plurality of measurements at a pool site in order to characterize the existing circulation system; transmitting the measurements to a design technician at a remote design location; establishing a communication link between the field technician and the design technician allowing additional parameters related to the pool site to be discussed; at the remote design location, creating a virtual design for the retrofit based on the measurements and the additional parameters, said virtual design including new fittings and piping configured to improve fluid flow through the circulation system; transmitting information related to the virtual design back to the pool site. 14. A method as recited in claim 13, further including the steps of: at the remote design location, generating pricing information sufficient to generate a cost estimate for the retrofit; and transmitting the pricing information to the pool site. 15. A method as recited in claim 13, further including the step of transmitting an image of the virtual design from the remote design location to the pool site for approval. 16. A method as recited in claim 13, further including the steps of: building a retrofit kit based on the virtual design including the new fittings and pipings; delivering the retrofit kit to the pool site; and installing the retrofit kit into the circulation system at the pool site. 17. A method as recited in claim 13, further including the step at the pool site of generating an image of the circulation system and transmitting said image to the remote design location for use in creating the virtual design. 18. A method as recited in claim 13, further including the step of inputting the measurements obtained at the pool site into a data entry device and using the data entry device to transmit the measurements to the remote design location.	<SOH> BACKGROUND <EOH>In many industries in which a flow of fluid is utilized, it is desirable to maximize flow, or minimize flow resistance, in order to reduce the amount of equipment runtime necessary to push through a given volume of fluid. By reducing the amount of runtime, the amount of wear and tear on the equipment can be reduced, and the cost of running the equipment can be significantly lowered. In industries such as the pool industry, for example, an increase in the throughput of water passed through a filter pump and recirculated through the pool can reduce the necessary runtime of the pump, thereby reducing the cost of gas or electricity necessary to run the pump. A major obstacle to flow in the pool industry is the use of standard piping components, such as 90° elbows, 45° fittings, unions, tees, and crosses, made from materials such as PVC and assembled with materials such as PVC cement, Teflon® tape, or silicone cement. While these basic elements are cheap and readily available at most hardware stores, they can result in sharp turns and other partial barriers that can lead to a significant reduction in flow, compared to a more linear or smooth run, as known in the art for flow of a fluid. A swimming pool can be retrofitted to provide for improved flow. Existing retrofits come with several disadvantages, however. One disadvantage is that the person doing the retrofit generally is limited to standard plumbing components in standard sizes and shapes. As such, only limited improvement can be obtained by redirecting the flow, such as flow from a suction pipe to the main circulation pump. Further, it takes a substantial amount of time to retrofit a plumbing installation. It typically is necessary for a salesman to go to the site and take measurements, then go offsite to determine the necessary piping and associated costs, then return to the client at a later time for approval, a signature, and a deposit. Subsequently, an installer will be sent in to dismantle the existing piping and equipment and install new components. The installer must build the new piping using standard parts, oftentimes using parts not carried on the installer's truck, such that the installer has to make at least one trip to the hardware store during installation. The installation also will require a significant amount of cutting and gluing, such that a standard installation can easily take over eight hours of time. The amount of time not only increases the cost of each retrofit, but lowers the number of pools that can be retrofitted in a given period of time by a single technician.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a diagram of a communication system that can be used in accordance with one embodiment of the present invention. FIG. 2 shows diagrams of (a) an equipment system of the prior art and (b) an equipment system that can be designed using the communication system of FIG. 1 . FIG. 3 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 4 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 5 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 6 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. detailed-description description="Detailed Description" end="lead"?	PRIORITY This continuation application claims priority to U.S. patent application Ser. No. 11/191,089, filed Jul. 27, 2005, which application is incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to the design of installations such as systems providing for fluid transport. BACKGROUND In many industries in which a flow of fluid is utilized, it is desirable to maximize flow, or minimize flow resistance, in order to reduce the amount of equipment runtime necessary to push through a given volume of fluid. By reducing the amount of runtime, the amount of wear and tear on the equipment can be reduced, and the cost of running the equipment can be significantly lowered. In industries such as the pool industry, for example, an increase in the throughput of water passed through a filter pump and recirculated through the pool can reduce the necessary runtime of the pump, thereby reducing the cost of gas or electricity necessary to run the pump. A major obstacle to flow in the pool industry is the use of standard piping components, such as 90° elbows, 45° fittings, unions, tees, and crosses, made from materials such as PVC and assembled with materials such as PVC cement, Teflon® tape, or silicone cement. While these basic elements are cheap and readily available at most hardware stores, they can result in sharp turns and other partial barriers that can lead to a significant reduction in flow, compared to a more linear or smooth run, as known in the art for flow of a fluid. A swimming pool can be retrofitted to provide for improved flow. Existing retrofits come with several disadvantages, however. One disadvantage is that the person doing the retrofit generally is limited to standard plumbing components in standard sizes and shapes. As such, only limited improvement can be obtained by redirecting the flow, such as flow from a suction pipe to the main circulation pump. Further, it takes a substantial amount of time to retrofit a plumbing installation. It typically is necessary for a salesman to go to the site and take measurements, then go offsite to determine the necessary piping and associated costs, then return to the client at a later time for approval, a signature, and a deposit. Subsequently, an installer will be sent in to dismantle the existing piping and equipment and install new components. The installer must build the new piping using standard parts, oftentimes using parts not carried on the installer's truck, such that the installer has to make at least one trip to the hardware store during installation. The installation also will require a significant amount of cutting and gluing, such that a standard installation can easily take over eight hours of time. The amount of time not only increases the cost of each retrofit, but lowers the number of pools that can be retrofitted in a given period of time by a single technician. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a communication system that can be used in accordance with one embodiment of the present invention. FIG. 2 shows diagrams of (a) an equipment system of the prior art and (b) an equipment system that can be designed using the communication system of FIG. 1. FIG. 3 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 4 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 5 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. FIG. 6 is a flowchart showing steps of a process that can be followed in accordance with various embodiments of the present invention. DETAILED DESCRIPTION Systems and methods in accordance with various embodiments of the present invention can overcome various deficiencies in existing approaches to designing and/or retrofitting systems such as systems providing for a flow of fluid. In one embodiment, a technician can collect information from a site that can be transmitted to a base location, where a design for a new system can be created, which can be relayed back to the technician for communication to a customer in a single customer meeting. The technician and persons at the base location can communicate during the design process in order to ensure an accurate design. In another embodiment, a new system can be designed on-site using information gathered by the technician. Once a system is selected and approved by the customer, an equipment kit can be generated that includes everything necessary to retrofit/convert the old system to the newly designed system or to install a new system. This allows an installer to quickly and easily do the work without the need to go offsite during installation for additional parts or to spend time cutting and cementing existing parts. Such approaches can reduce the amount of time the customer has to meet with a technician, allow designs to be generated and approved in a single visit, reduce the amount of travel time, and can allow a kit to be designed such that an installer visiting the site only has to view instructions and install the kit without having to gather parts and/or cut and cement existing parts. FIG. 1 shows a diagram of a communication and data transfer system 100 that can be used in accordance with various embodiments. The use of such a system will be discussed with respect to the retrofit of an existing pool equipment structure, but it should be understood that this is merely exemplary and should not be read as a limitation on the scope of the embodiments discussed herein. In a swimming pool example, a customer can request a quotation for a retrofit of the piping equipment for a backyard swimming pool. A field technician can be dispatched to meet the customer at a given time in the backyard of the customer. Once there, the customer can lead the technician to the pool and the equipment pad 102 containing various pool equipment, typically including a main pump 104 for circulating water through the pool, a filter 108 for catching fine debris or contaminants that may have slipped through a pool skimmer, and a heater 106 for heating the pool water to a desired temperature. The equipment pad also will have various runs of piping 110 connecting the various pieces of equipment and pipes running to and from the pool. The field technician can utilize a remote unit 120 to collect information about the pool equipment 102 to be retrofit. The remote unit can be a single self-contained device, or can include a number of separate devices that can be connected as necessary: If a remote unit contains a cellular phone for voice communications, for example, there may be no need for the cellular phone to be connected to the other components of the remote unit, particularly if the other components include a data transfer device capable of transferring information to a base unit. An exemplary remote unit can include an imaging device 122 allowing the technician to capture various images of the pool and the pool equipment 120. The imaging device can be any appropriate device known for capturing two- or three-dimensional images, such as a digital camera or laser scanner. The remote unit can include a data entry device 126, such as any of the various data entry devices known in the art such as a keyboard, mouse, joystick, stylus, or touch screen, allowing a technician having taken measurements of the pool and pool equipment to enter the information into the remote unit. In another embodiment, a scanner such as a laser scanner or radar device can be used to capture the information and dimension measurements together, such that a separate image capture device and data entry device may not be necessary. A data entry device still can be useful to input customer and other information. The remote unit can include a display device 128, such as a monitor, for allowing the technician to enter and/or view collected information, as well as to display the images and information to the customer. The remote unit can include a wireless device 124, such as a cellular phone and/or cellular modem, allowing the technician to upload the information and images to a base unit. The wireless device also can allow the technician to communicate with persons at the base unit, or a separate communications device such as a cellular phone can be used. If a cellular phone is used to transfer data from a laptop device, for example, then the cellular phone can have a data connection to the laptop. If data is transferred via a cellular modem of the laptop, then the cellular phone does not need to be connected to any other components of the remote unit. The remote unit can include a printer 130 allowing the technician to generate information such as a formal quotation, virtual view of the new equipment, and an analysis of cost savings, that can be given to the customer. The remote unit also can include a payment device 132, such as a credit/debit card reader, allowing the customer to approve the design and place a deposit or payment for the services. As discussed above, these components can take any of a number of configurations, such as a laptop computer with a cellular modem connected to a digital camera and printer. Another alternative utilizes a PDA phone allowing pictures to be taken with the internal camera phone, data to be entered into a spreadsheet on the device, the information to be transmitted by the device to the base unit, and communication with the base unit through a phone connection or another mechanism such as text messaging. In yet another embodiment, design software can be included in the PDA phone such that when the technician enters the information and captures the images, the design can be done internally through software, and the PDA phone can be used to display the proposal and generated information to the customer. The phone connection can have various uses, such as to ask questions of a designer or obtain approval of the design. At the headquarters or other location where the information will be received and the design created, in at least some embodiments, a base unit 140 can be used to receive the information. The base unit can include a communication device 144 capable of receiving information from the remote unit 120. The communication device can be any appropriate device, such as a modem, phone, or wireless device. The communication can not only accept information and mages from the remote unit, but can allow personnel at the base unit to communicate with the field technician. The communication unit can include separate devices, such as a modem for data communication and a phone for interpersonal communication. The base unit also can include a computer graphics program, virtual design studio, or other photo editing device 142 capable of taking the images from the imaging device 122 and either automatically, or manually with input from the personnel, generating a view of the new equipment installed at the actual customer site after the retrofit. The base unit can include a data entry device 146 allowing the personnel to use the photo editor, as well as to enter any additional information for the site and/or design. The base unit can include a display device 148, such as a standard monitor or a projection device allowing personnel to easily see the existing layout during the design process. The base unit also can include a payment device 152 allowing the customer to give verbal approval and account or other information, such as credit card number, whereby the personnel at the base unit can enter the information into the payment device. The base unit can include a parts and design kit 150. This can be an actual kit, made up of fittings and piping, or can be a virtual or computer generated kit, allowing a design to be generated through software. A combination also can be used, wherein a virtual design is made that the personnel attempt to build using the actual pieces, in order to determine if the design will work and/or if additional information is needed. A design kit allows personnel to design a system that will work for the given equipment specifications, whereby the personnel can determine the improvement in flow and necessary equipment costs. The equipment described with respect to FIG. 1 allows a field technician and personnel at a base unit to gather information and design a new flow system all in a single visit to the customer site (although multiple visits could be made as well, such as if the customer did not have time to wait for the design or wanted to discuss the project with a spouse before authorizing). The technician arriving at the location can find an existing equipment pad such as is shown in the prior art diagram of FIG. 2(a). The technician can measure and record dimensions such as the spacing of the return lines 202 exiting the cement pad, the distance to the pump 204, the distance from the outlet of the pump to the inlet of the filter 206, and the distance from the outlet of the filter 206 to the return line 208 in the cement pad. The technician also can measure vertical distances where needed, such as distances relative to the top surface of the cement pad, such that the design can be created accurately in three dimensions. By taking images of the equipment pad and sending them to the base unit, a designer at the base unit can determine whether there might be anything blocking a potential path that would not otherwise have shown up in the measurements, as well as to determine whether any additional measurements or information are needed. The images also allow the virtual design to be placed “in” the image of the equipment pad at the customer location, so customers can see what the equipment will look like in their backyards. For instance, after the virtual design 250 has been completed, as shown in the example of FIG. 2(b), a view of the piping and equipment can be dropped into the image showing the new pump 252 and filter 254 on the cement pad. The image also can show the new piping going between the equipment, as well as to the suction lines 258 and return line 260. Providing the designer with at least one image of the site allows the designer to more easily change the path of the piping. The designer can do away with T-junctions and 90° elbows, which can significantly reduce flow, and replace the existing piping with shaped piping runs that have no sharp turns and that can increase the overall flow of the system. For instance, the piping from the suction lines 202 in the prior art device include two 90° elbows, while the piping from the suction lines 258 in the new design includes a single rounded pipe with a much larger turning radius and no sharp turns, allowing the water to more easily flow to the respective pump. Increasing the flow not only provides the benefit of allowing the pump to run less to circulate the same amount of water, thereby reducing energy costs, but also allows for the use of higher efficiency pumps, which can further reduce energy costs. Pumps such as low head pumps or variable r.p.m. pumps, which can require a greater volume of flow through the circulating system, can reduce operating head pressure and allow for a significant reduction in kilowatt consumption. For example, the wattage of the pump generally can be reduced by a factor of four when the rpm value is reduced by a factor of two, per pump affinity laws. For a pump running at 3450 rpm and drawing ten Amps, a reduction to 1725 rpm will draw only 2.5 Amps. Volume of flow, on the other hand, is only reduced by a factor that is half the reduction factor for rpm, such that the pump in this example will provide 75% of the flow at 1725 rpm, compared to 100% flow at 3450 rpm. If head loss in an existing system can be reduced by 15-20%, such as by utilizing laminar flow piping, the resulting flow can be nearly equal to the full rpm. value, at only about 25% of the kilowatt consumption. FIG. 3 shows steps of an overall process 300 that can be used with use the system of FIG. 1 to generate a design such as that shown in FIG. 2(b). In such a process, a field technician takes a series of images useful for designing a new flow system 302, such as images of the equipment pad, existing equipment, the pool, and the surrounding area of the yard. As discussed above, these images can be any appropriate images, such as digital pictures or images created from at least one set of scan data. The technician also can take a series of measurements relating to the pool and equipment, if the measurements are not obtained by the scanner, and that information can be entered into the remote unit 304 to be sent to the base unit. If a three-dimensional scanner is used, dimension information can be transferred directly to a memory device of the remote unit for later transfer to the base unit. In this case, the data entry device can be used simply to input customer information to be stored in the memory device. In an alternative embodiment, customer data can be entered into a data entry device at the base unit before the technician is dispatched, such that there is no need for the technician to enter customer information and a data entry device may not be necessary. It also should be noted that various steps in this method can be done in any of a number of different orders, and that the listing in the method is not meant to imply a sequential order unless otherwise stated. For example, a technician can make measurements before, during, or after taking images, and can communicate with base unit personnel at any time during the process. Once entered or transferred into the remote unit, the measurement data and images can be transmitted to a base unit for processing 306, such as by uploading the pertinent data to the base unit via a cellular modem of the remote unit. The information can be received by the base unit, such as through another cellular modem, and can be stored in files, databases, or any other techniques known for storing information in an electronic, optical, magnetic, or other appropriate format. Personnel at the base unit can view and/or manipulate the information and images to be used in generating a virtual equipment setup 308. The base unit personnel and the technician can communicate with each other before and/or during the design process to discuss the information and images, as well as to gather any additional information needed to generate an accurate design 310. Once the virtual design is created, a new image can be generated including the proposed design setup, and information can be generated regarding equipment costs and energy savings 312. The new image(s) and information can be sent to the technician for display or other communication to the potential customer 314. The owner can select to authorize the work based on the image and information, all of which can have been generated during a single visit by the technician 316. From the design, a piping and equipment kit can be generated that includes everything (at least from a component standpoint) that a technician will need to retrofit the existing equipment pad. An installer then can install the kit using only basic tools and without the need to locate, cut, or otherwise obtain any additional parts during the installation process 318. In order to better explain such a process, individual steps of an exemplary process will be discussed below in further detail. These explanatory processes are not intended to limit the scope of the overall process, but only to explain the implementation of such a process in accordance with one embodiment. FIG. 4 shows steps of an exemplary process 400 by which a field technician can obtain information for an installation for which a design is to be generated. As discussed above, a field technician can take a series of images of the installation, which can include images of the equipment, the relationship of the equipment to the pool, parts to be retained or replaced, pipes of interest (such as the chase pipe, suction pipe, return pipe, and cleaner pipe), and the surrounding area 402. At least one of these images can be a top-down image of the equipment pad showing the relationship of the equipment and pool lines. Another image can shown the relationship of the pad to the pool. The number and type of images taken can vary by installation, but should be sufficient to show a view of each critical component necessary for the retrofit. The images can be taken with any appropriate imaging device, such as a digital camera or three-dimensional scanning device, which can be internal to the communication device used to send the information to the base unit, such as a cellular PDA phone with a built in camera, or can be separate but connected to, or otherwise in communication with, the communication device. In an alternative embodiment, a cellular phone with a built-in camera can be used to take and transfer images, as well as to provide for voice communication, but can be separate from a data entry device, and/or scanner, and data transfer device used to transfer dimension information. The field technician also can take a series of measurements 404, before, during, or after the capturing of the images. The number of measurements can vary by installation, and can be dependent upon factors such as the number of critical features, number of obstructions, and relative positions of the features and/or obstructions. Critical dimension measurements can include the horizontal and vertical distances between any fittings to which new piping is to be attached, such as the return pipe feed, heater, and/or risers coming out of the cement. Other critical measurements can include the available space on the pad once the old equipment has been removed. An exemplary minimal set of measurements can include the separation in two dimensions of the suction and return lines, as these positions typically are fixed in the cement pad unless the pad also is to be replaced. The measurements to be taken can be known by the technician beforehand, or can be prompted by software on the data entry device. For instance, a series of options of equipment types can be displayed to the technician, such that the technician can select the appropriate type. From that selection, a series of measurements can be requested by the software that guide the technician through the measurement process. If a scanner or radar is used, the software can guide the technician through the scanner placement process such that the necessary measurements can be captured. In order to generate a rough estimate of energy savings of a new installation, a field technician or base unit personnel can simply compare the kilowatt reduction in moving from an existing pump to the new pump. This rough estimate would not take into consideration the effect on flow of the piping improvement, which should easily add at least 10-15% to the savings due to the new pump. The technician can use an ammeter to take an amp reading for the main pump, as the actual value sometimes is different from what is printed on the pump label. In order to provide a more accurate estimate of energy savings, the field technician can gather information about the current flow rate of the pool equipment 406. In one embodiment, the technician can screw a vacuum gauge into a drain port on the existing pump, and can utilize a pressure gauge on top of the filter. The technician then can multiply the reading (in inches of mercury) on the vacuum gauge by 1.13 to obtain the head of the suction piping between the pool and the pump. The resultant value can be added to the reading on the pressure gauge (multiplied by 2.31 to get the reading in feet of head on the pressure side between the pump and the pool), to get a good estimate of the total dynamic head (TDH). For example, if the suction reading is 16″ of mercury (×1.13=18.08′) and the pressure reading is 22.5 psi (×2.31=51.97′) then the TDH of the existing system is approximately 70.05′. If the TDH of the new system is projected to be about 40.00′, then there will be a reduction in head loss of about 30′, which allows the pump to be run for an amount of time each day that is about 40% less than is necessary for the existing system. In order to get a true estimate of energy savings, it would be necessary to know the distance to the pool, the number of fittings, and other information, which cannot always be readily obtained as part of that information is buried underground. The technician can gather any other necessary information, such as distance to the pool or area information, as well as any necessary customer information 408. All this information can be entered via the data entry device, such as by typing the information into a form in a word processing program or spreadsheet, selecting checkboxes or radio buttons in a computer window, or any other ways known for entering data into a data processing or storage device 410. A certain amount of intelligence can be built into the forms to guide the field technician through the measurement collection and entry process. In one embodiment, other than typing in the customer information, all measurement and equipment data can be entered using a single selection action, such as a click of a mouse or stylus. The field technician can submit this information from the remote unit to a base unit located off-site, such as at a headquarters or central office location 410. This submission can be accomplished via any technological approach known for sending information, such as through any of a number of wireless data transfer mechanisms. The information and images can be sent together, or separately. For example, if the images are taken with a camera phone but the data is entered into a laptop, the technician can have the option of uploading the images to the laptop then submitting the images through a wireless modem of the laptop, or can choose to submit the images directly from the camera phone. The technician can contact personnel at the base unit 412, before, during, or after submission of the information. The technician can inform the personnel that the information has been gathered, allowing persons reviewing the information at the base unit to ask questions about the existing installation. These questions can include interpretations of included information or requests for further information. In an alternative embodiment, the information is sent as a message to the base unit. Once the message is received, a person monitoring the base unit can contact the technician after reviewing the information. The timing and number of contacts can vary as necessary. The contacts can be audio, video, text, or any other appropriate ways for communicating between the person at the base unit and the technician. The technician can provide any additional information over the phone, for example, or can enter the additional information via the data entry device of the remote unit and submit the information electronically. FIG. 5 shows steps of an exemplary process 500 by which personnel monitoring the base unit can receive information from a field technician and use this information to design a virtual system for the installation. As discussed above, a communication device of the base unit can receive a series of images of the installation, including images of the equipment, the pool, and the surrounding area, as well as customer and/or measurement information gathered by the technician 502. The information can be received by an operator of the base unit, who then can transfer the information to a designer (such as where a person is doing the design work by hand), or the information can be received directly by the designer. For simplicity of explanation, it will be assumed that the information is received by a designer. The information in one embodiment is imported into a spreadsheet program, which includes a number of formulas, as well as preset electricity costs and other selectable options. The spreadsheet can be tied to a central database that includes parameter values where appropriate, such as material costs, and that can be used to store the information for each job, design, and/or quotation. In another embodiment, the information is imported directly into a customized design program that automatically generates the design and uses information stored in a central database to compute values such as design costs and energy savings. The automatic design generation and cost computations can be done at the base unit or at the remote unit. If done at the remote unit, the design and values can be transmitted to the base unit for approval. Once the information is received from the field technician, and the designer has had an opportunity to review the images and information, the designer can contact the field technician to request further information 504, such as additional dimensions or clarification of existing numbers. The designer also can contact the field technician during the design process, where additional questions may arise. The communication from the designer can come via any appropriate mechanism, such as a cell phone call or text message. The designer can enter the additional information into the base unit 506 in order to ensure that the information is saved for later use. Once the designer has received all (or at least a minimum amount of) the necessary information, the designer can generate a sample equipment pad based on the information and images 508. The designer can determine the appropriate equipment (such as a pump of appropriate size) to be installed and connected in the sample pad. The sample pad can be a three-dimensional design created through a computer graphics program or virtual design studio using computer-generated parts, for example, or can be a physical model created using fittings and piping to create a physical structure. Methods for making virtual models using computer design programs are known in the art and will not be discussed herein in detail. If the design is done by computer, then any appropriate computer assisted drafting program can be used that is capable of generating a three-dimensional design allowing for precise measurements of dimensions to be made. If a physical model is made, fixed fittings and piping and/or variable fittings and piping can be used to create the model. By fixed fittings and piping, it is meant that the designer can have available a large number of fittings and pipe runs of different angles and sizes, such that these pieces can simply be connected appropriately to create the design. By variable fittings and piping, it is meant that the shape and/or size of each component can be altered, such as by bending a flexible run of pipe, in order to arrive at the final design. Using flexible components can be more accurate for the final design, as customized fittings and pipe runs can be made in order to maximize flow and minimize material cost. Using flexible fittings also allows for a more accurate material cost estimate where customized piping is to be used. The entire redesign process can take less than an hour, such as 10-15 minutes for a basic system and 40-60 minutes for a more complex system. Once the design is completed, the designer (or another appropriate person or device) can determine the approximate cost to implement the design 510, using factors such as types and numbers of fittings and amount of material takeoff. A series of pull-down bid templates can be provided to provide for fast and simple quotations. For a physical design, this can include taking actual measurements of the piping runs. For computer assisted designs, the calculations of lengths, widths, etc., can be done automatically through software, such that the total cost can be obtained at the end of the design process or can be updated continually throughout the design. The calculations also can determine the approximate cost savings, such as by factoring in the approximate improvement in flow and the reduction in power usage by a new pump. In order to estimate energy savings, a number of formulas can be used, such as: Kilowatts per hour consumed=Amps×Voltage×10% power loss factor/1000 This result can be used to determine the annual energy consumption by estimating the total number of hours of operation per year. For example, in a pool with a main filter pump and a cleaner/booster pump, the energy consumption for a 9.1 Amp/240V main pump, considering a 10% power loss factor, uses about 1.966 kW/hour. If this pump is run for 8 hours a day at $0.20 per kW/hour, then the annual cost to run the main pump will be about $1,148.04. For a 5.2 Amp/240V booster pump run 3 hours a day, the annual cost is about $245.96, for a total annual energy cost of about $1,394 to run both pumps. For a proposed replacement system, using a single 1.9 Amp/240V main pump, running 8 hours a day, the annual energy cost is about $239.69. By improving the flow through piping, such that this lower power pump can be used, the customer then can expect a projected annual energy savings of about $1,154.30, or about an 83% savings. Once the flow of the system is measured, the increase in flow (as a function of percent) can be used to reduce the amount of necessary run time of the pump to obtain the same throughput. For instance, if the flow is increased by 15% then the pump can run 15% less than is currently necessary. As discussed above, there is no easy way to know the exact underground piping configuration, such that total dynamic head often must be estimated. Certain suppositions about the piping can be used, such as average parameter values for runs of distance, such as average flow over a distance using standard PVC plumbing. In one embodiment, retrofits are estimated to obtain on average a 70% improvement in electrical costs, using both redirected flow and a new pump, with an overall range of about 25%-85% in energy savings. A virtual view of the completed design also can be created 512, such as by adding skins to virtual components and adding the actual images as a background, or by opening at least one of the images in a photo editing program and using piping templates to form a view of the approximate design. The designer also can shoot a physical design against a background such as a green screen (as known in the art) and drop the design onto one of the images. Many other approaches for creating a virtual view in a digital image are known, and ways for implementing each of these will not be discussed herein in detail. A view of the completed design, as well as pricing information and estimated cost savings, can be sent to the field technician 514, such as by using any of the devices discussed above for transmitting info between the base unit and remote unit. FIG. 6 shows steps of an exemplary process 600 by which the field technician can use the information received back from the base unit. As discussed above, a communication device of the remote unit can receive the virtual design, as well as information about the pricing for the project and the projected energy savings 602. This information can be shared with the potential customer during the same visit, as opposed to a subsequent visit as in previous systems. The field technician can have the opportunity to contact the designer or other base unit personnel with questions or comments before presenting the results to the customer 604. The technician can show the design to the customer 606, such as by bringing up the design on a display such as a laptop or PDA screen. Alternatively, the technician can use a projector to project images on a wall or other surface, or can print out a version to show the customer. The technician also can relay the pricing and cost information 608 using similar display devices, and can have the option of printing out forms such as a pricing form, cost savings form, plan layout, estimate, and/or contract. Once the potential customer has a chance to review the information 610, the customer can have the opportunity to request changes or ask additional questions 612, which can be transmitted to the base unit if necessary, with a response transmitted back to the remote unit for the technician to relay to the customer. After reviewing the proposal and asking any questions or making any changes, the customer can have the option of approving the work at a later time, or can choose to authorize the retrofit/design work during the visit by the field technician 614. There are any of a number of ways for the customer to authorize the work, such as by signing a contract and handing the field technician a check, or having the technician call the base unit or type information into the remote unit to provide a credit card number. In another embodiment, the remote device can include, or be connected to, a payment device such as a credit/debit card reader than can allow the customer to pay for the transaction immediately. This can include a deposit or full payment, depending upon factors such as the work being done and any applicable contractor limitations. Once the work is authorized and payment (or at least a deposit) is received, a kit can be created that includes all the necessary parts to retrofit the equipment pad. This kit can include, for example, all the fittings and piping, whether standard or customized, as well as any connecting hardware, a new pump, and any other necessary equipment. Alternative kits can minimally include only any customized piping and/or fittings. The kit can allow the installer to arrive at the location bringing only a standard tool set. The kit can be delivered to the installer, or can be delivered to the customer's address. When the installer arrives, the installer can remove any unnecessary equipment before the retrofit. The kit can come with a set of step by step instructions, and/or a series of diagrams, showing the installer how to install the new equipment and piping. The instructions in one embodiment are generated automatically by the design software. The instructions also can come with a parts list or any other information typically enclosed with a kit to be assembled. The parts of the kit also can be individually labeled for ease of assembly, and can be labeled or configured such that each part can only be installed in the correct orientation. The ability for the installer to simply connect the components can significantly reduce the install time, and therefore the installation cost, as well as reducing the likelihood for errors in the installation process. Further, a simplified installation process allows a less experienced installer to do the retrofit work, such that labor costs can be further reduced. Experienced people instead can be used to monitor the base unit and/or do the design work. Where an installer of an existing system would have to execute tasks such as measuring pipes, cutting pipes of the appropriate length and fitting pipes using existing components, and ensuring proper flow for the given system, an approach in accordance with various embodiments of the present invention allows an installer to simply remove the old equipment and piping, install the new pump, and attach the customized piping simply by screwing or otherwise connecting the new piping to the existing fittings and equipment. The entire process now can take on the order of four hours or less, much of which is involved in removing the existing equipment. Although described with respect to pool systems, there are a number of other industries that can utilize such a two-way communication design process to improve accuracy and reduce the amount of time necessary for the field technician and the customer in order to arrive at a design. While improved flow designs can be used for applications such as irrigation design, water flow, air flow, and power plants, any retrofit that has to design around existing two- or three-dimensional limitations can benefit from such an approach. Even designs of new installations can benefit by such an approach, where images and dimensions of the location for the design can be sent along with other necessary information in order to obtain a design and quote during a single customer visit. As discussed above, much of this functionality can be obtained through software at either the remote unit or base unit. This functionality can be stored in code form on any computer readable medium known or used in the art, such as but not limited to internal memory, external memory, hard disks, optical discs, magnetic discs, CD-ROMS, DVD-ROMS, memory sticks, and memory cards. The functionality also can be in code form in any of a number of signals transmitted to or from the units. The base unit and remote units can include any appropriate device capable of sending, receiving, and processing data. The functionality of the base unit can be contained in the remote unit in some embodiments, such that no communication is necessary unless circumstances dictate otherwise. It should be recognized that a number of variations of the above-identified embodiments will be obvious to one of ordinary skill in the art in view of the foregoing description. Accordingly, the invention is not to be limited by those specific embodiments and methods of the present invention shown and described herein. Rather, the scope of the invention is to be defined by the following claims and their equivalents.	G	60G06	161G06F	19	00
11678476	US20080209242A1-20080828	MODEM CARD CONFIGURED TO COMPENSATE FOR POWER SUPPLY	ACCEPTED	20080814	20080828	[]	G06F132	["G06F132", "G06F126"]	7876814	20070223	20110125	375	222000	70649.0	LUGO	DAVID	[{"inventor_name_last": "Rodriguez", "inventor_name_first": "Romeo Hernandez", "inventor_city": "San Diego", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Matsuo", "inventor_name_first": "Kotaro", "inventor_city": "Poway", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Nergis", "inventor_name_first": "Aydin", "inventor_city": "San Diego", "inventor_state": "CA", "inventor_country": "US"}]	A modem card includes a connector configured to be detachably connected to a computer. The card also includes electronics configured to be powered by a power supply located in the computer and to transmit wireless signals to a communications network at a transmit power. The electronics are configured to vary the transmit power such that the transmit power does not exceed a maximum transmit power. Increases in the transmit power cause a drop in the voltage of the power. The electronics are also configured to determine an adjusted maximum transmit power. The adjusted maximum transmit power is a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage. The electronics are also configured to reduce the value of the maximum transmit power to a value that that is less than or equal to the value for the adjusted maximum transmit power.	1. A modem card, comprising: a connector configured to be connected to a computer; electronics configured to be powered by power supplied from a power supply located in the computer; and the electronics being configured to transmit wireless signals to a communications network, the signals being transmitted at a transmit power, vary the transmit power such that the transmit power does not exceed a maximum transmit power, the transmit power being varied such that a voltage of the power drops in response to increases in the transmit power, determine a value for an adjusted maximum transmit power, the adjusted maximum transmit power being a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage, reduce a value of the maximum transmit power to a value that that is less than or equal to the value determined for the adjusted maximum transmit power. 2. The card of claim 1, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power where the power falls below a voltage threshold, the voltage threshold being equal to or greater than the shut-down voltage, and the revised transmit power being less than the maximum transmit power; repeatedly reducing the revised transmit power and transmitting the wireless signals to the communications system using the revised transmit powers, determining the voltage that results from each revised transmit power, and treating one of the revised transmit powers that result in a voltage that is at least equal to the voltage threshold as the adjusted maximum transmit power. 3. The card of claim 1, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power; transmitting the wireless signals at the revised transmit power; determining the voltage that results from transmitting the wireless signals at the revised transmit power; and determining whether the determined voltage is below a voltage threshold that is at least equal to the shut-down voltage. 4. The card of claim 3, wherein determining the adjusted maximum transmit power includes: decreasing the revised transmit power in response to determining that the determined voltage is below the voltage threshold. 5. The card of claim 3, wherein determining the adjusted maximum transmit power includes: treating the revised transmit powers as the adjusted maximum transmit power in response to determining that the determined voltage is at least equal to the voltage threshold. 6. The card of claim 3, wherein the electronics are configured to receive signals from the communications network; and increasing the transmit power to a revised transmit power is performed in response to the electronics receiving a signal from the communications network which requests that the electronics increase the transmit power. 7. The card of claim 3, wherein the voltage threshold is equal to the shut-down voltage. 8. The card of claim 3, wherein the voltage threshold is greater than the shut-down voltage. 9. The card of claim 1, wherein a set maximum transmit power is stored in the electronics and is not calculated by the electronics but is used as the maximum transmit power at some time during operation of the card, the adjusted maximum transmit power being determined to have a value that is different from a value of the set maximum transmit power. 10. A computer system, comprising: a computer having a power supply that provides power having a voltage; and a modem card removably connected to the computer, the modem card including electronics powered by the power from the power supply, the electronics being configured to transmit wireless signals to a communications network, the signals being transmitted at a transmit power, vary the transmit power such that the transmit power does not exceed a maximum transmit power, increases in the transmit power causing a drop in the voltage of the power, determine a value for an adjusted maximum transmit power, the adjusted maximum transmit power being a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage, reduce a value of the maximum transmit power to a value that that is less than or equal to the value for the adjusted maximum transmit power. 11. The system of claim 10, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power where the power falls below a voltage threshold, the voltage threshold being equal to or greater than the shut-down voltage, and the revised transmit power being less than the maximum transmit power; repeatedly reducing the revised transmit power and transmitting the wireless signals to the communications system using the revised transmit powers, determining the voltage that results from each revised transmit power, and treating one of the revised transmit powers that result in a voltage that is at least equal to the voltage threshold as the adjusted maximum transmit power. 12. The system of claim 10, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power; transmitting the wireless signals at the revised transmit power; determining the voltage that results from transmitting the wireless signals at the revised transmit power; and determining whether the determined voltage is below a voltage threshold that is at least equal to the shut-down voltage. 13. The system of claim 12, wherein determining the adjusted maximum transmit power includes: decreasing the revised transmit power in response to determining that the determined voltage is below the voltage threshold. 14. The system of claim 12, wherein determining the adjusted maximum transmit power includes: treating the revised transmit powers as the adjusted maximum transmit power in response to determining that the determined voltage is at least equal to the voltage threshold. 15. A method of operating a modem card, comprising: transmitting wireless signals to a communications network, the signals being transmitted at a transmit power; varying the transmit power such that the transmit power does not exceed a maximum transmit power, the transmit power being varied such that a voltage of the power drops in response to increases in the transmit power; determining an adjusted maximum transmit power, the adjusted maximum transmit power being a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage; and changing a value of the maximum transmit power to the value of the adjusted maximum transmit power. 16. The method of claim 15, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power where the power falls below a voltage threshold, the voltage threshold being equal to or greater than the shut-down voltage, and the revised transmit power being less than the maximum transmit power; repeatedly reducing the revised transmit power and transmitting the wireless signals to the communications system using the revised transmit powers; determining the voltage that results from each revised transmit power; and treating one of the revised transmit powers that result in a voltage that is at least equal to the voltage threshold as the adjusted maximum transmit power. 17. The method of claim 15, wherein determining the adjusted maximum transmit power includes: increasing the transmit power to a revised transmit power; transmitting the wireless signals at the revised transmit power; determining the voltage that results from transmitting the wireless signals at the revised transmit power; and determining whether the determined voltage is below a voltage threshold that is at least equal to the shut-down voltage. 18. The method of claim 17, wherein determining the adjusted maximum transmit power includes decreasing the revised transmit power in response to determining that the determined voltage is below the voltage threshold. 19. The method of claim 17, wherein determining the adjusted maximum transmit power includes treating the revised transmit powers as the adjusted maximum transmit power in response to determining that the determined voltage is at least equal to the voltage threshold. 20. A program product for a modem card, the program product comprising: computer-executable logic contained on a computer-readable medium and configured for causing the following computer-executed operations to occur: transmitting wireless signals to a communications network, the signals being transmitted at a transmit power; varying the transmit power such that the transmit power does not exceed a maximum transmit power, the transmit power being varied such that a voltage of the power drops in response to increases in the transmit power; determining an adjusted maximum transmit power, the adjusted maximum transmit power being a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage; and changing a value of the maximum transmit power to the value of the adjusted maximum transmit power.	<SOH> BACKGROUND <EOH>Modem cards allow a computer to wirelessly communicate with a communications system. During operation of the modem card, the modem card transmits wireless signals to the communications system. In some instances, the communications system requests that the PC card increase the transmit power of the signals. The modem card can increase the transmit power up to a maximum transmit power. The maximum transmit power is generally set by the manufacturer of the modem card. Modem cards are powered by a power supply located in the computer to which the modem card is connected. Increasing the transmit power of the modem card increases the current draw from the modem card. As a result, the increased transmit power can cause a drop in the voltage of the power being supplied to the modem card by the computer (supplied voltage). Different computer manufacturers use different power supplies. As a result, increasing the transmit power to the maximum transmit power causes the supplied voltage to drop to different levels in different computers. In some computers, the supplied voltage can drop below a shut-down voltage where the computer shuts down the computer or the modem card. As a result, there is a need for modem cards that compensate for variation in the power supplies used in different computers.	<SOH> SUMMARY <EOH>A modem card includes a connector configured to be detachably connected to a computer. The modem card also includes electronics configured to be powered by a power supply located in the computer. The electronics are configured to transmit wireless signals to a communication network at a transmit power level. The electronics are configured to vary the transmit power such that the transmit power does not exceed a maximum transmit power. Increases in the transmit power cause a drop in the voltage of the power supplied to the modem card. The electronics are also configured to determine an adjusted maximum transmit power. The adjusted maximum transmit power is a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage. The electronics are also configured to reduce the value of the maximum transmit power to a value that that is less than or equal to the value for the adjusted maximum transmit power.	TECHNICAL FIELD The present invention relates to computer peripheral devices and more particularly to modem cards. BACKGROUND Modem cards allow a computer to wirelessly communicate with a communications system. During operation of the modem card, the modem card transmits wireless signals to the communications system. In some instances, the communications system requests that the PC card increase the transmit power of the signals. The modem card can increase the transmit power up to a maximum transmit power. The maximum transmit power is generally set by the manufacturer of the modem card. Modem cards are powered by a power supply located in the computer to which the modem card is connected. Increasing the transmit power of the modem card increases the current draw from the modem card. As a result, the increased transmit power can cause a drop in the voltage of the power being supplied to the modem card by the computer (supplied voltage). Different computer manufacturers use different power supplies. As a result, increasing the transmit power to the maximum transmit power causes the supplied voltage to drop to different levels in different computers. In some computers, the supplied voltage can drop below a shut-down voltage where the computer shuts down the computer or the modem card. As a result, there is a need for modem cards that compensate for variation in the power supplies used in different computers. SUMMARY A modem card includes a connector configured to be detachably connected to a computer. The modem card also includes electronics configured to be powered by a power supply located in the computer. The electronics are configured to transmit wireless signals to a communication network at a transmit power level. The electronics are configured to vary the transmit power such that the transmit power does not exceed a maximum transmit power. Increases in the transmit power cause a drop in the voltage of the power supplied to the modem card. The electronics are also configured to determine an adjusted maximum transmit power. The adjusted maximum transmit power is a transmit power at which the signals can be transmitted to the communications system without the voltage dropping below a shut-down voltage. The electronics are also configured to reduce the value of the maximum transmit power to a value that that is less than or equal to the value for the adjusted maximum transmit power. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a computer system configured to transmit wireless signals to a communications system. The computer system includes a modem card connected to a computer such that the computer provides power to electronics in the modem card. FIG. 2 is a graph illustrating a hypothetical relationship between the transmit power of the wireless signals and the voltage of the power that the computer supplies to the modem card. FIG. 3 is a flow chart for a method of operating the modem card. DETAILED DESCRIPTION A modem card is configured to be detachably connected to a computer. When the modem card is connected to the computer, a power supply in the computer provides power to the modem card (supplied power). The supplied power powers the operation of electronics in the modem card. The electronics employ the supplied power to transmit wireless signals to a communications system. The modem card can vary the transmit power of the signals up to a maximum transmit power. Increasing the transmit power reduces the voltage of the supplied power. The modem card determines an adjusted maximum transmit power. The adjusted maximum transmit power is a transmit power at which the signals can be transmitted to the communications system without the voltage of the supplied power dropping below a shut-down voltage. The modem card changes the value of the maximum transmit power from a set maximum transmit power to a value that is at most equal to the value of the adjusted maximum transmit power. As a result, the modem card transmits signals using a maximum transmit power that is less than or equal to the adjusted maximum transmit power. Accordingly, the electronics can increase the transmit power to the maximum transmit power without the voltage of the supplied power dropping below a shut-down voltage. The modem card can determine a different adjusted maximum transmit power for different power supplies and accordingly for different computers. As a result, the ability of the modem card to increase the transmit power to the maximum transmit power without the voltage of the supplied power dropping below the shut-down voltage is independent of the computer being employed. FIG. 1 illustrates a computer system 10 in wireless communication with the base station 12 of a wireless communications system 14. The computer system 10 includes a modem card 16 in communication with a computer 18. The modem card 16 enables the computer 18 to wirelessly communicate with the wireless communications system 14 over a wireless air-link. Examples of suitable wireless communications systems 14 include, but are not limited to, code-division multiple access (CDMA) based networks. Suitable computers 18 include laptop computers and notebook computers but can also include other computers 18 that employ modem cards 16 to communicate with wireless communication systems such as game systems and office equipment. Suitable modem cards 16 includes, but are not limited to, Personal Computer 18 Memory Card International Association (PCMCIA cards or PC cards) having wireless modem capabilities, Express Cards having wireless modem capabilities, Miniature Cards (Mini Cards) having wireless modem capabilities, and Express Mini Cards or Mini Express Cards having wireless modem capabilities. The modem card 16 includes a connector 20 that permits the modem card 16 to be detachably connected to a connector 22 in the computer 18. For instance, PC cards typically employ a 68-contact, dual row pin and socket connector while an Express Card typically employs a 26-contact beam on blade connector. The computer 18 can optionally include a port or a slot configured to receive all or a portion of the modem card 16. The connector 22 can be positioned in the port or slot such that the connector 20 on the modem card 16 is connected with the connector 22 on the computer 18. The computer 18 includes a power supply 24 that provides power to electronics 32 in the modem card 16 through the connector 20. For instance, modem cards 16 typically operate at about 5 V or 3.3 V. In some instances, the power supply 24 provides power to the modem card 16 at about 5 V or at about 3.3 V. The electronics 32 include a processor 34 in communication with a voltmeter 35. The processor 34 can employ the voltmeter to monitor, measure, and/or determine the voltage of the power being supplied to the modem card 16. A suitable processor 34 includes, but is not limited to, a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions attributed to the electronics 32 and/or the processor 34. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor 34 may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. The electronics 32 include a transceiver 36 in communication with an antenna 37. The processor 34 is in communication with the transceiver. The processor 34 can employ the transceiver 36 to wirelessly transmit signals to the communications system 14 and to wirelessly receive signals from the communications system 14. As an alternative to the transceiver 36, the electronics 32 can be in communication with a receiver and a transmitter. The electronics 32 include a memory 38 in communication with the processor 34. The electronics 32 can store data for communicating with the communications system 14 in the memory 38. For instance, a maximum transmit power can be stored in the memory. The memory 38 can be any memory device or combination of memory devices suitable for read/write operations. In some instances, the electronics 32 include a computer-readable medium 40 in communication with the processor 34. The computer-readable medium 40 can have a set of instructions to be executed by the processor 34. The processor 34 can execute the instructions such that the electronics 32 perform desired functions such as executing a request for packet a data service originated by the user. Although the computer-readable medium 40 is shown as being different from the memory, the computer-readable medium 40 can be the same as the memory 38. Suitable computer-readable media 38 include, but are not limited to, optical discs such as CDs, magnetic storage diskettes, Zip disks, magnetic tapes, RAMs, and ROMs. During operation of the modem card, the modem card communicates with the communications system. Communication with the communications system can include the modem transmitting signals to the communications system and receiving signals from the communications system. During communication with the communications system, the communications system may determine that the signals transmitted by the computer are undesirably weak. In response, the communications system sends the computer a signal requesting that the modem card increase the transmit power for the signals transmitted from the modem card. The transmit power is the signal power at the output of the antenna 37 is typically measured in units such as dBm or watts. Increasing the transmit power can cause a drop in the voltage of the power supplied to the modem card. For instance, FIG. 2 is a graph illustrating a hypothetical relationship between transmit power and the voltage of the power supplied to the modem card (supplied voltage). The transmit power is shown on the x-axis of FIG. 2. The supplied voltage is shown on the y-axis of FIG. 2. Curve 50 in FIG. 2 shows the supplied voltage decreasing as the transmit power increases. As a result, the communications system requesting that the modem card increases the transmit power can cause a drop in the voltage supplied to the modem card. A set maximum transmit power is labeled in FIG. 2. The “set maximum transmit power” is typically set before the modem card is commercially available. For instance, the “set maximum transmit power” is typically programmed into the electronics by the manufacturer of the modem card or the manufacturer of the electronics. As a result, the set maximum transmit power is not calculated by the electronics. During operation of the modem card, the transmit power can be increased to a maximum transmit power. At one or more times during the operation of the card, the card may be asked to increase the transmit power to the set maximum transmit power. However, as is evident from FIG. 2, increasing the transmit power to the set maximum power can cause the voltage to drop below a shut-down voltage that is also labeled in FIG. 2. The reason for this voltage drop involves how the notebook system is designed. For example, PCMCIA specs call for 3.3V supply that supports up to 1 amp current draw. However, the supply for some notebooks falls below the 3.3V specification at a 1 amp current draw. When the voltage falls below the shut-down voltage, some computers shut down the modem card. Other computers may shut down the computer. For instance, some computers may re-start the computer when the supplied voltage falls below the shut-down voltage. As a result, the communications system requesting that the modem card increase the transmit power can cause the computer to shut down the computer or the modem card. The shut-down voltage varies between notebook designs. For example, notebook computers with a PCMCIA slot and a 3.3V supply, typically have a shut down voltage between 2.7V and 3.0V. The electronics adjust the value of the maximum transmit power relative to an adjusted maximum transmit power. The electronics determine the adjusted maximum transmit power such that the transmit power does not increase to a level where the supplied voltage falls below the shut-down voltage. For instance, the electronics can initially use the set maximum transmit power as the maximum transmit power and then adjust the maximum transmit power down to a value that is less than or equal to the adjusted maximum transmit power labeled in FIG. 2. The adjusted maximum transmit power is selected such that even when the transmit power is raised to the adjusted maximum transmit power, the voltage does not drop to the shut-down voltage. For instance, the adjusted maximum transmit power of FIG. 2 results in a voltage that is greater than the shut-down voltage. The electronics can determine the adjusted maximum transmit power using an iterative process. For instance, the electronics can employ a voltage threshold illustrated in FIG. 2. When the electronics responding to requests to increases the transmit power causes the supplied voltage to drop below the voltage threshold, the electronics reduce the transmit power to a revised transmit power. Each time the electronics generate a revised transmit power, the electronics transmit signals at the revised transmit power and determines the voltage of the supplied power that results from transmitting the signals at the revised transmit power. The value of the revised transmit power is repeatedly reduced until one or more of the revised transmit powers results in a supplied voltage that is at least equal to the voltage threshold. The adjusted maximum transmit power is set to a value that is at most equal to the value of one of the revised transmit powers that results in a supplied voltage that is at least such that the supplied voltage is at or above the voltage threshold. As shown by arrow designation 52 in FIG. 2, the voltage threshold is selected to be greater than or equal to the shut-down voltage. Since the adjusted maximum transmit power results in a supplied voltage that is at or above the voltage threshold and the voltage threshold is greater than or equal to the shut-down voltage, the adjusted maximum transmit power results in a supplied voltage that is greater than or equal to the shut down voltage. Accordingly, the adjusted maximum transmit voltage is selected to reduce events where the computer shuts itself down and/or shuts down the modem card. The voltage threshold is preferably above the shut down voltage. As is evident from the above description, the supplied voltage can fall below the voltage threshold during the process of determining the adjusted maximum transmit power. In some instances, a voltage threshold above the shut-down voltage may prevent the supplied voltage from falling below the shut-down voltage while determining the adjusted maximum transmit power. Curve 50 illustrated in FIG. 2 may vary as a result of the outer resources and/or peripherals to which the computer is providing power. For instance, the drop in the voltage supplied to the modem may become more rapid as the computer increases the power supplied to resources and/or peripherals other than the modem card. As a result, the computer can continue to determine a new adjusted maximum transmit power when the communications system requests that the modem card increase the transmit power. FIG. 3 is a flow chart for a method of operating a modem card. At process block 100, the power supply in the computer supplies power to the electronics in the modem card. At process block 102 the electronics begin communicating with a communications system. When the electronics proceed from process block 100 to process block 102, an initial transmit power serves as the maximum transmit power for communicating with the communications system. The set maximum transmit power can serve as the initial maximum transmit power. Alternately, a maximum transmit power that was previously determined by the electronics can serve as the initial maximum transmit power. At determination block 104, the electronics make a determination whether the modem card has received a request for increased transmit power from the communications system. When the determination is negative, the electronics continue communicating with the communications system at process block 102. When the determination at determination block 104 is positive, the electronics determine a revised transmit power at process block 106. The revised transmit power is determined so as to have a transmit power between the transmit power employed at process block 104 and the maximum transmit power or has a value equal to the maximum power. At process block 108, the modem card transmits signals at the revised transmit power. At determination block 110, the electronics determine whether transmitting signals at the revised transmit power results in an undesirable drop in the supplied voltage. For instance, the electronics can determine the voltage of the power being supplied to the modem card from the power supply. The electronics can compare the voltage to the voltage threshold. The determination at determination block 110 can be positive when the determined voltage is at or below the voltage threshold and the determination at determination block 110 can be negative when the determined voltage exceeds the voltage threshold. When the determination at determination block 110 is negative, the electronics returns to process block 102 and continues to communicate with the communication using the revised transmit power and the maximum transmit power that is currently being employed. When the determination at determination block 110 is positive, the electronics determine the adjusted maximum transmit power at process block 111. Process block 111 includes process blocks 112 where the value of the revised transmit power is reduced. For instance, the revised transmit power can be decreased by a pre-determined increment. At process block 114, the electronics transmit signals to the communications system at the revised transmit power. At determination block 116, the electronics determine whether transmitting signals at the revised transmit power results in an undesirable drop in the supplied voltage. For instance, the electronics can determine the voltage of the power being supplied to the modem card from the power supply. The electronics can compare the determined voltage to a voltage threshold. The voltage threshold can be the same or different from the voltage threshold of determination block 110. The determination at determination block 116 can be positive when the determined voltage is at or below the voltage threshold and the determination at determination block 116 can be negative when the determined voltage exceeds the voltage threshold. When the determination is positive, the electronics return to process block 112. When the determination at determination block 116 is negative, the electronics reduce the value of the maximum transmit power at process block 118. For instance, the electronics can treat the revised transmit power as an adjusted maximum transmit power. The electronics can adjust the value of the maximum transmit power to a value that is less than or equal to the adjusted maximum transmit power. In some instances, the electronics adjust the value of the maximum transmit power to a value that is equal to the value of the adjusted maximum transmit power. In the event that the electronics adjust the value of the maximum transmit power to a value that is less than the value of the adjusted maximum transmit power, the electronics can multiply the adjusted maximum transmit power by a factor that is less than 1 or subtract a factor from the adjusted maximum transmit power. The electronics proceed from process block 118 to process block 102 where the electronics communicate with the communications system using the maximum transmit power determined at process block 118. Each time the electronics adjust the maximum transmit power, the electronics can store the maximum transmit power in the memory. As a result, the electronics can employ the stored maximum transmit power as the initial transmit power each time the computer is powered on without the modem card being removed from the computer, each time that the modem card is used to communicate with the communications system without the computer being shut down, and/or the next time the modem card is used after being removed from the computer. Additionally or alternately, each time the computer is powered on without the modem card being removed from the computer, each time that the modem card is used to communicate with the communications system without the computer being shut down, and/or the next time the modem card is used after being removed from the computer. All or a portion of the method described above can be executed by the electronics. In some instances, the electronics include a computer-readable medium and instructions for executing all or a portion of the methods disclosed above are included on the computer-readable medium. The processor can execute these instructions during operation of the modem card. Other embodiments and modifications of this invention will occur readily to those of ordinary skill in the art in view of these teachings. The above description is illustrative and not restrictive. This invention is to be limited only by the following claims, which include all such embodiments and modifications when viewed in conjunction with the above specification and accompanying drawings. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.	G	60G06	161G06F	1	32
11823672	US20090006885A1-20090101	Heartbeat distribution that facilitates recovery in the event of a server failure during a user dialog	ACCEPTED	20081216	20090101	[]	G06F1120	["G06F1120", "G06F1516"]	8201016	20070628	20120612	714	004000	59198.0	TRUONG	LOAN	[{"inventor_name_last": "Pattabhiraman", "inventor_name_first": "Ramesh V.", "inventor_city": "New Albany", "inventor_state": "OH", "inventor_country": "US"}, {"inventor_name_last": "Vemuri", "inventor_name_first": "Kumar V.", "inventor_city": "Naperville", "inventor_state": "IL", "inventor_country": "US"}]	An exemplary method facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the first group of servers. A second group of servers determines that one of the first servers has failed based on the periodic heartbeat information. The second group of servers is disposed in communication channels between users and the first group of servers. One of the second group of servers receives a message containing a request from a first user having the one of the first group of servers as a destination. One of the second group of servers determines that the message is part of an ongoing dialog of messages between the first user and the one of the first group of servers. Stored dialog information contained in previous communications between the first user and the one of the first group of servers associated with the ongoing dialog is retrieved. Another message is transmitted from the one of the second group of servers to another of the first group of servers. The another message includes the request contained in the message and the retrieved dialog information. This enables the another server to process the request based on the retrieved dialog information without requiring the first user to have to retransmit previously transmitted information that was part of the dialog information.	1. A method for automatic recovery upon failure of a server in a network responsible for replying to user requests comprising the steps of: generating periodic heartbeat information by each of a plurality of first servers of a first type responsible for replying to user requests where the heartbeat information provides an indication of the current operational functionality of each of the first servers; receiving the periodic heartbeat information at each of a plurality of second servers of a second type and determining at each of the plurality of second servers of a second type that one of the first servers has failed based on the periodic heartbeat information, where the second servers have access to communication channels between users and the first servers; receiving by one of the second servers a message containing a request from a first user having the one of the first servers as a destination; determining by the one of the second servers that the message is part of an ongoing dialog of messages between the first user and the one of the first servers; causing stored dialog information contained in previous communications between the first user and the one of the first servers associated with the ongoing dialog to be retrieved; transmitting another message from the one of the second servers to another of the first servers that is not the one of the first servers, where the another message includes the request contained in the message and the retrieved dialog information, thereby enabling the another server to process the request based on the retrieved dialog information without requiring a retransmission from the first user of previously transmitted information that was part of the dialog information. 2. The method of claim 1 further comprising the step of transmitting the heartbeat information for each of the first servers to each of the second servers. 3. The method of claim 1 further comprising the step of storing information contained in messages that flow through the respective second servers at one of a database resource accessible to the respective second servers and a user's communication device, so that the stored information associated with each dialog can be separately identified and retrieved. 4. The method of claim 1 further comprising the step of processing, by the another first server, the request by using information contained in the received dialog information. 5. The method of claim 4 wherein the processing by the another first server of the request requires access to certain information contained in the received dialog information in order for a responsive reply to be transmitted by the another first server to the first user. 6. The method of claim 1 further comprising the steps of storing at the one of the second servers an identity of the dialog information of which the message is a member and storing an identity of the another first server. 7. The method of claim 6 further comprising the step of routing further messages from the first user that are part of the identified ongoing dialog messages to the identified another first server. 8. A first server that facilitates automatic recovery upon failure of one of second servers in a network responsible for replying to user requests comprising: a microprocessor controlled apparatus that receives periodic heartbeat information for each of the second servers of a second type responsible for replying to user requests where the heartbeat information provides an indication of the current operational functionality of the respective second servers; the microprocessor controlled apparatus determines that the one of the second servers has failed based on the periodic heartbeat information, where the microprocessor controlled apparatus supports communication channels between users and the second servers; the microprocessor controlled apparatus receives a message containing a request from a first user having the one of the second servers as a destination; the microprocessor controlled apparatus determines that the message is part of an ongoing dialog of messages between the first user and the one of the second servers; the microprocessor controlled apparatus causing stored dialog information contained in previous communications between the first user and the one of the second servers associated with the ongoing dialog to be retrieved; the microprocessor controlled apparatus transmits another message to another of the second servers that is not the one of the second servers, where the another message includes the request contained in the message and the retrieved dialog information, thereby enabling the another server to process the request based on the retrieved dialog information without requiring a retransmission from the first user of previously transmitted information that was part of the dialog information. 9. The first server of claim 8 further comprising the microprocessor controlled apparatus storing information contained in messages that flow through the first server so that the stored information associated with each dialog can be separately identified and retrieved. 10. The first server of claim 8 wherein processing by the another second server of the request requires access to certain information contained in the received dialog information in order for a responsive reply to be transmitted by the another second server to the first user. 11. The first server of claim 8 further comprising the microprocessor controlled apparatus storing an identity of the dialog information of which the message is a member and storing an identity of the another second server. 12. The first server of claim 11 further comprising the microprocessor controlled apparatus routing further messages from the first user that are part of the identified ongoing dialog messages to the identified another second server. 13. A method for providing nodes in a network with heartbeat information comprising the steps of: receiving periodic heartbeat information at a central node for each of a plurality of first nodes of a first type responsible for replying to user requests where the heartbeat information provides an indication of the current operational functionality of the respective first nodes; generating one message at the central node based on the periodic heartbeat information where the one message contains heartbeat information associated with each of the first nodes; transmitting from the central node the one message to each of a plurality of second nodes of a second type that differs from the first type; determining at each of the second nodes based on the received one message whether each of the first nodes is currently capable of providing its respective normal functionality. 14. The method of claim 13 further comprising the steps of determining at one of the second nodes that one of the first nodes is not currently capable of providing its normal functionality, and assigning by the one of the second nodes another of the first nodes to handle user requests received by the one of the second nodes designated by the user to be processed by the one of the first nodes. 15. The method of claim 13 further comprising the steps of: receiving periodic heartbeat information at the central node for each node in the network where the heartbeat information provides an indication of the current operational functionality of the respective nodes; generating the one message at the central node based on the periodic heartbeat information where the one message contains heartbeat information associated with all of the nodes; transmitting from the central node the one message to each of the nodes; determining at each of the nodes based on the received one message whether any other node in the network is not currently capable of providing its respective normal functionality.	<SOH> BACKGROUND <EOH>This invention relates to monitoring the health of a cluster of servers that provide services to users. More specifically, this invention relates to using such health information to facilitate a recovery during a user dialog with a server in view of a failure of the server which had been supporting the dialog. Heartbeats have been typically utilized by a single monitoring node to determine the health of other nodes in the network. The single monitoring node may periodically transmit inquiries to each of the nodes being monitored with the expectation of receiving a reply from each within a known time to confirm the health of each node. Detecting the failure of a node by its missing heartbeat at the monitoring node permits the latter to implement alternative actions. For example, the monitoring node may redirect future service requests directed to the failed node to another node. Such action may be sufficient where the service request represents a new initial request for service or is a stand-alone request that is independent of past history involving the failed node. However, as recognized as part of the present invention, redirecting a service request sent to a failed node to another node does not represent an effective solution where the service request is dependent on prior information stored at or exchanged with the failed node, i.e. where the prior history of communications with the failed node is required to process the current request such as in an ongoing dialog. Thus, a need exists for a better recovery technique when a service node fails, especially where a user request is dependent on past communications with the failed node.	<SOH> SUMMARY <EOH>It is an object of the present invention to satisfy this need. An exemplary method of the present invention facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the first group of servers. A second group of servers determines that one of the first servers has failed based on the periodic heartbeat information. The second group of servers is disposed in communication channels between users and the first group of servers. One of the second group of servers receives a message containing a request from a first user having the one of the first group of servers as a destination. One of the second group of servers determines that the message is part of an ongoing dialog of messages between the first user and the one of the first group of servers. Stored dialog information contained in previous communications between the first user and the one of the first group of servers associated with the ongoing dialog is retrieved. Another message is transmitted from the one of the second group of servers to another of the first group of servers. The another message includes the request contained in the message and the retrieved dialog information. This enables the another server to process the request based on the retrieved dialog information without requiring the first user to have to retransmit previously transmitted information that was part of the dialog information. Servers that implement the above method provide another exemplary embodiment of the present invention. A tangible computer readable storage medium encoded with control instructions for servers provide a further exemplary embodiment of the present invention.	BACKGROUND This invention relates to monitoring the health of a cluster of servers that provide services to users. More specifically, this invention relates to using such health information to facilitate a recovery during a user dialog with a server in view of a failure of the server which had been supporting the dialog. Heartbeats have been typically utilized by a single monitoring node to determine the health of other nodes in the network. The single monitoring node may periodically transmit inquiries to each of the nodes being monitored with the expectation of receiving a reply from each within a known time to confirm the health of each node. Detecting the failure of a node by its missing heartbeat at the monitoring node permits the latter to implement alternative actions. For example, the monitoring node may redirect future service requests directed to the failed node to another node. Such action may be sufficient where the service request represents a new initial request for service or is a stand-alone request that is independent of past history involving the failed node. However, as recognized as part of the present invention, redirecting a service request sent to a failed node to another node does not represent an effective solution where the service request is dependent on prior information stored at or exchanged with the failed node, i.e. where the prior history of communications with the failed node is required to process the current request such as in an ongoing dialog. Thus, a need exists for a better recovery technique when a service node fails, especially where a user request is dependent on past communications with the failed node. SUMMARY It is an object of the present invention to satisfy this need. An exemplary method of the present invention facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the first group of servers. A second group of servers determines that one of the first servers has failed based on the periodic heartbeat information. The second group of servers is disposed in communication channels between users and the first group of servers. One of the second group of servers receives a message containing a request from a first user having the one of the first group of servers as a destination. One of the second group of servers determines that the message is part of an ongoing dialog of messages between the first user and the one of the first group of servers. Stored dialog information contained in previous communications between the first user and the one of the first group of servers associated with the ongoing dialog is retrieved. Another message is transmitted from the one of the second group of servers to another of the first group of servers. The another message includes the request contained in the message and the retrieved dialog information. This enables the another server to process the request based on the retrieved dialog information without requiring the first user to have to retransmit previously transmitted information that was part of the dialog information. Servers that implement the above method provide another exemplary embodiment of the present invention. A tangible computer readable storage medium encoded with control instructions for servers provide a further exemplary embodiment of the present invention. DESCRIPTION OF THE DRAWINGS Features of exemplary implementations of the invention will become apparent from the description, the claims, and the accompanying drawings in which: FIG. 1 is a block diagram of a network suited for incorporation of an embodiment of the present invention. FIG. 2 is a diagram of illustrative nodes as shown in FIG. 1. FIG. 3 is a flow diagram of illustrative steps for distributing heartbeat information in accordance with an embodiment of a method of the present invention. FIG. 4 is a flow diagram of illustrative steps for recovery following a node failure in accordance with an embodiment of a method of the present invention. DETAILED DESCRIPTION One aspect of the present invention resides in the recognition that the mere presence of heartbeats to measure the health of nodes in a network is not necessarily sufficient to efficiently handle recovery upon the occurrence of the failure of a node. This is especially apparent with recovery in a network where an ongoing dialog is begun with a serving node that fails prior to completion of the dialog. As used herein, a “dialog” refers to a series of communications with a server in which processing of one or more of the communications in the series by the server depends upon information or results associated with a prior communication in the series. For example, assume that a user desires to see a map with an area surrounding an address. The user sends the address, city and state to the server as a first part of a dialog. The server utilizes a database to identify the location and transmits a map image to the user showing the address located on the map having a default granularity. After studying the map for a time, the user desires to see the requested location on a map with greater granularity, i.e. a zoom-in of the map at the same address location. The user transmits a zoom-in request to the same server where the zoom-in request does not contain the original address information since the server already has this information. In response, the server generates another map with increased granularity based on the original location information and transmits this image to the user. This completes the services desired by the user and the dialog. This example is illustrative of a dialog because fulfilling the zoom-in request by the server depends upon the original location information received in the prior request. If the server in this example had failed following the transmission of the original map image to the user but prior to the receipt of the zoom-in request, another server to which the zoom-in request could be redirected would not be able to properly service the request since it would not have access to the original address information upon which the zoom-in request is based. As will be explained in more detail below, an embodiment of the present invention more effectively handles a server failure to enable recovery for users while minimizing the need to seek a repeat of prior sent information of the dialog from the users. FIG. 1 shows an illustrative network that supports a plurality of users where each user is supported by communication device 10, 12 and 14. The communication devices may comprise a personal computer, personal digital assistant, cellular telephone or other type of communication device capable of two-way communications, either over a wireline connection or wirelessly. In the illustrative network, front end servers 20, 22, 24, 26 and 28 support communication services with the communication devices of the users. Each front end server is capable of supporting a plurality of users. The front end servers are coupled to a load balancing switch 30 which is also coupled to back end servers 40, 42, 44 and 46. In the illustrative network the back end servers are configured to include resources required to respond to and satisfy requests made by users. The front end servers provide general communication and routing support for the users. The load balancing switch 30 serves as a switch that defines communication channels between the front end and back end servers, and operates to distribute the total load from all users across the back end servers. FIG. 2 is a block diagram of a node 50 such as used in the network is shown in FIG. 1. The architecture shown for node 50 could be utilized for the front end processors/servers, the load balancing switch or the back end servers. A microprocessor 52 is supported by read-only memory (ROM) 54, random access memory (RAM) 56, and nonvolatile data storage device 58 which may be a hard drive. An input/output module 60 is coupled to the microprocessor 52 and supports inbound and outbound communications with external devices. Input devices 62 such as a keyboard or mouse permit an administrator to provide data and control inputs to the microprocessor. Output generated by the microprocessor can be displayed to the administrator by an output device 64 such as a monitor. Program instructions initially stored in ROM 54 and storage device 58 are typically transferred into RAM 56 to facilitate run-time operation of the application implemented by microprocessor 52. Each of the types, i.e. classes, of nodes in FIG. 1 has a different responsibility. The primary application implemented by the front end servers involves handling communications with the communication devices of the users. The primary application associated with the load balancing switch involves control of communication channels and routing of communications over the channels between the front end servers and the back end servers. If node 50 represents the load balancing switch 30, a channel switching unit (not shown) may also be employed to maintain selectable interconnections between channels connecting the front end servers and channels connecting the rear end servers. The primary application implemented by the rear end servers relates to processing user requests, accessing information associated with a user request, and transmitting a reply to a user request, where the reply may include information or data relevant to the request. It will be apparent to those skilled in the art that the stored program instructions in the nodes will support the respective application programs which include the implementation of the illustrative steps of an embodiment of the method in accordance with the present invention as described below. FIG. 3 illustrates the generation and distribution of heartbeat information in accordance with an embodiment of a method of the present invention. In step 100 heartbeat information is obtained, such as by the load balancing switch, for at least each node in one class of nodes. At least each of one type of server, e.g. back end servers, generates a heartbeat as an indication of the health, i.e. operational functionality, of the respective nodes. This information is received by the load balancing switch. In addition to providing health information of a node, the heartbeat may also include other information such as an indication of the load of the respective node. In another embodiment, each of the server nodes of the network, e.g. the front end nodes and the back end nodes, generate heartbeat information that is collected by the load balancing switch 30. In an alternative embodiment of the above, the load balancing switch may utilize a reliable transport to itself issue heartbeats to various nodes belonging to each class of nodes. The success or failure of the heartbeat delivery step can serve as a direct indicator of the health of the nodes that were “pinged” in each case. As used herein receiving heartbeat information includes any technique by which the heartbeat information can be obtained. Each heartbeat ping may itself contain the health information of the other class of nodes that that node might be interested in. This information could be further augmented with load information if the nodes themselves were to convey that in a periodic pulse to the load balancing switch. Since the load balancing switch starts with minimal information about the health of the nodes in the cluster but builds this knowledge up as it successfully pings more and more nodes with heartbeat reports, this process of cluster health information collection and dissemination represents a “growth spiral heartbeat mechanism”. In step 102 the heartbeat information collected by the load balancing switch is combined into a message. That is, all of the currently available heartbeat information for all nodes reporting heartbeat information is combined into one message so that the health of each can be determined based on receipt of this message. Of course, other information associated with the heartbeat information, e.g. loading of each node, will also be contained in the message. In step 104 the heartbeat information of each of at least one class of nodes is communicated to at least each of another class of nodes by transmitting the one message to the latter. For example, the heartbeat information for each of the back end servers can be communicated by the load balancing switch by sending the message to each of the front end servers. This provides each of the front end servers with information concerning the operational status and load associated with each of the back end servers. In another embodiment in which each of the nodes communicates heartbeat information with each of the other nodes, each node in the network will report its operational status and load information to a central collecting node which will collect this information into a message and transmit the message to each of the other nodes in the network. The heartbeats can be automatically generated on a periodic basis. Alternatively, one or more nodes in the network, e.g. a central collecting node, can be responsible for polling each of the nodes in the network for heartbeat information. FIG. 4 is a flow diagram that shows exemplary steps for recovery upon the failure of a back end server in accordance with an embodiment of a method of the present invention. In this example a user is engaged in a dialog via a front end server and load balancing switch with a back end server, and the back end server experiences a failure prior to the conclusion of the dialog. In accordance with the embodiment of the present invention, a recovery is provided by which a continuance of the dialog with another back end server proceeds without requiring the user to input information previously provided earlier in the dialog. This is facilitated by the front end server handling the dialog recognizing the failure of the back end server based on the received heartbeat information. To provide a more concrete example, assume that the user associated with communication device 12, supported by front end server 22 and load balancing switch 30, is in a dialog in which services are being supplied by back end server 42. In step 150 front end server 22 receives periodically updated heartbeat information, such as in a message from the load balancing switch containing health information for each of the back end servers. Front end server 22 may also store information associated with each dialog handled through it. For example, at the beginning of a dialog supported through front end server 22, a record can be generated in a database associated with server 22 that identifies the user's communication device 12, the back end server 42 and a dialog identification number. All information contained in communications between the user and the back end server involving this dialog that flow through the front end server 22 can be stored in this record. Assuming the communication protocol communicates an indication signifying the conclusion of the dialog, server 22 can cause the associated record to be deleted upon the end of subject dialog or after a predetermined time of inactive communications associated with the dialog. Alternatively, the dialog information may be stored elsewhere such as in the user's communication device such as in cookies. In step 152 a determination is made of whether a node of another class of nodes has failed based on received heartbeat information such as in a message from the load balancing switch. In this example, front end node 22 will periodically make determinations about the health of the back end servers based on received heartbeat information. A NO determination by step 152, indicating no failure of any of the back end servers, results in the front end server continuing to route communications normally between the user communication devices and the assigned back end servers. In accordance with this example, the user of communication device 12 is an ongoing dialog with back end server 42 as supported by front end server 22. The ongoing dialog consists of periodic messages sent from the user to the back end server 42 with corresponding replies sent from the back end server 42 to the user. Upon an initial communication from the user to start the subject dialog, one of the back end servers is assigned by the load balancing switch 30 to handle the dialog. Subsequent communications during the dialog from the user would be routed to the same back end server. A YES determination by step 152, representing that a node failure has been detected, causes the identity of the failed node to be stored as in step 156. In this example, front end server 22 detects the failure of back end server 42 and stores its identity as a failed node. In step 158 a determination is made of whether the front end server 22 detects the receipt of another message in an ongoing dialog addressed for the failed node. In this example, the user of communication device 12 has transmitted another communication in the ongoing dialog that had been supported by back end server 42, i.e. the user will be unaware that back end server 42 is no longer operative. A NO determination by step 158, representing that a received message from a user is not another message in an ongoing dialog series with the failed server, results in further processing at step 154, i.e. normal routing of the message to load balancing switch 30 is made by the front end server for distribution to the assigned back end server. A YES determination by step 158, representing that the received message from a user is another message in an ongoing dialog with the failed server, results in further processing as indicated at step 160. Front end server 22 identifies this dialog and causes the stored record of information associated with the subject ongoing dialog to be retrieved. The current received message is routed along with the retrieved relevant information to another assigned node of the same class as the failed node. Alternatively, if the information may be stored elsewhere, e.g. in the user's communication device, the front end server can generate a request to the device storing the dialog information for the storage device to transmit this information to another back end server selected by the front end server that will handle the continuing dialog. Front end server 22 selects another back end server, e.g. back end server 44, to continue providing the user with services associated with the ongoing dialog previously supported by back end server 42. Because the back end server 44 will receive the current message as well as all of the information associated with the previous messages of the ongoing dialog, the back end server 44 will be able to continue to provide services to the user associated with the ongoing dialog without having to query the user for required information available from the stored dialog. In accordance with step 162, any further messages from the user in the same dialog are routed to the new assigned node. That is, further messages in the same dialog from the user associated with communication device 12 initially addressed to back end server 42 will automatically be readdressed by front end server 22 to have back end server 44 as the destination node. In a possible alternative embodiment of the invention, the dialogs may be proactively recovered by the front-end node when a back-end node failure is detected and notified to the front-end node through heartbeats. In this scenario, the front-end node may opt not to wait till the next request from a client arrives within the established dialog context, but may proactively choose to populate state in a different back-end server for each of the dialogs it had associated with that server. This way, idle cycles on the front-end server can be utilized to perform “dialog maintenance” functions, and new incoming requests for failed dialogs do not take significantly longer to process. This represents a proactive dialog recovery. This provides an efficient and beneficial solution to difficulties which arise with the failure of a server during an ongoing user dialog in which services are being provided by the failed server. Such a recovery from a failure of a servicing node prevents the user from being burdened to retransmit all or at least a portion of the information that had been previously transmitted to and/or handled by the failed node. This is supported by the failure of the servicing node being made known to another transporting node based on the heartbeat information. In accordance with embodiments of the present invention, an automatic recovery is accomplished where the user experiences an uninterrupted call flow for the dialog. The nodes in one example employ one or more computer-readable signal-bearing tangible media. The computer-readable signal-bearing media store software, firmware and/or assembly language for performing one or more portions of one or more embodiments of the invention. The computer-readable signal-bearing medium for the nodes in one example comprise one or more of a magnetic, electrical, optical, biological, and atomic data storage tangible medium. For example, the computer-readable signal-bearing medium comprise floppy disks, magnetic tapes, CD-ROMs, DVD-ROMs, hard disk drives, and electronic memory. Although exemplary implementations of the invention have been depicted and described in detail herein, it will be apparent to those skilled in the art that various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention. With regard to the illustrative steps of an embodiment of a method of the present invention, other steps can be substituted, steps deleted, and/or the steps could be practiced in a different order or by a different apparatus. Heartbeat information can be communicated by transmitting and receiving a heartbeat from each node to every other node in another class. Any node or network element through which communications from an external device such as a user's communication device will travel prior to reaching a servicing node can be utilized to reassign a different service node in the event of a failure of the service node supporting a dialog. Alternatively, one node could monitor for the failure of a servicing node while a different network element is utilized to reassign a different service node in the event of a failure. In accordance with the illustrative network, the front end servers could monitor for the failure of a back end server while the load balancing switch functions to reassign a different back end server in the event of a failure of a back end server. Because all service requests flow through the load balancing switch in the illustrative embodiment, the load balancing switch could monitor for failure of a back end server, cause a retrieval of the prior related dialog information, and reassign a different back end server in the event of a failure of a back end server with an ongoing user dialog. More than two classes of nodes can utilize the heartbeat information distribution and automatic recovery techniques described herein. The scope of the invention is defined in the following claims.	G	60G06	161G06F	11	20
11873334	US20080163385A1-20080703	METHOD AND APPARATUS FOR RAID ON MEMORY	ACCEPTED	20080619	20080703	[]	G06F1108	["G06F1108"]	7549020	20071016	20090616	711	114000	67748.0	FARROKH	HASHEM	[{"inventor_name_last": "Mahmoud", "inventor_name_first": "Fadi", "inventor_city": "Livermore", "inventor_state": "CA", "inventor_country": "US"}]	A method for protecting memory is provided. The method includes reading a block of data from a storage drive and writing the block of data to a first memory portion and a second memory portion. The method also includes managing the first memory portion and the second memory portion to protect the block of data. The block of data can be recovered from a non-failing portion in case either the first memory portion or the second memory portion fails.	1. A method for protecting memory, comprising: reading a block of data from a storage drive; writing the block of data to a first dual in-line module (DIMM) and a second DIMM plugged onto a single host adapter card coupled to the storage drive, wherein the first DIMM and the second DIMM are coupled to a single Redundant Array of Independent Disks (RAID) controller on the single host adapter card; and managing the first DIMM and the second DIMM to protect the block of data, wherein the block of data can be recovered from a non-failing DIMM in case either the first DIMM or the second DIMM fails. 2. The method of claim 1, wherein the first DIMM and the second DIMM plugged onto the single host adapter card are protected by Redundant Array of Independent Disks (RAID). 3. The method of claim 2, wherein the first DIMM and the second DIMM are protected by a RAID level 0. 4. The method of claim 2, wherein the first DIMM and the second DIMM are protected by a RAID level 1. 5. The method of claim 1, wherein the operation of managing the first DIMM and the second DIMM to protect the block of data is performed by a RAID Input/Output processor integrated on the single host adapter card. 6. The method of claim 1, wherein if either the first DIMM or the second DIMM is faulty, the faulty DIMM be replaced by another new DIMM by hot plugging. 7. The method of claim 1, wherein each of the first DIMM and the second DIMM is partitioned into multiple memory partitions. 8. A system for increasing a performance and fault tolerance of a computer system, the system comprising: a set of storage drives configured to store data; a first DIMM and a second DIMM protected by Redundant Array of Independent Disks (RAID), wherein the first DIMM and the second DIMM are plugged onto a host adapter card; and a single RAID controller configured to store data in the set of storage drives into the first DIMM and the second DIMM, wherein the first DIMM and the second DIMM are coupled to the single RAID controller, the single RAID controller is further configured to redundantly protect data stored into the first DIMM and the second DIMM, and the single RAID controller is integrated on the host adapter card. 9. The system of claim 8, wherein the single RAID controller implements a RAID level 0 to redundantly protect data stored into the first DIMM and the second DIMM. 10. The system of claim 8, wherein the single RAID controller implements a RAID level 1 to redundantly protect data stored into the first DIMM and the second DIMM. 11. The system of clam 8, wherein the single RAID controller includes a direct Memory access (DMA) engine configured to transfer data from the set of storage drives to the first DIMM and the second DIMM. 12. The system of claim 11, wherein the DMA engine has multi-channels to allow parallel transfer of data from the set of storage drives to the first DIMM and the second DIMM. 13. The system of claim 8, wherein the single RAID controller includes a firmware to virtually split each of the first DIMM and the second DIMM into multiple memory partitions. 14. The system of claim 8, wherein if either the first DIMM or the second DIMM is faulty, the faulty DIMM be replaced by another new DIMM by hot plugging.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates generally to the field of computing technology, and more particularly, to methods and structures for optimizing the performance and fault tolerance of a computing system. 2. Description of the Related Art As is well known, computer systems typically include a processor, a main memory, and a secondary storage memory. Normally, the processor is a Central Processing Unit (CPU) or a microprocessor, the main memory is Random Access Memory (RAM), and the secondary storage is a hard disk drive. As the information such as data and instructions in RAM and the hard disk drives are executed by the processor, data protection has become one of the chief concerns in designing RAM and hard disk drives. Specifically, data protection is important as valuable data stored in hard disk drives, or temporarily held in RAM, can be lost due to abnormal occurrences such as human errors, equipment failures, and adverse environmental conditions. FIG. 1 illustrates a simplified schematic diagram of a host adapter card 102 of the prior art as it includes a dedicated memory 104 , a Redundant Array of Independent Disks (RAID) Input/Output Processor (RAID IOP) adapter chip 108 , and a Small Computer System Interface (SCSI) host adapter chip 110 . As shown, the host adapter card 102 is designed to be plugged into the primary PCI bus using a plug 112 . As also shown, the RAID IOP is coupled to the dedicated memory 104 through a bus 106 . Typically, the dedicated memory 104 can be either soldered to the motherboard or be a Dual In-Line Memory Module (DIMM) that is plugged onto the host adapter card 102 or a memory chip (not shown in the Figure). Irrespective of being soldered to the motherboard or being a DIMM, the larger the size of the dedicated memory 104 is, the better the performance of the computer system will be. For that reason, use of larger memory sizes has become a predominate trend. DIMMs have specifically played a significant role in promoting the use of expanded memory, because additional DIMMs can be added as a need for additional memory arises. Despite its advantages, using DIMMs has proven to be less than reliable. That is, despite using multiple DIMMs, the failure of one DIMM to function properly is disastrous and costly, as it results in system shut down. In one example, specifically, the failure of one DIMM used on the host adapter card results in the failure of the host adapter card 102 , which ultimately causes corruption of data. In such situation, the entire computing system must be shut down causing a significant loss. Additionally, shutting down the entire computer system further creates unknown effects on system components and data stored therein. Furthermore, eliminating the problem requires the replacement of the DIMM, subsequent to which, requires the reconfiguration of the entire system. In view of the foregoing, there is a need for a new methodology and apparatus for improving the performance and fault tolerance of computer systems through improving data integrity.	<SOH> SUMMARY OF THE INVENTION <EOH>Broadly speaking, the present invention fills these needs by providing an apparatus and methods for improving the performance and increasing the fault tolerance of a computing system by using Redundant Array of Independent disks (RAID) on memory. In one implementation, the embodiments of present invention implement RAID on a dedicated memory of a host adapter card. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below. In one embodiment, a method for protecting memory is provided. The method includes reading a block of data from a storage drive. The method also includes writing the block of data to a first dual in-line module (DIMM) and a second DIMM plugged onto a single host adapter card coupled to the storage drive. The first DIMM and the second DIMM are coupled to a single Redundant Array of Independent Disks (RAID) controller on the single host adapter card. The method further includes managing the first DIMM and the second DIMM to protect the block of data. The block of data can be recovered from a non-failing DIMM in case either the first DIMM or the second DIMM fails. In another embodiment, a system for increasing a performance and fault tolerance of a computer system is provided. The system includes a set of storage drives configured to store data. The system further includes a first DIMM and a second DIMM protected by Redundant Array of Independent Disks (RAID), wherein the first DIMM and the second DIMM are plugged onto a host adapter card. In addition, the system includes a single RAID controller configured to store data in the set of storage drives into the first DIMM and the second DIMM. The first DIMM and the second DIMM are coupled to the single RAID controller. The single RAID controller is further configured to redundantly protect data stored into the first DIMM and the second DIMM. The single RAID controller is integrated on the host adapter card. The advantages of the present invention are numerous. Most notably, RAID on memory significantly increases system performance and the reliability of data in a computer system. For instance, the RAID level 0 on a host adapter card significantly improves the performance of the computer system. In one example, this occurs by using parallel reading and caching of data from a hard disk drive into a plurality of DIMMs or a plurality of virtual memory partitions. Another advantage of the present invention is that by using the RAID level 1 on memory, the highest reliability of data can be provided. Yet another advantage of performing RAID on memory is that by implementing multiple memory chips (e.g., DIMMs) to construct a dedicated array RAID array of memory on a host adapter card, the embodiments of the present invention facilitate performing of hot plugging on a faulty memory chip (e.g., DIMM). In this manner, the embodiments of the present invention substantially eliminate down time associated with shutting down the entire computing system to replace faulty memory. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.	CLAIM OF PRIORITY This application is a divisional application claiming priority under 35 U.S.C. § 120 of U.S. patent application Ser. No. 10/185,307, entitled “Method and Apparatus for RAID on Memory,” filed on Jun. 27, 2002, which is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to the field of computing technology, and more particularly, to methods and structures for optimizing the performance and fault tolerance of a computing system. 2. Description of the Related Art As is well known, computer systems typically include a processor, a main memory, and a secondary storage memory. Normally, the processor is a Central Processing Unit (CPU) or a microprocessor, the main memory is Random Access Memory (RAM), and the secondary storage is a hard disk drive. As the information such as data and instructions in RAM and the hard disk drives are executed by the processor, data protection has become one of the chief concerns in designing RAM and hard disk drives. Specifically, data protection is important as valuable data stored in hard disk drives, or temporarily held in RAM, can be lost due to abnormal occurrences such as human errors, equipment failures, and adverse environmental conditions. FIG. 1 illustrates a simplified schematic diagram of a host adapter card 102 of the prior art as it includes a dedicated memory 104, a Redundant Array of Independent Disks (RAID) Input/Output Processor (RAID IOP) adapter chip 108, and a Small Computer System Interface (SCSI) host adapter chip 110. As shown, the host adapter card 102 is designed to be plugged into the primary PCI bus using a plug 112. As also shown, the RAID IOP is coupled to the dedicated memory 104 through a bus 106. Typically, the dedicated memory 104 can be either soldered to the motherboard or be a Dual In-Line Memory Module (DIMM) that is plugged onto the host adapter card 102 or a memory chip (not shown in the Figure). Irrespective of being soldered to the motherboard or being a DIMM, the larger the size of the dedicated memory 104 is, the better the performance of the computer system will be. For that reason, use of larger memory sizes has become a predominate trend. DIMMs have specifically played a significant role in promoting the use of expanded memory, because additional DIMMs can be added as a need for additional memory arises. Despite its advantages, using DIMMs has proven to be less than reliable. That is, despite using multiple DIMMs, the failure of one DIMM to function properly is disastrous and costly, as it results in system shut down. In one example, specifically, the failure of one DIMM used on the host adapter card results in the failure of the host adapter card 102, which ultimately causes corruption of data. In such situation, the entire computing system must be shut down causing a significant loss. Additionally, shutting down the entire computer system further creates unknown effects on system components and data stored therein. Furthermore, eliminating the problem requires the replacement of the DIMM, subsequent to which, requires the reconfiguration of the entire system. In view of the foregoing, there is a need for a new methodology and apparatus for improving the performance and fault tolerance of computer systems through improving data integrity. SUMMARY OF THE INVENTION Broadly speaking, the present invention fills these needs by providing an apparatus and methods for improving the performance and increasing the fault tolerance of a computing system by using Redundant Array of Independent disks (RAID) on memory. In one implementation, the embodiments of present invention implement RAID on a dedicated memory of a host adapter card. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below. In one embodiment, a method for protecting memory is provided. The method includes reading a block of data from a storage drive. The method also includes writing the block of data to a first dual in-line module (DIMM) and a second DIMM plugged onto a single host adapter card coupled to the storage drive. The first DIMM and the second DIMM are coupled to a single Redundant Array of Independent Disks (RAID) controller on the single host adapter card. The method further includes managing the first DIMM and the second DIMM to protect the block of data. The block of data can be recovered from a non-failing DIMM in case either the first DIMM or the second DIMM fails. In another embodiment, a system for increasing a performance and fault tolerance of a computer system is provided. The system includes a set of storage drives configured to store data. The system further includes a first DIMM and a second DIMM protected by Redundant Array of Independent Disks (RAID), wherein the first DIMM and the second DIMM are plugged onto a host adapter card. In addition, the system includes a single RAID controller configured to store data in the set of storage drives into the first DIMM and the second DIMM. The first DIMM and the second DIMM are coupled to the single RAID controller. The single RAID controller is further configured to redundantly protect data stored into the first DIMM and the second DIMM. The single RAID controller is integrated on the host adapter card. The advantages of the present invention are numerous. Most notably, RAID on memory significantly increases system performance and the reliability of data in a computer system. For instance, the RAID level 0 on a host adapter card significantly improves the performance of the computer system. In one example, this occurs by using parallel reading and caching of data from a hard disk drive into a plurality of DIMMs or a plurality of virtual memory partitions. Another advantage of the present invention is that by using the RAID level 1 on memory, the highest reliability of data can be provided. Yet another advantage of performing RAID on memory is that by implementing multiple memory chips (e.g., DIMMs) to construct a dedicated array RAID array of memory on a host adapter card, the embodiments of the present invention facilitate performing of hot plugging on a faulty memory chip (e.g., DIMM). In this manner, the embodiments of the present invention substantially eliminate down time associated with shutting down the entire computing system to replace faulty memory. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements. FIG. 1 illustrates a simplified block diagram of a host adapter card in accordance with the prior art. FIG. 2 depicts a simplified schematic diagram of a computer system having a RAID array of virtual dedicated memory partitions, in accordance with one embodiment of the present invention. FIG. 3A is a simplified schematic diagram illustrating the achievement of higher performance through striping of data using RAID array of dedicated memory partitions, in accordance with yet another embodiment of the present invention. FIG. 3B is a simplified schematic diagram showing a plurality of DIMMs forming a RAID array of memory, in accordance with still another embodiment of the present invention. FIG. 3C is a simplified schematic diagram depicting striping of data from a RAID array of hard disks into a RAID array of virtual memory partitions, in accordance with still another embodiment of the present invention. FIG. 4A is a simplified schematic diagram illustrating a RAID level 1 on memory, in accordance with yet another embodiment of the present invention. FIG. 4B is a simplified schematic diagram illustrating caching of data from a RAID level 1 on hard disk drives to a RAID level 1 on memory constructing from a multiple DIMMs, in accordance with yet another embodiment of the present invention. FIG. 5 is a simplified schematic diagram of a computer system including a plurality of dedicated virtual memory partitions, in accordance with yet another embodiment of the present invention. FIG. 6 is a flowchart diagram of method operations performed in hot plugging a faulty DIMM, in accordance with yet another embodiment of the present invention. FIG. 7 is a flowchart diagram of method operations performed in hot plugging a single DIMM, in accordance with yet another embodiment of the present invention. FIG. 8 is a flowchart diagram of method operations performed in upgrading a DIMM through hot plugging, in accordance with yet another embodiment of the present invention. FIG. 9 is a flowchart diagram of method operations in performing a RAID level 1 on memory on a plurality of DIMMs, in accordance with yet another embodiment of the present invention. FIGS. 10A-10H illustrate a plurality of exemplary Graphic User Interfaces (GUI) in a RAID on Memory Utility, in accordance with yet another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An invention for computer implemented methods for increasing the performance and the fault tolerance of a computing system through ensuring integrity of data, is provided. Preferably, the embodiments of the present invention implement Redundant Array of Independent (Inexpensive) Disks (RAID) on Memory to improve the performance and the reliability of data in a dedicated memory of a host adapter card. In one example, RAID on memory includes a plurality of virtual memory partitions. In a different implementation, RAID on memory includes a plurality of memory chips. In one example, the memory chips implemented are DIMMs. By way of example, in a RAID level 0 on memory data, within a hard disk drive is stripped between a plurality of DIMMs, or a plurality of virtual memory partitions. In a different example, a RAID level 1 on memory, data within a hard disk is read and cached into a pair of DIMMs or two virtual memory partitions. Preferably, implementing multiple DIMMs enables the hot plugging of a faulty DIMM. Reference is now made to FIG. 2 illustrating a simplified schematic diagram of a computer system 200 having a RAID on memory including a plurality of dedicated virtual memory partitions 204a and 204b, in accordance with one embodiment of the present invention. The computer system 200 includes a host processor 214, a primary Peripheral Component Interconnect (PCI) bus 218, a host memory 216, a host adapter card 202, and a RAID array of hard disk drives 212. The host processor 214 and the host memory 216 are coupled to the primary PCI bus 218. The host processor 214 processes information such as data and instructions while the host memory 216 stores and provides information to the processor 214. The primary PCI bus provides a high speed data path between the CPU 214 and the connected peripheral devices so as to provide additional functionality. For instance, the RAID array of hard disk drives 212 is connected to the primary PCI 218 through a host adapter card 202. The host adapter card 202 is coupled to a secondary PCI bus 222 that is coupled to the PCI-system bus bridge 220. The host adapter card 202 is configured to interface and control access to the RAID array of hard disk drives 212. The host adapter card 202 includes a RAID Input/Output Processor (RAID IOP) 208, a dedicated memory 204, and a SCSI controller 210. The RAID IOP 208 includes a Direct Memory Access (DMA) engine 209 configured to transfer data from the RAID array of hard disk drives 212 to one or more of virtual memory partitions 204a and 204b of the RAID array of virtual memory partitions 204. In one example, the DMA engine has multi-channels thus allowing parallel transfer of data from any of the hard disk drives 212a and 212b to any of virtual memory partitions 204a and 204b of the RAID array of virtual memory partitions 204. In one embodiment, the RAID IOP further includes a memory controller 211 configured to interface and control access to the virtual memory partitions 204a and 204b of the RAID array of virtual memory partitions 204. Achieving higher performance through striping of data using RAID array of dedicated memory partitions 204 can further be understood with respect to the simplified schematic diagram shown in FIG. 3A, in accordance with one embodiment of the present invention. As shown, data stored in the RAID array of hard disk drives 212 is cached into the RAID array of dedicated memory partitions 204. The RAID array of hard disk drives 212 includes a plurality of hard disk drives 212a through 212n. One container 212′ shows two hard drives 212a and 212b respectively transferring 64 Mbytes of data in portions 214a and 214b using a stripping technique. Each portion 214a and 214b writes 32 Mbytes of data in 204a-1 and 204b-1, and 204a-2 and 204b2 of virtual memory partitions 204a and 204b, correspondingly. In one exemplary embodiment, a plurality of parameters of a desired memory RAID level is provided to the DMA engine 209 of the RAID IOP 208. For instance, in the embodiment of FIG. 3A, a desired RAID level 0, which is memory striping, is provided to the RAID IOP 208. That is, data stored in the RAID array of hard disk drives 212 are interleaved across multiple virtual memory partitions 204a and 204b, providing increased performance. As shown, a portion of the hard disk drive 212a of the RAID array of hard disk drives 212 operates on data sectors totaling 64 MB, which under RAID on memory level 0 is configured to be stripped between the virtual memory partition 204a and 204b, equally. That is, the data contents of the portion 214a of the hard disk drive 212a is read and subsequently interleaved equally between the virtual memory partitions 204a and 204b. By way of example, using 213a, a first 32 Mbytes of data in the hard disk 212a is read and then cached in 204a-1 of the virtual memory partition 204a. Then, using the 213a′, a second 32 Mbytes of data in the hard disk drive 212a is read and cached in 204b-1 of the virtual memory partition 204b. Similarly, a first portion of data stored within hard disk drive 212b is read and cached in 204a-2 of virtual memory partition 204a using 213b. In a like manner, a second portion of data stored within the hard disk drive 212b is read and cached into a 204b-2 of the virtual memory partition 204b. In one example, the DMA engine is designed such that it is multi-channeled giving the DMA engine the capability to transfer the first and second portions of data within the hard disk drive 212a in parallel. In this manner, advantageously, the period of time required to read the entire 64 Mbytes of data stored within the hard disk drive 212a is reduced substantially by half. In a like manner, reading of the first and second portions of data stored within the hard disk drive 212b and caching same into the first and second virtual memory partitions is reduced substantially by half. Additionally, it must be noted that in a different embodiment, the time required to read data stored in each of the hard disk drives 212a and 212b may be reduced by caching the stored data within each of the hard disk drives 212a and 212b into three or four (i.e., more than two) virtual memory partitions. In this manner, the time required to read the 64 Mbytes of data stored in each portion 214a and 214b of the corresponding hard disk drives 212a and 212b can be reduced by one-third and one-fourth, respectively. In a different implementation, as shown in FIG. 3B, a plurality of DIMMs 204 and 204′ can be used to cache data read from each of the hard disk drives 212a and 212b, in accordance with one embodiment of the present invention. In this example, the first portion of the 64 Mbytes data stored in the hard disk drive 212a is read and then cached into a 204-1 of a DIMM 204 using 213a. In a same manner, the second portion of data stored in hard disk drive 212a is read and cached into a 204′-1 of a DIMM 204′ using 213a′. As shown, as a result of being multi-channeled, the DMA engine 209 is capable of reading the first portion and the second portion of data in the hard disk drive 212a in parallel, reducing the time required for caching the entire data by half. Similarly, the first portion of data stored in the hard disk drive 212b is read and then cached into 204-2 of DIMM 204 using 213a′. Then, the second portion of data stored in the second hard disk drive 212b is read and cached into 204′-2 of DIMM 204′ using 213b′. Thus, again, the multi-channel DMA engine 209 enables the parallel reading of the first and second portions of the hard disk drive 212b as well as parallel caching of the first and second portions of the data in 204-2 of DIMM 204 and 204′-2 of DIMM 204′. Data read from each of the hard disk drives 212a and 212b is beneficially interleaved between two DIMMs, in parallel, thus reducing the time required to read and write data substantially by half. It must be noted that although the embodiments of the present invention are shown to include DIMMs, one having ordinary skill in the art should appreciate that any suitable memory chip can be implemented to store data (e.g., memory sticks, Single In-line Memory Module (SIMMs), etc.) Reference is made to FIG. 3C depicting the striping of data from the RAID array of hard disk drives 212 into a RAID array of virtual memory partitions 204, in accordance with one embodiment of the present invention. As shown, the memory 204 has been virtually divided into four partitions of 204a through 204d. In one example, a first portion of data stored within the hard disk drive 212a is cached and stripped into 204a-1, the second portion of data stored within the hard disk drive 212a is cached and interleaved into 204b-1, a third portion of data stored within the hard disk drive 212a is cached and interleaved into 204c-1, and a fourth portion of data stored within the hard disk drive 212a is cached and interleaved into 204d-1, respectively. Similarly, the first portion of data stored within the hard disk drive 212b is cached and interleaved into the 204a-2 of the first virtual memory partition 204a, the second portion of data stored within the hard disk drive 212b is cached and interleaved into the 204b-2 of the second virtual memory partition 204b, the third portion of data stored within the hard disk 212b is cached and interleaved into 204c-2 of the third virtual memory partition 204c, and the fourth portion of data stored within the hard disk 212b is cached and interleaved into 204d-2 of the fourth virtual memory partition 204d, correspondingly. In one exemplary embodiment, each of the first portions of the hard disks 212a and 212b are cached into 204a-1 and 204a-2 using 213a and 213b. In a like manner, each of the second portions of the hard disks 212a and 212b are cached into 204b-1 and 204b-2 using 213a′ and 213b′; each of the third portions of the hard disks 212a and 212b are cached into 204c-1 and 204c-2 using 213a″ and 213b″; and each of the fourth portions of the hard disks 212a and 212b are cached into 204d-1 and 204d-2 using 213a′″ and 213b′″. This is specifically made possible by the multi-channel DMA engine capable of reading and caching data from multiple hard disk drives into multiple virtual memory partitions of the memory. Turning to FIG. 4A, implementing a RAID level 1 on memory can further be understood, in accordance with one embodiment of the present invention. The RAID level 1 on memory is mirroring which is one-hundred percent duplication of data within the disks. In the embodiment of FIG. 4A, data within the hard disk drive 212a and 212b are duplicates, providing higher system reliability. In accordance to one example, data stored within the hard disk drive 212a (e.g., a data portion 214a of 64 MB) is read and cached into the first virtual memory partition 204a. Similarly, data stored within the hard disk drive 212b (e.g., a data portion 214b of 64 MB) is read and cached into the virtual memory partition 204b, in parallel. As discussed in more detail above, parallel caching of data stored within the hard disk drives 212a and 212b has been made possible using the multi-channel DMA engine 209 and the virtual splitting of the memory into two virtual partitions, each having a size of 64 MB. Each of the first and second memory partitions 204a and 204b having the size of 64 Mbytes is capable of caching in 64 Mbytes of data, which in this embodiment, are identical. Of course, memory can have much larger sizes, but for purposes of example, 64 Mbytes is used. In this manner, data duplicated within the hard disk drives 212a and 212b are also duplicated in virtual memory partitions 204a and 204b, increasing the reliability of the system. As a consequence, a corruption of data cached into the second virtual memory partition 204b will have no significant negative effect, as an identical copy of the data is cached into the first virtual memory partition 204a. Thus, the RAID level 1 on memory of the present invention beneficially increases the fault tolerance of the system. In a different example, as shown in FIG. 4B, multiple DIMMs can be implemented to cache duplicated data stored within the hard disk drives 212a and 212b using the RAID level 1 on memory of the present invention, in accordance with one embodiment of the present invention. As illustrated, data portion 214a stored within the hard disk drive 212a having a size of 64 Mbytes or larger is read and cached into a first DIMM 204 while data portion 214b stored within the hard disk drive 212b is read and cached into the second DIMM 204′. Each of the first DIMM and the second DIMM 204 and 204′ has a size of 64 Mbytes, as shown in 204-1 and 204′-1 and each has a respective address of X and Y. That is, when different DIMMs are implemented to cache duplicated data, the caching of data is facilitated by using each of the addresses of the first and second DIMMs 204 and 204′. Again, in this embodiment, duplicated data stored within the hard disk drives 212a and 212b are cached into two different DIMMs 204 and 204′, despite the data within the two hard disk drives 212a and 212b being duplicate. In this manner, corruption of data within the first and second DIMMs 204 or 204′, respectively, has a minimal negative effect on the system. A simplified schematic diagram of a computer system 500 having a RAID array on memory of a plurality of virtual memory partitions 204a and 204b is illustrated in FIG. 5, in accordance with one embodiment of the present invention. The computer system 500 includes a host processor (CPU) 214, a primary Peripheral Component Interconnect (PCI) bus 218, a host memory 216, a host adapter card 202, and a RAID array of hard disk drives 212. The primary PCI bus provides a high speed data path between the CPU 214 and the connected peripheral devices. The RAID array of hard disk drives 212 is connected to the primary PCI 218 through a host adapter card 202. The secondary PCI bus 222 is coupled to the PCI-system bus bridge 220. The host adapter card 202 interfaces and controls access to the RAID array of hard disk drives 212. The host adapter card 202 includes a RAID Input/Output Processor (RAID IOP) 208, a RAID array of dedicated memory 204, and a SCSI controller 210. The RAID IOP 208 includes a Direct Memory Access (DMA) engine 209, firmware 217, and a controller 211. The DMA engine is configured to transfer data from the RAID array of hard disk drives 212 to one or more of virtual memory partitions 204a and 204b of the dedicated RAID array of memory 204. In one example, the DMA engine 209 has multi-channels, thus allowing parallel transfer of data from any of the hard disk drives 212a and 212b to any of virtual memory partitions 204a and 204b of the dedicated RAID array of memory 204. The memory controller 211 interfaces and controls access to the virtual memory partitions 204a and 204b of the dedicated RAID array of memory 204 implementing 206a and 206b, respectively. The firmware 217 is a software interface configured to run on the RAID IOP. In one example, the RAID parameters (e.g., RAID level, necessary number of virtual memory partitions, number of containers, etc.) are defined by the firmware 217. The firmware 217 then implements the parameters to virtually split the dedicated memory 204. Thus, the firmware 217 is aware of the number of virtual memory partitions and their associated addresses. FIG. 6 illustrates a flow chart 600 of method operations performed in hot plugging a faulty DIMM, in accordance with one embodiment of the present invention. The method begins in operation 602 in which the host adapter card is configured so as to include more than one DIMM. Then, in operation 604, an error is detected in one of the DIMMs. For instance, depending on the situation, the error may be having a faulty DIMM or having corrupted data on one of the DIMMs. Proceeding to operation 604, it is determined that the error is due to having a faulty DIMM. Upon making such detection, in operation 608, a user's input to replace the faulty DIMM is received. In one example, the user is configured to interact using a RAID interface software such as Storage Manager Professional (SMPro) or Storage Manager on ROM (SMOR), both of which are RAID software interfaces developed by Adaptec of Milpitas in California. Continuing to operation 610, the integrity of data in the faulty DIMM is ensured by reading out data content of the faulty DIMM. Next, in operation 612, the faulty DIMM is hot plugged. As used herein, “hot plugging a DIMM” is defined as shutting down the power to the existing DIMM in the computer system thus allowing the removal of same while the computer system power and the host adapter card power are still on and operating. Thus, in operation 612, the power to the faulty DIMM is shut down, which in one embodiment, is performed by the firmware. Next, in operation 614, the faulty DIMM is removed and replaced. Upon replacing the faulty DIMM, in operation 616, connection is established to the replaced DIMM. In one instance, the firmware restores power to the replaced DIMM. Then, in operation 618, the data content of the faulty DIMM is restored into the replacement DIMM. In this manner, the integrity of data cached into a plurality of DIMMs forming a RAID array of memory is beneficially ensured without the necessity of shutting down the power to the entire system. Turning to flowchart diagram 700 of method operations shown in FIG. 7, hot plugging a DIMM can further be understood, in accordance with one embodiment of the present invention. The method begins in operation 702, in which the host adapter card is configured to include a single DIMM followed by operation 704 wherein an error is detected in the DIMM. In one instance, it may be detected that the DIM is faulty while in a different embodiment, it may be determined that data to be cached into the DIMM is corrupted. Next, in operation 706, the user is provided with different mechanisms to recover data in the DIMM, depending on the error occurring during reading of data from the host memory or from the operating system. For instance, the error may have occurred during reading of data from the operating system in the computer system that includes RAID on hard disk drives. In such situation, if RAID level 0 is implemented, the portion of valid data that is still available is recovered and the user is informed of the loss of a portion of the data. If RAID level 1 is implemented, the copy of the data is implemented to restore the data in the faulty DIMM. If RAID level 5 is used, the lost data is regenerated. In a different scenario, where error has occurred during reading of data from host memory, a copy of the data may be recovered using the data in the host memory. Continuing to operation 708, the user input to replace the DIMM is received. In one example, the interface between the user and the RAID on memory may be SMPro or SMOR. Next, in operation 710, the DIMM is hot plugged. That is, the power to the DIMM is shut down while the system power is still on. Then, the DIMM is removed and replaced in operation 712, which is followed by operation 714 wherein the connection to the replaced DIMM is established. In operation 716, the data recovered in operation 706 is restored into the replaced DIMM, if such request has been made by the user. Thus, data in one DIMM can be recovered implementing the hot plug feature of the present invention, beneficially eliminating the necessity to shut down the system power. In this manner, the loss of memory and the valuable time associated with shutting down the system as well as reconfiguring the system is reduced. The method operations in upgrading a DIMM by hot plugging the DIMM is illustrated in the method operations of flowchart 800 depicted in FIG. 8, in accordance with one embodiment of the present invention. The method begins in operation 802 in which a user's decision to upgrade a DIMM is received. Next, in operation 804, the user's decision is communicated to the firmware defined on RAID IOP. In one example, the SMPro or SMOR software is used to provide interaction between the firmware and the user. Continuing to operation 806, the selected DIMM is hot plugged. That is, the power connected to the selected DIMM is shut down. This is advantageous, as in contrast to the prior art, the embodiments of the present invention do not necessarily have to use the operating system, the drivers, and application layers to interact with the firmware so as to hot plug the DIMM That is, in the embodiments of the present invention, depending on the operating system environment, the user can implement the operating system and one of the RAID user interfaces to communicate with the firmware almost directly. Thus, the embodiments of the present invention advantageously enable a user to hot plug the DIMM rather than shutting down the entire system or the host adapter card. In operation 806, the old DIMM is replaced with an upgraded DIMM. For instance, a DIMM having a 64 Mbytes memory size is upgraded to a DIMM having a 128 Mbytes memory size. Then, in operation 810, connection is established to the upgraded DIMM. That is, the firmware restores power to the replaced DIMM. Thereafter, in operation 812, the user is informed of the status of the upgraded DIMM. In one embodiment, SMPro or SMOR software interface is implemented to interact with the user. FIG. 9 depicts the flowchart 900 of method operations performed in RAID level 1 on a plurality of DIMMs forming a RAID array of memory, in accordance with one embodiment of the present invention. The method begins in operation 902 in which a hard disk having data stored therein is provided. Next, in operation 904, a portion of data stored in the hard disk is read and is then written on a first address on a DIMM in operation 906. Proceeding to operation 908, the portion of data read in operation 904 is written to a second address located on a different DIMM. In this manner, data stored in a portion of a single hard disk drive is read and written into two DIMMs, increasing the reliability of data in a dedicated memory. In one example, using different addresses to write data is an indication of having physically different DIMMs. FIGS. 10A-10G illustrate a plurality of exemplary Graphic User Interfaces (GUI) in a RAID On Memory Utility, in accordance with one embodiment of the present invention. In one example, upon booting the system, the RAID on Memory utility is initiated checking on substantially all DIMMs within the dedicated memory. As shown, the utility verifies the number of DIMMs in the system and provides the user with such information. Upon detecting the number of active DIMMs, using dialog boxes 1004 and 1006, the user is informed of the detection of the two DIMMs. Thereafter, continuing with the initialization process, in boxes 1008 and 1010, the user is informed of the detection of an error in DIMM 1. Using boxes 1012 and 1014, the user is informed as to the need to replace DIMM 1. Using boxes 1016-1026, the user is given an option to replace DIMM 1. As shown, in boxes 1020 and 1022, the user has selected to replace DIMM 1. In boxes 1028 and 1030, the user is given the option to initiate the hot plugging of DIMM 1. As shown, the user is given an option to either press the start button 1034 or an exit button 1036 to leave the RAID on Memory utility. The user is further given an opportunity to seek help using the help button 1032. Continuing to FIG. 10B, the progress of the RAID on Memory utility is shown in further detail. Implementing the box 1038, the user is informed of the initiation of hot plugging of DIMM 1. Then, in box 1040 depicted in FIG. 10C, the user is informed that data content of DIMM 1 is read followed by a box 1042, in which the power is shut down to DIMM 1. Next, in box 1044, the user is instructed to replace DIMM 1 followed by a request in box 1046 requesting pressing of a continue button 1048. The power to DIMM 1 is then restored as shown in box 1050 of FIG. 10F. Following the restoring of power to DIMM 1, the data content of DIMM 1 is restored as shown in box 1052 of FIG. 10G. As shown in box 1054, the user is then informed of the successful restoring of data to DIMM 1 confirmed by a done button 1056. It must be appreciated by one having ordinary skill in the art that the SCSI controller of the present invention may be integrated into a motherboard of computer systems as opposed to being on an adapter card. Additionally, the present invention may be implemented using an appropriate type of software driven computer-implemented operation. As such, various computer-implemented operations involving data stored in computer systems to drive computer peripheral devices (i.e., in the form of software drivers) may be employed. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. Further, the manipulations performed are often referred to in terms such as ascertaining, identifying, scanning, or comparing. Any of the operations described herein that form part of the invention are useful machine operations. Any appropriate device or apparatus may be utilized to perform these operations. The apparatus may be specially constructed for the required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general purpose machines may be used with computer programs written in accordance with the teachings herein, where it may be more convenient to construct a more specialized apparatus to perform the required operations. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.	G	60G06	161G06F	11	08
11744758	US20070204252A1-20070830	Methods and Systems for Placement	ACCEPTED	20070815	20070830	[]	G06F1750	["G06F1750"]	7669160	20070504	20100223	716	009000	98137.0	TAT	BINH	[{"inventor_name_last": "Furnish", "inventor_name_first": "Geoffrey", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "LeBrun", "inventor_name_first": "Maurice", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Bose", "inventor_name_first": "Subhasis", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}]	Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations. The forces are optionally selectively modulated as a function of simulation time. The placements of the devices are compatible with various design flows, such as standard cell, structured array, gate array, and field-programmable gate array.	1. A method of generating a cell placement from a circuit netlist, the method comprising: modeling the circuit netlist as an analogous continuous dynamic physical system of nodes and nets of a first plurality of the nodes, wherein a second plurality of the nodes are represented by analogous physical state variables including position and velocity; formulating a system of continuous coupled simultaneous ordinary differential equations describing motion of the nodes and the nets in accordance with a plurality of forces including attractive and spreading forces; and integrating the equations of motion to at least approximate a continuous evolution of the analogous physical state variables over time. 2. The method of claim 1, wherein the analogous physical state variables representing the second plurality of nodes further include mass. 3. The method of claim 1, further wherein; the cell placement is adapted for use in a circuit layout to specify locations for a plurality of cells, the circuit netlist representing the cells and interconnect between the cells, the circuit layout including the cell placement; and the modeling, the formulating, and the integrating are performed at least in part to perform a global placement that determines an initial placement of the cells. 4. The method of claim 3, wherein the circuit layout further includes routing of the interconnect. 5. The method of claim 1, wherein at least some of the attractive forces include connectivity forces corresponding to at least some interconnections described by the circuit netlist. 6. The method of claim 5, wherein the connectivity forces bias movement of at least a portion of the nodes to shorten at least some of the interconnections. 7. The method of claim 1, wherein at least some of the attractive forces include retention forces corresponding to at least some grouping constraints arising from predetermined requirements. 8. The method of claim 7, wherein the predetermined requirements include layout floorplanning requirements. 9. The method of claim 1, wherein at least some of the spreading forces correspond to spatial concentrations of at least some of the nodes. 10. The method of claim 1, wherein at least some of the spreading forces include exclusion forces corresponding to predetermined layout floorplan constraints. 11. The method of claim 10, wherein the layout floorplan constraints include reserved locations for at least some floorplan elements. 12. The method of claim 1, wherein at least a portion of the circuit netlist is a gate-level netlist. 13. A computer readable medium having a set of instructions stored therein which when executed by a processing device causes the processing device to perform procedures comprising: modeling a circuit netlist as an analogous continuous dynamic physical system of nodes and nets of a first plurality of the nodes, wherein a second plurality of the nodes are represented by analogous physical state variables including position, velocity, and mass; formulating a system of continuous coupled simultaneous ordinary differential equations describing motion of the nodes and the nets in accordance with a plurality of forces including attractive and spreading forces; integrating the equations of motion to at least approximate a continuous evolution of the analogous physical state variables over time; and generating a cell placement from the circuit netlist in accordance with the modeling, the formulating, and the integrating. 14. The computer readable medium of claim 13, wherein at least some of the attractive forces include connectivity forces corresponding to at least some interconnections described by the circuit netlist. 15. The computer readable medium of claim 13, wherein at least some of the attractive forces include retention forces corresponding to at least some grouping constraints determined from predetermined requirements. 16. The computer readable medium of claim 13, wherein at least some of the spreading forces correspond to spatial concentrations of at least some of the nodes. 17. The computer readable medium of claim 13, wherein at least some of the spreading forces include exclusion forces corresponding to predetermined layout floorplan constraints. 18. The computer readable medium of claim 13, wherein at least a portion of the circuit netlist is a gate-level netlist. 19. A method comprising: modeling a circuit netlist as an analogous continuous dynamic physical system of nodes and nets of a first plurality of the nodes, wherein a second plurality of the nodes are represented by analogous physical state variables including position, velocity, and mass; integrating a system of continuous coupled simultaneous ordinary differential equations describing motion of the nodes and the nets in accordance with a plurality of forces to at least approximate a continuous evolution of the analogous physical state variables over time; and generating a cell placement from the circuit netlist in accordance with the modeling, the formulating, and the integrating. 20. The method of claim 19, wherein at least one of the forces is an attractive connectivity force corresponding to at least one interconnection described by the circuit netlist. 21. The method of claim 19, wherein at least one of the forces is an attractive retention force corresponding to at least one grouping constraint determined from predetermined requirements. 22. The method of claim 19, wherein at least one of the forces is a spreading force corresponding to at least one spatial concentration of at least a portion of the nodes. 23. The method of claim 19, wherein at least one of the forces is an exclusion spreading force corresponding to at least one predetermined layout floorplan constraint. 24. The method of claim 19, wherein at least a portion of the circuit netlist is a gate-level netlist. 25. A system comprising: means for modeling a circuit netlist as an analogous continuous dynamic physical system of nodes and nets of a first plurality of the nodes, wherein a second plurality of the nodes are represented by analogous physical state variables including position, velocity, and mass; means for integrating a system of continuous coupled simultaneous ordinary differential equations describing motion of the nodes and the nets in accordance with a plurality of forces to at least approximate a continuous evolution of the analogous physical state variables over time; and means for generating a cell placement from the circuit netlist in accordance with the means for modeling, the means for formulating, and the means for integrating. 26. The system of claim 25, wherein the forces comprise attractive forces and spreading forces. 27. The system of claim 26, wherein at least some of the attractive forces include connectivity forces corresponding to at least some interconnections described by the netlist.	<SOH> BACKGROUND <EOH>1. Field Advancements in integrated circuit design, including placement and routing of elements in a Computer Aided Design (CAD) context, are needed to provide improvements in performance, efficiency, and utility of use. 2. Related Art Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes.	<SOH> BRIEF DESCRIPTION OF DRAWINGS <EOH>FIG. 1 is a flow diagram illustrating selected details of an embodiment of placing, routing, analyzing, and generating fabrication data for any portion of an integrated circuit according to a Simultaneous Dynamical Integration (SDI)-based flow. FIG. 2 is a flow diagram illustrating selected details of an embodiment of placing and routing any portion of an integrated circuit according to an SDI-based flow. FIG. 3A is a flow diagram illustrating selected details of an embodiment of global placement according to SDI-based modeling and simulation. FIG. 3B is a flow diagram illustrating selected details of an embodiment of initial placement operations for global placement. FIG. 3C is a flow diagram illustrating selected details of an embodiment of density field based force component computation. FIG. 3D is a flow diagram illustrating selected details of an embodiment of gate density accumulation. FIG. 3E is a conceptual diagram illustrating an embodiment of two-point interpolation of node mass to grid points. FIG. 3F is a conceptual diagram illustrating an embodiment of three-point interpolation of node mass to grid points. FIG. 3G is a conceptual diagram illustrating an embodiment of applying boundary grid point masses to interior grid points. FIG. 3H is a flow diagram illustrating selected details of an embodiment of digital density filtering. FIG. 3I is a flow diagram illustrating selected details of an embodiment of interpolating gate fields to nodes. FIG. 4 is a flow diagram illustrating selected details of an embodiment of SDI-based modeling and simulation. FIG. 5A is a flow diagram illustrating selected details of a first embodiment of resource reconciliation, as a first example of legalization. FIG. 5B is a flow diagram illustrating selected details of a second embodiment of resource reconciliation, as a second example of legalization. FIG. 5C is a flow diagram illustrating selected details of an embodiment of partitioning. FIG. 6 is a flow diagram illustrating selected details of an embodiment of detailed placement (also referred to as detail placement elsewhere herein). FIG. 7A is a flow diagram illustrating selected aspects of an embodiment of delay path reduction and minimization, as an example of timing closure. FIG. 7B illustrates a conceptual view of selected elements of an embodiment of timing-driven forces. FIG. 7C illustrates a spatial organization of the driver and the coupled loads of FIG. 7B . FIG. 7D illustrates an embodiment of Net Boundary Box (NBB) estimation of routing to cover the driver and the loads of FIG. 7C . FIG. 7E illustrates an embodiment of a rectilinear Steiner Route Tree (SRT) estimation to cover the driver and loads of FIG. 7C . FIG. 7F illustrates an embodiment of estimated RC parasitics associated with the RST of FIG. 7E . FIGS. 8A and 8B collectively are a flow diagram illustrating selected details of an embodiment of an integrated circuit Electronic Design Automation (EDA) flow using one or more techniques including SDI-directed global placement, legalization, legalization-driven detailed placement, timing optimization, and routing. FIG. 9 illustrates selected details of an embodiment of manufacturing integrated circuits, the circuits being designed in part based on SDI-directed design techniques. FIG. 10 illustrates selected details of an embodiment of a computer system to execute EDA routines to perform SDI-directed place and route operations. FIG. 11 illustrates an embodiment of an SDI-based detailed placement flow. FIGS. 12A and 12B illustrate concepts relating to an embodiment of netlist elaboration. FIG. 13 illustrates an embodiment of detailed placement of a Q-block. FIG. 14 illustrates an embodiment of an additional pass of detailed placement of a Q-block. FIG. 15A illustrates a form of the form-level net of FIG. 12A . In this view the resource-level nodes are shown internal to the form. FIG. 15B illustrates another form that uses different resources to implement the same function as the form of FIG. 15A . In at least one embodiment, the form of FIG. 15B is substituted for the form of FIG. 15A through a morphing process. FIG. 16A illustrates the supply and demand for resources R 1 through R 6 corresponding to target functions of an integrated circuit design having a first selection of forms for the target functions. For at least some of the resources, the demand exceeds the available supply. FIG. 16B illustrates the supply and demand for resources R 1 through R 6 for the same target functions, but using a second selection of forms for the target functions obtained by morphing certain forms to use different resources. For each of the resources shown, the demand is less than or equal to the supply. FIG. 17A illustrates an example circuit with a plurality of critical paths. FIG. 17B illustrates example computations relating to an embodiment of CPF scoring. FIG. 18 illustrates an embodiment of a cascade of buffers of increasing drive strength. FIG. 19 illustrates example computations relating to an embodiment of SDF calculation. FIG. 20A illustrates an overall procedural control flow in an illustrative relative slack embodiment. FIG. 20B illustrates the adjustment of timing driven weight in the relative slack embodiment of FIG. 20A . FIG. 21A illustrates a driver in the interior of a net bounding box region. FIG. 21B illustrates a driver to one side of a net bounding box region. FIGS. 22A and 22B illustrate an example circuit excerpt before and after processing according to an embodiment of timing driven buffering and resizing for an array architecture. FIG. 23 illustrates a flow diagram of an integrated circuit design flow including an embodiment of processing in accordance with an embodiment of timing driven buffering and resizing for an array architecture. FIG. 24A illustrates a top-level view of an embodiment of timing driven buffering and resizing for an array architecture. FIG. 24B illustrates a detail view of selected details of an embodiment of timing driven resizing for an array architecture. FIGS. 25A and 25B illustrate an example route tree as processed by an embodiment of segmenting a portion of the route for timing driven buffering and resizing. FIG. 26 illustrates example results of an embodiment of logic replication and tunneling for an array architecture. FIG. 27 illustrates a control flow in an illustrative embodiment, as used for density modification. FIG. 28 illustrates a control flow of an illustrative embodiment, as used to determine the Steiner-cuts congestion term on the SDI grid. FIG. 29 illustrates procedures of an illustrative embodiment, showing creation of a congestion array. FIG. 30 illustrates procedures of an illustrative embodiment, showing calculation of a final congestion density enhancement array. FIG. 31 illustrates an embodiment of a processing flow for node tunneling out of exclusion zones in an SDI-based integrated circuit design flow. FIG. 32 illustrates an embodiment of SDI-related force calculations in a tunneling congestion relief context. FIG. 33 illustrates an embodiment of evaluation of tunneling transition criteria. FIG. 34A illustrates an example clock tree suitable for input to a Clock Tree Synthesis (CTS) tool for Structured Array Fabric (SAF)-based design flows. FIG. 34B illustrates an example clock tree output from the CTS tool operating on the input illustrated in FIG. 34A . FIG. 34C illustrates an example clock tree network. FIG. 35 illustrates an overview of an embodiment of a CTS flow. FIG. 36A illustrates an example die floorplan of a design having embedded Random Access Memory (RAM) or other Intellectual Property (IP) blocks. FIG. 36B illustrates a portion of a clock net in a context of a portion of FIG. 36A . FIG. 37A illustrates an example of timing driven pin swapping. FIG. 37B illustrates an example of effects of clock tree partitioning. FIG. 38 illustrates an analysis according to an embodiment of clock domain and sub-domain partitioning. detailed-description description="Detailed Description" end="lead"?	CROSS REFERENCE TO RELATED APPLICATIONS Priority benefit claims for this application are made in the accompanying Application Data Sheet, Request, or Transmittal (as appropriate, if any). To the extent permitted by the type of the instant application, this application incorporates by reference for all purposes the following applications, all owned by the owner of the instant application: PCT Application Serial No. PCT/US2006/025294 (Docket No. LS.2006.01B), filed Jun. 28, 2006, first named inventor Geoffrey Mark Furnish, and entitled METHODS AND SYSTEMS FOR PLACEMENT; U.S. Provisional Application Ser. No. 60/805,086 (Docket No. LS.2006.01PB), filed Jun. 18, 2006, first named inventor Geoffrey Mark Furnish, and entitled METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING; U.S. Provisional Application Ser. No. 60/804,826 (Docket No. LS.2006.14), filed Jun. 15, 2006, first named inventor Geoffrey Mark Furnish, and entitled SIMULTANEOUS DYNAMICAL INTEGRATION APPLIED TO DETAILED PLACEMENT U.S. Provisional Application Ser. No. 60/804,690 (Docket No. LS.2006.13), filed Jun. 14, 2006, first named inventor Subhasis Bose, and entitled GENERALIZED CLOCK TREE SYNTHESIS FOR STRUCTURED ARRAY FABRIC; U.S. Provisional Application Ser. No. 60/804,643 (Docket No. LS.2006.11), filed Jun. 13, 2006, first named inventor Maurice J. LeBrun, and entitled TUNNELING AS A BOUNDARY CONGESTION RELIEF MECHANISM; U.S. Provisional Application Ser. No. 60/804,574 (Docket No. LS.2006.05), filed Jun. 13, 2006, first named inventor Maurice J. LeBrun, and entitled INCREMENTAL RELATIVE SLACK TIMING FORCE MODEL; U.S. Provisional Application Ser. No. 60/804,448 (Docket No. LS.2006.10), filed Jun. 12, 2006, first named inventor Maurice J. LeBrun, and entitled NODE SPREADING VIA ARTIFICIAL DENSITY ENHANCEMENT AS A MEANS TO REDUCE ROUTING CONGESTION; U.S. Provisional Application Ser. No. 60/804,173 (Docket No. LS.2006.09), filed Jun. 8, 2006, first named inventor Geoffrey Mark Furnish, and entitled MORPHING FOR GLOBAL PLACEMENT USING INTEGER LINEAR PROGRAMMING; U.S. Provisional Application Ser. No. 60/803,032 (Docket No. LS.2006.06), filed May 24, 2006, first named inventor Subhasis Bose, and entitled TIMING DRIVEN FORCE DIRECTED PLACEMENT FLOW; U.S. Provisional Application Ser. No. 60/747,651 (Docket No. LS.2006.07), filed May 18, 2006, first named inventor Subhasis Bose, and entitled TIMING DRIVEN BUFFERING AND RESIZING FOR STRUCTURED ARRAY ARCHITECTURES; U.S. Provisional Application Ser. No. 60/697,902 (Docket No. LS.2005.01C), filed Jul. 9, 2005, first named inventor Geoffrey Furnish, and entitled METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING; U.S. Provisional Application Ser. No. 60/696,661 (Docket No. LS.2005.01B), filed Jul. 5, 2005, first named inventor Geoffrey Furnish, and entitled METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING; and U.S. Provisional Application Ser. No. 60/694,949 (Docket No. LS.2005.01), filed Jun. 29, 2005, first named inventor Geoffrey Furnish, and entitled METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING; and U.S. application Ser. No. 10/447,465 (Docket No. 6485.00002), filed May 28, 2003, first named inventor Eric Dellinger, and entitled MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC. BACKGROUND 1. Field Advancements in integrated circuit design, including placement and routing of elements in a Computer Aided Design (CAD) context, are needed to provide improvements in performance, efficiency, and utility of use. 2. Related Art Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes. Synopsis The invention may be implemented in numerous ways, including as a process, an article of manufacture, an apparatus, a system, a composition of matter, and a computer readable medium such as a computer readable storage medium or a computer network wherein program instructions are sent over optical or electronic communication links. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. The Detailed Description provides an exposition of one or more embodiments of the invention that enable improvements in performance, efficiency, and utility of use in the field identified above. The Detailed Description includes an Introduction to facilitate the more rapid understanding of the remainder of the Detailed Description. The Introduction includes Example Embodiments of one or more of systems, methods, articles of manufacture, and computer readable media in accordance with the concepts described herein. As is discussed in more detail in the Conclusions, the invention encompasses all possible modifications and variations within the scope of the issued claims. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a flow diagram illustrating selected details of an embodiment of placing, routing, analyzing, and generating fabrication data for any portion of an integrated circuit according to a Simultaneous Dynamical Integration (SDI)-based flow. FIG. 2 is a flow diagram illustrating selected details of an embodiment of placing and routing any portion of an integrated circuit according to an SDI-based flow. FIG. 3A is a flow diagram illustrating selected details of an embodiment of global placement according to SDI-based modeling and simulation. FIG. 3B is a flow diagram illustrating selected details of an embodiment of initial placement operations for global placement. FIG. 3C is a flow diagram illustrating selected details of an embodiment of density field based force component computation. FIG. 3D is a flow diagram illustrating selected details of an embodiment of gate density accumulation. FIG. 3E is a conceptual diagram illustrating an embodiment of two-point interpolation of node mass to grid points. FIG. 3F is a conceptual diagram illustrating an embodiment of three-point interpolation of node mass to grid points. FIG. 3G is a conceptual diagram illustrating an embodiment of applying boundary grid point masses to interior grid points. FIG. 3H is a flow diagram illustrating selected details of an embodiment of digital density filtering. FIG. 3I is a flow diagram illustrating selected details of an embodiment of interpolating gate fields to nodes. FIG. 4 is a flow diagram illustrating selected details of an embodiment of SDI-based modeling and simulation. FIG. 5A is a flow diagram illustrating selected details of a first embodiment of resource reconciliation, as a first example of legalization. FIG. 5B is a flow diagram illustrating selected details of a second embodiment of resource reconciliation, as a second example of legalization. FIG. 5C is a flow diagram illustrating selected details of an embodiment of partitioning. FIG. 6 is a flow diagram illustrating selected details of an embodiment of detailed placement (also referred to as detail placement elsewhere herein). FIG. 7A is a flow diagram illustrating selected aspects of an embodiment of delay path reduction and minimization, as an example of timing closure. FIG. 7B illustrates a conceptual view of selected elements of an embodiment of timing-driven forces. FIG. 7C illustrates a spatial organization of the driver and the coupled loads of FIG. 7B. FIG. 7D illustrates an embodiment of Net Boundary Box (NBB) estimation of routing to cover the driver and the loads of FIG. 7C. FIG. 7E illustrates an embodiment of a rectilinear Steiner Route Tree (SRT) estimation to cover the driver and loads of FIG. 7C. FIG. 7F illustrates an embodiment of estimated RC parasitics associated with the RST of FIG. 7E. FIGS. 8A and 8B collectively are a flow diagram illustrating selected details of an embodiment of an integrated circuit Electronic Design Automation (EDA) flow using one or more techniques including SDI-directed global placement, legalization, legalization-driven detailed placement, timing optimization, and routing. FIG. 9 illustrates selected details of an embodiment of manufacturing integrated circuits, the circuits being designed in part based on SDI-directed design techniques. FIG. 10 illustrates selected details of an embodiment of a computer system to execute EDA routines to perform SDI-directed place and route operations. FIG. 11 illustrates an embodiment of an SDI-based detailed placement flow. FIGS. 12A and 12B illustrate concepts relating to an embodiment of netlist elaboration. FIG. 13 illustrates an embodiment of detailed placement of a Q-block. FIG. 14 illustrates an embodiment of an additional pass of detailed placement of a Q-block. FIG. 15A illustrates a form of the form-level net of FIG. 12A. In this view the resource-level nodes are shown internal to the form. FIG. 15B illustrates another form that uses different resources to implement the same function as the form of FIG. 15A. In at least one embodiment, the form of FIG. 15B is substituted for the form of FIG. 15A through a morphing process. FIG. 16A illustrates the supply and demand for resources R1 through R6 corresponding to target functions of an integrated circuit design having a first selection of forms for the target functions. For at least some of the resources, the demand exceeds the available supply. FIG. 16B illustrates the supply and demand for resources R1 through R6 for the same target functions, but using a second selection of forms for the target functions obtained by morphing certain forms to use different resources. For each of the resources shown, the demand is less than or equal to the supply. FIG. 17A illustrates an example circuit with a plurality of critical paths. FIG. 17B illustrates example computations relating to an embodiment of CPF scoring. FIG. 18 illustrates an embodiment of a cascade of buffers of increasing drive strength. FIG. 19 illustrates example computations relating to an embodiment of SDF calculation. FIG. 20A illustrates an overall procedural control flow in an illustrative relative slack embodiment. FIG. 20B illustrates the adjustment of timing driven weight in the relative slack embodiment of FIG. 20A. FIG. 21A illustrates a driver in the interior of a net bounding box region. FIG. 21B illustrates a driver to one side of a net bounding box region. FIGS. 22A and 22B illustrate an example circuit excerpt before and after processing according to an embodiment of timing driven buffering and resizing for an array architecture. FIG. 23 illustrates a flow diagram of an integrated circuit design flow including an embodiment of processing in accordance with an embodiment of timing driven buffering and resizing for an array architecture. FIG. 24A illustrates a top-level view of an embodiment of timing driven buffering and resizing for an array architecture. FIG. 24B illustrates a detail view of selected details of an embodiment of timing driven resizing for an array architecture. FIGS. 25A and 25B illustrate an example route tree as processed by an embodiment of segmenting a portion of the route for timing driven buffering and resizing. FIG. 26 illustrates example results of an embodiment of logic replication and tunneling for an array architecture. FIG. 27 illustrates a control flow in an illustrative embodiment, as used for density modification. FIG. 28 illustrates a control flow of an illustrative embodiment, as used to determine the Steiner-cuts congestion term on the SDI grid. FIG. 29 illustrates procedures of an illustrative embodiment, showing creation of a congestion array. FIG. 30 illustrates procedures of an illustrative embodiment, showing calculation of a final congestion density enhancement array. FIG. 31 illustrates an embodiment of a processing flow for node tunneling out of exclusion zones in an SDI-based integrated circuit design flow. FIG. 32 illustrates an embodiment of SDI-related force calculations in a tunneling congestion relief context. FIG. 33 illustrates an embodiment of evaluation of tunneling transition criteria. FIG. 34A illustrates an example clock tree suitable for input to a Clock Tree Synthesis (CTS) tool for Structured Array Fabric (SAF)-based design flows. FIG. 34B illustrates an example clock tree output from the CTS tool operating on the input illustrated in FIG. 34A. FIG. 34C illustrates an example clock tree network. FIG. 35 illustrates an overview of an embodiment of a CTS flow. FIG. 36A illustrates an example die floorplan of a design having embedded Random Access Memory (RAM) or other Intellectual Property (IP) blocks. FIG. 36B illustrates a portion of a clock net in a context of a portion of FIG. 36A. FIG. 37A illustrates an example of timing driven pin swapping. FIG. 37B illustrates an example of effects of clock tree partitioning. FIG. 38 illustrates an analysis according to an embodiment of clock domain and sub-domain partitioning. DETAILED DESCRIPTION A detailed description of one or more embodiments of the invention is provided below along with accompanying figures illustrating selected details of the invention. The invention is described in connection with the embodiments. It is well established that it is neither necessary, practical, or possible to exhaustively describe every embodiment of the invention. Thus the embodiments herein are understood to be merely exemplary, the invention is expressly not limited to or by any or all of the embodiments herein, and the invention encompasses numerous alternatives, modifications and equivalents. To avoid monotony in the exposition, a variety of word labels (including but not limited to: first, last, certain, various, further, other, particular, select, some, and notable) may be applied to separate sets of embodiments; as used herein such labels are expressly not meant to convey quality, or any form of preference or prejudice, but merely to conveniently distinguish among the separate sets. The order of some operations of disclosed processes is alterable within the scope of the invention. Wherever multiple embodiments serve to describe variations in process, method, and/or program instruction features, other embodiments are contemplated that in accordance with a predetermined or a dynamically determined criterion perform static and/or dynamic selection of one of a plurality of modes of operation corresponding respectively to a plurality of the multiple embodiments. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured. Introduction This introduction is included only to facilitate the more rapid understanding of the Detailed Description; the invention is not limited to the concepts presented in the introduction (including explicit examples, if any), as the paragraphs of any introduction are necessarily an abridged view of the entire subject and are not meant to be an exhaustive or restrictive description. For example, the introduction that follows provides overview information limited by space and organization to only certain embodiments. There are many other embodiments, including those to which claims will ultimately be drawn, discussed throughout the balance of the specification. As described herein, “dynamic time-evolving SDI” refers to SDI techniques for the modeling and simulation of elements for integrated circuit placement and routing. Dynamic time-evolving SDI includes applying principles of Newtonian mechanics to an “analogy-system” based on a netlist that is a specification of the integrated circuit as part of an EDA flow (such as during physical design development of the integrated circuit). In some usage scenarios the analogy-system (often referred to simply as “system”) includes a single point particle corresponding to each device in the netlist. The system further includes a set of one or more forces acting on each of the particles, in certain embodiments computed as a weighted sum. Various numerical integration techniques are used to apply Newton's second law of motion to the system, forming a time-evolving representation of the system in state-space. In other words a simulation determines paths of the particles in a plane (or three dimensions). Then resultant locations of the point particles are mapped back into resultant placements of the corresponding devices, thus providing SDI-directed placements. Using dynamic time-evolving SDI, elements of the system are pushed simultaneously forward in time through a smooth integration in which the model for the system dynamics is an abstraction utilizing continuous variables and simultaneous exploration. Departures from idealizations of continuous variables and simultaneity are artifacts of techniques for solving the system of coupled simultaneous governing equations, such as that occur with numerical integration on a digital computer. In such digital computer implementations, the departures are limited to specifiable tolerances determined by the quality of result goals and economic considerations (such as available solution time, supply of computing power available, and other similar constraints). The system forces include attractive and spreading components, used to model effects of interconnect, resource usage (such as device area), and to drive various optimizations (such as timing closure). Some of the system forces are directly expressed as functions of the positions of other devices (such as attractive forces between connected devices), some of the forces are indirect functions of the positions of other devices and are computed by way of various fields (such as one or more density fields), and some of the forces that act on some of the devices are independent of the positions of the other devices in the system. Computing selected forces as fields in certain embodiments affords more computational efficiency. SDI-directed placement is useful in various integrated circuit design flows and related implementation architectures, including full custom, semi-custom, standard cell, structured array, and gate array design flows and related implementation architectures. Several variations in the context of structured array design flows enable efficient processing of numerous constraints imposed by the partially predetermined nature of the arrays. A library of composite cells or “morphable-devices” is provided to a synthesis tool (such as Synopsys Design Compiler or any other similar tool). The morphable-devices are used as target logic elements by the synthesis tool to process a netlist (either behavioral or gate-level) provided by a user. A synthesis result is provided as a gate-level netlist (such as a Verilog gate-level netlist) expressed as interconnections of morphable-devices. The synthesis tool assumes the morphable-devices represent the final implementation, subject to device sizing to resolve circuit timing issues. The morphable-devices are, however, subject to additional modifications in the structured array design flow context (see “Structured Arrays”, elsewhere herein), as each morphable-device may be implemented in a plurality of manners using varying resources of the structured array. During phases of resource reconciliation (where attempts are made to satisfy required resources with locally available resources), one or more of the morphable-devices may be transformed to a logically equivalent implementation. For example, an AND function may be implemented by an AND gate, by a NAND gate and an Inverter, or by any other equivalent formulation. Functionally equivalent alternatives are grouped according to implementation function, and individual realizations within a given function are referred to as “forms”. Thus any morphable-device may be implemented as any instance of any form having an equivalent function. Subsequent operations account for variation between logically equivalent forms (such as differences in area, timing behavior, routing resources used or provided, and any other characteristic distinguishing one form from another). Operations relating to interchanging implementations of morphable-devices to satisfy structured array resource limitations and underlying topology, as well as meeting spatial organization constraints, are termed “morphing”. The SDI-directed placement, in various contexts including structured array design flows, includes several phases: global placement, legalization, and detailed placement. Global placement in certain embodiments provides a first-cut location for each morphable-device in a netlist. The first-cut location is subject to additional refinement by subsequent processing (including legalization and detailed placement). Global placement is considered complete when a configuration is attained that is determined to be sufficiently close to legality to proceed to legalization, i.e. the configuration is likely to be reducible to a satisfactory implementation. Legalization starts with the global placement configuration and produces a final configuration in which demand for resources in every region is determined to be no greater than corresponding supply in each region. Detailed placement starts with the legalized placement configuration and assigns every element implementing a morphable-device to specific resources in an implementation (such as a set of specific resource-slots in a structured array architecture). Some simple functions may have degenerate forms requiring only a single resource instance, but more complex forms are composite, requiring more than one physical resource instance plus internal interconnect to correctly implement the function. Various morphing and similar transformation operations may be used in any combination of phases including global placement, legalization, and detailed placement, according to various embodiments. Morphing techniques used in one phase may be distinct or may be substantially similar to morphing techniques used in another phase, varying according to implementation. In some embodiments, different processing phases proceed with morphing operations operating according to respective morphing classes, i.e. a set of morphing classes for global placement, a set of morphing classes for legalization, and set of morphing classes for detailed placement. The morphing classes according to phases may be distinct or may be substantially similar to one another, according to embodiment. SDI-directed placement operations, when applied in a structured array design flow context, may include specialized forces relating to various “morphing classes” representing categories of structured array resources or related functionality. For example, resources for combinational circuitry may be grouped in a combinational morphing class, while resources for sequential circuitry may be grouped in a sequential morphing class. In some situations morphable-devices are restricted to implementation by resources belonging to a limited set of morphing-classes. Continuing with the example, combinational logic morphable-devices may be restricted to implementation by resources of the combinational morphing class, while sequential logic morphable-devices may be restricted to implementation by sequential morphing class elements. One or more specialized forces relating to each of the morphing classes may be used during global placement to effect spreading of morphable-devices according to corresponding morphing classes. Continuing with the example, a combinational spreading force may be selectively applied to combinational logic morphable-devices, while a sequential spreading force may be selectively applied to sequential logic morphable-devices. In certain embodiments, it is useful to subject all devices in the netlist (whether morphable or not) to a single spreading force that acts to drive the circuit toward a density that is sustainable on the implementation architecture, and augment the spreading force with the specialized resource-class-specific spreading forces to further tune the placement. Structured Arrays In some usage scenarios structured arrays are implementation vehicles for the manufacture of integrated circuits, as described elsewhere herein. Structured arrays in certain embodiments include fundamental building blocks (known as “tiles”) instantiated one or more times across an integrated circuit substrate to form a Structured Array Fabric (SAF). In some embodiments structured arrays are homogeneous (i.e. all of the tiles are identical), while in some embodiments the arrays are heterogeneous (i.e. some of the tiles are distinct with respect to each other). Heterogeneity may occur as a result of tile type, arrangement, or other differences. Irregardless of tile number and arrangement, however, the SAF tiles are fixed (i.e. prefabricated) and independent of any specific design implemented thereupon. SAF tiles, according to various embodiments, may include any combination of fully or partially formed active elements (such as transistors, logic gates, sequential elements, and so forth), as well as fully or partially formed passive elements (such as metallization serving as wires and vias providing interconnection between layers of metal). In some SAF embodiments “lower” layers of interconnect are included in SAF tiles (as the lower layers are formed relatively early in fabrication), while “upper” layers of interconnect are specific to a design (as the upper layers are formed relatively later in fabrication). Such SAF embodiments permit the lower prefabricated (and thus non-customizable) layers to be shared between different design implementations, while the higher/customizable layers provide for design-specific specialization or personalization. SAF structures may be used to construct an entire chip, or may constitute only a portion of the floorplan of an encompassing circuit, allowing for design variation. The size of the SAF tiles is generally irrelevant to design flows, and a tile may be as small and simple as a single inverter or as large and complex as a Randomly Accessible read-write Memory (RAM) block or other large-scale Intellectual Property (IP) element. EDA flows targeting designs based on structured array technology (such as the SDI-directed flow described elsewhere herein) account for the predetermined nature of the array, from gate-level netlist synthesis through subsequent implementation processing including layout of cells and interconnect. Such EDA flows enable realizing advantages of manufacture of integrated circuits including SAF tiles. The advantages include reduced manufacturing cost, as fewer mask layers (for example those corresponding to upper layers of interconnect) are customized for each design, as well as reduced characterization cost (for example by re-use of known structures such as the SAF tiles). High-Level Integrated Circuit Physical Design Flow FIG. 1 is a flow diagram illustrating selected details of an embodiment of placing, routing, analyzing, and generating fabrication data for any portion of an integrated circuit according to an SDI-based flow. A representation of all or any portion of the integrated circuit is provided (“Design Description” 120), in certain embodiments including a gate-level netlist, placement constraints, timing requirements, and other associated design specific data. The gate-level netlist may be provided in any proprietary or standard format, or a hardware description language (such as Verilog). A representation of fabrication flow is also provided (“Technology Description” 121), in certain embodiments including information relating to fabrication material starting state and manufacturing flow. The fabrication material information may include data describing wafers and any associated predetermined processing on the wafers (for example fabrication of lower layers of devices). The predetermined processing may be associated with transistors, combinatorial logic gates, sequential logic devices, storage arrays, regular structures, power distribution, clock distribution, routing elements, and other similar portions of active and passive circuitry. The manufacturing flow information may include information relating to physical and electrical design rules and parameters for extraction of parasitic information for analyzing results during physical design flow processing. Flow begins (“Start” 101) and continues (“Pre-Process” 102), where the design and technology descriptions are parsed and various design-specific data structures are created for subsequent use. The design description in certain embodiments includes a gate-level netlist describing interconnections of devices (morphable-devices, according to some embodiments), as well as constraints specific to implementation of the design (such as timing and placement requirements). The technology description includes information such as library definitions, fabrication technology attributes, and descriptions of manufacturing starting material (for example data describing SAF tile arrangement and composition of active and passive elements). Physical locations of some or all of the devices are then determined (“SDI Place & Route” 103), i.e. the design is placed, and wiring according to the netlist is determined (i.e. the design is routed). Place and route processing in certain embodiments includes multiple iterations of one or more internal processes (see “Place and Route Flow”, elsewhere herein). The placed and routed design is then analyzed (“Result Analysis” 104), in certain embodiments with one or more analysis tools performing various functions such as parasitic extraction, timing verification, physical and electrical rule checking, and Layout-Versus-Schematic (LVS) formal verification. Results of the analysis are examined by any combination of automatic (such as software) and manual (such as human inspection) techniques (“OK?” 105). If the results are acceptable, then flow continues (“Yes” 105Y) to produce information to manufacture the design according to the results (“Generate Fabrication Data” 106). The fabrication data varies by embodiment and design flow context, and may include any combination of mask describing data, FPGA switching-block programming data, and FPGA fuse/anti-fuse mapping and programming data. Processing is then complete (“End” 199). If the results are not acceptable, then flow loops back (“No” 105N) to repeat some portion of the place and route operations. In some usage scenarios (not illustrated) one or more modifications to any combination of the design and the technology may be made before repeating some of the place and route operations. For example, synthesis may be repeated (with any combination of changes to functionality as specified by behavioral or gate-level inputs and synthesis commands), a different technology may be chosen (such as a technology having more metal layers), or a different starting material may be selected (such as choosing a “larger” structured array having more SAF tiles). Processing functions (“Pre-Process” 102, “SDI Place & Route” 103, “Result Analysis” 104, “OK?” 105, and “Generate Fabrication Data” 106) are responsive to various instructions and input data (“Commands and Parameters” 130), according to various embodiments. The effects of the commands and parameters on the processing are represented conceptually in the figure (arrows 102C, 103C, 104C, 105C, and 106C, respectively). In various embodiments information is communicated between the processing functions (and other processing elements not illustrated) in various forms and representations, as shown conceptually (“Working Data” 131 and associated arrows 102D, 103D, 104D, and 106D, respectively). The working data may reside in any combination of processor cache, system memory, and non-volatile storage (such as disks), according to implementation and processing phase. The illustrated placement, route, and analysis processing is applied, in various embodiments, to integrated circuits implemented in various design flows or contexts, including application specific, structured array (homogenous and heterogeneous varieties), mask-definable gate array, mask-programmable gate array, Field-Programmable Gate Array (FPGA), and full custom. The processing may be applied to an entire integrated circuit, or one or more portions or sub-sections of an integrated circuit, according to various usage scenarios. For example, an otherwise full custom integrated circuit may include one or more regions of standard cells, and each of the standard cell regions may be processed according to all or portions of the illustration. For another example, an Application Specific Integrated Circuit (ASIC) may include some regions of standard cells and other regions of SAF tiles. Any combination of the standard cell and SAF tile regions may be processed according to all or portions of the illustrated flow. These and all similar variations are contemplated. Place and Route Flow FIG. 2 is a flow diagram illustrating selected details of an embodiment of placing and routing any portion of an integrated circuit, according to an SDI-based flow, such as operations referred to elsewhere herein (“SDI Place & Route” 103, of FIG. 1, for example). Overall the flow includes determining approximate (i.e. subject to subsequent refinement) locations for devices, reconciling resources, determining nearly final locations and implementations for the devices, minimizing critical delay paths, and wiring the devices according to a netlist. In certain embodiments each of the elements of the flow includes internal functions to determine acceptability of results, iterate as necessary to improve the results, and to direct feedback to earlier processing functions of the flow as needed. Processing begins (“Start” 201), in certain embodiments by receiving one or more data structures and files describing a netlist having devices and associated connectivity, along with manufacturing technology information. The structures and files may result from parsing design and technology information (“Pre-Process” 102, of FIG. 1, for example). Approximate locations for the devices of the netlist are then determined (“SDI Global Placement” 202) according to the netlist, the technology, and commands/parameters (such as those from “Commands and Parameters” 130, of FIG. 1). If global placement results are acceptable (i.e. suitable as a starting point for further processing), then flow proceeds (“OK” 202Y). If the global placement results are not acceptable, then flow loops back (“Not OK” 202N, “Repeat” 220, and “Revise” 202R) to repeat all or portions of the global placement. Revised global placement processing (via “Revise” 202R) in certain embodiments includes modifying any combination of the netlist, global placement commands and parameters, and manufacturing technology (such as specifying a larger die, or a denser device fabrication process) based in part upon previous processing. Subsequent to acceptable global placement, resources are reconciled according to the global placement and manufacturing information (“Legalization” 203), resulting in elimination of areas of oversubscribed resources. In certain embodiments modifications are made to the global placement results (effecting “movement” of placed elements) thus producing a legalized placement. If legalization results are acceptable, then flow proceeds (“OK” 203Y). If the legalized placement is not acceptable (or not computed), then flow loops back for additional processing (“Not OK” 203N). In certain embodiments the additional processing is based on previous processing, and may include repeating any portion of global placement (“Revise” 202R via “Repeat” 220) and continuing onward, or repeating any portion of legalization (“Revise” 203R via “Repeat” 220), according to various usage scenarios and embodiments. After acceptable legalization, then nearly final (or “exact”) locations and implementations for the devices are determined (“(SDI) Detailed Placement” 204). Relatively small-scale adjustments are made to legalization results, via any combination of placed element movement and placed element implementation, according to embodiment. In certain structured array embodiments, the placed element implementation includes morphing of selected devices to functionally equivalent alternatives. If detailed placement results are acceptable, then flow proceeds (“OK” 204Y). If the detailed placement is not acceptable (or not computed), then flow loops back for additional processing (“Not OK” 204N). In certain embodiments the additional processing is based in part upon previous processing, and may include repeating any portion of previous place and route functions and then continuing onward (such as via any of “Revise” 204R, “Revise” 203R, and “Revise” 202R by way of “Repeat” 220). Subsequent to detailed placement, delay paths are minimized (“Timing Closure” 205), in certain embodiments to meet user specified timing, in various ways according to embodiment and/or user option or configuration. In certain embodiments the detailed placement is analyzed and buffers (or buffer trees) are inserted in high fanout and timing-critical nets. In some embodiments drivers are resized and optimized to meet maximum capacitance and/or required time constraints with respect to timing critical receivers. In some embodiments clock networks are synthesized, while in other embodiments the clock networks are predefined. In either case the appropriate clock network elements are inserted into the netlist for clock distribution and to meet clock skew constraints. Further according to embodiment and/or user option or configuration, other timing closure driven optimizations are performed (see “Timing Closure”, elsewhere herein). If the timing closure results are acceptable, then flow proceeds (“OK” 205Y). If the timing closure is not acceptable, then flow loops back for additional processing (“Not OK” 205N). The additional processing may include repeating any portion of previous place and route functions, based in part upon previous processing and then continuing onward (such as via any of “Revise” 205R, “Revise” 204R, “Revise” 203R, and “Revise” 202R by way of “Repeat” 220). Note that in some embodiments flow loops back as a natural consequence of timing closure processing, rather than merely as a result of not-acceptable timing closure results. For example, certain timing closure techniques call for repetition of previous processing (such as one or more of “SDI Global Placement” 202, “Legalization” 203, and “(SDI) Detailed Placement” 204), using various combinations of modified behaviors and parameters, along with optional changes to the netlist and constraints, according to various embodiments. After timing closure is complete (or considered “close enough”), the resultant devices are wired together according to the resultant netlist (“Routing” 206), and corresponding interconnect is generated. If the routing results are acceptable, then flow proceeds (“OK” 206Y). Place and route processing is then complete (“End” 299), and results are available for further use, such as any combination of analysis and mask generation (“Generate Fabrication Data” 106 of FIG. 1, for example). If the routing results are not acceptable, then flow loops back for additional processing (“Not OK” 206N). In certain embodiments the additional processing is based in part upon previous processing, and may include repeating any portion of previous place and route functions and then continuing onward (such as via any of “Revise” 206R, “Revise” 205R, “Revise” 204R, “Revise” 203R, and “Revise” 202R by way of “Repeat” 220). Various combinations of place and route processing functions (such as “SDI Global Placement” 202, “Legalization” 203, “(SDI) Detailed Placement” 204, “Timing Closure” 205, and “Routing” 206) may include reading and writing shared information (such as references to “Working Data” 131, of FIG. 1). Examples of working data include netlists, constraints, progress indicators, and other similar shared processing items. Various combinations of the aforementioned place and route processing functions also may include receiving one or more inputs specifying requested behaviors or processing (such as information from “Commands and Parameters” 130, of FIG. 1). Examples of commands and parameters include scripts specifying iteration closure conditions, control parameters, goal descriptions, and other similar information to guide processing. The commands and parameters may be provided via any combination of scripts, command line inputs, and graphical user interfaces, according to various embodiments. In some embodiments processing of one or more elements of FIG. 2 is optional, or performed only for selected iterations though the illustrated flow. For example, timing closure operations may be operative in a first processing mode where legalization and detailed placement are skipped, and processing relating to timing closure is partially performed as part of global placement. Alternatively the first processing mode may be viewed as global placement operations being performed to a limited extent, then analyzed and further directed by timing closure operations (without legalization or direct placement), and then additional global placement operations being performed. Eventually a second mode of processing may be entered where legalization and detailed placement are performed, optionally followed by additional timing closure operating as in the first mode or operating in a manner specifically tailored to the second mode (see “Timing Closure”, elsewhere herein). Simultaneous Dynamical Integration (SDI) Directed Global Placement Conceptually SDI may be understood as modeling each individual device of the netlist as a node, or point particle, having an associated mass, position (or location), and velocity. The nodes representing the devices of the netlist are coupled by and interact with each other via attractive and spreading forces. The forces may include attractive forces representing electrical connections between the devices (as specified by the netlist), and spreading forces modeling resource requirements versus availability (such as a density of logic gates needed versus a density of logic gates on hand). The nodes and effects of the coupling forces are simulated as evolving over time as governed by a system of coupled ordinary differential equations using continuous variables, according to classical Newtonian mechanics (i.e. force equals mass multiplied by acceleration, or F=ma). Thus locations of nodes (corresponding to device placements) evolve over time from initial positions to subsequent positions (corresponding eventually to the global placement result for the devices). More specifically, the independent variables in the dynamical system simulation include configuration-space variables (position and velocity) of the nodes. In certain embodiments the position and velocity representations are multi-dimensional quantities (two or three dimensions, for example), according to usage scenario and embodiment. Force terms in the coupled equations of motion are related to any combination of the topology of the connections of the devices, timing analysis of evolving device locations (placement), obstructions, and region constraints (fixed and floating), according to embodiment. Force terms may also be related to any combination of partial node density, partial resource usage density, viscous damping, energetic pumping, interconnect congestion effect modeling, power or clock distribution, and signal integrity representation, according to embodiment. Force terms may include any function of the independent variables, provided commands and parameters, and other similar mathematical devices useful in managing numerical behavior of continuous time integration of the system of nodes and forces. In certain embodiments the obstructions are represented as exclusion zones, and arise as a result of architectural considerations, location-fixed (or predetermined) blocks (such as large RAM arrays or IP elements), and other similar placement limiting conditions. In certain embodiments the region constraints are represented as fixed, relative, or floating location requirements on selected devices of the netlist. Corresponding position requirements (such as an initial position with no subsequent change during system simulation time) are imposed for the corresponding nodes in the dynamical simulation. Various combinations of region constraints (relating to integrated circuit floorplan specifications, for example) may be developed by any combination of automatic techniques (by software, for example) and manual techniques (by users), according to usage scenarios and embodiments. Conceptually the system of coupled simultaneous differential equations is operational in continuous variables. While it is envisioned that certain embodiments will perform at least some of the integration according to true analog integration techniques, in which the state variables are actually continuous, in digital computer embodiments, the integration is performed using digital integration techniques. Digital computers are limited to representing all quanta with finite-precision variables and that continuous time integration may be implemented on digital computers using “pseudo-continuous” numerical approximation techniques, a.k.a. “numerical methods.” Even when implemented using finite-precision approximations, the “continuous variables” abstraction is a useful way to conceive and describe some of the techniques described herein and to distinguish compared to other approaches using conceptually discrete variables. Thus the term continuous as used throughout this disclosure should be interpreted in accordance with the foregoing. In digital computer embodiments, continuous state variables (including those variables representing simulation time, mass, location, and velocity) are approximated as any combination of single, double, or extended floating-point numbers. The continuous time integration of the simultaneous coupled dynamical governing equations may be performed in digital computer embodiments by any suitable digital integration technique, such as Runge-Kutta, predictor-corrector, leap-frog, and any similar technique adaptable to continuous multi-variable state space integration. In some embodiments the integration technique is chosen for suitability based at least in part on adaptability to parallel processing (see “Computer System Executing SDI-Directed EDA Routines”, elsewhere herein). The forces acting in the system provide coupling between the nodes and act to accelerate the nodes over time, resulting in movement of the nodes throughout the state-space over time. A set of attractive forces (known as “net attractive forces”) is modeled to represent connectivity between the devices of the netlist, or more specifically between pins (i.e. terminals of circuit elements) of devices. In some embodiments the net attractive forces are modeled as individual springs between a pin of one device and a pin of another device, with every interconnection between any two pins being modeled as a corresponding spring. Force associated with each spring is computed according to Hooke's law (force is proportional to distance between the pins). The net attractive force acting on each device is a vector sum of all net attractive forces acting on all of the pins of the respective device. In some embodiments the constant of proportionality used to calculate spring force is identical for all springs. In some embodiments the constant of proportionality is dependent on the fanout of a net (i.e. the number of pins connected together). In some embodiments relatively high fanout nets are considered to be one or more drivers providing a signal to one or more loads. Springs between the loads of the relatively high fanout nets are eliminated (while springs from drivers to loads are retained). In some embodiments springs between drivers and loads have a different constant of proportionality than other springs. Modeling of net attractive forces is not restricted to ideal springs, and may instead be based on a general linear or non-linear force model, according to various embodiments. A set of spreading forces (known as “spatial spreading forces”) is modeled based on one or more macroscopic density fields. In certain embodiments the density fields are computed based on analysis of metrics associated with respective devices corresponding to the nodes (and their locations) in the dynamical system. The metrics may include any combination of standard cell area (in, for example, standard cell flow processing), fabric resource consumption (in, for example, SAF flow processing), equivalent gate count, and other similar functions of node properties. In some embodiments the spatial spreading forces (see “Field-Based Force Components”, elsewhere herein) are with respect to a density field based on resource utilization of corresponding nodes in a local region. In some embodiments resource utilization may be evaluated using an area averaging or summation of nearby devices or an equivalent-gate count rating (cost function) of spatially close devices. In some embodiments a plurality of density fields are computed with respect to a plurality of metrics. In some embodiments any combination of first, second, and third density fields are computed with respect to first, second, and third categories of logic devices (such as combinational logic devices, sequential logic devices, and total logic devices). In some embodiments each of a plurality of partial density fields is computed according to a set of respective non-interchangeable morphing classes (such as combinational and sequential morphing classes) associated with an underlying SAF. In some embodiments (such as selected standard cell based design flows) the density fields are computed based wholly or partially on device area. In some embodiments (such as selected structured array based design flows) the density fields are computed based wholly or partially on resource utilization as measured by counts of the number of each type of resource needed to implement the function associated with each device in the netlist. Other attractive and spreading forces may also be included, according to usage scenario and embodiment. Floorplan constraints, or various region constraints, may be expressed as attractive or spreading forces, or as potential wells (with a tendency to retain nodes in a region) or potential barriers (with a tendency to disperse nodes from a region), according to usage scenario and embodiment. For example, boundaries of a die, or locations of input/output (IO) rings may be expressed as fixed constraints that are mapped to attractive forces acting on nodes having interconnect to the IO ring. For another example, a selected region of the die may be excluded from use (such as for yield improvement or noise reduction) by fixed or relative (i.e. floating) constraints that are mapped to spreading forces acting on nearby or all nodes (see “Exclusion Zones”, elsewhere herein). In other embodiments or modes of operation, such floorplan constraints may be implemented through coordinate clipping inside the integrator, thereby preventing the motion of devices into disallowed regions. User specified circuit timing constraints may warrant that certain pins in the netlist be moved closer together to improve the performance of the design. A corresponding set of attractive forces between drivers and select loads is fed into the system as attractive forces with configurable binding strength. Viscous Damping Forces other than attractive and spreading forces between nodes or other elements may also be accounted for. As an example, a viscous damping force may be included as a way to (a) compensate for the effect of numerical errors (potentially incurred by the time integration and spatial differencing techniques used) contributing toward numerical heating, and (b) change the ratio between kinetic and potential energy of the node distribution. The damping serves to decelerate the ballistic motion of a node. One embodiment of such a force on a given node is a term proportional to the negative of the node velocity, with the proportionality constant being equal to μ, the global coefficient of viscosity. The value of μ may be supplied by direct manual input (by a user) or via automatic control, (under software control) according to embodiment, to provide partial control of the node distribution as a whole. While μ is a global constant, it may have a local effect, and thus in some embodiments other parameters are selected for manipulation to provide control of the node distribution as a whole. For example, in some implementations a ratio of KE/TE, where KE is the kinetic energy of the node distribution and TE is the total energy of the system, is a convenient control parameter. In some embodiments, the global viscosity coefficient is split into two terms, a gradually drifting term and a dynamically calculated term. The gradually drifting term enables the system to gradually adapt to time varying forces or parameter changes, while the dynamical term prevents runaway acceleration on a per-timestep basis. Each timestep the total effective μ is adjusted in response to normalized kinetic energy (KE/TE) changes from a selected target value. In certain embodiments the adjustment to R is given by: If KE/TE>target then: dm=cdm1((KE/TE/target)−1)+cdm2((KE/TE/target)−10)ˆ2 μ—eff=μ(1+dm) μ=(1+<small adjustment>) If KE/TE<target then: dm=cdm1((target/KE/TE)−1)+cdm2((target/KE/TE)−10)ˆ2 μ—eff=μ/(1+dm) μ/=(1+<small adjustment>) where: double mu_max=1.e+8; double cdm1=1.; double cdm2=0.01; and Note that “double” refers to double-precision variables used in some embodiments. The <small adjustment> may vary with the relative difference between the target and actual values of KE/TE, and tends to be small compared to 1. The term “mu_max” limits μ to prevent numerical problems with a timestepper used for numerical integration. The quadratic term contributes little until KE/TE differs from the target by a factor of 10, and quenches runaway conditions. By splitting the calculation of μ into a purely dynamical term and a slowly varying term, the system remains generally stable while retaining an ability to react quickly to energy spikes. Further, by using a constant μ during the course of the time integration, performance may be enhanced, as operation counts are substantially reduced and adaptive integrator timesteps (if relevant) may be allowed to increase. In some embodiments a viscous damping proportionality constant is identical for all nodes in the system, while in other embodiments one or more distinct proportionality constants may be employed. For example, in certain embodiments the viscous damping proportionality constant is modeled as a scalar field of position and the value of the constant at the position of each circuit device is computed. Moreover, in certain embodiments the scalar field is analytically specified, and selectively includes a dependence upon the independent time variable. In other embodiments the scalar field is a derived quantity computed from other numerical characteristics that may be evaluated for the time-evolving simulation. Additionally, the viscous force is not limited to being proportional to the velocity of a node. In certain embodiments the viscous force instead follows a functional form based on other selected state of the system. The aforementioned forces are merely representative examples. Forcing terms may be associated with interactions between one or more nodes, and between one or more fixed (or immovable) elements. Forcing terms may also be associated with fields that may be dependent in some way upon one or more nodes, or with fields that are independent of nodes. These and all similar types of forcing terms are contemplated in various embodiments. Thus forces on the nodes of the system include direct interactions with topological neighbors (according to the netlist), collective interactions involving numerical constructs associated with temporal bulk properties of the node distribution, and with architectural features of the implementation. The result of the combination forces impinging on the system nodes is a complex dynamical interaction where individual nodes meander through the placement domain under the influence of the forces and wherein the forces vary continuously with the motion of all nodes in the netlist. The motion exhibits both chaotic and coherent behaviors. The motion of a given node may appear chaotic in the sense that the node trajectory may meander back and forth as a result of connections to other nodes. Yet the system may also exhibit coherent (or collective) motion in the sense that tightly connected nodes will tend to move in bulk and remain in proximity to topological neighbors even as the tightly connected nodes collectively move far from respective starting points. The integration of the governing equations of motion proceeds using standard techniques of numerical integration. (See for example, a reference describing numerical integration.) As an example, the next several paragraphs assume the use of a Runge-Kutta integrator. The computation of the forcing terms is referred to as “computing the derivatives”. Differentiation is denoted with respect to time by ′ (prime), so that dx/dt=x′, d2x/dt2=x″, and so forth. The following variables are introduced to set up the governing equations for solution by numerical integration: vx,i=(xi)′ vy,i=(yi)′ The subset of the system of equations relating to the ith node (for a two-dimensional layout application) is: (xi)′=vx,i (yi)′=vy,i (vx,i)′=Fx,i (vy,i)′=Fy,i Thus the system of simultaneous second order differential equations is transformed to a (larger) system of simultaneous first order differential equations, where the right hand side of each equation is the derivative of the respective left hand side. Conceptually computation of a derivative per se is not required (unless some element of the forcing terms is itself expressed as a derivative of something else), but rather the right hand sides of the equations are the derivatives. There is time-varying complexity in the behavior (character of motion) of the moveable nodes in the netlist when the forcing terms are time varying. In some embodiments a time varying timestep is used to preserve numerical accuracy and to continue processing until convergence criteria (error limits) are met during each timestep in the integration. The integrator accepts as input a specification of a desired timestep, and then processes the timestep in two ways: once directly, and once as two half-steps. If the results are not close enough as determined by a specifiable error-norm, then the target timestep is reduced until it is possible to perform the one-step plus the two-half-steps approaches with results within an error norm. Besides new coordinate values for the independent variables, the integrator also returns the length of the timestep just taken and the advised length for the next timestep. Thus during periods of laminar motion when numerical convergence is readily achieved, the timestep trends longer on successive calls to the integrator. But in periods of turbulent or chaotic motion, where convergence requires more effort, the timesteps become as small as needed to ensure the accuracy of the integration. FIG. 3A is a flow diagram illustrating selected details of an embodiment of global placement according to SDI modeling and simulation, such as operations referred to elsewhere herein (“SDI Global Placement” 202, of FIG. 2, for example). Overall the flow includes various functions to enable and perform a series of dynamical simulations based on Newtonian mechanics on a system representing the netlist and associated design constraints and targets. The simulations use SDI techniques to orchestrate the interactions between particles (representing netlist devices). The SDI techniques make use of fields that are calculated as functions of the particle positions. The functions include determining a set of nodes corresponding to the devices in the netlist, initialization of state variables (including mass, location, and velocity associated with each node), adjusting forces, and evolving the resultant system of simultaneous dynamical governing equations forward in time via integration. The flow is repeated beginning at the adjustment processing until a suitable result is available, or it is determined that a suitable result will not become available without further processing outside of the illustrated flow. Processing begins (“Start” 301) with receipt of pre-processed information, in certain embodiments as data structures representing the netlist and the associated devices and connectivity (“Pre-Process” 102, of FIG. 1, for example). Further data structures for representing a system of nodes and forces are created and initialized (“Determine Nodes and Forces” 302), with each node in the system corresponding one-to-one with each device of the netlist, and with each node having a corresponding set of forces acting on it. State variables for the dynamical simulation are initialized (“Initialize State Variables” 303), including determining starting values for mass, location, and velocity state variables for each node. The initial node locations correspond to initial placements of the corresponding netlist devices (see “Initial Placement”, elsewhere herein). Initial force values are also determined. Large-scale goal-driven modifications to the forces in the system are then made (“Macro Adjust Forces” 304). In some embodiments one or more attractive forces are over- or under-weighted for periods of time, and one or more spreading forces may also be reduced or increased in relative proportion to the attractive forces. For example, a “condensing” phase may inflate attractive forces and deflate spreading forces, and an “extending” phase may deflate attractive forces and inflate spreading forces. Operations associated with the macroscopic force adjustment track simulation time and change the forces according to condensing and extending phases. During the phases of system evolution, the coordinates of individual nodes continue to evolve separately based on the governing equations for each individual node. Consequently, the behavior of any individual node may vary from the bulk behavior of the collective system. Other large-scale force adjustments may also be made, according to embodiment, including entirely removing one or more forces for a period of simulation time, and introducing a new force. The removal (or introduction) of a force may be at a predetermined point in simulation time, at a point in simulation time determined by computation of a test condition, any similar mechanism, and/or at the discretion of a human operator of the system, according to various embodiments. In certain embodiments the removal (or introduction) of a force is gradual, and the rate of change of the removal (or introduction) may vary over simulation time or be constant, according to implementation. In some embodiments the macroscopic force adjustments are in response to various force-control instructions and input data (such as represented conceptually by “Commands and Parameters” 130, of FIG. 1). Large-scale goal-driven modifications to the effects of masses in the system are then made (“Macro Adjust Masses” 305). In certain embodiments the effects of masses are modified during phases where node densities are being adjusted to more evenly distribute resource consumption, or to more evenly match resources needed with resources available. For example, in usage scenarios including global placement of devices according to SAF tiles, macroscopic mass adjustments may be made to “encourage” cells in over-subscribed regions to “move” to less subscribed regions (see “Depletion Weighting”, located elsewhere herein). As in the case of macroscopic force adjustments, macroscopic mass adjustments may be varied according to simulation time phase, and may be gradually introduced (or removed) over the course of system evolution throughout simulation time. In some embodiments the macroscopic mass effect adjustments are in response to various mass-control instructions and input data (such as represented conceptually by “Commands and Parameters” 130, of FIG. 1). Note that adjusting the effects of mass, in certain embodiments, is with respect to densities and forces brought about by the masses, while the momentum of each of the nodes having adjusted mass effects remains unchanged. A dynamical simulation of the nodes (as point particles) according to the mass, location, velocity, force, and other state variables is performed (“SDI Simulation” 306) for some amount of system simulation time. The time may be a predetermined interval, dependent on specific completion criteria (as provided to the SDI simulation), and any similar interval specification scheme, according to various embodiments. At the end of the simulation time the system arrives at a new state. In certain embodiments the new state includes new locations for one or more of the nodes, and the new locations of the nodes are interpreted as corresponding to new locations for the devices being placed. According to various embodiments, any combination of the system variables (including simulation time and node mass, location, and velocity) and corresponding interpretations of the system variables in the context of the netlist (including device location and density) are examined to determine if portions of the flow should be repeated (“Repeat?” 307) or if flow is complete (“OK Result?” 308). If repeating the flow would likely improve results, and no other end condition has been met, then flow loops back (“Yes” 307Y) to macro adjustment of selected forces and masses. In some embodiments configurable settings are adjusted prior to or in conjunction with force and mass macro adjustments (such as settings associated with “Commands and Parameters” 130, of FIG. 1). If the global placement is close enough (“No” 307N), then flow is complete (“OK” 202Y) and processing continues to legalization (see FIG. 2). If there would likely be no benefit in iterating the global placement (“No” 307N), and the results are not acceptable, then flow is also complete (“Not OK” 202N), but subsequent processing then includes one or more revisions (see FIG. 2). Tests to determine if the flow is to be repeated may be made for a predetermined end condition, a predetermined rate of change, other similar criteria, and any combination thereof according to assorted implementations. In some embodiments the flow is not repeated even if improvement is likely possible (for example if an interval of simulation time has expired). Determinations (“Repeat?” 307 and “OK Result?” 308) are according to any combination of automatic (software program) and manual (human user) techniques, according to various embodiments. For example, an automatic technique may include software determining if the most recent iteration is a significant improvement over a previous iteration. If so, then repeating the flow is beneficial. As another example, a manual technique may include a user observing the time-evolving locations of devices and noticing that further improvements are possible and that repeating the flow would be beneficial. Another manual technique may include a user determining that the placement as changing over time is “stuck”, perhaps due to some incorrectly specified constraints, and that additional iterations of the global placement flow are not likely to be beneficial unless modifications are made to the constraints. Any portion (or all) of global placement may be performed according to various techniques, in addition to the aforementioned SDI directed technique. The additional techniques include simulated annealing, objective minimization techniques such as conjugate-gradient, chaotic processing, and other similar mechanisms to provide approximate or “close enough” device coordinates, according to various embodiments. Initial Placement FIG. 3B is a flow diagram illustrating selected details of an embodiment of initial placement operations for global placement, such as selected operations performed while initializing state variables (as in “Initialize State Variables” 303 of FIG. 3A). Processing begins (“Start” 310) and then one of a plurality of starting location definition techniques is chosen (“Select Technique” 310A), based, in some embodiments, on instructions provided by a user (such as information from “Commands and Parameters” 130, of FIG. 1). A first technique determines an initial placement based on a placement performed in the past (“Prior Solution” 311). A second technique formulates an initial placement based on randomization (“Random” 312). A third technique develops an initial placement according to any of a number of other mechanisms (“Selected Algorithm” 313), chosen by any combination of software and user input. The chosen technique is then performed and processing is complete (“End” 314). Mass Determination In some embodiments, determination of mass (as in “Determine Nodes and Forces” 302, for example) is dependent on the design flow or implementation context (such as application specific, structured array, mask-definable gate array, mask-programmable gate array, FPGA, and full custom). For example, in a standard cell context, the mass of a node may be computed as a function (such as a linear function) of area occupied by the corresponding device in the netlist. For another example, in a structured array context, the mass of a node may be computed with respect to consumption of resources provided by the structured array, or with respect to local availability or scarcity of the resources, according to the corresponding device as implemented by the resources. For another example, in an FPGA context, the mass of a node may be computed according to consumption of Look Up Table (LUT) resources, or similar switching and/or routing resources. In some embodiments the spatial spreading forces (see “Field-Based Force Components”, located elsewhere herein) are with respect to a density field based on resource utilization (such as an area averaging or summation of nearby devices or an equivalent-gate count cost function of spatially close devices) of corresponding nodes in a local region. In some embodiments first and second density fields are computed with respect to first and second categories of logic devices (such as combinational logic devices and sequential logic devices). Field-Based Force Components In some embodiments various elements of the spatial spreading forces are with respect to one or more resource usage based density fields, or other types of density fields. The density fields are managed independently, and may include any combination of all nodes, combinational nodes, and sequential nodes. Computation of density fields and resultant spreading forces conceptually includes calculating local densities according to a discrete grid, computing density fields, allocating field strengths according to the discrete grid to system nodes, and calculating resultant spatial spreading forces acting on the system nodes. In some embodiments the discrete grid is a uniform (or non-variable) grid, and in some embodiments the grid is a non-uniform (or variable) grid, the grid being implemented according to architectural considerations. Local density calculation includes summing resource usage computed in continuous spatial variables (i.e. node location and mass) according to the discrete grid and digitally filtering the resultant gridded scalar field. The local density calculation includes special accounting for edges of the grid. The digital filter result is suitable for processing by a field solver. Density field computation performed by the field solver includes determining density fields (given density values on the grid) and digitally filtering the result. Allocating field strengths includes interpolating field strengths to nodes (in continuous location space) while accounting for edges of the grid. Repulsive (or spreading) forces are then computed according to the allocated field strengths. In some embodiments the grid is a unit grid, and the region enclosed by adjacent grid lines is termed a “cell”. The grid may be two-dimensional (i.e. x and y) or the grid may be three-dimensional (i.e. x, y, and z), according to implementation technology and other design-flow related parameters. In some embodiments resource usage density is proportional to the respective mass of each node, and the mass is in turn directly proportional to a “gate rating” that is a measure of relative cost of implementing a logic function corresponding to the node. In some embodiments the gate rating of the node is measured in “gate-equivalents” commonly associated with design-flow device selection criteria. FIG. 3C is a flow diagram illustrating selected details of an embodiment of density field based force component computation, in a specific context of resource usage densities expressed in certain embodiments as mass that is proportional to gate rating. The operations of the flow are performed for each of a possible plurality of density fields, each field having separate accounting. Flow begins (“Start” 330), and proceeds to determine local resource usage density by accumulating system node masses with respect to a scalar field organized as a regular grid (in the illustrated embodiment) according to the SDI simulation spatial field (“Accumulate Gate Densities” 331). The grid is finite in size, completely covering space in the system simulation corresponding to the area available for the devices of the netlist (either an entire die or a portion thereof). The grid is extended, via one or more guard grid locations (or grid cells) one or more units around each border of the area (the boundaries of the area) to more accurately and efficiently model edge effects. The guard grid elements are then included in the gate density calculation (“Fold Guard Cell Contributions” 332). The single-unit guard-cell buffer is used in some embodiments employing two and three-point allocation/interpolation schemes, and a multi-unit guard-cell buffer is used in some embodiments having higher order allocation schemes. The resultant density values are then further optionally processed (“Digitally Filter Density” 333), according to embodiment, to smooth variations caused by grid element representation inaccuracies. Density values for guard grid elements are then determined (“Calculate Density Guard Cell Values” 334) to enable straightforward and efficient field solver implementations. Density field computations (“Solve Gate Fields” 335) are then performed by the field solver, determining the field value at each point as equal to minus the gradient at the point (i.e. field=−Grad(n)). Any field solution technique applicable to calculating a derivative with respect to a discrete grid may be used, such as a second order finite difference formula, or any other suitable technique, according to embodiment. In some embodiments the second order finite difference formula is given as the derivative at grid point “i”, and is equal to one-half the quantity equal to the difference of the values at adjacent grid points along one of the orthogonal dimensions (i.e. field(i)=(density(i+1)−density(i−1))/2). Derivatives are calculated for each orthogonal dimension of the system node space (two or three dimensions, according to embodiment). The result is a gridded vector field for each gridded density (such as all, combinational, and sequential). In some embodiments vector field values are stored in a data structure as a tuple. Each member of the tuple corresponds to a value associated with an orthogonal dimension of the vector field, and there is a tuple associated with each grid point. In some embodiments vector field values are stored separately as scalar fields, according to each vector field orthogonal component. Each respective scalar field represents all grid points. In some embodiments vector field values are stored according to other arrangements that are mathematically equivalent to tuples or scalar fields. In addition, vector fields may be stored in various combinations of tuple, scalar field, and other forms, according to embodiment. The representation employed for the vector fields may also change during processing to enable more efficient computations. Further, during processing, any portion of vector field representations may be stored in any combination of processor cache memory (or memories), processor main memory (or memories), and disk (or other similar non-volatile long-term) storage, according to usage scenario and implementation. The gridded vector fields are then processed according to a digital filter (“Digitally Filter Fields” 336). In some embodiments the filtering of the gridded vector fields is according to operations identical, except for edge processing, to the smoothing performed on density values (as in “Digitally Filter Density” 333). The difference between the filter operations is that for density filtering even parity is used when processing the boundaries, while for field filtering even parity is used for field components parallel to the boundary and odd parity is used for field components perpendicular to the boundary. The difference in parity accounts for the differentiation operation performed between density and field domains, such that parity is reversed from even (for density) to odd (for field) when differentiation is directed into a boundary. For a (scalar) density, even parity means values associated with guard grid points are added to interior grid points. For a (vector) field, even parity means the guard grid points are equal to respective closest inner grid points for, and odd parity means that the guard grid points are equal to the negative of respective closest inner grid points (“Calculate Field Guard Cell Values” 337). Thus the average field directed into (or out of) a boundary vanishes at the boundary. Assigning guard point field values enables subsequent efficient computation of field values in the continuous location representation of nodes from the discrete field values (“Interpolate Gate Fields to Nodes” 338). Corresponding forces may then be calculated according to node field values and node masses. Processing is then complete (“End” 339). FIG. 3D is a flow diagram illustrating selected details of an embodiment of gate density accumulation, such as operations referred to elsewhere herein (“Accumulate Gate Densities” 331, of FIG. 3C, for example). Conceptually mass associated with each node (represented in continuous location space) is allocated to a local neighborhood portion of the discrete grid points. Guard grid points are added around the boundary of the grid to efficiently process edge conditions. In some embodiments a two-point linear spline, also known as a Cloud-In-Cell (CIC) or area weighting technique, is used to allocate the mass of each node to four neighboring grid points. In some embodiments a three-point spline technique is used to allocate node mass to nine neighboring grid points. More specifically, flow begins (“Start” 340) by initializing accumulation variables (such as to zero), and then a check is made to determine if processing is complete for all nodes in the simulated system (“Iterated Over All Nodes?” 341). If so, (“Yes” 341Y), then gate field interpolation processing is complete (“End” 345). If not, then a first (and subsequently a next) node is selected for processing, and flow continues (“No” 341N). Spline coefficients are then determined for the node (“Determine Spline Weights” 342), based on distances from the respective node to each field grid point (see the discussion of FIG. 3E, elsewhere herein). After all of the spline weights for all of the grid points have been calculated, a check is made to determine if all fields the respective node contributes to have been processed (“Iterated Over all Fields” 343). If so (“Yes” 343Y), then processing loops back to check if all nodes have been processed. If not, then a first (and subsequently a next) field is selected for processing, and flow continues (“No” 343N). The effect of the node is then accumulated to the respective field array at each of the grid points currently subject to interpolation (“Apply Node Weight to Field Array” 344). Processing then loops back to determine if all fields have been processed. FIG. 3E is a conceptual diagram illustrating an embodiment of two-point interpolation of node mass to grid points, as performed during mass accumulation (such as “Determine Spline Weights” 342, of FIG. 3D). Boundary 394 is shown to represent edges of the system simulation space (and corresponding edges of an integrated circuit region or die). Several points of the discrete grid are illustrated: interior point I1 381, boundary points B1 371, B2 372, and B3 373, and guard points G1 386, G2 388, and G3 389. Mass from node N1 375 is shown accumulating to four grid points (G1, G2, G3, and B2), according to distance along orthogonal dimensions of the system simulation location space (δx1 390 and δy1 392). Conceptually grid points B2 and G1 together receive (1−δx1) of the mass of N1, while grid points G2 and G3 together receive δx1 of the mass of N1. More specifically each dimension is processed in a geometric fashion, so the total mass contribution from N1 to B2, for example, is (1−δx1)(1−δy1), and so forth. As illustrated in the figure, δx1 is the projected distance along the x-axis from B2 to N1, and similarly for δy1 with respect to the y-axis, B2, and N1. The figure also illustrates mass allocation of node N2 376 to four neighboring grid points (B1, B2, B3, and I1), none of which are guard points. The mass contribution from N2 to point B2 is additive with the mass contribution from N1 to B2. Also, there may be any number of other nodes (not illustrated) within the same grid cell as either of nodes N2 and N1, and masses from the respective nodes are accumulated in the same manner as illustrated for N2 and N1. FIG. 3F is a conceptual diagram illustrating an embodiment of three-point interpolation of node mass to grid points, as performed during mass accumulation (such as “Determine Spline Weights” 342, of FIG. 3D). The figure is representative of operations similar to FIG. 3E, except the node being processed according to mass accumulation affects masses accumulating for nine nearest-neighbor grid points (B0 370, B1 371, B2 372, B3 373, B4 374, I4 384, I3 383, I2 382, and I1 381). The formula representing accumulation to a point (such as I1) is implementation dependent. FIG. 3G is a conceptual diagram illustrating an embodiment of applying guard grid point masses to interior grid points, such as operations referred to elsewhere herein (“Fold Guard Cell Contributions” 332 of FIG. 3C, for example). The elements and representations are similar to FIG. 3E. In a first stage of processing, contributions of “right-hand column” guard elements (G2 388, G3 389, and G4 390) are summed, or “folded” into corresponding guard and interior elements of the adjacent column (G1 386, B2 372, and B3 373, respectively), as suggested conceptually by curved arrows 396. In a second stage of processing, contributions of “top row” guard elements (G1 386 and G0 385) are summed to (or folded into) corresponding interior elements of the adjacent row (B1 371 and B2 372, respectively), as suggested conceptually by curved arrows 395. The summation processing corresponds to even parity. Similar processing is performed for the other two edges of the region. FIG. 3H is a flow diagram illustrating selected details of an embodiment of digital density filtering, such as operations referred to elsewhere herein (“Digitally Filter Density” 333, of FIG. 3C, for example). Conceptually each density grid is filtered, alone or in combination with other density grids, according to embodiment. Filtering each density grid may include filtering all of the elements of the respective grid, although in certain embodiments filtered elements may be selected. Applying the digital density filtering process includes determining edge conditions for each grid element, “smoothing” temporary copies of elements of the grid, and replacing the original grid elements with the smoothed elements. More specifically, flow begins (“Start” 350) and a working copy of grid elements is created. Then additional elements are added “outside” the spatial boundaries of the temporary grid (“Populate Guard Cells” 351). The added guard elements enable more useful smoothing results in some usage scenarios. Then a local averaging is performed on elements of the temporary grid, including the guard elements (“Apply Spreading Function” 352). In some implementations the spreading function reduces numerical artifacts associated with short-wavelength density fluctuations. In some usage scenarios the numerical artifacts arise due to inaccuracies in representation of a grid or grid elements. Any combination of smoothing functions may be used, according to various embodiments, including relatively conservative and relatively more aggressive techniques. In some embodiments a binomial weighting function implementing a 1-2-1 spreading (with a subsequent division by four to preserve total mass) over spatially neighboring grid element values is used. In some embodiments the binomial weighting is performed in any number of orthogonal dimensions, up to and including the maximum number of spatial dimensions represented in the SDI simulation. After completing the spreading processing, the temporary elements are used to replace the original array elements (“Copy to Original Array” 353) and flow is complete (“End” 354). In some embodiments all of the filtering operations for all of the elements of all of density grids are completed before any of the associated temporary results replace the original elements, as the original elements are required as inputs to respective filtering computations for each grid. Alternatively, temporary copies of all of the original elements may be made, and the copying may occur as filtering result are made available. Other similar arrangements of original and temporary element management with respect to filtering computations are envisioned. As mentioned elsewhere herein, processing according to the illustrated flow is entirely optional, according to embodiment. In addition, in some embodiments multiple iterations of the flow may be performed, in some usage scenarios using varying filter functions. Consequently zero or more iterations of the illustrated flow are performed (the iterations are not explicitly shown), according to application requirements and implementation. FIG. 3I is a flow diagram illustrating selected details of an embodiment of interpolating gate fields to nodes, such as operations referred to elsewhere herein (“Interpolate Gate Fields to Nodes” 338, of FIG. 3C, for example). Conceptually field components calculated according to the (discrete) grid are mapped onto the continuous spatial coordinates of node locations. In some embodiments the mapping is according to the node mass accumulation (such as summations performed in “Accumulate Gate Densities” 331). In other words, if an N-point spline technique is used to accumulate densities, then an N-point spline technique is also used to interpolate fields to nodes, and the value of N is the same for both techniques. Using matched spline weights during accumulation and interpolation prevents “self-forces” that would otherwise arise and spontaneously propel a node inconsistently with forces acting on the node. More specifically, flow begins (“Start” 360) by initializing node force values (such as to zero), and then a check is made as to whether processing is complete for all nodes in the simulated system (“Iterated Over All Nodes?” 361). If so, (“Yes” 361Y), then gate field interpolation processing is complete (“End” 365). If not, then a first (and subsequently a next) node is selected for processing, and flow continues (“No” 361N). Spline coefficients are then determined for the node (“Determine Spline Weights” 362), based in part on user input in some embodiments (such as those from “Commands and Parameters” 130, of FIG. 1). In some embodiments the user input is chosen to drive balancing corresponding device distribution throughout an integrated circuit die. After all the spline weights for the respective node have been determined, a check is made to determine if all fields affecting the respective node have been processed (“Iterated Over all Fields” 363). If so (“Yes” 363Y), then processing loops back to check if all nodes have been processed. If not, then a first (and subsequently a next) field is selected for processing, and flow continues (“No” 363N). The force contributed according to the respective field is accumulated with forces associated with other fields (“Sum Field Contributions to Force on Node” 364). The accumulation is according to each orthogonal spatial dimension associated with force modeling (i.e. x and y for two-dimensional systems and x, y, and z for three-dimensional systems). Flow then loops back to determine if all fields have been processed. Depletion Weighting The effect a node has on local density and resultant forces may be “artificially” increased (or decreased) to expedite nodes moving to more satisfactory placements more quickly. Local density modification may be considered to be a result of manipulating a weighting associated with the mass of one or more nodes, and is referred to as depletion weighting. In other words, depletion weighting is a technique that may be used to drive the system to the point of legality in an SAF flow via dynamical means. By providing a dynamical solution to the problem, a higher quality result may be obtained in some usage scenarios. In certain embodiments depletion weighting operates by attaching a modifier to the density contributed by a node and the expansion field force acting upon it. In some embodiments an expansion field without depletion weighting is used. In some embodiments an expansion field with depletion weighting is used. In some usage scenarios the depleting weighting improves any combination of actual node resource footprint, block footprint, and block capacity. In some usage scenarios the depleting weighting results in nodes being driven apart only as far as necessary to achieve legality. In certain embodiments the depletion weight is calculated from a weighted sum of the differences between the available resources and the node resource footprint onto a quantization block, i.e. the amount of resource depletion caused by presence of the node in its current state. The depletion weight acts as a simple linear weight modification to both the density contributed by the node (in accumulation processing phases) and force acting on the node (in interpolation processing phases), and dependencies computed as: dpwt=(1+m)ˆpdpwt where pdpwt is the power-law configuration parameter (that in certain embodiments defaults to 0, i.e. no modification), and the modifier “m” is as defined below. There is in addition a linear term and configuration parameter cdpwt (that in certain embodiments defaults to 1, i.e. no modification) that in some usage scenarios enables improved results compared to the power-law form alone. The weights are computed differently if the quantization block is depleted in any one of the resources required for the node. For example, a node may be oversubscribed in only a single resource, but undersubscribed for others, leading to no net result unless resources are considered individually. Thus, if any resource appears depleted with respect to requirements for a node, then only the depleted resources are considered. In some usage scenarios the node is thus “coerced” out of a quantization block by depletion weighting related expansion forces. The following equations are used when there is depletion for at least one resource. Nomenclature: f_a node footprint for atom (a) b_f_a block footprint for atom (a) b_c_a block capacity for atom (a) For overfull (i.e. depleted) quantization blocks, the modifier m is given by: m=cdpwtsum—a{f—a(b—f—a−b—c—a)/b—c—a} where only terms with (b_f_a−b_c_a)>0 are considered, sum_a indicates a sum over all values of iteration variable “a”, and the term atom refers to a slot in an underlying SAF. The modifier ensures that (a) resources that are more limited are given higher weight, and (b) nodes possessing multiple depleted resources have higher weight. For the case of no depletion, the modifier m is given by: m=sum—a{f—a(b—f—a−b—c—a)/b—c—a/b—c—a}/sum_a{f—a/b—c—a} where (compared to the depleted block case) additional terms serve to map the amount of depletion onto the range [−1,0] (resulting in a weight in the range [0,1]). Thus m=−1 is the minimum when the block is completely empty and m>0 when the block is full. In some embodiments depletion zones may be treated differently from one another. In some embodiments a simpler normalization multiplier is used, i.e. 1/sum_a{f_a}, having the effect of treating all depletion zones equally. In some embodiments where depletion zones are treated differently from one another, depletion weighting tends to reduce density contributed by nodes that “fit” and to increase density for nodes that “don't fit”. Also, nodes that fit tend to be affected by weaker expansion forces and nodes that don't fit tend to be affected by stronger expansion forces. Thus the net effect of the depletion weighting is that nodes that easily fit contribute a smaller density and are affected by a lesser force from the expansion fields, but nodes that don't fit contribute a larger density and are affected by a stronger force. The variation in forces tends to contribute to forward progress in several ways. The density differential between nodes that are fitting and those that are not creates a situation where the system naturally (thermodynamically) evolves to a lower energy state, where everything fits. Also, the force differential provides a direct dynamical mechanism to cause non-fitting nodes to leave an overfull block (as a result of the density surplus and the attendant local expansion field) before other nodes get a chance to leave the block. In some embodiments a depletion weight technique calculates the node depletion weight at each of the nearest neighbor grid points used in the accumulation and interpolation, so that nodes near a block boundary are subject to forces due to the inclusion of the node in the neighboring block as well the bock the node is included in. In certain usage scenarios this prevents nodes from oscillating (or “sloshing”) between blocks when there is likely no benefit to be gained from the oscillation. The induced per-block expansion field tends to drive non-fitting nodes towards the boundary where they may tend to cluster temporarily if the neighboring block does not have the capacity to accept them. The cluster may be, however, a transient effect. Nodes that are bunched near the edge of a block either slide along the edge until reaching an accepting block on either side, or hover at the edge until conditions in the nearest neighboring block become favorable for transit. Exclusion Zones In some embodiments various regions, or exclusion zones, may be defined that are not allowed to include any morphable-devices, any placed elements, or any elements of certain types, according to various usage scenarios. During later stages of global placement iterations, exclusion zones may be processed to provide gradually growing regions of higher density fields that result in repulsing forces that tend to expel nodes from the exclusion zones. In certain embodiments the exclusion zones “grow” as simulation time moves forward, starting out as point particles (like nodes), as miniature representations of the desired exclusion zone (the miniature having an overall shape and aspect ratio equal or nearly equal to the desired exclusion zone), or as two-dimensional lines, according to various usage scenarios. Subsequently the starting representation evolves into an ever-growing object until the object matches the desired exclusion zone in size and location. Similarly exclusion zones specified as strips across the entire area being placed and routed begin as an exclusion line and grow over simulation time into an exclusion area equal in dimension and location to the required exclusion zone. Exclusion zones (also referred to as “xzones”) are a way to model architectural entities that explicitly prohibit inclusion of all non-qualifying node (or corresponding device) types, while preserving the SDI-based numerical model. In certain embodiments all adjacent xzones are collapsed into a single xzone, to simplify treatment. In some embodiments simulation proceeds according to the laws of motion defined elsewhere herein, ignoring xzones, allowing the netlist a relatively large amount of time for detangling. Once the nodes are suitably spread, a transition is made to “exclusion mode” where the xzone constraints are obeyed. A first technique to manage the transition is to explicitly move nodes out of the way, starting from the center of the exclusion zone and continuing outward. In some embodiments the outward processing is gradual to reduce disruption caused by spatial shifting of the nodes. The center of the xzone and moving xzone boundaries are defined to push nodes in a desired direction, i.e. in the direction of accessible final placement states. For exclusion zones that are in the form of a stripe along the entire chip area, nodes are moved to one or both sides as appropriate. For exclusion zones that are in the form of isolated rectangles, the nodes are moved in a ray from the center point to the affected node, to spread out the distribution in an isotropic manner. A second technique is to apply an artificial density enhancement to the area inside the exclusion zone as it slowly expands. In this technique, twice the average density on the xzone boundary is imposed in the interior of the xzone during transition. This provides a dynamical shove against the nodes in advance of the approaching barrier. After the xzone transition is complete, simulation continues as during the xzone transition, but with added constraints including: Nodes are snapped to xzone boundaries at the end of each timestep. A node may “tunnel” to the other side of an xzone if energetically favorable (see “Tunneling Congestion Relief” located elsewhere herein for additional information); and The density fields obey specified parity boundary conditions at the edge of each xzone, to ensure physically relevant behavior at the boundary. In some implementations even parity is used, and in some implementations periodic parity is used. Simultaneous Dynamical Integration (SDI) Simulation SDI simulation (also known as Particle In Cell (PIC) simulation) provides approximations to solutions of Newton's second law (i.e. force equals mass multiplied by acceleration, or F=ma), as expressed by a system of coupled ordinary differential equations. For each node, the sum of the forces (also known as forcing terms) acting on the respective node is equal to the mass of the respective node multiplied by the second derivative with respect to time of the state-space representation of the node. In some embodiments nodes are restricted to planar (i.e. two-dimensional) movements, and there are four equations per node (x-position, y-position, x-velocity component, and y-velocity component). In some embodiments nodes are not so restricted (i.e. allowed three-dimensional movements), and there are six equations per node (x, y, and z-positions, and corresponding velocity components). FIG. 4 is a flow diagram illustrating selected details of an embodiment of SDI modeling and simulation, such as operations referred to elsewhere herein (“SDI Simulation” 306, of FIG. 3A, for example). Overall the illustrated processing serves to advance a dynamical system simulation forward in time, updating state-space variables according to Newtonian mechanics. Processing begins (“Start” 401) and the system of coupled ordinary differential equations is approximately solved by numerical integration for a short delta simulation time interval (“Integrate Time Forward” 402). Changes to all of the state variables for all of the nodes are then simultaneously processed (“Update State Variables” 403), based on the numerical integration. In some embodiments relatively small-scale changes are then made to one or more of the forces and masses of the system (“Micro Adjust Forces” 404 and “Micro Adjust Masses” 405), according to a specified or a computed rate of change, in certain usage scenarios to provide more nearly continuous changes to state-space variables than would otherwise be possible. The changes to the force(s) are in addition to changes naturally arising due to the advancement of simulation time. For example, in some embodiments large-scale force (and mass) changes (such as “Macro Adjust Forces” 304 and “Macro Adjust Masses” 305, of FIG. 3A) are partially effected by incremental changes. The new system state is examined (“Finished” 406) to determine if the SDI simulation is complete via a test of an end condition. An example termination condition is completion of simulation of a specified time interval. If the SDI simulation is finished (“Yes” 406Y), then processing is complete (“End” 499). If the end condition is not satisfied, then flow loops back for further simulation forward in time (“No” 406N). In some embodiments configurable settings are adjusted prior to or in conjunction with continuing SDI simulation (such as settings associated with “Commands and Parameters” 130, of FIG. 1). Numerical integration techniques compatible with the time-integration include Runge-Kutta, predictor-corrector, leap-frog, and other similar integration techniques. Various embodiments use any combination of integration techniques. In some embodiments the time-integration is according to a fixed timestep, while in other embodiments the integration is according to an adaptive timestep. The adaptive timestep results in reduced integration costs during system simulation time periods of slowly changing state variables and improved numerical accuracy during system simulation time periods of rapidly changing state variables, or otherwise “stiff” governing equations. In some embodiments the integrator (such as used in “Integrate Time Forward” 402) receives an input Delta-t (an amount to advance system simulation time). In some embodiments the integrator provides an actual Delta-t (an amount system simulation time actually advanced during the integration) and a suggested Delta-t for use in succeeding integration timesteps. In some of the adaptive timestep embodiments one or more of the actual and suggested Delta-t values are used to control the adaptive timestep. While the discussion of SDI is specific to global placement, the technique is applicable to other functions of the aforementioned place and route flow, including any combination of global placement, legalization, detailed placement, and routing. Legalization Conceptually legalization determines if the global placement is likely to be usable for a successful detailed place and route, and if not, legalization attempts to improve placement before proceeding to detailed placement. The determination of suitability for detailed placement includes assessing one or more metrics correlated with local solvability of placement (and routing) problems not addressed by global placement. In some embodiments one of the metrics includes sectioning all of the devices according to a grid (such as a regular grid) of analysis windows, and determining locally if within each analysis window resources exceed (or fall below) requirements. If all of the analysis windows are simultaneously solvable (i.e. available resources meet or exceed requirements), then detailed placement and routing is likely to succeed without additional refinements to the global placement. Improvements, or corrective actions, may take various forms including any combination of “moving” devices from one region to another, transforming devices from one implementation form to another, and partitioning-related strategies. FIG. 5A is a flow diagram illustrating selected details of a first embodiment of resource reconciliation, as a first example of legalization (such as “Legalization” 203, of FIG. 2). Overall the flow includes determining a size of an analysis window and allocating all devices in groups to their respective containing windows, and sub-dividing and transforming logic functions to reduce resource over-subscription. The flow also includes checks to determine if the devices allocated to each window may be implemented with the resources available in the window (i.e. no analysis window is over-subscribed), and if continued iterations are likely to provide improved results. Processing begins (“Start” 501) with global placement information (such as produced by “SDI Global Placement” 202, of FIG. 2, for example). The global placement result may not be legal (i.e. in a standard cell flow devices may be overlapping, or in a structured array flow more resources may be used than are locally available), but is good enough to continue processing via refinement techniques implemented in legalization. An analysis window is determined (“Quantize” 502), corresponding to a quantization block size, and conceptually replicated in a regular contiguous (but not overlapping) fashion such that all of the devices in the netlist are allocated to one (and only one) window (some windows may be devoid of devices). In some embodiments relating to a structured array design flow, the analysis window is a rectangular shape having a size that is an integer multiple of a corresponding SAF tile. In some embodiments the analysis window is aligned with respect to SAF tiles. A first determination as to whether all of the analysis windows (also referred to as quantization blocks or simply “Q-Blocks”) are simultaneously legal, i.e. none are over-subscribed, is made (“All Q-Blocks OK?” 503). If all of the Q-Blocks are legal, then legalization processing is complete (“OK” 203Y) and processing continues to detailed placement (see FIG. 2). Otherwise (“No” 503N) the devices are sub-divided (“Partition” 504) via partitioning strategies including any combination of fixed blocks, recursive bisection, and other similar techniques, according to embodiment. A second legalization check is performed (“All Q-Blocks OK?” 505) that is substantially similar to the first check. As in the first checking case, if all of the Q-Blocks are legal, then processing is complete (“OK” 203Y) and the legalized result is ready for detailed placement. Otherwise (“No” 505N) the devices are transformed (individually or in groups) to logically equivalent formulations having reduced resource over-subscription (“Morph” 506). The transformation, or morphing, operations are directed to manipulate the netlist such that logic functions requiring resources not available in a Q-Block are implemented as logic functions using resources that are available. As an example, an OR function required in a Q-Block exhausted of OR gates may instead be implemented as a NOR gate followed by an inverting gate, if a NOR gate and an inverting gate are available in the Q-Block. Morphing may be used in usage scenarios including structured array regions. A third legalization check is performed (“All Q-Blocks OK?” 507) that is also substantially similar to the first check. As in the first checking case, if all of the Q-Blocks are legal, then processing is complete (“OK” 203Y) and the legalized result is ready for detailed placement. Otherwise (“No” 507N) a determination is made as to whether further legalization iterations are likely to result in improvement (“Continue?” 508). If continuing is potentially beneficial (“Yes” 508Y), then one or more adjustments are made to the analysis windows (“Adjust Q-Blocks” 509), and flow loops back to repeat processing starting with quantization. In some embodiments the adjustments include increasing the Q-Block size in one or more dimensions according to a granularity that is an integer multiple of a corresponding dimension of an underlying SAF tile. For example, the Q-Block size may start out as “1 by 1” (i.e. equal in size to the SAF tile), then be increased by one in the first dimension to “2 by 1” (i.e. twice the SAF tile size in the first dimension), and then be increased by one in the second dimension to “2 by 2” (i.e. twice the SAF tile size in the second dimension). Alternatively, the Q-Block size may be successively lowered, or may be increased in one dimension while being decreased in another, according to various embodiments. More than one Q-Block size choice may result in legal or otherwise useful results, according to various characteristics of the results (such as minimum and maximum local resource utilization, and other similar metrics). If it is determined that continuing legalization processing is not useful (i.e. not likely to further a solution), then processing is also complete (“Not OK” 203N) and subsequent processing includes one or more revisions (see FIG. 2). In some embodiments checking if a Q-Block size equals or exceeds a predetermined value (either before or after one or more adjustments) is part of the continuation determination, as legalization achieved with relatively smaller Q-Block sizes, in some usage scenarios, is more likely to result in successful detailed placement. FIG. 5B is a flow diagram illustrating selected details of a second embodiment of resource reconciliation, as a second example of legalization (such as “Legalization” 203, of FIG. 2). Flow begins (“Start” 520) and proceeds to determine a window for quantizing (“Quantize at Specified Window Size” 521), binning elements into Q-blocks and optionally morphing selected elements to find a legal result. All Q-Blocks are then tested to determine if or to what extent resource conflicts exist (“All Q-Blocks Legal?” 522). If all Q-Blocks are simultaneously free of resource conflicts (“Yes” 522Y), then processing proceeds to mark the current state as a possible solution (“Nominate Current System State as Candidate Solution” 531). A test is then made to determine if the current Q-Block is a minimum size Q-Bock (“Q-Block Window Size at Smallest Possible Dimensions?” 532). If so (“OK” 203Y), then processing is complete and the result is ready for detailed placement. If the current Q-Block is not the minimum size (“No” 532N), then processing proceeds with a smaller window (“Reduce Target Q-Block Window Size” 533). Flow then loops back (“Go to Start” 535) to attempt processing with the reduced window size. If at least one Q-Block has a resource conflict (“No” 522N), then a determination is made as to the severity of the remaining conflicts (“Characterize Extent of Quantization Failure” 523). In some embodiments the determinations include “Easy”, “Hard”, and “Extreme” cases. Relatively simple conflicts (“Easy” 528) are processed by depletion weighting (“Activate/Tune Depletion Weighting” 524), and relatively more difficult cases (“Hard” 529) are processed by modifications to repulsive (or spreading) force sources (“Adjust Spreading Field Strengths” 525). Processing for the Easy and Hard cases then flows back to repeat all or portions of global placement (as revisions in the context of FIG. 2) according to depletion weighting activation/tuning or adjusted spreading strengths (“Back to Global Placement” 527 and then “Not OK” 203N). Substantially more difficult cases (“Extreme” 530) are processed by partitioning (“Go to Partitioning” 526). The determination of conflict severity or difficulty may include examination of objective factors (such as a ratio of resources demanded compared to supplied in the Q-Blocks or other computable figures of merit), and may also include examination of subjective factors (such as how much processing time has already been expended during legalization, and other similar progress indicators), according to various embodiments. In certain usage scenarios, upon entry to legalization, there may be a subjective perception that the system is far from legal due, for example, to over-concentration of nodes of one or more resource classes (such as Nand2, Nor2, Mux2, Inverter, and so forth) in certain regions. In some usage scenarios the strength of the spreading forces acting on the over-concentrated resource class is increased, and earlier processing (such as global placement processing with revisions via “Not OK” 203N of FIG. 2) is repeated. In other usage scenarios, if the resource imbalance is mild, then an attempt may be made to gently nudge the system with depletion weighting activated as revised global placement processing (such as via “Not OK” 203N of FIG. 2). However, if extended time-evolution with increasingly powerful depletion weighting does not resolve the conflicts, then in certain embodiments the quantization failure may ultimately be deemed “Extreme” even though only a comparative paucity of Q-Blocks show only slightly over-subscribed resources. As the depletion weighting influencing factors become increasingly strong, the governing dynamical equations become stiff, and the overall assessment of legalization difficulty may be escalated to extreme, even though over-subscription is small. According to various embodiments assessment of legalization difficulty includes any combination of examining the system state, the netlist topology, the timing constraints and the architecture definition. In some embodiments of the flow for standard cell implementation technologies, legalization may be pursued via modifications or adjustments to the spreading force strength. For example, the masses of nodes may be directly correlated to the areas of the standard cells, and the capacity of each Q-Block directly correlated to the respective Q-Block area. Thus spreading forces may be used to drive density so that area consumed by nodes within a Q-Block is no greater than the area of the Q-Block. When achieved, legalization is complete and flow proceeds to detail placement. In some embodiments legalization may be pursued via partitioning, optionally in combination with spreading force strength adjustments. Partitioning FIG. 5C is a flow diagram illustrating selected details of an embodiment of partitioning (such as processing performed as a result of “Go to Partitioning” 526, of FIG. 5B). Flow begins (“Start” 540) and then a technique for partitioning is chosen (“Select Partitioning Algorithm” 541) via any combination of manual (user directed) or automatic (software determined) mechanisms, according to various embodiments. If a Q-Block technique is chosen (“Q-Block Edge Flow” 542), then processing is performed for each Q-Block (“For Each Q-Block” 543). If a Bi-Section technique is chosen (“Recursive Bi-Section” 548), then processing is performed for each of a set of progressively smaller windows (“For Each Window” 549), starting, in some embodiments, with a window size equal to the entire place and route region, and proceeding to progressively smaller and smaller windows. Processing for each Q-Block according to the Q-Block edge flow technique includes determining nodes causing resource conflicts (“Identify Nodes Impinging on Over-Subscribed Resources” 544), followed by choosing an exit edge (“Pick Edge to Flow Through” 545) for the nodes that are impinging. Then the nodes are ranked, for example, by separation from the chosen exit (“Prioritize by Distance to Edge” 546) and then moved across the exit edge (“Push Nodes Across Edge Until Legal or Balanced With Respect to Resource Class” 547), thus entering a different Q-Block. After all Q-Blocks have been processed, a determination is made as to whether a legal result has been obtained (“Legal Result?” 559). If a legal result has not been obtained, then one or more revisions are indicated and earlier processing is repeated ((No) “Not OK” 203N). If a legal result has been obtained (“Yes” 559Y), then the current configuration is nominated as a candidate solution, as in other legalization techniques (“Nominate Current State as Candidate Solution” 560). Processing may then proceed to detailed placement (“OK” 203Y), or may return for further legalization processing with a goal of achieving a legal result at a smaller Q-Block size (Not OK, 203N), conceptually as a revision to legalization processing as described with respect to FIG. 2. Processing for each window according to the recursive Bi-Section technique includes formulating two sections to break the window into (“Introduce Cut Line Across” 550) and then determining resource requirements and availability in each of the sections (“Count Resource Supply/Demand in Each Region” 551). Nodes are then moved between the sections (“Exchange Circuit Nodes Across Cut Lines Until Legal or Fail” 552) until successful (“Legal” 557) or no further improvements are possible (“Fail” 556). If the result is legal, then the current state is marked as a possible result (“Nominate Current State as Candidate Solution” 553) and then a determination is made as to whether a smaller Q-Block should be attempted (“Desired Q-Block Configuration?” 554). If a target Q-Block size has not been reached, then flow returns back (“No” 558) to continue bisecting windows. If the target Q-Block size has been reached, then processing is complete and flow may proceed to detailed placement (“OK” 203Y). In some embodiments the recursion operations are according to a tail recursion formulation, and testing for the desired Q-Block configuration may include a tail recursion end check (for example, if the next region is smaller than a predetermined end condition size) as an iteration termination condition for recursive window processing. In some embodiments for use in an SAF flow context the predetermined end size is equal to an SAF tile size. If no further improvements are possible (via “Fail” 556), then flow continues (“Done” 555) where a determination is made as to whether an acceptable candidate solution has been found (“OK” 203Y) and detailed placement may follow, or whether revisions and repetition of earlier processing are indicated (“Not OK” 203N). Nodes may be selected for speculative migration across the cut line according to any combination of various criteria, including proximity to an edge, a footprint onto over-subscribed resources, and any other related reason, according to embodiment. In some embodiments speculative expulsion of a node from one side of the cut line to the other side may include morphing operations on any combination of nodes on the one side, the other side, and both sides. The morphing operations are directed to discover suitable implementation forms for all nodes such that nodes in each containing region may be fully implemented using only resources in the respective containing region. Detailed Placement Conceptually detailed placement serves to fine-tune placement as produced by legalization, determining final placement of all the devices of the netlist. In certain embodiments operations are relatively limited in scope, focusing on optimizations and refinements generally limited to a region corresponding to a Q-Block. Particular detail placement techniques are described in detail in the SAF embodiments illustrated herein. Nevertheless, any of a variety of detail placement procedures and techniques may instead be employed, as the specific mechanism for performing detail placement (assignment of devices to specific, non-conflicting locations) is not a limiting aspect of the SAF techniques described herein. In some SAF embodiments illustrated herein legalization produces Q-Blocks where supply is known to meet demand. Since the SAF already has the resources laid out in some structured manner, there is thus certainty of the existence of a fitting assignment of resource instances in the netlist to resource slots in the SAF. Consequently, there is no risk of failure to find a detailed placement solution, and moreover the Q-Blocks can be detail placed independently, including in certain embodiments, in parallel, concurrent operation. Some embodiments use continuous variables during global placement to specify placement position. Conceptually, the position coordinates determined by global placement in these embodiments may be considered as “optimal” locations for each node, when interpreted as being representative of the collective configuration of all circuit elements. Detail placement attempts to find actual resource slots in the SAF for each resource instance in the netlist such that all resource instances are simultaneously slotted as close as possible to the coordinate calculated during SDI-directed global placement. Stated differently, a collective assignment of all resource instances to resource slots is sought for each resource class in the SAF, such that the overall variance from the coordinates assigned by global placement (and possibly modified during legalization) is minimized or reduced. Some embodiments slot each node independently in the closest available unoccupied slot (instead of prioritizing individual nodes). FIG. 6 is a flow diagram illustrating selected details of an embodiment of detailed placement useful in a variety of applications (such as processing performed in relation to “Detailed Placement” 204 of FIG. 2). The illustrated flow may be used in design techniques relating to SAFs. Overall the flow includes determining a prioritized order to satisfy resource requirements and performing limited-scope optimizations, according to various embodiments. The flow may iterate internally to provide successively more refined solutions, and terminates when an acceptable result is found, or when it is determined that further iterations are not likely to produce improved results. Flow begins (“Start” 601) upon receipt of placement information as produced by legalization (such as “Legalization” 203 of FIG. 2, for example). As represented by “Assign Resources” 602, resources are prioritized by class. In an illustrative embodiment the prioritization is in accordance with a function of demand for resources of a respective class and supply of SAF resource slots, the slots being consumed by the resource instances of the respective resource class. The prioritization is carried out such that as the percentage of consumed slot supply increases, the priority of the respective resource class is increased, and as the supply of resource slots increases (irrespective of demand), the priority of the respective resource class is decreased. The function is used to evaluate the priority of each resource class, and assignment of resource instances to resource slots is performed one resource class at a time, in the determined priority order of resource classes. In some of embodiments the prioritization is done on a Q-Block basis. That is, the function is evaluated with respect to the demand, supply, and consumption local to each Q-Block. Iterating through resource classes in priority order, within each resource class the resource instances impinging upon the respective resource class are identified, and an initial assignment of resource instances to resource slots is generated, with each resource instance drawing the closest still-unoccupied resource slot currently available. Closeness is measured in terms of distance from a slot center to the coordinate assigned by global placement (and possibly modified by legalization), for the node containing the resource instance. Processing continues with a first form of limited-scope refinement (“Pairwise Interchange” 603), where selected pairs of allocated resources are interchanged in an attempt to discover an improved solution. In certain embodiments, within the set of resource instances previously assigned slots, speculative interchanges are considered between every instance and every other slot (whether occupied or not). In other words, a resource instance may be swapped with the instance occupying another slot, or may simply be moved to an empty slot. Each speculative interchange is scored according to a function of the slot position and the preferred position of the occupying resource (as assigned by global placement and possibly modified by legalization). An example function is the sum of the squares of the distances between the slot centers and the preferred positions. Speculative interchanges are accepted with strictly greedy semantics, on the demonstration of a reduced sum of squared distances from instance to slot. The interchange process will eventually stall when the collective variance of resource instances from desired positions can no longer be strictly reduced. In some embodiments pairwise interchanges may be evaluated according to a predicate: D(p—i,s—j′)ˆ2+D(p—i′,s—j)ˆ2<?D(p—i,s—j)ˆ2+D(p—i′,s—j′)ˆ2 where p_i is the ideal position of node I; s_j is the actual location of slot j; and D(p_i,s_j) is the distance between p_i and s_j. The sum of D(p_i,s_j′)ˆ2 over all assignments (i->j) is minimized, according to the predicate. When the collective variance may no longer be reduced, any resource instances of other resource classes that are associated with composite forms (i.e. forms realizable from resources of more than one slot, such as an And2 realized from a Nand2 slot and an Inverter slot) participating in the pairwise interchange are placed in an available slot (corresponding to an ancillary resource) that is closest to the resource instance of the respective composite form. The (ancillary) resource instance slot assignments are then marked as locked, and the ancillary instances are thereafter excluded from the set of assignable and revisable resource instances to be placed when a corresponding resource class is subsequently processed. When all resource classes in the SAF have been processed as described above, a complete and valid initial detail placement for one Q-Block has been rendered, and subsequent optimization processes are enabled. In certain embodiments, the above processes (“Assign Resources” 602 and “Pairwise Interchange” 603) are used in combination with “Dynamic Morphing” 604. In some dynamic morphing embodiments note is made of resource instances that are placed farthest from a respective desired location and improved placement of the forms is attempted by morphing to a functionally equivalent available destination form having a more suitable placement configuration of resources instances. In certain dynamic morphing embodiments, such speculation over implementation form for netlist nodes is combined with iteration over slot assignment and pairwise interchange. In the latter dynamic morphing embodiments various visited states are scored according to collective variance from preferred locations (as described above) and the best state that can be found is taken as a result. In certain embodiments states visited are limited by a computational cost criteria. Flow then continues to a third form of limited scope refinement (“Pin Swap” 605), where pin swapping directed to improve routability is performed. Here, speculation is performed over various functionally equivalent mappings of netlist nets to instance pins. As an example, the inputs of a NAND gate may be interchanged without changing the function implemented in the gate. This and other similar equivalent mappings for other gates and circuitry are selectively evaluated. By considering such netlist transformations, attempts are made to reduce the difficulty of achieving a fully routed circuit layout. In some embodiments an optional first-cut attempt at improving timing paths is then performed (“Size Devices” 606). As an example, driver sizing is selectively performed by revising the netlist to employ forms composed of resources with higher drive strengths. Optimization is not limited to such up-sizing. Selective down-sizing of drivers on non-critical paths is also performed, to free up high drive strength resources (such as in an SAF) for use by paths that are more critical. A determination is then made (“Repeat?” 607) as to whether additional iterations of all or part of the detailed placement flow is likely to improve results. If so (“Yes” 607Y), then processing loops back to resource assignment and continues forward again from there. If further iterations are found to be unlikely to offer improvement (“No” 607N), then a determination is made as to whether the results are acceptable (“OK Result?” 608). If so (“OK” 204Y), then processing is complete and ready for routing. If the results are not acceptable (“Not OK” 204N), then processing is also complete and subsequent processing includes one or more revisions (see FIG. 2). The repeat and acceptable determinations are made by any combination of automatic (such as software) and manual (such as human inspection) techniques, according to various embodiments. FIG. 6 is an illustrative example of detailed placement, as the order and/or presence of operations 602 through 606 will vary according to embodiment. That is, many combinations of “Assign Resources” 602, “Pairwise Interchange” 603, “Dynamic Morphing” 604, “Pin Swap” 605, and “Size Devices” 606, will have utility as embodiments of detailed placement, including combinations reordering and/or omitting one or more of these operations. As specific examples, some embodiments perform “Assign Resources” 602 and “Pairwise Interchange” 603 but omit “Dynamic Morphing” 604 and “Pin Swap” 605, while other embodiments selectively perform “Dynamic Morphing” 604 and then subsequently perform “Assign Resources” 602 and “Pairwise Interchange” 603. Another embodiment of detail placement re-employs SDI-directed placement methodology (targeted at a resource-level netlist) optionally constrained to a reduced sub-circuit present in a specific Q-Block. In the SDI-directed detail placement embodiment, the specific forcing terms in the system of simultaneous governing equations are modified from that described in global placement, and force models more appropriate to detail placement are substituted. For example, in detail placement, once the Q-blocks are formed and legalized, there is no further need to perform inter-Q-Block interchange of nodes. Consequently the bulk density fields that were used in global placement to control unsustainable over-concentrations of specific resource types are unnecessary by construction in the detail placement context. Thus the bulk density fields are replaced by forcing terms that represent a spring drawing the resource-level instances of each form toward the position assigned by global placement. Simultaneously, overlap repulsions arising from pair-wise occupancy exclusions between resource instances of each resource class act to drive the resource instances toward feasible slots while preserving the topological disentanglement that was a key result of the global placement previously obtained by SDI-directed techniques. The illustrated SAF embodiments emphasize a conceptual separation between global placement, legalization and detail placement, as facilitated by the described form-level netlist abstraction and the technique of morphing and facilitating data structures and SAF enabling properties. The approaches to detail placement used in the illustrative SAF embodiments herein are not meant to be limiting and other detail placement approaches may be substituted. In some standard cell implementation technologies, there is no concept of resource classes. In some usage scenarios “slots” correspond to tiled regions of a defined size. Any standard cell may be positioned at any location on a so-called standard cell grid, with the understanding that each standard cell consumes some number of contiguous abutting slots, and that neighboring standard cell instances are non-overlapping. In some implementations assessment of Q-Block legality by comparing demand for standard cell slots to the capacity of the Q-Block (determined by counting the number of contained standard cell slots), is an uncertain predictor of detail placement success. As an example, consider a Q-Block that is 10 standard cell rows high by 100 standard cell columns wide. The assigned standard cells in the Q-Block would be organized into no more than 10 rows, each row limited to 100 units (standard cell columns) in length. A detail placer may be unable to construct row-sets of instances. Continuing the example, consider 11 standard cell instances of a single cell type, the single cell requiring 51 standard cell columns. Then the Q-Block would be infeasible, even though the slot supply comfortably exceeded demand. As a result, standard cell embodiments may use a quantization (a Q-Block sizing) that is enough larger than the largest frequently occurring standard cell (in certain usage scenarios standard cells having sequential logic, a.k.a. “sequentials”) to improve the likelihood that over-concentrations of unwieldy standard cells will succeed during the slot assignment phase of detail placement. In some embodiments of a detail placer for standard cell design flows the detail placer may include a mechanism for feeding back from detail placement to legalization. In one representative standard cell embodiment, the feedback includes operating an iterative partitioner included in the detail placer. Solution of each Q-Block is attempted. If any fail, then the capacity of the failing Q-Blocks is artificially depressed. The partitioner then runs to attempt to redistribute the netlist nodes to distort the net topologies to the least possible extent, while still achieving resource legality in each Q-Block, including the effect of the artificially depressed capacity of certain Q-Blocks for the purpose of inducing the system to move some cells to different neighboring Q-Blocks in the hopes of finding a soluble configuration. Some embodiments targeting standard cell flows are based upon a conceptual framework where the global-placement position coordinates assigned to each netlist node are deemed ideal when considered as a collective determination, not as an individual determination. Consequently, the standard cell embodiment partitioner preferably seeks to move across the failing Q-Block edges whatever is already closest to the edge, and that can therefore be displaced slightly with the least distortion in the overall netlist net topology. In another representative standard cell embodiment, the cells in a Q-Block are grouped into rows, determined through considering relative juxtaposition of the cells in the coordinate that varies perpendicularly to the standard cell rows (such as the y coordinate). Thus cells at higher y position coordinate will be promoted to the row above in preference to cells with lower y position coordinate. Once the rows are formed and the contents optimized until each row fits in the width of the containing Q-Block, layout within the rows proceeds in a similar fashion. Specifically, cells are laid out horizontally within each row, and the global placement assigned x position coordinates are used to determine relative packing order along the standard cell row within each Q-Block. In another representative standard cell embodiment, the detail placement is solved via a re-employment of the SDI-directed techniques described previously for global placement. The spreading fields of global placement are replaced with forcing terms modeling a spring drawing each netlist cell instance toward the respective node position coordinate determined by global placement. Moreover, pairwise overlap repulsion interactions between neighboring nodes are included and tend to tile the nodes toward net disentanglement. In variations of embodiments of detail placement for standard cells, further optimizations may be performed through orientation speculation and pin swapping, e.g. to reduce routing congestion. The optimizations are based upon the observation that each net that crosses a given line contributes to demand for tracks crossing the line. If the demand for the tracks crossing the line exceeds the supply of perpendicular-running tracks, then routing is more difficult. However, the condition of over-demand for routing tracks may be highly localized. If nets crossing the line from opposite directions to reach pins on either side can be swapped, then the track demand is reduced by two. Techniques include pin swapping by exploitation of pin permutability semantics on an underlying standard cell (such as swapping inputs on a NAND gate) and by rotation and flipping a standard cell according to standard rules of the implementation architecture. Timing Closure and Timing-Driven Placement Conceptually timing closure and timing-driven placement operate to reduce critical timing delays to facilitate higher-speed operation of an implementation of a netlist. A high fidelity timing kernel, in conjunction with precise modeling of interconnect parasitics, specifies timing-driven attractive forces, or modifies effects of one or more net attractive forces used during SDI-directed global placement. Timing-driven forces are derived from a snapshot of state variables of the time-evolving dynamical system simulation. As the dynamical system changes (due to influences of various forces, for example), electrical characteristics of a placement of the associated netlist also change, and effects of the new state variables (such as longer or shorter interconnects) are fed back into a timing kernel to reevaluate timing characteristics of a placement corresponding to the state variables. In some embodiments timing-driven forces are calculated and applied to nets selectively, in certain embodiments as a function of any combination of one or more slack coefficients, worst negative slack values, and total negative slack values. In some embodiments timing forces may also be derived using a path-based approach, where the paths include various critical and near-critical paths according to a placement of the netlist as indicated by the state variables. Various quanta of SDI simulation time may advance between timing-driven force re-calculation, from as frequently as a single SDI iteration to as infrequently as an unbounded number of SDI iterations. For example, timing-driven forces may be adjusted on every iteration of the integration timestep or every N iterations, where N may be provided by a user, or determined by software, according to embodiment. In some embodiments, the frequency of timing update may be automatically computed by the timing kernel (in an “auto timing-directed-force update mode”) depending on the state of the dynamical system. For example, when the system is “hot” (i.e. has a relatively high ratio of kinetic energy to total energy), timing force updating is performed more frequently than when the system is “cold” (i.e. has a relatively low ratio of kinetic energy to total energy). In some embodiments the update frequency is determined in part by tracking system parameters including any combination of a cumulative node displacement since last update, a maximum displacement per net, and other similar metrics to trigger an auto-update of timing forces. An incremental timing update is performed on a timing graph when relatively small displacements of nodes are detected with respect to the prior update. Iterative slack allocation and net delay budgets are computed on the instantaneous placement every N iterations to adapt the timing budgets based on the time-evolving placements. Certain high fanout (or portions of high fanout) nets are identified as non-critical with respect to timing and have little or no timing-driven forces associated with them. False timing paths and non-critical multi-cycle timing paths are also identified as non-critical and receive little or no timing-driven force enhancements. In some usage scenarios control nets such as reset and one or more clocks may be recognized as timing non-critical. Timing critical nets (or portions of nets) are identified and receive relatively stronger timing-driven forces, in certain embodiments based on normalized timing slack determined for the net. Thus a distinct timing-driven force component may be associated with every pin on every net (or any sub-grouping thereof). In embodiments where the connectivity-based net attractive force is equal for each pin on a net, the timing-driven force tends to enable prioritizing resultant physical location according to greater timing criticality. At a macroscopic level, timing-driven forces tend to keep timing critical and near timing critical devices in relatively close physical proximity, thus reducing associated parasitics and improving timing performance. The timing-driven forces also tend to guide placements toward solutions where relatively higher drive strength devices are associated with relatively greater parasitic loads (corresponding to longer wire lengths) and relatively lower drive strength devices are associated with relatively lower parasitics (corresponding to shorter wire lengths). In some embodiments parasitics (for example parasitics of relatively short interconnects) are estimated using a simple bounding box model (i.e. net parasitics are estimated as the product of a semi perimeter of a bounding box of the pins on the net multiplied by a constant wire capacitance per unit length). In some embodiments transformations including buffering, clock tree synthesis, driver resizing, timing-based restructuring, and incremental timing post fixes are ignored during parasitic estimation, while in other embodiments the transformations are accounted for by various estimation techniques. In some embodiments parasitics (for example parasitics of relative long or relatively high fanout interconnects) are estimated after inserting buffer trees and building heuristically constructed near-Minimal Rectilinear Steiner Trees (MRST) of the high fanout nets to accurately and efficiently estimate circuit timing. In some embodiments devices are modeled as having an effective resistance that ignores input ramp time and non-linear timing response effects of the device based on output capacitive load. In some embodiments a high fidelity timing kernel propagates input ramp rise and fall times (treating them separately), and simultaneously propagates circuit ramp time from various timing start points to various timing end points. Timing exceptions (such as false and multi-cycle paths) are propagated through the timing graph to account for effects of the exceptions. In some embodiments, during placement, a lumped capacitive interconnect delay model that ignores effects of distributed Resistance-Capacitance (RC) trees is used to estimate selected parasitic effects. In some embodiments actual net routing information (or approximations thereof) forms a basis for generation of one or more distributed RC trees for estimating selected parasitic effects. In some embodiments timing closure is implemented in a Timing Kernel (TK) that dynamically updates a timing graph based on current placement state (that is in turn derived from the locations of the nodes in the SDI simulation). Net and device delays are computed and propagated to slack results on each pin, normalized slack coefficient(s) are determined, and then updated timing-driven forces are generated for use by subsequent SDI simulation. The timing graph is a graph data structure representing the netlist and includes pre-computations and pre-propagations of user-defined constraints including any combination of clock period, false path and multi-cycle path identifications, arrival times at primary inputs, and required times at primary outputs. In certain embodiments the timing graph is organized as a Directed Acyclic Graph (DAG) data structure. In certain embodiments the pre-computations and pre-propagations are generated only when a new netlist is provided or modifications are made to the current netlist. The timing graph includes timing node elements and timing edge elements. A timing node element represents pins of a macro (such as a morphable-device), and a timing edge element represents connectivity of timing node elements (such as a flattened or non-hierarchical net of the netlist). Timing delay through a timing node element (also known as a stage delay) is a function of several parameters, including a cell delay (Dc) and a wire delay (Dw). The cell delay is a function of input transition time and cell output loading. In some embodiments cell delay values are determined via a cell delay table lookup. The cell delay table may be representative of non-linear timing behavior and is specified in a timing library (such as a portion of “Technology Description” 121 of FIG. 1). Cell output transition times are also a function of input transition times and output loads, and are computed by the TK and propagated from inputs to outputs. A Steiner buffered tree constructor creates an interconnect tree based on coordinates of pins of morphable-devices. RC parasitics are then computed from the interconnect tree, and corresponding cell delays are computed according to pi-models of the RC parasitics. Wire delays are computed using Elmore-Penfield-Rubenstein delay models according to estimated net and pin parasitics. FIG. 7A is a flow diagram illustrating selected aspects of an embodiment of delay path reduction and minimization, as an example of timing closure (such as “Timing Closure” 205, of FIG. 2). As described with respect to FIG. 2, in some embodiments timing closure is essentially operative within global placement, rather than, or in addition to, operative external to global placement. In other words, in some embodiments timing closure operations are performed intimately with operations of global placement (such as those illustrated in FIG. 3A). Flows having closely associated global placement and timing improvement are known as having timing-driven global placement. For example, timing-driving forces may be adjusted (such as in “Macro Adjust Forces” 304) on every iteration (via “Repeat?” 307), or the timing-driven forces may be adjusted every N iterations, where N is computed or is provided by a user (such as via “Commands and Parameters” 130, of FIG. 1). The following discussion is according to timing closure operation within global placement, however the technique is applicable in other contexts. Processing begins (“Start” 701) with new morphable-device locations as derived from SDI simulated time advancement and resultant node location evolution. Timing node element locations and associated pin spatial positions are updated accordingly in a timing graph (“Update Pin Coordinates” 702). Approximate interconnect distributed resistance and capacitance values are determined (“Estimate Parasitics” 703) via any combination of an NBB technique (such as for short interconnects) and a Steiner-route technique (such as for long interconnects). Driver trees are then added for long and high fanout nets, and nets exceeding a specified maximum capacitance threshold (“Insert Buffers” 704). In some embodiments the driver tress are constructed according to recursive bipartition-based buffering, until a maximum drive capacity has been met. If one or more new devices are added, thus changing the netlist, then processing loops back to repeat parasitic estimation (“Changes”, 704C). If no new devices are added (for example since current buffering is sufficient or maximum drive capacity has been met), then more nearly accurate parasitic approximations are determined, in certain embodiments via Steiner-route techniques, and processing continues (“No Changes” 704N). Delays are then disseminated through the timing graph, including computing new timing edge element specific transition times (“Propagate” 705). Arrival times and required times are also propagated through the timing graph in topological order. Arrival times are propagated via a Depth-First Search (DFS) order while required times are propagated in reverse DFS order. Spare delay time is then derived for each timing node element of the timing graph (“Compute Slack” 706). The resultant slack times are then normalized and used to determine revised timing weight coefficients and associated timing-driven forces for one or more pins (“Normalize Slack” 707). In some embodiments timing-driven forces are reevaluated only for pins participating in timing critical nets. A determination is then made as to whether the timing closure is acceptable (“OK Result?” 708). If so, then flow is complete (“OK” 205Y), and processing continues to routing (see FIG. 2). If not, then flow is also complete (“No OK” 205N), but subsequent processing then includes one or more revisions (see FIG. 2). FIG. 7B illustrates a conceptual view of selected elements of an embodiment of timing-driven forces, such as used during timing-driven global placement. Driver D 715 is coupled to pins of three loads L1 711, L2 712, and L3 713, and L4 714. Each node is shown with an associated timing slack in parentheses (−2, −1, 0, and −1, respectively). Corresponding timing-driven forces are shown as F1 721, F2 722, F3 723, and F4 724 respectively. Since the timing slack for L1 711 is the most negative (−2), the corresponding timing-driven force F1 721 is the largest of the three illustrated. Similarly, since the timing slack for L3 713 is the least negative (0), the corresponding timing-driven force F3 723 is the smallest of the three illustrated. During SDI-directed placement, the action of timing forces F1 721, F2 722, F3 723, and F4 724 would be such that the dynamical system nodes corresponding to D 715 and L1 711 would experience a stronger mutual attraction than that between D 715 and L2 712, L3 713, or L4 714 other things being equal. However, in a realistic circuit, many other factors would be simultaneously considered, and moreover, more than one independent critical path could flow through any of the participating nodes. Consequently, the actual motion of the nodes may not turn out to be the same as might be indicated by such a consideration-in-isolation, as the full complexity of the dynamical system may still overcome timing forces acting on any given node. Steiner Route Tree Construction In some embodiments Steiner-route tree construction is according to a heuristic-based modified Prim-Dijkstra algorithm, including elements of Prim's Minimum Spanning Tree (MST) algorithm and Dijkstra's Shortest Path Tree (SPT) algorithm, using a coefficient alpha that is between 0 and 1. As MST yields minimum wire length (or a spanning tree) and SPT yields a minimum radius tree, the coefficient alpha enables efficient trade-offs between MST and SPT. Resistance/Capacitance (RC) Parasitic Estimation In certain embodiments, interconnect delay, or wire delay, is determined by modeling a net as a distributed RC network, with load devices presenting a capacitive load on the net. Various approximation schemes may be used, according to embodiment, to estimate the eventual routing for the net before the routing is performed (during placement, for example). The estimated routing is used in turn to derive associated approximate RC network parameters, and the RC approximations are then used to estimate timing delays, as described elsewhere herein. The RC network is divided into segments, and a wire segment delay is computed for each segment. In some embodiments the wire segment delay is computed according to an Elmore delay model (wire segment delay equals wire segment resistance multiplied by the sum of the wire segment capacitance and all of the associated input capacitances). In some embodiments the wire segment delay is computed according to a higher order moment delay calculation. In some embodiments routing associated with large (or high fanout) nets is approximated by Steiner tree graph analysis. Delays from a driver to each respective load are then determined as the sum of resistance in series between the driver and the load multiplied by the sum of the capacitance between the driver and the load, where “between” refers to the tree graph segments coupling the driver to the load. In some embodiments parasitics for short nets are estimated using net contributing factor heuristics. For example, wire capacitance from a driver to a load is equal to a load contribution factor multiplied by a “NetMSRT” multiplied by a capacitance per unit length. NetMSRT is equal to a Net Semi-Perimeter (NSP) multiplied by an “NSP-FanOut-Scaling” factor. The NSP-FanOut-Scaling factor is equal to one-half the quantity equal to the square root of the number of net loads plus one. The load contribution factor describes a relative contribution of a load with respect to all of the loads on the net, and may be expressed as the distance to the load divided by the entire length of the net. Wire resistance is derived similarly to wire capacitance, except resistance per unit length is used instead of capacitance per unit length. FIG. 7C illustrates a spatial organization (or topology) of driver D 715 and coupled loads L1 711, L2 712, and L3 713 and L4 714 of FIG. 7B. FIG. 7D illustrates an embodiment of NBB estimation of routing to cover the driver and the loads of FIG. 7C. As shown, NBB 725 covers all of the loads and the driver, and is defined by the spatial locations of D 715, L1 711, and L4 714. FIG. 7E illustrates an embodiment of a rectilinear SRT estimation to cover the driver and loads of FIG. 7C. FIG. 7F illustrates an embodiment of estimated RC parasitics associated with the RST of FIG. 7E. Timing Weights Computation In certain embodiments a timing weight is computed for all pins having a negative timing slack. All other pins are considered non-critical. Non-critical nets are marked as inactive nets and no timing forces are applied to them. Non-critical pins are assigned timing weights of zero (and thus affect no timing-driven forces). The timing weight of a pin may be modeled as a function of various timing parameters including pin slack, worst negative slack, total negative slack, interconnect length, and other similar parameters, according to implementation. In some embodiments the timing weight for a pin is equal to the square of the quantity equal to the slack of the pin divided by the worst negative slack of the entire netlist, and in various embodiments the timing weight is computed according to any number of linear and high-order calculations. The timing-driven forces are computed according to Hooke's law with a coefficient equal to the respective timing weights (i.e. timing force equal to negative timing weight multiplied by distance between driver node and load node). Selected Timing Closure User Commands Timing closure and timing-driven placement are automated to varying degrees according to embodiment. In certain embodiments the automation is controlled or directed by a plurality of control parameters provided in data files or scripts (such as via “Commands and Parameters” 130, of FIG. 1). In some embodiments a relatively small number of control parameters may be provided by a Graphical User Interface (GUI). Timing constraints are used to perform timing closure and timing-driven placement, and the GUI may also provide for user input of timing constraints files, such as Synopsys Design Constraint (SDC) compatible information, via a “source SDC” command or menu item. In some embodiments and usage scenarios design automation software (including timing closure and timing-driven placement) may be operated in a batch mode. In the batch mode any combination of selected switches may be specified in a file (such as a “schedule file”, that may be included in “Commands and Parameters” 130, of FIG. 1). A first control switch instructs SDI-driven (sometimes also referred to as force-driven) placement operations (such as operations performed by a placement engine) to apply timing-driven forces at each timestep. By default, the forces are turned off in some embodiments. Timing-driven forces are recomputed at predefined intervals, or at a selected frequency with respect to timesteps, as specified by another control switch. A second control switch instructs SDI-driven placement to perform timing analysis at predefined time intervals of the SDI simulation, and to report a specified number of critical paths or selected critical paths. In certain usage scenarios the report includes some or all of the most critical paths. If the first control switch is on, then the second control switch is automatically turned on also. However, in some usage scenarios, users may keep the first control switch off with the second control on to perform a timing analysis based on a current system configuration. Selected critical paths may then be reported at predefined intervals during SDI-driven placement. The interval may be user specified, and the reported paths may include a selection of the most critical paths, with the report including worst-negative-slack information. A third control switch controls how frequently a timing update is performed and timing-driven force computation is performed in the SDI simulation (i.e. when the first control switch is on). In some embodiments a default value for a parameter associated with the third control switch is 50; i.e. every 50 timesteps timing-driven forces are determined anew. In certain usage scenarios a larger value is specified for lager designs. For example if a design is more than one million gates, then an iteration frequency of 100 may be specified. In some usage scenarios the frequency may be adjusted dynamically (either manually by a user or automatically by software). For example, at stages of placement where changes are relatively small (such as later stages of placement), the interval may be increased. In some embodiments GUI “radio buttons” may be provided to enable a user to enable (or disable) any combination of the control switches. In some embodiments a command window (either separate from or associated with the GUI) may be used to specify the third control switch and the associated parameter. SDI-Directed Electronic Design Automation (EDA) Flow FIGS. 8A and 8B collectively are a flow diagram illustrating selected details of an embodiment of an integrated circuit Electronic Design Automation (EDA) flow using one or more techniques including SDI-directed global placement, legalization, legalization-driven detailed placement, timing optimization, and routing. In the illustrations dashed-boxes represent information provided in certain embodiments by users of the flow. In some embodiments element 815 is provided by users of the flow while in other embodiments it is generated by element 813, and thus 815 is shown having a unique dashed-box patterning. As a starting point, a design to be implemented is provided as a Hardware Description Language (HDL) or Register Transfer Language (RTL) specification (“User Verilog/VHDL RTL Design” 812). Libraries are provided describing functional and timing characteristics associated with all library cells that may be implemented on a base wafer, such as a predetermined or prefabricated structured array wafer (“Cell Timing Models (.lib)” 811). The libraries may be accessed by various tools shown later in the flow. The design is then converted to a specific implementation description according to the library and the design specification (“Synthesis” 813). Semiconductor vendor process information such as the number and type of metal layers and via layers, process design rules, and process parameters are provided (“Base Die Description” 814). The die description also includes all die floorplan information associated with implementation as a structured array, i.e. descriptions of SAF tiles. The die description is processed (“Design Create Import Verilog/VHDL” 816) in conjunction with a gate-level netlist produced by synthesis (“Gate-level Netlist (Verilog/VHDL)” 815) resulting in a parsed netlist. Selected improvements are performed, such as buffer deletion, dead logic removal, inverter pair elimination, and constant propagation (“Design Pre-optimization (buffer deletion, dead logic removal)” 817). Then directives to guide the physical design are processed (“Load Floorplanning Constraints (IOs, RAMs, group, region constraints)” 818). In certain usage scenarios the floorplan constraints are used to “lock” selected elements into desired regions of the die. For example IO pads may be assigned to the perimeter, and RAMs may be allocated to specific zones. Core logic may be guided to selected areas or grouped together as desired. In some embodiments the floorplan constraints are provided via one or more scripts (“Place Script; Floorplan Script” 822). Timing performance criteria are then processed (“Load Timing Constraints” 819), in some embodiments according to timing libraries (“SDC Timing Libraries (.lib)” 823). Information in the timing libraries may be according to an SDC format, and includes input arrival times, output required times, false path identification, and multi-cycle path notations. In certain embodiments subsequently locations are determined for all of the elements in the netlist (“Placement” 820), guided by previously provided constraints. Timing performance improvements are then made to effect timing closure (“Buffering Clock Tree Synthesis Timing Driven Buffering/Resizing” 821). Clock tree synthesis strives to meet desired clock skew constraints, and buffer resizing serves to meet user specified timing constraints. Processing then flows (via 824) to output post layout design data (“Export: DEF/Verilog” 831). In certain usage scenarios a format compatible with Design Exchange Format (DEF) is used to facilitate interchange with various EDA tools. The output DEF (“DEF” 832) specifies the structure of the design and all placement information. The output Verilog (“Verilog” 834) specifies the post-layout gate-level netlist. The DEF output is provided along with information describing routing technology (“LEF” 833) to compute interconnect details (“Router” 835). The resultant geometry is output as DEF (“Routed DEF” 836) that is processed (“3D Extractor” 837) along with the routing technology information to determine connectivity and parasitic information (“SPEF” 839). The parasitic information is according to a Standard Parasitic Exchange Format (SPEF). A timing performance check is then made (“Timing Analysis” 840) using the parasitic information, the post-layout gate-level netlist, and device characterization information (“StdCell Library” 838). A correctness check is also made (“Formal Verification” 826) by comparing a pre-layout gate-level netlist (“Pre-layout Gate-level Netlist” 825) with the intended-to-correspond post-layout gate-level netlist. In some usage scenarios the pre-layout gate-level netlist is identical to the netlist output from synthesis. The illustrated EDA flow is an example only, as some of the illustrated operations may be omitted or performed in slightly different orderings according to various embodiments. Manufacture of Devices Designed Via SDI-Directed Techniques Conceptually a structured array architecture is defined to satisfy a plurality of user-specific designs. The architecture is optionally based on a pre-characterized standard cell library. A plurality of user-specific designs are targeted for the defined architecture, and physical layout is generated at least in part based on a SDI-directed place and route flow. An inventory of wafers (or die) built according to the structured array architecture is used as a starting point to manufacture instances of the user-specific designs. Thus a single structured array architecture (and corresponding predetermined wafer inventory) serves to implement more than one user-specific design via a SDI-directed placement and routing. FIG. 9 illustrates an embodiment of selected details of manufacturing integrated circuits, the circuits being designed in part based on SDI-directed design techniques. The manufacturing flow begins (“Start” 901) by receiving objectives for a design or a group of designs (“Goals” 902) along with optional information (“Standard Cell Library” 904) regarding relatively fixed-function elements previously manufactured and characterized according to a selected integrated circuit production facility or “fab”. The received items are processed to determine one or more SAF tiles to be arrayed to form a structured array integrated circuit (“Define Structured Array” 903). The standard cell library information may be used to develop SAF tiles with lower cost than developing SAF tiles from “scratch”. Fabrication images are produced from the structured array design (“Produce Lower Layer Masks” 905). The lower layer masks are combined with starting materials (“Wafers” 906) to produce an inventory of pre-fabricated structured array die (“Fabricate Lower Layers” 907). A first and a second device are designed according to a SDI-driven place and route flow, and the resultant design databases are provided to the flow (“Device 1 SDI P&R Result” 908 and “Device 2 SDI P&R Result” 909). Each of the databases is then used to produce corresponding sets of upper layer fabrication images (“Produce Device 1 Upper Layer Masks” 910 and “Produce Device 2 Upper Layer Masks” 911, respectively). The upper layer masks are used to manufacture (“Fabricate Device 1 Upper Layers” 912 and “Fabricate Device 2 Upper Layers” 913, respectively) one or more integrated circuits according to each of the respective designs, using portions of the previously developed inventory (“Fabricate Lower Layers” 907). The manufactured devices are then tested (“Test Device 1” 914 and “Test Device 2” 915, respectively) and the flow is complete (“End” 999). Computer System Executing SDI-Directed EDA Routines FIG. 10 illustrates an embodiment of selected details of a computer system to execute EDA routines to perform SDI-directed place and route operations. There are multiple sub-systems illustrated including computing and storage complexes (System 1001A and System 1001B) and workstations (local WS 1017B and remote WS 1017C). Similar elements have identifiers using the same numerical base, and a letter suffix is used to distinguish different instances. For brevity, unless there is a notable difference between the instances, only the first instance of similar elements is described. A data processing machine (System 1001A) includes a pair of computational elements (Processors 1014A and 1015A). Each processor includes a Central Processing Unit (CPUs 1010A and 1011A, respectively) as well as working memory (RAMs 1012A and 1013A, respectively). The machine is coupled to a storage array, such as disk 1018A, that includes images of EDA software (SW 1019A) and design database information (DD 1020A). An interconnection resource (Local Area Network LAN 1016) enables local communication between System 1001A, System 101B, and workstation/PC (WS 1017B) enables local users to access the facilities to direct and observe computations. Systems 1001A and System 1001B are also coupled to Wide Area Network WAN 1030, such as a corporate intranet, the Internet, or both. Remote WS 1017C communicates with any combination of System 1001A and System 1001B via WAN 1030. In certain embodiments, WS 1017C has a disk 1018C, that includes images of EDA software (SW 1019C) and design database information (DD 1020C). In some embodiments at least part of the EDA software images may be compressed or encrypted while stored on disk. SW 1019A may include one or more machine-readable executable files corresponding to any combination of processing operations illustrated in FIG. 1, as well as any processing operations performed on behalf or under control of elements in FIG. 1. For example, global placement (such as SDI-directed global placement), legalization, detailed placement, timing closure, and routing operations may be encoded as portions of SW 1019A for execution by System 1001A. Similarly, design data (such as data corresponding to any combination of portions of “Commands and Parameters” 130 and “Working Data” 131) may be stored in portions of DD 1020A. In operation the CPUs (in conjunction with associated RAMs) execute portions of SW 1019A to perform assorted EDA functions. In some embodiments SW 1019A may include routines that are chosen (or optimized) in part to facilitate parallel execution of EDA routines (such as SDI-directed global placement, legalization, detailed placement, and routing) on CPUs 1010A and 1011A. In some embodiments the parallel execution may be carried out on System 1001A simultaneously (or overlapping) with System 1001B (via LAN 1016) such that CPUs 1010A, 1011A, 1010B, and 1011B are operating together to provide a SDI-directed EDA solution for a single user-specific design. The parallel processing is not limited to two machines, nor to machines with multiple internal processors. Rather, the parallel computation may be performed on a collection of processors, however organized or subdivided amongst independent machines. For example, the software may run on a massively parallel supercomputer, or on a network of multiprocessor computers, or on a network of single processor computers. In certain embodiments, each of System 1001A, WS 1017B, or WS 1017C may have an associated removable media drive, represented respectively by drives 1040A, 1040B, and 1040C. The removable media drives are used to load at least parts of the EDA software images, such as those discussed above, from removable media, represented respectively by disks 1045A, 1045B, and 1045C. The removable media and the associated drives can take many forms, including but not limited to optical, magnetic, and flash media, including such media as floppy disks, CD-ROMs, DVD-ROMs, and flash disks. In certain embodiments, WS 1017C transfers at least parts of EDA software images SW 1019C from either or both of System 1001A and System 1001B via WAN 1030. With or without a local EDA software image, according to various embodiments, WS 1017C may interact with either or both of System 1001A and System 1001B for the purpose of locally or remotely executing or controlling any of the global placement (such as SDI-directed global placement), legalization, detailed placement, timing closure, and routing operations, as otherwise taught throughout this disclosure. In various embodiments, WS 1017C selectively has control interactions and/or data transfers (including data related to the design database information) with respect to either or both of System 1001A and System 1001B. In various embodiments, the transfers are selectively compressed or encrypted. At least parts of the EDA software images, the control interactions, or the data transfers, are thus observable as propagated signals at points that include signal observation point 1035C and point 1035A. In various embodiments, the propagated signals selectively include interactions related to enabling and/or licensing of WS 1017C (or a particular user of WS 1017C) to locally and/or remotely execute and/or control any of the EDA operations taught herein. In certain embodiments, an FTP service is made available to WS 1017C for downloading of at least parts of EDA software image 1019C via WAN 1030. In related embodiments, the downloaded software is adapted to be a demonstration embodiment, with either limited functionality or that functions only for a predetermined interval. In other related embodiments, a software key is used by WS 1017C (obtained via WAN 1030 or other means of distribution) to enable or restore functionality of at least parts of the EDA software, whether the EDA software was loaded from removable media 1045C or propagated via WAN 1030. In related embodiments, the management and distribution of the software key is a component of the licensing process. The licensing is not limited to workstations. In an analogous embodiment, at least part of System 1001A and System 1001B are licensed using selective aspects of the above described techniques. In certain embodiments, executing EDA software, as otherwise taught herein, selectively reports license related events via WAN 1030 to license management processes running on at least one designated server. In related embodiments, the reported license related events are evaluated in accordance with predetermined criteria and alerts, reports, control events, and/or billings are selectively and/or automatically created and/or updated. SDI-Based Detailed Placement Embodiments FIG. 11 illustrates an embodiment of an SDI-based detailed placement flow useful in a variety of applications. The SDI-based detailed placement flow may replace and/or augment operations performed after global placement and before routing (such as any combination of processing relating to “Legalization” 203 and “(SDI) Detailed Placement” 204 of FIG. 2). In 1101 a legal global placement is developed (such as via “SDI Global Placement” 202 of FIG. 2). In 1102 nodes are (optionally) prevented from moving between Q-blocks, thus increasing the likelihood that a fitting (i.e. legal) global placement is retained during continued system evolution. In some usage scenarios where circuit density is at or near a threshold of what can be supported in a structured ASIC architecture, the processing of 1102 is invoked. In some usage scenarios where the processing of 1102 is omitted, subsequent legalization processing is used. In 1103 spreading force strengths are increased, and in some usage scenarios the spreading forces are substantially increased. According to various embodiments the spreading forces are increased by any combination of reducing digital filtering of fields sourcing the spreading forces, and increasing spatial resolution of a grid the spreading fields are calculated with respect to. In some usage scenarios the (substantial) increase in spreading forces does not result in (substantial) bulk motion since nodes (such as form-level nodes) are prevented from moving between Q-blocks. In some usage scenarios the (substantial) increase in spreading forces does add energy to the system, and various techniques for changing the ratio between kinetic and potential energy of the system may be employed (as described elsewhere herein). In some usage scenarios processing in 1103 serves to overcome tight packing of form-level nodes that causes local density of the form level nodes (on relatively short spatial length scales) to exceed slot density (i.e. supply) of the underlying SAF. In some usage scenarios the exceeding of supply increases effort required by a slot assigner to discriminate between alternate slot assignments. By spreading out the form-level nodes and reducing large density fluctuations on short spatial length scales, the form-level nodes within the Q-block are driven farther apart, and thus closer to coordinates of ultimate slot assignments. In some usage scenarios the reduction of density fluctuations serves to reduce dislocation during detail slot assignment, thus improving quality of the detail placement overall. In 1104 morphing is optionally repeated, with new target locations for form-centers. In some usage scenarios nodes demanding a resource may be unevenly distributed in a region, and thus some of the resource-level nodes are moved a comparatively long distance to reach a slot. The movement results in “cut inflation”, where nets are forced to be routed over relatively longer distances and thus consume more routing resources than were anticipated by the form-level placement. The cut inflation results in decreased routability. The cut inflation may be overcome by the optional morphing, to improve the balance between spatial distribution of resource slots and nodes. Nodes are then moved shorter distances during slot assignment, reducing cut inflation and routability degradation. In 1105 the netlist is elaborated with resource-level nodes and nets spanning pins on the resource-level nodes (see the discussion relating to FIG. 12A and FIG. 12B). Forces are included to tie resources to respective parent forms. In some embodiments information relating to the resource-level nodes (and associated spanning nets) is retained in extended data structures to facilitate SDI-based processing of the resource-level nodes. In 1106 forces and interaction coefficients are initialized to relatively low values for the new resource-level elements of the combined (i.e. elaborated) netlist. Integration is then resumed in 1107. The resumed integration is according to the forces and interaction coefficients for the new elements in addition to the forces and the interaction coefficients “inherited” from the global SDI-based processing. In some usage scenarios using the new and inherited forces and coefficients together results in disentanglement of the resource-level nodes now present in the netlist. Enabling the resource-level nodes to move independently of each other provides a context for resources to move left (or right) or up (or down) with respect to sibling resources of the same parent form. The movement of the resource-level forms enables more efficient slot assignments otherwise indistinguishable when only the center of the parent form is examined. In 1108 integration (i.e. time evolution of the system) is stopped according to selected criteria. In some embodiments dampening effects are increased to drive the system toward a new state reflecting separation of resource-level nodes and to prevent or reduce thrashing. In some embodiments the dampening effects are auto-regulated. The selected criteria may include any combination of a number of integrator steps, an amount of “system time”, system kinetic energy (i.e. temperature) falling to a threshold value, system kinetic energy falling by a threshold percentage with respect to an initial value, and system kinetic energy falling by a threshold percentage in a single time step. The number, the amount, the threshold value, and the threshold percentages may be predetermined or programmatically varied according to various implementations and usage scenarios. In 1109 all Q-blocks are processed. In some embodiments the processing for each Q-block is according to functions described elsewhere herein with respect to FIG. 13. In 1110 processing relating to 1109 is repeated until stopping criteria are met. In some embodiments the criteria include full placement of all resource classes. In some embodiments processing then continues according to functions described elsewhere herein with respect to FIG. 14. FIGS. 12A and 12B illustrate concepts relating to an embodiment of netlist elaboration. FIG. 12A illustrates a portion of a system with three form-level nodes located on computational grid 1210 and coupled by a plurality of form-level nets. FIG. 12B illustrates the system of FIG. 12A with resource-level nodes (corresponding to resource-level forms) for each of the form-level nodes “added” to the system. Also illustrated are connections between resource-level nodes and corresponding parent nodes, as well as resource-level nets. The parent connections and resource-level nets are representative of corresponding forces and interaction coefficients that are added to the system as a result of elaboration and in preparation for SDI-based detailed placement time evolution. The resource-level nodes and nets may be retained in extended data structures for the SDI-based processing. FIG. 13 illustrates an embodiment of detailed placement of a Q-block. In 1301 priority of each resource class in a Q-block is assessed, based on a combination of factors relating to resource supply and consumption. Less supply makes for higher priority, and more consumption makes for higher priority. Note that prioritization results naturally vary from one Q-block to another, as nodes (demand) and available slots (supply) vary from one Q-block to another. Processing according to 1310, 1320, and 1330 is then performed for each resource class in order according to the resource class prioritization. In 1310 slot dˆ2 optimized slot assignment for nodes of the respective resource class is performed via one or more techniques identical to or similar to processing associated with elements illustrated or discussed with respect to FIG. 6 (such as “Pairwise Interchange” 603). In some embodiments the slot assignment is performed using an implementation dependent technique. In 1320 resource-level macros of the respective resource class are assigned to computed (or destination) slots. The assignments are then “fixed” (i.e. prevented from moving or being reassigned). According to various embodiments the fixing may be via any combination of a variety of techniques. The techniques include: Instantaneous enactment, i.e. a node is moved directly to the destination slot and locked; Gradual enactment; i.e. a node is propelled toward the destination slot using a slow but overwhelming force, stronger than all other forces acting on the node, so that the node reaches the destination slot in an adiabatic motion over some reasonable number of timesteps and is locked there; and Direct parametric motion; i.e. a line is drawn from the current position of the node to the destination slot, and the node is moved directly along the line toward the destination slot over a series of timesteps and is locked there. In 1330 remaining unfixed elements are optionally enabled to relax according to new coordinates corresponding to the destination slot assignments most recently made in 1320. In some embodiments (such as various embodiments using instantaneous enactment) processing in 1330 is performed. In some embodiments (such as various embodiments using gradual enactment or direct parametric motion) processing in 1330 is skipped. FIG. 14 illustrates an embodiment of an additional pass of detailed placement of a Q-block. Processing according to 1410, 1420, 1430, and 1440 is performed for each resource class in order according to the resource class prioritization determined in 1301 of FIG. 13. Each resource class is unfixed in turn to enable additional relaxation. In some usage scenarios a plurality of iterations of processing of all resource classes according to FIG. 14 is performed. Unfixing each resource class enables higher priority resource classes (i.e. classes processed ahead of other classes) to relax with respect to lower priority resource classes (i.e. classes processed behind other classes). Additional Morphing Embodiments In at least some structured ASICs the supply of fundamental hardware resources is predetermined and fixed. Careful apportionment of netlist nodes into function-realization-entities (forms) can help to improve the quality of the physical solution of the EDA flow. However, size and performance constraints cause the form selections of different nodes in the netlist to be coupled, resulting in an extremely complex and thus potentially expensive computational optimization problem. A procedural approach to generating a solution includes a technique making use of Integer Linear Programming (ILP). Illustrative embodiments for circuit placement are described. A schema for representation of a circuit netlist when nodes of an initial (e.g. synthesis- or schematic-derived) gate level netlist are interchangeable with functionally equivalent alternatives implemented using different hardware resources is used. Herein, each functionally equivalent realization is called a “form”, and the initial gate level netlist is called the form-level netlist. Exchanging a form instance in the form-level netlist with a functionally equivalent alternate form is herein called “morphing”. FIG. 12A illustrates a form-level net of form-level nodes overlaid on a computational grid. FIG. 12B illustrates one type of view of an elaboration of the form-level net of FIG. 12A to include resource-level nodes in a resource-level net. FIG. 15A illustrates a form of the form-level net of FIG. 12A. In this view the resource-level nodes are shown internal to the form. FIG. 15B illustrates another form that uses different resources to implement the same function as the form of FIG. 15A. In at least one embodiment, the form of FIG. 15B is substituted for the form of FIG. 15A through a morphing process. In a structured ASIC, the supply of hardware resources is predetermined and fixed. The optimal selection of implementation form for each node in the form-level netlist is a complex problem involving many coupled considerations. For example, certain hardware resources in a structured ASIC might be faster than others, but if all form-level nodes were morphed into forms that utilize the faster resource, then the total silicon area required to implement a circuit could be greater than otherwise necessary, thus increasing cost of manufacture. A denser placement may be obtained if the form-level instances in the netlist are morphed amongst available forms so aggregate demand for each resource type across all form instances in the netlist follows the same proportional relationship as the supply thereof in the structured ASIC architecture being used to implement the circuit. However, since in such an apportionment, many form instances will be implemented using forms that require slower hardware resources, the circuit may perform slower overall. Careful apportionment of the forms among the nodes of the netlist to optimize overall performance of the circuit is important. Each change of a given form instance from one implementation form to another results in a change to timing characteristics of all logic paths through the affected node, hence providing another coupling pathway in the form determination process. Similarly, if resource exhaustion forces a node to be implemented using a form such that the nearest available implementation resources are far from the ideal location of the node, then routability degradation may occur. There are many uses of morphing in structured ASIC EDA. The following list of examples is provided for illustration only, and should not be taken as limiting. As one illustrative example, consider the case of a netlist that is to be placed in a structured ASIC logic array instance. Knowledge of whether the netlist can be packed to fit into the available resource supply of the specified structured ASIC is desired. A simple tabulation of the resources demanded by the forms in the initial gate level netlist can be performed and compared to the supply of resources in the structured ASIC logic array instance. FIG. 16A illustrates the supply and demand for resources R1 through R6 corresponding to target functions of an integrated circuit design having a first selection of forms for the target functions. For at least some of the resources, the demand exceeds the available supply. However, even if the demand for any resource exceeds supply in the structured ASIC logic array instance, then a fit may still be possible. It may be possible to morph some or all of the nodes in the form-level netlist by exchanging selected form instances with functionally equivalent alternate forms, to relieve the over demand for certain resources while increasing the demand for other underutilized resources. FIG. 16B illustrates the supply and demand for resources R1 through R6 for the same target functions as for FIG. 16A, but using a second selection of forms for the target functions obtained by morphing certain forms to use different resources. For each of the resources shown, the demand is less than or equal to the supply. In this way, a morphing operation can yield a determination of the feasibility of fitting a netlist into a structured ASIC logic array instance. As another illustrative example, consider the case of a netlist that is to be placed into the smallest possible accepting logic array instance of the structured ASIC. In this situation the size of the structured ASIC is not predetermined, but is to be an output of the netlist packing optimization problem. Possible approaches include: A) A succession of structured ASIC logic array instances of different sizes are individually evaluated using the fit-checking procedure described in the preceding example. The smallest structured ASIC logic array instance that is large enough to hold the netlist is the result. B) Morph the form-level netlist until the stoichiometric ratios of the resources demanded by the forms matches as nearly as possible with the stoichiometric provisioning proportions in the structured ASIC. Then the ratio between the corresponding elements in the resource demand versus provisioning yields the required logic array size. In yet another illustrative example, consider the case of the placement of a netlist within a specified structured ASIC logic array instance. In this case, in addition to determining if a netlist can fit, a complete final placement is sought, such that all resources consumed by forms of a form-level netlist are uniquely assigned to resource “slots” in the structured ASIC logic array instance. One approach is to divide available area into abutting blocks, and then attempt to find a morphing solution that fits a respective portion of the netlist over each block into the respective resource complement of the respective block. As with the netlist fit-checking operation described above, there may be an initial imbalance between the resources demanded by the forms and the structured ASIC logic array supply in a given region that can be relieved through morphing. Only a subset of the nodes in the netlist participate in the morphing operation, and only a portion of the resources of the structured ASIC logic array instance are available for utilization. The block morphing operation is performed on the subset of the netlist that is contained within each of the blocks. The blocks need not be of uniform shape or size. Of course, embodiments such domain decomposition and netlist subsection morphing are not the only approaches to placement generation. As long as the whole netlist is morphed to fit within the resources of the whole structured ASIC logic array instance, there will be some way that the resources of the form instances in the netlist could be assigned to resource slots. As an additional illustrative example, consider the case of placement of a netlist into a dynamically sized structured ASIC logic array instance, where the final size of the logic array is determined simultaneously with generation of a legal placement. Such a facility might work by “spreading” the netlist until nodal density fell to a point where block-based morphing (as described above) was successful for all domains containing circuit elements. The size of the final fitting configuration determines the size of the structured ASIC logic array to be used for the netlist. This example is distinct from the minimum logic array size determination example above, in that the former represents a theoretical maximum packing density determination, where all the netlist form-level nodes participate in the morph, whereas in this case there are many independent morphing problems where a reduced subset of the netlist nodes participate in the morphing operation. The size of the logic array instance that can be obtained in this way will in general be lower bounded by the former “theoretical maximum density” logic array size described in the earlier example. In general, the fewer the number of form-level instances that participate in a morphing operation, the less space-efficient the solution will be. As an additional illustrative example, consider the case of a placement flow that aims to generate a placement of a netlist using iterative refinement of morphing regions. In this scenario, processing starts with a structured ASIC logic array instance size known to be big enough to hold a morphed version of the netlist (at least as big as the minimum theoretical size produced by the logic array size minimization example in the previous section). A morphing window is defined, initially to be the size of the full structured ASIC logic array instance. The netlist is globally placed within the window using any available global placement or partitioning technique and morphing operations are attempted in subdomains (or subwindows) of the (previous) morphing window. The subwindows may be constructed by bisection of the enclosing window, or by any other suitable subdivision technique. When the global placement has evolved to the point that each subwindow is morphing soluble, the netlist nodes are constrained to stay within the subwindows, and the subwindows themselves are taken to define a reduced spatial domain for further global placement or partitioning refinement. In this way, the process proceeds by recursive subdivision of morphing windows, until some limiting cutoff criteria is reached. For example, the process might terminate when the morphing windows reach a size of 10 nanometersˆ2, or any other similar stopping criteria. Note in particular, that spatial resolution of the recursively refined morphing window grid is not required to be spatially uniform. Indeed, nonuniform spatial resolution refinement grids may be of special utility in situations with complex floorplans. Morphing Techniques Now consider a detailed description of some specific techniques for implementing morphing according to various embodiments. Morphing Techniques: Interchange Morpher An illustrative interchange morphing (problem) solver uses three specification components: 1) A library. The library is a statement of available forms, the function each form implements, and quantity of each resource that is utilized by each form. 2) Netlist nodes, each node of some particular initial form type. The netlist nodes may be a subset of the netlist. 3) Capacity of resources provided by the structured ASIC. The capacity may be a subset of total resources available for placement. In some usage scenarios the capacity is specified as an array of integers, indexed by an identifier of the resources in the structured ASIC logic array architecture. Interchange morphing proceeds in stages, as follows: 1) Assess initial demand for resources by accumulating demand for each resource type by the form of each participating node. In pseudo-code: for_each node n do: f=n.form for_each resource r do: footprint(r)=footprint(r)+library.resource_demand(f,r) If footprint(r)<=capacity(r) for each r, then the nodes fit on entry and no additional morphing is required in order to achieve a fit. In some usage scenarios additional morphing may be desirable, since there are many factors of interest besides just placement feasibility. 2) Take forms without alternates. Depending on the specific construction details of the structured ASIC library, there may be forms with no alternates, i.e., functions with only one way to be implemented in the structured ASIC architecture (that is specified in the library). Forms without alternates will not be morphing since there are no interchange possibilities, so the forms without alternates are taken as is. One way to do this is to remove the forms from the morphing participation set, and remove resources consumed by the removed forms from the resource capacity vector. Alternatively other bookkeeping strategies may be used. 3) Register balancing. In some structured ASIC architecture configurations, the forms implementing sequential (register) functions are restricted, having much reduced morphability (fewer alternate implementation forms) compared to combinational forms. For example, there may be only one or two sequential resources (flip flops) in the structured ASIC architecture, from which the sequential forms can be built. Often there is only a single sequential form per sequential resource type, for the sequential functions. In contrast, it is not uncommon for combination functions to have a dozen alternate implementation forms, with corresponding resource demand touching each non-inverter resource type. Because of the reduced implementation flexibility, it may be desirable to resolve sequential balancing next. This can be done, for example, by the following procedure. Score sequential nodes according to respective footprints onto oversubscribed resources. Sort the nodes by the scores, so the higher scoring nodes are considered first for morphing into alternate forms. For each sequential node with a footprint onto an oversubscribed resource, score each respective alternate form according to an objective function, and select the best scoring form. If the selected form is different from the current form, then a morph is performed. After each morph, check to see if the sequential resources have been brought into alignment with the resource supply. If so, then exit the register balancing processing, and otherwise continue to the next node. Aspects of certain objective functions will now be detailed. Other objective functions may also be used, thus these embodiments are merely illustrative and not limiting. For scoring sequential forms, founding some usage scenarios it may be useful to accumulate 1 (one) for each combinational resource utilized, plus 10 times the number of any oversubscribed resources used by the form. Lower scores are thus preferable. For combinational forms, in some usage scenarios it may be useful to accumulate for each resource ‘a’ utilized by the form, the quantity: double sa=(100.cfpatfpa)/capacity—a(tfpa>capacity[a]?(100.tfpa/capacity—a): 1.); where cfpa is the form footprint onto resource a, tfpa is the total footprint onto resource a if the form were to be chosen, capacity[a] is available supply for resource ‘a’ in the current morphing context, and capacity_a is the same as capacity[a], unless capacity[a] equals zero, in which case capacity_a is 0.01 (to avoid division by zero). The formula has the property of heavily costing demand for oversubscribed resources, and of accentuating the cost of using forms with a footprint onto resources that are provided in smaller proportions by the structured ASIC architecture. In some embodiments alternate mathematical formulas provide similar behavior. 4) Morph combinational nodes. Similar to register balancing, remaining as yet unmorphed non-sequential (e.g. combinational) nodes that have a footprint onto an over subscribed resource are identified. The alternate forms are scored according to the objective function, and the best (lowest cost) morph selected. In some usage scenarios the combinational node morphing results in a collection of nodes that have been morphed to fit within a resource supply of a specified problem context. In some usage scenarios the combination node morphing results are insufficient, and the following additional procedures may be optionally invoked. 5) A morph away from an oversubscribed resource may be blocked because alternate forms all have a footprint onto some resource that will become oversubscribed if the morph is taken. Thus ways to “make room” for forms that will be coming out of oversubscribed resources and impinging upon different resources than a starting configuration are searched for. One technique is to “extract” inverter forms. Since the inverter function can be implemented with essentially any combinational resource, there is really no danger of an inverter being unable to be reinserted, if there is room. The technique comprises extracting inverters, scoring forms with a footprint onto oversubscribed resources using the objective function, and then taking the best scoring alternate form. Finally, the inverters (the forms implementing the inverter function) are added back in, morphing as necessary to attempt to achieve a fit. In some usage scenarios 5) is run after the procedures 1 through 4, although this is not required. 6) Building on 5), morphing may be inhibited whenever a destination resource is fully occupied. Thus in addition to extracting the inverters, any forms that impinge on almost-full resources are also extracted. The extracting opens up additional space so that when iterating through the forms impinging on over-subscribed resources, there is more room in resources that previously appeared full. Then the full set of removed nodes are reinserted, morphing as needed. In some usage scenarios 6) is run after 5), but this is not required. Morphing Techniques Integer Linear Programming Based Morphing Some morphing embodiments use integer linear programming. A linear program is constructed comprising a system of equations and constraints specified over a set of state variables representing the number of forms of each form-type. The formulation includes: 1) Function instance conservation constraint equations 2) Resource capacity constraints 3) An objective function The independent system variables are taken to be the number of each form to be utilized. The system variables are constrained to be non-negative integers. The count of instances of a given form type cannot be either fractional (a given netlist node is implemented exactly and entirely using one specific form in any valid morph state) or negative. Once the constraint equations and the objective function are specified, the ILP solver returns with the number of each form to be utilized, which optimizes the objective function and satisfies the constraints. Of course, it is possible that no solution exists, if for example, the number of form instances assigned to a region is so great that the forms cannot be packed in, or if there is inadequate morphability in any of the functions. If there is no solution, then the ILP solver returns a status indicating that no solution could be found. The function instance conservation constraint equations state that the result will have the same number of instances of each function type as were in the original configuration of the subset of the netlist participating in the morph. Stated another way, the intent of morphing is to select alternate forms implementing the same circuit function, so the action of the morpher on a set of nodes should preserve the number of instances implementing each function. Within a function, the distribution of nodes implemented in different forms can change, but the total number of nodes in all the forms implementing the function is the same in the output as in the input. Morphing per se does not change the Boolean algebraic structure of the form-level netlist. (Other optimization technologies unrelated to morphing do that, and use of morphing does not preclude use of the other technologies.) For example, suppose that the number of form instances implementing the NAND2 function is 5, apportioned on input as 3 form instances using form NAND2—1 and 2 using form NAND2—2, and that the number of form instances implementing a MUX4 function is 7, apportioned as 3 form instances using MUX4—1, 2 using MUX4—2 and 2 using MUX4—3. Further assume that the state variables x_0, x_1, x_2, x_3, x_4 represent the number of form instances of the forms NAND2—1, NAND2—2, MUX4—1, MUX4—2 and MUX4—3 respectively. Then the following two constraint equations would be among the set of function instance conservation equations: 1x—0+1x—1+0x—2+0x—3+0x—4+0x—5+ . . . =5 0x—0+0x—1+1x—2+1x—3+1x—4+0x—5+ . . . =7 The resource capacity constraints are inequalities that state that the resources utilized by a given form allocation may not exceed resources that are available. There is one respective constraint inequality for each resource in the structured ASIC architecture. In the respective inequality constraint for each resource, the coefficient of each state variable is the number of that resource consumed by the corresponding form. The right hand side is the capacity of that resource in the current region context. For example, consider a morphing problem for a structured ASIC architecture containing NAND2, NOR2 and INV resources (among others). There are INV_INV, INV_ND2 and INV_NR2 implementing an inverter function each using one of the INV, NAND2 and NOR2 resources respectively. There is a form XNOR2—1 implementing an XNOR2 function using three NAND2 resources and one NOR2 resource. There is a form XNOR2—2 implementing an XNOR2 function using two NAND2 and two NOR2 resources. In the current region there are 400 INV, 100 NAND2, and 150 NOR2 resources. Then the resource capacity constraints would include terms like these: 1x—0+1x—1+1x—2+0x—3+0x—4+ . . . <=400 0x—0+0x—1+0x—2+x—3+2x—4+ . . . <=100 0x—0+0x—1+0x—2+1x—3+2x—4+ . . . <=150 where x—0 represents the number of INV_INV forms, x_1 the number of INV_ND2 forms, x_2 the number of INV_NR2 forms, x_3 the number of XNOR2—1 forms and x_4 the number of XNOR2—2 forms. Some structured ASIC architectures have resources that can be reconfigured to switch between different primitive Boolean functions. For example, in some structured ASIC architectures, a mask reconfiguration might allow an abstract resource to be switched between implementing either a NAND2 function or a NOR2 function. Morphing support for such architectures can be accommodated in variations of the integer linear programming formulation by including combination constraint inequalities to constrain the sum of forms implemented using the reconfigurable resources to be no larger than the total possible. For example, posit a structured ASIC architecture such that within a given region there are 100 NAND2 resources, 100 NOR2 resources, and 100 NAND2/NOR2 combination resources. Label the NAND2 resource 0, the NOR2 resource 1, and the NAND2/NOR2 combination resource 2. Further, represent the footprint of form i onto resource j as R_ij and the supply of resource i as S_i. Then constraint inequalities would include terms like: R—00x—0+R—10x—1+R—20x—2+ . . . <=S—0+S—2 R—01x—0+R—11x—1+R—21x—2+ . . . <=S—1+S—2 (R—00+R—01)x—0+(R—10+R—11)x—1+(R—20+R—21)x—2+ . . . <=S—0+S—1+S—2 The above formulation enables exploration of solutions where the combination resources are allocated flexibly between either resource behavior, but simultaneously excludes solutions that oversubscribe the simple plus combinational resource supply. Morphing Techniques: Objective Function In some usage scenarios an ILP solver package allows a user to specify an objective function of the system variables to optimize, as there may be many solution vectors that satisfy the various constraint equations. Without the ILP solver, the best choice of the many available solutions may not be apparent. An objective function is a function specified as a linear combination of the system state variables. The ILP solver then returns the best solution found, as measured by the objective function. That is, of the range of solutions satisfying the constraint equations, the chosen solution will be the one that maximizes the objective function. F=sum—iO—ix—i where i ranges over the number of variables in the system, x_i is the ith system variable, and O_i is the coefficient to be applied to the ith system variable. More specifically, 0<=i<N_forms, where N_forms is the number of forms in the library and x_i is the number of the corresponding form in the solution. One particularly useful objective function to use is a so-called “form efficiency”. The form efficiency measures efficiency of implementation of each form in terms of respective Boolean computational work that the respective form performs divided by a similar measure of Boolean computational work that could be performed using resources consumed implementing the respective form. In some usage scenarios the efficiency of a form varies between 0 and 1, although the normalization is immaterial to the optimization problem. Other embodiments use optimization objectives other than form efficiency. Morphing Techniques Software Implementation An illustrative usage scenario of form morphing follows. The structured ASIC logic array is divided into regions, and a global placer apportions circuit nodes to the various regions. A morphing controller function then cycles through the regions, identifies respective resource capacities and respective netlist nodes contained within each region, and calls the morpher, passing in the resource capacities, nodes (with the current form assignments), possibly a choice of objective function, and possibly also an indication of the priority of the nodes, and possibly also a function for evaluating the suitability of any given form for any given node. The morpher evaluates the number of nodes implementing each function present in the set of participating nodes as respective function instance counts according to a library. The function instance counts, along with the resource capacities, are used to formulate the system of equations and inequality constraints, as described above. The coefficients of the objective function are supplied, and the ILP solver is invoked. If a solution is found, then the resulting quota of forms (i.e., a particular distribution of form types determined by the ILP solver) is apportioned to the participating nodes in some manner. One illustrative example technique is to pass through the nodes, and test to see if the full quota of the respective current form has been reached yet. If not, take the form, and move to the next node. If so, morph this node to the next not-yet-exceeded form type within its function group. An additional illustrative, but not limiting, example technique for apportioning forms is as follows. Order input nodes according to a priority indicator supplied by a caller. Assign each node to a “preferred” form type (for example, whatever form type the node was assigned by the tool (e.g. a timing-driven synthesis tool) that produced the original form-level structural netlist), if available. If unavailable, then assign to one of the other forms in the function group (e.g. a lower or higher drive strength logically equivalent form). An additional illustrative, but not limiting, example technique for apportioning forms is as follows. When a preferred form quota for a node is exhausted, then instead of assigning the node, push the node back onto a queue for subsequent consideration. After all nodes have been visited once, and either assigned or queued, the queue of blocked nodes is reprocessed. Each node of the queue is assigned any of the available alternate forms in a corresponding function group. An additional illustrative, but not limiting, example technique for apportioning forms is as follows. Use the supplied evaluator function to evaluate the form-ranking on a per node basis, thus enabling factors outside the scope of the ILP formulation to affect determination of the apportionment of the quota of forms developed by the ILP based morpher. In other words, the morpher is responsible for determining a fitting set of form quotas, but other systems or techniques are responsible for apportioning available forms based on more detailed per-node considerations. For example, timing critical path nodes may receive special treatment. Path-Based Timing Force Embodiments Timing Driven Force Computation Timing driven SDI-based placement uses timing forces to systematically influence and optimize timing performance of a placement of elements such as in a design for an integrated circuit. In some embodiments timing characteristics of a circuit are modeled in a timing graph from a time-evolving placement and timing forces are applied by a placement engine as a feedback mechanism. A timing graph may be a Directed Acyclic Graph (DAG) that has nodes that represent pins of a circuit netlist (e.g. provided by a user of the engine and an associated design flow) and edges that represents timing arcs within a library cell and interconnections of the netlist. The timing forces are applied in conjunction with net connectivity forces and spreading forces to improve placement quality as measured by circuit timing performance and routability. One approach for modeling timing force for use in a timing driven SDI-based placement flow is known as a Path-Based Timing Force (PBTF) model. PBTF heuristics apply proportionate timing forces on each node (or element) of various critical paths, so that when spreading forces are applied according to each critical path, the elements are pushed away or held together based on respective contribution to overall circuit performance. In various embodiments of a PBTF system, any combination of factors may be used in determining timing force on an element. The factors include: Critical Paths influence Factor (CPF); Drive Resistance Factor (DRF); and Stage Delay Factor (SDF). Critical Paths influence Factor (CPF) CPF models contributions of a node to all or any portion of critical paths of a circuit. In various embodiments of a PBTF model usage scenario a timing driven placement seeks to improve any combination of the Worst Negative Slack (WNS) and the Total Negative Slack (TNS) of the circuit. Contributions of a node to the critical paths of the circuit are accounted for to improve the TNS of the circuit. FIG. 17A illustrates an example circuit with a plurality of critical paths. The critical paths include: Path 1, P1={N0, N2, N3}; Path 2, P2={N0, N2, N4}; Path 3, P3={N1, N2, N3}; and Path 4, P4={N1, N2, N4}. Node N2 is common to all the paths, while all the other nodes are present in two of the four paths. Thus in some embodiments a CPF computation for node N2 will be higher than CPF computations for the other nodes. In some usage scenarios all critical paths of the circuit are explicitly enumerated. In some usage scenarios not all critical paths of the circuit are explicitly enumerated, since there are an exponential number of timing paths, and CPF modeling builds a heuristic based CPF model for each node of a timing graph. A CPF score is computed by topologically traversing nodes of the timing graph in forward Depth-First-Search (DFS) order and reverse DFS order. Two scores are computed for each node: transitive FanIn CPF (FICPF) and transitive FanOut CPF (FOCPF). The respective CPF score of each node is the product of FICPF and FOCPF. FICPF is computed during the forward DFS traversal as a sum of FICPFs of all immediate predecessor nodes of a node if the respective predecessor node is a critical node: node—FICPF=Sum (critical fanin—FICPF). Similarly, during reverse DFS traversal, an FOCPF of each timing graph node is computed as a sum of FOCPFs of all immediate successor nodes if the respective successor node is a critical node: node—FOCPF=Sum (critical fanout—FOCPF). Then each node CPF score is computed by multiplying the respective FICPF and the respective FOCPF: node CPF score=node—FICPFnode—FOCPF. CPF is then normalized by dividing the CPF score by the maximum CPF of the timing graph: normalized_node—CPF=(node CPF score)/Max (node CPF score). (Eq. 1) FIG. 17B illustrates example computations relating to an embodiment of CPF scoring. Tuples in the figure represent (FICPF, FOCPF) pairs, and underlined numbers represent slack on each node. Drive Resistance Factor (DRF) DRF models contributions of each node on a critical path based on drive resistances of node drivers. In some usage scenarios drive resistance of a node driver is a significant delay contributor to overall path timing. In one modeling equation that considers first-order effects, stage delay of a gate is computed as follows. gate delay=Ti+RdCl; (Eq. 2) where Ti: intrinsic delay of the gate; Rd: drive resistance of the gate; and Cl=interconnect capacitance+pin capacitances (i.e. total capacitive load on the output of a gate). In some embodiments pin capacitances are fixed (or unchanged) during timing driven placement, and thus the timing driven force model is directed to influence interconnect capacitance. According to Eq. 2, improving the product of drive resistance and total output load tends to improve stage delay of a critical path node. The product may be improved by arranging for drivers with relatively higher driver resistance (Rd) to drive relatively lower capacitive loads, resulting in drivers having relatively low driver resistance (such as some drivers on critical paths) driving higher capacitive loads (such as relatively long wires). In some usage scenarios an incremental delay cost associated with driving a “stretched” wire with a strong driver is less than with a weak driver. FIG. 18 illustrates an embodiment of a cascade of buffers of increasing drive strength (i.e. decreasing drive resistance). Five levels of buffer are illustrated with relative drive strengths of x1, x2, x4, x8, and x16 (i.e. each stage provides a factor of two more drive than the preceding stage). Nodes driven by the buffers are illustrated respectively as N1, N2, N3, N4, and N5. Overall delay of the path illustrated in FIG. 18 is minimized if all the logic levels have equal delay. Ignoring intrinsic gate delays, the delay for each element of the path is balanced by equalizing respective products of RdCl. Since Rd(x1)>Rd(x2)>Rd(x4)>Rd(x8)>Rd(x16) the PBTF system attempts to maintain the following relative capacitive loading ordering: Cl(x1)<Cl(x2)<Cl(x4)<Cl(x8)<Cl(x16). Since Cl is directly proportional to wire length, and higher timing force tends to result in shorter wire lengths, timing forces are made proportionate to drive resistance. Relative DRF is normalized by dividing a respective DRF weight of each node by the DRF weight of the node having the least drive resistance: node DRF=(node—DRF_weight)/Min(node—DRF_weights of all nodes) (Eq. 3) where node_DRF_weight=Drive resistance of the driver gate for the node under consideration. Stage Delay Factor (SDF) Stage Delay Factor (SDF) models stage delay contributions of each driver on a critical net (or net on a critical path) and accounts for the maximum path length of each load pin on the critical net. The SDF combines stage delay and maximum path length factors to assign an SDF force component to each load pin. An SDF force is proportional to the maximum path length associated with the load pin. The SDF is computed as follows: SDF Factor=dcoeffexp(lpwpd/min_cycle−1) (Eq. 4) where lpwpd=load pin: worst path delay; min_cycle=clock period delay of the clock controlling the net; and dcoeff=driver stage delay coefficient. The dcoeff is computed as follows: dcoeff=(dgsd/dpwpd)path_levels where dgsd=stage delay of the driver gate; dpwpd=driver pin: worst path delay; and path_levels=number of logic levels in the path. Load pin: worst path delay is computed as follows: lpwpd=AT(load_pin)+clock_cycle−RT(load_pin) Driver pin: worst path delay is computed as follows: dpwpd=AT(driver_pin)+clock_cycle−RT(driver_pin) where AT: Arrival time; and RT: Required time. FIG. 19 illustrates example computations relating to an embodiment of SDF calculation. In the figure: lpwpd(L1)=12; lpwpd(L2)=11; lpwpd(L3)=7; dpwpd=12; clock_cycle=10; dgsd=1; SDF(L1)=dcoeffexp(12/10−1); SDF(L2)=dcoffexp(11/10−1); and SDF(L3)=0. A stage delay of a driver gate is the sum of the driver gate delay and the interconnect wire delay that is driven by the driver. The driver gate stage delay discriminates the load based on criticality by factoring in the worst path delay of the load pin. If a load pin is part of a slower critical path, then a higher force coefficient is associated with the load pin than a load pin that is part of a relatively faster critical path. The exponential term provides discrimination between two critical paths of unequal lengths. For example, if a first critical path is missing by a target by 2 ns while a second critical path is missing the target by 1 ns, then a higher multiplying factor is associated with the first path (compared to the second path) due to the exponential term. Thus critical paths with worse violations are weighted more. Bounding Box Based Pin Force In some embodiments timing forces are not applied in association with non-critical loads that fanout from a critical driver, thus enabling some relaxation of some (non-critical) loads so that more critical load pins of a net may be pulled closer to the driver. In some embodiments timing forces are applied for non-critical pins, if the pins form any portion of a bounding box of a critical net. A bounding box is defined as a rectangle around all the pins of a net. If a non-critical pin is on the edge of the bounding box, then an attractive force is applied to the load pin, thus in some cases reducing total interconnect capacitance (or at least preventing an increase in capacitance). Path Based Timing Force A first variant of a path-based-timing-force is: PBTF1=CPFRDF+SDF where CPF: Normalized_node_CPF (as in Eq. 1); RDF: Normalized_node_DRF (as in Eq. 3); and SDF: Normalized_node_sdf (as in Eq. 4). A second variant of a path-based-timing-force is: PBTF2=CPFRDF+RSF where CPF: Normalized_node_CPF (as in Eq. 1); RDF: Normalized_node_DRF (as in Eq. 3); RSF: Normalized_node_RSF; and Normalized_node_RSF=node_slack/Minimum slack of timing graph. Relative-Slack-Based Timing Force Embodiments The SDI technique of optimizing chip placement relies on a variety of forces affecting nodes in a dynamical fashion, integrated forward in time. These forces are chosen to simultaneously improve metrics that constitute a desirable placement, including routability and timing performance, while achieving a physically realizable (legal) configuration. An approach to timing-driven placement is described in what are referred to herein as “relative slack” embodiments. Relative slack embodiments provide improved results (in both absolute performance as well as numerical behavior) in some usage scenarios. In a first illustrative, but not limiting, class of relative slack embodiments forces affecting pins on a critical path (as well as pins on shared nets) are increased or decreased in an incremental fashion, rather than being directly calculated by a timing kernel. In the first class of embodiments, pin-to-pin forces (so-called timing-based or timing-driven forces) affecting nets (e.g. timing-critical nets) are governed by a force law equation having a linear increase with distance (Hooke's law) and a driver-to-load connectivity model. Other classes of relative slack embodiments may employ any arbitrary functional variation with distance, as well as alternate connectivity models. A set of weights governing the timing-based force attraction are periodically updated, and adjusted in to result in successively better relative node configurations with regard to overall circuit performance. Relative slack embodiments assume existence of a timing kernel that is called during an SDI run to provide relative slack data used in updating the timing driven forces. Specific details of the timing kernel implementation are irrelevant since only r data from a timing graph and propagated pin slacks analysis are needed. The frequency of update can be controlled in a variety of ways: e.g. at regular timestep intervals, in response to a triggering event (dynamical or otherwise), or in response to external (user, script, or graphical) input. Each update provides a “snapshot” of the critical path analysis for every net and pin in the system at that moment of time. The relative slack as calculated for each pin, as well as the position of connected pins (to handle boundary box effects as noted below), results in an adjustment in the “timing weight” associated with each pin. The timing weight is then used as a multiplier in the force law equation governing pin-to-pin attraction. Pins that need to be moved closer together to satisfy timing constraints tend to have weights increased (modulo possible normalization, noted below), in some usage scenarios in a manner varying with the amount of slack available. That is, the less slack (or more negative slack), the greater the positive adjustment to the attraction. Pins that have excess slack tend to have weights decreased. The reduction in weight on pins that have become “over-tightened” creates additional room for relaxation towards an optimal timing state. At least some relative slack embodiments seek to improve timing of nets that do not meet target slack through “bounding box” (or bbox) contraction. Because increases to total net length result in increased capacitance, the associated timing can be negatively impacted by long distance nets—even if the associated load pin is not on the critical path. The long distance net effect may be especially pronounced on large designs. The bounding box contraction considers a range of distances from the net bounding box, to help ensure that the bounding box is continuously contracted (otherwise pins on the bounding box may merely trade places). The incremental approach to change in timing forces provides a quiet and consistent approach to timing closure during the course of an SDI run. In some cases where the timing constraints have been unrealistically set, it may be necessary to introduce a maximum to the total timing forces exerted by the system (for example, adding an upper limit to the ratio of timing net energy to total net energy, through a normalization term). A wide variety of other tunable controls are possible, including but not limited to: baseline relative tightening factor (typically small compared to unity); target min pin slack (typically zero); positive pin slack where relaxation may occur; minimum change in pin slack to consider it in an “improving state”; distance between driver and load pins when no further tightening occurs; distance from net bounding box where tightening starts to occur; min bounding box size when no further “bbox” tightening occurs; and relative strength of bounding box vs. critical path tightening terms. Illustrative Detailed Relative Slack Procedure An illustrative, but not limiting, relative slack procedural flow is as follows. First, in at least some embodiments, a pre-processing phase is performed (in other embodiments this might occur as a post-processing phase), where timing weight adjustment criteria or timing weights themselves are adjusted to control properties of distribution of the timing weights as a whole. The pre-processing permits balancing resulting timing-driven forces with other effects in the system, such as connectivity forces (affecting routability) and expansion fields (affecting routability as well as utilization). Second, update a timing graph using a Timing Kernel (TK). Using the updated timing graph, for every pin on every timing critical net, the slack associated with the respective pin is calculated (See 20,200 of FIG. 20A). Third, iterate over all timing critical nets 20,300, and all load pins on the nets 20,400. Fourth, for each load pin on a respective timing critical net, calculate a respective pin timing weight adjustment (20,500 of FIG. 20A and the entirety of FIG. 20B): 1. Calculate worst slack on the respective net and find bounding box pins. The pins are taken from some region around the bounding box of the net (the size of which is determined by performance tuning, scaling by system size). 2. Determine if the respective driver pin needs to be factored into the bbox calculation. That is, when the driver pin determines the bounding box position, increasing the attraction to nearby pins that are farther from the bbox may be counterproductive. The attraction to pins on the far side of the bbox is likely more influential in decreasing the overall capacitance. FIG. 21A illustrates a driver D in the interior of a net bounding box region determined by loads L1, L2, and L4. FIG. 21B illustrates a driver D to one side of a net bounding box region determined by the driver and loads L1, L2, and L4. 2a. To focus on connections of loads to the driver, the effect of a driver on a bbox is indirectly applied to the loads themselves, through a multiplication factor on any tightening term. 3. For each pin, modify a respective timing weight as needed (see FIG. 20B). 4. For pins that meet target slack (Yes-path from 21,210 to 21,250): 4a. If the slack for the associated is net is negative (No-path from 21,250 to 21,270), then to continue to make positive progress bounding box effects are considered. By taking into account a range of distances from the bbox, rather than a hard boundary, sloshing (oscillations) as pins move onto or off of the bbox is reduced. If (see decision 21,270) a net is near or on the bounding box of a critical net, then determine how much to tighten up the connection. If (see decision 21,280) a load pin is within a specified (small) distance from the driver, do nothing (End 21,285), as further tightening of the connection is counterproductive (e.g. result in increased oscillatory motion between the load and driver). Otherwise, strategies for tightening (increase weight 21,290) include: if the bbox size is sufficiently small, then do nothing; if a pin is on bbox, then tighten at full strength; if a pin is farther than a specified distance from the bbox, then do nothing; and otherwise (in between), then tighten from O-Ix full strength, depending linearly on distance. 4b. If the pin was not tightened (Yes-path from 21,250 to 21,260), then the pin may be considered as a candidate for relaxation (21,260). By allowing connections to either strengthen or weaken, the ability of the system to evolve and relax to an optimal configuration is improved. 4b1. The amount of relaxation allowed for the pin connection is dependent on the worst slack for the net. If the pin has positive slack, but the worst case slack on the net is negative, then the amount of relaxation allowed is reduced. Recall that the pin was not tightened, so little is added to the total capacitance on the net. 4b2. Further, the relaxation is subject to a reasonable upper bound. Otherwise the weights may drop from substantial to nonexistent in a single pass. 4b3. In both of these cases, by moderating the relaxation allowed during one update cycle, we help prevent sudden movement away from what was potentially a fairly optimal solution. This is manifested as increased sloshing in the overall timing performance. 5. For pins having negative slack (No-path from 21,210 to 21,220): 5a. If (see decision 21,220) slack of a constrained pin is improving according to a specified criterion, then let the pin continue to evolve without change (Yes-path to End 21,225). 5b. If (see decision 21,230) the driver and load are within a critical distance, then no tightening is performed (Yes-path to End 21,235). Otherwise tighten the connection (increase weight 21,240), in a manner varying with the ratio of the slack on the pin and the worst negative slack, thus pins most affecting the critical path are likely affected the most. Timing Driven Buffering Embodiments Timing Driven Buffering Overview Timing driven buffering and resizing for integrated circuit designs, e.g. structured array architectures, provides increased performance, reduced cost, or both. Nets having high capacitance and/or fanout and timing critical nets are preferentially processed to reduce maximum delay and/or transition time, enabling allocation of limited structured array resources to more important nets. Timing driven buffering is performed to generate trees of buffers. Timing driven sizing is performed to upsize selected elements. During the buffering Steiner tree routes are segmented and various buffering options are evaluated for each segment according to buffer cost, required time, and lumped capacitance. The options are sorted and partitioned according to the sort. Computational efficiency is improved by eliminating all but a topmost portion of each partition. Options are further evaluated according to performance including timing and routing costs. Displacement coefficients of macros are computed during the sizing to evaluate desirability of reallocating resources implementing less critical macros to more critical macros. A plurality of low-level implementations of each macro are evaluated and compared. Logic replication and tunneling may be performed according to timing improvements and routing costs. Hold time fixes may be implemented by delaying clocks and/or replacing a fast FlipFlop (FF) with a slower element. In some embodiments of design flows relating to array architecture based integrated circuits (e.g. structured arrays or other similar Application Specific Integrated Circuit (ASIC) implementations), timing driven buffering is used to “reconstruct” or “re-synthesize” nets having high capacitive loads or having high fanouts. In some usage scenarios modifying the nets reduces a maximum capacitive load driven by any buffer or driver, or group of elements. In some usage scenarios the modifying reduces a maximum fanout associated with any net or group of nets. In some embodiments a high capacitive load may be driven by a dedicated buffer, or a dedicated tree of buffers. In various embodiments any combination of maximum transition time, maximum rise/fall time, and maximum delay are minimized when performing timing driven buffering. In some embodiments the timing driving buffering is according to fixed resources available in various structured array architectures. In some embodiments the timing driven buffering is iterative (e.g. to achieve timing closure). In some embodiments the timing driven buffering accounts for any combination of local and global congestion. In some embodiments the timing driven buffering includes morphing non-buffer resources and allocating the morphed resources as buffers. In some embodiments of array architecture design flows, timing driven gate resizing is used to improve performance of various combinations of highly capacitive and high fanout nets. Logic gates are upsized (i.e. replaced with a gate having an equivalent logic function but greater drive strength) as necessary to reduce maximum delay and/or transition times. In some embodiments the upsizing is via so-called “form replacement” or replacing a form level macro with an alternate form level macro (such as substituting a gate with a higher drive strength for a gate with a lower drive strength). In some embodiments timing driven gate resizing is constrained according to fixed resources available in various structured array architectures. In some embodiments a plurality of resources are simultaneously “swapped” (i.e. deallocated from a first use and reallocated to a second use) to improve critical path timing. In some embodiments the timing driven gate resizing includes morphing non-buffer resources and allocating the morphed resources as “upsized” gates or buffers. In various embodiments of timing driven buffering and resizing for structured array architectures, timing driven hold time fixes are implemented by any combination of morphing, delaying clock signals, and buffering. In some embodiments any combination of logic replication and tunneling are used to improve circuit performance of designs implemented according to a structure array fabric. FIGS. 22A and 22B illustrate, respectively, an example circuit excerpt before and after processing according to an embodiment of timing driven buffering and resizing for an array architecture. FIG. 22A illustrates critical load C2 driven by buffer b2 that is driven by buffer b1 that is in turn coupled to Driver. Thus there are two buffers between the driver and the critical load. Non-critical loads NC1 and NC2 are also driven by buffer b2. Loads on a critical path from Driver to C2 include c0 driven by Driver and C1 driven by buffer b1. FIG. 22B illustrates a result of timing driven buffering and resizing, as applied to the topology of FIG. 22A, where critical load C2 is driven from new/modified buffer b1′ that is directly coupled to Driver. Thus there is only one buffer between the driver and the critical load, providing enhanced arrival time for the critical load compared to the topology of FIG. 22A. Structured ASIC Timing Closure FIG. 23 illustrates a flow diagram of an integrated circuit design flow including an embodiment of processing in accordance with an embodiment of timing driven buffering and resizing for an array architecture, e.g. a structured ASIC. Timing Driven Buffering FIG. 24A illustrates a top-level view of an embodiment of timing driven buffering and resizing for an array architecture. In some usage scenarios timing driven buffering and resizing serves to reduce delays of critical path elements and decrease transition times associated with drivers (or nets or both). Routing-aware buffering is used to reduce maximum congestion in otherwise heavily congested regions. In some embodiments an initial buffering phase is performed ignoring timing-driven constraints, while in other embodiments the initial buffering accounts for timing-driven constraints. According to various implementations timing-driven buffering and resizing includes any combination of net prioritization, global Steiner tree routing, evaluating multiple route trees, computing buffering options, pruning, and determining and selecting a solution. In some embodiments a buffering subsystem processes nets individually, prioritizing the nets according to timing criticality, enabling preferential treatment for more critical nets. The preferential treatment is according to any combination of buffering resources, wiring resources, and routing congestion (measured according to a metric). In structured array usage scenarios, buffer resources are finite and several nets may be simultaneously competing for the same resources. Ordering nets and processing the most critical nets (or the nets having the highest negative slack) first provides the more critical nets with access to the buffer resources first. In addition, as more nets are processed, the most critical of the remaining nets have access to wire routing regions most beneficial to routing the remaining nets through. Less critical nets are relegated to more meandering routes to meet region congestion constraints. In some embodiments the buffering subsystem initially constructs global Steiner tree routes for all nets to estimate heavily congested regions. Routing and/or congestion hotspots that should be avoided while buffering (at least for non-critical nets) are identified. In some embodiments the buffering subsystem initially builds multiple route trees for each driver that couple the respective driver to all loads of the driver. The route trees are heuristic based, and the heuristics include prioritizing critical loads differently than non-critical loads and operating with an awareness of the previously identified hotspots. The route tree building includes any combination of shortest path weight and net spanning factor techniques, enabling results having different topologies. In one embodiment of one of the route tree heuristics, loads are first grouped into multiple partitions based on load (or pin) criticality. More critical loads are prioritized for Steiner tree route construction first. Then less critical loads are processed, enabling the more critical loads to have a more direct route from driver to load. In addition, the more critical loads are presented with higher shortest path weight, thus reducing branching of the route tree from the more critical loads to the less critical loads. In some implementations a Steiner tree based route is decomposed into several segments, such as according to a global cell granularity used when constructing the Steiner tree based route. A dynamic programming technique is used to compute a buffer solution for each of the route trees. The dynamic technique includes maintaining several solutions for each segment to be considered for use to implement a sub-tree of the respective route tree. The respective route tree is processed bottom-up, i.e. all of the load terminals of the tree are visited before the driver. Buffering options at a segment are computed by combining solutions of all predecessor sub-trees with a current solution. FIG. 25A illustrates a portion of a route tree having several branches decomposed into segments according to processing by an embodiment of timing driven buffering. Child options are a function of downstream options. For example: Options at S0=Product(Options at S1, Options at S2). FIG. 25B illustrates several segment options for segment S0 of FIG. 25A. The options include no buffering (Opt1), a buffer before the branch to segment S2 (Opt2), a buffer on segment S1 (after the branch as Opt3), a buffer on segment S2 (after the branch as Opt4), and two buffers after the branch, one on each of segments S1 and S2 (Opt5). If a segment currently being processed is a branch point, then the current segment has multiple sub-trees below it, and each of the sub-trees contains an array of options. The options are merged by performing a cross product of option sets. After computing the cross product, each feasible solution for the sub-tree is combined with a buffering solution for the current segment. Multiple segment options are computed for each segment. The number of options produced is proportional to the number of buffer types (or buffer electrical characteristics) available according to technology associated with an integrated circuit design (such as a standard cell library). In some implementations various options are computed for each segment, including a non-buffered option, a high-drive strength buffer option, and a low-drive strength buffer option. For each option, several parameters are determined, including Buffer Cost (BC), Required Time (RT), and lumped Capacitive Load (CL). The parameters are subsequently used to determine option cost and feasibility. BC measures cost according to the buffering solution for the entire sub-tree “underneath” the segment being evaluated. RT measures expected required time for a signal at the input of the segment. CL measures cumulative capacitive load of the segment and all associated child segments. Pruning techniques are used to limit computation, maintaining selected options for each route segment. The selected options chosen are those most likely to result in a “good” solution according to the root of the route tree. A first pruning technique includes deleting any infeasible solutions, such as a buffering option that has accumulated capacitance exceeding the maximum drive capability according to available buffers. A second pruning technique removes redundant options. An option having higher BC, smaller RT, and higher BC compared to an existing option is considered redundant. A third pruning technique includes trimming the number of options according to an upper bound. In some embodiments the upper bound is variable, while in other embodiments the upper bound is predetermined (at a value such as 10, 20, 50, or 100). In some implementations the options are sorted in order of RT (highest RT first). In some embodiments a contiguous portion of the top of the sorted options is retained, the portion being equal in number to the upper bound (i.e. the “best” options are kept). In some embodiments the sorted options are partitioned into four quarters, and a number of options are preserved from each quarter. In some embodiments the number is chosen to be one-fourth of the upper bound. In some usage scenarios the preserving according to partitions enables discovery of solutions that appear locally inferior, but when combined with parent segments appear superior. In some embodiments determining and selecting a buffering solution includes evaluating options according to performance (such as arrival time) and (estimated) routing congestion. A disproportionately higher weighting is applied to timing cost when evaluating a critical net. A buffering solution having lower hotspot (i.e. congestion) cost is preferentially chosen for non-critical nets. Timing Driven Sizing FIG. 24B illustrates a detail view of selected details of an embodiment of timing driven resizing for an array architecture. Timing-driven form sizing (or resizing) selects alternate forms to improve any combination of drive capability and stage delay, for example by replacing a lower drive strength gate with a relatively higher drive strength gate. In some usage scenarios macro or form sizing is preferred over buffering when cost of upsizing a driver is less than buffering a net. In some structured ASIC usage scenarios buffer sites are predetermined according to block tiles, and thus the fixed locations of buffer sites may result in relatively high intrinsic buffer cost or associated congestion cost. In some situations there may be no available sites (or slots) near a macro targeted for resizing. In some embodiments a form-sizing subsystem attempts to discover nearby sites by (re)implementing the macro using a different set of primitives. According to various embodiments the primitives correspond to standard cells, structured array tile elements, or other similar low-level resources. In some implementations the form-sizing subsystem is enabled to “displace” (or “move”) selected forms (such as forms on non-critical paths) that are initially near the macro that is to be resized. In structured array integrated circuit designs, strictly speaking the forms are not moved, but instead fixed-location sites are deallocated in one area and reallocated in another area. A Displacement Coefficient (DC) of a macro is computed as follows: DC of macro=Sum (DC of each morphable form within the macro); and DC of a morphable form=Product(primitive densities of all the primitives within the morphable form). The DC is a conceptual measurement of “placeability” or ease of placement of an element when the element is currently unplaced. A macro is more placeable if it may be implemented with more morphable alternatives. A morphable alternative is more placeable if the primitives of the morphable alternative are placeable (or relatively more placeable), such as when there are available (or unused) sites for the primitives. The primitive densities relating to the DCs of morphable forms are computed as follows. A site density grid is constructed that is a two-dimensional matrix of grid resource usage. For each element of the density grid, a number of available resources and used resources are computed for each resource type. Relatively sharp density gradients are smoothed by accumulating density from eight neighboring grid elements to a respective grid element. Thus the computed density at each grid element is an average density at the element in conjunction with eight nearest neighboring elements. The site density grid values are then used to determine the DCs of the morphable forms. The DC of a morphable form is computed by looking up the density of each of the primitives of the morphable form, within the site density grid and according to respective primitive types. The morphable form DC computation continues by multiplying the look up results (i.e. primitive densities) together. If a particular resource or resource type is depleted (or nearly depleted) within the grid, then the morphable form DC is zero (or nearly zero). Thus the resource depletion results in the placeability of the morphable form being low. Resizing a macro includes selecting a form from a plurality of implementation choices. Each of the choices is speculatively selected and evaluated with respect to the macro being resized. A timing score is computed that is equal to arrival time at an output of the macro assuming the macro is implemented with the speculatively selected form. If the timing score is poorer than previously saved possible implementation choices, then the current choice is rejected. If the timing score is better, and the drive strength of the speculatively selected form is sufficient to drive the capacitive load at the output, then the speculatively selected form is saved as a possible implementation choice. In some embodiments placing a macro after determining an implementation according to one or more morphable forms proceeds as follows. New coordinates of the (now form level) macro are computed based on all of the connections of the form level macro. The coordinates of drivers of nets connected to all of the input pins of the form level macro as well as associated net fanouts are used to compute the new coordinates. In some embodiments a form placing sub-system performs an attempted placement of each of the possible implementation choices determined during the resizing of the macro. The underlying morphable forms are already prioritized based on the respective timing scores, and the attempted placements are performed in priority order (i.e. morphable forms resulting in better arrival times are tried first). Each primitive of each respective morphable form is placed individually as follows. A site locator (or slot locator) searches all possible sites around a given coordinate within a certain window size. If a respective site is unoccupied, then the unoccupied site is assigned to the primitive. If the respective site is occupied, then the DC of the parent form level macro of the occupied site is looked up. If the DC is below a threshold value, then the parent macro is left untouched and other sites are tried. If the DC is above the threshold, then the parent macro is scheduled to move from the site (i.e. the primitive in the site will be placed elsewhere) and the primitive is assigned to the site. The parent macro that is scheduled to move is queued to be visited later based on criticality of the parent macro. Timing Driven Logic Replication and Tunneling In some embodiments a driver node is logically replicated for nets having high capacitive loading or high fanout. The replication is performed selectively according to evaluations of timing improvements and routing costs. In some embodiments tunneling is performed to move the driver closer to a cluster of loads. In some embodiments the tunneling is performed after evaluating the timing improvements and routing costs. FIG. 26 illustrates example results of an embodiment of logic replication and tunneling for an array architecture. The example illustrates a single FF driving three clusters of load (C1, C2 and C3). After replication and tunneling (shown in the lower portion of the figure), the FF is replicated as FF1, FF2, and FF3. Each of the replicated FFs is then placed near the respective cluster driven by the FF. Timing Driven Hold Time Fixes In some embodiments timing driven hold time fixes proceed as follows. Excess setup time (or slack setup time) is determined for each launch FF that is a root of a hold time violation. If there is excess setup time, then in some embodiments the clock signal feeding the launch FF is delayed. In some implementations the delay is via addition of a dummy load. In other embodiments a hold time violation is addressed by morphing the launch FF to a slower FF. In some implementations the morphing is via swapping the (original) launch FF with an unused (or available) slower FF. Density Enhancement Embodiments Node density in various SDI embodiments is influenced by a variety of effects, including netlist connectivity, circuit performance, and expansion fields. The former two exert an attractive force between nodes that depends upon netlist topology considerations or critical path analysis. For brevity these are referred to as “connectivity forces”. Without the presence of expansion fields, the connectivity forces tend to draw together nodes into a highly clumped configuration that may exceed local slot resource supply. Spreading of nodes by the expansion fields then serves a twofold purpose: (a) provide solutions to slot assignment over some suitably chosen sub-discretization of a die, and (b) enhance routability, since localized clumping of nodes implies greater local demand for routing resources. In a chip floorplan that is free of obstructions, very strong expansion fields result in a node distribution that is almost perfectly uniform. However this situation may not be desirable, since some amount of clumping may be beneficial. Once the node distribution reaches the point of routability, further increases to the expansion field strength may only worsen the routing problem by forcing nodes further apart than is optimal, seen by examining cutscores or circuit performance as a function of expansion field strength. Further, the demand for routing resources may exceed supply only in very localized regions, while the bulk of the node distribution presents a tractable routing problem. The localized regions may occur due to netlist (topological) or floorplan effects. Increasing the expansion field strength to compensate for the “lumpiness” of the node distribution in selected regions affects the distribution as a whole, and in some usage scenarios may be suboptimal. In cases where the floorplan contains obstructions, the supply of routing resources can be a complex function of position on the die, and here a global approach can fail to have the desired effect entirely. The illustrative but not limiting density-driven approaches presented here for addressing the problem of routing congestion in SDI can be categorized as follows: 1. Region Based a. By factor b. By function 2. Steiner Cuts Based a. Relative b. Absolute (i.e. supply vs demand) In the illustrative density enhancement embodiments, the density enhancement is inserted between the “fold” and “filtering” phases of node density computation. The flow 27,100 for density modification is illustrated in FIG. 27. Note effects introduced by procedures 27,100b, 27,100c, and 27,100d are completely independent of each other and can therefore be applied in any combination. In procedure 27,100a, the normalization factor is typically taken as the average density, not counting that in excluded regions. In procedure 27,100b, for each defined region that possesses a density scaling factor, the density is multiplied by the associated factor at each density field gridpoint contained within the region. Note this technique is essentially the same as increasing the effective mass for each node contained therein. Given a statistically uniform node distribution to start with, the scale factor density enhancement tends to drive nodes out of the specified region, ultimately resulting in a node density on the order of (average density)/(scale factor) there, edge effects notwithstanding. Any number of such regions and scale factors can be defined. Regions may overlap if so desired. In procedure 27,100c, for each defined region that possesses a density enhancement function, the associated spatial variation multiplied by the normalization factor is added to the existing density. The spatial variation is evaluated at each density field gridpoint contained within the region. In some embodiments an arbitrary functional variation is supported by expressing the function in Tcl (Tool Command Language) and using an embedded Tcl interpreter to return the result of the given expression at each gridpoint. The functional variation enhancement may be well suited for the case where the node density becomes very rarefied, e.g. in small channels between obstructions. In rareified density situations, the scale factor approach becomes less effective for pushing nodes out of the region, since there are fewer nodes to “push against”. The functional variation serves essentially as a background density, only depending on the existing node density through the normalization factor (which is global). As in procedure 27,100b, there is no limit to the number of regions and functions that can be defined, and regions may overlap if desired. In procedure 27,100d, a Steiner-cuts congestion density enhancement term is added. At this point in the flow, for this density enhancement embodiment, a congestion enhancement value at each gridpoint is available (described in detail below). Adding the congestion enhancement term (times a suitable normalization factor, e.g. the average density) for each gridpoint gives a final result. The flow 28,200 used to determine the Steiner-cuts congestion term on the SDI grid in the density enhancement embodiment is given in FIG. 28. In procedure 28,200a, a so-called “congestion array” is generated that is a measure of routing congestion output, taken from a Steiner cuts measurement. Since the calculation of routing congestion may be computationally expensive, the congestion array need only be calculated initially and at specified intervals as a run proceeds. An intermediate grid is used to assert the independence of the congestion array from the particular form of the routing congestion diagnostic, as well as from the SDI grid resolution. The procedures used to create the congestion array are illustrated in FIG. 29. In procedure 28,200b, the congestion array is run-length averaged according to a specified relaxation factor. This helps prevent sudden “shock” to the system (which can cause unphysical fluctuations) every time the congestion array is recalculated, by phasing the change in gradually. The relaxation parameter is chosen to vary from zero (static; congestion array never changes) to unity (congestion array changes instantaneously). In procedure 28,200c, a final congestion density enhancement array is calculated. The calculation may be performed once each timestep, in response to configuration changes, or both. Further details are illustrated in FIG. 30. In procedure 29,300a, the Steiner-cuts array is fetched from the generator. In some embodiments a timing kernel (TK) performs procedure 29,300a. The calculation may include an idealized buffer tree, at implementor or user discretion. In procedure 29,300b, the Steiner-cuts array is subject to a filtering operation to increase smoothness, which helps improve accuracy of a subsequent interpolation procedure. In some embodiments a number of binomial digital filter passes are used. In procedure 29,00c, the value at each gridpoint in the intermediate grid discretization is calculated using a linear spline approach. In procedure 30,400a, the congestion array is smoothed using filtering similar procedure 29,300b, in part to improve the accuracy of the interpolation. But filtering is also considered the “final smoothing” phase of the field and is subject to the most user and/or programmatic control, to improve the quality of the final result. The smoothing is most effective when the scale lengths associated with the variation of the density enhancement are “semi-global”, e.g. small compared to the die size, but large compared to motion of a node in a single timestep. In procedure 30,400b, the congestion array is normalized as needed. First it is clipped at a pre-determined value of maximum congestion, to constrain resulting density gradients within reasonable limits. In relative spreading mode, a normalization of unity is imposed, thus inducing a density-driven outflow from congested areas without regard to actual routing supply. In absolute spreading mode, the routing demand versus supply is compared to the maximum allowable relative demand (e.g. 80% capacity). Only at gridpoints where congestion exceeds the allowed limit does the enhancement field take on substantial values (while enforcing a reasonably smooth variation). In the case of a density-gradient model for calculating the expansion fields, the congestion density field that results is flat everywhere that routing supply satisfies demand, rising smoothly into elevated “mounds” at locations where the demand exceeds supply. The congestion array is then modified according to desired strength of the density enhancement effect. Both multiplicative and power-law transformations may be applied. The strength of the enhancement may be increased over time to allow for the gradual movement of nodes out of congested areas. In procedure 30,400c, the value of the congestion array at each SDI gridpoint is calculated using a linear spline approach. Tunneling Congestion Relief Embodiments In some SDI-based integrated circuit design flow embodiments “tunneling” is used to relieve congestion at boundaries. Tunneling governs transitions of nodes through one or more obstructed regions not available for node placement, i.e. xzones, of a chip (or portion thereof). In some embodiments the transition is according to a mathematical criterion. In some embodiments nodes are selected as tunneling candidates according to node attraction into one of the obstructed regions. In some embodiments the criterion is affected by node density. In some embodiments the criterion is affected by node interconnections (or connectivity). In some embodiments the criterion is affected by circuit performance (i.e. timing). Tunneling enables further placement progress, according to selected metrics such as routability and circuit performance, while taking into account xzones. Tunneling has several aspects including candidate node selection, nodal move speculation, and node tunneling criteria (i.e. keep move/tunnel or reject). In some embodiments tunneling is performed at the end of an SDI timestep. Any intervening sub-steps taken by the time integrator (e.g. part steps taken by a Runge-Kutta (RK) integrator) are not considered. During the course of a timestep (and any associated sub-steps) the nodes are allowed to drift into xzones in order to allow the time integrator to proceed at full speed, since in some usage scenarios a smooth trajectory in a numerical simulation enables more accurate integration, and thus may enable a longer timestep (given a predetermined accuracy target). At the end of one full timestep, only nodes that have been coerced into xzones are considered for tunneling speculation. FIG. 31 illustrates an embodiment of a processing flow for node tunneling out of exclusion zones in an SDI-based integrated circuit design flow. In some implementations any combination of the illustrated elements are performed by software routines known collectively as a “node mover”. In 31,100a nodes are selected as candidates for tunneling based on respective positions. Nodes that have moved into an xzone are included in a set of all transiting nodes. Each respective node will have arrived at the respective position (or point) due to (discounting inertial effects) the vector sum of all forces acting on the respective node. For example, some of the forces may be due to netlist connectivity (i.e. the respective node is drawn towards topologically close nodes) and some of the forces may be due to a local overabundance of nodes (density buildup). In some usage scenarios selecting nodes in xzones for tunneling consideration is an efficient selection criteria that discriminates nodes likely to benefit from a tunneling transition to another side of an xzone or multiple abutting xzones. In 31,100b, having determined candidate nodes, per-node initialization is performed. In some usage scenarios total tunneling candidate nodes are a small fraction of total nodes, and for efficiency a secondary set of data structures is used to process the candidate nodes. A transiting node class contains a node id (that maps to an original node entry) and any ancillary data required for accurate tunneling speculation. Henceforth, the class of all node candidates for tunneling is referred to as “transiting nodes”. In 31,100c, all transiting nodes are snapped to the nearest xzone boundary. The snapped position is identical to the resulting node position were no tunneling to occur, and assures a baseline for proper field computation and comparison to the post-transit result. In 31,100d, the forces on transiting nodes at the current positions (pre-speculation) are evaluated. See the discussion relating to FIG. 32 located elsewhere herein for further information. In 31,100e, the position of the transiting node is restored to the positions before processing relating to 31,100c. The node mover then finds the intercept on the xzone boundary that results from application of the force vector components on the node. In some embodiments node inertia is also taken into account when determining the xzone boundary intercept. The node is speculatively moved to just past the intercept position, outside the original xzone. In the event that multiple abutting xzones exist and the node lands in yet another xzone, the mover is invoked again using the original trajectory to direct the move. The speculative movement procedure is continued as many times as necessary for the node to arrive in a region external to any xzone. In 31,100f, the forces on transiting nodes at the new positions (post-speculation) are evaluated. See the discussion relating to FIG. 32 located elsewhere herein for further information. In 31,100g, the transition criteria are evaluated and examined. If the transition is accepted, then the node associated with the transiting node acquires the new coordinates. Otherwise the coordinates as determined in 31,100c are retained. See the discussion relating to FIG. 33 located elsewhere herein for further information. FIG. 32 illustrates an embodiment of SDI-related force calculations in a tunneling congestion relief context. In 32,200a, forces on the node are cleared and preparations are made for the field calculation. In 32,200b, forces on each node due to all non-field interactions are summed, including all connectivity and timing based pin to pin forces, as well as any other nodal interaction forces present. In 32,200c, gate field components are computed. The first time through (pre-speculation phase), a full field calculation is performed. The pre-speculation phase is with the nodes snapped to the nearest xzone boundary, so the result represents a result assuming no nodes transit. The second time through (post-speculation phase), the field calculation from the first phase is used, but applied to the speculative nodal coordinates. That is, it is assumed that the fields are not significantly changed on a global scale as a result of tunneling. In some usage scenarios, since only a small number of transitions are considered relative to the total number of nodes, the assumption serves as a reasonable approximation, and may be beneficial for computational efficiency since field computations for each individual speculation are avoided. FIG. 33 illustrates an embodiment of evaluation of tunneling transition criteria. In 33,300a, the speculative node coordinates are examined to see if there are violations of any node region constraints and if nodes fall into a legal logic area. If there is any violation, then the transition is rejected. In 33,300b, a statistical window on how many transitions are considered is applied. In some implementations the window is small (such as 1%, 2%, 5%, or 10%) compared to unity but not so small that an inordinate number of passes through speculator routines are required to process all qualifying nodes. The windowing helps prevent sloshing, where many nodes tunnel from a high to a low density region at once, altering density so much that nodes tunnel back later. In other words, the statistical window helps to ensure that approximations made with respect to 32,200c (of FIG. 32) are valid. In 33,300c, a variety of biasing factors are applied. In some implementations the factors are multiplied together. In some implementations one or more of the factors is less than unity. The factors include any combination of the following. A default biasing factor. A bias against multiple transitions in a row, to ensure longer relaxation time. A distance based biasing, to make it more difficult to travel long distances. The distance based biasing may involve either a hard limit or a functional dependence on distance traveled (e.g. linear or quadratic). A distance based biasing specific to timing critical nodes. Nodes on a critical path may have an unpredictable effect on timing due to tunneling, so the critical path nodes may be selectively more further constrained than other nodes. In 33,300d, the magnitude of the forces on the node at the old and the new positions are computed. If the new force magnitude after biasing is less than the old force magnitude, then the transition is considered to be energetically favorable and therefore accepted. Otherwise the transition is rejected. Clock Tree Synthesis (CTS) Embodiments CTS is a process for creating a clock network in an Integrated Circuit (IC) physical design flow. CTS has general applicability to design flows having limited placement options for clock buffers, such as SAF-based design flows. Note that although CTS is described herein within a general context of an SDI-based flow, there are applications to other types of design flows using conventional EDA tools. In some usage scenarios a structured ASIC design has one or more clock signals that fan out to many (perhaps thousands) of register clock pins. A register clock pin may be a clock pin of a flip-flop, a latch, or clock pins of embedded memory and other IP blocks. Clock nets produced by logic synthesis or derived from schematics act as placeholders for CTS-produced clock nets. Each of the logic synthesized clock nets drives a high drive strength buffer (an ideal clock). Each of the CTS-produced clock nets includes one or more levels of buffers, interconnect wires, and other gating logic such as clock_and, clock_or, clock_mux, and other similar clock manipulation elements. In some embodiments CTS is run post placement so that precise coordinates of clock pins driven by each clock net are known (such as portions of processing performed in conjunction with “Buffering Clock Tree Synthesis Timing Driven Buffering/Resizing” 821 of FIG. 8A). In some implementations a CTS tool builds a clock network that strives to optimize characteristics of the clock network including skew and latency. Clock skew is the difference of signal arrival times at clock pins of two registers. The CTS tool optimizes a maximum clock skew of the circuit, i.e. the largest clock skew between any pair of registers that have timing paths (setup/hold) between them is minimized. Clock latency is delay from a root of a clock tree to a clock input pin of a register. The CTS tool optimizes the maximum latency, i.e. the largest delay is minimized. In addition to skew and latency metrics, there are other considerations such as power and routing congestion addressed by the CTS tool. The CTS tool attempts to optimize (i.e. minimize) the buffers and wire resources used for clock distribution since the resources directly impact circuit routing congestion and dynamic power usage. In some embodiments CTS is performed in a post detail placement phase to enable building optimized clock networks, based on locations of clock leaf pins. Gating logic enables power reduction by selectively turning on and off sub-trees of a clock tree. Clock selector logic (such as using a clock_mux) multiplexes multiple user clocks and test clocks. A clock tree may have several levels of clock selector logic gates and several levels of clock gating logic gates. In some usage scenarios clock gating circuitry is pre-designed by the user at a hardware description level and is then synthesized into gates by a synthesis tool. The CTS tool balances clock networks while taking into consideration delays of various gating logic, thus treating the gating logic transparently and automatically. FIG. 34A illustrates an example clock tree suitable for input to a CTS tool for SAF-based design flows. Primary clock domains are illustrated as pclk0 and pclk1. Gated clock sub-domains are illustrated as gclk0 and gclk1. A clock selector based clock sub-domain is illustrated as mclk. Clocks pins of registers are illustrated as ckp0, ckp1, . . . ckpn; ckg0, . . . ckgn; cks0, cks1, . . . cksn; and cksg0, . . . cksgn. Register clock pins ckg0, . . . ckgn and cksg0, cksgn are associated with gated clocks. Register pins cks0, cks1, . . . cksn are associated with selected clocks. Register clock pins cksg0, . . . cksgn are associated with two levels of clock processing (select and gate functions). FIG. 34B illustrates an example clock tree output from the CTS tool operating on the input illustrated in FIG. 34A. In the illustrated output various Clock Networks produced by the CTS tool (according to the input illustrated by FIG. 34A) are shown driving the register clock pins. FIG. 34C illustrates an example clock tree network. Leaf buffers are illustrated as b1, b2, b3, and b4. Each of the buffers are shown driving (or fanning out to) a respective sea of clock pins as illustrated conceptually by the triangular element at each respective driver output. Terminals of the clock network are illustrated as t1, t2, and t3. Selected terminal buffers are illustrated as tb1 and tb2. A clock root is illustrated as CT. The illustrated clock tree network is representative of some implementations of the Clock Networks of FIG. 34B. For example, consider the Clock Network of FIG. 34B driving register clock pins ckp0, ckp1, . . . ckpn. CT of FIG. 34C corresponds to the element driving pclk0. Leaf buffer b1 drives ckp0, leaf buffer b2 drives ckp1, and so forth. FIG. 35 illustrates an overview of an embodiment of a CTS flow. According to various embodiments the CTS flow includes any combination of floorplan driven clock partitioning, topological clock sorting, top-down recursive bi-partitioning, clock domain (and sub-domain) processing, bottom-up skew minimization, and top-down buffer placement. Floorplan driven clock partitioning (such as illustrated in FIG. 35) may be used when a die floorplan has extensive arrays of RAM and/or IP structures that lack suitable sites or slots for clock tree buffer elements. When the CTS tool builds a clock tree, buffer sites at intermediate points of each clock network are used to drive two sub-trees “underneath” the respective intermediate point. Having large rows(columns) of RAMs/IP blocks implies that there are extensive die regions that are either completely devoid of clock buffer sites or have the sites at sub-optimal locations. Therefore, CTS preprocesses the clock network and embeds Pseudo-clock Sub-Domains (PSDs) that are first balanced within each row(column). Subsequently, the clock sub-domains are deskewed across logic rows(columns). The first level PSDs can be deskewed by buffer resources within a row(column), thus alleviating the need to find sites over RAM and/or IP regions. FIG. 36A illustrates an example die floorplan of a design having embedded RAM or other IP blocks. Regions 36,300a represent an I/O ring. Regions 36,300b1, 36,300b2, and 36,300b3 represent rows of embedded RAMs. Regions 36,300c1, 36,300c2, and 36,300c3 represent rows of logic blocks. CTS clock preprocessing proceeds as follows. Within each PSD, all clock leaf pins in each contiguous logic region (such as each of regions 36,300c1, 36,300c2, and 36,300c3) are merged so the leaf pins fan out from a single Root Clock row(column) Buffer (RCB). The RCB is optimally placed at the centroid of the bounding-box encompassed by all the leaf clock pins within the respective logic region. All RAM clock pins are then combined with logic clock pins by drawing a partitioning line through the middle of each RAM region. For example, if there are RAM clock pins in region 36,300b2, then each one is merged with clock pins of one of adjacent regions 36,300c1 or 36,300c2 depending on proximity of the respective RAM clock pin to the adjacent regions (i.e. the closest one of the regions is chosen). Then each of the region PSDs are deskewed individually. In some usage scenarios the deskewing is by combining even and odd row(column) RCBs separately. In other words, every other row(column) is processed together. In situations where RAM (or IP) rows(columns) are alternated with logic block rows(columns), and the rows(columns) are of approximately the same size, processing even/odd rows(columns) separately simplifies equidistant placement of RCB pairs, since the center of each RCB pair will be in a logic block row(column). For example, RCBs associated with region 36,300c1 are processed with RCBs associated with region 36,300c3, and equidistant placement may be satisfied by region 36,300c2, a logic region. Note that the RCBs associated with a logic region may include RAM clock pins from adjacent RAM regions, such as region 36,300c1 RCBs include merge RAM clock pins from the upper half of region 36,300b2 and the lower half of region 36,300b1. Subsequently, the even and odd RCBs are deskewed at the clock root. The aforementioned merging, partitioning, and RCB placement processing is performed for each primary clock. The leaf clock pins driven by gated-clocks and clock selectors cells are treated transparently during the processing. If a gated-clock or clock-selector logic drives leaf clock pins in multiple logic regions, then the gating logic is replicated in each of the respective regions the gated clock fans out to, thus enabling transparent merging of un-gated and gated-clock leaf pins. FIG. 36B illustrates a portion of a clock net in a context of a portion of FIG. 36A. Clock net “clk” feeds both un-gated and gated clock pins that span out to logic regions 36,300c1 and 36,300c2. The gated clock is replicated in region 36,300c2 so that the RCB in each region is enabled to independently drive both the un-gated and the gated branches of the clock trees. The replication technique reduces multi-level clock balancing across RAM regions and introduction of skew uncertainties. Topological clock sorting, or domain ordering (such as illustrated in FIG. 35) is performed so that the CTS tool visits the clock domains in an order that facilitates deskewing of lower level sub-domains prior to higher level sub-domains. In some embodiments various clock sorting functions are performed by software routines implemented in a topological sorter. In some usage scenarios a primary clock has several gated-clock and select-clock logic based sub-domains. As shown in FIG. 34A, main clock (clk) fans out to several leaf level clock pins after several levels of gating (gclk0, mclk, and gclk1). The sub-domains gclk0, mclk, and gclk1 carry the same primary clock (clk), but are gated (controlled) by user logic to enable selectively turning off for one or more clock cycles. Clock distribution information of FIG. 34A is processed by the topological sorter to produce sub-domain ordering: gclk1->mclk->gclk0->pclk0->pclk1->clk. The ordering ensures that when the un-gated leaf level pins of clk nets are being deskewed with the gated-clock pin (gclk0), the gated clock pin has already been completely processed (expanded) and any associated clock network latency is determined. Clock domains(and sub-domain) processing (such as illustrated in FIG. 35) includes processing the domains according to the topological domain ordering. A Clock Domain Processor (CDP) of the CTS tool first collects all clock pins to be deskewed. A user may mark pins to be excluded for deskewing and the CDP obeys the marking. The CDP forms two level clusters. For all the leaf clock pins that are pins of a leaf level register (such as flipflops, latches, and RAM blocks), recursive partitioning forms bottom-up clusters that may be driven by a leaf level clock buffer. Clustering of leaf level clock pins (such as illustrated in FIG. 35) is performed via recursive partitioning of all the leaf level clock pins, and forms small well-formed clock pin clusters that may be driven by leaf level clock buffers, thus reducing complexity of leaf level clock buffer implementation. The partitioning uses recursive bipartitioning with an objective function that minimizes the diameter of the polygon formed by all pins in a partition. As the diameter of the polygon computation has polynomial complexity, in some implementations a fast heuristic technique with linear complexity is used. The linear complexity technique computes an NSP of a bounding box of all leaf level pins in a partition. Clusters are also formed to increase relative “closeness” to other clusters having common setup and hold paths. Cluster closeness of two clusters is the number of clock buffers common to the clusters. In other words, tightly coupled leaf clock pins are grouped to share relatively many clock buffers, thus enabling more efficient skew reduction. FIG. 37A illustrates an example of timing driven pin swapping. As illustrated, it is preferable to partition clusters as P1={La, Ca}, P2={Lb, Cb} instead of P1={La, Lb} and P2={Ca, Cb}. The former promotes sharing of clock buffers between launch and capture flip-flops thereby reducing the skew between launch and capture flip-flops since unshared clock buffers may be subject to separate process, voltage, and temperature variations and thus may introduce skew. During recursive bipartitioning, each partition is scored based on timing relationships between each pin and every other pin of the partition. Cluster cost is a weighted sum of interconnect wiring cost and cluster-closeness cost. The interconnect wiring cost is determined from the NSP of the bounding box of all the pins constituting the cluster. For example, partition cost may be given by: Part_cost=0.5ciccic+0.5ctcctc where cic: is cluster interconnect cost, given by: cic=(1−part_interconnect_cost/best_interconnect_cost); and ctc is cluster timing cost given by ctc=(1−part_timing_cost/best_timing_cost). Additionally, pairwise swapping of edge pins based on timing relationships of the pins within the cluster is performed. The swapping is directed to achieve maximal common launch and capture paths for a pair of clock pins that have either a setup path or a hold path in common. FIG. 37B illustrates an example of effects of (top-down) clock tree partitioning. A random distribution of clock pins is illustrated in the upper portion of the figure. Results of clock tree partitioning and cluster formation are illustrated in the lower portion of the figure. The CDP performs top-down partitioning using leaf-level buffer input pins and any clock sub-domain clock pins. Clock sub-domain clock input pins include input pins of gated clock cells, clock selector cells, and derived clock pins of flip-flops. The clock sub-domains are processed top-down instead of being clustered with leaf level clock pins, thus enabling insertion delay of the clock sub-domain to be utilized to balance the sub-domains. As illustrated, results of a first recursive partitioning pass are shown as 37,100. Results of a pair of (independent) second recursive partitioning passes are shown as 37,200a and 37,200b. Results of a third recursive partitioning pass are shown as 37,300b. Note that although the recursive portioning results are illustrated as straight cut-lines splitting contiguous regions, various embodiments and starting conditions may result in cut-lines of any shape or form, such as zig-zags, curves, and so forth. Further note that the split regions may be non-contiguous; i.e. form one or more “islands” driven by a single leaf-level buffer. FIG. 38 illustrates an analysis according to an embodiment of clock domain and sub-domain partitioning. A clock “Root” is illustrated with relationships to leaf buffers lb1, lb2, lb3, lb4, lb5, lb6, and lb7. A tree of clock terminals is illustrated by t1, t2, t3, t4, t5, t6, and t7. In some embodiments edges are added to represent timing relationships (such as setup and hold times) between leaf level buffers. One type of timing relationship between first and second buffers is when the first buffer drives a first storage element, the second buffer drives a second storage element, and the two storage elements are coupled via a path having a setup (or hold) timing constraint. An example setup(hold) timing relationship between a flip-flop driven by lb1 and a flip-flop driven by lb4 is represented conceptually as dashed-line 38,100. As illustrated, skew is minimized between the two flip-flops by driving lb1 and lb4 via the same clock terminal (t4). The CDP creates distinct clock domains for the following types of clock nets: Primary clock nets; Clock nets driven by gated clock cells; Clock nets driven by clock selector cells; Pseudo clock domains (if floorplan driven clock partitioning has been performed); and Derived clock nets. Timing relationships between the leaf level buffers are used to create optimum timing driven partitions. A scoring function for a partition is a function of interconnect cost and timing cost. To determine setup/hold timing relationships between leaf level buffers, an abstract graph is used as illustrated in the figure, having edges between two leaf level buffers if a setup/hold path exists between elements driven by the two leaf level buffers. The weight of the edge is the number of setup/hold paths between the two leaf level buffers. As a result of top-down partitioning, the clock tree has two types of nodes, terminals and paths. A terminal represents a graph node that is processed by downstream modules for skew minimization. Each of the terminals has a pair of paths that represent the respective buffer path from the respective parent terminal to the respective pair of child terminals. Clock domain edges are analyzed so that clock clusters recursively propagate the clock edge (e.g. a rising edge or a falling edge) used by the clock pin clusters at leaf level. Thus only one of rise time or fall time is propagated for all intervening levels of logic cells (including buffers and non-buffers). During skew minimization (such as illustrated in FIG. 35) each internal terminal of a clock network is analyzed in a bottom-up visitation order and an ideal delay for each respective buffer pair is determined that will minimize the skew of the terminal. Skew minimization uses a successive approximation approach to determine types of buffer(s) and interconnect lengths associated with each of the buffers. During a first pass skew optimization (or minimization), a default input transition time is used to compute delays of all clock buffers. For each terminal, respective locations of buffer pairs to be placed are determined that would minimize skew for an entire sub-tree. If the skew cannot be minimized by placing the buffer pair between two child terminals, then an amount of meandering interconnect/buffers to minimize the skew is determined. An iterative skew improver portion of the CTS tool performs multi-pass skew computation and idealized delay allocation for each stage of a buffer tree. The skew improver performs a multi-pass optimization because skew minimization is done bottom-up but input transition is propagated top-down. Therefore during the first pass, a skew minimizer uses a default input transition for each buffer stage of a clock network and performs skew minimization at each level. Subsequently, a clock network timing update is performed that updates transition times at each level, top-down, using an estimated output load on each of the buffers of the network. A second pass of skew minimization is performed that uses the propagated input transition time at each of the clock buffers. Subsequent passes are performed (such as 1, 2, 3, 4, or 5 iterations) seeking convergence of the skew minimizer. Clock network timing is updated in accordance with buffer placement, delays of buffer gates, and interconnect delays. Since cell delays are functions of input transition time and phase, the clock network timing (arrival time and transition time) is relatively accurate to ensure that buffer cell delays computed at each of the terminals matches closely with post-routed-extracted delays. Transition time at an output of a gate is a function of input transition time at the gate and effective output load (Ceff) driven by the gate. The proper phase of transition times is propagated down a clock network to accurately estimate transition times and cell delays at a next level of the clock network. In some usage scenarios (such as an SAF-based design flow) buffers may not be placed at ideal locations (i.e. there is no logic block in a proper buffer position). Thus clock buffer placement is performed iteratively. Whenever a buffer is placed at a somewhat non-ideal location, the effect of that buffer placement is propagated throughout the clock sub-tree. A buffer placer module of the CTS tool inserts a pair of buffers at each terminal of a clock network. Unlike standard cell design flows where a buffer may be placed anywhere in a row of standard cell logic, structured ASICs are constrained in where buffer resources may be placed. Buffer placement is performed recursively down the clock tree. At each terminal, the buffer placer evaluates a finite number of buffer pair sites for suitability as a buffer pair of the respective terminal. The buffer pairs are located by using a search window around an ideal buffer pair location. The buffer placer uses a speculative scoring function to score each pair of buffers. Each buffer pair is scored on the basis of the objective function: buf_pair_cost=0.9buf_delay_cost+0.1buf_dist_cost; where buf_delay_cost=dd0dd0+dd1dd1+dd2dd2; where dd0=(1−est_delay/ideal_delay) for the respective parent terminal; dd1=(1−est_delay/ideal_delay) for the respective left terminal; and dd2=(1−est_delay/ideal_delay) for the respective right terminal. Similarly, buf—dist_cost=dbbdbb+msd1msd1+msd2msd2; and dbb=manhattan distance between the pair of buffer. Ideally the pair of buffers should be as close as possible to reduce any delay uncertainty between a parent buffer and respective buffer pairs. Using a dbb term penalizes any pair of buffers that are far apart. msd1(2)=distance between left/right buffer and merging segment. A merging segment is a line that goes between a pair of idealized buffer locations. The distance of the buffer location and the merge segment are measured. The idealized buffer locations for the downstream sub-tree are computed with the parent buffer being ideally placed on the merging segment. If actual placement of the buffer deviates too much from the idealized line segment then the estimates for the downstream terminal are no longer valid. When two sub-trees have considerable differences in accumulated insertion delays then delay buffers are inserted to match insertion delay at a parent terminal. Differences in insertion delays may occur in some usage scenarios where one branch of the clock sub-tree is a (relatively large) gated-clock sub-domain and remaining branches are relatively smaller gated or un-gated clock-sub-domains. Delay buffers are scored using an objective scoring function: delay—buf_cost=0.70dcostdcost+0.2ncostncost+0.1pcostpcost; where dcost=(1−(accum_delay+incr_delay)/ideal_delay); ncost=(1−actual_length/ideal_length); and pcost=(1−path_remaining_length/path_ideal_remaining_length). Besides the delay cost (which has the highest weighting), delay buf_cost uses two other metrics to evaluate a candidate delay buffer. Ncost factors in any deviation from ideal length of an interconnect for a respective path, and pcost factors in deviation of path length from a respective ideal path length. If the skew minimizer determines that the path requires some amount of meandering interconnect to add extra delay at the buffer, then a dummy-load insertion technique is used to implement the incremental meandering wire resource. A dummy load inserter portion of the CTS tool searches for optimal dummy load sites (typically a low drive strength inverter) on an SAF-based chip and connects the buffer to the dummy load. The CTS tool balances for max and min corners simultaneously as optimum skew for a max corner is not the optimum skew for min corner. In some usage scenarios skew at the max corner typically affects the setup timing paths whereas clock skew for the min corner affects the hold time paths. During deskewing monitored by the CTS tool, timing for both max and min corners (also known as mixed mode) is considered, and the CTS tool uses scoring functions (as described elsewhere herein) that uses a weighted sum of max and min scoring functions. Post-routed-extracted parasitics are used to perform clock tree optimization. The clock optimization is used to achieve timing closure in designs having correlation issues with predicted clock skew and post-extracted clock skew. In some usage scenarios, the CTS tool achieves a high degree of correlation with post-extracted skew using several techniques as described elsewhere herein. The CTS tool performs several clock tree optimizations, such as replacement of a clock gating cell, replacement of terminal buffers, dummy load insertion, and swapping a CTS buffer for some other morphable element that may be implemented as a buffer. CONCLUSION Certain choices have been made in the description merely for convenience in preparing the text and drawings and unless there is an indication to the contrary the choices should not be construed per se as conveying additional information regarding structure or operation of the embodiments described. Examples of the choices include: the particular organization or assignment of the designations used for the figure numbering and the particular organization or assignment of the element identifiers (i.e., the callouts or numerical designators) used to identify and reference the features and elements of the embodiments. Although the foregoing embodiments have been described in some detail for purposes of clarity of description and understanding, the invention is not limited to the details provided. There are many embodiments of the invention. The disclosed embodiments are exemplary and not restrictive. It will be understood that many variations in construction, arrangement, and use are possible, which are consistent with the description and are within the scope of the claims of the issued patent. For example, interconnect and function-unit bit-widths, clock speeds, and the type of technology used are variable according to various embodiments in each component block. The names given to interconnect and logic are merely exemplary, and should not be construed as limiting the concepts described. The order and arrangement of flowchart and flow diagram process, action, and function elements are variable according to various embodiments. Also, unless specifically stated to the contrary, value ranges specified, maximum and minimum values used, or other particular specifications (such as integration techniques and design flow technologies), are merely those of the described embodiments, are expected to track improvements and changes in implementation technology, and should not be construed as limitations. Functionally equivalent techniques known in the art are employable instead of those described to implement various components, sub-systems, functions, operations, routines, and sub-routines. It is also understood that many functional aspects of embodiments are realizable selectively in either hardware (i.e., generally dedicated circuitry) or software (i.e., via some manner of programmed controller or processor), as a function of embodiment dependent design constraints and technology trends of faster processing (facilitating migration of functions previously in hardware into software) and higher integration density (facilitating migration of functions previously in software into hardware). Specific variations in various embodiments include, but are not limited to: differences in partitioning; different form factors and configurations; use of different operating systems and other system software; use of different interface standards, network protocols, or communication links; and other variations to be expected when implementing the concepts described herein in accordance with the unique engineering and business constraints of a particular application. The embodiments have been described with detail and environmental context well beyond that required for a minimal implementation of many aspects of the embodiments described. Those of ordinary skill in the art will recognize that some embodiments omit disclosed components or features without altering the basic cooperation among the remaining elements. It is thus understood that much of the details disclosed are not required to implement various aspects of the embodiments described. To the extent that the remaining elements are distinguishable from the prior art, components and features that are omitted are not limiting on the concepts described herein. All such variations in design comprise insubstantial changes over the teachings conveyed by the described embodiments. It is also understood that the embodiments described herein have broad applicability to other computing and networking applications, and are not limited to the particular application or industry of the described embodiments. The invention is thus to be construed as including all possible modifications and variations encompassed within the scope of the claims of the issued patent.	G	60G06	161G06F	17	50
11692558	US20070233715A1-20071004	RESOURCE MANAGEMENT SYSTEM, METHOD AND PROGRAM FOR SELECTING CANDIDATE TAG	ACCEPTED	20070920	20071004	[]	G06F700	["G06F700", "G06F1730"]	9069867	20070328	20150630	715	234000	94935.0	HILLERY	NATHAN	[{"inventor_name_last": "Rekimoto", "inventor_name_first": "Junichi", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}]	Resource management system, method and program for selecting candidate tag are provided. The tag can be readily attached to a resource by presenting a candidate tag also to a resource newly registered in a database. The degree of similarity of a new registration resource to each of a plurality of already-registered resources that have been already registered in the database is calculated. A tag attached to an already-registered resource of which the degree of similarity is large is selected as a candidate for a tag to be attached to the new registration resource. Thereby, a candidate tag can be also presented to a resource newly registered in the database. A user can further readily attach a tag compared to a conventional system.	1. A resource management system comprising: degree-of-similarity calculating means for calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database; and candidate tag selecting means for selecting a tag attached to an already-registered resource of which said degree of similarity calculated by said degree-of-similarity calculating means is large, as a candidate for a tag to be attached to said new registration resource. 2. The resource management system according to claim 1, wherein; said resource is a web page, and said degree-of-similarity calculating means calculates the degree of similarity between text date described in an already-registered web page and text data described in a new registration web page. 3. A method for selecting a candidate tag, comprising: the degree-of-similarity calculating step of calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database; and the candidate tag selecting step of selecting a tag attached to an already-registered resource of which said degree of similarity calculated in said degree-of-similarity calculating step is large, as a candidate for a tag to be attached to said new registration resource. 4. A candidate tag selecting program embodied on a computer-readable medium for making an information processing unit executes: the degree-of-similarity calculating step of calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database; and the candidate tag selecting step of selecting a tag attached to an already-registered resource of which said degree of similarity calculated in said degree-of-similarity calculating step is large, as a candidate for a tag to be attached to said new registration resource.	<SOH> BACKGROUND <EOH>The present invention relates to a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program, and is applicable to the case of managing many resources by using a tag. Hereinafter, on the Internet, a system in which many users attach a tag to a common resource (a picture and a web bookmark) for arrangement has been generally used. For example, in the Flickr that is a picture sharing service for sharing a picture on the network (see http://www.flickr.com), an arbitrary tag such as “TOKYO”, “FOOD” or “PARTY” is attached to (associated with) a picture uploaded on a database, so that only a resource having a specified tag can be retrieved and extracted. Further, because resources are unnecessary to be classified in a specified hierarchical structure, a plurality of different images can be attached to one resource as tags, so that resources can be arranged further flexibly. This tag attachment may be individually performed. However, in the case where many users share the same resource, it works further effectively. For example, in the del.icio.us that is a social bookmark service for sharing an web bookmark on the network (see http://del.icio.us), a user can attach an arbitrary tag such as “PROGRAMMING”, “GUIDE”, “SERVICE” or “SHOPPING” to a bookmarked web page for arrangement. Further, this del.icio.us has a candidate tag present function in that if the same web page has been already bookmarked by other user, a tag attached by the above other user is presented as a candidate tag. Thereby, if a desired tag has been already attached by other user, it is unnecessary to enter the character string, and the user can readily perform tag attachment by selecting the presented candidate tag with a mouse or the like. However, in the aforementioned candidate tag present function, when in newly performing a bookmark registration of an web page that has not been bookmarked by other user, because existent tag information cannot be used, the user have to enter a tag explicitly. Therefore, there has been a tendency that as to a famous web page of which the degree of sharing is high such that many tags have been already attached, plentiful tags will be attached and it can be readily retrieved, however, as to an web page newly bookmarked, because a tag attachment operation is complicated, tag attachment is not performed so actively. As the above, in a conventional social bookmark service, there has been a problem that a tag attachment operation to a new bookmark is complicated.	<SOH> SUMMARY <EOH>In view of the foregoing, it is desirable to provide a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program in that a tag can be readily attached to a resource newly registered. The present application can be applied to various resource management systems. According to an embodiment, there is provided degree-of-similarity calculating means for calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database, and candidate tag selecting means for selecting a tag attached to an already-registered resource of which the degree of similarity calculated by the degree-of-similarity calculating means is large, as a candidate for a tag to be attached to the new registration resource. By selecting a tag attached to a resource of which the degree of similarity is high as a candidate tag, a candidate tag can be also presented to a resource newly registered in a database. Thereby, a user can further readily attach a tag compared to a conventional system. The nature, principle and utility of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. Additional features and advantages are described herein, and will be apparent from, the following Detailed Description and the figures. BRFSUM description="Brief Summary" end="tail"?	CROSS REFERENCE TO RELATED APPLICATION The present application claims priority to Japanese Patent Application JP 2006-095051 filed in the Japanese Patent Office on Mar. 30, 2006, the entire contents of which is being incorporated herein by reference. BACKGROUND The present invention relates to a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program, and is applicable to the case of managing many resources by using a tag. Hereinafter, on the Internet, a system in which many users attach a tag to a common resource (a picture and a web bookmark) for arrangement has been generally used. For example, in the Flickr that is a picture sharing service for sharing a picture on the network (see http://www.flickr.com), an arbitrary tag such as “TOKYO”, “FOOD” or “PARTY” is attached to (associated with) a picture uploaded on a database, so that only a resource having a specified tag can be retrieved and extracted. Further, because resources are unnecessary to be classified in a specified hierarchical structure, a plurality of different images can be attached to one resource as tags, so that resources can be arranged further flexibly. This tag attachment may be individually performed. However, in the case where many users share the same resource, it works further effectively. For example, in the del.icio.us that is a social bookmark service for sharing an web bookmark on the network (see http://del.icio.us), a user can attach an arbitrary tag such as “PROGRAMMING”, “GUIDE”, “SERVICE” or “SHOPPING” to a bookmarked web page for arrangement. Further, this del.icio.us has a candidate tag present function in that if the same web page has been already bookmarked by other user, a tag attached by the above other user is presented as a candidate tag. Thereby, if a desired tag has been already attached by other user, it is unnecessary to enter the character string, and the user can readily perform tag attachment by selecting the presented candidate tag with a mouse or the like. However, in the aforementioned candidate tag present function, when in newly performing a bookmark registration of an web page that has not been bookmarked by other user, because existent tag information cannot be used, the user have to enter a tag explicitly. Therefore, there has been a tendency that as to a famous web page of which the degree of sharing is high such that many tags have been already attached, plentiful tags will be attached and it can be readily retrieved, however, as to an web page newly bookmarked, because a tag attachment operation is complicated, tag attachment is not performed so actively. As the above, in a conventional social bookmark service, there has been a problem that a tag attachment operation to a new bookmark is complicated. SUMMARY In view of the foregoing, it is desirable to provide a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program in that a tag can be readily attached to a resource newly registered. The present application can be applied to various resource management systems. According to an embodiment, there is provided degree-of-similarity calculating means for calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database, and candidate tag selecting means for selecting a tag attached to an already-registered resource of which the degree of similarity calculated by the degree-of-similarity calculating means is large, as a candidate for a tag to be attached to the new registration resource. By selecting a tag attached to a resource of which the degree of similarity is high as a candidate tag, a candidate tag can be also presented to a resource newly registered in a database. Thereby, a user can further readily attach a tag compared to a conventional system. The nature, principle and utility of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. Additional features and advantages are described herein, and will be apparent from, the following Detailed Description and the figures. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram showing an overall configuration of a bookmark sharing system. FIG. 2 is a schematic diagram showing the configuration of a bookmark registration screen. FIG. 3 is a flowchart of a candidate tag selecting processing procedure. FIG. 4 is a schematic diagram for explaining the calculation of a tag factor corresponding to the attached number of tags. FIG. 5 is a schematic diagram for explaining a text management system to which an embodiment of the present invention is applied. DETAILED DESCRIPTION Preferred embodiments will be described with reference to the accompanying drawings. (1) Overall Configuration of Social Bookmark System Referring to FIG. 1, the reference numeral 1 designates a bookmark sharing system as a whole. The bookmark sharing system 1 is formed by that a plurality of user terminals 4 are connected to a bookmark server 2 via the Internet 3. Each user terminal 4 is an information processing unit having an Internet connection function such as a personal computer, a personal digital assistant (PDA) and a cellular phone. Each of them accesses an web server on the Internet 3 (not shown) according to a user operation, obtains web page data, and displays an web page based on the above obtained web page data to make a user view it. In addition to this, in the bookmark sharing system 1, by that the user of the user terminal 4 registers a user account on the bookmark server 2, a bookmark list peculiar to the above user account can be formed in the bookmark server 2. The registration user of the bookmark sharing system 1 (hereinafter, it is also simply referred to as “user”) can register the bookmark of an arbitrary web page in the user's own bookmark list (hereinafter, it is also simply referred to as “bookmark an web page”). Additionally, in the bookmark sharing system 1, when in registering a bookmark in the bookmark list, the user can attach an arbitrary tag to the above bookmark. Further, the user also can retrieve a bookmark registered by other user, by using an arbitrary tag as a keyword. That is, in the bookmark server 2, the lists of their respective bookmarks of each user have been stored in a bookmark database in a hard disk drive 11 (FIG. 2). If receiving a bookmark registration request from the user terminal 4, the Central Processing Unit (CPU) 10 of the bookmark server 2 enters this in the bookmark list of the registration user by associating an web page with a tag that are specified in the above bookmark registration request. Further, if receiving a bookmark retrieval request from the user terminal 4, the CPU 10 of the bookmark server 2 performs retrieval from the bookmark database, by using the tag specified by the above registration request as a keyword, extracts a bookmark to which the same tag as the specified tag has been attached as the retrieval result, and returns this to the user terminal 4. In this manner, in the bookmark sharing system 1, users can register their own bookmark lists in the bookmark server 2 respectively. At the same time, many bookmarks registered by each user can be shared among all of the registration users, and a desired bookmark can be retrieved using a tag from among the above many bookmarks. (2) Automatic Presentation of Candidate Tag (2-1) Configuration of Bookmark Registration Screen In addition to the above configuration, at the time when a user newly registers an arbitrary web page in a bookmark list, if this new registration page has been already registered by other user, the bookmark server 2 presents a tag attached to the already-registered page by the other user or the like as a candidate tag. That is, if accepting a predetermined bookmark registration operation by the user via input means such as a keyboard, the user terminal 4 transmits the Uniform Resource Locator (URL) of the new registration page that was specified by the user as an object of a bookmark in this operation to the bookmark server 2, with a bookmark registration temporary request. If receiving the bookmark registration temporary request transmitted from the user terminal 4, by responding this, the CPU 10 of the bookmark server 2 returns display data for displaying a bookmark registration screen 20 shown in FIG. 2 to the user terminal 4. Thereby, the bookmark registration screen 20 is displayed in the above user terminal 4. As shown in FIG. 2, in the bookmark registration screen 20, a URL display field 21 to display the URL of the new registration page specified as the bookmark object in the bookmark registration temporary request (hereinafter, it is referred to as “new registration URL”), a page name display field 22 to display the name of the new registration page, a tag display field 23 to display a tag to be attached to the new registration page, and a bookmark registration button 24 to register the new registration page in the user's bookmark list are displayed. In the URL display field 21, the page name display field 22 and the tag display field 23, an arbitrary character can be entered by the user via input means such as a keyboard provided in the user terminal 4. For example, in the page name display field 22, a page name attached to the new registration page is automatically displayed. However, the above page name can be freely changed by the user. Similarly, the URL displayed in the URL display field 21 can also be freely changed by the user. Thereby, a lower-order page, a higher-order page or the like in the web page can be arbitrary specified and set as a new registration URL. Further, in the tag display field 23, one or a plurality of character strings to be attached to a bookmark can be arbitrary entered by the user as a tag. Further, at a part lower than the tag display field 23 in the bookmark registration screen 20, one or a plurality of candidate tags 25 recommended by the bookmark server 2 for the new registration URL specified in the bookmark registration temporary request are displayed. This candidate tag 25 is that the bookmark server 2 selected a tag related to the new registration URL by candidate tag selecting processing that will be described later. Then, the user can select an arbitrary one of the displayed candidate tags 25 to make it display in the tag display field 23. That is, if accepting a candidate tag 25 selecting operation by the user via the input means such as a keyboard, by responding to this, the user terminal 4 copies the character string of the selected candidate tag 25, and displays it in the tag display field 23. In this manner, in the bookmark sharing system 1, the bookmark server 2 presents candidate tags 25 related to a new registration URL. Thereby, the user can readily perform tag attachment. Then, if accepting a pressing operation of the bookmark registration button 24 by the user via the input means, by responding to this, the user terminal 4 transmits the new registration URL and the page name, and an attached tag to the bookmark server 2 with a bookmark registration request. If receiving the bookmark registration request transmitted from the user terminal 4, by responding to this, the CPU 10 of the bookmark server 2 associates the page name and the tag with the new registration URL received at the same time, and registers this in this user's bookmark list as an already-registered URL. Further, at this time, the CPU 10 of the bookmark server 2 accesses an web page specified by the new registration URL, obtains a document described in the above web page as already-registered text data, and registers this in the bookmark list in association with the already-registered URL. (2-2) Candidate Tag Selecting Processing Next, the aforementioned candidate tag selecting processing for a new registration URL by the bookmark server 2 will be described in detail. If receiving a bookmark registration temporary request from the user terminal 4, the CPU 10 of the bookmark server 2 retrieves the same URL as the new registration URL that was received with the above bookmark registration temporary request from the bookmark lists of all of users on the bookmark database. If the same URL as the new registration URL has been registered in some bookmark lists as an already-registered URL, the CPU 10 obtains a tag attached to the above already-registered URL from the bookmark database, and transmits this to the user terminal 4 as a candidate tag with display data for displaying the bookmark registration screen 20. On the contrary, if the same URL as the new registration URL has not been registered in any bookmark lists (that is, if this URL will be registered in the bookmark database for the first time), the CPU 10 cannot select a candidate tag in this state. Therefore, the CPU 10 of the bookmark server 2 accesses a new registration page specified by the above new registration URL, and obtains a character string described in the above new registration page as new registration text data. Then, the CPU 10 compares the obtained new registration text data with all of already-registered text data stored in the bookmark database and calculates the degree of similarity respectively (the calculating method will be described later), selects a predetermined number of (for example, ten) already-registered text data of which the degree of similarity to the above new registration text data is high, and transmits a tag attached to the already-registered URL corresponding to the above selected already-registered text data of which the degree of similarity is high to the user terminal 4 as a candidate tag, with display data for displaying the bookmark registration screen 20. Then, the user terminal 4 displays the candidate tag received from the bookmark server 2 in the bookmark registration screen 20 to present this to the user. In this manner, the CPU 10 of the bookmark server 2 retrieves an already-registered page having the contents similar to a new registration page, and selects a tag attached to this as a candidate tag. Thereby, a candidate tag can be also presented to a bookmark registered in the bookmark database for the first time. (2-3) Calculation of Degree of Similarity and Selection of Candidate Tag Next, the aforementioned method for calculating the degree of similarity between new registration text data and already-registered text data, and a method for selecting a candidate tag will be described. As a method for calculating the degree of similarity between text data, a method for obtaining the number of co-occurrence of words, a method using Latent Semantics Analysis (LSA), and the like have been generally used. These various methods for calculating the degree of similarity can be used in the present invention. Further, as a method for selecting a candidate tag, if the degree of similarity between new registration text data and already-registered text data Sim(Newpage,Webi) was calculated as being within −1 to 1, a tag attached to the already-registered page is added by the following formula: W(Tagj)≡Σ{Sim(NewPage,Webi)*(Σ hasTag(Webi,Tagj))} (1) Here, the W(Tag) is an weighting factor to determine whether or not Tag should be set as a candidate. Further, if the tag Tagj has been attached to a certain web page Webi, the tag factor hasTag(Webi,Tagj) becomes 1, and if the tag Tagj has not been attached, it becomes 0. In this manner, the weighting factor W(Tag) can be calculated about the respective tags attached to all of the already-registered pages. Thereby, an adequate number of (for example, ten) tags of which the above weighting factor W(Tag) is large are selected, and are transmitted to the user terminal 4 as candidate tags. (2-4) Candidate Tag Selecting Processing Procedure Next, the procedure of the aforementioned processing that the bookmark server 2 selects a candidate tag for a new registration page and transmits this to the user terminal 4 will be described in detail, with reference to a flowchart shown in FIG. 3. The CPU 10 of the bookmark server 2 enters a candidate tag selecting processing procedure RT1 from the start step, and proceeds to step SP1. If receiving a new registration URL from the user terminal 4 with a bookmark registration temporary request, the CPU 10 proceeds to the next step SP2. In step SP2, the CPU 10 retrieves the same URL as the above new registration URL from already-registered URL in the bookmark database, by using the received new registration URL as a retrieval keyword, and proceeds to the next step SP3. In step SP3, the CPU 10 determines whether the same already-registered URL as the new registration URL has been registered in the bookmark database, based on the retrieval result. If an affirmative result is obtained in step SP3, this means that an web page that is going to be performed bookmark registration has already been registered in the bookmark database by other user. At this time, the CPU 10 proceeds to step SP4 to select a tag attached to the same already-registered URL as the new registration URL as a candidate tag, and proceeds to step SP7. On the contrary, if a negative result is obtained in this step SP3, this means that the above web page will be registered in the bookmark database for the first time. At this time, the CPU 10 proceeds to step SP5. In step SP5, the CPU 10 serving as degree-of-similarity calculating means accesses a new registration page specified by the new registration URL, obtains a character string described in the above page as new registration text data, and compares the above new registration text data with all of the already-registered text data stored in the bookmark database and calculates the degree of similarity respectively. Then, the CPU 10 proceeds to the next step SP6. In step SP6, the CPU 10 serving as candidate tag selection means calculates the respective weighting factors W(Tag) of tags attached to each already-registered page based on the calculated degree of similarity, and selects a tag of which the above weighting factor W(Tag) is large as a candidate tag. Then, the CPU 10 proceeds to the next step SP7. And then, in step SP7, the CPU 10 transmits the selected candidate tag to the user terminal 4, and proceeds to the next step SP8 to finish the candidate tag selecting processing procedure. (3) Operation and Effect According to the above configuration, if a new registration page accepted from the user terminal 4 has been already bookmarked by other user, the bookmark server 2 in the bookmark sharing system 1 selects a tag that has been attached to this page by that other user as a candidate tag, and transmits this to the user terminal 4. Thereby, a tag attachment operation to the above new registration page can be readily performed. Further, even if the new registration page accepted from the user terminal 4 has not been bookmarked by other user, the bookmark server 2 selects a tag that has been attached to a page having the similar contents to the new registration page, in all of the web pages that have been performed bookmark registration in the bookmark database as a candidate tag, and transmits this to the user terminal 4. Thereby, a tag attachment operation can be also readily performed to an web page that will be completely newly performed bookmark registration in the bookmark database. (4) Other Embodiments In the aforementioned embodiment, it has dealt with the case where a tag factor is calculated based on the presence of tag attachment, by setting a tag factor hasTag(Webi,Tagj)=1 when a tag Tagj has been attached to a certain web page Webi, and by setting a tag factor hasTag(Webi,Tagj)=0 when a tag Tagj has not been attached. However, the present invention is not only limited to this but also the tag factor may be calculated by considering the number of users who attached a tag. For example, it can be considered that when n pieces of tag Tagj have been attached to a certain web page Webi, a tag factor HasTag(Webi,Tagj)=n is set. That is, in a social tagging system as the bookmark sharing system 1 of an embodiment of the present invention, there is often a case where a plurality of users attach the same tag to a certain web page. For example, in FIG. 4, to a certain web page WebA, a tag “WINE” has been attached by three users, a tag “BAR” has been attached by two users, and a tag “RESTAURANT” has been attached by one user. A tag factor in this case is hasTag(WebA,WINE)=3, hasTag(WebA,BAR)=2, and hasTag(WebA,RESTAURANT)=1. In this manner, if calculating a weighting factor W(Tag) using a tag factor in consideration of the attached number of tags, a candidate tag which reflects tag attachment state and is highly accurate can be selected. Further, in the aforementioned embodiment, it has dealt with the case where the present invention is applied to tag attachment to an web page in the bookmark sharing system 1. However, the present invention is not only limited to this but also it can be widely applied to the case of attaching a tag to various resources of which the degree of similarity can be calculated. As such resources to which the present invention is applicable, audio data and image data, and the like can be considered. Then, as a method for calculating the degree of similarity for audio data, a similarity of power spectrum in musical compositions (J.-J. Aucouturier and F. Pachet: Music similarity measures: What's the use? Proc. ISMIR 2002, pp. 157•63 (2002)), a similarity of rhythm (J. Paulus and A. Klapuri: Measuring the similarity of rhythmic patterns. Proc. ISMIR 2002, pp. 150-156 (2002)), the feature amount of a modulation spectrum (Dixon, E. Pampalk and G. Widmer: Classification of dance music by periodicity patterns. Proc. ISMIR 2003, pp. 159•65 (2003), or the like can be used. On the other hand, as a method for calculating the degree of similarity for image data, a method based on fractal images (Takanori Yokoyama, Toshinori Watanabe and Ken Sugawara: “Feature Amount Based on Correspondence of Fractal Coded Images and Similarity Retrieval”, the technical report by the Institute of Image Information and Television Engineers, Vol. 26, No. 54, pp. 29-32, 2002), or the like can be used. Further, in the aforementioned embodiment, it has dealt with the case where the present invention is applied to a system in that a plurality of users attach a tag to a resource to manage information as a social tagging system. However, the present invention is not only limited to this but also can be applied to an individual information management system in that one user manages information. As an example of such individual information management system, a text management system in that a tag is attached to a text memo and is managed on a computer can be considered, for example. That is, as shown in FIG. 5, in the text management system, an arbitrary tag is attached to a text memo entered by a user, and the text memo can be retrieved using the above tag. Then, if a new text memo is entered by the user, the CPU of a computer executing the text management system calculates the degree of similarity between the above new text memo and existent text memos already entered, and presents a tag that has been attached to a text memo of which the degree of similarity is high as a candidate tag for the new text memo. Thereby, in this text management system, the user can perform tag attachment to a text memo with a simple operation. According to an embodiment, there is provided degree-of-similarity calculating means for calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database, and candidate tag selecting means for selecting a tag attached to an already-registered resource of which the degree of similarity calculated by the degree-of-similarity calculating means is large, as a candidate for a tag to be attached to the new registration resource. Thereby, a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program in that a candidate tag can be also presented to a resource newly registered in a database, and a user can further readily attach a tag compared to a conventional system can be realized. It should be understood that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications can be made without departing from the spirit and scope of the present subject matter and without diminishing its intended advantages. It is therefore intended that such changes and modifications be covered by the appended claims.	G	60G06	161G06F	7	00
11863902	US20090089313A1-20090402	DECENTRALIZED RECORD EXPIRY	ACCEPTED	20090318	20090402	[]	G06F1730	["G06F1730"]	7783607	20070928	20100824	707	662000	64848.0	ARJOMANDI	NOOSHA	[{"inventor_name_last": "Cooper", "inventor_name_first": "Brian", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Weaver", "inventor_name_first": "Daniel", "inventor_city": "Redwood City", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Bigby", "inventor_name_first": "Michael", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Srivastava", "inventor_name_first": "Utkarsh", "inventor_city": "Fremont", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Bohannon", "inventor_name_first": "Philip L.", "inventor_city": "Cupertino", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Yerneni", "inventor_name_first": "Ramana", "inventor_city": "Cupertino", "inventor_state": "CA", "inventor_country": "US"}]	A technique is described that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. In accordance with the technique, a record is checked to see if it has expired only when it has been accessed for a read or a write. If at the time of a read a record is determined to have expired, then it is not served. If at the time of a write a record is determined to have expired, then the write is treated as an insertion of a new record, and steps are taken to treat the insertion consistently with regard to the previous expired version. A background process is used to delete records that have not been written to or actively deleted by a client after expiration.	1. A method for automatically deleting an expired record in a distributed database system comprising a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases, the method comprising: receiving a write request for a record at one of the plurality of nodes, wherein the record is part of a partition stored in the database managed by the one of the plurality of nodes; determining whether the record is expired responsive to receiving the write request; determining if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired; and responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, generating an updated record based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition; and overwriting the expired record with the updated record. 2. The method of claim 1, wherein generating an updated record based on the write request further comprises setting a sequence number stored in the updated record to an initial value. 3. The method of claim 1, further comprising: sending a message to the other nodes regarding the overwriting of the expired record with the updated record. 4. The method of claim 1, further comprising: responsive to determining that the incarnation number associated with the partition does not exceed the incarnation number stored in the record, deleting the expired record, wherein deleting the expired record comprises sending a message to a remote node to increment an incarnation number associated with a partition stored in the database managed by the remote node, generating an updated record based on the write request, and inserting the updated record. 5. The method of claim 3, wherein generating the updated record comprises: obtaining an incarnation number from a remote node, wherein the incarnation number obtained from the remote node is associated with a partition stored in the database managed by the remote node, and replacing the incarnation number stored in the record with the incarnation number obtained from the remote node. 6. A distributed database system, comprising: a plurality of nodes, wherein the plurality of nodes are interconnected via a communication system; and a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases; wherein each node in the plurality of nodes is further configured to receive a write request for a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired responsive to receiving the write request, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and, responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, to generate an updated record based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition, and to overwrite the expired record with the updated record. 7. The system of claim 6, wherein each node in the plurality of nodes is configured to generate an updated record based on the write request by setting a sequence number stored in the updated record to an initial value. 8. The system of claim 6, wherein each node in the plurality of nodes is further configured to send a message to the other nodes via the communication system regarding the overwriting of the expired record with the updated record. 9. The system of claim 6, wherein each node in the plurality of nodes is further configured to, responsive to determining that the incarnation number associated with the partition does not exceed the incarnation number stored in the record, delete the expired record, wherein deleting the expired record comprises sending a message to a remote node to increment an incarnation number associated with a partition stored in the database managed by the remote node, to generate an updated record based on the write request, and to inserting the updated record. 10. The system of claim 9, wherein each node in the plurality of nodes is configured to generate the updated record by obtaining an incarnation number from a remote node, wherein the incarnation number obtained from the remote node is associated with a partition stored in the database managed by the remote node, and replacing the incarnation number stored in the record with the incarnation number obtained from the remote node. 11. A method for automatically deleting an expired record in a distributed database system comprising a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases, the method comprising: reading a record at one of the plurality of nodes, wherein the record is part of a partition stored in the database managed by the one of the plurality of nodes; determining whether the record is expired; determining if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired; and purging the record responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record. 12. The method of claim 11, further comprising: sending a message to the other nodes regarding the purging of the record. 13. The method of claim 11, further comprising: responsive to determining that the incarnation number associated with the partition does not exceed the incarnation number stored in the record, deleting the expired record, wherein deleting the expired record comprises sending a message to a remote node to increment an incarnation number associated with a partition stored in the database managed by the remote node. 14. A distributed database system, comprising: a plurality of nodes, wherein the plurality of nodes are interconnected via a communication system; and a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases; wherein each node in the plurality of nodes is further configured to read a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and to purge the record responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record. 15. The system of claim 14, wherein each node in the plurality of nodes is further configured to send a message to the other nodes regarding the purging of the record. 16. The system of claim 14, wherein each node in the plurality of nodes is further configured to, responsive to determining that the incarnation number associated with the partition does not exceed the incarnation number stored in the record, delete the expired record, wherein deleting the expired record comprises sending a message to a remote node to increment an incarnation number associated with a partition stored in the database managed by the remote node. 17. A method in a distributed database system for determining which of a first version of a record and a second version of a record is the most recent, comprising: comparing an incarnation number associated with the first version of the record and an incarnation number associated with the second version of the record, wherein each incarnation number represents a version of a partition that existed at the time each record was created; and responsive to determining that one of the first version of the record or the second version of the record has a greater incarnation number, identifying as the most recent the one of the first version of the record or the second version of the record having the greater incarnation number. 18. The method of claim 17, wherein comparing an incarnation number associated with the first version of the record and an incarnation number associated with the second version of the record comprises: reading the first version of the record to obtain the incarnation number associated with the first version of the record; and reading the second version of the record to obtain the incarnation number associated with the second version of the record. 19. The method of claim 17, further comprising: responsive to determining that the first version of the record and the second version of the record have the same incarnation number, comparing a sequence number associated with the first version of the record and a sequence number associated with the second version of the record; and responsive to determining that one of the first version of the record or the second version of the record has a greater sequence number, identifying as the most recent the one of the first version of the record or the second version of the record having the greater sequence number. 20. The method of claim 19, wherein comparing a sequence number associated with the first version of the record and a sequence number associated with the second version of the record comprises: reading the first version of the record to obtain the sequence number associated with the first version of the record; and reading the second version of the record to obtain the sequence number associated with the second version of the record.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The invention generally relates to the deletion of data from a database. In particular, the invention relates to the automatic deletion of expired data in a distributed database system. 2. Background As used herein the term “record expiry” refers to a system-initiated deletion of a database record. Database records may be set to expire for any number of reasons. For example, the value or relevance of some information decreases over time. Additionally, expiry may be used to remove older data from a system to free up resources to make room for newer data. Various approaches are known for automatically determining when a record in a database has expired and then deleting the record accordingly. By necessity, every approach adds some level of complexity to a database system and consumes some resources of the system. In a distributed database system in which multiple copies of the same record exist in different storage locations, record expiry becomes an even more complex task as the expiration of a record must be carried out in a manner that ensures that different versions of the same record can be properly sequenced after the expiration has occurred. Furthermore, the expiration of a record in a distributed database system consumes even more resources as database operations impacting one copy of a record must be propagated to remotely-stored copies of the same record. What is needed then is a technique that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system.	<SOH> BRIEF SUMMARY OF THE INVENTION <EOH>The present invention provides a technique that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. In particular, a method is described herein for automatically deleting an expired record in a distributed database system that includes a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases. In accordance with the method, a write request is received for a record at one of the plurality of nodes. The record is part of a partition stored in the database managed by the one of the plurality of nodes. Responsive to receiving the write request, it is determined whether the record is expired. Responsive to a determination that the record is expired, it is determined if an incarnation number associated with the partition exceeds an incarnation number stored in the record. Responsive to a determination that the incarnation number associated with the partition exceeds the incarnation number stored in the record, an updated record is generated based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition. Further responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, the expired record is overwritten with the updated record. A distributed database system is also described herein. The system includes a plurality of nodes, wherein the nodes are interconnected via a communication system. The system also includes a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases. Each node in the plurality of nodes is further configured to receive a write request for a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired responsive to receiving the write request, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and, responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, to generate an updated record based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition, and to overwrite the expired record with the updated record. An additional method is described herein for automatically deleting an expired record in a distributed database system comprising a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases. In accordance with the method, a record is read at one of the plurality of nodes. The record is part of a partition stored in the database managed by the one of the plurality of nodes. It is then determined whether the record is expired. Responsive to a determination that the record is expired, it is determined if an incarnation number associated with the partition exceeds an incarnation number stored in the record. Responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, the record is purged. An additional distributed database system is also described herein. The system includes a plurality of nodes, wherein the nodes are interconnected via a communication system. The system also includes a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases. Each node in the plurality of nodes is further configured to read a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and to purge the record responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record. Another method is described herein for determining in a distributed database system which of a first version of a record and a second version of a record is the most recent. In accordance with the method, an incarnation number associated with the first version of the record is compared to an incarnation number associated with the second version of the record. Each incarnation number represents a version of a partition that existed at the time each record was created. Responsive to determining that one of the first version of the record or the second version of the record has a greater incarnation number, the one of the first version of the record or the second version of the record having the greater incarnation number is identified as the most recent. The foregoing method may further include comparing a sequence number associated with the first version of the record and a sequence number associated with the second version of the record responsive to determining that the first version of the record and the second version of the record have the same incarnation number. Then, responsive to determining that one of the first version of the record or the second version of the record has a greater sequence number, the one of the first version of the record or the second version of the record having the greater sequence number is identified as the most recent. Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein.	BACKGROUND OF THE INVENTION 1. Field of the Invention The invention generally relates to the deletion of data from a database. In particular, the invention relates to the automatic deletion of expired data in a distributed database system. 2. Background As used herein the term “record expiry” refers to a system-initiated deletion of a database record. Database records may be set to expire for any number of reasons. For example, the value or relevance of some information decreases over time. Additionally, expiry may be used to remove older data from a system to free up resources to make room for newer data. Various approaches are known for automatically determining when a record in a database has expired and then deleting the record accordingly. By necessity, every approach adds some level of complexity to a database system and consumes some resources of the system. In a distributed database system in which multiple copies of the same record exist in different storage locations, record expiry becomes an even more complex task as the expiration of a record must be carried out in a manner that ensures that different versions of the same record can be properly sequenced after the expiration has occurred. Furthermore, the expiration of a record in a distributed database system consumes even more resources as database operations impacting one copy of a record must be propagated to remotely-stored copies of the same record. What is needed then is a technique that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. BRIEF SUMMARY OF THE INVENTION The present invention provides a technique that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. In particular, a method is described herein for automatically deleting an expired record in a distributed database system that includes a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases. In accordance with the method, a write request is received for a record at one of the plurality of nodes. The record is part of a partition stored in the database managed by the one of the plurality of nodes. Responsive to receiving the write request, it is determined whether the record is expired. Responsive to a determination that the record is expired, it is determined if an incarnation number associated with the partition exceeds an incarnation number stored in the record. Responsive to a determination that the incarnation number associated with the partition exceeds the incarnation number stored in the record, an updated record is generated based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition. Further responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, the expired record is overwritten with the updated record. A distributed database system is also described herein. The system includes a plurality of nodes, wherein the nodes are interconnected via a communication system. The system also includes a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases. Each node in the plurality of nodes is further configured to receive a write request for a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired responsive to receiving the write request, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and, responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, to generate an updated record based on the write request, wherein generating the updated record comprises replacing the incarnation number stored in the record with the incarnation number associated with the partition, and to overwrite the expired record with the updated record. An additional method is described herein for automatically deleting an expired record in a distributed database system comprising a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases. In accordance with the method, a record is read at one of the plurality of nodes. The record is part of a partition stored in the database managed by the one of the plurality of nodes. It is then determined whether the record is expired. Responsive to a determination that the record is expired, it is determined if an incarnation number associated with the partition exceeds an incarnation number stored in the record. Responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record, the record is purged. An additional distributed database system is also described herein. The system includes a plurality of nodes, wherein the nodes are interconnected via a communication system. The system also includes a plurality of databases, wherein each node in the plurality of nodes is configured to manage a respective one of a plurality of databases. Each node in the plurality of nodes is further configured to read a record, wherein the record is part of a partition stored in the database managed by the node, to determine whether the record is expired, to determine if an incarnation number associated with the partition exceeds an incarnation number stored in the record responsive to determining that the record is expired, and to purge the record responsive to determining that the incarnation number associated with the partition exceeds the incarnation number stored in the record. Another method is described herein for determining in a distributed database system which of a first version of a record and a second version of a record is the most recent. In accordance with the method, an incarnation number associated with the first version of the record is compared to an incarnation number associated with the second version of the record. Each incarnation number represents a version of a partition that existed at the time each record was created. Responsive to determining that one of the first version of the record or the second version of the record has a greater incarnation number, the one of the first version of the record or the second version of the record having the greater incarnation number is identified as the most recent. The foregoing method may further include comparing a sequence number associated with the first version of the record and a sequence number associated with the second version of the record responsive to determining that the first version of the record and the second version of the record have the same incarnation number. Then, responsive to determining that one of the first version of the record or the second version of the record has a greater sequence number, the one of the first version of the record or the second version of the record having the greater sequence number is identified as the most recent. Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention. FIG. 1 is a block diagram of an example distributed database system in which an embodiment of the present invention may operate. FIG. 2 depicts a simple example of horizontal partitioning. FIG. 3 depicts a simple example of replication. FIG. 4 illustrates one implementation of a distributed database system in which a node comprises a plurality of servers and in which each server is connected to a corresponding local storage system or device that stores a different partition replica. FIG. 5 shows components of a distributed database system that are involved in updating a record when a client update request is first received by a node that is designated the record master. FIG. 6 shows components of a distributed database system that are involved in updating a record when a client update request is first received by a node that is not designated the record master. FIG. 7 depicts a format of an example database record that includes a composite version number in accordance with an embodiment of the present invention. FIG. 8 illustrates a flowchart of a method for setting and/or updating incarnation and sequence numbers in accordance with an embodiment of the present invention. FIG. 9 illustrates a flowchart of a method by which a node in a distributed database system uses record-level incarnation numbers and sequence numbers to determine which of two versions of the same record is most recent in accordance with an embodiment of the present invention. FIG. 10 depicts steps relating to record expiry that are performed by a node within distributed database system when performing a read operation in accordance with an embodiment of the present invention. FIG. 11 depicts steps relating to record expiry that are performed by a node within a distributed database system when performing a write (or update) operation in accordance with an embodiment of the present invention. FIG. 12 illustrates a flowchart of a garbage collection process implemented by nodes within a distributed database system in accordance with an embodiment of the present invention. FIG. 13 illustrates an example processor-based computer system that may be used to implement the present invention. The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION OF THE INVENTION A. Example Operating Environment FIG. 1 is a high-level block diagram of an example distributed database system 100 in which an embodiment of the present invention may operate. System 100 is described herein by way of example only and is not intended to limit the present invention. Based on the teachings provided herein, persons skilled in the relevant art(s) will understand that the present invention may be implemented in a distributed database system having a different architecture than that of system 100 or in a distributed database system that is configured to function in a different manner than that of system 100. As shown in FIG. 1, distributed database system 100 includes a plurality of nodes 102a, 102b, 102c and 102d. Although only four nodes are shown in FIG. 1, persons skilled in the relevant art(s) will appreciate that, depending on the size and organization of distributed database system 100, the system may include any number of nodes. Nodes 102a, 102b, 102c and 102d are communicatively interconnected via a communication system 106. In the following description, two components of system 100 will be termed “local” with respect to one another if communication between them does not require a transfer of information between any of nodes 102a, 102b, 102c and 102d. Otherwise, the two components will be termed “remote.” In one implementation of distributed database system 100, the nodes are geographically dispersed. However, this need not be the case. Thus, as used herein, the terms “local” and “remote” are not intended to suggest that the nodes must be geographically dispersed. Each node is configured to provide database services to a different plurality of local clients. Thus, for example, node 102a is configured to provide database services to a plurality of local clients 108a, node 102b is configured to provide database services to a plurality of local clients 108b, node 102c is configured to provide database services to a plurality of local clients 108c, and node 102d is configured to provide database services to a plurality of local clients 108d. To provide database services, each node is communicatively connected to a local database. In particular, node 102a is connected to a local database 104a, node 102b is connected to a local database 104b, node 102c is connected to a local database 104c, and node 102d is connected to a local database 104d. Each local database includes a copy of all or a portion of the total database records within distributed database system 100. Thus, copies of the data records of system 100 are distributed across the multiple databases 102a, 102b, 102c and 102d. In distributed database system 100, the database records are divided into partitions and replicas of the partitions are stored in each local database 104a, 104b, 104c and 104d. Although the techniques of partitioning and replicating are well-known to persons skilled in the relevant art(s), a brief description of these techniques as applied to the records of distributed database system 100 will now be provided. As noted above, in distributed database system 100, the database records are divided into partitions. Each partition comprises a distinct and independent portion of the database. Taken together, the partitions constitute a copy of the entire logical database. In distributed database system 100, the manner in which the database records are divided is termed “horizontal partitioning.” In horizontal partitioning, individual rows of a database are placed into different tables, wherein each row represents a database record. This is in contrast to “vertical partitioning,” which involves removing columns (or fields) to obtain tables having fewer columns, and then creating new tables to store the remaining columns. A simple example of horizontal partitioning is illustrated in FIG. 2. As shown in FIG. 2, a database 202 includes a plurality of records, wherein each record comprises a unique key 212 and associated information 214. Key 212 is used to uniquely identify each record and serves as an index for locating each record within database 202. Information 214 represents any type of information that may be stored in a database in association with a key and may comprise, for example, one or more information fields. Through the application of horizontal partitioning, database 202 is split into a first partition 204 and a second partition 206, wherein first partition 204 includes the first five records of database 202 and second partition 206 includes the last five records. Taken together, first partition 204 and second partition 206 comprise a complete logical copy of database 202. Of course, this is just one example of horizontal partitioning. Persons skilled in the relevant art(s) will understand that by using horizontal partitioning, a single database may be divided into any number of partitions, and that partitions may include any number of records. Horizontal partitioning may be used for a variety of reasons. For example, a large database may be rendered more manageable by dividing it into separate partitions. Furthermore, in some systems, different partitions can be assigned to different storage systems or devices to parallelize and improve throughput of network operations. Additionally, partitioning may facilitate load balancing by allowing one or more partitions to be moved from one storage system or device to another. As also noted above, in addition to using partitions, distributed database system 100 also uses replication. In replication, multiple copies or instances of a database or its partitions are created, and the multiple copies are managed by different nodes. Replication can also improve the throughput of network operations. For example, one benefit of replication is that it permits clients at disparate geographic locations to each access a local replica of the same data, thereby increasing the speed and decreasing the expense associated with database accesses by each client. Replication can also be used for load balancing purposes. A simple example of replication is illustrated in FIG. 3. As shown in FIG. 3, a single logical database 302 comprises four horizontal partitions—namely, Partition A, Partition B, Partition C and Partition D. Using replication, the single logical database 302 is copied to generate four logical databases replicas—namely, logical database 304, logical database 306, logical database 308 and logical database 310. Each of the logical database replicas includes a copy of the same partitions included in the original logical database 302. In this example, each of the logical database replicas is used to serve clients in a different geographic region and each replica's partitions are named accordingly. For example, logical database 304 serves clients in a geographic region denoted “north” and its partitions are accordingly named Partition A North, Partition B North, Partition C North and Partition D North. This is just one example of replication. Persons skilled in the relevant art(s) will understand that by using replication, any number of partition replicas may be created. In one implementation of distributed database system 100, each node comprises a plurality of servers, and each of the servers is responsible for managing a different partition replica that is stored on a respective local storage system or device. This is depicted in FIG. 4, which illustrates an implementation of system 100 in which node 102a comprises four servers—namely, server A, server B, server C and server D. Each of these servers is connected to a corresponding local storage system or device which stores a particular partition replica. In particular, as shown in FIG. 4, server A is connected to a local storage system or device that stores local partition A, server B is connected to a local storage system or device that stores local partition B, server C is connected to a local storage system or device that stores local partition C and server D is connected to a local storage system or device that stores local partition D. Taken together, local partitions A, B, C and D may comprise a complete replica or copy of the data records of system 100. Also, taken together, the storage systems or devices used to store these local partitions comprise local database 104a. Because distributed database system 100 stores a separate replica of the same set of partitions in each of local databases 104a, 104b, 104c and 104d, the system is configured to use certain protocols to ensure that changes made to a database record in one partition replica are propagated to copies of the same record that exist in other replicas of the same partition. This is necessary to ensure consistency among the multiple partition replicas. For example, because multiple copies of a single record can exist in different partition replicas, distributed database system 100 is configured to designate only one node a “record master” for each record. The record master always manages the most recent version of the record. Distributed database system 100 is configured to ensure that any update of a record is performed by the record master. The update is then propagated from the record master to all the other nodes using a message broker or other notification system or protocol. By way of illustration, FIG. 5 depicts components of distributed database system 100 that are involved in updating a record when the client update request is first received by the record master. As shown in FIG. 5, a client 502 (which is intended to represent one of the plurality of clients 108a shown in FIG. 1) requests an update by sending a request to node 102a. Because node 102a is the record master, it can immediately perform the update and then send a confirmation message back to client 502. The update can then be propagated from node 102a to the other nodes shown in FIG. 1 for application to other copies of the same record residing in remote databases. This propagation can occur sometime after the initial update has occurred. Consequently, the propagation of the update does not in any way impact the speed with which the initial update occurs. Also, the propagation can be scheduled to occur at a time that least interferes with the operation of distributed database system 100, such as at a time when communication system 106 has more bandwidth than it needs to satisfy pending client requests. Alternatively, node 102a can initiate the propagation of the update to the other nodes shown in FIG. 1 prior to performing the update locally. This approach is beneficial in that it ensures that the update will be published to the other nodes even if node 102a should fail during the performance of the local update. Should node 102a fail, a process is implemented that ensures that node 102a will implement the pending update locally after node 102a is brought back online. In contrast to the example shown in FIG. 5, FIG. 6 illustrates components of distributed database system 100 that are involved in updating a record when the client update request is first received by a node that is not the record master. As shown in FIG. 6, client 502 requests an update by sending a request to node 102a. Because node 102a is not the record master, node 102a must forward the request via communication system 106 to the record master. In this example, the record master is node 104c. Thus, node 102a forwards the request to node 102c. Node 102c performs the update and then sends a confirmation message back to node 102a for forwarding on to client 402. The update is also propagated to the other nodes shown in FIG. 1 for application to other copies of the same record residing in remote databases. Depending upon how distributed database system 100 is configured, in addition to forwarding the request to node 102c and forwarding the confirmation to client 502, node 102a may also need to perform a database operation to determine whether it is, in fact, the record master for the record to be updated. This is because in one implementation of distributed database system 100, whether a node is a record master for a particular record is designated by an indicator that is stored within the record itself. This is illustrated in example database record 700 of FIG. 7, which includes a record master indicator 706. After determining that it is not the record master, node 102a may also need to engage in communication with each of nodes 102b, 102c and 102d to determine which one of those nodes is the record master. As can be seen from FIG. 5 and FIG. 6, then, performing an update when the record master first receives the update request consumes less time and system resources than when a node that is not the record master first receives the update request. Thus, distributed database system 100 is configured to designate a node as a record master for a record if the record in question is deemed most likely to be updated by clients that are local with respect to the node. The manner in which distributed database system 100 performs this designation is beyond the scope of this application and therefore will not be described further herein. In distributed database system 100, insertions and deletions may be thought of as special kinds of updates. As will be described in more detail herein, in one mode of operation, an insertion request must be forwarded to a node that is designated the partition master and the partition master inserts the record if it is determined that no other record exists that has the same key. As will also be described in more detail herein, deletions are performed using a multi-step process. First the record master hides but does not delete the relevant record. Then, the deletion request is forwarded to a partition master. The partition master deletes the local copy of the relevant record and then publishes both the deletion and a new incarnation number to the remote nodes. Only then does the record master purge the relevant record. In contrast to a client request to update a record, which must always be performed by the record master, requests to read a record need not always be performed by the record master. In other words, distributed database system 100 allows read requests to be satisfied by nodes that are not the record master by accessing a record stored in a local database, even if that record is not the most recent copy of that record. This allows distributed database system 100 to optionally present out-of-date data to a user in the interest of decreasing transaction time and conserving system resources. B. Use of Version Numbers in Accordance with an Embodiment of the Present Invention In distributed database system 100, each insertion, deletion or update of a record may be thought of as producing a new “logical version” of the record. The term “logical” is used in this context because distributed database system 100 is not configured to actually maintain a copy of each version of the record, but rather is configured to maintain only the most recent version. The term “logical” is also used in this context because a deleted record may be considered to be another version of a record even though the record no longer exists after the deletion. Certain operations performed by database management system 100 require the system to determine which version of a particular record is the most recent. For example, if a series of updates are performed on a record by the record master, a remote node may subsequently receive multiple versions of the record propagated from the record master. The versions may not necessarily be received in an order that corresponds to the order in which the updates were performed by the record master. For example, if communication system 106 is a packet network, network latency may cause one version of the record representing a more recent update to arrive before another version of the record representing an older update. To deal with this, the node receiving the multiple versions of the record must be capable of determining which version is truly the most recent. In order to make this determination, distributed database system 100 maintains a version number in association with each database record. The version number is stored as a part of each record. In accordance with an embodiment of the present invention, the version number comprises two components: a record-level incarnation number, which is a copy of a partition-level incarnation number that is incremented whenever a record in a partition is deleted (and possibly more frequently), and a record-level sequence number, which is incremented whenever a record is updated. As will be described in more detail below, the composite nature of the version number allows distributed database system 100 to properly sequence different versions of a given record. FIG. 7 depicts a format 700 of an example database record that includes a version number in accordance with an embodiment of the present invention. As shown in FIG. 7, in addition to a key 702, a record master indicator 706, and information fields 708, the database record also includes a version number 704, which consists of a record-level incarnation number 710 and a sequence number 712. As noted above, in distributed database system 100, a partition-level incarnation number is maintained. This means that each node is configured to maintain an incarnation number for each locally-stored database partition. However, because distributed database system 100 stores multiple replicas of each partition, the system is also configured to designate only one of the nodes a “partition master.” The partition master is the node that that stores the only authoritative copy of the current partition-level incarnation number for a given partition. All other nodes must obtain their partition-level incarnation number for that partition from the partition master. Furthermore, as will be described in more detail below, all deletions performed by a record master must be reported to the partition master and all insertions performed by a record master must be performed, in part, by obtaining a partition-level incarnation number from the partition master. FIG. 8 illustrates a flowchart 800 of a method for setting and/or updating incarnation and sequence numbers in accordance with an embodiment of the present invention. In particular, flowchart 800 depicts a method by which an embodiment of the present invention sets and/or updates partition-level incarnation numbers as well as record-level incarnation numbers and sequence numbers. In one embodiment, the method of flowchart 800 is performed by each node in distributed database system 100 whenever the node performs a database operation upon a record for which the node is the designated record master. Generally speaking, database operations that are performed by a node upon a record for which the node is not designated record master will not cause a modification of a partition-level incarnation number, a record-level incarnation number, or a sequence number. As shown in FIG. 8, the method of flowchart 800 begins at step 802, in which the type of database operation that has been performed by the record master is determined. As shown at decision step 804, if the database operation is an update, then the sequence number associated with the record is increased as shown at step 810. This increased sequence number will then be reflected in all updates propagated from the record master to other nodes for updating remotely-stored copies of the same record. After step 810, processing ends as shown at step 812. If the database operation is not an update, then processing proceeds from decision step 804 to decision step 806. As shown at decision step 806, if the database operation is a delete, then the partition-level incarnation number maintained by the partition master is increased as shown at step 814. If the node at which the delete occurred is the partition master, then this operation can be handled locally. However, if the node at which the delete occurred is not the partition master, then this operation must be performed by a remote node. As shown at step 816, after the incarnation number is increased in step 814, the deletion and the updated incarnation number are then published to all remote nodes. Each remote node then purges the relevant record and also updates its own partition-level incarnation number to match the updated authoritative version of the partition-level incarnation number from the partition master. After step 816, processing ends as shown at step 812. If the database operation is not a delete, then processing proceeds from decision step 806 to decision step 808. As shown at decision step 808, if the database operation is an insert, then the partition-level incarnation number is obtained from the partition master as shown at step 818. If the node at which the insert occurred is the partition master, then this operation can be handled locally. However, if the node at which the insert occurred is not the partition master, then this operation must be performed by a remote node. At shown at step 820, if the partition master is a remote node, then the node at which the insert occurred updates its own partition-level incarnation number to match the obtained authoritative version of the partition-level incarnation number from the partition master. At step 822, the node at which the insert occurred sets the record-level incarnation number of the newly-inserted record to match the obtained authoritative version of the partition-level incarnation number from the partition master. At step 824, the node at which the insert occurred sets the sequence number of the newly-inserted record to an initial value, which in one embodiment is the lowest value that can be held by the sequence number. If at decision step 808 it is determined that the database operation is not an insert, then processing ends as shown at step 812. FIG. 9 illustrates a flowchart 900 of a method by which a node in distributed database system 100 uses record-level incarnation numbers and sequence numbers to determine which of two versions of the same record is most recent. The method of flowchart 900 may be used by a node, for example, when it receives two different versions of the same record from a remote record master following the performance of a series of updates to the record by the record master. As shown in FIG. 9, the method of flowchart 900 begins at step 902 in which the node compares the two record-level incarnation numbers respectively associated with the two version of the record. At decision step 904, it is then determined whether the record-level incarnation numbers compared in step 902 are the same. If they are not the same, then as shown in step 906 the version of the record with the larger record-level incarnation number is deemed the most recent and processing ends at step 922. However, if it is determined at decision step 904 that the record-level incarnation numbers compared in step 902 are the same, then processing proceeds to step 908, in which the node compares the two sequence numbers respectively associated with the two versions of the record. At decision step 910, it is then determined whether the sequence numbers compared in step 908 are the same. If they are not the same, then as shown in step 912 the version of the record with the larger sequence number is deemed the most recent and processing ends at step 922. However, if it is determined at decision step 910 that the sequence numbers compared in step 908 are the same, then processing proceeds to step 914, in which the node compares the contents of each version of the record. At decision step 916, it is then determined whether the contents of each version of the record are the same. If the contents are the same, then the versions are identical and either can be deemed the most recent as shown at step 920. Also, during this step, a warning is automatically logged. If the contents are not the same, then two different versions of the same record have the same version number. In this case, the version of the record received first by the node is deemed the most recent and the version received second is rejected as shown at step 918. Also, during this step, a critical error is automatically logged that invites or requires human attention. After the execution of either step 918 or 920, processing ends at step 922. As can be seen from the foregoing description, distributed database system 100 maintains and uses incarnation numbers and sequence numbers to sequence different versions of the same record. If the system used only a sequence number to perform this function, then a problem might result when a record was deleted and then a record with the same key was inserted. The deletion of the record would cause the sequence number associated with the record to be lost. As a result, if a record having the same key was inserted, there would be no way to ensure that the sequence number associated with the newly-inserted record was distinct from other versions of the deleted record that might still reside in one or more storage locations in distributed database system 100. The method of flowchart 800 addresses this issue by assigning a version number to the newly-inserted record that is distinct from any version number associated with a previous version of the record. In particular, by incrementing the incarnation number of a partition on any delete from the partition, and then setting the record-level incarnation number of the newly-inserted record equal to the incremented partition-level incarnation number, the method of flowchart 800 ensures that if a record is deleted and then a record with the same key is inserted, the newly-inserted record will have a distinct version number as compared to the deleted record. This is because the incarnation number portion of the version number will by necessity be distinct. This approach is superior to that used by conventional distributed database systems that maintain “tombstone” records to address the same problem. As will be appreciated by persons skilled in the relevant art(s), in such conventional systems, after deletion of a record, a stub record is maintained to represent the deleted record, wherein the stub record includes a version number associated with the deleted record. The creation, maintenance and expiration of such tombstone records add a significant amount of complexity and expense to the distributed database system. An embodiment of the present invention avoids the use of such tombstone records by essentially aggregating the same information into a partition-level incarnation number. However, maintaining the partition-level incarnation number can still require an expensive operation. As shown above in flowchart 800 of FIG. 8, all insert and delete operations performed by a record master require accessing the partition master. If the record master is not also the partition master, then this operation must be performed by a remote node. This remote access is costly in terms of the time and bandwidth. For distributed database systems with large partitions, it is virtually impossible to ensure that the record master and the partition master will always be the same node. Therefore, in such systems, there is a reasonable likelihood that a record deletion or insertion will require the performance of this expensive operation. C. Decentralized Record Expiry in Accordance with an Embodiment of the Present Invention As used herein the term “record expiry” refers to a system-initiated deletion of a database record. Database records may be set to expire for any number of reasons. For example, the value or relevance of some information decreases over time. Additionally, expiry may be used to remove older data from a system to free up resources to make room for newer data. In distributed database system 100, expiry is logically a delete, with the only difference being that it is initiated by the system rather than by a client. Thus, when a record expires, the record master must ensure that the incarnation number maintained at the partition master is increased. One straightforward way to implement an expiration in distributed database system 100 is for each node to determine when a record for which it is designated record master has expired and to perform the following steps responsive to determining that the record has expired: (1) stop accepting updates to the record, (2) access the partition master to increment the partition-level incarnation number, and then (3) purge the record. However, this solution is expensive for at least two reasons. First, it requires a mechanism that triggers an alert to the record master when the record has expired. Second, in any case where the record master is not also the partition master, the solution requires a remote access to the partition master, which as described above, can be expensive. In a large-scale distributed database system with millions or billions of records, the necessary logic for implementing the trigger and the bandwidth cost for remote accesses to the partition master can be prohibitive. An embodiment of the present invention utilizes a different approach. In accordance with this embodiment, database records are not actively expired. Rather, a record is checked to see if it has expired only when it has been accessed for a read or a write. If at the time of a read a record is determined to have expired, then distributed database system 100 does not serve it, instead acting as if it had been deleted. If at the time of a write a record is determined to have expired, then the write is treated as an insertion of a new record, and steps are taken to treat the insertion consistently with regard to the previous expired version. This approach to expiry will now be more fully described in reference to flowchart 1000 of FIG. 10 and flowchart 1100 of FIG. 11. In particular, flowchart 1000 of FIG. 10 depicts steps that are performed by a node within distributed database system 100 when performing a read operation while flowchart 1100 of FIG. 11 depicts steps that are performed by a node within distributed database system when performing a write (or update) operation. As shown in FIG. 10, the method of flowchart 1000 begins at step 1002, in which a client request to read a record is received. At decision step 1004, a determination is made as to whether the requested record has expired. Determining whether the record has expired may involve determining whether an expiration period associated with the record has passed or whether a current date and/or time is later than an expiration date and/or time associated with the record. However, these examples are not intended to be limiting and other methods may be used to determine whether the record has expired as will be appreciated by persons skilled in the relevant art(s). If the record has not expired, then the read request is handled in a normal fashion as shown at step 1006. However, if the record has expired, then the record is not served to the client. Thus, the read request is effectively treating as if the record has been deleted. This is shown at step 1008. After the performance of either step 1006 or step 1008, processing ends as shown at step 1010. As shown in FIG. 11, the method of flowchart 1100 begins at step 1102, in which a client request to write a record is received by the record master. As noted above, all write requests are handled by the record master. At step 1104, a determination is made as to whether the requested record has expired. As noted above, determining whether the record has expired may involve determining whether an expiration period associated with the record has passed or whether a current date and/or time is later than an expiration date and/or time associated with the record. However, these examples are not intended to be limiting and other methods may be used to determine whether the record has expired as will be appreciated by persons skilled in the relevant art(s). If the record has not expired, then the write request is handled in a normal fashion as shown at step 1118 and then processing ends as shown at step 1120. However, if the record has expired, then the write is treated as an insertion of a new record, and steps are taken to treat the insertion consistently with regard to the previous expired version. These steps begin with decision step 1106. At decision step 1106, the record master determines whether the local partition-level incarnation number has advanced beyond the incarnation number in the expired record. If it has not (i.e., if the local partition-level incarnation number is less than or equal to the incarnation number in the expired record), then the record master first initiates a normal delete of the expired record as shown at step 1108. As described above in reference to flowchart 800 of FIG. 8, this deletion requires accessing the partition master to update the authoritative partition-level incarnation number. After step 1108, the record master next initiates a normal insertion of the updated record as shown at step 1110. As also described above in reference to flowchart 800 of FIG. 8, this insertion requires accessing the partition master to obtain the authoritative partition-level incarnation number. The performance of these steps ensures that the inserted record will have a distinct version number from the expired record, as described in detail above. However, if the record master is not also the partition master, than a costly remote access must be performed to carry out each of these steps. After the performance of step 1110, processing ends as shown at step 1120. If, however, at decision step 1106, the record master determines that the local partition-level incarnation number has advanced beyond the incarnation number in the expired record (i.e., if the local partition-level incarnation number is greater than the incarnation number in the expired record), then the record master locally generates a new version number for the updated version of the record in the manner shown at step 1112. In particular, the new version number is created by combining the local partition-level incarnation number with a sequence number, wherein the sequence number is set to an initial value. In one embodiment the initial value is the lowest value that can be held by the sequence number. This value may be, for example, zero. Then, at step 1114, the record master overwrites the expired version of the record with the updated version of the record. At step 1116, the record master propagates this change to other nodes using a message broker or other notification system or protocol. After step 1116, processing ends as shown at step 1120. Note that due to the publication of increments to the authoritative version of the partition-level incarnation number by the partition master (as described above in reference to step 816 of FIG. 8), the local partition-level incarnation number should never be less than the incarnation number in the expired record. Thus, the detection of such a condition during step 1106 would indicate a programming error or some other error condition within system 100. Performing steps 1112, 1114 and 1116 as described above avoids the remote accesses to the partition master that need to be performed during steps 1108 and 1110 in cases where the record master is not the partition master. These remote accesses can be avoided because the test implemented by decision step 1106 ensures that the version number generated locally for the updated record in step 1112 will be distinct from the version number associated with the expired record. Note than in some cases the local partition-level incarnation number may be less than the authoritative partition-level incarnation number maintained by the partition master. However, this is not a problem so long as the local partition-level incarnation number exceeds the record-level incarnation number in the version number of the expired record. In a distributed database in which each partition includes a very large number of records, it is highly likely that the local partition-level incarnation number will exceed the record-level incarnation number in the version number of the expired record. This is because it is highly likely that at least one other record in the partition will have been recently deleted or expired, thereby causing the local partition-level incarnation number to increase beyond the record-level incarnation number. Thus, it is anticipated that in a distributed database system with large partitions, expiration upon writes can be handled using steps 1112, 1114 and 1116 (which avoid remote accesses) rather than steps 1108 and 1110 (which may require remote accesses) in the vast majority of cases. In distributed database system 100, some records may expire but never be written to or actively deleted by a client after expiration. Consequently, in an embodiment of the present invention, each node implements a “garbage collection” process that augments the previously-described processes. Each node runs the garbage collection process periodically and in the background to reclaim storage space. For efficiency, the process may be run only when utilization of node resources for servicing client requests is low. As will be described in more detail below, the garbage collection process iterates over all locally-stored records. If a record is expired and the node is the record master, expiry is initiated in a like manner to that described in steps 1114 and 1116 of FIG. 11, except that purging replaces the overwriting in step 1114. The partition master only needs to be contacted if the local partition-level incarnation number has not advanced beyond that in the expired record's version number. FIG. 12 provides a flowchart 1200 of such a process. As shown in FIG. 12, the method of flowchart 1200 begins at step 1202, in which the node reads a record from its local database. At decision step 1204, the node determines if it is the record master for that record. If the node is not the record master, then control flows to decision step 1216. At decision step 1216, the node determines if there are any more records in the local database. If there are more records in the local database, then control returns to step 1202 and the next record is read from the local database. If there are no more records in the local database, then the process ends as shown at step 1218. If, at decision step 1204, the node determines that it is the record master for the record that was read in step 1202, then control flows to decision step 1206. At decision step 1206, the node determines whether the record that was read in step 1202 has expired. As noted above, determining whether the record has expired may involve determining whether an expiration period associated with the record has passed or whether a current date and/or time is later than an expiration date and/or time associated with the record. However, these examples are not intended to be limiting and other methods may be used to determine whether the record has expired as will be appreciated by persons skilled in the relevant art(s). If the record has not expired, then control flows to decision step 1216, in which the node determines if there are any more records in the local database. If there are more records in the local database, then control returns to step 1202 and the next record is read from the local database. If there are no more records in the local database, then the process ends as shown at step 1218. If it is determined at decision step 1206 that the record that was read in step 1202 has expired, then control flows to decision step 1208. At decision step 1208, the node determines whether the local partition-level incarnation number has advanced beyond the incarnation number in the expired record. If it has not (i.e., if the local partition-level incarnation number is less than or equal to the incarnation number in the expired record), then the node initiates a normal delete of the expired record as shown at step 1210. As described above in reference to flowchart 800 of FIG. 8, this deletion requires accessing the partition master to update the authoritative partition-level incarnation number. However, if the node performing the garbage collection process is not also the partition master, than a costly remote access must be performed to carry out this step. After the performance of step 1210, control flows to decision step 1216, in which the node determines if there are any more records in the local database. If there are more records in the local database, then control returns to step 1202 and the next record is read from the local database. If there are no more records in the local database, then the process ends as shown at step 1218. If it is determined at decision step 1208 that the local partition-level incarnation number has advanced beyond the incarnation number in the expired record (i.e., if the local partition-level incarnation number is greater than the incarnation number in the expired record), then the node purges the expired record as shown at step 1212. No contact with the partition master need be made. At step 1214, the node propagates this change to other nodes using a message broker or other notification system or protocol. After step 1214, control flows to decision step 1216, in which the node determines if there are any more records in the local database. If there are more records in the local database, then control returns to step 1202 and the next record is read from the local database. If there are no more records in the local database, then the process ends as shown at step 1218. Performing steps 1212 and 1214 as described above avoids the remote access to the partition master that needs to be performed during step 1210 in cases where the record master is not the partition master. The remote access can be avoided because the test implemented by decision step 1208 ensures that any record inserted after the purging of the expired record that has the same key as the expired record will be assigned a version number that is distinct from the version number associated with the expired record. As noted above, in a distributed database in which each partition includes a very large number of records, it is highly likely that the local partition-level incarnation number will exceed the record-level incarnation number in the version number of the expired record. This is because it is highly likely that at least one other record in the partition will have been recently deleted or expired, thereby causing the local partition-level incarnation number to increase beyond the record-level incarnation number. Thus, it is anticipated that in a distributed database system with large partitions, expiry based on a garbage collection process can be handled using steps 1212 and 1214 (which avoid remote accesses) rather than step 1210 (which may require a remote access) in the vast majority of cases. It should be noted that in an alternate embodiment, the garbage collection process can use a normal delete (as described above in reference to step 1210) to delete expired records in every case. Although this is less optimal than the method described above in reference to flowchart 1200 in terms of conserving time and system bandwidth, it is a simpler approach and may be deemed acceptable in some cases. For example, since the garbage collection process is run in the background instead of as a part of a client-initiated process, it may be that a certain amount of latency is tolerable. Also, since the garbage collection process may be run during periods of time when system resource utilization is low, it may also be that a certain amount of extra resource consumption is tolerable. D. Example Computer System Implementation Many of the elements of distributed database system 100 as well as many of the steps of flowcharts 800, 900, 1000, 1100 and 1200 may be implemented using any well-known processor-based computer system. An example of such a computer system 1300 is depicted in FIG. 13. As shown in FIG. 13, computer system 1300 includes a processing unit 1304 that includes one or more processors. Processor unit 1304 is connected to a communication infrastructure 1302, which may comprise, for example, a bus or a network. Computer system 1300 also includes a main memory 1306, preferably random access memory (RAM), and may also include a secondary memory 1320. Secondary memory 1320 may include, for example, a hard disk drive 1322, a removable storage drive 1324, and/or a memory stick. Removable storage drive 1324 may comprise a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. Removable storage drive 1324 reads from and/or writes to a removable storage unit 1328 in a well-known manner. Removable storage unit 1328 may comprise a floppy disk, magnetic tape, optical disk, or the like, which is read by and written to by removable storage drive 1324. As will be appreciated by persons skilled in the relevant art(s), removable storage unit 1328 includes a computer usable storage medium having stored therein computer software and/or data. In alternative implementations, secondary memory 1320 may include other similar means for allowing computer programs or other instructions to be loaded into computer system 1300. Such means may include, for example, a removable storage unit 1330 and an interface 1326. Examples of such means may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units 1330 and interfaces 1326 which allow software and data to be transferred from the removable storage unit 1330 to computer system 1300. Computer system 1300 may also include a communications interface 1340. Communications interface 1340 allows software and data to be transferred between computer system 1300 and external devices. Examples of communications interface 1340 may include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface 1340 are in the form of signals which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 1340. These signals are provided to communications interface 1340 via a communications path 1342. Communications path 1342 carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link and other communications channels. As used herein, the terms “computer program medium” and “computer usable medium” are used to generally refer to media such as removable storage unit 1328, removable storage unit 1330, a hard disk installed in hard disk drive 1322, and signals received by communications interface 1340. Computer program medium and computer useable medium can also refer to memories, such as main memory 1306 and secondary memory 1320, which can be semiconductor devices (e.g., DRAMs, etc.). These computer program products are means for providing software to computer system 1300. Computer programs (also called computer control logic, programming logic, or logic) are stored in main memory 1306 and/or secondary memory 1320. Computer programs may also be received via communications interface 1340. Such computer programs, when executed, enable the computer system 1300 to implement features of the present invention as discussed herein. Accordingly, such computer programs represent controllers of the computer system 1300. Where the invention is implemented using software, the software may be stored in a computer program product and loaded into computer system 1300 using removable storage drive 1324, interface 1326, or communications interface 1340. The invention is also directed to computer program products comprising software stored on any computer useable medium. Such software, when executed in one or more data processing devices, causes a data processing device(s) to operate as described herein. Embodiments of the present invention employ any computer useable or readable medium, known now or in the future. Examples of computer useable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, zip disks, tapes, magnetic storage devices, optical storage devices, MEMs, nanotechnology-based storage device, etc.), and communication mediums (e.g., wired and wireless communication networks, local area networks, wide area networks, intranets, etc.). E. Conclusion While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be understood by those skilled in the relevant art(s) that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. Accordingly, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.	G	60G06	161G06F	17	30
11856832	US20080072254A1-20080320	DIGITAL VIDEO BROADCASTING SYSTEM, DIGITAL VIDEO BROADCASTING TERMINAL, AND METHOD FOR PROVIDING FILE INFORMATION IN FILE DOWNLOAD SERVICE	ACCEPTED	20080305	20080320	[]	G06F300	["G06F300"]	8316397	20070918	20121120	725	039000	98253.0	FEATHERSTONE	MARK	[{"inventor_name_last": "Jung", "inventor_name_first": "Ji-Wuck", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Kim", "inventor_name_first": "Young-Jip", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Jeon", "inventor_name_first": "Jin-Woo", "inventor_city": "Seongnam-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Song", "inventor_name_first": "Jae-Yeon", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}]	A digital video broadcasting system, digital video broadcasting terminal, and method for providing file information in a file download service are provided. To this end, the digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that provide the file download service comprise a file set generated by grouping at least one file, the schedule event fragment comprises the information about files included in the file set, and a terminal for receiving the ESG, for evaluating the schedule event fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating the information about the files included in the file set and displaying the information if the schedule event fragment comprises the information about the file set.	1. A digital broadcasting system for providing file information in a file download service using broadcasting information, the digital broadcasting system comprising: a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that provide the file download service comprise a file set generated by grouping at least one file, the schedule event fragment comprises information about files included in the file set; and a terminal for receiving the ESG, for evaluating the schedule event fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating the information about the files included in the file set and displaying the information if the schedule event fragment comprises the information about the file set. 2. The digital broadcasting system of claim 1, wherein the broadcasting server incorporates at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into a content location element of the schedule event fragment if the files that provide the file download service comprise the file set. 3. The digital broadcasting system of claim 2, wherein if the files that provide the file download service comprise a single file that is transmitted as a single file unit, the broadcasting server sets an encoding type value included in the content URI type element as a value for indicating that the files that provide the file download service comprise the single file. 4. The digital broadcasting system of claim 2, wherein the terminal determines if the schedule event fragment comprises the information about the file set by evaluating encoding type information included in the content location element. 5. The digital broadcasting system of claim 4, wherein if the terminal determines that the information about the file set is included in the received ESG, it evaluates file list information corresponding to each of the files included in the information about the file set through the content list type element. 6. The digital broadcasting system of claim 1, wherein the broadcasting server incorporates information about a single file into a content location element of the schedule event fragment if the files that provide the file download service comprise the single file, and incorporates at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into an archive location element of the schedule event fragment if the files that provide the file download service comprise the file set. 7. The digital broadcasting system of claim 6, wherein the terminal determines if the information about the file set is included in the received ESG by evaluating the archive location element. 8. The digital broadcasting system of claim 7, wherein if the files that provide the file download service comprise the file set, the terminal evaluates file list information corresponding to each of the files included in the information about the file set through the content list type element. 9. A digital broadcasting system for providing file information in a file download service using broadcasting information, the digital broadcasting system comprising: a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that provide the file download service comprise information about a file set generated by grouping at least one file, the content fragment comprises information about files included in the file set; and a terminal for receiving the ESG, for evaluating the content fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating the information about the files included in the file set and displaying the information if the content fragment comprises the file set. 10. The digital broadcasting system of claim 9, wherein the broadcasting server incorporates at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into an archive location element of the content fragment if the files that provide the file download service comprise a file set. 11. The digital broadcasting system of claim 10, wherein the terminal determines if the content fragment comprises the information about the file set by evaluating the archive location element of the content fragment. 12. The digital broadcasting system of claim 11, wherein if the terminal determines that the files that provide the file download service comprise the information about the file set, it evaluates file list information corresponding to each of the files included in the information about the file set through the content list type element. 13. A method for providing file information in a file download service using broadcasting information, the method comprising: transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that provide the file download service comprise information about a file set generated by grouping at least one file, the schedule event fragment comprises information about files included in the file set; receiving, by a terminal, the ESG; determining, by the terminal, if a request for downloadable file information is input; determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the schedule event fragment if the request for the downloadable file information is input; and evaluating, by the terminal, the information about the files included in the file set and displaying the information if the schedule event fragment comprises the file set. 14. The method of claim 13, wherein the transmitting by the broadcasting server of the ESG comprises: if the files that provide the file download service comprise the information about the file set, generating, by the broadcasting server, the ESG by incorporating at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into a content location element of the schedule event fragment; and transmitting, by the broadcasting server, the generated ESG. 15. The method of claim 14, wherein the generating by the broadcasting server of the ESG comprises setting, by the broadcasting server, an encoding type value included in the content URI type element as a value for indicating that the files that provide the file download service comprise a single file that is transmitted as a single file unit if the files that provide the file download service comprise the single file. 16. The method of claim 14, wherein the determining by the terminal if the schedule event fragment comprises the information about the file set comprises determining if the schedule event fragment comprises the information about the file set by evaluating encoding type information included in the content location element of the schedule event fragment included in the received ESG. 17. The method of claim 13, wherein the transmitting by the broadcasting server of the ESG comprises: if the files that provide the file download service comprise the information about the file set, generating, by the broadcasting server, the ESG by incorporating single file information into a content location element of the schedule event fragment and incorporating at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into an archive location element of the schedule event fragment; and transmitting, by the broadcasting server, the generated ESG. 18. The method of claim 17, wherein the determining, by the terminal, if the content fragment comprises the information about the file set comprises determining, by the terminal, if the files that provide the file download service comprise the file set, by evaluating the archive location element. 19. The method of claim 16, wherein the evaluating, by the terminal, of the information about the files included in the file set and the displaying of the information comprises, if the received file is the file set, evaluating file list information of the files included in the file set through the content list type element; and displaying the file list information in a position corresponding to the file set on a screen. 20. A method for providing file information in a file download service using broadcasting information, the method comprising: transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that provide the file download service comprise information about a file set generated by grouping at least one file, the content fragment comprises information about files included in the file set; receiving, by a terminal, the ESG and determining, by the terminal, if a request for downloadable file information is input; determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the content fragment if the request for the downloadable file information is input; and evaluating, by the terminal, the information about the files included in the file set and displaying the information if the content fragment comprises the file set. 21. The method of claim 20, wherein the transmitting by the broadcasting server of the ESG comprises: if the files that provide the file download service comprise the information about the file set, generating, by the broadcasting server, the ESG by incorporating at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set into an archive location element of the content fragment; and transmitting, by the broadcasting server, the generated ESG. 22. The method of claim 20, wherein the determining by the terminal if the content fragment comprises the information about the file set comprises determining, by the terminal, if the files that provide the file download service comprise the file set by evaluating the archive location element of the content fragment. 23. The method of claim 20, wherein the evaluating by the terminal of the information about the files included in the file set and the displaying of the information comprises displaying file list information corresponding to each of the files included in the file set through the content list type element if the content fragment comprises the file set. 24. A terminal for providing file information of files in a file download service using broadcasting information, the terminal comprising: a receiver for receiving an Electronic Service Guide (ESG); a memory unit for storing the received ESG; a display unit for displaying input data; and a controller for evaluating a schedule event fragment of the received ESG to determine whether the ESG comprises information about a file set, for evaluating information about files included in the file set if the ESG comprises the information about the file set, and for displaying the information through the display unit. 25. The terminal of claim 24, wherein a content location element of the schedule event fragment comprises at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set. 26. The terminal of claim 25, wherein the controller determines if the files that provide the file download service comprise the information about the file set by evaluating encoding type information included in the content location element. 27. The terminal of claim 26, wherein if the files that provide the file download service comprise information about the file set, the controller evaluates file list information corresponding to the files included in the file set through the content list type element of the schedule event fragment. 28. The terminal of claim 24, wherein a content location element of the schedule event fragment comprises information about a single file and an archive location element of the schedule event fragment comprises at least one of a content Uniform Resource Identifier (URI) type element comprising information about an encoding type used to group the files included in the file set and a content list type element comprising file list information corresponding to the file set. 29. The terminal of claim 28, wherein the controller determines if the files that provide the file download service comprise the information about the file set by evaluating the archive location element. 30. The terminal of claim 29, wherein the controller evaluates file list information corresponding to each of the files included in the file set through the content list type element if the files that provide the file download service comprise information about the file set. 31. The terminal of claim 27, wherein if the files that provide the file download service comprise information about the file set, the controller evaluates file list information corresponding to each of the files included in the file set through the content list type element and displays the file list information in a position corresponding to the file set on a screen.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an apparatus and method for a digital video broadcasting system. More particularly, the present invention relates to a digital video broadcasting system, digital video broadcasting terminal, and method for providing information about downloadable files using an Electronic Service Guide (ESG) in a file download service. 2. Description of the Related Art Generally, in a digital broadcasting system, a broadcasting signal, which has been conventionally transmitted in an analog manner, is transmitted in a digital manner. A broadcasting signal transmitted in a digital manner provides superior quality and provides various services for both video and audio. Digital broadcasting is classified as Digital Video Broadcasting (DVB), Digital Audio Broadcasting (DAB), Digital Multimedia Broadcasting (DMB), MediaFLO, and the like. DVB is a European digital broadcasting standard and can be classified into various forms according to its nature, such as DVB-Terrestrial (DVB-T), DVB-Satellite (DVB-S), and DVB-Handheld (DVB-H). DVB-T is a standard for terrestrial digital broadcasting, DVB-S is a standard for satellite digital broadcasting, and DVB-H is a standard for portable mobile digital broadcasting. DVB-H is a technology standard established for the transmission of digital signals to handheld devices such as mobile terminals and the like. DVB-H provides excellent reception of terrestrial digital broadcasting to handheld devices (i.e. mobile terminals). Moreover, it can be used to implement digital mobile multimedia broadcasting to provide high-quality video and audio content to users anytime and anywhere, for example while driving or walking. Unlike other digital broadcasting standards, DVB-H transmits important information required for a broadcasting service through Electronic Service Guide (ESG) data. DVB-H uses a File Delivery over Unidirectional Transport (FLUTE) protocol as a Content Delivery Protocol (CDP). The FLUTE protocol allows transmission of files such as text, audio, video and image files. As part of its standard, DVB-H uses the FLUTE protocol to download files required for ESG configuration and ESG update. DVB-H provides video broadcasting and audio broadcasting as fundamental broadcasting services. In addition, DVB-H provides a data broadcasting service. In other words, three types of services, i.e., video service, audio service and data service, can be provided by the DVB-H standard. Information about each of the three services is transmitted through ESG information. A terminal, for example a handheld device, receiving a DVB-H broadcasting signal, analyzes ESG information included in the broadcasting signal in order to recognize the type of service transmitted through the broadcasting signal and service related information. The ESG information includes Extensible Markup Language (XML) data, and the format of ESG XML information is defined using an XML scheme in the standard. DVB-H broadcasting information is transmitted as ESG fragment information. An ESG fragment can be classified into various types according to the information included in the ESG fragment. ESG data defined in the DVB-H service includes 7 fragments, i.e., a service bundle fragment, a purchase fragment, a purchase channel fragment, a service fragment, a schedule event fragment, a content fragment, and an acquisition fragment. The terminal collects these fragments together in order to recognize all of the information contained in the DVB-H broadcasting signal. A DVB-H broadcasting service includes a data broadcasting service. A data broadcasting service is a file download service that involves downloading a particular data file transmitted through a broadcasting signal. In the file download service, file data required for a service, such as an HTML page, Audio/Video (AV) files, and ring tones, in addition to a streaming service, is transmitted using the FLUTE protocol. In order to acquire file data used for a particular period of time, a FLUTE session is initiated using Session Description Protocol (SDP) information of the ESG data and the desired file data is transmitted. In the file download service, information required for the file download service is transmitted using the service fragment, the schedule event fragment, the content fragment, and the acquisition fragment of the ESG data. FIGS. 4A and 4B illustrate an ESG for a DVB-H file download service. Uniform Resource Identifier (URI) information for each transmission file is transmitted through a schedule event fragment. It can be seen from FIGS. 4A and 4B that a download service for three ring tone MP3 files, i.e., a Ring Tone 1 , a Ring Tone 2 , and a Ring Tone 100 , is provided. More specifically, it can be seen from FIGS. 4A and 4B that URI information for each MP3 file is transmitted through a content location element of the schedule event fragment. As can be seen from FIGS. 4A and 4B , information required to provide the download service for the three MP3 files is transmitted through the content fragment, the service fragment, the schedule event fragment, and the acquisition fragment. FIG. 5 illustrates the syntax of a general ESG schedule event fragment. Referring to FIG. 5 , a content location element 500 of the schedule event fragment has information about the type of any URI and can indicate URI information of a single service file. As such, when the current DVB-H system provides file information for a download service using an ESG, it can provide information about a download service for a single file as illustrated in FIGS. 4A and 4B . However, when several individual files are grouped together for download in the file download service, there is no way to provide information about each of the several files included in the grouped file. As a result, when a set of several files is provided in a file download service, information about each of the several files included in the set may not be provided. For example, when a service provider offers 10 ring tone MP3 files, grouped together as a single file, to a user for purchase, the user may desire to evaluate information about each of the 10 ring tone MP3 files, i.e., a file list, before paying for and downloading the 10 ring tone MP3 files. However, according to the current DVB-H Convergence of Broadcast and Mobile Services (CBMS) ESG standard, when a terminal is provided with several files grouped as a single file, there is no way to provide information about each of the individual files of the grouped file, thus resulting in a failure to provide sufficient information to the user.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an object of the present invention is to provide a digital video broadcasting system, terminal, and method for providing information about a plurality of files grouped as a single file through an ESG. According to one aspect of the present invention, a digital broadcasting system for providing file information in a file download service using broadcasting information is provided. The digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that are included in the file download service comprise a file set that is generated by grouping a plurality of files, the schedule event fragment comprises information about the plurality of files included in the file set, and a terminal for receiving the ESG, for evaluating the schedule event fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating and displaying the information about the plurality of files included in the file set if the schedule event fragment comprises the information about the file set. According to another aspect of the present invention, a digital broadcasting system for providing file information in a file download service using broadcasting information is provided. The digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the content fragment comprises information about the plurality of files included in the file set and a terminal for receiving the ESG, for evaluating the content fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating and displaying the information about the plurality of files included in the file set if the content fragment comprises the file set. According to another aspect of the present invention, a method for providing file information in a file download service using broadcasting information is provided. The method includes transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the schedule event fragment comprises information about the plurality of files included in the file set, receiving, by a terminal, the ESG, determining, by the terminal, if a request for downloadable file information is input, determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the schedule event fragment if the request for the downloadable file information is input, and evaluating and displaying, by the terminal, the information about the files included in the file set if the schedule event fragment comprises the file set. According to another aspect of the present invention, a method for providing file information in a file download service using broadcasting information is provided. The method includes transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the content fragment comprises information about the plurality of files included in the file set, receiving, by a terminal, the ESG, determining, by the terminal, if a request for downloadable file information is input, determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the content fragment if the request for the downloadable file information is input, evaluating and displaying, by the terminal, the information about the files included in the file set if the content fragment comprises the file set. According to another aspect of the present invention, a terminal for providing file information of files in a file download service using broadcasting information is provided. The terminal includes a receiver for receiving an Electronic Service Guide (ESG), a memory unit for storing the received ESG, a display unit for displaying input data, and a controller for evaluating a schedule event fragment of the received ESG to determine whether the ESG comprises information about a file set, for evaluating information about files included in the file set if the ESG comprises the information about the file set, and for displaying the information through the display unit.	PRIORITY This application claims the benefit under 35 U.S.C. §119(a) of a Korean Patent Application filed in the Korean Intellectual Property Office on Sep. 18, 2006 and assigned Serial No. 2006-90180 and a Korean Patent Application filed in the Korean Intellectual Property Office on Apr. 20, 2007 and assigned Serial No. 2007-39066, the entire disclosures of both of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for a digital video broadcasting system. More particularly, the present invention relates to a digital video broadcasting system, digital video broadcasting terminal, and method for providing information about downloadable files using an Electronic Service Guide (ESG) in a file download service. 2. Description of the Related Art Generally, in a digital broadcasting system, a broadcasting signal, which has been conventionally transmitted in an analog manner, is transmitted in a digital manner. A broadcasting signal transmitted in a digital manner provides superior quality and provides various services for both video and audio. Digital broadcasting is classified as Digital Video Broadcasting (DVB), Digital Audio Broadcasting (DAB), Digital Multimedia Broadcasting (DMB), MediaFLO, and the like. DVB is a European digital broadcasting standard and can be classified into various forms according to its nature, such as DVB-Terrestrial (DVB-T), DVB-Satellite (DVB-S), and DVB-Handheld (DVB-H). DVB-T is a standard for terrestrial digital broadcasting, DVB-S is a standard for satellite digital broadcasting, and DVB-H is a standard for portable mobile digital broadcasting. DVB-H is a technology standard established for the transmission of digital signals to handheld devices such as mobile terminals and the like. DVB-H provides excellent reception of terrestrial digital broadcasting to handheld devices (i.e. mobile terminals). Moreover, it can be used to implement digital mobile multimedia broadcasting to provide high-quality video and audio content to users anytime and anywhere, for example while driving or walking. Unlike other digital broadcasting standards, DVB-H transmits important information required for a broadcasting service through Electronic Service Guide (ESG) data. DVB-H uses a File Delivery over Unidirectional Transport (FLUTE) protocol as a Content Delivery Protocol (CDP). The FLUTE protocol allows transmission of files such as text, audio, video and image files. As part of its standard, DVB-H uses the FLUTE protocol to download files required for ESG configuration and ESG update. DVB-H provides video broadcasting and audio broadcasting as fundamental broadcasting services. In addition, DVB-H provides a data broadcasting service. In other words, three types of services, i.e., video service, audio service and data service, can be provided by the DVB-H standard. Information about each of the three services is transmitted through ESG information. A terminal, for example a handheld device, receiving a DVB-H broadcasting signal, analyzes ESG information included in the broadcasting signal in order to recognize the type of service transmitted through the broadcasting signal and service related information. The ESG information includes Extensible Markup Language (XML) data, and the format of ESG XML information is defined using an XML scheme in the standard. DVB-H broadcasting information is transmitted as ESG fragment information. An ESG fragment can be classified into various types according to the information included in the ESG fragment. ESG data defined in the DVB-H service includes 7 fragments, i.e., a service bundle fragment, a purchase fragment, a purchase channel fragment, a service fragment, a schedule event fragment, a content fragment, and an acquisition fragment. The terminal collects these fragments together in order to recognize all of the information contained in the DVB-H broadcasting signal. A DVB-H broadcasting service includes a data broadcasting service. A data broadcasting service is a file download service that involves downloading a particular data file transmitted through a broadcasting signal. In the file download service, file data required for a service, such as an HTML page, Audio/Video (AV) files, and ring tones, in addition to a streaming service, is transmitted using the FLUTE protocol. In order to acquire file data used for a particular period of time, a FLUTE session is initiated using Session Description Protocol (SDP) information of the ESG data and the desired file data is transmitted. In the file download service, information required for the file download service is transmitted using the service fragment, the schedule event fragment, the content fragment, and the acquisition fragment of the ESG data. FIGS. 4A and 4B illustrate an ESG for a DVB-H file download service. Uniform Resource Identifier (URI) information for each transmission file is transmitted through a schedule event fragment. It can be seen from FIGS. 4A and 4B that a download service for three ring tone MP3 files, i.e., a Ring Tone 1, a Ring Tone 2, and a Ring Tone 100, is provided. More specifically, it can be seen from FIGS. 4A and 4B that URI information for each MP3 file is transmitted through a content location element of the schedule event fragment. As can be seen from FIGS. 4A and 4B, information required to provide the download service for the three MP3 files is transmitted through the content fragment, the service fragment, the schedule event fragment, and the acquisition fragment. FIG. 5 illustrates the syntax of a general ESG schedule event fragment. Referring to FIG. 5, a content location element 500 of the schedule event fragment has information about the type of any URI and can indicate URI information of a single service file. As such, when the current DVB-H system provides file information for a download service using an ESG, it can provide information about a download service for a single file as illustrated in FIGS. 4A and 4B. However, when several individual files are grouped together for download in the file download service, there is no way to provide information about each of the several files included in the grouped file. As a result, when a set of several files is provided in a file download service, information about each of the several files included in the set may not be provided. For example, when a service provider offers 10 ring tone MP3 files, grouped together as a single file, to a user for purchase, the user may desire to evaluate information about each of the 10 ring tone MP3 files, i.e., a file list, before paying for and downloading the 10 ring tone MP3 files. However, according to the current DVB-H Convergence of Broadcast and Mobile Services (CBMS) ESG standard, when a terminal is provided with several files grouped as a single file, there is no way to provide information about each of the individual files of the grouped file, thus resulting in a failure to provide sufficient information to the user. SUMMARY OF THE INVENTION The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an object of the present invention is to provide a digital video broadcasting system, terminal, and method for providing information about a plurality of files grouped as a single file through an ESG. According to one aspect of the present invention, a digital broadcasting system for providing file information in a file download service using broadcasting information is provided. The digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that are included in the file download service comprise a file set that is generated by grouping a plurality of files, the schedule event fragment comprises information about the plurality of files included in the file set, and a terminal for receiving the ESG, for evaluating the schedule event fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating and displaying the information about the plurality of files included in the file set if the schedule event fragment comprises the information about the file set. According to another aspect of the present invention, a digital broadcasting system for providing file information in a file download service using broadcasting information is provided. The digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the content fragment comprises information about the plurality of files included in the file set and a terminal for receiving the ESG, for evaluating the content fragment of the ESG upon receipt of a request for downloadable file information, and for evaluating and displaying the information about the plurality of files included in the file set if the content fragment comprises the file set. According to another aspect of the present invention, a method for providing file information in a file download service using broadcasting information is provided. The method includes transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the schedule event fragment comprises information about the plurality of files included in the file set, receiving, by a terminal, the ESG, determining, by the terminal, if a request for downloadable file information is input, determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the schedule event fragment if the request for the downloadable file information is input, and evaluating and displaying, by the terminal, the information about the files included in the file set if the schedule event fragment comprises the file set. According to another aspect of the present invention, a method for providing file information in a file download service using broadcasting information is provided. The method includes transmitting, by a broadcasting server, an Electronic Service Guide (ESG) comprising a content fragment wherein, if files that are included in the file download service comprise information about a file set generated by grouping a plurality of files, the content fragment comprises information about the plurality of files included in the file set, receiving, by a terminal, the ESG, determining, by the terminal, if a request for downloadable file information is input, determining, by the terminal, if the content fragment comprises the information about the file set by evaluating the content fragment if the request for the downloadable file information is input, evaluating and displaying, by the terminal, the information about the files included in the file set if the content fragment comprises the file set. According to another aspect of the present invention, a terminal for providing file information of files in a file download service using broadcasting information is provided. The terminal includes a receiver for receiving an Electronic Service Guide (ESG), a memory unit for storing the received ESG, a display unit for displaying input data, and a controller for evaluating a schedule event fragment of the received ESG to determine whether the ESG comprises information about a file set, for evaluating information about files included in the file set if the ESG comprises the information about the file set, and for displaying the information through the display unit. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of exemplary embodiments of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a digital video broadcasting system according to an exemplary embodiment of the present invention; FIG. 2 is a block diagram illustrating a digital video broadcasting terminal according to an exemplary embodiment of the present invention; FIG. 3 is a flowchart illustrating a process of providing file information during a file download service in a digital video broadcasting terminal according to an exemplary embodiment of the present invention; FIGS. 4A and 4B illustrate an ESG for a general ESG file download service; FIG. 5 illustrates the syntax of a general ESG schedule event fragment; FIGS. 6A and 6B illustrate the syntax of an ESG schedule event fragment including file list information of a file set including a plurality of sub files according to an exemplary embodiment of the present invention; FIGS. 7A and 7B illustrate an ESG using the syntax of the ESG schedule event fragment illustrated in FIGS. 6A and 6B according to an exemplary embodiment of the present invention; and FIGS. 8A and 8B illustrate the syntax of an ESG schedule event fragment including file list information of a file set including a plurality of sub files according to an exemplary embodiment of the present invention; FIG. 9 illustrates an ESG using the syntax of the ESG schedule event fragment illustrated in FIGS. 8A and 8B according to an exemplary embodiment of the present invention; FIGS. 10A and 10B illustrate the syntax of a content fragment including file list information of a file set including a plurality of sub files according to an exemplary embodiment of the present invention; FIG. 11 illustrates an ESG using the syntax of the content fragment illustrated in FIGS. 10A and 10B according to an exemplary embodiment of the present invention; and FIG. 12 illustrates a screen displaying information of each file that is made as a single file and information of sub files included in a file set according to exemplary embodiments of the present invention. Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features and structures. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS The matters defined in the description such as a detailed construction and elements are provided to assist in a comprehensive understanding of exemplary embodiments of the invention. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications can be made to what is described herein without departing from the scope and spirit of the invention. Also, descriptions of well-known functions and constructions are omitted for clarity and conciseness. In an exemplary method of the present invention, a terminal receives an ESG schedule event fragment or a content fragment. If the ESG schedule event fragment or the content fragment includes information indicating that a file set, including several files and file list information corresponding to the several files in the file set, is provided as part of a file download service, the file list information is evaluated in order to provide information about each of the several files included in the file set to a user. FIG. 1 is a block diagram illustrating the structure of a digital video broadcasting system according to an exemplary embodiment of the present invention. As shown in FIG. 1, the digital video broadcasting system includes a broadcasting service providing server 110 for generating a Transport Stream (TS) for content provided by a content provider 100 and broadcasting the generated TS, a broadcasting network 113 for broadcasting the TS from the broadcasting service providing server 110 to a terminal 120, and the terminal 120 for receiving the broadcasted TS and performing a digital broadcasting service using the TS. The broadcasting service providing server 110 includes a broadcasting service application unit 111 and a broadcasting service management unit 112. The broadcasting service application unit 111 transmits an audio/video stream and file data to the terminal 120, and the broadcasting service management unit 112 transmits ESG data to the terminal 120. According to an exemplary embodiment of the present invention, a file download service provides a set of several files from a service provider that are made as a single file. When the single file, comprised of the several files, is provided, the broadcasting service providing server 110 transmits an ESG including an ESG schedule event fragment or a content fragment that contains information indicating transmission of the file set and file list information corresponding to each of the several files in the set to the terminal 120. Upon receipt of the ESG, the terminal 120 determines if information indicating the transmission of a file set is included in the ESG schedule event fragment. If so, the terminal 120 evaluates the file list information corresponding to the file set in order to provide the file list information to the user. The following detailed description includes several exemplary embodiments in which the broadcasting service providing server 110 incorporates information about a file set into an ESG. In an exemplary embodiment of the present invention, information about a file set is provided using a content location element of a schedule event fragment. In another exemplary embodiment of the present invention, information about a file set is provided using a content location element indicating information of a single file instead of a file set and an archive location element indicating information of a file set. In yet another exemplary embodiment of the present invention, an archive location element is defined in a content fragment. First, a method for providing information about a file set according to an exemplary embodiment of the present invention will be provided. When several files are transmitted as a file set according to an exemplary embodiment of the present invention, the syntax of an ESG schedule event fragment transmitted by the broadcasting service providing server 110 can be configured as illustrated in FIGS. 6A and 6B. Referring to FIGS. 6A and 6B, the ESG schedule event fragment according to an exemplary embodiment of the present invention includes not only URI information of a download file using a content location element, but also includes information about the files included in the file set if the download file is a file set. In a content location element 600 of an ESG schedule event fragment according to an exemplary embodiment of the present invention, a content URI type element includes information about an encoding type used to group the several files into the file set in order to allow the terminal 120 to determine whether the received file is a file set that includes several files. In an exemplary embodiment illustrated in FIGS. 6A and 6B, an algorithm used for grouping the several files into a file set is a tar algorithm. Of course, other algorithms may be used. The encoding type may be set to “none” by default, and thus an encoding type attribute may be omitted in the transmission of a single file. In other words, as indicated by 600, the ESG schedule event fragment according to an exemplary embodiment of the present invention includes information about an encoding type used to group several files into a file set as an encoding type in a content URI type element and includes file list information corresponding to the file set in a content list type element. An ESG using the syntax of the ESG schedule event fragment as illustrated in FIGS. 6A and 6B will now be described with reference to FIGS. 7A and 7B. FIGS. 7A and 7B illustrate an ESG for providing information about a file set using a content location element of the ESG schedule event fragment illustrated in FIGS. 6A and 6B according to an exemplary embodiment of the present invention. A description will be made of an example in which an ESG is transmitted that includes information about a Ring Tone Set that is a file set, information about a ring Tone 2 and information about a ring Tone 100. Also as part of the example, the service provider transmits three MP3 files, i.e., a ring Tone 1, a ring Tone 2, and a ring Tone 3, as the Ring Tone Set, to a user. A content fragment then includes information indicating that a Ring Tone set including three MP3 files is provided as indicated by 700, information indicating that a Ring Tone 2 is provided as indicated by 702, and information indicating that a Ring Tone 100 is provided as indicated by 704. A schedule event fragment includes information about the three files of the Ring Tone Set. In particular, the schedule event fragment includes a content URI encoding type and a content list corresponding to the file set as indicated by 710. In the information 710, 706 indicates the content URI encoding type corresponding to the file set and 707, 708 and 709 indicate information about the files included in the file set, i.e., information about the ring Tone 1, information about the ring Tone 2, and information about the ring Tone 3, respectively. Upon receipt of the ESG as illustrated in FIGS. 7A and 7B, the terminal 120 can evaluate a content URI encoding type to recognize that, out of the received files, a file corresponding to a ring tone set includes several files that are grouped using a tar algorithm. The terminal 120 can also recognize which files are included in the Ring Tone Set by evaluating a content list before a downloading operation is performed. Next, a method for providing information about a file set according to another exemplary embodiment of the present invention will be described. In order to transmit several files as a file set that is a single file according to an exemplary embodiment of the present invention, the syntax of a schedule event fragment transmitted by the broadcasting service providing server 110 is as shown in FIGS. 8A and 8B. In this exemplary embodiment, an element indicating information about a single file and an element indicating information about a file set are separately used. Referring to FIG. 8A, a content location element is used for a single file having no file set as indicated by 810, and an archive location element is used for a single file having a file set as indicated by 820. The content location element and the archive location element may also be used separately for a single file having no file set or a single file having a file set. When file information to be provided is a file set, basic information may be first provided using a content location element and then detailed information of the file set may be provided using an archive location element, as agreed between a service provider and a terminal. The archive location element has the same content location type information as in the previous exemplary embodiment of the present invention. In other words, although not shown in FIGS. 8A and 8B, by using “esg:ContentLocationRefType” as archive location element type information, information about an encoding type used for grouping files may be included as an encoding type in a content URI type element according to the previous exemplary embodiment of the present invention and file list information corresponding to a file set may be included in a content list type element according to the previous exemplary embodiment of the present invention. FIG. 8B illustrates a modified content URI type element for an exemplary embodiment of the present invention. In other words, in the previous exemplary embodiment of the present invention, a value indicating that an encoding type is “none” is included in order to indicate a single file that is not a file set as shown in FIG. 6B. However, in an exemplary embodiment of the present invention, a single file that is not a file set is indicated using a content location element as shown in FIG. 8B and thus a content URI type element shown in FIG. 8B does not need to include a value indicating that an encoding type is “none”. Hereinafter, an ESG using the syntax of the schedule event fragment as shown in FIGS. 8A and 8B will be described with reference to FIG. 9. FIG. 9 illustrates an ESG for a file download service using the schedule event fragment as shown in FIGS. 8A and 8B according to an exemplary embodiment of the present invention. A description will be made of an example in which an ESG is transmitted that includes information about a Ring Tone Set, information about a ring Tone 2, and information about a ring Tone 100. Also as part of the example, the service provider transmits three MP3 files, i.e., a ring Tone 1, a ring Tone 2, and a ring Tone 3, as the Ring Tone Set that is a single file, to a user. A content fragment then includes information indicating that a Ring Tone Set including three MP3 files is provided as indicated by 910, information indicating that a Ring Tone 2 is provided as indicated by 920, and information indicating that a Ring Tone 100 is provided as indicated by 930. A schedule event fragment includes information about the three files of the Ring Tone Set. In particular, unlike in the previous exemplary embodiment of the present invention, a content URI encoding type and a content list corresponding to the file set as indicated by 910 use an archive location element as indicated by 970 in an exemplary embodiment of the present invention. In other words, an archive location element is used for a file set and a content location element is used for other cases. In the information 970, 935 indicates the content URI encoding type corresponding to the file set as indicated by 910 and 940, 950, and 960 indicate information about the files included in the file set, i.e., information about the ring Tone 1, information about the ring Tone 2, and information about the ring Tone 3, respectively. Next, a method for providing information about a file set according to an exemplary embodiment of the present invention will be described. In order to transmit several files as a single file set according to an exemplary embodiment of the present invention, the syntax of a schedule event fragment and the syntax of a content fragment transmitted by the broadcasting service providing server 110 are as shown in FIGS. 10A and 10B. Here, an exemplary embodiment of the present invention is different from the previous exemplary embodiment of the present invention in that the archive location element is included in a content fragment instead of a schedule event fragment. In other words, in the previous exemplary embodiment of the present invention, information about a file set is provided in a content fragment indicating information of the file set, instead of recognizing file set information of content according to each schedule in a schedule event fragment. Referring to FIG. 10B, the archive location element is included in the content fragment as indicated by 1020. In the schedule event fragment, a content location element is used to indicate a single file using an “AnyURI” type as indicated by 1010 in FIG. 10A. Hereinafter, an ESG using the syntax of a content fragment shown in FIGS. 10A and 10B will be described with reference to FIG. 11. FIG. 11 illustrates an ESG using the syntax of the content fragment illustrated in FIGS. 10A and 10B according to an exemplary embodiment of the present invention. A description will be made of an example in which an ESG is transmitted that includes information about a Ring Tone Set, information about a ring Tone 2, and information about a ring Tone 100. Also as part of the example, content locations of the three files are transmitted through the content fragment and the service provider transmits three MP3 files, i.e., a ring Tone 1, a ring Tone 2, and a ring Tone 3, as the Ring Tone Set that is a single file, to a user. A content fragment then includes information indicating that a Ring Tone set including three MP3 files is provided. The content fragment includes information about the three files and a content URI encoding type and a content list corresponding to a file set is included in an archive location element as indicated by 1150. In the information 1150, 1110 indicates a content URI encoding type of the file set and 1120, 1130, and 140 indicate information about each of the three files, i.e., information about a ring Tone 1, information about a ring Tone 2, and information about a ring Tone 3. Hereinafter, the structure of a terminal 120 according to an exemplary embodiment of the present invention will be described with reference to FIG. 2. An exemplary terminal 120 is a digital video broadcasting terminal. FIG. 2 is a block diagram illustrating an exemplary digital video broadcasting terminal 120. The digital video broadcasting terminal 120 includes a digital broadcasting receiver 202, a memory unit 204, a controller 200, a key input unit 210, a display unit 206, and an audio processor 208. Once a broadcasting channel is selected through use of the controller 200, the digital broadcasting receiver 202 receives and demodulates digital broadcasting data from the broadcasting channel and outputs the demodulated digital broadcasting data to the controller 200. In an exemplary embodiment of the present invention, the digital broadcasting system is a DVB-H broadcasting system and the digital broadcasting receiver 202 is a DVB-H Orthogonal Frequency Division Multiplex (OFDM) demodulator. In such an exemplary system, the OFDM demodulator performs OFDM demodulation on a signal received from a broadcasting station that broadcasts DVB-H broadcasting data and outputs digital broadcasting data of a channel selected by a user. The digital broadcasting receiver 202 receives an ESG data stream included in a digital broadcasting TS broadcasted by a digital broadcasting device. The terminal 120 may also include a Radio Frequency (RF) unit (not shown) including an RF transmitter for up-converting and amplifying the frequency of a transmission signal, and an RF receiver for low-noise amplifying and down-converting the frequency of a reception signal. The memory unit 204 stores data required by the controller 200 and, in particular, stores file download service information included in ESG data received from the broadcasting service providing server 110. The controller 200 controls the overall operation of the digital video broadcasting terminal 120, decodes a digital broadcasting stream output from the digital broadcasting receiver 202, and outputs the decoded digital broadcasting stream through the display unit 206 and the audio processor 208. The terminal 120 may also include a video signal processor (not shown) and an audio signal processor (not shown) for respectively processing decoded video and audio signals. In an exemplary embodiment, if information indicating the transmission of a file set is included in an ESG schedule event fragment or a content fragment generated by the broadcasting service providing server 110, the controller 200 performs a control operation in such a way as to evaluate file list information corresponding to the file set and to provide the file list information to the user. A detailed operation of the controller 200 for evaluating information about a file set provided through an ESG schedule event fragment or a content fragment by the broadcasting service providing server 110 and providing information about the file set to the user will be described later with reference to FIG. 3. The key input unit 210 receives a user manipulation signal, such as a key input, and transmits the received user manipulation signal to the controller 200. The display unit 206 outputs display data generated in the digital video broadcasting terminal 120. In an exemplary embodiment, the display unit 206 is a Liquid Crystal Display (LCD) for sufficiently supporting the resolution of broadcasting data. When an LCD is implemented with a touch screen, the display unit 206 may also serve as an input unit. The audio processor 208 modulates an electric signal input from a microphone into voice data, and demodulates encoded voice data input from the digital broadcasting receiver 202 into an electric signal and outputs the electric signal to a speaker. The audio processor 208 may include a data codec for processing packet data and an audio codec for processing an audio signal such as voice. In an exemplary embodiment, the audio processor 208 is included in the controller 200. Hereinafter, an exemplary operation of the digital video broadcasting terminal 120 for providing file information to the user in a file download service will be described with reference to FIGS. 3 and 7A through 12. In step 300, once the digital video broadcasting terminal 120 receives ESG data through the digital broadcasting receiver 202, the controller 200 stores the received ESG data in the memory unit 204. The controller 200 determines if a request for viewing information about downloadable files is input from a user in step 302. If so, step 306 is performed. If not, the controller proceeds to step 304 and a corresponding operation is performed. At the request of the user in step 302, the controller 200 proceeds to step 306 and analyzes a schedule event fragment or a content fragment in the ESG data stored in the memory unit 204. In this step, the controller 200 analyzes a schedule event fragment or a content fragment. In step 308, the controller 200 determines if the analysis result with respect to the schedule event fragment or the content fragment in the ESG data indicates that the downloadable files include a file set. Although a schedule event fragment is first analyzed and then a content fragment is analyzed in a general ESG data analysis, the analysis of step 306 is performed on the schedule event fragment or the content fragment in order to determine if the downloadable files include a file set. If the controller 200 receives the ESG generated according to an exemplary embodiment of the present invention, it determines if one of the downloadable files is configured as a file set by evaluating a content URI encoding type element including encoding information as indicated by 710 of FIG. 7A. If the downloadable files do not include a file set and each of the downloadable files is a single file, the controller 200 displays information about each of the downloadable files on a screen using a general file information display method in step 314. If the controller 200 receives the ESG generated according to an exemplary embodiment of the present invention, it determines if one of the downloadable files is configured as a file set by evaluating a file set list included in an archive location element of a schedule event fragment as indicated by 970 of FIG. 9. If the controller 200 receives the ESG generated according to an exemplary embodiment of the present invention, it determines if one of the downloadable files is configured as a file set by evaluating a file set list included in an archive location element of a content fragment as indicated by 1150 of FIG. 11. If it is determined in step 308 that the downloadable files do include a file set as well as single files, in step 310 the controller 200 displays file information for the downloadable files, each of which is a single file, using a general file information display method. Also in step 310, the controller evaluates file information for sub-files included in the file set. As part of the evaluation, the controller 200 evaluates information about the sub-files included in the file set using a content list element corresponding to the file set. If the controller receives the ESG generated according to an exemplary embodiment of the present invention, by checking information 707, 708, and 709 included in a content list as illustrated in FIG. 7A, the controller 200 recognizes that the sub files are ringTone 1, ringTone 2, and ringTone 3, respectively. If the controller 200 receives the ESG generated according to an exemplary embodiment of the present invention, by checking information 940, 950, and 960 included in a content list as illustrated in FIG. 9, the controller 200 recognizes that the sub files are ringTone 1, ringTone 2, and ringTone 3, respectively. If the controller 200 receives the ESG generated according to an exemplary embodiment of the present invention, by checking information 1120, 1130, and 1140 included in a content list as illustrated in FIG. 11, the controller 200 recognizes that the sub files are ringTone 1, ringTone 2, and ringTone 3, respectively. The controller 200 then displays file information for the sub-files included in the file set through the display unit 206 in step 312. The display of the file information for the sub-files may be simultaneous with the display of the information of the single files. For example, the screen of the digital video broadcasting terminal 120 may display the file information as illustrated in FIG. 12. In other words, general file information is displayed for the files, i.e., “2. Ring Tone 2” and “3. Ring Tone 100”, each of which is a single file, and file list information of the sub files included in the Ring Tone Set, i.e., “ringTone 1.mp3, ringTone 2.mp3, and ringTone 3.mp3”, is displayed for the file set “1. Ring Tone Set” as a popup window. The file list information of the sub-files for the file set “1. Ring Tone Set” may be displayed as a popup window 800 simultaneously with the file information for the other files as illustrated in FIG. 12, or may be displayed as a popup window upon a user's key click or cursor dragging. As described above, according to exemplary embodiments of the present invention, for a download service using broadcasting information, several files may be transmitted as a file set, thereby improving the efficiency of file transmission when compared to transmitting the files separately. Furthermore, when several files are serviced as a file set, information about the files included in the file set is provided through ESG information, thereby allowing the user to evaluate the information about the files included in the file set before downloading the files. While the invention has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.	G	60G06	161G06F	3	00
11923664	US20090113553A1-20090430	METHOD AND SYSTEM FOR HIDING INFORMATION IN THE INSTRUCTION PROCESSING PIPELINE	ACCEPTED	20090416	20090430	[]	G06F2100	["G06F2100", "H04L900"]	8141162	20071025	20120320	726	026000	65882.0	EL HADY	NABIL	[{"inventor_name_last": "Myles", "inventor_name_first": "Ginger Marie", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}]	A system, article of manufacture and method is provided for transferring secret information from a first location to a second location. The secret information is encoded and stalls in executable code are located. The executable code is configured to perform a predetermined function when executed on a pipeline processor. The encoded information is inserted into a plurality of instructions and the instructions are inserted into the executable code at the stalls. There is no net effect of all of the inserted instructions on the predetermined function of the executable code. The executable code is transferred to the second location. The location of the stalls in the transferred code is identified. The encoded information is extracted from the instructions located at the stalls. The encoded information may then be decoding information to generate the information at the second location.	1. A method for embedding information in a computer program comprising: performing data dependency analysis on said computer program to identify locations within said computer program where pipeline processing dependencies require a stall, said locations including no-operation instructions: encoding said information; and inserting an instruction in said location, said instruction containing at least a portion of said information by dividing said information into a plurality of consecutive sections and inserting said instructions containing said consecutive sections non-consecutively into said locations within said computer program. 2. (canceled) 3. (canceled) 4. (canceled) 5. (canceled) 6. (canceled) 7. (canceled) 8. (canceled) 9. (canceled) 10. (canceled) 11. (canceled) 12. (canceled) 13. (canceled) 14. (canceled) 15. (canceled) 16. (canceled) 17. (canceled) 18. (canceled) 19. (canceled) 20. (canceled)	<SOH> BACKGROUND <EOH>Steganographic and watermarking techniques have been used to hide ancillary information in many different types of media. Steganographic techniques are generally used when the purpose is to conduct some type of secret communication and stealth is critical to prevent the interception of the hidden message. Watermarking techniques are more appropriate where the primary concern is to protect the hidden information, the watermark, from damage or removal. In steganography a classic model is known as the “prisoners' problem”. One example of the prisoners' problem is a scenario where Alice and Bob are two prisoners sent to different cells. Any communication between them must go through a warden Wendy. Because the warden wants to ensure that they are not developing an escape plan, she will not allow encrypted messages or any other suspicious communication. Therefore, Alice and Bob must set up a subliminal channel to communicate their escape plan invisibly. Based on this model, steganography works as follows. When Alice wants to send a secret message to Bob she first selects a cover-object c. The cover-object is some harmless message which will not raise suspicion. She then embeds the secret message m in the cover-object to produce the stego-object s. The stego-object must be created in such a way that Wendy, knowing only the seemingly harmless message s, will not be able to detect the presence of a secret in the cover-object c. Alice then transmits the message s over an insecure channel to Bob. Once received, Bob is able to decode the message m since he knows the embedding method and their shared secret key. Steganography is useful in many applications, such as the prevention of piracy of media. When using still images, video, or audio as the cover media we are able to leverage limitations in the human visual and auditory systems. This has led to a plethora of research on digital steganography and watermarking. Unfortunately, when the cover medium is an executable program we are far more restricted as to the type of transformations we can apply. These restrictions have resulted in fewer techniques, most of which suffer from inadequate data rates and/or poor resistance to attack. In contrast to image and sound steganography very little attention has been paid to code steganography. Most of the research directed at hiding information in executables has focused on providing piracy protection and thus has taken the form of software watermarking. A number of software watermarking techniques have been developed and proposed. Some software watermarking algorithms embed the watermark through an extension to a method's control flow graph. The watermark is encoded in a subgraph which is incorporated in the original graph. In other techniques, the instruction frequencies of the original program are modified to embed the watermark. A dynamic watermarking algorithm has been proposed which embeds the watermark in the structure of the graph, built on the heap at runtime, as the program executes on a particular input. Other proposed techniques are path-based and rely on the dynamic branching behavior of the program. To embed the watermark the sequence of branches taken and not taken on a particular input are modified. An abstract interpretation framework may also be used to embed a watermark in the values assigned to integer local variables during program execution. Other techniques leverage the ability to execute blocks of code on different threads. The watermark is encoded in the choice of blocks executed on the same thread. Also, a branch function may be used which generates the watermark as the program executes. In addition to software watermarking, other techniques are aimed directly at code steganography. For example one technique draws on the inherent redundancy in the instruction set to encode a message by noting that several instructions can be expressed in more than one way. For example, adding a value x to a register can be replaced with subtracting −x from the register. By creating sets of functionally equivalent instructions, message bits can be encoded in the machine code. Two improvements on the equivalent instruction substitution technique have been proposed using alternative encoding methods. The first technique is based on the ordering of basic blocks. The chain of basic blocks is selected based on the bits to be encoded. The second technique operates on a finer granularity and relies on the ordering of the instructions within a basic block. One recent code steganography technique is suggested not as a method for transferring secret messages, but as a way to provide additional information to the processor. The information encoding is accomplished by modifying operand bits in the instruction. To ensure proper execution a look-up table is stored in the program header. Each of the above techniques has certain disadvantages such as inadequate data rates and poor resistance to attack. Accordingly, there is a need for methods and systems for providing hidden messages in executable programs which have acceptable data rates and are very resistant to attack.	<SOH> SUMMARY OF THE INVENTION <EOH>To overcome the limitations in the prior art briefly described above, the present invention provides a method, computer program product, and system for hiding information in an instruction processing pipeline. In one embodiment of the present invention a method for embedding information in a computer program comprises: identifying at least one location within the computer program where pipeline processing dependencies require a stall; and inserting an instruction in the location, the instruction containing at least a portion of the information. In another embodiment of the present invention, a method of hiding information in the instruction processing pipeline of a computer program comprises: identifying at least one stall in the instruction processing pipeline; and filling the stall with an instruction that encodes a secret message, the instruction not altering the functionality of the computer program. In a further embodiment of the present invention includes an article of manufacture for use in a computer system tangibly embodying computer instructions executable by the computer system to perform process steps for transferring information from a first location to a second location the process steps comprising: encoding the information; locating stalls in executable code, the executable code being configured to perform a predetermined function when executed on a pipeline processor; inserting the encoded information into a plurality of instructions; inserting the instructions into the executable code at the stalls, there being no net effect of all of the inserted instructions on the predetermined function of the executable code; transferring the executable code to the second location; identifying the location of the stalls in the transferred executable code; extracting the encoded information from the instructions located at the stalls; and decoding the encoding information to generate the information at the second location. An additional embodiment of the present invention comprises a system for embedding a digital signature in executable code comprising: stall identifying unit for identifying the location of stalls within the executable code; and instruction insertion unit for inserting an instruction in a first of the locations, the instruction containing at least a first portion of a digital signature. Various advantages and features of novelty, which characterize the present invention, are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention and its advantages, reference should be made to the accompanying descriptive matter together with the corresponding drawings which form a further part hereof, in which there is described and illustrated specific examples in accordance with the present invention.	FIELD OF INVENTION The present invention generally relates to computer implemented steganographic and watermarking techniques, and particularly to methods and systems for encoding secret information in arbitrary program binaries. BACKGROUND Steganographic and watermarking techniques have been used to hide ancillary information in many different types of media. Steganographic techniques are generally used when the purpose is to conduct some type of secret communication and stealth is critical to prevent the interception of the hidden message. Watermarking techniques are more appropriate where the primary concern is to protect the hidden information, the watermark, from damage or removal. In steganography a classic model is known as the “prisoners' problem”. One example of the prisoners' problem is a scenario where Alice and Bob are two prisoners sent to different cells. Any communication between them must go through a warden Wendy. Because the warden wants to ensure that they are not developing an escape plan, she will not allow encrypted messages or any other suspicious communication. Therefore, Alice and Bob must set up a subliminal channel to communicate their escape plan invisibly. Based on this model, steganography works as follows. When Alice wants to send a secret message to Bob she first selects a cover-object c. The cover-object is some harmless message which will not raise suspicion. She then embeds the secret message m in the cover-object to produce the stego-object s. The stego-object must be created in such a way that Wendy, knowing only the seemingly harmless message s, will not be able to detect the presence of a secret in the cover-object c. Alice then transmits the message s over an insecure channel to Bob. Once received, Bob is able to decode the message m since he knows the embedding method and their shared secret key. Steganography is useful in many applications, such as the prevention of piracy of media. When using still images, video, or audio as the cover media we are able to leverage limitations in the human visual and auditory systems. This has led to a plethora of research on digital steganography and watermarking. Unfortunately, when the cover medium is an executable program we are far more restricted as to the type of transformations we can apply. These restrictions have resulted in fewer techniques, most of which suffer from inadequate data rates and/or poor resistance to attack. In contrast to image and sound steganography very little attention has been paid to code steganography. Most of the research directed at hiding information in executables has focused on providing piracy protection and thus has taken the form of software watermarking. A number of software watermarking techniques have been developed and proposed. Some software watermarking algorithms embed the watermark through an extension to a method's control flow graph. The watermark is encoded in a subgraph which is incorporated in the original graph. In other techniques, the instruction frequencies of the original program are modified to embed the watermark. A dynamic watermarking algorithm has been proposed which embeds the watermark in the structure of the graph, built on the heap at runtime, as the program executes on a particular input. Other proposed techniques are path-based and rely on the dynamic branching behavior of the program. To embed the watermark the sequence of branches taken and not taken on a particular input are modified. An abstract interpretation framework may also be used to embed a watermark in the values assigned to integer local variables during program execution. Other techniques leverage the ability to execute blocks of code on different threads. The watermark is encoded in the choice of blocks executed on the same thread. Also, a branch function may be used which generates the watermark as the program executes. In addition to software watermarking, other techniques are aimed directly at code steganography. For example one technique draws on the inherent redundancy in the instruction set to encode a message by noting that several instructions can be expressed in more than one way. For example, adding a value x to a register can be replaced with subtracting −x from the register. By creating sets of functionally equivalent instructions, message bits can be encoded in the machine code. Two improvements on the equivalent instruction substitution technique have been proposed using alternative encoding methods. The first technique is based on the ordering of basic blocks. The chain of basic blocks is selected based on the bits to be encoded. The second technique operates on a finer granularity and relies on the ordering of the instructions within a basic block. One recent code steganography technique is suggested not as a method for transferring secret messages, but as a way to provide additional information to the processor. The information encoding is accomplished by modifying operand bits in the instruction. To ensure proper execution a look-up table is stored in the program header. Each of the above techniques has certain disadvantages such as inadequate data rates and poor resistance to attack. Accordingly, there is a need for methods and systems for providing hidden messages in executable programs which have acceptable data rates and are very resistant to attack. SUMMARY OF THE INVENTION To overcome the limitations in the prior art briefly described above, the present invention provides a method, computer program product, and system for hiding information in an instruction processing pipeline. In one embodiment of the present invention a method for embedding information in a computer program comprises: identifying at least one location within the computer program where pipeline processing dependencies require a stall; and inserting an instruction in the location, the instruction containing at least a portion of the information. In another embodiment of the present invention, a method of hiding information in the instruction processing pipeline of a computer program comprises: identifying at least one stall in the instruction processing pipeline; and filling the stall with an instruction that encodes a secret message, the instruction not altering the functionality of the computer program. In a further embodiment of the present invention includes an article of manufacture for use in a computer system tangibly embodying computer instructions executable by the computer system to perform process steps for transferring information from a first location to a second location the process steps comprising: encoding the information; locating stalls in executable code, the executable code being configured to perform a predetermined function when executed on a pipeline processor; inserting the encoded information into a plurality of instructions; inserting the instructions into the executable code at the stalls, there being no net effect of all of the inserted instructions on the predetermined function of the executable code; transferring the executable code to the second location; identifying the location of the stalls in the transferred executable code; extracting the encoded information from the instructions located at the stalls; and decoding the encoding information to generate the information at the second location. An additional embodiment of the present invention comprises a system for embedding a digital signature in executable code comprising: stall identifying unit for identifying the location of stalls within the executable code; and instruction insertion unit for inserting an instruction in a first of the locations, the instruction containing at least a first portion of a digital signature. Various advantages and features of novelty, which characterize the present invention, are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention and its advantages, reference should be made to the accompanying descriptive matter together with the corresponding drawings which form a further part hereof, in which there is described and illustrated specific examples in accordance with the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is described in conjunction with the appended drawings, where like reference numbers denote the same element throughout the set of drawings: FIG. 1 is a block diagram of a typical computer system wherein the present invention may be practiced; FIG. 2 shows a block diagram of a system for embedding a message in executable code in accordance with an embodiment of the invention; FIG. 3 shows a flow chart of a method of embedding a message in executable code in accordance with an embodiment of the invention; FIG. 4 shows a block diagram of a system for extracting the message embedded in the system shown in FIG. 2 in accordance with an embodiment of the invention; and FIG. 5 shows a flow chart of a method of extracting a message from executable code in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION The present invention overcomes the problems associated with the prior art by teaching a system, computer program product, and method for hiding information in an instruction processing pipeline. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. Those skilled in the art will recognize, however, that the teachings contained herein may be applied to other embodiments and that the present invention may be practiced apart from these specific details. Accordingly, the present invention should not be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described and claimed herein. The following description is presented to enable one of ordinary skill in the art to make and use the present invention and is provided in the context of a patent application and its requirements. The various elements and embodiments of invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention may be implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters. FIG. 1 is a block diagram of a computer system 100, in which teachings of the present invention may be embodied. The computer system 100 comprises one or more central processing units (CPUs) 102, 103, and 104. The CPUs 102-104 suitably operate together in concert with memory 110 in order to execute a variety of tasks. In accordance with techniques known in the art, numerous other components may be utilized with computer system 100, such a input/output devices comprising keyboards, displays, direct access storage devices (DASDs), printers, tapes, etc. (not shown). Although the present invention is described in a particular hardware embodiment, those of ordinary skill in the art will recognize and appreciate that this is meant to be illustrative and not restrictive of the present invention. Those of ordinary skill in the art will further appreciate that a wide range of computers and computing system configurations can be used to support the methods of the present invention, including, for example, configurations encompassing multiple systems, the internet, and distributed networks. Accordingly, the teachings contained herein should be viewed as highly “scalable”, meaning that they are adaptable to implementation on one, or several thousand, computer systems. The present invention provides a system and method of hiding information in an instruction processing pipeline. In particular, the present invention hides information in arbitrary program binaries. This is done by identifying stalls in the instruction processing pipeline. Instead of filling these stalls with no operation (nop) instructions the stalls are filled with instructions which will not adversely alter the functionality of the program, but which encode a hidden message. The present invention can be used for secret communication or for watermarking/fingerprinting. It can also be used for encoding a digital signature of the executable code. The present invention, in one embodiment, is a code steganographic technique that takes a message and an executable as input, and outputs a semantically equivalent executable which contains the secret message. To accomplish this, the present invention may analyze how the executable's instruction sequence would be processed in the instruction processing pipeline. The present invention takes advantage of the manner in which the executable's instruction sequence is processed. Due to data dependencies between instructions it is not always possible to maintain a completely full instruction pipeline. These dependencies result in instruction stalls, often referred to as bubbles in the pipeline. Until the dependency can be resolved, the processing of a new instruction is stalled for x time units. The stall is generally accomplished by inserting x nops in the instruction sequence. In accordance with the present invention, message encoding occurs by replacing those nop instructions with instructions that will not adversely alter the functionality of the program. Each instruction substitution may then represent a single bit, or some piece, of the secret message. In one embodiment the present invention may be employed on Microprocessor without Interlocked Pipeline Stages (MIPS) Executable and Linking Format (ELF) executables. However, the principles of the present invention may be applicable to any pipeline architecture. The MIPS architecture is a useful example due to the relative simplicity of the instruction pipeline processing and the fixed length instruction set, which makes binary rewriting easier. The embedding process itself is aided by the analysis that is normally performed during compilation. That is, when a program is compiled instruction scheduling analysis is performed, which identifies data dependencies. Depending on the specific level of optimization, when a dependency is found different actions take place. For an application compiled with optimization disabled, identification of a dependency results in the insertion of one or more nops in the instruction sequence. When optimization is enabled the compiler tries to reorder the instructions. Then if reordering fails the fall back is nop insertion. As a result, the embedding process of the present invention may not require data dependency analysis, although it is possible to employ data dependency analysis as part of the embedding process. With nops already inserted as part of the conventional data dependence, in accordance with one embodiment of the invention, the instruction sequence may be scanned for nop instructions. When a nop is found it may be replaced with an instruction corresponding to the current message bit. The inserted instruction may be selected from an instruction codebook which may be constructed and shared with the intended message recipient prior to beginning the secret communication. Alternatively, the method for constructing the instruction codebook may be shared with the recipient prior to the secret communication. FIG. 2 shows a block diagram of a message embedding system 200 for embedding information into an instruction processing pipeline in accordance with an embodiment of the invention. Executable code 202 is received by a message embedder 204. The message embedder 204 uses a stall locater module 206 for finding all the stalls in the code. In cases where dependency analysis has been done, the stall locator simply needs to locate the nops. In situations where the dependency analysis has not been done, the stall locator may do this analysis first before locating the stalls. A secret message 208 is received by a message encoder 210, which converts the message into a form that is suitable for insertion into the executable code 202. For example, the message may be in human readable form, and the message encoder 210 may converts it into an encoded digital representation. In some embodiments, this encoded message may be encrypted using conventional encryption techniques. The encoded message is then received by the message embedder 204 where an insertion module 212 inserts the encoded message into the executable code in the locations where the nops were located. In particular, the nops are removed and an instruction containing the encoded message is inserted in its place. Generally, it will take several nops to represent the entire encoded message, so the insertion module 212 will separate the encoded message into sections that will be inserted into multiple nop locations. The result will be a version of the executable code 214 that performs the same as the original executable code 202, but now contains the hidden message. 208. In should be noted that the insertion module 212 will insert instructions, which include parts of the encoded message, which will take the place of the nop instructions. The inserted instructions will be constructed so that they will have the same effect as a nop; that is, they will occupy one execution cycle without performing any operation. Alternatively, an inserted encoded message may comprise an instruction that actually does perform some operation, but a subsequent instruction will undo that operation so there will be no net effect. This approach may be preferred in some instances because it may make it more difficult for an unauthorized person to detect the locations of the instructions containing the encoded message. FIG. 3 shows a flow chart of a process 300 for embedding a message in executable code in accordance with one embodiment of the invention. In step 302 the secret encoded message and the executable code are received, for example, by the message embedder 204. In step 304 the first and subsequent instructions are selected one at a time. Step 306 determines if a stall exists at this instruction. As discussed above, where dependency analysis has already been performed, this step may simply comprise determining if the selected instruction is a nop instruction. If it is not, the process returns to step 304 and the next instruction is selected. If step 306 determines that the instruction is a stall, the process moves to step 308, which looks at the code book and at the message to determine which instruction to put in that location in the place of the nop. In step 310 the proper instruction message containing the correct portion of the secret message is inserted into the executable code. Step 312 then determines if the entire message has been embedded. If not, the process returns to step 304 and the next instruction is selected. If the entire message has been embedded then step 314 outputs the semantically equivalent, executable code containing the encoded message. In many steganographic techniques it is often common to assume what is called a passive warden. This means that any person serving as an intermediary in the message exchange will read the message and possibly prevent it from being exchanged, but will not attempt to modify it. Because of this assumption, we can use a static embedding technique (one that only uses information statically available). Therefore, one possible method for selecting the nops is simply to replace them in the order that they appear in the executable. However, in some applications, for example, where the present invention is used for watermarking purposes code modification attacks are a concern. Hence, in such applications a dynamic embedding technique may be preferred. One dynamic embedding technique that may be employed is to replace those nop instructions which reside on a particular execution path through the program instead of in the order that they appear in the executable. In this case, the program would be executed using a particular input sequence prior to embedding the secret message. As the program executes, the path through the program is recorded. Then, instead of selecting instruction as they appear in the static executable, we select instructions along the identified path through the program. To extract the watermark, the receiver will use the same input sequence to identify the path through the program. Then the message will be extracted from the instructions along that path. Since the embedded instructions are now linked to program execution it is more difficult to rearrange them. One of the keys to dynamic watermarking is that the input sequence used should remain secret; it basically serves the same purpose as a secret key in cryptography. Only the sender and the receiver should know the secret input sequence. FIG. 4 shows a block diagram of a message extraction system 400 in accordance with one embodiment of the invention. The executable code 402 with the secret encoded message embedded therein is received by a message extractor 402. Executable code 402 may comprise the executable code 214 with the embedded message shown in FIG. 2. Message locator module 406 will determine the location of the instructions containing the secret message. For example, message locator module 406 may do this by using information from a previously provided code book (not shown). The codebook may contain a list of all instructions used to encode part of the secret message and the value the instruction represents. For example, it could be comprised of (1) add eax, 0 represents 0 and (2) mul eax, 1 represents 1. Then each time the receiver saw one of these instructions in the executable he would check to see if it represented a stall, if so then he found a bit of the message. Without the codebook the receiver would not know which instructions could be part of the code or what value the instruction represented. Extraction module 408 will next extract the message elements contained in each instruction found by the message locator module and assemble them into an encoded message. A message decoder 410 will then decode the message and generate the original message 412, which may be, in machine-readable or human-readable form. The message decoder 410 may use a conventional decryption technique that corresponds to the encryption technique used by the encoder 210 shown in FIG. 2. The executable code 414 has not been functionally altered by the message extraction system 400, so it may continue to be used for its original purpose, or may be used again to encode another secret message in accordance with the above-described techniques. It may be noted that with information hiding techniques, it is harder to get the information out then it is to put it in. To extract the message the message locator 406 may simply scan the message looking for instructions which are known to represent bits of the message. This knowledge may come from the previously provided code book. However, it is possible that this technique could result in extraneous bits. To provide a more accurate message recovery, some embodiments of the invention may perform some data dependency analysis. That is, the message locator 406 may check to see if the removal of an identified instruction would result in a pipeline stall. If so, then the message extraction system 400 will decode the instruction to its corresponding bit, otherwise it will ignore the instruction. An important parameter associated with code steganography techniques relates to the potential data rate. The resulting data rate achieved by the present invention will be determined by the number of stalls in the pipeline. Hence, it will be useful to analyze the executable code to determine the number of stalls available to receive parts of the secret message. In some cases this may be done by counting the number of nops and using this information to calculate a potential data rate. FIG. 5 shows a flow chart of a process 500 for extracting a message in executable code in accordance with one embodiment of the invention. In step 502 the executable code containing the embedded secret encoded message is received, for example, by the message extractor 404. In step 504 the first and subsequent instructions are selected one at a time. Step 506 determines if the selected instruction is an instruction that represents bits of the secret message. This may be done for example, by determining if the instruction corresponds to information given in the code book. If it is not, the process returns to step 504 and the next instruction is selected. If step 506 determines that the instruction represents bits of the secret message, the process may optionally moves to step 508, which may perform data dependency analysis. For example this step may involve a check to determine if the removal of an identified instruction would result in a pipeline stall. If removal would result in pipeline stall there is a greater degree of certainty that the instruction contains parts of the secret message. In some embodiments, step 508 may be skipped; however, there is a greater chance of extraneous bits being included with the secret message. In step 510 the instruction is added to the secret message. Step 512 then determines if the last instruction has been analyzed. If not, the process returns to step 504 and the next instruction is selected. Once all the instructions have been processed then step 514 decodes the message using information from the code book. The decided message is then output for reading in step 516. In addition to using the present invention for secret communication or for watermarking/fingerprinting, the present invention can also be used for encoding a digital signature of executable code. This can be done by computing the signature with the nop instruction in place and encoding the signature in the executable. One way to verify the signature is to extract the signature from the code, replace the message contributing instructions with nop instructions, compute the signature for the executable, and verify. For fixed length instruction sets this has the advantage of digital signature protection without an increase in executable size. In accordance with the present invention, we have disclosed systems and methods for encoding information in an instruction processing pipeline. Those of ordinary skill in the art will appreciate that the teachings contained herein can be implemented in many applications in addition to those discussed above where there is a need for secret communication, watermarking, fingerprinting and digital signatures. References in the claims to an element in the singular is not intended to mean “one and only” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described exemplary embodiment that are currently known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the present claims. No clam element herein is to be construed under the provisions of 35 U.S.C. section 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or “step for.” While the preferred embodiments of the present invention have been described in detail, it will be understood that modifications and adaptations to the embodiments shown may occur to one of ordinary skill in the art without departing from the scope of the present invention as set forth in the following claims. Thus, the scope of this invention is to be construed according to the appended claims and not limited by the specific details disclosed in the exemplary embodiments.	G	60G06	161G06F	21	00
11841611	US20090055583A1-20090226	STORING REDUNDANT SEGMENTS AND PARITY INFORMATION FOR SEGMENTED LOGICAL VOLUMES	ACCEPTED	20090212	20090226	[]	G06F1216	["G06F1216", "G06F1200", "G06F1300"]	7877544	20070820	20110125	711	114000	68066.0	DAVIDSON	CHAD	[{"inventor_name_last": "Kishi", "inventor_name_first": "Gregory Tad", "inventor_city": "Oro Valley", "inventor_state": "AZ", "inventor_country": "US"}]	Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that has a plurality of segments created by the storage manager application. At least one additional copy of at least one of the plurality of segments is maintained in at least one linear storage medium of a secondary storage. A request for data is received, at the first computational device, from a second computational device. At least one of the plurality of segments and the at least one additional copy are used to respond to the received request for data.	1. A method, comprising: maintaining, by a storage manager application implemented in a first computational device a virtual logical volume having a plurality of segments created by the storage manager application; maintaining at least one additional copy of at least one of the plurality of segments in at least one linear storage medium of a secondary storage; receiving a request for data, at the first computational device, from a second computational device; and using at least one of the plurality of segments and the at least one additional copy to respond to the received request for data. 2. The method of claim 1, further comprising: maintaining parity information in association with the plurality of segments; using the parity information, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. 3. The method of claim 2, further comprising: storing the parity information of a group of segments of the plurality of segments in a separate segment. 4. The method of claim 1, wherein recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. 5. The method of claim 1, wherein the first computational device is a virtual tape server; wherein the second computational device is a host; wherein a cache storage coupled to the virtual tape server is implemented in a disk device; wherein a secondary storage coupled to the virtual tape server is implemented in a tape device; and wherein the linear storage medium is a tape in the tape device. 6. A system, comprising: a memory; and a processor coupled to the memory, wherein the processor performs operations, the operations comprising: (i) maintaining, by a storage manager application implemented in a first computational device a virtual logical volume having a plurality of segments created by the storage manager application; (ii) maintaining at least one additional copy of at least one of the plurality of segments in at least one linear storage medium of a secondary storage; (iii) receiving a request for data, at the first computational device, from a second computational device; and (iv) using at least one of the plurality of segments and the at least one additional copy to respond to the received request for data. 7. The system of claim 6, the operations further comprising: maintaining parity information in association with the plurality of segments; using the parity information, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. 8. The system of claim 7, the operations further comprising: storing the parity information of a group of segments of the plurality of segments in a separate segment. 9. The system of claim 6, wherein recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. 10. The system of claim 6, wherein the first computational device is a virtual tape server; wherein the second computational device is a host; wherein a cache storage coupled to the virtual tape server is implemented in a disk device; wherein a secondary storage coupled to the virtual tape server is implemented in a tape device; and wherein the linear storage medium is a tape in the tape device. 11. An article of manufacture including code, wherein the code when executed by a machine causes operations to be performed, the operations comprising: maintaining, by a storage manager application implemented in a first computational device a virtual logical volume having a plurality of segments created by the storage manager application; maintaining at least one additional copy of at least one of the plurality of segments in at least one linear storage medium of a secondary storage; receiving a request for data, at the first computational device, from a second computational device; and using at least one of the plurality of segments and the at least one additional copy to respond to the received request for data. 12. The article of manufacture of claim 11, the operations further comprising: maintaining parity information in association with the plurality of segments; using the parity information, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. 13. The article of manufacture of claim 12, the operations further comprising: storing the parity information of a group of segments of the plurality of segments in a separate segment. 14. The article of manufacture of claim 11, wherein recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. 15. The article of manufacture of claim 11, wherein the first computational device is a virtual tape server; wherein the second computational device is a host; wherein a cache storage coupled to the virtual tape server is implemented in a disk device; wherein a secondary storage coupled to the virtual tape server is implemented in a tape device; and wherein the linear storage medium is a tape in the tape device. 16. A method for deploying computing infrastructure, comprising integrating computer-readable code into a first computational device, wherein the code in combination with the first computational device is capable of performing: maintaining, by a storage manager application implemented in the first computational device a virtual logical volume having a plurality of segments created by the storage manager application; maintaining at least one additional copy of at least one of the plurality of segments in at least one linear storage medium of a secondary storage; receiving a request for data, at the first computational device, from a second computational device; and using at least one of the plurality of segments and the at least one additional copy to respond to the received request for data. 17. The method for deploying computing infrastructure of claim 16, wherein the code in combination with the first computational device is further capable of performing: maintaining parity information in association with the plurality of segments; using the parity information, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. 18. The method for deploying computing infrastructure of claim 17, wherein the code in combination with the first computational device is further capable of performing: storing the parity information of a group of segments of the plurality of segments in a separate segment. 19. The method for deploying computing infrastructure of claim 16, wherein recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. 20. The method for deploying computing infrastructure of claim 16, wherein the first computational device is a virtual tape server; wherein the second computational device is a host; wherein a cache storage coupled to the virtual tape server is implemented in a disk device; wherein a secondary storage coupled to the virtual tape server is implemented in a tape device; and wherein the linear storage medium is a tape in the tape device.	<SOH> BACKGROUND <EOH>1. Field The disclosure relates to a method, system, and article of manufacture for storing redundant segments and parity information for segmented logical volumes. 2. Background In certain virtual tape storage systems, hard disk drive storage may be used to emulate tape drives and tape cartridges. For instance, host systems may perform input/output (I/O) operations with respect to a tape library by performing I/O operations with respect to a set of hard disk drives that emulate the tape library. In certain virtual tape storage systems at least one virtual tape server (VTS) is coupled to a tape library comprising numerous tape drives and tape cartridges. The VTS is also coupled to a direct access storage device (DASD), comprised of numerous interconnected hard disk drives. The DASD functions as a cache to volumes in the tape library. In VTS operations, the VTS processes the host's requests to access a volume in the tape library and returns data for such requests, if possible, from the cache. If the volume is not in the cache, then the VTS recalls the volume from the tape library to the cache, i.e., the VTS transfers data from the tape library to the cache. The VTS can respond to host requests for volumes that are present in the cache substantially faster than requests for volumes that have to be recalled from the tape library to the cache. However, since the capacity of the cache is relatively small when compared to the capacity of the tape library, not all volumes can be kept in the cache. Hence, the VTS may migrate volumes from the cache to the tape library, i.e., the VTS may transfer data from the cache to the tape cartridges in the tape library.	<SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that has a plurality of segments created by the storage manager application. At least one additional copy of at least one of the plurality of segments is maintained in at least one linear storage medium of a secondary storage. A request for data is received, at the first computational device, from a second computational device. At least one of the plurality of segments and the at least one additional copy are used to respond to the received request for data. In further embodiments, parity information is maintained in association with the plurality of segments. The parity information is used, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. In yet further embodiments, the parity information of a group of segments of the plurality of segments is stored in a separate segment. In additional embodiments, recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. In yet additional embodiments, the first computational device is a virtual tape server and the second computational device is a host, wherein a cache storage coupled to the virtual tape server is implemented in a disk device, wherein a secondary storage coupled to the virtual tape server is implemented in a tape device, and wherein the linear storage medium is a tape in the tape device.	BACKGROUND 1. Field The disclosure relates to a method, system, and article of manufacture for storing redundant segments and parity information for segmented logical volumes. 2. Background In certain virtual tape storage systems, hard disk drive storage may be used to emulate tape drives and tape cartridges. For instance, host systems may perform input/output (I/O) operations with respect to a tape library by performing I/O operations with respect to a set of hard disk drives that emulate the tape library. In certain virtual tape storage systems at least one virtual tape server (VTS) is coupled to a tape library comprising numerous tape drives and tape cartridges. The VTS is also coupled to a direct access storage device (DASD), comprised of numerous interconnected hard disk drives. The DASD functions as a cache to volumes in the tape library. In VTS operations, the VTS processes the host's requests to access a volume in the tape library and returns data for such requests, if possible, from the cache. If the volume is not in the cache, then the VTS recalls the volume from the tape library to the cache, i.e., the VTS transfers data from the tape library to the cache. The VTS can respond to host requests for volumes that are present in the cache substantially faster than requests for volumes that have to be recalled from the tape library to the cache. However, since the capacity of the cache is relatively small when compared to the capacity of the tape library, not all volumes can be kept in the cache. Hence, the VTS may migrate volumes from the cache to the tape library, i.e., the VTS may transfer data from the cache to the tape cartridges in the tape library. SUMMARY OF THE PREFERRED EMBODIMENTS Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that has a plurality of segments created by the storage manager application. At least one additional copy of at least one of the plurality of segments is maintained in at least one linear storage medium of a secondary storage. A request for data is received, at the first computational device, from a second computational device. At least one of the plurality of segments and the at least one additional copy are used to respond to the received request for data. In further embodiments, parity information is maintained in association with the plurality of segments. The parity information is used, in addition to the at least one of the plurality of segments and the at least one additional copy, to respond to the request for data. In yet further embodiments, the parity information of a group of segments of the plurality of segments is stored in a separate segment. In additional embodiments, recall efficiency for the data is increased by maintaining the at least one additional copy of the at least one of the plurality of segments in the at least one linear storage medium of the secondary storage. In yet additional embodiments, the first computational device is a virtual tape server and the second computational device is a host, wherein a cache storage coupled to the virtual tape server is implemented in a disk device, wherein a secondary storage coupled to the virtual tape server is implemented in a tape device, and wherein the linear storage medium is a tape in the tape device. BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings in which like reference numbers represent corresponding parts throughout: FIG. 1 illustrates a block diagram of a computing environment, in accordance with certain embodiments; FIG. 2 illustrates a block diagram of representations of a virtual logical volume in accordance with certain embodiments; FIG. 3 illustrates a block diagram that shows a first exemplary mapping of the segments of an exemplary virtual logical volume to exemplary tapes of a secondary storage, in accordance with certain embodiments; FIG. 4 illustrates a block diagram that shows a second exemplary mapping of the segments of an exemplary virtual logical volume to exemplary tapes of a secondary storage, in accordance with certain embodiments; FIG. 5 illustrates a block diagram that shows a third exemplary mapping of the segments of an exemplary virtual logical volume to exemplary tapes of a secondary storage, in accordance with certain embodiments; FIG. 6 illustrates operations implemented in the computing environment, in accordance with certain embodiments; and FIG. 7 illustrates a block diagram of a computer architecture in which certain described aspects of the embodiments are implemented. DETAILED DESCRIPTION In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made. Handling Logical Volumes a Single Entity In certain VTS systems, logical volumes are handled as a single entity. However, when the size of physical volumes corresponding to logical volumes becomes very large, such as in Linear Tape Open (LTO) drives, all data included in logical volumes may not be accommodated at the same time in the cache storage. Additionally, transfer operations of large logical volumes from the secondary storage to the cache storage may take a significantly greater amount of time in comparison to small logical volumes. The recall times for data may become excessively large in situations where logical volumes are handled as a single entity for transfer to the cache storage from the secondary storage in a VTS environment. Exemplary Embodiments Certain embodiments provide for the segmentation of virtual logical volumes in a VTS environment comprising a VTS that is coupled to a cache storage and a secondary storage, wherein the segmented virtual logical volumes are used to respond to data requests from a host. In certain embodiments the segments corresponding to the virtual logical volume are distributed among a plurality of tapes, wherein redundant segments are also stored in at least one or more of the plurality of tapes for recall efficiency, and wherein parity segments may also be stored in at least one or more of the plurality of tapes for further data redundancy. If a recall of a segmented virtual logical volume fails because of bad data on a certain tape, then the redundant and/or parity segments stored in one or more other tapes may be used for data recovery. It should be noted that by distributing segments corresponding to the virtual logical volume in a plurality of tapes, by storing additional copies of segments, and by storing parity data, both recall efficiency and data redundancy may be achieved. In certain embodiments fully redundant write of data segments onto tape is not performed. In such embodiments, parity provides the data protection redundancy, whereas the redundant segments provide recall efficiency by permitting fewer tapes to be mounted for responding to a request for data. FIG. 1 illustrates a block diagram of a computing environment 100, in accordance with certain embodiments. The computing environment 100 includes a VTS 102. Additional VTSs can be deployed, but for purposes of illustration, a single VTS 102 is shown. In certain exemplary embodiments the VTS 102 may comprise a server computational device and may include any operating system known in the art. However, in alternative embodiments the VTS 102 may comprise any suitable computational device, such as a personal computer, a workstation, mainframe, a hand held computer, a palm top computer, a telephony device, network appliance, etc. The VTS 102 may be referred to as a first computational device 102. The computing environment 100 also includes a host 104 that is coupled to the VTS 102. Additional hosts may be deployed, but for purposes of illustration, a single host 104 is shown. The host 104 may be may coupled to the VTS 102 through a host data interface channel or any other direct connection or switching mechanism, known in the art (e.g., fibre channel, Storage Area Network (SAN) interconnections, etc.). The host 104 may be any suitable computational device known in the art, such as a personal computer, a workstation, a server, a mainframe, a hand held computer, a palm top computer, a telephony device, network appliance, etc. The VTS 102 includes at least one application, such as a storage manager application 106 that manages storage. The storage manager application 106 may be implemented either as a standalone application or as a part of one or more other applications. The storage manager application 106 manages a cache storage 108, such as a disk based storage system, and a secondary storage 110 comprising a plurality of linear storage media 112a, 112b, . . . , 112n, wherein in certain embodiments the linear storage media may comprise tapes. The cache storage 108 and the secondary storage 110 are coupled to the VTS 102 via a direct connection or via a network connection. The cache storage 108 improves performance by allowing host I/O requests from the hosts 104 to the secondary storage 110 to be serviced from the faster access cache storage 108 as opposed to the slower access secondary storage 110. The disks in the cache storage 108 may be arranged as a Direct Access Storage Device (DASD), Just a Bunch of Disks (JBOD), Redundant Array of Inexpensive Disks (RAID), etc. The storage manager application 106 may perform or manage the data movement operations between the host 104, the cache storage 108, and the secondary storage 110. The storage manager application 106 generates virtual logical volumes 114, wherein virtual logical volumes 114 are logical representations of data stored in cache storage 108 and the secondary storage 110. The storage manager application 106 maps the data stored in the cache storage 108 and secondary storage 110 to a plurality of virtual logical volumes 114. The hosts 104 perform I/O operations by using the virtual logical volumes 114 via the VTS 102. The storage manager application 106 maps the virtual logical volumes 114 to the linear storage media 112a . . . 112n of the secondary storage 110. In certain embodiments, the storage manager application 106 maps segments of an exemplary virtual logical volume to corresponding segments 116a, 116b, . . . 116n in the linear storage media 112a . . . 112n, and also creates additional segments 118a, 118b, . . . 118n and parity segments 120a,120b, . . . 120n in the linear storage media 112a . . . 112n. An additional segment stored on a linear storage medium may comprise a copy of a segment stored on another linear storage medium. For example, an additional segment 118a stored on linear storage medium 112a may in certain embodiments comprise a copy of one of the segments 116b stored in the linear storage medium 112b. A parity segment stores the parity corresponding to a plurality of segments. For example, in certain embodiments the parity segment 120a may store the parity data generated from segment 116b and 116n. While FIG. 1 shows additional segments and parity segments on each of the linear storage media 112a, 112b, 112n, in alternative embodiments one or more of the linear storage media may lack additional segments or parity segments. In certain embodiments the storage manager application 106 implemented in the first computational device 102 maintains a virtual logical volume 114 that has a plurality of segments created by the storage manager application 106. At least one additional copy 118a of at least one of the plurality of segments is maintained in at least one linear storage medium 112a of a secondary storage 110. A request for data is received, at the first computational device 102, from a second computational device 104. At least one of the plurality of segments and the at least one additional copy 11 8a are used to respond to the received request for data. In further embodiments, parity information is maintained in parity segments associated with the plurality of segments in the secondary storage 110. The parity information stored in a parity segment, such as parity segment 120b, may be used, in addition to the at least one of the plurality of segments and the at least one additional copy 118a, to respond to the request for data. FIG. 2 illustrates a block diagram of an exemplary representation of a virtual logical volume in accordance with certain embodiments that may be implemented in the computing environment 100. One representation 200 of the virtual logical volume 114 of FIG. 1 may comprise a plurality of segments 202a, 202b, 202c, . . . 202n, wherein a segment is a unit of data storage. A greater or a fewer number of segments than shown in FIG. 2 may be implemented in certain embodiments. In certain embodiments, the segments 202a, 202b, 202c, . . . , 202n of the virtual logical volumes 114 are stored in the linear storage media 112a . . . 112n of the secondary storage 110, along with the additional segments 118a . . . 118n and the parity segments 120a . . . 120n. FIG. 3 illustrates a block diagram that shows a first exemplary mapping 300 of the segments of an exemplary virtual logical volume 302 to exemplary tapes of an exemplary secondary storage 304, in accordance with certain embodiments. The first exemplary mapping 300 is shown for illustrative purposes only and other exemplary mappings including those that are described elsewhere in this disclosure may be used in alternative embodiments. In FIG. 3, the exemplary virtual logical volume 302 is comprised of three segments referred to as segment A 306, segment B 308, and segment C 310. In an exemplary embodiment, the three segments 306, 308, 310 are stored by the storage manager application 106 in an exemplary first tape 312, an exemplary second tape 314 and an exemplary third tape 316 as shown. The storage manager application 106 stores in the exemplary first tape 312 the segment A 306, a copy 318 of segment B 308, and a parity segment 320 that may comprise parity data computed from some or all of the plurality of segments 306, 308, 310. The storage manager application 106 further stores in the exemplary second tape 314 the segment B 308, a copy 322 of segment C 310, and a parity segment 324 that may comprise parity data computed from some or all of the plurality of segments 306, 308, 310. The storage manager application 106 also stores in the exemplary third tape 316 the segment C 310, a copy 326 of segment A 306, and a parity segment 328 that may comprise parity data computed from some or all of the plurality of segments 306, 308, 310. In certain embodiments one or more the exemplary tapes 312, 314, 316 may be mounted for recalling data stored in the segments 306, 308, 310 of the virtual logical volume 302. By storing additional copies 318, 322, 326 recall efficiency is increased in comparison to embodiments where additional copies are not stored in the tapes. For example, in FIG. 3, mounting any two of the three tapes 312, 314, 316 is adequate for recalling all segments 306, 308, 310 of the virtual logical volume 302 even when no parity segments are stored. Also, all segments 306, 308, 310 may be recalled by mounting the exemplary first tape 312 and the exemplary third tape 316 even when no parity segments are stored. In certain embodiments where a tape is defective, the parity segments stored in the tapes that are not defective may be used to recover data. In FIG. 2, recall efficiency of the virtual logical volume 302 is increased by storing the copies 318, 322, 324. As a result of storing the copies 318, 322, 324, two tapes (instead of three) are adequate to recall all the segments 306, 308, 310. Additionally, even if a tape is defective, the data corresponding to the virtual logical volume 302 can be recalled from the other two tapes. The parity data provides further data protection in case of loss of a tape. FIG. 4 illustrates a block diagram that shows a second exemplary mapping 400 of the segments “ABCDEF” 402a of an exemplary virtual logical volume 402 to exemplary tapes 404a, 404b, 404c, 404d of an exemplary secondary storage 404, in accordance with certain embodiments. In the second exemplary mapping 400, duplicative segments (i.e. copies of segments) are not present in the tapes. The storage manager application 106 stores segments and parity on the tapes 404a, 404b, 404c, 404d as follows: (1) First Tape (reference numeral 404a) stores segment A (reference numeral 406) and segment D (reference numeral 408); (2) Second tape (reference numeral 404b) stores segment B (reference numeral 410) and segment E (reference numeral 412); (3) Third tape (reference numeral 404c) stores segment C (reference numeral 414) and segment F (reference numeral 416); and (4) Fourth tape (reference numeral 404d) stores parity segment P(ABC) (reference numeral 418) and parity segment P(DEF) (reference numeral 420), wherein P(ABC) (reference numeral 418) is a parity segment that stores the parity data corresponding to segments A, B,C, and P(DEF) is a parity segment that stores the parity data corresponding to segments D, E, F. The storage manager application 106 may need to mount the first tape 404a, second tape 404b, and third tape 404c to recall data corresponding to the virtual logical volume 404. The fourth tape 404d may be mounted if one of the first, second, and third tape 404a, 404b, 404c is defective. FIG. 5 illustrates a block diagram that shows a third exemplary mapping 500 of the segments “ABCDEF” 502a of an exemplary virtual logical volume 502 to exemplary tapes 504a, 504b, 504c, 504d of an exemplary secondary storage 504, in accordance with certain embodiments. In the second exemplary mapping 500, duplicative segments (i.e. copies of segments) are present in the tapes. The storage manager application 106 stores segments and parity information on the tapes 504a, 504b, 504c, 504d as follows: (1) First Tape (reference numeral 504a) stores segment A (reference numeral 506), segment D (reference numeral 508), and segment C (reference numeral 510); (2) Second tape (reference numeral 504b) stores segment B (reference numeral 512), segment E (reference numeral 514), and segment F (reference numeral 516); (3) Third tape (reference numeral 504c) stores segment C (reference numeral 518) and segment F (reference numeral 520); and (4) Fourth tape (reference numeral 504d) stores parity segment P(ABC) (reference numeral 522) and parity segment P(DEF) (reference numeral 524), wherein P(ABC) (reference numeral 522) is a parity segment that stores the parity data corresponding to segments A, B, C, and P(DEF) (reference numeral 524) is a parity segment that stores the parity data corresponding to segments D, E, F. In FIG. 5, the storage manager application 106 may need to mount the first tape 504a and the second tape 504b to recall data corresponding to the virtual logical volume 404. One or more of the other tapes 504c, 504d may have to be mounted if either the first tape 504a or the second tape 504b is defective. In the embodiment described in FIG. 5, by storing the segments of the virtual logical volume redundantly, e.g., by storing segment C is both the first tape 504a and the third tape 504c, recall efficiency is increased in comparison to the embodiment described in FIG. 4 where the segments of the virtual logical volume are not stored redundantly. FIG. 6 illustrates operations implemented in the computing environment 100, in accordance with certain embodiments. In certain embodiments, the operations may be performed by the storage manager application 106 implemented in the first computational device 102. Control starts at block 600, where the storage manager application 106, implemented in the first computational device 102 maintains a virtual logical volume 114 having a plurality of segments created by the storage manager application 106. The storage manager application 106 maintains (at block 602) at least one additional copy 118a of at least one of the plurality of segments in at least one linear storage medium 112a of a secondary storage 110. In certain embodiments, the storage manager application 106 also maintains (at block 604) parity information in association with the plurality of segments, and in certain additional embodiments the storage manager application 106 stores the parity information of a group of segments of the plurality of segments in a separate segment. Control proceeds to block 606, where the storage manager application 106 receives a request for data corresponding to a virtual logical volume 114, at the first computational device 102. The request may have arrived at the first computational device 102 from a second computational device 104. The storage manager application 106 uses (at block 608) at least one of the plurality of segments and the at least one additional copy 11 8a and optionally the parity information to respond to the received request for data. Therefore, FIG. 6 illustrates certain embodiments wherein segments corresponding to a virtual logical volume are redundantly distributed among a plurality of linear storage media. Parity information corresponding to the segments may also be stored on one or more of linear storage media. The redundantly distributed segments provide recall efficiency because fewer linear storage media may have to be mounted to recall data. The distribution of the segments among a plurality of linear storage media and the storage of the parity information may also provide protection against loss of data on one or more linear storage media. In certain embodiments the distribution of segments may provide partial redundancy whereas in other embodiments the distribution of segments may provide complete redundancy. The parity information provides additional redundancy protection beyond that provided by the redundant distribution of segments in the plurality of linear storage media. Additional Embodiment Details The described techniques may be implemented as a method, apparatus or article of manufacture involving software, firmware, micro-code, hardware and/or any combination thereof. The term “article of manufacture” as used herein refers to code or logic implemented in a medium, where such medium may comprise hardware logic [e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.] or a computer readable storage medium, such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, optical disks, etc.), volatile and non-volatile memory devices [e.g., Electrically Erasable Programmable Read Only Memory (EEPROM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, firmware, programmable logic, etc.]. Code in the computer readable storage medium is accessed and executed by a processor. The medium in which the code or logic is encoded may also comprise transmission signals propagating through space or a transmission media, such as an optical fiber, copper wire, etc. The transmission signal in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signal in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices. Additionally, the “article of manufacture” may comprise a combination of hardware and software components in which the code is embodied, processed, and executed. Of course, those skilled in the art will recognize that many modifications may be made without departing from the scope of embodiments, and that the article of manufacture may comprise any information bearing medium. For example, the article of manufacture comprises a storage medium having stored therein instructions that when executed by a machine results in operations being performed. Certain embodiments can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, certain embodiments can take the form of a computer program product accessible from a computer usable or computer readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk - read only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD. The terms “certain embodiments”, “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean one or more (but not all) embodiments unless expressly specified otherwise. The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise. [0047] Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries. Additionally, a description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments. Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously, in parallel, or concurrently. When a single device or article is described herein, it will be apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be apparent that a single device/article may be used in place of the more than one device or article. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments need not include the device itself. FIG. 7 illustrates the architecture of computing system 700, wherein in certain embodiments the VTS 102 and the hosts 104 of the computing environments 100 of FIG. 1 may be implemented in accordance with the architecture of the computing system 700. The computing system 700 may also be referred to as a system, and may include a circuitry 702 that may in certain embodiments include a processor 704. The system 700 may also include a memory 706 (e.g., a volatile memory device), and storage 708. The storage 708 may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage 708 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 700 may include a program logic 710 including code 712 that may be loaded into the memory 706 and executed by the processor 704 or circuitry 702. In certain embodiments, the program logic 710 including code 712 may be stored in the storage 708. In certain other embodiments, the program logic 710 may be implemented in the circuitry 702. Therefore, while FIG. 7 shows the program logic 710 separately from the other elements, the program logic 710 may be implemented in the memory 706 and/or the circuitry 702. Certain embodiments may be directed to a method for deploying computing instruction by a person or automated processing integrating computer-readable code into a computing system, wherein the code in combination with the computing system is enabled to perform the operations of the described embodiments. At least certain of the operations illustrated in FIGS. 1-7 may be performed in parallel as well as sequentially. In alternative embodiments, certain of the operations may be performed in a different order, modified or removed. Furthermore, many of the software and hardware components have been described in separate modules for purposes of illustration. Such components may be integrated into a fewer number of components or divided into a larger number of components. Additionally, certain operations described as performed by a specific component may be performed by other components. The data structures and components shown or referred to in FIGS. 1-7 are described as having specific types of information. In alternative embodiments, the data structures and components may be structured differently and have fewer, more or different fields or different functions than those shown or referred to in the figures. Therefore, the foregoing description of the embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.	G	60G06	161G06F	12	16
11872430	US20080033600A1-20080207	AUTOMATED PART PROCUREMENT AND SERVICE DISPATCH	ACCEPTED	20080123	20080207	[]	G06F1900	["G06F1900"]	7424345	20071015	20080909	700	107000	98614.0	RAPP	CHAD	[{"inventor_name_last": "Norbeck", "inventor_name_first": "Dean", "inventor_city": "Marco Island", "inventor_state": "FL", "inventor_country": "US"}]	A method for repairing an HVAC system is disclosed. The method includes monitoring a plurality of sensors positioned throughout the HVAC system and receiving data associated therewith, determining whether the data received from the plurality of sensors is within corresponding predetermined operational parameters, analyzing data determined to be outside the corresponding predetermined operational parameters to diagnose a malfunction of the HVAC system, accessing an on-board bill of materials to determine a proper replacement part to correct the malfunction, automatically ordering the replacement part, and automatically dispatching a service technician to install the replacement part.	1. A method for repairing an HVAC system comprising the steps of: monitoring a plurality of sensors positioned throughout the HVAC system; receiving data associated with the sensors outside of predetermined operational parameters; identifying a malfunction of the HVAC system corresponding to the received data outside of the corresponding predetermined operational parameters; accessing an on-board bill of replaceable HVAC system materials to determine a proper replacement part to correct the malfunction; automatically ordering the replacement part; and automatically dispatching a service technician to repair the HVAC system. 2. The method of claim 1, wherein the step of automatically ordering the replacement part comprises initiating a communication to a parts center via a communications port, and ordering the replacement part from the parts center for delivery to the HVAC system. 3. The method of claim 1, further comprising determining an arrival date of the ordered replacement part at the location of the HVAC system from a first parts center; and determining whether an HVAC system failure will occur prior to the determined arrival date. 4. The method of claim 3, further comprising dispatching a service technician to the HVAC system before the determined arrival date in response to determining the HVAC system failure will occur prior to the determined arrival date. 5. The method of claim 3, further comprising canceling an automatically ordered replacement part from a first parts center and automatically ordering a replacement part from a second parts center in response to determining the arrival date from the first parts center. 6. The method of claim 1, wherein the monitoring a plurality of sensors comprises monitoring sensors selected from the group of temperature sensors, pressure sensors, vibration sensors, current sensors, voltages sensors, and combinations thereof. 7. The method of claim 1, wherein the step of automatically ordering the replacement part comprises electronically ordering the replacement part from a parts center. 8. The method of claim 1 further comprising the step of automatically advising a point of contact associated with the HVAC system of the HVAC system malfunction. 9. The method of claim 1 further comprising recording a log of the data determined to be outside the corresponding predetermined operational parameters; and remotely accessing, by a service technician, the log of the data determined to be outside the corresponding predetermined operational parameters. 10. The method of claim 1 further comprising updating the on-board bill of materials to include the replacement part.	<SOH> BACKGROUND OF THE INVENTION <EOH>Commercial heating, ventilation and air conditioning (HVAC) units, such as aptly named “rooftop units,” are often assembled onto the flat roofs of structures such as supermarkets, office buildings and other commercial structures. Chillers, or chilled water units, are cost-effective systems that utilize both water or other suitable liquids and refrigerants. Chillers cool the water or other liquid, then circulate the cooled water to other components in the system, such as an air handling unit. Chillers are typically located in equipment rooms such as in basements or at other remote locations of large buildings. Water is an excellent secondary coolant because it is readily available, inexpensive, non-toxic and substantially non-corrosive. It also has a favorable specific heat value. Other secondary coolants can also be used, depending upon the application. These include calcium chloride or sodium chloride brines, methanol, propylene glycols, ethylene glycol and glycerin. Chillers are frequently used for commercial air conditioning and industrial process cooling as well as for low temperature refrigeration. While there are various types of chillers, which may include many different components, a chiller typically includes a compressor, a motor and a control center, which may be in the form of a microprocessor control. A chiller can also include, in addition to the above equipment, a condenser, an evaporator and a metering device. Due to their sometimes difficult-to-reach locations, servicing chillers and rooftop units can be time consuming and inefficient, particularly if a service technician must make multiple trips to diagnose and later return with proper parts to effect a repair. However, most current methods of monitoring the operation of chillers, rooftop units of air conditioning systems, or other HVAC systems do not provide the capability to diagnose an existing problem or anticipate the occurrence of a problem that could result in shut down or improper operation of equipment and to arrange for that problem to be repaired. What is needed is a system for monitoring an HVAC system that utilizes information from the control center of the unit to automatically identify a malfunctioning part causing a problem, place an order for that part, and dispatch a service technician to install the replacement part upon its arrival.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is a method and system for monitoring operations of a heating ventilating and air conditioning (HVAC) system such as a chiller system or a rooftop unit having a control center, and upon occurrence of a malfunction or other system failure, to automatically order needed replacement parts and dispatch a service technician to install the parts and make the repair. The system utilizes a control center located on-site, that is to say, at the facilities at which the chiller system or rooftop unit is located. The control center is in one-way communication with sensors configured to monitor components of the chiller system and receives data indicative of the operation of each of the components. The control center determines whether each component is operating within the normal operating parameters and stores data indicative of component operation in memory. If the data indicates that the HVAC system component is operating outside of normal parameters, a processing unit in the control center evaluates the information and determines whether remedial action is required. If a malfunction has occurred and remedial action is required, the control center determines the remedial action needed to correct the malfunction, including accessing a bill of materials to determine a proper replacement part. The processing unit then initiates a communication to order the replacement part from a repair center and dispatches a service technician to perform the repair. A method for repairing an HVAC system is disclosed. The method comprises the steps of monitoring a plurality of sensors positioned throughout the HVAC system and receiving data associated therewith, determining whether the data received from the plurality of sensors is within corresponding predetermined operational parameters, conducting a diagnosis of the HVAC system to identify a malfunction of the HVAC system in response to having data determined to be outside the corresponding predetermined operational parameters, accessing an on-board bill of materials to determine a proper replacement part to correct the malfunction, automatically ordering the replacement part, and automatically dispatching a service technician to install the replacement part. A system for automatically procuring parts and dispatching a service technician to repair an HVAC system is also disclosed. The system comprises a plurality of sensors positioned throughout the HVAC system and an HVAC system control center in communication with the plurality of sensors, the control center comprising a microprocessor, a memory and a communications port. The microprocessor comprises computer instructions to execute the steps of monitoring data received from the plurality of sensors, comparing the received data against pre-determined operational parameters, analyzing data outside of the operational parameters to determine an HVAC system malfunction, accessing an on-board bill of materials from the memory to identify a replacement part based on the data analysis to correct the HVAC system malfunction, initiating a call to a parts center via the communications port to order the replacement part, and initiating a call via the communications port to dispatch a service technician to install the replacement part. One advantage of exemplary embodiments of the present invention is that the HVAC system can perform a self-diagnosis and in response to that diagnosis, automatically order a replacement part without the need for a service technician to make a diagnostic visit and a subsequent repair visit to install the part in the malfunctioning system. Another advantage of exemplary embodiments of the present invention is the ability to reference an on-board bill of materials stored in memory to automatically determine a proper replacement part in light of a self-diagnosis by the HVAC system. Still another advantage of exemplary embodiments of the present invention is direct communication by the HVAC system to order replacement parts and dispatch a service technician without the need to route communications through a central HVAC service center or other intermediary. Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 11/388,502, filed Mar. 24, 2006, allowed, which is incorporated by reference in its entirety. FIELD OF THE INVENTION The present invention is directed to self-diagnosis of malfunctioning equipment and more particularly directed to automatically procuring replacement parts for use in the repair of malfunctioning equipment and the coordinated dispatching of a service technician to perform the repair. BACKGROUND OF THE INVENTION Commercial heating, ventilation and air conditioning (HVAC) units, such as aptly named “rooftop units,” are often assembled onto the flat roofs of structures such as supermarkets, office buildings and other commercial structures. Chillers, or chilled water units, are cost-effective systems that utilize both water or other suitable liquids and refrigerants. Chillers cool the water or other liquid, then circulate the cooled water to other components in the system, such as an air handling unit. Chillers are typically located in equipment rooms such as in basements or at other remote locations of large buildings. Water is an excellent secondary coolant because it is readily available, inexpensive, non-toxic and substantially non-corrosive. It also has a favorable specific heat value. Other secondary coolants can also be used, depending upon the application. These include calcium chloride or sodium chloride brines, methanol, propylene glycols, ethylene glycol and glycerin. Chillers are frequently used for commercial air conditioning and industrial process cooling as well as for low temperature refrigeration. While there are various types of chillers, which may include many different components, a chiller typically includes a compressor, a motor and a control center, which may be in the form of a microprocessor control. A chiller can also include, in addition to the above equipment, a condenser, an evaporator and a metering device. Due to their sometimes difficult-to-reach locations, servicing chillers and rooftop units can be time consuming and inefficient, particularly if a service technician must make multiple trips to diagnose and later return with proper parts to effect a repair. However, most current methods of monitoring the operation of chillers, rooftop units of air conditioning systems, or other HVAC systems do not provide the capability to diagnose an existing problem or anticipate the occurrence of a problem that could result in shut down or improper operation of equipment and to arrange for that problem to be repaired. What is needed is a system for monitoring an HVAC system that utilizes information from the control center of the unit to automatically identify a malfunctioning part causing a problem, place an order for that part, and dispatch a service technician to install the replacement part upon its arrival. SUMMARY OF THE INVENTION The present invention is a method and system for monitoring operations of a heating ventilating and air conditioning (HVAC) system such as a chiller system or a rooftop unit having a control center, and upon occurrence of a malfunction or other system failure, to automatically order needed replacement parts and dispatch a service technician to install the parts and make the repair. The system utilizes a control center located on-site, that is to say, at the facilities at which the chiller system or rooftop unit is located. The control center is in one-way communication with sensors configured to monitor components of the chiller system and receives data indicative of the operation of each of the components. The control center determines whether each component is operating within the normal operating parameters and stores data indicative of component operation in memory. If the data indicates that the HVAC system component is operating outside of normal parameters, a processing unit in the control center evaluates the information and determines whether remedial action is required. If a malfunction has occurred and remedial action is required, the control center determines the remedial action needed to correct the malfunction, including accessing a bill of materials to determine a proper replacement part. The processing unit then initiates a communication to order the replacement part from a repair center and dispatches a service technician to perform the repair. A method for repairing an HVAC system is disclosed. The method comprises the steps of monitoring a plurality of sensors positioned throughout the HVAC system and receiving data associated therewith, determining whether the data received from the plurality of sensors is within corresponding predetermined operational parameters, conducting a diagnosis of the HVAC system to identify a malfunction of the HVAC system in response to having data determined to be outside the corresponding predetermined operational parameters, accessing an on-board bill of materials to determine a proper replacement part to correct the malfunction, automatically ordering the replacement part, and automatically dispatching a service technician to install the replacement part. A system for automatically procuring parts and dispatching a service technician to repair an HVAC system is also disclosed. The system comprises a plurality of sensors positioned throughout the HVAC system and an HVAC system control center in communication with the plurality of sensors, the control center comprising a microprocessor, a memory and a communications port. The microprocessor comprises computer instructions to execute the steps of monitoring data received from the plurality of sensors, comparing the received data against pre-determined operational parameters, analyzing data outside of the operational parameters to determine an HVAC system malfunction, accessing an on-board bill of materials from the memory to identify a replacement part based on the data analysis to correct the HVAC system malfunction, initiating a call to a parts center via the communications port to order the replacement part, and initiating a call via the communications port to dispatch a service technician to install the replacement part. One advantage of exemplary embodiments of the present invention is that the HVAC system can perform a self-diagnosis and in response to that diagnosis, automatically order a replacement part without the need for a service technician to make a diagnostic visit and a subsequent repair visit to install the part in the malfunctioning system. Another advantage of exemplary embodiments of the present invention is the ability to reference an on-board bill of materials stored in memory to automatically determine a proper replacement part in light of a self-diagnosis by the HVAC system. Still another advantage of exemplary embodiments of the present invention is direct communication by the HVAC system to order replacement parts and dispatch a service technician without the need to route communications through a central HVAC service center or other intermediary. Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart illustrating a method of repairing an HVAC system using automated part procurement and service dispatch according to an exemplary embodiment of the invention. FIG. 2 is a portion of the flowchart of FIG. 1 further illustrating the step of monitoring with sensors. FIG. 3 is a system for automated part procurement and service dispatch according to an exemplary embodiment of the invention. Where the same parts are referred to in different Figures, like numerals are used for ease of identification. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION Exemplary embodiments of the invention are directed to automated part procurement and service dispatching for an HVAC system that includes a control center to automatically analyze a system malfunction and determine appropriate repairs for the HVAC system. Based on the determined needed repair, a processor accesses an on-board bill of materials, i.e. stored in a memory local to the HVAC system, to identify a replacement part(s) needed for the repair. The processor then initiates a communication with a repair center and orders the part(s). Additionally, a service technician is automatically dispatched to repair the HVAC system. Control centers with diagnostic capabilities are well known for use in HVAC systems to diagnose and record HVAC system faults and failures for later access by a service technician called to the site of HVAC system. The control center's diagnostic capabilities typically involve receiving electronic communications from various types of sensors positioned throughout the HVAC system that sense operating parameters of the HVAC system. The HVAC system operating parameter data is communicated to a microprocessor that monitors parameters of the HVAC system during operation. According to exemplary embodiments of the invention, the microprocessor has the ability to receive and analyze the operating parameter data, as well as the ability to initiate external communication protocols. When the HVAC system fails or malfunctions, the monitored parameters can be used to determine the cause of error though artificial intelligence or a series of logic rules relating to failure symptoms stored in memory to identify a failed part. The parameters can also be used to identify a part that is near failure and which needs to be replaced before the system breaks down. The microprocessor accesses the bill of materials to determine indicia associated with the failed part, such as a part number, useful for ordering a replacement part. The microprocessor initiates a communication with a parts center and electronically places an order for the proper part. Another communication notifies a service technician of the failure. The notification may be delivered in any convenient manner. Preferably, the notification is either electronic, such as an email sent to a predetermined email address, or telephonic, using speech generation software. Based at least in part on the communication with the parts center or other source of the replacement part, the microprocessor coordinates and dispatches the technician to the repair site when the replacement part is due to arrive or soon after it is due to have arrived. In some emergency situations, the microprocessor may dispatch a service technician before the part is due to arrive, for example, if the microprocessor determines the replacement part is not expected to arrive prior to system failure. Preferably, all of the communications originate from the HVAC system and connect directly to the parts center, service office and/or service technician without the need to be routed through a central HVAC service hub or other intermediary. The microprocessor may initiate yet another communication to a point of contact, such as the owner or maintenance department of the building associated with the malfunctioning HVAC system and advise the owner of the scheduled repair. The communication may provide the owner an opportunity to decline or postpone the repair, upon the occurrence of which the part order and/or dispatch call may be cancelled. In most cases, however, maintaining uninterrupted, or minimally interrupted HVAC service is desired or even necessary and the replacement part and service technician automatically arrive at the customer site prior to any loss of service to the customer or in some cases even before the customer notices a problem. A bill of materials, which may be limited to a bill of replaceable materials, for the HVAC system is incorporated into the memory of the control center, giving the microprocessor access to information identifying the components in the HVAC system, such as condensers, evaporators, burners or compressors, as well as sub-components of those components, such as valves, motors, transducers, sensors, or filters, all by way of example only. Information pertaining to site location is also incorporated into the control center memory. Delivery information, if different from site location, and contact information is also preferably included in the memory. The bill of replaceable materials could also be visually displayed to a screen or other output device as a look-up table available to the technician once on-site. The technician can then verify the correct part number was ordered or the technician may order any additional parts determined to be needed. When a part is replaced, the bill of materials may be manually or automatically updated to reflect the current on-board components. The invention is further described with respect to the following non-limiting example illustrated in FIG. 1. At s100, one or more sensors is monitored by a microprocessor associated with a control center of an HVAC system, or in some cases, with a control center of a particular HVAC component, in which the microprocessor is in one-way communication with the sensors. Different sensors may be used to measure any of a number of different types of properties useful for diagnosis of HVAC system function (or malfunction) or other properties desired to be monitored. As shown in FIG. 2, temperature sensors, pressure sensors and vibration sensors are each monitored at s110, s120 and s130. Additional sensors may also be measured as illustrated with the generic step s190. Typically, monitoring the sensors includes at least monitoring pressure, temperature, and vibration sensors. Voltage and current are also typically monitored properties using appropriate sensors. For each property to be measured, one or more sensors may be used. Each sensor is placed at a pre-determined location in the HVAC system selected for the best monitoring of the property of the HVAC system. Returning to FIG. 1, a determination is made whether data received from the sensors being monitored are within predetermined operating parameters associated with normal operating functionality at s200. If all of the sensors are within the parameters, the process returns to s100 for further monitoring. If data from one or more of the sensors is not within the parameters, the process passes to s300 and the measured properties are analyzed. Using information based at least in part on the number and type of sensors that received data falling outside the parameters and the magnitude by which the measured properties are non-compliant, the microprocessor determines the source of the malfunction with reference to diagnostic information stored in a control center memory accessible to the microprocessor in order to diagnose the malfunction at s400. For example, in a chiller, the sensors may determine that vibration sensors located near the chiller motor are reporting vibrations that fall outside of normal operating parameters. Using this information, and with reference to corresponding diagnostic information stored in the memory, the microprocessor may determine that the location and magnitude of the sensed vibration is consistent with motor bearings that are starting to fail in the chiller motor. It will be appreciated that in many cases, changes in properties monitored throughout the HVAC system will be the result of changes due to normal system operation, such as a change in load that results in changes in temperature or pressure, and are not attributable to changes in temperature or pressure that signal a malfunction. Thus, the diagnostic information typically includes a range of compliant behavior using known trends and pre-determined allowable limits expected to occur in normal operation. In some cases, the operating parameters themselves may associated with pre-determined load conditions, such that the acceptable operating parameters against which the monitored data is compared changes as the load changes. The diagnostic information is typically analyzed over a pre-determined period of time. Analyzing non-compliant parameters with respect to time may be particularly useful in differentiating a slight change or aberration in normal system operating conditions from a malfunction or impending system failure. In some cases, where the measured parameters are to be evaluated over time, the microprocessor may also compile and record a log of changes in the memory for use in later analysis in identifying a slowly failing part or to form a base line against which later conditions can be compared. This type of trend analysis may further depend on the magnitude by which the monitored parameters exceed the normal operating parameters. Returning to the chiller motor example, vibrations may begin as minor fluctuations outside of the operating parameters but persist over the course of several days or increase in frequency or magnitude. The vibrations may initially only exceed operating parameters by less than 1%, but increase over the course of a week to be 10% or more outside of the operating parameters. Based on the percentage by which the vibrations exceed parameters over a period of time, a trend can be determined to identify the malfunction and/or project how long the part will operated with the malfunction before failure. By analyzing properties over time to determine a trend, the microprocessor may avoid ordering parts that were aberrations in operation and not true malfunctions requiring a repair. By way of further example, the monitored vibration data may exceed the operating parameters by a small percentage and then return to normal for at least a pre-determined period of time without again exceeding the operating parameters. Conversely, if the chiller motor vibrations quickly escalate well outside of the normal operating parameters, the microprocessor may earlier or immediately identify the malfunction and a needed repair. The diagnostic parameters preferably include safety limits, wherein parameters measured outside of the safety limits indicate the malfunction creates a safety hazard or indicates an imminent catastrophic system failure and results in an emergency shutdown. Whether or not trend analysis is used as part of the part failure analysis, a separate log of malfunctions determined, as well as the parameters causing each diagnosis, may be compiled and stored in the control center memory. The log may be reviewed by a service technician once on-site. Alternatively, the technician may review the log in advance of arriving at the site by remotely accessing the control center over a communication network, such as the internet. At s500, the microprocessor accesses a bill of materials also stored in the control center memory. It should be appreciated that the bill of materials may be accessed either before or after the HVAC malfunction has been diagnosed. In some circumstances, identifying whether a specific part is a component of the HVAC system may be helpful or necessary to properly analyze and diagnose the malfunction. In combination with the diagnosed error, the bill of materials can be used by the microprocessor to identify the part or parts that need to be replaced in order for the HVAC system to be repaired. In the example of motor bearing failure in the chiller motor, the microprocessor may determine that the chiller has a particular type of chiller motor, and that a particular model number is needed to effect the repair. In some circumstances, the bill of materials may also contain certain other key characteristics of the on-board part useful in ordering a suitable replacement part, for example, in the event the particular model number is no longer available. By way of further example, the bill of materials may contain information regarding the size and capacity of the chiller motor in addition to, or in lieu of, a specific part number. Once the part(s) to be replaced is identified, a request to one or more pre-selected parts centers is initiated at s600 by the microprocessor using a communications port associated with the control center. The communications port may be adapted for either or both of wired and wireless communications and may be telephonic or electronic. Preferably, contact information for multiple pre-selected parts centers is accessible by the microprocessor in the event that the first contacted parts center is unable to deliver the necessary replacement part as discussed below. In addition to the part itself, information for payment and delivery may also be communicated by the microprocessor. The payment and delivery information may be separately stored in memory, but preferably is associated with the bill of materials. The microprocessor is adapted for two-way external communications in order to receive information from the parts center. In this manner, the microprocessor may first order the part at s700 and then receive information sufficient to determine an expected arrival of the replacement part at s800. If the arrival date is beyond a pre-selected period of time, the microprocessor may initiate a call to one of the other pre-selected parts centers in an attempt to more quickly procure the necessary part. If successful in identifying an earlier arrival date, the control center places an order with the parts center providing the earlier-to-arrive part, and if necessary, cancels any less-timely order previously placed with a different parts center. The pre-selected acceptable period of time for delivery may be any desired period of time and may be determined at least in part by the urgency of the repair as calculated during the diagnostics. The pre-selected period of time may also be determined based on a particular customer's status, such as depending on the size, importance or nature of business of the customer. After, the part has been ordered, the microprocessor also initiates a communication to dispatch a service technician to install the replacement part and who may conduct any further on-site analysis that the technician determines is appropriate. The service dispatch may be made directly to a specific technician assigned to the particular HVAC site or may be routed through a service office to dispatch any available technician. As shown in FIG. 1, preferably the microprocessor first determines whether the malfunction that initiated the automatic part procurement process is likely to result in a system failure and/or shutdown prior to the part's arrival at s900. If so, it may be desirable to dispatch a technician in advance of the part's arrival to perform stop-gap maintenance at s910 until the proper part arrives. Preferably, the parameters used to determine whether the HVAC system is operating normally are selected in combination with sensors sensitive enough to diagnose a malfunction well in advance of failure. In this way, the automatic part procurement can be initiated far enough in advance such that the microprocessor dispatches the service technician at s920 in a manner coordinated with the expected arrival of the replacement part. Returning to the example of a chiller with failing motor bearings, the microprocessor may determine that based on the level of vibration detected, the motor is likely to operate for at least another 200 hours to failure. Thus, if the appropriate replacement part procured through the parts center was designated for arrival in four days, a service technician could be automatically dispatched to install the new motor on day five without significant risk of system failure in the interim. It will be appreciated, that in addition to the day, an expected time of delivery may also be provided, such that the expected arrival date includes both the day and time of expected arrival. After the replacement part has been installed, particularly where the replacement part is not the same model number as the part replaced, the bill of materials may be automatically or manually updated by the service technician so that the bill of materials accurately reflects the post-repair make-up of the HVAC system. While the foregoing example was described with respect to motor bearings of a chiller, it will be appreciated that any number of components within a chiller or other HVAC system can be monitored and analyzed using a variety of diagnostic sensors, and that the systems and methods described can be used with these other HVAC systems and their respective components. FIG. 3 illustrates an exemplary system 10 for automated part procurement and service dispatching according to an embodiment of the invention. An HVAC system 110 having an HVAC control center 120 is located at an installation site. HVAC systems which may particularly benefit from the present invention include chillers and other large commercial HVAC systems that are often placed in difficult to service locations, such as on building rooftops, and thus particularly benefit from the efficiency of limiting the number of on-site visits for system repair. As illustrated, the HVAC control center 120 comprises a microprocessor 122, which may be a CPU or any other suitable processor, a memory 124, a communications port 126, and a display screen 128. The display screen 128 is typically, but need not necessarily be, a liquid crystal display (LCD). The display screen 128 typically provides for visual monitoring of the HVAC system 110 operations by the technician once on-site. Preferably, the display screen 128 also permits viewing the bill of materials and a log of recorded faults, including the faults that led to the ordering of the replacement part and the dispatch of the service technician viewing the display screen 128. The memory 124 can be any form of electronic storage device suitable for storing data accessible by the microprocessor 122, including by way of example only, a hard disk, flash memory, CD-ROM, DVD-ROM, or computer memory (RAM or ROM). A plurality of sensors 115 are distributed at pre-determined locations throughout the HVAC system 110, which plurality of sensors 115 are in one-way communication with the control center 120 such that the microprocessor 122 monitors and analyzes data sent by the sensors 115. The microprocessor 122 is in two-way communication with a parts center 200 to order replacement parts as described above via the communications port 126 over a communications network 400, which may be either or both of a wired or wireless communications network. The microprocessor is also in communication with a service office 300 or directly with a service technician via the communications port 126 over the communications network 400 to coordinate the dispatch of the service technician with the arrival of the ordered replacement part as also described above. While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.	G	60G06	161G06F	19	00
11942524	US20080126775A1-20080529	ELECTRONIC APPARATUS INCORPORATING A PLURALITY OF MICROPROCESSOR UNITS	ACCEPTED	20080514	20080529	[]	G06F15177	["G06F15177"]	7987350	20071119	20110726	713	001000	67150.0	TRAN	VINCENT	[{"inventor_name_last": "Miwa", "inventor_name_first": "Kenji", "inventor_city": "Kawasaki-shi", "inventor_state": "", "inventor_country": "JP"}]	An electronic apparatus includes an initializing unit configured to, at power-on, execute in parallel a process of initializing data, which is stored in a first nonvolatile memory and requires initialization, into a first volatile memory by a first microprocessor unit and a process of initializing data, which is stored in a second nonvolatile memory and requires initialization, into a second volatile memory by a second microprocessor unit, and to copy a second set of initialized data, which has been initialized by the second microprocessor unit and stored in the second volatile memory, into the first volatile memory via the communication interface. A startup time of the electronic apparatus is shortened.	1. An electronic apparatus including: a first nonvolatile memory; a first volatile memory; a first microprocessor unit to which are connected the first nonvolatile memory and the first volatile memory; a second nonvolatile memory; a second volatile memory; a second microprocessor unit to which are connected the second nonvolatile memory and the second volatile memory; a communication interface arranged to interconnect the first microprocessor unit and the second microprocessor unit; and an initializing unit configured to, at power-on, execute in parallel a process of initializing data, which is stored in the first nonvolatile memory and requires initialization, into the first volatile memory by the first microprocessor unit, and a process of initializing data, which is stored in the second nonvolatile memory and requires initialization, into the second volatile memory by the second microprocessor unit; and copy a second set of initialized data, which has been initialized by the second microprocessor unit and stored in the second volatile memory, into the first volatile memory via the communication interface. 2. The electronic apparatus according to claim 1, wherein the initializing unit further copies a first set of initialized data, which has been initialized by the first microprocessor unit and stored in the first volatile memory, into the second volatile memory via the communication interface. 3. The electronic apparatus according to claim 1, wherein the initializing unit executes the initialization such that the initialized data and the second set of initialized data are not overlapped with each other. 4. The electronic apparatus according to claim 1, wherein the data stored in the first nonvolatile memory and requiring initialization and the data stored in the second nonvolatile memory and requiring initialization are each given by one of divided parts of data, which are successively required in accordance with the progress of an entire initialization process, and the initializing unit copies the initialized data at a time when a process of initializing each of the divided parts of the data is completed. 5. The electronic apparatus according to claim 4, wherein the divided parts of the data are divided to have the same data size. 6. The electronic apparatus according to claim 4, wherein the divided parts of the data are divided to have the same processing time. 7. The electronic apparatus according to claim 1, wherein the first volatile memory connected to the first microprocessor unit receives a copy of the initialized data before the other data. 8. A control method for an electronic apparatus including: a first nonvolatile memory; a first volatile memory; a first microprocessor unit to which are connected the first nonvolatile memory and the first volatile memory; a second nonvolatile memory; a second volatile memory; a second microprocessor unit to which are connected the second nonvolatile memory and the second volatile memory; and a communication interface arranged to interconnect the first microprocessor unit and the second microprocessor unit, the control method comprising: a first processing step of, at power-on, initializing data, which is stored in the first nonvolatile memory and requires initialization, into the first volatile memory by the first microprocessor unit; a second processing step of, at power-on, initializing data, which is stored in the second nonvolatile memory and requires initialization, into the second volatile memory by the second microprocessor unit; and a step of copying a second set of initialized data, which has been initialized by the second microprocessor unit and stored in the second volatile memory, into the first volatile memory via the communication interface, wherein the first processing step and the second processing are executed in parallel.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an electronic apparatus, such as an electronic camera, which incorporates a plurality of microprocessor units. 2. Description of the Related Art An electronic camera becoming more widely used at present has a tendency to increase the number of pixels of an image pickup element employed in the electronic camera with the provision of more advanced functions. In the past, various kinds of control processes were performed by one microprocessor unit (hereinafter referred to also as “MPU (Micro Processing Unit)”). However, an electronic camera incorporating a plurality of MPUs has also been recently practiced to realize higher performance and higher functionality. At the system startup of an electronic camera after power-on, the startup operation is performed by reading all of data, which is stored in a ROM (Read Only Memory) and requires initialization, into a RAM (Random Access Memory). At that time, a system has to be started up after the initialization of all of the data which requires the initialization. The data requiring the initialization includes, for example, not only setting values and correction values for a sensor and hardware which are necessary for picking up an image, but also setting values selected from a menu. In the electronic camera having more advanced functions, the number of setting values which have to be set and selected is increased and the number of pixels of an image pickup element, such as a CCD (Charge-Coupled Device) or CMOS sensor, is also increased. Therefore, an amount of the data requiring the initialization tends to increase. For that reason, a difficulty arises in shortening a startup time of the camera. Hence, an image pickup operation cannot be started immediately even with pressing of a release button after the power-on, and a shutter chance is missed. In a digital camera disclosed in Japanese Patent Laid-Open No. 2003-189165, to overcome the above-described disadvantages, a program is divided into two parts, i.e., one part required to start up an image pickup system and another part. After power-on, the program part necessary for the image pickup system is first initialized and started up. Then, the remaining part is initialized and started up. By first starting up only the program part necessary for the image pickup system, a startup time from the power-on to a photographing-enable state can be shortened to reduce a possibility that the shutter chance is missed. Also, in a camera disclosed in Japanese Patent Laid-Open No. 2001-94844, management information necessary for reading and writing data from and in a memory card is saved/recovered respectively in response to power-off/on of the camera. This technique eliminates the need of newly reconstructing the management information for the memory card at the power-on. Accordingly, a time taken until the start of a photographing operation can be shortened to reduce a possibility that the shutter chance is missed. In the digital camera disclosed in the above-cited Japanese Patent Laid-Open No. 2003-189165, however, the photographing operation is allowed at a point in time when the startup of the program part necessary for the image pickup system is completed. Therefore, the photographing operation is allowed in spite of a situation where there is actually an error in a memory card, or where the memory card has no vacant capacity and cannot store any more images even when the images are photographed. The above-cited Japanese Patent Laid-Open No. 2001-94844 discloses the camera related to the technique of saving/recovering the management information necessary for the memory card, and it does not propose a method of avoiding prolongation of the system startup time, which is caused by an increase in the setting values required in the sensor and the hardware. Further, Japanese Patent Laid-Open No. 2001-94844 proposes a system incorporating a plurality of MPUs, but it has the following disadvantage. When the plurality of MPUs require the same management information, each of the MPUs has to save/recover the same management information, thus resulting in a longer startup time.	<SOH> SUMMARY OF THE INVENTION <EOH>In view of the above-described problems, the present invention is directed to an electronic apparatus capable of shortening a startup time. According to one aspect of the present invention, an electronic apparatus includes a first nonvolatile memory, a first volatile memory, a first microprocessor unit to which are connected the first nonvolatile memory and the first volatile memory, a second nonvolatile memory, a second volatile memory, a second microprocessor unit to which are connected the second nonvolatile memory and the second volatile memory, a communication interface arranged to interconnect the first microprocessor unit and the second microprocessor unit, and an initializing unit configured to, at power-on, execute in parallel a process of initializing data, which is stored in the first nonvolatile memory and requires initialization, into the first volatile memory by the first microprocessor unit and a process of initializing data, which is stored in the second nonvolatile memory and requires initialization, into the second volatile memory by the second microprocessor unit, and to copy a second set of initialized data, which has been initialized by the second microprocessor unit and stored in the second volatile memory, into the first volatile memory via the communication interface. Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic apparatus, such as an electronic camera, which incorporates a plurality of microprocessor units. 2. Description of the Related Art An electronic camera becoming more widely used at present has a tendency to increase the number of pixels of an image pickup element employed in the electronic camera with the provision of more advanced functions. In the past, various kinds of control processes were performed by one microprocessor unit (hereinafter referred to also as “MPU (Micro Processing Unit)”). However, an electronic camera incorporating a plurality of MPUs has also been recently practiced to realize higher performance and higher functionality. At the system startup of an electronic camera after power-on, the startup operation is performed by reading all of data, which is stored in a ROM (Read Only Memory) and requires initialization, into a RAM (Random Access Memory). At that time, a system has to be started up after the initialization of all of the data which requires the initialization. The data requiring the initialization includes, for example, not only setting values and correction values for a sensor and hardware which are necessary for picking up an image, but also setting values selected from a menu. In the electronic camera having more advanced functions, the number of setting values which have to be set and selected is increased and the number of pixels of an image pickup element, such as a CCD (Charge-Coupled Device) or CMOS sensor, is also increased. Therefore, an amount of the data requiring the initialization tends to increase. For that reason, a difficulty arises in shortening a startup time of the camera. Hence, an image pickup operation cannot be started immediately even with pressing of a release button after the power-on, and a shutter chance is missed. In a digital camera disclosed in Japanese Patent Laid-Open No. 2003-189165, to overcome the above-described disadvantages, a program is divided into two parts, i.e., one part required to start up an image pickup system and another part. After power-on, the program part necessary for the image pickup system is first initialized and started up. Then, the remaining part is initialized and started up. By first starting up only the program part necessary for the image pickup system, a startup time from the power-on to a photographing-enable state can be shortened to reduce a possibility that the shutter chance is missed. Also, in a camera disclosed in Japanese Patent Laid-Open No. 2001-94844, management information necessary for reading and writing data from and in a memory card is saved/recovered respectively in response to power-off/on of the camera. This technique eliminates the need of newly reconstructing the management information for the memory card at the power-on. Accordingly, a time taken until the start of a photographing operation can be shortened to reduce a possibility that the shutter chance is missed. In the digital camera disclosed in the above-cited Japanese Patent Laid-Open No. 2003-189165, however, the photographing operation is allowed at a point in time when the startup of the program part necessary for the image pickup system is completed. Therefore, the photographing operation is allowed in spite of a situation where there is actually an error in a memory card, or where the memory card has no vacant capacity and cannot store any more images even when the images are photographed. The above-cited Japanese Patent Laid-Open No. 2001-94844 discloses the camera related to the technique of saving/recovering the management information necessary for the memory card, and it does not propose a method of avoiding prolongation of the system startup time, which is caused by an increase in the setting values required in the sensor and the hardware. Further, Japanese Patent Laid-Open No. 2001-94844 proposes a system incorporating a plurality of MPUs, but it has the following disadvantage. When the plurality of MPUs require the same management information, each of the MPUs has to save/recover the same management information, thus resulting in a longer startup time. SUMMARY OF THE INVENTION In view of the above-described problems, the present invention is directed to an electronic apparatus capable of shortening a startup time. According to one aspect of the present invention, an electronic apparatus includes a first nonvolatile memory, a first volatile memory, a first microprocessor unit to which are connected the first nonvolatile memory and the first volatile memory, a second nonvolatile memory, a second volatile memory, a second microprocessor unit to which are connected the second nonvolatile memory and the second volatile memory, a communication interface arranged to interconnect the first microprocessor unit and the second microprocessor unit, and an initializing unit configured to, at power-on, execute in parallel a process of initializing data, which is stored in the first nonvolatile memory and requires initialization, into the first volatile memory by the first microprocessor unit and a process of initializing data, which is stored in the second nonvolatile memory and requires initialization, into the second volatile memory by the second microprocessor unit, and to copy a second set of initialized data, which has been initialized by the second microprocessor unit and stored in the second volatile memory, into the first volatile memory via the communication interface. Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of primary components of an electronic camera according to one exemplary embodiment of the present invention. FIG. 2 is a flowchart showing the operation at the startup of one MPU in FIG. 1. FIG. 3 is a flowchart showing the operation at the startup of another MPU in FIG. 1. DESCRIPTION OF THE EMBODIMENTS Embodiments of the present invention will be described in detail in accordance with the accompanying drawings. FIG. 1 is a block diagram of main components of an electronic camera, which is one example of an electronic apparatus incorporating a plurality of MPUs, according to one exemplary embodiment of the present invention. Referring to FIG. 1, the electronic camera includes an MPU 101 incorporated therein, a RAM 102 serving as a volatile memory used by the MPU 101, and a ROM 103 serving as a nonvolatile memory used by the MPU 101. The MPU 101, the RAM 102, and the ROM 103 are interconnected by a system bus 104 on the side including the MPU 101. The ROM 103 stores software and parameters which are required to operate the camera. The parameters include ones which are common in the same model, and other ones which are specific to each model and differ per camera (i.e., depending on individual settings). Also, the parameters include ones which are just read and are not rewritten, and other ones which are read and rewritten. Generally, a nonvolatile ROM has a slower read rate than a RAM. Therefore, when it is required to read a parameter at a high rate, even a parameter that is just read is often used after being developed into a RAM from a ROM. The electronic camera further includes an MPU 301 incorporated therein, a RAM 302 serving a volatile memory used by the MPU 301, and a ROM 303 serving as a nonvolatile memory used by the MPU 301. The MPU 301, the RAM 302, and the ROM 303 are interconnected by a system bus 304 on the side including the MPU 301. The MPU 101 and the MPU 301 are connected to each other by a high-rate bus 201, i.e., a high-rate communication interface dedicated for interconnection between MPUs, such that information is notified via the inter-MPU high-rate bus 201. The inter-MPU high-rate bus 201 is a dedicated bus having a data transfer rate comparable to that of the RAM which is connected to each of the MPU 101 and the MPU 301. When data is transferred, the type and the transfer size of the data are first notified from the MPU as a transfer source to the MPU as a transfer destination. Then, the transfer destination MPU performs preparations for receiving the data and notifies the end of the preparations for the reception to the transfer source MPU. Finally, the transfer source MPU starts transmission of the data. In such a way, the data can be transferred between the MPUs via the bus. Parameters necessary for executing a program and parameters (correction data) necessary for correcting an image in an image pickup operation are separately stored in the ROM 103 and the ROM 303. The parameters necessary for executing the program are parameters that are required to start up the program and are further required earlier than the operation of the electronic camera. On the other hand, the parameters necessary for the image correction are parameters that are required to be initialized until reaching a time when the image pickup operation is actually performed after the startup of the electronic camera. The reason why the parameters are divided into ones necessary for executing the program and the others (correction data) necessary for the image correction resides in enabling the MPU 101 and the MPU 301 to initialize the divided groups of parameters in parallel at the startup by storing the divided groups of parameters to be initialized, which are required at different points in time, in two respective ROMs. The operation of the thus-constructed electronic camera at the startup will be described next. FIG. 2 is a flowchart showing the operation at the startup of the MPU 101, and FIG. 3 is a flowchart showing the operation at the startup of the MPU 301. When the startup is instructed by turning-on a power switch, the MPU 101 and the MPU 301 are both released from the reset state at the same time to start up a system of the electronic camera. The operations at the startup of the MPU 101 and the MPU 301 will be described in detail with reference to the flowcharts of FIGS. 2 and 3. The MPU 101 first develops the parameters necessary for executing the program into the RAM 102 from the ROM 103 (S101). Then, after the completion of development of the parameters, the MPU 101 executes a program booting process (S102). The MPU 301 first develops the correction data necessary for correcting the image into the RAM 302 from the ROM 303 (S201). Then, after the completion of development of the correction data, the MPU 301 executes correction-data transmission setting for the inter-MPU high-rate bus 201 (S202) and notifies the end of the preparations for transmitting the correction data to the MPU 101 (S203). Upon receiving, from the MPU 301, a notice indicating the end of the preparations for transmitting the correction data (S103), the MPU 101 performs the setting needed to receive the correction data for the inter-MPU high-rate bus 201 (S104) and notifies the end of the preparations for receiving the correction data to the MPU 301 (S105). After receiving a notice indicating the end of the preparations for the reception (S204), the MPU 301 transfers the correction data (S205) such that the MPU 101 can develop the correction data, which has been developed in the RAM 302, into the RAM 102 via the inter-MPU high-rate bus 201 (S106). Upon the completion of development of the correction data, the parameters requiring the development are all developed in the RAM 102. At this time, the electronic camera comes into a state where the MPU 101 can start the operation of the electronic camera, such as image pickup or reproduction. After receiving the correction data and developing the parameters, the MPU 101 performs the setting needed to transmit the parameters via the inter-MPU high-rate bus 201 (S107) and notifies the end of the preparations for the transmission to the MPU 301 (S108). After receiving a notice indicating the end of preparations for transmission (S206), the MPU 301 develops the parameters necessary for executing the program, which have been developed in the RAM 102 and sent to the RAM 302 via the inter-MPU high-rate bus 201. More specifically, the MPU 301 performs the setting needed to receive the parameters for the inter-MPU high-rate bus 201 (S207) and notifies the end of the preparations for the reception to the MPU 101 (S208). After receiving a notice indicating the end of the preparations for the reception (S109), the MPU 101 starts transfer of the parameters (S110) such that the MPU 301 can develop the parameters necessary for executing the program into the RAM 302 (S209). Upon the completion of development of the parameters, the MPU 301 is allowed to transit to a program booting process and executes the program booting process (S210). Hence, the electronic camera comes into a state where the MPU 301 can start the operation of the electronic camera, such as image pickup or reproduction. Because the electronic camera system comes into a started-up state at the time when the boot-up of the program and the initialization of the parameters are completed on the side including the MPU 101, there is no problem even when the startup process is completed in the MPU 301 with a delay from the MPU 101. In that case, the MPU 101 operates as a primary MPU in the electronic camera system. In the above-described exemplary embodiment, the setting for the inter-MPU high-rate bus 201 by the transfer destination MPU is performed after receiving the notice indicating the end of the preparations for the transmission in the transfer source MPU. However, since the development sequence and the development size of the parameters are known in advance in many cases, the setting for the reception can be set for the inter-MPU high-rate bus 201 before the notice indicating the end of the preparations for the transmission is received from the transfer source MPU. In such a case, a time required from the setting of the data transfer to the actual transfer using the inter-MPU high-rate bus 201 can be shortened by notifying the end of the preparations for the reception immediately upon receiving the notice indicating the end of the preparations for the transmission. Also, the data transfer via the inter-MPU high-rate bus 201 can be performed through hardware using DMA (Direct Memory Access), for example, so as to reduce the amount of processing to be executed by the MPU. Further, the data transfer via the inter-MPU high-rate bus 201 can be performed by such an arrangement that the transfer source MPU is able to directly access a memory in the transfer destination MPU to copy the parameters in the memory without the process of mutually confirming the communication partners, i.e., the transfer source MPU and the transfer destination MPU. As described above, when developing the parameters necessary for performing the operation of the electronic camera, the MPU 101 is just required to read the parameters necessary for executing the program from the ROM having a relatively low read rate, and the parameters necessary for the image correction are developed by using the inter-MPU high-rate bus 201. Accordingly, the startup time can be shortened. In addition, since the developments of the parameters from the ROMs are performed by the MPU 101 and the MPU 301 in parallel, quicker startup of the electronic camera can be realized. The electronic camera according to the above-described exemplary embodiment incorporates the plurality MPUs each having the ROM and the RAM and also includes the inter-MPU high-rate bus 201 connecting the MPUs to each other. At power-on of the electronic camera, the data stored in the ROMs and requiring initialization is developed into the RAMs for the initialization by the plural MPUs at the same time. Then, respective sets of the initialized data are copied between the MPUs from one to the other and vice versa via the inter-MPU high-rate bus 201. As a result, in the electronic camera incorporating the plural MPUs to realize higher performance and higher functionality, the startup time can be shortened as far as possible even with the presence of a large amount data requiring the initialization, thus reducing a possibility that the shutter chance is missed. Also, the data to be initialized at the power-on is initialized by the plural MPUs in a manner not overlapping with each other. With that feature, the initialization process can be performed without overlapping and the time required for the initialization can be minimized. Further, the data to be initialized at the power-on is divided into data that is necessary in the first half of the initialization process of the electronic camera and data that is necessary in the second half of the initialization process of the electronic camera. Correspondingly, MPUs are separated into at least one MPU for initializing the data necessary in the first half of the initialization process of the electronic camera and at least one MPU for initializing the data necessary in the second half of the initialization process of the electronic camera. With that feature, when the initialization of the data necessary in the first half of the initialization process of the electronic camera is completed, a subsequent initialization process can be immediately started at earlier timing. The data necessary in the second half of the initialization process of the electronic camera is copied between the MPUs after the initialization of the data necessary in the first half of the initialization process. Hence, all of the data can be initialized while realizing a shorter initialization time of the electronic camera. Moreover, the data to be initialized at the power-on is divided so as to have the same data size. Therefore, the time required for each MPU to execute the initialization is the same, thus minimizing the time taken until one MPU starts copying of the data from the other MPU after each MPU has completed the initialization of the respective data. In other words, the initialization time of the electronic camera can be prevented from being prolonged due to the reason that one MPU has to wait for the completion of the initialization executed by the other MPU. Alternatively, the data to be initialized at the power-on is divided so as to have the same initialization time. With that feature, even when the initialization time differs depending on the difference in the contents of the initialization process in spite of the divided sets of data having the same size, the MPUs can complete the respective initialization processes at the same timing as a result of dividing the data in consideration of the initialization time. After the completion of the initialization process executed by one MPU, the copying of the data from the other MPU to the one MPU can be started immediately and the initialization time of the electronic camera can be shortened. In addition, a primary one of the plural MPUs is set to initialize the data necessary in the first half of the initialization process of the electronic camera. Since the primary MPU initializes the data necessary in the first half of the initialization process, the primary MPU can execute the entire initialization process with higher priority than the other MPU. After the primary MPU has completed the entire initialization process, the other MPU executes the remaining initialization process. Hence, the initialization time required to start up the electronic camera by the primary MPU can be shortened. With the features described above, an electronic camera is realized which has a shorter startup time and can reduce a possibility that the shutter chance is missed. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all modifications, equivalent structures and functions. This application claims the benefit of Japanese Patent Application No. 2006-318636 filed Nov. 27, 2006, which is hereby incorporated by reference herein in its entirety.	G	60G06	161G06F	151	77
11692145	US20080243960A1-20081002	DETERMINISTIC FILE CONTENT GENERATION OF SEED-BASED FILES	ACCEPTED	20080917	20081002	[]	G06F1730	["G06F1730"]	7685211	20070327	20100323	707	200000	94832.0	ORTIZ DITREN	BELIX	[{"inventor_name_last": "Bergauer", "inventor_name_first": "Ryan C.", "inventor_city": "Redmond", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Wohlgemuth", "inventor_name_first": "Sean C.", "inventor_city": "Duvall", "inventor_state": "WA", "inventor_country": "US"}]	A method for deterministic file content generation of seed based files is comprised of extracting a seed value from a seeded file signature, passing the seed value to a seeded content generating function to produce a set of generated content, and appending the set of generated content to the seed file signature to produce a seed-based file. A delta offset may also be included in the seeded file signature, the delta offset indicating where modified content is to be substituted within the generated content.	1. A method, comprising: extracting a seed value and a file length from a seeded file signature; initializing a seeded content generating function using the seed value to produce a set of blocks; and iteratively adding each block included in the set of blocks to produce generated file content. 2. The method of claim 2, further comprising: extracting a delta offset value and a delta length from the seeded file signature; and determining if the position of the current iteration is equivalent to or greater than the delta offset value and is less than or equal to the sum of the delta length and the delta offset value; in response to a positive determination, passing the block associated with the current iteration to a separate deterministic function to produce a new block; and adding the block to the generated file content in place of the block associated with the current iteration. 3. The method of claim 1, wherein the seed content generating function is a pseudorandom number generating function. 4. The method of claim 1, wherein the seed content generating function is a function that produces a set of data in a reproducible fashion using the seed value. 5. The method of claim 1, further comprising receiving the seeded file signature from a first client. 6. The method of claim 1, further comprising: appending the generated file content to the seeded file signature to produce a stream. 7. The method of claim 6, further comprising: sending the stream. 8. The method of claim 1, further comprising comparing the generated file content to a set of generated file content produced by another process using the seeded file signature. 9. The method of claim 1, wherein the seed value is an integer 4 bytes long. 10. A computer readable storage medium having stored thereon a data structure, comprising: a first data field containing data representing a seed value, the seed value being used to seed a seeded content generating function that produces a set of generated content; a second data field containing data representing a file length, the file length used to determine the size of the generated content; a third data field containing data representing a delta offset value, the delta offset value used to determine a location falling within the generated content to begin inserting modified content; and a fourth data field containing data representing a delta length, the delta length used to determine a location falling within the generated content to end inserting modified content. 11. The data structure of claim 10, further comprising a fifth data field with a length equal to the file length, the fifth data field containing the generated content. 12. The data structure of claim 10, wherein the first data field is 8 bytes long. 13. The data structure of claim 10, wherein the second data field is 8 bytes long. 14. The data structure of claim 10, wherein the third data field is 8 bytes long. 15. The data structure of claim 10, wherein the fourth data field is 8 bytes long. 16. The data structure of claim 10, wherein the modified content is determined by transforming a portion of the generated content using a deterministic integer function. 17. The data structure of claim 10, wherein the sum of the value contained in the third data field and the value contained in the fourth data field may not exceed the value contained in the second data field. 18. A system for deterministic file content generation of seed based files, comprising: a first client for producing a seeded file signature, the first client for producing a first set of seed based content based on the seeded file signature, the first client for sending the seeded file signature and the first seed based content; and a first server for receiving the seeded file signature and the first seed based content, the server for removing the seed based content to produce the seeded file signature. 19. The system of claim 19, further comprising: the first server producing a second set of seed based content based on the seeded file signature, the first server sending the seeded file signature and the second set of seed based content to a second client; and the second client for receiving the seeded file signature and the second set of seed based content, the second client for storing the seeded file signature and the second set of seed based content. 20. The system of claim 19, the first client further for applying a transform to a portion of the first set of seed based content to produce a region of modified content included in the seed based content.	<SOH> BACKGROUND <EOH>The testing of network servers under load often requires the server to receive and store large amounts of test data in physical storage such as a hard drive. Clients creating the large amounts of test data must also create and store large amounts of data. Due to the finite amount of physical storage, each of the client and server may eventually run out of disk space and testing may not continue.	<SOH> SUMMARY <EOH>The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later. The present example provides a data structure and methods for deterministic seeded file content generation of seed-based files. A seeded file may include a seed value, a file length value indicating the length of the content to be generated, a delta offset value indicating an area within the generated content to begin inserting modified content, and a delta length indicating the length of the modified content. Content is generated by passing the seed value to a deterministic function that produces a reproducible set of generated data using the seed value. The modified data is produced by passing the corresponding value from the set of generated data to a second deterministic function to produce the modified value. The modified value replaces the corresponding value in the set of generated data. Many of the attendant features will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.	BACKGROUND The testing of network servers under load often requires the server to receive and store large amounts of test data in physical storage such as a hard drive. Clients creating the large amounts of test data must also create and store large amounts of data. Due to the finite amount of physical storage, each of the client and server may eventually run out of disk space and testing may not continue. SUMMARY The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later. The present example provides a data structure and methods for deterministic seeded file content generation of seed-based files. A seeded file may include a seed value, a file length value indicating the length of the content to be generated, a delta offset value indicating an area within the generated content to begin inserting modified content, and a delta length indicating the length of the modified content. Content is generated by passing the seed value to a deterministic function that produces a reproducible set of generated data using the seed value. The modified data is produced by passing the corresponding value from the set of generated data to a second deterministic function to produce the modified value. The modified value replaces the corresponding value in the set of generated data. Many of the attendant features will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings. DESCRIPTION OF THE DRAWINGS The present description will be better understood from the following detailed description read in light of the accompanying drawings, wherein: FIG. 1 shows an example of a computing device 100 for implementing one or more embodiments of deterministic file content generation. FIG. 2 shows a block diagram of an example system for testing network file replication. FIG. 3 shows an example of a seeded file signature. FIG. 4 shows an example seed file expansion method. Like reference numerals are used to designate like parts in the accompanying drawings. DETAILED DESCRIPTION The detailed description provided below in connection with the appended drawings is intended as a description of the present examples and is not intended to represent the only forms in which the present example may be constructed or utilized. The description sets forth the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples. Although the present examples are described and illustrated herein as being implemented in a deterministic file content generation system, the system described is provided as an example and not a limitation. As those skilled in the art will appreciate, the present examples are suitable for application in a variety of different types of deterministic file content generation systems. FIG. 1 and the following discussion are intended to provide a brief, general description of a suitable computing environment to implement embodiments of the invention. The operating environment of FIG. 1 is only one example of a suitable operating environment and is not intended to suggest any limitation as to the scope of use or functionality of the operating environment. Other well known computing devices, environments, and/or configurations that may be suitable for use with embodiments described herein include, but are not limited to, personal computers, server computers, hand-held or laptop devices, mobile devices (such as mobile phones, Personal Digital Assistants (PDAs), media players, and the like), multiprocessor systems, consumer electronics, mini computers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like. Although not required, embodiments of the invention will be described in the general context of “computer readable instructions” being executed by one or more computing devices. Computer readable instructions may be distributed via computer readable media (discussed below). Computer readable instructions may be implemented as program modules, such as functions, objects, Application Programming Interfaces (APIs), data structures, and the like, that perform particular tasks or implement particular abstract data types. Typically, the functionality of the computer readable instructions may be combined or distributed as desired in various environments. FIG. 1 shows an example of a computing device 100 for implementing one or more embodiments of deterministic file content generation. In one configuration, computing device 100 includes at least one processing unit 102 and memory 104. Depending on the exact configuration and type of computing device, memory 104 may be volatile (such as RAM), non-volatile (such as ROM, flash memory, etc.) or some combination of the two. This configuration is illustrated in FIG. 1 by dashed line 106. In other embodiments, device 100 may include additional features and/or functionality. For example, device 100 may also include additional storage (e.g., removable and/or non-removable) including, but not limited to, magnetic storage, optical storage, and the like. Such additional storage is illustrated in FIG. 1 by storage 108. In one embodiment, computer readable instructions to implement embodiments of the invention may be stored in storage 108. Storage 108 may also store other computer readable instructions to implement an operating system, an application program, and the like. The term “computer readable media” as used herein includes computer storage media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions or other data. Memory 104 and storage 108 are examples of computer storage media. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by device 100. Any such computer storage media may be part of device 100. Device 100 may also include communication connection(s) 112 that allow device 100 to communicate with other devices. Communication connection(s) 112 may include, but is not limited to, a modem, a Network Interface Card (NIC), or other interfaces for connecting computing device 100 to other computing devices. Communication connection(s) 112 may include a wired connection or a wireless connection. Communication connection(s) 112 may transmit and/or receive communication media. Communication media typically embodies computer readable instructions or other data in a “modulated data signal” such as a carrier wave or other transport mechanism and includes any information delivery media. The term “computer readable media” may include communication media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Device 100 may include input device(s) 114 such as keyboard, mouse, pen, voice input device, touch input device, infra-red cameras, video input devices, and/or any other input device. Output device(s) 116 such as one or more displays, speakers, printers, and/or any other output device may also be included in device 100. Input device(s) 114 and output device(s) 116 may be connected to device 100 via a wired connection, wireless connection, or any combination thereof. In one embodiment, an input device or an output device from another computing device may be used as input device(s) 114 or output device(s) 116 for computing device 100. Components of computing device 100 may be connected by various interconnects, such as a bus. Such interconnects may include a Peripheral Component Interconnect (PCI), such as PCI Express, a Universal Serial Bus (USB), firewire (IEEE 1394), an optical bus structure, and the like. In another embodiment, components of computing device 100 may be interconnected by a network. For example, memory 104 may be comprised of multiple physical memory units located in different physical locations interconnected by a network. Those skilled in the art will realize that storage devices utilized to store computer readable instructions may be distributed across a network. For example, a computing device 130 accessible via network 120 may store computer readable instructions to implement one or more embodiments of the invention. Computing device 100 may access computing device 130 and download a part or all of the computer readable instructions for execution. Alternatively, computing device 100 may download pieces of the computer readable instructions, as needed, or some instructions may be executed at computing device 100 and some at computing device 130. Those skilled in the art will also realize that all or a portion of the computer readable instructions may be carried out by a dedicated circuit, such as a Digital Signal Processor (DSP), programmable logic array, and the like. Turning now to FIG. 2, FIG. 2 shows a block diagram of an example system for testing network usage load 200. A system for testing network usage load 200 typically includes a first client 202 communicatively coupled to a server 206, and second client 204 also communicatively coupled to a server 206. Note that the first client 202 and the second client 204 are also communicatively coupled by virtue of the common communicative coupling to server 206. The process of load testing a server system, such as the server 206, typically involves creating a predetermined demand on a server system and monitoring the functioning of the server system in response to the predetermined demand. For example, a load test may involve a large number of clients connecting to a server. Each client may send a large amount of information to the server for the server to process. The ability of the server to respond to the large number of clients and process large amounts of information may be measured to determine the performance of the server when deployed. If a load test is intended to test the response of a server to network traffic, it may not be necessary for any or all of the clients or the server to actually store the received network traffic. However, in order to verify that the data was received at the server correctly the server may store the network traffic to examine the received data. In this case, the received data must either be stored on disk, or stored in memory. In the case where file system access is to be a part of the load test, a system for testing network usage load 200 may be used to load test a server 206. In the system for testing network usage load 200, the first client 202 may include an example seeded file signature 208 that will be described more fully in the discussion of FIG. 3. The server 206, first client 202, and second client 204 also include an example seeded file expansion method 210 that will be described more fully in the discussion of FIG. 4. However, for the purposes of discussion, the seeded file signature 208 may be comprised of numerical data including a seed value, a file length, a delta start block, and a delta length. The seed file expansion method 210 is configured to expand the seeded file signature 208 to an expanded file. The contents of the expanded file are determined by passing the seed value to a function configured to deterministically generate random data using the seed value. The seed file expansion method 210 uses the file length included in the seed file signature 208 to determine the size of the expanded file. The contents of the expanded file are then appended to the seeded file signature to create the complete expanded file. In this way, the first client 202 may store the smaller seeded file signature 208, then expand the seeded file signature 208 to create a network stream representing the expanded file that may be comprised of the. The first client 202 may then send the stream representing the expanded file over the network connection to the server 206. The server 206 may then strip off the appended file contents and store only the seeded file signature 208 because the server 206 may reproduce the expanded file using the seed file expansion method 210. Additionally or alternatively, the server 206 may store the streamed expanded file on disk and/or in memory. The server 206 may then send a stream representing the expanded file to the second client 204, and the second client 204 may also strip off the appended file and store only the seeded file signature 208. Additionally or alternatively, the second client 204 may store the stream representing the expanded file. The delta start block and the delta length of the seeded file signature 208 provide a method for deterministically modifying an expanded file. The delta length may correspond to an offset in the expanded file and the delta length may correspond to the length of the section to be modified. The method for determining the content of the delta section will be discussed in more detail in the discussion of FIG. 4. Turning now to FIG. 3, FIG. 3 shows an example of a seeded file signature 208. The seeded file signature is illustrated as part of an expanded seeded file 314 including generated content 310 and modified content 312. The seed file signature 208 is a data structure comprised of four data fields. The first data field includes a seed value 302. The second data field includes a file length value 304. The third data field includes a delta region offset value 306. The fourth data field includes a delta region length value 308. In an exemplary implementation, each of the four data fields, 302, 304, 306, and 308 are stored in computer readable media as a file. Each of the four data fields 302, 304, 306, and 308 are 8 bytes in size for a total of 32 bytes. Alternatively, each of the four data fields 302, 304, 306, and 308 may be of any size and may be stored in any order. The seed value 302 may be any value and of any type. In an exemplary implementation, the seed value 302 is used to seed a pseudorandom number generating function to produce a series of random values to act as the generated content 310 for the expanded seeded file 314. To that end, the file length value 304 may also be of any value of any type. In an exemplary implementation, the file length value 304 acts to determine the number of iterations to run the pseudorandom number generating function, and thus determine the length of the generated content 310 for an expanded seeded file 314. In an alternative implementation, the file length value 304 acts to determine the size of the data set that will be generated by the pseudorandom number generating function. The delta region offset value 306 may be of any value and of any type. In an exemplary implementation, the delta region offset value 306 in an integer representing the address or offset into the generated content 310 of an expanded seeded file 314. Such a delta region offset value 306 indicates that a separate deterministic function is to be applied to the result of subsequent iterations of the pseudorandom number generating function to produce modified content 312 within the generated content 310. To that end, the delta region length value 306 may be of any value of any type. In an exemplary implementation, the delta region length value 306 acts to determine the number of iterations to run the separate deterministic function to determine modified content 312 for the expanded seeded file 314. Note that the delta region offset 306 may not be smaller than the data representing the beginning of the generated content 310. Accordingly, the length represented by summing the delta region offset value 306 and the delta region length value 308 may not exceed the file length 304. Turning now to FIG. 4, FIG. 4 shows an example seed file expansion method 210. Block 410 refers to an operation in which the signature is extracted from a seeded file. Such a signature may be implemented in accordance with the seeded file signature 208 (from FIG. 3). In an exemplary implementation, the signature includes a seed value, a file length, a delta region offset, and a delta region length. Block 415 refers to an operation in which a pseudorandom number generator is seeded with the seed value. Such a pseudorandom number generator may be implemented such that when seeded with the seed value the pseudorandom number generator produces a reproducible set of random numbers. In an alternative implementation, any seeded content generating function that accepts a seed value and deterministically produces a set of reproducible data may be used. Block 420 refers to an operation in which a counter is initialized at zero and iteratively runs for a number of times equivalent to the file length value. Block 425 refers to an operation in which it is determined whether or not the current value of the counter is greater than the delta region offset value. In response to a positive determination, it has been determined that the counter is in the delta region of the generated contents and flow continues to Block 435. In response to a negative determination, it has been determined that the counter is not in the delta region of the generated contents and flow continues to Block 430. Block 430 refers to an operation in which the current output of the pseudorandom number generator is appended to the generated content. If there are more iterations remaining in the counter, flow returns to Block 420. If there are no more iterations remaining in the counter, the generated content has been created and flow ends. Block 435 refers to an operation in which the current output of the pseudorandom number generator is passed to a deterministic integer function to produce a modified value. An example of a deterministic integer function may be a function that accepts an integer parameter and adds another predetermined value to it. It is to be appreciated, however, that any deterministic integer function may be used. Once calculated, the modified value is appended to the generated content. If there are more iterations remaining in the counter, flow returns to Block 420. If there are no more iterations remaining in the counter, the generated content has been created and flow ends.	G	60G06	161G06F	17	30
11866619	US20080082769A1-20080403	Mass storage system and method	ACCEPTED	20080318	20080403	[]	G06F1200	["G06F1200"]	7873790	20071003	20110118	711	118000	68309.0	BANSAL	GURTEJ	[{"inventor_name_last": "Bouchou", "inventor_name_first": "Jean-Louis", "inventor_city": "Rosny-Sous-Bois", "inventor_state": "", "inventor_country": "FR"}, {"inventor_name_last": "Dejon", "inventor_name_first": "Christian", "inventor_city": "Paris", "inventor_state": "", "inventor_country": "FR"}]	The present invention concerns a storage method and system (1) comprising processing means (11) and storage resources (20, 100) containing firstly storage means (20) including at least one physical library (P201 to P20n) and secondly memory means (100) called a cache (100), in which the processing means (11) of the storage system (1), vis-à-vis the computer platforms (101 to 10n), emulate at least one virtual library (V201 to V20n) from at least one physical library (P201 to P20n) which the storage system has under its control, characterized in that the processing means (11) of the storage system (1) comprise a management module (30) responsible for emulation and managing priorities over time for accesses to the storage resources (20, 100) using the results of calculations of at least one cache activity index per determined periods of time, and of at least one cache occupancy rate at a given time.	1. A storage system (1) for data generated, in at least one format, by at least one computer platform (101 to 10n) and transmitted to the storage system (1) via at least one communication network (RC) through access means (101) of computer platforms (101 to 10n) to the storage system (1) comprising processing means (11) and storage resources (20, 100) comprising firstly: storage means (20) containing at least one physical library (P201 to P20n) including at least one robot (P22) capable of loading and unloading at least one data storage cartridge (P211 to P21n) in and from at least one reader (P2001 to P200n) to allow the writing and reading of data transmitted by the computer platform (101 to 10n) in the physical library (P201 to P20n), and secondly cache memory means (100), which the said processing means (11) of the storage system (1) emulate, vis-à-vis the computer platforms (101 to 10n), at least one virtual library (V201 to V20n) from at least one physical library (P201 to P20n) under control of the storage system (1), the data thus stored in the physical library (P201 to P20n) and the virtual library (V201 to V20n) being grouped into groups of virtual volumes of determined size having at least one image (V1 to Vn) in the physical library (P201 to P20n) and/or one image (V′1 to V′n) in the virtual library (V201 to V20n), the access means (101) of the platforms (101 to 10n) to the storage system (1) thereby being arranged for accessing for reading and writing, via the communication network (RC), an image (V′1 to V′n) in the cache (100) of each of the virtual volumes stored by the storage system (1), the storage system being further characterized in that the processing means (11) of the storage system (1) comprises a management module (30) managing accesses to the storage resources (20, 100) both in the physical library (P201 to P20n) and in the virtual library (V201 to V20n), in relation to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1), the management module (30) being responsible for emulation of the virtual volumes (V1 to Vn) of the physical library into virtual volumes (V′1 to V′n) of the virtual library of the cache (100) and comprising firstly a of cache activity control module (31) calculating at least one cache activity index per determined periods of time, reflecting utilization of the access bandwidth to the cache (100), and secondly cache occupancy control module (32) calculating at least one cache occupancy rate at a given time, the management module (30) triggering said calculations periodically or on an ad hoc basis, whenever space is allocated for a new virtual volume (V′1 to V′n) in the cache (100) and using the result of said calculations, with reference to at least one management algorithm (AG) of the access bandwidth to the cache and implemented in the storage system (1), so as to regulate occupancy of the cache (100) while managing priorities over time for access to the storage resources (20, 100) by the computer platforms (101 to 10n) to flush the cache (100) by a read/write operation of the virtual volumes (V′1 to V′n) of the cache (100) or by the system (1) itself for at least one operation, thereby enabling the copying of data from at least one virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) towards at least one virtual volume (V1 to Vn) of the physical library (P201 to P20n). 2. The storage system according to claim 1, characterized in that the cache (100) consists of a plurality of hard disks (1001 to 100n) on which a plurality of partitions (P1 to Pn) is distributed, the management module (30) comprising an organization module (33) permanently keeping up to date information on the distribution of the partitions (P1 to Pn) installed on the hard disks and on the distribution of the data recorded on the different partitions (P1 to Pn), said organization module (33), on the basis of said up-to-date information, generating at least one directory (RP) containing information on the locations and utilization of the virtual volumes (V′1 to V′n) of the cache (100), the virtual volumes (V′1 to V′n) on which reading or writing is in progress being identified as open virtual volumes, and the virtual volumes on which no reading or writing is in progress being identified as closed virtual volumes. 3. The storage system according to claim 2, characterized in that the management module (30) provides access to the content of the storage resources (20, 100) of the system (1) and verifies the content of the physical library (P201 to P20n) and virtual library (V201 to V20n) to assign to each of the virtual volumes a status value from among at least the following statuses: <<disk only>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100) but does not have an image in the physical library or has at least one image in the physical library (P201 to P20n) which is not valid i.e. does not contain the same data as the image (V′1 to V′n) in the virtual library (V201 to V20n); <<out of cache>> status when the virtual volume does not have any image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100); <<disk and tape>> status when the virtual volume has valid images both in the virtual library (V201 to V20n) of the cache (100) and in the physical library (P200 to P20n); <<swapping in>> status when the virtual volume has an image (V′1 to V′n) in the progress of being loaded in the virtual library (V201 to V20n), from an image (V1 to Vn) in the physical library (P201 to P20n); <<swapping out>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) in the progress of being copied into an image (V1 to Vn) of the physical library (P201 to P20n); <<incomplete>> status when the virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) is open and does not contain any data or contains incomplete data; <<moving out>> status when the virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) is in the progress of being copied from one partition (P1 to Pn) of the cache (100) to another; <<swappable>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100) but has at least one image (V1 to Vn) in the physical library (P201 to P20n) which is not valid or the image (V′1 to V′n) in the virtual library (V201 to V20n) is in progress of being copied into an image (V1 to Vn) of the physical library (P201 to P20n), i.e. the volume either has <<disk only>> status or has <<swapping out>> status. 4. The storage system according to claim 2, wherein the cache occupancy control module (32) calculates firstly an individual occupancy rate corresponding to calculation of the occupancy rate on each of the partitions (P1 to Pn) of the cache (100) individually, and secondly a mean occupancy rate corresponding to calculation of the occupancy rate of all the partitions (P1 to Pn) of the cache (100). 5. The storage system according to claim 4, characterized in that the mean occupancy rate of the cache (100) at a given time, calculated by the cache occupancy control module (32), corresponds for all the partitions (P1 to Pn) of the cache (100), to the sum of the size of the data present in the closed virtual volumes (V′1 to V′n) having <<disk only>> status and the size for all the partitions (P1 to Pn) allocated to the open virtual volumes (V′1 to V′n), irrespective of their status, this sum being compared, for all partitions (P1 to Pn), to the total size available in all the partitions (P1 to Pn) of the cache (100), to obtain the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100). 6. The storage system according to claim 4, characterized in that the individual occupancy rate of each partition (P1 to Pn) of the cache (100) at a given time, calculated by the cache occupancy control module (32), corresponds, for each of the partitions (P1 to Pn) of the cache (100) individually, to the size of the data present in the virtual volumes (V′n to V′n) having <<disk only>> status, whether they are open or closed, this size being compared for each partition (P1 to Pn) with the total available size in the partition (P1 to Pn) under consideration, to obtain the individual occupancy rate of each partition (P1 to Pn). 7. The storage system according to claim 1, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 8. The storage system System according to claim 7, characterized in that the management module (30) compares the activity index of the cache with a minimum activity threshold and a maximum activity threshold, compares the individual occupancy rate of the cache with a maximum occupancy threshold and compares the mean occupancy rate of the cache with a first priority threshold, below which occupancy of the cache (100) has priority over flushing, and a second flush start threshold, above which flushing of the cache (100) can be performed, to manage accesses to the cache (100) by the management algorithm (AG) for managing the access bandwidth to the cache, implemented in the storage system, and comprising at least one of the following rules: if the value of the individual occupancy rate of a partition (P1 to Pn) of the cache (100) is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache (100), the flush operation of the cache (100) is essential and is authorized to start to the possible detriment of accesses to the cache by the computer platforms (101 to 10n), part of the access bandwidth to the cache (100) then being used for the copying of one or more virtual volumes (V′1 to V′n) of this partition (P1 to Pn) into the physical library (P201 to P20n) during this flush operation, if the value of the activity index of the cache (100) is less or equal to the value of the minimum activity threshold, any flush operation of the cache (100) is authorized to start, to allow copying of one or more virtual volumes (V′1 to V′n) towards the physical library (P201 to P20n), if the value of the activity index of the cache (100) lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache (100) already in progress is authorized to continue, the copying of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n) being authorized during this flush operation in progress, but if no flush operation is in progress a new flush operation of the cache (100) is not authorized to start, if the value of the activity index of the cache (100) is higher than the value of the maximum activity threshold, a new flush operation of the cache (100) is not authorized to start and a flush operation of the cache (100) already in progress is interrupted, to the benefit of accessing to the cache (100) by the computer platforms (101 to 10n), unless the value of the individual occupancy rate of the cache (100) is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache (100) is higher than the flush start threshold, new copying of one or more virtual volumes (V′1 to V′n) from the cache (100) into the physical library (P201 to P20n), during a flush operation already in progress, then being forbidden, whilst copying already in progress of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n), during this flush operation in progress, is authorized to be completed, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the value of the priority threshold, accesses to the storage resources (20, 100) in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1) have priority over the accesses needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100), this copying then possibly being deferred until release of these resources (20, 100), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the priority threshold, accesses to the storage resources (20, 100) in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system, do not have priority over the accesses needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100) which can therefore be started or continued to the possible detriment of accesses to the storage resources (20, 100) by the computer platforms (101 to 10n), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is only authorized to start if the value of the activity index of the cache (100) is less or equal the value of the minimum activity threshold, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is essential and is authorized to start. 9. The storage system according to claim 7, characterized in that the cache activity control module (31) comprises means for consulting information generated by an organization module (33), to calculate the activity index of the cache (100) by counting the number of open virtual volumes, the maximum activity threshold corresponding to the total number of virtual volumes (V′1 to V′n) of the cache (100) open at the same time which consume a fraction of the bandwidth that is considered too high to allow an internal operation to start which requires access to the cache (100). 10. The storage system according to claim 4, characterized in that the cache occupancy control module comprises means for consulting the information generated by an organization module (33), to calculate firstly the mean occupancy rate of the cache (100) by comparing the sum of the total size of the data present in the open virtual volumes (V′1 to V′n), irrespective of their status, and the total size of the data present in the closed virtual volumes (V′1 to V′n) having <<disk only>> status, with the total storage capacity in all the partitions (P1 to Pn) of the cache (100), and secondly to calculate the individual occupancy rate of each of the partitions (P1 to Pn) of the cache (100) by comparing, for a given partition (P1 to Pn), the size of the data present in the virtual volumes (V′1 to V′n) having <<disk only>> status, whether they are open or closed, with the total storage capacity of this partition (P1 to Pn) of the cache (100). 11. The storage system according to claim 10, characterized in that the organization module (33) cooperates with the cache activity control module (31) and the cache occupancy module (32) control to distribute the virtual volumes (V′1 to V′n) equitably over the different partitions (P1 to Pn) of the cache (100), in order to promote homogeneous distribution over all the disks carrying the different partitions (P1 to Pn) of the cache (100). 12. The storage system according to claim 4, characterized in that the management module (30), during the flush operation of the cache (100), uses the results of the calculations made by the cache occupancy control module (32) to select those virtual volumes (V′1 to V′n) of the cache (100) to be copied into the physical library (P201 to P20n), the virtual volumes (V′1 to V′n) thus selected being the closed virtual volumes (V′1 to V′n) having <<disk only>> status and which were the less recently accessed, for reading or writing, by the computer platforms (101 to 10n), either in a given partition (P1 to Pn) of the cache (100) if the value of the individual occupancy rate of this partition is greater or equal to the value of the maximum occupancy threshold, or in all the partitions (P1 to Pn) of the cache (100) if the values of the individual occupancy rates of all the partitions are below the value of the maximum occupancy threshold. 13. The storage system according to claim 12, characterized in that the management module (30) comprises an activity control module for the physical library (P201 to P20n), keeping permanently up to date at least information on the utilization of the readers (P2001 to P200n) and/or of the cartridges (P211 to P21n) of the physical libraries (P201 to P20n) under the control of the storage system (1), this reader utilization information thereby enabling the management module (30) to manage priorities over time for accesses to the storage resources (20, 100), firstly by the system (1) itself to flush at least one virtual volume (V′1 to V′n) of the cache (100) towards at least one virtual volume (V1 to Vn) of the physical library (P201 to P20n), and secondly by the computer platforms (101 to 10n) to read/write a virtual volume (V′1 to V′n) not present in the cache (100) and therefore necessitating consultation of the physical library (P201 to P20n) to copy a virtual volume (V1 to Vn) of this physical library (P201 to P20n) towards the cache (100), in the form of a virtual volume (V′1 to V′n) of the virtual library (V201 to V20n). 14. The storage system according claim 13, characterized in that the management module (30), through its access means to the content of the storage resources (20, 100) of the system (1), keeps permanently up to date at least information on the validity of the virtual volumes (V1 to Vn) present in the cartridges (P211 to P21n) of the physical libraries (P201 to P20n) under the control of the storage system (1), with respect to the virtual volumes (V′1 to V′n) which may have been modified in the cache (100) by the computer platforms (101 to 10n), this validity information thereby enabling the management module (30) to compare the space occupied by the obsolete virtual volumes (V1 to Vn) in the cartridges (P211 to P21n) of the physical library (P201 to P20n) with a maximum invalidity threshold, and when this space of obsolete virtual volumes (V1 to Vn) reaches this threshold, to perform compacting of the valid volumes (V1 to Vn) of this physical library (P201 to P20n), in the cartridges (P211 to P21n) containing virtual volumes (V1 to Vn) in the physical library (P201 to P20n) that are not utilized and/or corresponding to closed virtual volumes (V′1 to V′n) in the cache (100), by controlling the reading of all the valid volumes (V1 to Vn) of the source cartridges (P211 to P21n) containing obsolete volumes (V1 to Vn) and simultaneously copying these valid volumes (V1 to Vn) into target cartridges (P211 to P21n), so as to erase these source cartridges (P211 to P21n) and obtain only cartridges (P211 to P21n) containing valid volumes (V1 to Vn) in the physical library (P201 to P20n) and empty cartridges. 15. The storage system according to claim 14, characterized in that the management module (30), responsible for emulation of the virtual volumes (V1 to Vn) of the physical library (P201 to P20n) into virtual volumes (V′1 to V′n) of the virtual library (V201 to V20n) of the cache (100), offers the possibility that a virtual volume (V′1 to V′n) of the cache (100) may have multiple images (V1 to Vn) in the physical library (P201 to P20n), and that those virtual volumes (V′1 to V′n) of the cache (100) taken into account by the module (32) of cache occupancy control for the calculation of the occupancy rate, are volumes which correspond to the virtual volumes (V′1 to V′n) of the cache (100) having <<disk only>> status, i.e. having images (V1 to Vn) present in the physical library (P201 to P20n) which are not all valid. 16. The storage system according to claim 14, characterized in that the management module (30) uses the results of the operations performed by the cache activity control module (31), cache occupancy control module (32) the activity control module (34) of the physical library (P201 to P20n), so that the compacting of the valid volumes (V1 to Vn) of the physical library (P201 to P20n) by the management module (30) is conducted in relation to the activity and occupancy of the cache (100), giving preference to access to the storage resources (20, 100) by the computer platforms (101 to 10n) over accessing required for this compacting. 17. The storage system according to claim 16, characterized in that the processing means (11) runs a software application forming all the modules (30, 31, 32, 33 and 34) of the storage system (1) and responsible for the interoperability of the different means of the system, this software application cooperating with an operating system installed on the storage system to manage the operations to be performed by generating information on at least the locations and utilization of all the data present in the storage system (1), the data needed for running this application being previously recorded in a memory accessible by the processing means (11) of the system (1). 18. Method for saving/storing data generated, in at least one format, by at least one computer platform (101 to 10n) and transmitted to a storage system (1) via a communication network (RC) through platform access means (101) accessing the storage system (1), the storage system comprising storage resources (20, 100) comprising firstly storage means (20) containing at least one physical library (P201 to P20n) including at least one robot (P22) able to load and unload at least one data storage cartridge (P211 to P21n) in and from at least one reader (P2001 to P200n) allowing the writing and reading of data transmitted by the computer platform (101 to 10n) in the physical library (P201 to P20n), and secondly comprising cache memory means (100), in which the processing means (11) of the storage system (1), vis-à-vis the computer platforms (101 to 10n), emulate at least one virtual library (V201 to V20n) from at least one physical library (P201 to P20n) which the storage system (1) has under its control, the data thus stored in the physical library (P201 to P20n) and in the virtual library (V201 to V20n) being grouped into virtual volumes of determined size having at least image (V1 to Vn) in the physical library (P201 to P20n) and/or one image (V′1 to V′n) in the virtual library (V201 to V20n), the access means (101) of the platforms (101 to 10n) to the storage system (1) thereby accessing for reading and writing, via the communication network (RC), the image (V′1 to V′n) in the cache (100) of each of the virtual volumes stored by the storage system, the method being characterized in that it comprises at least the following steps: emulation (61) of the virtual volumes (V1 to Vn) of the physical library (P201 to P20n) into virtual volumes (V′1 to V′n) of the virtual library (V201 to V20n) of the cache (100), by a management module (30) present in the processing means (11) of the storage system (1) and managing accesses to the storage resources (20, 100) both to virtual volumes de (V1 to Vn) of the physical library (P201 to P20n) and to virtual volumes (V′1 to V′n) of the cache (100), in relation to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1); calculation (62), by a cache activity control module (31), of at least one activity index of the cache (100) per determined periods of time, reflecting utilization of the access bandwidth to the cache (100), this calculation step (62) being repeated to monitor changes in activity of the cache (100) periodically or on an ad hoc basis whenever space is allocated for a new virtual volume (V′1 to V′n) in the cache (100); calculation (63), by a cache occupancy control module (32), of at least one occupancy rate of the cache (100) at a given time, this calculation step (63) being repeated to monitor changes in occupancy of the cache (100) periodically or an ad hoc basis whenever space is allocated for a new virtual volume (V′1 to V′n) in the cache (100); decision (64), by the management module (30), in relation to the results of these calculations and to at least one management algorithm (AG) for managing the access bandwidth to the cache (100), implemented in the storage system (1), between authorization (70) or interdiction (80) of access to the storage resources (20, 100) by the computer platforms (101 to 10n) to read/write virtual volumes (V′1 to V′n) in the cache (100), or by the system (1) itself for at least one operation, called a cache flush, allowing the copying of data from at least one virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) to at least one virtual volume (V1 to Vn) of the physical library (P201 to P20n), so as to regulate occupancy of the cache (100) whilst managing priorities over time for accesses to the resources by the platforms and by the system itself. 19. Method according to claim 18, characterized in that it comprises firstly at least one installation step (67) to install a plurality of partitions (P1 to Pn) on a plurality of hard disks (1001 to 100n) forming the cache (100), and secondly at least one step (68) for the creation and updating, by an organization module (33), of data representing information on the distribution of partitions (P1 to Pn) and on the distribution of data recorded in the different partitions (P1 to Pn), said organization module (33), on the basis of this information, generating at least one directory (RP) containing information on the locations and utilization of the virtual volumes (V′1 to V′n), the virtual volumes (V′1 to V′n) on which reading or writing is in progress being identified as open virtual volumes, and the virtual volumes on which no reading or writing is in progress being identified as closed virtual volumes. 20. Method according to claim 19, characterized in that it comprises a verification step of the content of the physical library (P201 to P20n) and of the virtual library (V201 to V20n) by the management module (30), via access means to the content of the storage resources (20, 100) of the system (1), followed by an assignment step, to each of the virtual volumes, of a value called a status, from among at least the following statuses: <<disk only>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100) but does not have an image in the physical library, or has at least one image (V1 to Vn) in the physical library (P201 to P20n) which is not valid, i.e. does not contain the same data as the image (V′1 to V′n) in the virtual library (V201 to V20n); <<out of cache>> status when the virtual volume does not have any image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100); <<disk and tape>> status when the virtual volume has valid images both in the virtual library (V201 to V20n) of the cache (100) and in the physical library (P201 to P20n); <<swapping in>> status when the virtual volume has an image (V′1 to V′n) in the progress of being loaded into the virtual library (V201 to V20n), from an image (V1 to Vn) in the physical library (P201 to P20n); <<swapping out>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) in the progress of being copies into an image (V1 to Vn) of the physical library (P201 to P20n); <<incomplete>> status when the virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) is open and does not contain any data, or contains incomplete data; <<moving out>> status when the virtual volume (V′1 to V′n) of the virtual library (V201 to V20n) is in the progress of being copied from one partition (P1 to Pn) of the cache (100) to another; and <<swappable>> status when the virtual volume has an image (V′1 to V′n) in the virtual library (V201 to V20n) of the cache (100) but has at least one image (V1 to Vn) in the physical library (P201 to P20n) which is not valid or the image (V′1 to V′n) in the virtual library (V201 to V20n) is in the progress of being copied into an image (V1 to Vn) of the physical library (P201 to P20n), i.e. the volume either has <<disk only>> status or <<swapping out>> status. 21. Method according to claim 19, characterized in that step (63) to calculate the occupancy rate of the cache (100) at a given time, by the cache occupancy control module (32), comprises firstly a step (635) to calculate a so-called individual occupancy rate, corresponding to calculation of the occupancy rate on each of the partitions (P1 to Pn) of the cache (100) individually, and secondly a step (636) to calculate a so-called mean occupancy rate, corresponding to calculation of the occupancy rate of all the partitions (P1 to Pn) of the cache (100). 22. Method according to claim 21, characterized in that the step (636) to calculate the mean occupancy rate of the cache (100), by the cache occupancy control module (32) consists of measuring, for all the partitions (P1 to Pn) of the cache (100), the sum of the size of the data present in the closed virtual volumes (V′1 to V′n) having <<disk only>> status and the size allocated to the open virtual volumes (V′1 to V′n), irrespective of their status, this sum being compared with the total size available in all the partitions (P1 to Pn) of the cache (100), to obtain the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100). 23. Method according to claim 21, characterized in that step (635) to calculate the individual occupancy rate of each partition (P1 to Pn) of the cache (100), by the cache occupancy control module, consists of measuring, for each of the partitions (P1 to Pn) of the cache (100) individually, the total size of the data present in the virtual volumes (V′1 to V′n) having <<disk only>> status, whether they are open or closed, this size being compared with the total available size in the partition (P1 to Pn) under consideration of the cache (100), to obtain the mean occupancy rate of each of the partitions (P1 to Pn) of the cache (100). 24. Method according to claim 18, characterized in that the calculations step (62) to calculate the activity index of the cache (100) per determined periods of time, by the cache activity control module, consists of calculating a mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) opened simultaneously during each determined time period. 25. Method according to claim 22, characterized in that it comprises at least one additional comparison step (65) to compare the activity index of the cache with a minimum activity threshold and a maximum activity threshold, a comparison step (661) of the individual occupancy rate of the cache with the maximum occupancy threshold and a comparison step (662) of the mean occupancy rate with a first threshold called a priority threshold, below which occupancy of the cache (100) has priority over flushing, and with a second threshold called a flush start threshold above which flushing of the cache (100) can be performed, implemented by the management module (30) to manage accesses to the cache (100) by means of the management algorithm (AG) for managing the access bandwidth to the cache (100), implemented in the storage system (1), and comprising at least one of the following rules: if the value of the individual occupancy rate of a partition (P1 to Pn) of the cache (100) is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache (100), the flush operation of the cache (100) is essential and is authorized to start to the possible detriment of accesses to the cache (100) by the computer platforms (101 to 10n), part of the access bandwidth to the cache (100) then being used to copy one or more virtual volumes (V′n to V′n) from this partition (P1 to Pn) towards the physical library (P201 to P20n) during this flush operation, if the value of the activity index of the cache (100) is less or equal to the minimum activity threshold, any flush operation of the cache (100) is authorized to start, to allow the copying of one or more virtual volumes (V′1 to V′n) towards the physical library (P201 to P20n), if the value of the activity index of the cache (100) lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache (100) already in progress is authorized to continue, the copying of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n) being authorized during this flush operation in progress, but if no flush operation is in progress a new flush operation of the cache (100) is not authorized to start, if the value of the activity index of the cache (100) is higher than the value of the maximum activity threshold, a new flush operation of the cache (100) is not authorized to start and a flush operation of the cache (100) already in progress is interrupted, to the benefit of accessing to the cache (100) by the computer platforms (101 to 10n), unless the value of the individual occupancy rate of the cache (100) is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache (100) is higher than the flush start threshold, new copying of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n), during a flush operation already in progress, then being forbidden, whilst copying already in progress of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n), during this flush operation in progress, is authorized to be completed, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the priority threshold, accesses to the storage resources (20, 100), in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1), have priority over accessing needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100), this copying then possibly being deferred until release of these resources (20, 100), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the priority threshold, accesses to the storage resources (20, 100) in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1) do not have priority over accesses needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100), which can therefore start or continue to the possible detriment of accessing to the storage resources (20, 100) by the computer platforms (101 to 10n), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is only authorized to start if the value of the activity index of the cache (100) is less or equal to the value of the minimum activity threshold, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is essential and is authorized to start. 26. Method according to claim 19, characterized in that the calculation step (62) to calculate the activity index of the cache (100), by the cache activity control module (31), comprises at least one consultation step (621) of the data generated by the organization module (33), to calculate the activity index of the cache (100) by counting the number of open virtual volumes in the cache (100), the maximum activity threshold corresponding to the total number of virtual volumes (V′1 to V′n) of the cache (100) open at the same time which consume a fraction of the access bandwidth considered too high to allow the start of an internal operation requiring access to the cache (100). 27. Method according to claim 22, characterized in that the calculation step (63) to calculate the occupancy rate of the cache (100), by the cache occupancy control module (32), comprises at least one consultation step (631) of the data generated by the organization module (33) to calculate firstly the mean occupancy rate of the cache (100) by comparison (632) of the sum of the total size of the data present in the open virtual volumes (V′1 to V′n), irrespective of their status, and the total size of the data present in the closed virtual volumes (V′1 to V′n) having <<disk only>> status, with the total storage capacity of all the partitions (P1 to Pn) of the cache (100), and secondly the individual occupancy rate of each of the partitions (P1 to Pn) of the cache (100) by comparison (633), for a given partition (P1 to Pn), of the size of the data present in the virtual volumes (V′1 to V′n) having <<disk only>> status, whether they are open or closed, with the total storage capacity of this partition (P1 to Pn) of the cache (100). 28. Method according to claim 19, characterized in that the emulation step (61) of the virtual volumes (V′1 to V′n) by the management module (30) comprises a cooperation step (611) of the organization module (33) with the cache activity control module (31) and the cache occupancy control module (32) to distribute the virtual volumes (V′1 to V′n) equitably over the different partitions (P1 to Pn) of the cache (100), in order to promote homogeneous distribution over all the disks carrying the different partitions (P1 to Pn) of the cache (100). 29. Method according to claim 18, characterized in that the flush operation of the cache (100), results from the use, by the management module (30), of the results of the calculations made by the cache occupancy control module (32), to select the virtual volumes (V′1 to V′n) of the cache (100) to be copied into the physical library (P201 to P20n), the virtual volumes (V′1 to V′n) thus selected being closed virtual volumes (V′1 to V′n) having <<disk only>> status and which were the less recently accessed for reading or writing by the computer platforms (101 to 10n), either in a given partition (P1 to Pn) of the cache (100) if the value of the individual occupancy rate of this partition is greater or equal to the value of the maximum occupancy threshold, or in all the partitions (P1 to Pn) of the cache (100) if the values of the individual occupancy rates of all the partitions are lower than the value of the maximum occupancy threshold. 30. Method according to claim 18, characterized in that it comprises at least one step (71) for the creation and update, by an activity control module (34) of the physical library (P201 to P20n), of data representing information on utilization of the readers and/or of the cartridges of the libraries (P201 to P20n) under the control of the storage system (1), this information thereby enabling the management module (30) to manage priorities over time for accesses to the storage resources (20, 100), firstly by the system (1) itself to flush at least one virtual volume (V′1 to V′n) from the cache (100) towards a volume (V1 to Vn) of the physical library (P201 to P20n), and secondly by the computer platforms (101 to 10n) to read/write a virtual volume (V′1 to V′n) not present in the cache (100) and therefore necessitating consultation of the physical library (P201 to P20n) to copy a volume (V1 to Vn) from this physical library (P201 to P20n) to the cache (100), in the form of a virtual volume (V′1 to V′n) of the virtual library (V201 to V20n). 31. Method according to claim 20, characterized in that it comprises at least one step (69) for the creation and update, by the management module (30), of data representing information on the validity of the volumes (V1 to Vn) present in the cartridges (P211 to P21n) of the physical libraries (P201 to P20n) under the control of the storage system (1), with respect to the virtual volumes (V1 to Vn) which may have been modified in the cache (100) by the computer platforms (101 to 10n), this information on validity enabling the management module (30) to implement a comparison step (89) of the space occupied by obsolete virtual volumes (V1 to Vn) in the cartridges (P211 to P21n) of the physical library (P201 to P20n) with a maximum invalidity threshold and, if this space occupied by these obsolete virtual volumes (V1 to Vn) reaches this threshold, to implement a compacting step (90) of the valid volumes (V1 to Vn), taken from cartridges (P211 to P21n) containing volumes (V1 to Vn) that are non-utilized and/or correspond to closed virtual volumes (V′1 to V′n), by controlling the reading (92) of all the valid volumes (V1 to Vn) of the source cartridges (P211 to P21n) containing obsolete volumes (V1 to Vn) and simultaneously copying (93) these valid volumes (V1 to Vn) into target cartridges (P211 to P21n), so as to erase these source cartridges (P211 to P21n) and only obtain cartridges (P211 to P21n) containing valid volumes (V1 to Vn) in the physical library (P201 to P20n). 32. Method according to claim 31, characterized in that the emulation steps (61) of the virtual volumes (V1 to Vn) of the physical library (P201 to P20n) into virtual volumes (V′1 to V′n) of the virtual library (V201 to V20n) of the cache (100) and the management steps of the cache (100) by the management module (30), offer the possibility that a virtual volume (V′1 to V′n) of the cache (100) may have multiple images (V1 to Vn) in the physical library (P201 to P20n), step (69) by the management module (30) to create and update information representing validity of the volumes (V1 to Vn) present in the cartridges (P211 to P21n) of the physical libraries (P201 to P20n) allowing those virtual volumes (V′1 to V′n) of the cache (100) taken into account by module (32) of cache occupancy control, for calculation of the occupancy rate, to correspond to the virtual volumes (V′1 to V′n) of the cache (100) having <<disk only>> status, i.e. having images (V1 to Vn) present in the physical library (P201 to P20n) which are not all valid. 33. Method according to claim 31, characterized in that the compacting step (90) of the physical library (P200 to P20n) comprises a step (91), in which the management module (30) uses the results of the operations performed by the cache activity control module (31) cache occupancy control module (32) and activity control module (34) of the physical library (P201 to P20n), so that the compacting of the valid volumes (V1 to Vn) of the physical library (P201 to P20n) by the management module (30) is performed in relation to the activity and occupancy of the cache (100), by giving preference to accessing to the storage resources (20, 100) by the computer platforms (101 to 10n) over accessing needed for this compacting. 34. Method according to claim 18, characterized in that it comprises a step to install a software application in the operating system of the storage system (1), said software application forming all the modules (30, 31, 32, 33 and 34) of the storage system (1) and responsible for the interoperability of the different means of this system, said software application cooperating with an operating system installed on the storage system (1) to manage the operations to be performed by generating information on at least the locations and utilization of all the data present in the storage system (1), this installation step enabling the recording of the data needed to run this application in a memory accessible by the processing means (11) of the system (1). 35. The storage system according to claim 3, wherein the cache occupancy control module (32) calculates firstly an individual occupancy rate corresponding to calculation of the occupancy rate on each of the partitions (P1 to Pn) of the cache (100) individually, and secondly a mean occupancy rate corresponding to calculation of the occupancy rate of all the partitions (P1 to Pr) of the cache (100). 36. The storage system according to claim 35, characterized in that the mean occupancy rate of the cache (100) at a given time, calculated by the cache occupancy control module (32), corresponds for all the partitions (P1 to Pn) of the cache (100), to the sum of the size of the data present in the closed virtual volumes (V′1 to V′n) having <<disk only>> status and the size for all the partitions (P1 to Pn) allocated to the open virtual volumes (V′1 to V′n), irrespective of their status, this sum being compared, for all partitions (P1 to Pn), to the total size available in all the partitions (P1 to Pn) of the cache (100), to obtain the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100). 37. The storage system according to claim 35, characterized in that the individual occupancy rate of each partition (P1 to Pn) of the cache (100) at a given time, calculated by the cache occupancy control module (32), corresponds, for each of the partitions (P1 to Pn) of the cache (100) individually, to the size of the data present in the virtual volumes (V′1 to V′n) having <<disk only>> status, whether they are open or closed, this size being compared for each partition (P1 to Pn) with the total available size in the partition (P1 to Pn) under consideration, to obtain the individual occupancy rate of each partition (P1 to Pn). 38. The storage system according to claim 36, characterized in that the individual occupancy rate of each partition (P1 to Pn) of the cache (100) at a given time, calculated by the cache occupancy control module (32), corresponds, for each of the partitions (P1 to Pn) of the cache (100) individually, to the size of the data present in the virtual volumes (V′1 to V′n) having <<disk only>> status, whether they are open or closed, this size being compared for each partition (P1 to Pn) with the total available size in the partition (P1 to Pn) under consideration, to obtain the individual occupancy rate of each partition (P1 to Pn). 39. The storage system according to claim 2, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 40. The storage system according to claim 3, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 41. The storage system according to claim 4, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 42. The storage system according to claim 5, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 43. The storage system according to claim 35, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 44. The storage system according to claim 36, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 45. The storage system according to claim 37, characterized in that an activity index of the cache per determined periods of time is calculated by cache activity control module (31), said activity index correspondence to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes (V′1 to V′n) of the cache (100) that are simultaneously open during each determined period of time. 46. The storage system according to claim 35, characterized in that the management module (30) compares the activity index of the cache with a minimum activity threshold and a maximum activity threshold, compares the individual occupancy rate of the cache with a maximum occupancy threshold and compares the mean occupancy rate of the cache with a first priority threshold, below which occupancy of the cache (100) has priority over flushing, and a second flush start threshold, above which flushing of the cache (100) can be performed, to manage accesses to the cache (100) by the management algorithm (AG) for managing the access bandwidth to the cache, implemented in the storage system, and comprising at least one of the following rules: if the value of the individual occupancy rate of a partition (P1 to Pn) of the cache (100) is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache (100), the flush operation of the cache (100) is essential and is authorized to start to the possible detriment of accesses to the cache by the computer platforms (101 to 10n), part of the access bandwidth to the cache (100) then being used for the copying of one or more virtual volumes (V′1 to V′n) of this partition (P1 to Pn) into the physical library (P201 to P20n) during this flush operation, if the value of the activity index of the cache (100) is less or equal to the value of the minimum activity threshold, any flush operation of the cache (100) is authorized to start, to allow copying of one or more virtual volumes (V′1 to V′n) towards the physical library (P201 to P20n), if the value of the activity index of the cache (100) lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache (100) already in progress is authorized to continue, the copying of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n) being authorized during this flush operation in progress, but if no flush operation is in progress a new flush operation of the cache (100) is not authorized to start, if the value of the activity index of the cache (100) is higher than the value of the maximum activity threshold, a new flush operation of the cache (100) is not authorized to start and a flush operation of the cache (100) already in progress is interrupted, to the benefit of accessing to the cache (100) by the computer platforms (101 to 10n), unless the value of the individual occupancy rate of the cache (100) is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache (100) is higher than the flush start threshold, new copying of one or more virtual volumes (V′1 to V′n) from the cache (100) into the physical library (P201 to P20n), during a flush operation already in progress, then being forbidden, whilst copying already in progress of one or more virtual volumes (V′1 to V′n) from the cache (100) to the physical library (P201 to P20n), during this flush operation in progress, is authorized to be completed, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the value of the priority threshold, accesses to the storage resources (20, 100) in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system (1) have priority over the accesses needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100), this copying then possibly being deferred until release of these resources (20, 100), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the priority threshold, accesses to the storage resources (20, 100) in reply to requests transmitted by the access means (101) of the computer platforms (101 to 10n) to the storage system, do not have priority over the accesses needed to copy volumes requiring the same resources (20, 100) during a flush operation of the cache (100) which can therefore be started or continued to the possible detriment of accesses to the storage resources (20, 100) by the computer platforms (101 to 10n), if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is less or equal to the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is only authorized to start if the value of the activity index of the cache (100) is less or equal the value of the minimum activity threshold, if the value of the mean occupancy rate of all the partitions (P1 to Pn) of the cache (100) is higher than the value of the flush start threshold, a flush operation of the cache (100) towards the physical library (P201 to P20n) is essential and is authorized to start. 47. The storage system according to claim 46, characterized in that the cache activity control module (31) comprises means for consulting information generated by an organization module (33), to calculate the activity index of the cache (100) by counting the number of open virtual volumes, the maximum activity threshold corresponding to the total number of virtual volumes (V′1 to V′n) of the cache (100) open at the same time which consume a fraction of the bandwidth that is considered too high to allow an internal operation to start which requires access to the cache (100).			The present invention relates to the area of data processing, and in particular to the mass storage of data of different formats, generated by different heterogeneous computer platforms such as platforms of type GCOS8®, Unix®, Linux® or Windows® for example. These platforms run data-saving software applications e.g. GCOS8/TMS, Bull OpenSave, Veritas NetBackup or Legato Networker allowing generated data to be saved by sending it towards mass storage systems via a communication network such as a network of SAN type (<<Storage Area Network >>) or a network of Internet type for example. Mass storage systems all comprise communication means via at least one communication network, and data processing means firstly to manage exchanges with computer platforms and secondly to manage the storage of data derived from these platforms. Mass storage systems also comprise firstly memory means to store the data needed to run the software applications managing system operations, and secondly high capacity storage means to store mass data sent by the different platforms to which these systems are connected. In the prior art several types of mass storage systems are known, in which the high capacity storage means consist of physical libraries of magnetic storage media, called cartridges, handled by robots. These physical libraries comprise a plurality of cartridges in which data is written and read by means of at least one reader which individually accesses, via robotics, each of these cartridges when a request for writing or reading is transmitted by one of the computer platforms to the mass storage system. However, these known prior art solutions have the major disadvantages of being relatively slow, and of rapidly becoming saturated when numerous requests for access to the physical libraries are sent by the platforms. Mass storage systems are also known in the prior art which comprise large size memory means, called cache, forming a buffer between the computer platforms and the physical libraries. These large-size memory means consist, for example, of a plurality of hard disks in which the data sent or consulted by the platforms can be temporarily stored, to facilitate platform accessing to data while the system performs necessary operations within the physical library of physical cartridges. These mass storage systems known in the prior art therefore allow data to be stored temporarily in large-size memory means, to enable access thereto by platforms more rapidly than if they accessed the physical library. These mass storage systems therefore allow data consultation and updating to be managed at the request of the computer platforms from which this data originate. However, on account of the multitude and complexity of the maintenance tasks performed by these systems, when requests are transmitted by the computer platforms, the slowness and easy saturation of the processing capacities of these systems remain major drawbacks. The large-size memory means of these mass storage systems effectively have a certain bandwidth which limits the possible number of simultaneous accesses to data. In the prior art, in particular from patent application US 2005/055512 A1, mass storage systems are known which manage the flushing of various cache volumes in relation to pre-determined priorities and in relation to periods of inactivity corresponding to a low <<demand load >> when the need to flush the cache is low (since there is large free space in the cache). This type of solution has the disadvantage of only taking into account the occupancy of the cache, and does not allow fine-tuned management of the cache in relation to demands or the management of access to the cache by the computer platforms and the system itself. From the prior art, particularly from patent application U.S. Pat. No. 5,566,315 A, mass storage systems are known in which an allocation rate and a blocking rate are calculated to regulate flushing of the cache. This type of solution has the disadvantage of not anticipating blockage of the cache, since it consists of calculating the number of times when space allocations have failed because too much cache space is used. This type of solution thus does not allow fine-tuned management of the cache either, in relation to demand, nor does it allow management of the accesses to the cache by the computer platforms and the system itself. Finally, from the prior art, in particular from patent application U.S. Pat. No. 5,530,850 A, storage systems are known allowing the compacting of data stored and segmented on storage devices, subsequent to changes in entered data. This type of solution also has the disadvantage of not allowing fine-tuned management of the cache in relation to demand, nor the management of access to the cache by computer platforms and the system itself. Additionally, this type of solution does not allow the triggering of compacting in relation to the activity of the storage system. In this context, it would be of interest to optimise the management of the different tasks of writing, reading and ensuring the maintenance of the physical libraries which a mass storage system has under its control. The purpose of the present invention is to overcome some disadvantages of the prior art by proposing a storage system which is able to optimise the management of the different tasks of read, write and maintenance of physical libraries which are under its control, giving priority to data access by the computer platforms. This purpose is achieved with a storage system for data generated, in at least one format, by at least one computer platform and transmitted to the storage system via at least one communication network through access means of the platform to the storage system, the storage system comprising processing means and storage resources comprising firstly storage means containing at least one physical library including at least one robot capable of loading and unloading at least one data storage cartridge in and from at least one reader to allow the writing and reading of data transmitted by the computer platform in the physical library, and secondly memory means, called a cache, in which the processing means of the storage system emulate, vis-à-vis the computer platforms, at least one virtual library from at least one physical library which the storage system has under its control, the data thus stored in the physical library and the virtual library being grouped into groups of determined size, called virtual volumes, having at least one image in the physical library and/or one image in the virtual library, the access means of the platforms to the storage system thereby accessing for reading and writing, via the communication network, the image in the cache of each of the virtual volumes stored by the storage system, characterized in that the processing means of the storage system comprise a management module managing accesses to the storage resources both in the physical library and in the virtual library, in relation to requests transmitted by the access means of the computer platforms to the storage system, the management module being responsible for emulation of the virtual volumes of the physical library into virtual volumes of the virtual library of the cache and comprising firstly a module of cache activity control calculating at least one cache activity index per determined periods of time, reflecting utilization of the access bandwidth to the cache, and secondly a module of cache occupancy control calculating at least one cache occupancy rate at a given time, the management module triggering these calculations periodically or on an ad hoc basis whenever space is allocated for a new virtual volume in the cache and using the result of these calculations, with reference to at least one algorithm of management of the access bandwidth to the cache and implemented in the storage system, so as to regulate occupancy of the cache whilst managing priorities over time for access to the storage resources by the computer platforms to read/write virtual volumes of the cache or by the system itself for at least one operation, called flush of the cache, enabling the copying of data from at least one virtual volume of the virtual library towards at least one virtual volume of the physical library. According to another feature, the cache consists of a plurality of hard disks on which a plurality of partitions is distributed, the management module comprising an organization module keeping permanently up to date information on the distribution of the partitions installed on the hard disks and on the distribution of the data recorded on the different partitions, this organization module, on the basis of this information, generating at least one directory containing information on the locations and utilization of the virtual volumes of the cache, the virtual volumes on which reading or writing is in progress being identified as open virtual volumes, and the virtual volumes on which no reading or writing is in progress being identified as closed virtual volumes. According to another feature the management module comprises access means to the content of the storage resources of the system and verifies the content of the physical library and virtual library to assign to each of the virtual volumes a value, called a status, from among at least the following statuses: <<disk only>> status when the virtual volume has an image in the virtual library of the cache but does not have an image in the physical library or has at least one image in the physical library which is not valid i.e. does not contain the same data as the image in the virtual library; <<out of cache>> status when the virtual volume does not have any image in the virtual library of the cache; <<disk and tape>> status when the virtual volume has valid images both in the virtual library of the cache and in the physical library; <<swapping in>> status when the virtual volume has an image in the progress of being loaded in the virtual library, from an image in the physical library; <<swapping out>> status when the virtual volume has an image in the virtual library in the progress of being copied into an image of the physical library; <<incomplete>> status when the virtual volume of the virtual library is open and does not contain any data or contains incomplete data; <<moving out>> status when the virtual volume of the virtual library is in the progress of being copied from one partition of the cache to another; <<swappable>> status when the virtual volume has an image in the virtual library of the cache but has at least one image in the physical library which is not valid or the image in the virtual library is in progress of being copied into an image of the physical library, i.e. the volume either has (<disk only status or has <<swapping out>> status. According to another feature, the module of cache occupancy control calculates firstly a so-called individual occupancy rate corresponding to calculation of the occupancy rate on each of the partitions of the cache individually, and secondly a so-called mean occupancy rate corresponding to calculation of the occupancy rate of all the partitions of the cache. According to another feature, the mean occupancy rate of the cache at a given time, calculated by the module of cache occupancy control, corresponds for all the partitions of the cache, to the sum of the size of the data present in the closed virtual volumes having <<disk only>> status and the size for all the partitions allocated to the open virtual volumes, irrespective of their status, this sum being compared, for all partitions, to the total size available in all the partitions of the cache, to obtain the mean occupancy rate of all the partitions of the cache. According to another feature, the individual occupancy rate of each partition of the cache at a given time, calculated by the module of cache occupancy control, corresponds, for each of the partitions of the cache individually, to the size of the data present in the virtual volumes having <<disk only>> status, whether they are open or closed, this size being compared for each partition with the total available size in the partition under consideration, to obtain the individual occupancy rate of each partition. According to another feature, the activity index of the cache per determined periods of time, calculated by the module of cache activity control, corresponds to the mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes of the cache that are simultaneously open during each determined period of time. According to another feature, the management module compares the activity index of the cache with a minimum activity threshold and a maximum activity threshold, compares the individual occupancy rate of the cache with a maximum occupancy threshold and compares the mean occupancy rate of the cache with a first threshold, called a priority threshold, below which occupancy of the cache has priority over flushing, and a second threshold, called a flush start threshold, above which flushing of the cache can be performed, to manage accesses to the cache by means of the management algorithm for managing the access bandwidth to the cache, implemented in the storage system, and comprising at least one of the following rules: if the value of the individual occupancy rate of a partition of the cache is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache, the flush operation of the cache is essential and is authorized to start to the possible detriment of accesses to the cache by the computer platforms, part of the access bandwidth to the cache then being used for the copying of one or more virtual volumes of this partition into the physical library during this flush operation, if the value of the activity index of the cache is less or equal to the value of the minimum activity threshold, any flush operation of the cache is authorized to start, to allow copying of one or more virtual volumes towards the physical library, if the value of the activity index of the cache lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache already in progress is authorized to continue, the copying of one or more virtual volumes from the cache to the physical library being authorized during this flush operation in progress, but if no flush operation is in progress a new flush operation of the cache is not authorized to start, if the value of the activity index of the cache is higher than the value of the maximum activity threshold, a new flush operation of the cache is not authorized to start and a flush operation of the cache already in progress is interrupted, to the benefit of accessing to the cache by the computer platforms, unless the value of the individual occupancy rate of the cache is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache is higher than the flush start threshold, new copying of one or more virtual volumes from the cache into the physical library, during a flush operation already in progress, then being forbidden, whilst copying already in progress of one or more virtual volumes from the cache to the physical library, during this flush operation in progress, is authorized to be completed, if the value of the mean occupancy rate of all the partitions of the cache is less or equal to the value of the priority threshold, accesses to the storage resources in reply to requests transmitted by the access means of the computer platforms to the storage system have priority over the accesses needed to copy volumes requiring the same resources during a flush operation of the cache, this copying then possibly being deferred until release of these resources, if the value of the mean occupancy rate of all the partitions of the cache is higher than the priority threshold, accesses to the storage resources in reply to requests transmitted by the access means of the computer platforms to the storage system, do not have priority over the accesses needed to copy volumes requiring the same resources during a flush operation of the cache which can therefore be started or continued to the possible detriment of accesses to the storage resources by the computer platforms, if the value of the mean occupancy rate of all the partitions of the cache is less or equal to the value of the flush start threshold, a flush operation of the cache towards the physical library is only authorized to start if the value of the activity index of the cache is less or equal the value of the minimum activity threshold, if the value of the mean occupancy rate of all the partitions of the cache is higher than the value of the flush start threshold, a flush operation of the cache towards the physical library is essential and is authorized to start. According to another feature, the module of cache activity control comprises means for consulting information generated by the organization module, to calculate the activity index of the cache by counting the number of open virtual volumes, the maximum activity threshold corresponding to the total number of virtual volumes of the cache open at the same time which consume a fraction of the bandwidth that is considered too high to allow an internal operation to start which requires access to the cache. According to another feature, the module of cache occupancy control comprises means for consulting the information generated by the organization module, to calculate firstly the mean occupancy rate of the cache by comparing the sum of the total size of the data present in the open virtual volumes, irrespective of their status, and the total size of the data present in the closed virtual volumes having <<disk only>> status, with the total storage capacity in all the partitions of the cache, and secondly to calculate the individual occupancy rate of each of the partitions of the cache by comparing, for a given partition, the size of the data present in the virtual volumes having <<disk only>> status, whether they are open or closed, with the total storage capacity of this partition of the cache. According to another feature, the organization module cooperates with the module of cache activity control and the module of cache occupancy control to distribute the virtual volumes equitably over the different partitions of the cache, in order to promote homogeneous distribution over all the disks carrying the different partitions of the cache. According to another feature, the management module, during the flush operation of the cache, uses the results of the calculations made by the module of cache occupancy control to select those virtual volumes of the cache to be copied into the physical library, the virtual volumes thus selected being the closed virtual volumes having <<disk only>> status and which were the less recently accessed, for reading or writing, by the computer platforms, either in a given partition of the cache if the value of the individual occupancy rate of this partition is greater or equal to the value of the maximum occupancy threshold, or in all the partitions of the cache if the values of the individual occupancy rates of all the partitions are below the value of the maximum occupancy threshold. According to another feature, the management module comprises a module of activity control of the physical library, keeping permanently up to date at least information on the utilization of the readers and/or of the cartridges of the physical libraries under the control of the storage system, this information thereby enabling the management module to manage priorities over time for accesses to the storage resources, firstly by the system itself to flush at least one virtual volume of the cache towards at least one virtual volume of the physical library, and secondly by the computer platforms to read/write a virtual volume not present in the cache and therefore necessitating consultation of the physical library to copy a virtual volume of this physical library towards the cache, in the form of a virtual volume of the virtual library. According to another feature, the management module, through its access means to the content of the storage resources of the system, keeps permanently up to date at least information on the validity of the virtual volumes present in the cartridges of the physical libraries under the control of the storage system, with respect to the virtual volumes which may have been modified in the cache by the computer platforms, this information on validity enabling the management module to compare the space occupied by the obsolete virtual volumes in the cartridges of the physical library with a maximum invalidity threshold, and when this space of obsolete virtual volumes reaches this threshold, to perform compacting of the valid volumes of this physical library, in the cartridges containing virtual volumes in the physical library that are not utilized and/or corresponding to closed virtual volumes in the cache, by controlling the reading of all the valid volumes of the source cartridges containing obsolete volumes and simultaneously copying these valid volumes into target cartridges, so as to erase these source cartridges and obtain only cartridges containing valid volumes in the physical library and empty cartridges. According to another feature, the management module, responsible for emulation of the virtual volumes of the physical library into virtual volumes of the virtual library of the cache, offers the possibility that a virtual volume of the cache may have multiple images in the physical library, and that those virtual volumes of the cache taken into account by the module of cache occupancy control for the calculation of the occupancy rate, are volumes which correspond to the virtual volumes of the cache having <<disk only>> status, i.e. having images present in the physical library which are not all valid. According to another feature, the management module uses the results of the operations performed by the module of cache activity control, the module of cache occupancy control and module of activity control of the physical library, so that the compacting of the valid volumes of the physical library by the management module is conducted in relation to the activity and occupancy of the cache, giving preference to access to the storage resources by the computer platforms over accessing required for this compacting. According to another feature the processing means run a software application forming all the modules of the storage system and responsible for the interoperability of the different means of the system, this software application cooperating with an operating system installed on the storage system to manage the operations to be performed by generating information on at least the locations and utilization of all the data present in the storage system, the data needed for running this application being previously recorded in a memory accessible by the processing means of the system. A further purpose of the present invention is to propose a data-saving method allowing optimised management of the different write, read and library maintenance tasks under its control, by giving priority to data access by the computer platforms. This purpose is achieved with a method for saving/storing data generated, in at least one format, by at least one computer platform and transmitted to a storage system via a communication network through platform access means accessing the storage system, the storage system comprising storage resources comprising firstly storage means containing at least one physical library including at least one robot able to load and unload at least one data storage cartridge in and from at least one reader allowing the writing and reading of data transmitted by the computer platform in the physical library, and secondly comprising memory means, called a cache, in which the processing means of the storage system, vis-à-vis the computer platforms, emulate at least one virtual library from at least one physical library which the storage system has under its control, the data thus stored in the physical library and in the virtual library being grouped into groups of determined size, called virtual volumes, having at least image in the physical library and/or one image in the virtual library, the access means of the platforms to the storage system thereby accessing for reading and writing, via the communication network, the image in the cache of each of the virtual volumes stored by the storage system, the method being characterized in that it comprises at least the following steps: emulation of the virtual volumes of the physical library into virtual volumes of the virtual library of the cache, by a management module present in the processing means of the storage system and managing accesses to the storage resources both to virtual volumes de of the physical library and to virtual volumes of the cache, in relation to requests transmitted by the access means of the computer platforms to the storage system; calculation, by a module of cache activity control, of at least one activity index of the cache per determined periods of time, reflecting utilization of the access bandwidth to the cache, this calculation step being repeated to monitor changes in activity of the cache periodically or on an ad hoc basis whenever space is allocated for a new virtual volume in the cache; calculation, by a module of cache occupancy control, of at least one occupancy rate of the cache at a given time, this calculation step being repeated to monitor changes in occupancy of the cache periodically or an ad hoc basis whenever space is allocated for a new virtual volume in the cache; decision, by the management module, in relation to the results of these calculations and to at least one management algorithm for managing the access bandwidth to the cache, implemented in the storage system, between authorization or interdiction of access to the storage resources by the computer platforms to read/write virtual volumes in the cache, or by the system itself for at least one operation, called a cache flush, allowing the copying of data from at least one virtual volume of the virtual library to at least one virtual volume of the physical library, so as to regulate occupancy of the cache whilst managing priorities over time for accesses to the resources by the platforms and by the system itself. According to another feature, the method comprises firstly at least one installation step to install a plurality of partitions on a plurality of hard disks forming the cache, and secondly at least one step for the creation and updating, by an organization module, of data representing information on the distribution of partitions and on the distribution of data recorded in the different partitions, this organization module, on the basis of this information, generating at least one directory containing information on the locations and utilization of the virtual volumes, the virtual volumes on which reading or writing is in progress being identified as open virtual volumes, and the virtual volumes on which no reading or writing is in progress being identified as closed virtual volumes. According to another feature, the method comprises a verification step of the content of the physical library and of the virtual library by the management module, via access means to the content of the storage resources of the system, followed by an assignment step, to each of the virtual volumes, of a value called a status, from among at least the following statuses: <<disk only>> status when the virtual volume has an image in the virtual library of the cache but does not have an image in the physical library, or has at least one image in the physical library which is not valid, i.e. does not contain the same data as the image in the virtual library; <<out of cache>> status when the virtual volume does not have any image in the virtual library of the cache; <<disk and tape>> status when the virtual volume has valid images both in the virtual library of the cache and in the physical library; <<swapping in>> status when the virtual volume has an image in the progress of being loaded into the virtual library, from an image in the physical library; <<swapping out>> status when the virtual volume has an image in the virtual library in the progress of being copies into an image of the physical library; <<incomplete>> status when the virtual volume of the virtual library is open and does not contain any data, or contains incomplete data; <<moving out>> status when the virtual volume of the virtual library is in the progress of being copied from one partition of the cache to another; <<swappable>> status when the virtual volume has an image in the virtual library of the cache but has at least one image in the physical library which is not valid or the image in the virtual library is in the progress of being copied into an image of the physical library, i.e. the volume either has <<disk only>> status or <<swapping out>> status. According to another feature, the step to calculate the occupancy rate of the cache at a given time, by the module of cache occupancy control, comprises firstly a step to calculate a so-called individual occupancy rate, corresponding to calculation of the occupancy rate on each of the partitions of the cache individually, and secondly a step to calculate a so-called mean occupancy rate, corresponding to calculation of the occupancy rate of all the partitions of the cache. According to another feature, the step to calculate the mean occupancy rate of the cache, by the module of cache occupancy control, consists of measuring, for all the partitions of the cache, the sum of the size of the data present in the closed virtual volumes having <<disk only>> status and the size allocated to the open virtual volumes, irrespective of their status, this sum being compared with the total size available in all the partitions of the cache, to obtain the mean occupancy rate of all the partitions of the cache. According to another feature, step to calculate the individual occupancy rate of each partition of the cache, by the module of cache occupancy control, consists of measuring, for each of the partitions of the cache individually, the total size of the data present in the virtual volumes having <<disk only>> status, whether they are open or closed, this size being compared with the total available size in the partition under consideration of the cache, to obtain the mean occupancy rate of each of the partitions of the cache. According to another feature, step to calculate the activity index of the cache per determined periods of time, by the module of cache activity control, consists of calculating a mean, calculated over a determined number of successive determined time periods, of the maximum number of virtual volumes of the cache opened simultaneously during each determined time period. According to another feature, the method comprises at least one additional comparison step to compare the activity index of the cache with a minimum activity threshold and a maximum activity threshold, a comparison step of the individual occupancy rate of the cache with the maximum occupancy threshold and a comparison step of the mean occupancy rate with a first threshold called a priority threshold, below which occupancy of the cache has priority over flushing, and with a second threshold called a flush start threshold above which flushing of the cache can be performed, implemented by the management module to manage accesses to the cache by means of the management algorithm for managing the access bandwidth to the cache, implemented in the storage system, and comprising at least one of the following rules: if the value of the individual occupancy rate of a partition of the cache is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache, the flush operation of the cache is essential and is authorized to start to the possible detriment of accesses to the cache by the computer platforms, part of the access bandwidth to the cache then being used to copy one or more virtual volumes from this partition towards the physical library during this flush operation, if the value of the activity index of the cache is less or equal to the minimum activity threshold, any flush operation of the cache is authorized to start, to allow the copying of one or more virtual volumes towards the physical library, if the value of the activity index of the cache lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache already in progress is authorized to continue, the copying of one or more virtual volumes from the cache to the physical library being authorized during this flush operation in progress, but if no flush operation is in progress a new flush operation of the cache is not authorized to start, if the value of the activity index of the cache is higher than the value of the maximum activity threshold, a new flush operation of the cache is not authorized to start and a flush operation of the cache already in progress is interrupted, to the benefit of accessing to the cache by the computer platforms, unless the value of the individual occupancy rate of the cache is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache is higher than the flush start threshold, new copying of one or more virtual volumes from the cache to the physical library, during a flush operation already in progress, then being forbidden, whilst copying already in progress of one or more virtual volumes from the cache to the physical library, during this flush operation in progress, is authorized to be completed, if the value of the mean occupancy rate of all the partitions of the cache is less or equal to the priority threshold, accesses to the storage resources, in reply to requests transmitted by the access means of the computer platforms to the storage system, have priority over accessing needed to copy volumes requiring the same resources during a flush operation of the cache, this copying then possibly being deferred until release of these resources, if the value of the mean occupancy rate of all the partitions of the cache is higher than the priority threshold, accesses to the storage resources in reply to requests transmitted by the access means of the computer platforms to the storage system do not have priority over accesses needed to copy volumes requiring the same resources during a flush operation of the cache, which can therefore start or continue to the possible detriment of accessing to the storage resources by the computer platforms, if the value of the mean occupancy rate of all the partitions of the cache is less or equal to the value of the flush start threshold, a flush operation of the cache towards the physical library is only authorized to start if the value of the activity index of the cache is less or equal to the value of the minimum activity threshold, if the value of the mean occupancy rate of all the partitions of the cache is higher than the value of the flush start threshold, a flush operation of the cache towards the physical library is essential and is authorized to start. According to another feature, the step to calculate the activity index of the cache, by the module of cache activity control, comprises at least one consultation step of the data generated by the organization module, to calculate the activity index of the cache by counting the number of open virtual volumes in the cache, the maximum activity threshold corresponding to the total number of virtual volumes of the cache open at the same time which consume a fraction of the access bandwidth considered too high to allow the start of an internal operation requiring access to the cache. According to another feature, the step to calculate the occupancy rate of the cache, by the module of cache occupancy control, comprises at least one consultation step of the data generated by the organization module to calculate firstly the mean occupancy rate of the cache by comparison of the sum of the total size of the data present in the open virtual volumes, irrespective of their status, and the total size of the data present in the closed virtual volumes having <<disk only>> status, with the total storage capacity of all the partitions of the cache, and secondly the individual occupancy rate of each of the partitions of the cache by comparison, for a given partition, of the size of the data present in the virtual volumes having <<disk only>> status, whether they are open or closed, with the total storage capacity of this partition of the cache. According to another feature, the emulation step of the virtual volumes by the management module comprises a cooperation step of the organization module with the module of cache activity control and the module of cache occupancy control to distribute the virtual volumes equitably over the different partitions of the cache, in order to promote homogeneous distribution over all the disks carrying the different partitions of the cache. According to another feature, the flush operation of the cache, results from the use, by the management module, of the results of the calculations made by the module of cache occupancy control, to select the virtual volumes of the cache to be copied into the physical library, the virtual volumes thus selected being closed virtual volumes having <<disk only>> status and which were the less recently accessed for reading or writing by the computer platforms, either in a given partition of the cache if the value of the individual occupancy rate of this partition is greater or equal to the value of the maximum occupancy threshold, or in all the partitions of the cache if the values of the individual occupancy rates of all the partitions are lower than the value of the maximum occupancy threshold. According to another feature, the method comprises at least one step for the creation and update, by a module of activity control of the physical library, of data representing information on utilization of the readers and/or of the cartridges of the libraries under the control of the storage system, this information thereby enabling the management module to manage priorities over time for accesses to the storage resources, firstly by the system itself to flush at least one virtual volume from the cache towards a volume of the physical library, and secondly by the computer platforms to read/write a virtual volume not present in the cache and therefore necessitating consultation of the physical library to copy a volume from this physical library to the cache, in the form of a virtual volume of the virtual library. According to another feature, the method comprises at least one step for the creation and update, by the management module, of data representing information on the validity of the volumes present in the cartridges of the physical libraries under the control of the storage system, with respect to the virtual volumes which may have been modified in the cache by the computer platforms, this information on validity enabling the management module to implement a comparison step of the space occupied by obsolete virtual volumes in the cartridges of the physical library with a maximum invalidity threshold and, if this space occupied by these obsolete virtual volumes reaches this threshold, to implement a compacting step of the valid volumes, taken from cartridges containing volumes that are non-utilized and/or correspond to closed virtual volumes, by controlling the reading of all the valid volumes of the source cartridges containing obsolete volumes and simultaneously copying these valid volumes into target cartridges, so as to erase these source cartridges and only obtain cartridges containing valid volumes in the physical library. According to another feature, the emulation steps of the virtual volumes of the physical library into virtual volumes of the virtual library of the cache and the management steps of the cache by the management module, offer the possibility that a virtual volume of the cache may have multiple images in the physical library, step by the management module to create and update information representing validity of the volumes present in the cartridges of the physical libraries allowing those virtual volumes of the cache taken into account by module of cache occupancy control, for calculation of the occupancy rate, to correspond to the virtual volumes of the cache having <<disk only>> status, i.e. having images present in the physical library which are not all valid. According to another feature, the compacting step of the physical library comprises a step, in which the management module uses the results of the operations performed by module of cache activity control, module of cache occupancy control and module of activity control of the physical library, so that the compacting of the valid volumes of the physical library by the management module is performed in relation to the activity and occupancy of the cache, by giving preference to accessing to the storage resources by the computer platforms over accessing needed for this compacting. According to another feature, the method comprises a step to install a software application in the operating system of the storage system, this software application forming all the modules of the storage system and responsible for the interoperability of the different means of this system, this software application cooperating with an operating system installed on the storage system to manage the operations to be performed by generating information on at least the locations and utilization of all the data present in the storage system, this installation step enabling the recording of the data needed to run this application in a memory accessible by the processing means of the system. Other particular aspects and advantages of the present invention will become more clearly apparent from the description given below with reference to the appended drawings in which: FIG. 1 shows the storage system according to one embodiment of the invention, FIG. 2 illustrates the main steps of the method according to one embodiment of the invention, FIG. 3 shows the details of the emulation step such as implemented in the system, according to one embodiment of the invention, FIG. 4 shows the detailed steps of the method according to one embodiment of the invention, The present invention concerns a storage method and storage system 1 for data generated by at least one computer platform 101 to 10n. As mentioned previously, the invention allows the saving of data derived from various types of computer platforms, for example such as GCOS8®, Unix®, Linux® or Windows®. These platforms run data-saving software applications, such as GCOS8/TMS, Bull OpenSave, Veritas NetBackup or Legato Networker for example, enabling generated data to be saved by sending it towards mass storage systems via a communication network, such as the Internet network for example. Data items are generated by these different platforms in at least one data processing format and are transmitted to the storage system 1 via at least one communication network RC through access means 101 of the platform to the storage system 1. In particular, these access means 101 to the storage system 1 may consist of one of the above-cited data-saving software applications, combined with communication means via at least one communication network, or of any type of access means enabling the platform to perform data consultations or data changes or any known operation in this area. As is known per se, the storage system 1 comprises data processing means 11 and storage resources 20, 100. These storage resources 20, 100 comprise firstly storage means 20 containing at least one physical library P201 to P20n including at least one robot P22 capable of loading and unloading at least one data storing cartridge P211 to P21n in and from at least one reader P2001 to P200n, and secondly comprise memory means 100, called cache 100, which include at least one virtual library V201 to V20n which temporarily stores data corresponding to data of at least one cartridge V1 to Vn of a physical library P201 to P20n which the storage system has under its control. The processing means 11 of the storage system 1 according to the invention, vis-à-vis computer-platforms 101 to 10n, emulate at least one virtual library V201 to V20n from at least one physical library P201 to P20n. In storage systems known in the prior art, when the access means 101 to the storage system 1 of one of the computer platforms 101 to 10n managed by the storage system 1, requires data reading or writing, the robot 20 allows loading of the cartridge P211 to P21n corresponding to the required data into one of the readers P2001 to P200n of the physical library P201 to P20n to permit writing and reading of the data. On the other hand, in storage systems emulating a virtual library V201 to V20n from the physical library P201 to P20n, as is the case in the present invention, the computer platforms 101 to ion in fact access the virtual library V201 to V20n of the cache 100 instead of directly accessing the physical library P201 to P20n. Emulation therefore allows the storage system 1 to act vis-à-vis computer platforms 101 to 10n as if it effectively offers direct access to the physical library P201 to P20n, but by offering quicker access to the virtual library V201 to V20n. The computer platforms 101 to 10n therefore do not need to be modified and the storage system 1 takes in charge the converting of received requests in order to provide the data requested by the computer platforms 101 to 10n, as if it derived from a physical library P201 to P20n. Emulation may have different levels of details, going for example as far as emulating the physical library down to the last reader, but emulation allows the storage system 1 to have its own organization and it is not necessary that the organization of the libraries emulated in the cache correspond exactly to the organization of the physical libraries which the system has under its control. Therefore, when the storage system receives a request from a computer platform to mount a cartridge in a reader, it will interpret the received request and may for example simulate mounting of a cartridge in a reader to allow reading/writing of this cartridge by the computer platform, until this platform transmits a cartridge dismount request to the system. In manner known per se, the data stored in the physical library P201 to P20n is grouped into groups of determined size, called virtual volumes V1 to Vn. These virtual volumes V1 to Vn of the physical library P201 to P20n can be accessed by processing means 11 of the storage system 1. Similarly, the virtual library V201 to V20n in the cache 100 of the storage system 1, temporarily and in the form of at least one group called a virtual volume V′1 to V′n of the cache 100, stores data corresponding to the content of at least one virtual volume V1 to Vn of the library P201 to P20n. Therefore, the data items of each of the virtual volumes have at least one image V1 to Vn in the physical library P201 to P20n and/or one image V′1 to V′n in the virtual library V201 to V20n, the access means 101 of the platforms 101 to 10Hhd n to the storage system 1, via the communication network RC, thereby read/write accessing the image V′1 to V′n in the cache 100 of each of the virtual volumes stored by the storage system. The different components and resources of the storage system 1 such as, inter alia, the cache 100, the processing means 11 and the physical library P201 to P20n may, in manner known per se, be connected together by high data rate connections such as, for example, the optical fibres used according to the <<Fiber Channel>> protocol. In a manner more specific to the present invention, the processing means 11 of the storage system 1 comprise a management module 30 responsible for emulating volumes V1 to Vn of the library into virtual volumes V′1 to V′n of the cache. This management module (30) manages accessing, for reading and writing, to all the storage resources 20, 100, both to virtual volumes V1 to Vn of the physical library P201 to P20n, and to virtual volumes V′1 to V′n of the virtual library V201 V20n of the cache 100. At the time of requests transmitted by the access means 101 of the computer platforms 101 to 10n to the storage system, the management module 30 will authorize or forbid access to data in relation to demand and to the different parameters defined in an algorithm AG of management of the cache access bandwidth, implemented in the system 1. This management algorithm AG may for example be stored in a memory accessible by the processing means 11 of the system, and allows management of priorities over time for accesses to storage resources 20, 100 by the computer platforms 101 to 10n to read/write virtual volumes V′1 to V′n of the cache 100, or by the system 1 itself for at least one internal operation, called a cache flush, allowing the copying of data from at least one virtual volume V′1 to V′n of the virtual library V201 to V20n towards at least one virtual volume V1 to Vn of the physical library P200 to P20n. The cache flush operation is called <<internal>> in opposition to accessing to the cache 100 required by the computer platforms which a priori are external to the storage system. This operation in fact corresponds to a cache management operation decided by the system itself, internally, in accordance with management algorithms of the cache 100. Similarly, the compacting of valid volumes V1 to Vn of the physical library P201 to P20n, described further on, corresponds to an internal operation requiring access to the cache 100. The term <<internal operation>> will therefore be used herein for any operation internally decided by the system itself to manage its storage resources. During the flush operation of the cache 100, a certain number of virtual volumes V′1 to V′n of the virtual library V201 to V20n, eligible for flushing, are chosen so that they can be recopied into the physical library P201 to P20n. The flush operation will start, in relation to available resources 20, 100, with at least one of these eligible virtual volumes V′1 to V′n, then when use of the resources 20, 100 so allows, it will choose other virtual volumes V′1 to V′n for their recopying into the physical library P201 to P20n. A flush operation of the cache 100 may therefore concern a plurality of virtual volumes V′1 to V′n to be <<flushed>> (copied to the physical library) simultaneously or successively during a given flush operation, depending on the availability of resources. The start of a flush operation is determined by the activity of the system, and by cache occupancy, and the copies made during these flush operations are also controlled in relation to activity and occupancy as is explained in detail below. It is therefore possible to manage priorities over time for access to the storage resources 20, 100 by the computer platforms 101 to 10n to read/write virtual volumes V′1 to V′n of the cache 100, or by the system 1 itself for at least one internal operation. Additionally, according to some embodiments, the invention comprises at least one calculation of at least one cache activity index per determined periods of time, reflecting utilization of the access bandwidth to the cache 100. In this way, the use of the cache access bandwidth (generally, use of the resources) determines accessing to the cache 100 by the computer platforms 101 to 10n or by the system 1 itself. According to some embodiments, the invention comprises at least one calculation of at least one cache occupancy rate making it possible, for example, to determine whether data can be written in the cache or if the cache must be flushed, etc. Therefore, in various embodiments, the invention allows the regulated use of the cache access bandwidth, so as to avoid any blockage or delay arising from too extensive utilization of the resources of the system 1. Also, the invention allows the occupancy of the cache 100 to be regulated, whilst managing priorities over time for accessing the resources 20,100 of the storage system 1, as is detailed below. In some embodiments of the invention, the different means herein described can be carried by a software application run by the processing means 11 of the storage system 1. Therefore, this software application will form all the modules 30, 31, 32, 33 and 34 described herein and will be responsible for the interoperability of the different means of the storage system 1 according to the invention. This software application will cooperate with the operating system installed on the storage system 1 to manage the operations to be performed. According to the invention, the operating system of the storage system 1 may consist of any operating system which, in manner known per se, generates data representing information on at least the locations and utilization of all the data present in the storage system 1. Therefore the information generated by this operating system is used by the processing means 11 of the storage system according to the invention. For example, the operating system of the storage system 1 may consist of a system of AIX type. In this case, the data generated by this AIX system, representing information on at least the locations and utilization of all the data of this system, corresponds to a journaling system of JFS type (<<Journalized File System>>), particularly suitable for implementing the invention, although the invention can be implemented in other types of operating systems generating other types of file systems. The data required for running this application is evidently previously recorded in a memory accessible by the processing means 11 of the system 1, e.g. the memory in which the management algorithm AG is stored. In some embodiments of the invention, the cache 100 consists of a plurality of hard disks 1001 to 100n on which a plurality of partitions P1 to Pn is distributed. For example, the partitions P1 to Pn installed on these hard disks can be organized according to an array of RAID 5 type (<<Redundant Array of Inexpensive Disks>>), type 5 also being called <<Disk Array with Block-interleaved Distributed Parity>>) so as to allow repair in the event of any damage. In some embodiments of the invention, the management module 30 comprises an organization module 33 permanently updating information relating to the distribution of the partitions P1 to Pn installed on the hard disks and to the distribution of data recorded in the different partitions P1 to Pn. By means of the journaling file system JFS of the operating system, the organization module 33, on the basis of this information on distribution of the partitions P1 to Pn and data distribution, generates at least one directory (RP) containing information on the locations and utilization of the virtual volumes V′1 to V′n of the cache 100. The virtual volumes V′1 to V′n of the cache 100 on which read or write operations are in progress are identified as <<open virtual volumes>> and the virtual volumes on which no reading or writing is in progress are identified as <<closed virtual volumes>>. By means of the journalized file system JFS of the operating system, this organization module 33 integrates the information indicating which virtual volumes V′1 to V′n are open and which are closed, and therefore allows equitable distribution of data over the different partitions P1 to Pn of the cache 100. This equitable distribution of data over the different hard disks of the cache promotes homogeneous distribution of the volumes over the disks carrying the partitions, and therefore avoids heavy concentration of accesses to the disks carrying the different partitions P1 to Pn of the cache 100. Indeed, the hard disks 1001 to 100n of the cache 100 have a limited bandwidth which means that only a limited number of simultaneous accesses are allowed to the different partitions P1 to Pn. If several operations require access to one same disk, some operations will have to be placed on standby while the other operations are completed. Equitable distribution of data over the disks can minimize this placing on standby for access to the partitions P1 to Pn. In some embodiments of the invention, the management module 30 comprises access means to the content of the resources 20, 100 of the storage system 1. On accessing the storage resources (20, 100), the management module 30 can therefore verify the content of the physical library P201 to P20n and of the virtual library V201 to V20n so as to assign to each of the virtual volumes a value called a status. This status allows the management module 30 to manage the state of the virtual volumes V′1 to V′n and V1 to Vn, of the cache 100 and of the physical library P201 to P20n respectively. The management module 30 therefore assigns a status to each of the virtual volumes in relation to the content of the two libraries, from among at least the following statuses: <<disk only>> status when the virtual volume has an image V′1 to V′n in the virtual library V201 to V20n of the cache 100, but has no image in the physical library or has at least one image V1 to Vn in the physical library P200 to P20n which is not valid i.e. does not contain the same data as the image V′1 to V′n in the virtual library V201 to V20n; <<out of cache>> status when the virtual volume has no image V′1 to V′n in the virtual library V201 to V20n of the cache 100; <<disk and tape>> status when the virtual volume has valid images both in the virtual library V201 to V20n of the cache 100 and in the physical library P201 to P20n; <<swapping in>> status when the virtual volume has an image V′1 to V′n in the progress of being loaded (currently being loaded) into the virtual library V201 to V20n, from an image V1 to Vn in the physical library P201 to P20n; <<swapping out>> status when the virtual volume has an image V′1 to V′n in the virtual library V201 to V20n in the progress of being copied (currently being copied) in an image V1 to Vn of the physical library P201 to P20n; <<incomplete>> status when the virtual volume V′1 to V′n of the virtual library V201 to V20n is open and does not contain data or contains incomplete data; <<moving out>> status when the virtual volume V′1 to V′n of the virtual library V201 to V20n is in the progress of being copied from one partition P1 to Pn of the cache 100 to another; <<swappable>> status when the virtual volume has an image V′1 to V′n in the virtual library V201 to V20n of the cache 100, but has at least one image V1 to Vn in the physical library P201 to P20n which is not valid, or the image V′1 to V′n in the virtual library V201 to V20n is in the progress of being copied into an image V1 to Vn of the physical library P201 to P20n, i.e. the volume either has <<disk only>> or <<swapping out>> status. In some embodiments of the invention, the management module 30 comprises a module 31 of cache activity control which calculates at least one cache activity index per determined periods of time. This cache activity index per determined time periods may, for example, correspond to the mean number of virtual volumes V′1 to V′n opened in the cache 100, i.e. the virtual volumes V′1 to V′n of the cache 100 on which reading or writing is in progress during a determined period of time. More precisely, the activity index may be calculated over a sliding time period i.e. by repeating the calculation of the index over several successive determined time periods and by calculating the mean of the activity indexes obtained on each of these successive time periods. Therefore, the mean calculated for several successive non-periodic activity indexes enables the calculation of the activity index to perform better by eliminating any sudden, brief variations in activity. The activity index obtained subsequent to this mean calculation is therefore smoothed (low pass filter) and truly represents the activity of the cache 100. The activity index of the cache per determined periods of time may therefore correspond to the mean, calculated over a determined number of successive determined time periods, of the mean number of virtual volumes V′1 to V′n of the cache 100 simultaneously opened during each determined time period. The management module 30 can therefore monitor the activity of the cache 100 by triggering this calculation periodically or at different points in time when space is allocated for a new virtual volume V′1 to V′n in the cache 100. In some embodiments of the invention, the management module 30 also comprises a module 32 of cache occupancy control which calculates at least one cache occupancy rate at a given time. More precisely, this given time may be determined in relation to the operations performed by the storage system 1. For example, this calculation of occupancy rate may take place whenever a system operation translates as (results in) a closure of a virtual volume V′1 to V′n of the cache 100 and/or by the end of a flush operation of the cache 100, and/or during a flush operation, when copying of a virtual volume V′1 to V′n of the cache 100 is completed and/or there is new allocation of storage space in the cache 100 to define a virtual volume V′1 to V′n of the cache. It will be noted in passing that the opening of a virtual volume V′1 to V′n of the cache 100 results in the defining of the maximum space reserved for virtual volumes V′1 to V′n in the cache 100, so that the platform which requested opening of a virtual volume V′1 to V′n is able to record data therein having the size of a whole virtual volume V′1 to V′n, and on the closing of this virtual volume V′1 to V′n of the cache 100, if this virtual volume is not complete i.e. it does not contain as much data as is possible, the storage system 1 allocates only the necessary size to this virtual volume V′1 to V′n instead of maintaining for it the maximum size possible for virtual volumes V′1 to V′n. The management module 30 is therefore able to monitor occupancy of the cache 100 by triggering this calculation periodically or on an ad hoc basis whenever space is allocated for a new virtual volume V′1 to V′n in the cache 100, the closing of a volume not necessarily requiring an estimation of occupancy of the cache 100. In some embodiments of the invention, the module 32 of cache occupancy control calculates two different occupancy rates. It calculates firstly a so-called individual occupancy rate, corresponding to calculation of the occupancy rate on each of the partitions P1 to Pn of the cache 100 individually, and secondly a so-called mean occupancy rate corresponding to calculation of the occupancy rate of all the partitions P1 to Pn of the cache 100. In the embodiments in which the management module 30 assigns a status to the virtual volumes, the mean occupancy rate of the cache 100 may, for all the partitions P1 to Pn of the cache 100, correspond to the sum of the size of the data present in the closed virtual volumes V′1 to V′n having <<disk only>> status and the size allocated to the open virtual volumes V′1 to V′n, irrespective of their status, this sum being compared with the total size available in all the partitions P1 to Pn of the cache 100, to obtain the mean occupancy rate of all the partitions P1 to Pn of the cache 100. Similarly, the individual occupancy rate of each partition P1 to Pn of the cache 100 at a given time may, for each of the partitions P1 to Pn of the cache 100 individually, correspond to the size of the data present in the virtual volumes V′1 to V′n having <<disk only>> status, whether they are open or closed, this size being compared, for each partition P1 to Pn, with the total available size in the partition P1 to Pn under consideration, to obtain the individual occupancy rate of each partition P1 to Pn. In the embodiments in which the management module 30 does not assign a status to the virtual volumes, the cache occupancy rates may correspond either to the total size of the data present only in the closed virtual volumes V′1 to V′n in the cache 100, or to the total size of the data present both in the closed virtual volumes V′1 to V′n and in the open virtual volumes V′1 to V′n. In relation to the algorithm AG of management of the cache access bandwidth, the management module 30 uses the results of the calculations performed by the modules 31 and 32 controlling cache activity and cache occupancy respectively, so as to manage accessing to the storage resources 20, 100 of the system 1. Access to the cache 100 may evidently be requested by the computer platforms 101 to 10n to read/write virtual volumes V′1 to V′n, but also by the system 1 itself for a flush operation of all or part of the cache 100 towards the physical library P201 to P20n. In this way the algorithm AG managing the bandwidth for access to the cache 100 is able to give priority over time to the different accesses to the storage resources 20, 100 required for the different operations which can be performed by the system 1 according to the invention. More precisely, the management module 30 compares the activity index of the cache with a minimum activity threshold and a maximum activity threshold, compares the individual occupancy rate of the different partitions P′1 to P′n of the cache 100 with a maximum occupancy threshold, and compares the mean occupancy rate of the cache 100 with a first threshold, called a priority threshold, below which occupancy of the cache 100 has priority over flushing, and a second threshold, called a flush start threshold, above which flushing of the cache 100 can be performed. This comparison enables the management module 30 to manage accesses to the caches 100 by means of the algorithm AG managing the bandwidth for cache access. In some embodiments of the invention, the management algorithm AG preferably comprises all the rules described below, but more generally at least one of these rules. The invention also makes provision for the possible modification of these different rules through parameterisation of the management algorithm AG. One first rule provides that if the value of the individual occupancy rate of a partition P1 to Pn of the cache 100 is higher than the value of the maximum occupancy threshold, irrespective of the value of the activity index of the cache 100, the flush operation of the cache 100 is essential and is authorized to start, to the possible detriment of cache accessing by the computer platforms 101 to 10n, part of the access bandwidth to the cache 100 then being used for copying one or more virtual volumes V′1 to V′n from this partition P1 to Pn into the physical library P201 to P20n during this flush operation. Another rule provides that if the value of the activity index of the cache 100 is less or equal to the value of the minimum activity threshold, any flush operation of the cache 100 is authorized to start for the copying of one or more virtual volumes V′1 to V′n into the physical library P201 to P20n. Another rule provides that if the value of the activity index of the cache 100 lies between the value of the minimum activity threshold and the value of the maximum activity threshold, a flush operation of the cache 100 already in progress is authorized to continue, the copying of one or more virtual volumes V′1 to V′n from the cache 100 to the physical library P201 to P20n being authorized during this flush operation is progress, but if no flush operation is in progress a new flush operation of the cache 100 is not authorized to start. Therefore, a new flush operation of the cache 100 will not be authorized to start, only flush operations already in progress being authorized to continue, and the copying of virtual volumes of the cache 100 chosen to be eligible for flushing during this operation will be authorized. Also, these conditions set by the activity indexes may be lifted (cleared, broken) by conditions fixed by the individual and mean occupancy rates, i.e. a new flush operation will be authorized to start if the individual occupancy rate exceeds the maximum occupancy threshold or if the mean occupancy rate exceeds the flush start threshold. Another rule provides that if the value of the activity index of the cache 100 is higher than the value of the maximum activity threshold, a new flush operation of the cache 100 is not authorized to start, and a flush operation of the cache 100 already in progress is interrupted to the benefit of cache accessing by the computer platforms 101 to 10n, unless the value of the individual occupancy rate of the cache 100 is higher than the value of the maximum occupancy threshold or unless the value of the mean occupancy rate of the cache 100 is higher than the flush start threshold, any new copying of one or more virtual volumes V′1 to V′n of the cache 100 into the physical library P20 P20n, during a flush operation already in progress, being forbidden, whilst the copying already in progress of one or more virtual volumes V′1 to V′n of the cache 100 into the physical library P201 to P20n, during this flush operation in progress, is authorized to be completed. Therefore, as previously, these conditions set by the activity indexes can be lifted by the conditions fixed by the individual and mean occupancy rates, i.e. if the value of the individual occupancy rate or mean occupancy rate of the cache 100 is higher than the value of the maximum occupancy threshold or the flush start threshold respectively, a new flush operation of the cache 100 may take place. Another rule provides that if the value of the mean occupancy rate of all the partitions P1 to Pn of the cache 100 is less or equal to the value of the priority threshold, access to the storage resources 20,100 in reply to requests transmitted by the access means 101 of the computer platforms 101 to 10n to access the storage system 1 have priority over accesses needed to copy volumes (1) requiring the same resources 20, 100 during a flush operation of the cache 100, this copying possibly being deferred until release of these resources 20, 100. Another rule provides that if the value of the mean occupancy rate of all the partitions P1 to Pn of the cache 100 is higher than the priority threshold, accesses to the storage resources 20, 100 in reply to requests transmitted by the access means 101 of the computer platforms 101 to 10n, to access the storage system 1, do not have priority over accesses needed for copying which require the same resources 20, 100 during a flush operation of the cache 100, this flush operation can therefore start or continue to the possible detriment of accessing to the storage resources 20, 100 by the computer platforms 101 to 10n. Another rule provides that if the value of the mean occupancy rate of all the partitions P1 to Pn of the cache 100 is less or equal to the value of the flush start threshold, a flush operation of the cache 100 towards the physical library P201 to P20n is only authorized to start if the value of the activity index of the cache 100 is less or equal to the minimum activity threshold. Another rule provides that if the value of the mean occupancy rate of all the partitions P1 to Pn of the cache 100 is higher than the value of the flush start threshold, a flush operation of the cache 100 towards the physical library P201 to P20n is essential and is authorized to start. In addition, the algorithm may, in one variant of embodiment, have been previously parameterised so that the maximum occupancy threshold and the flush start threshold have the same value and are in fact one same threshold which determines flush start. The calculations of the individual and mean occupancy rates therefore provide precise control over the operations performed by the system 1 in relation to the utilization of the different partitions of the cache 100. The system therefore provides flexibility of use enabling an operator to fix different values for the thresholds and to control the different operations performed in relation to the parameters chosen by the operator in the management algorithm. These different rules and the parameterisation of the algorithm and thresholds allow flexible use of the system, and an operator in charge of parameterisation may for example choose to fix the priority threshold at a zero value so that occupancy never has priority over flushing. Similarly, the parameterisation of the thresholds allows a priority threshold for example to be fixed at higher value than the value of the flush start threshold, so that when the mean occupancy rate exceeds the flush start threshold of the cache a flush operation is authorized to start, but occupancy of the cache continues to have priority over flushing. Conversely, the priority threshold may be fixed at a lower value than the flush start threshold, so that when the mean occupancy rate exceeds the priority threshold, a cache flush operation has priority over occupancy, and if the flush start threshold is reached the flush operation becomes essential and will be triggered immediately having priority over occupancy. The invention therefore permits numerous different operating functions but essentially, and in general insofar as is possible, gives preference to access to the resources by the computer platforms. Finally, the algorithm is preferably parameterised such as explained above, so that if the activity index is less or equal to the minimum activity threshold, a cache flush operation can be started irrespective of the values of the occupancy rates, if there are closed virtual volumes having <<disk only>> status, eligible for flushing from the cache 100. However, parameterisation may be different and require a given occupancy rate to allow the start of a flush operation. In addition, it will be noted here that the rules fixed in relation to the values of indexes and rates were fixed under a relationship of type <<less or equal to>> and higher than>>, but evidently the relationship may be of the type <<lower than>> and <<greater or equal to>> or any combination of these relationships, without departing from the spirit of the invention. In some embodiments of the invention, the organization module 33 cooperates with the module 31 of cache activity control and the module 32 of cache occupancy control, in order to distribute data equitably over the different partitions P1 to Pn of the cache 100, so as to promote homogeneous distribution of the virtual volumes over all the disks carrying the different partitions P1 to Pn of the cache 100. Therefore, by means of this cooperation, the management module 30 allows the equitable distribution of data over the different partitions P1 to Pn of the cache 100 to be performed solely when the activity and occupancy of the cache 100 so permit. The module 31 of cache activity control comprises means for consulting the information generated by the organization module 33. By consulting the information generated by the organization module 33, the module 31 of cache activity control can therefore calculate the activity index of the cache 100 by counting the number of open virtual volumes V′1 to V′n in the cache 100. The minimum activity threshold corresponds to an activity value for which it is considered that the resources 20, 100 of the system 1 are under-exploited, or exploited at a sufficiently low level to allow flush operations of the cache 100 to be performed. The system 1 can then internally, i.e. by itself, without action by the computer platforms, launch flush operations of the cache 100. These flush operations of the cache 100 consist of a group of copying operations of virtual volumes V′1 to V′n having <<disk-only>> status, in parallel with accessing by the computer platforms which, if the activity index falls to below the minimum activity threshold, are sufficiently few in number to allow at least one flush operation to be performed without running the risk of limiting access to the cache by the computer platforms. As for the maximum activity threshold, this corresponds to the total number of virtual volumes V′1 to V′n of the cache which, when they opened at the same time, consume a fraction of the bandwidth that is considered too high to allow the start of an internal operation requiring access to the cache. The value of this threshold is therefore previously chosen to avoid creating any conflicting of access to the different partitions P1 to Pn of the cache 100. Similarly, the module 32 of cache occupancy control, controlled by the management module 30, comprises means for consulting the information generated by the organization module 33 to calculate firstly the mean occupancy rate of the cache 100 and secondly the individual occupancy rate of each of the partitions P1 to Pn of the cache 100. As mentioned previously, controlling of the content of the physical and virtual libraries by the management module 30 allows the assignment of statuses to the virtual volumes which are used for calculations of occupancy rates by the module 32 controlling the occupancy of the cache 100. In some embodiments of the invention, the management module 30, during the flush operation of the cache 100, uses the results of the calculations performed by the module 32 controlling cache occupancy to choose the virtual volumes V′1 to V′n of the cache 100 to be copied into the physical library P201 to P20n. The virtual volumes V′1 to V′n of the cache 100 thus selected for a flush operation are closed virtual volumes V′1 to V′n having <<disk only>> status since they are not in the progress of being used (not currently used) and do not have an image in the physical library or have at least one image in the physical library which is not valid. In some particularly advantageous embodiments, this selection may be made in accordance with a so-called LRU rule (<<Less Recently Used>>). The virtual volumes V′1 to V′n selected in accordance with this rule are the virtual volumes V′1 to V′n the less recently accessed, for reading or writing, by the partition P1 to Pn of the cache 100 if the value of individual occupancy rate of this partition is greater or equal to the value of the maximum occupancy threshold, or by the all the partitions P1 to Pn of the cache 100 if the values of the individual occupancy rates of all the partitions are lower than the maximum occupancy threshold. In some embodiments of the invention, the management module 30 also comprises a module 34 of activity control of the physical library P201 to P20n. This module 34 controlling the activity of this library permanently updates information at least on the utilization of the readers P2001 to P200n and/or of the cartridges P211 to P21n of the libraries P201 to P20n under the control of the storage system 1. This information is used by the management module 30 to manage priorities over time for access to the storage resources 20, 100, particularly in relation to the availability of the readers P2001 to P200n and/or cartridges P211 to P21n. Firstly this module 34 therefore permits the regulation of accesses to the storage resources 20, 100 by the system 1 itself for a flush operation of the cache 100 towards the physical library P201 to P20n. Secondly, this module 34 also allows regulation of accesses to the storage resources 20, 100 by the computer platforms 101 to 10n to read/write a virtual volume V′1 to V′n not present in the cache 100 and therefore requiring consultation of the physical library P201 to P20n for the copying of a virtual volume V1 to Vn from this physical library P201 to P20n to the cache 100, in the form of a virtual volume V′1 to V′n of the virtual library V201 to V20n. In some embodiments of the invention, the management module 30, through its access means to the content of the storage resources 20, 100, permanently updates information on at least the validity of the volumes V1 to Vn present in the cartridges P211 to P21n of the physical libraries P201 to P20n under the control of the storage system 1. The management module 30 therefore permanently verifies that the data present in the library is up to date relative to any virtual volumes V′1 to V′n which may have been modified in the cache 100 by the computer platforms 101 to 10n. This management module 30 responsible for emulating virtual volumes V1 to Vn of the physical library P201 to P20n into virtual volumes V′1 to V′n of the virtual library V201 to V20n of the cache, offers the possibility that a virtual volume V′1 to V′n of the cache 100 may have multiple images V1 to Vn in the physical library P201 to P20n but, by assigning statuses to the virtual volumes, allows the virtual volumes V′1 to V′n of the cache 100 which will be taken into account by the module 32 controlling cache occupancy, for calculation of occupancy rate, to be only those which correspond to the virtual volumes V′1 to V′n of the cache 100 whose images V1 to Vn present in the physical library P201 to P20n are not all valid (volumes having <<disk only>> status). This information on validity enables the management module 30 to compare the number of obsolete virtual volumes V1 to Vn in the cartridges P211 to P21n of the physical library P201 to P20n with a maximum invalidity threshold. Therefore, when this space occupied by these obsolete virtual volumes V1 to Vn reaches this threshold, the management module 30 carries out compacting of the valid volumes V1 to Vn of the physical library P201 to P20n, in the cartridges P211 to P21n containing virtual volumes V1 to Vn that are not used in the physical library P201 to P20n and/or corresponding to closed virtual volumes V′1 to V′n in the cache100. This compacting is performed by the management module 30 by controlling the reading of all the valid volumes V1 to Vn in the source cartridges P211 to P21n containing obsolete volumes V1 to Vn and the simultaneous copying of these valid volumes V1 to Vn into target cartridges P211 to P21n, so as to delete these source cartridges P211 to P21n and obtain only cartridges P211 to P21n containing valid volumes V: to Vn in the physical library P201 to P20n. In addition, in some embodiments of the invention, the management module 30 uses the results of the operations performed by the module 31 controlling cache activity and the module 32 controlling cache occupancy, so as to update the data in the cartridges P211 to P21n of the library P201 to P20n, in relation to the activity and occupancy of the cache 100. Therefore, this compacting of data in the cartridges P211 to P21n may be made by giving preference to accesses to the storage resources 20, 100 by the computer platforms 101 to 10n over the accessing required for compacting. For example, this compacting may possibly only take place if few accesses to the physical storage resources 20 are made during a determined time period. The management module 30 may, in some embodiments of the invention, compare the number of obsolete volumes V1 to Vn in the cartridges P211 to P21n of the physical library P201 to P20n with a maximum invalidity threshold. If this threshold is exceeded, the management module 30 will perform compacting of the valid virtual volumes V1 to Vn of the physical library. Therefore, the source cartridges P211 to P21n containing invalid volumes will be erased and only those cartridges P211 to P21n will remain which contain valid volumes V1 to Vn, placed end to end for example so as to save storage space which, up until then, was wasted by invalid or deleted volumes. The method of the invention will now be described with reference to FIGS. 2 to 4. The method of the invention is implemented by a storage system 1 of the type described above. This method comprises at least the following steps: emulating (61) virtual volumes V1 to Vn of the physical library P201 to P20n into virtual volumes V′1 to V′n of the virtual library V201 to V20n of the cache 100, by a management module 30 present in the processing means 11 of the storage system 1 and managing accesses to the storage resources 20, 100 both to virtual volumes V1 to Vn of the physical library P201 to P20n and to virtual volumes V′1 to V′n of the cache 100, in relation to requests transmitted by the access means 101 of the computer platforms 101 to 10n to the storage system 1; calculating (62), by a module 31 of cache activity control, at least one activity index of the cache 100 per determined period of time, this calculation step (62) being repeated to monitor changes in the activity of the cache 100 periodically or, on an ad hoc basis, whenever space is allocated for a new virtual volume V′1 to V′n in the cache 100; calculating (63), by a module 32 of cache occupancy control, at least one occupancy rate of the cache 100 at a given time, this calculation step (63) being repeated to monitor changes in occupancy of the cache 100 periodically or, on an ad hoc basis, whenever space is allocated for a new virtual volume V′1 to V′n in the cache 100; deciding (64), by the management module 30, in relation to the result of these calculations and of at least one algorithm AG of management of the access bandwidth to the cache 100, and implemented in the storage system 1, between authorization (70) or interdiction (80) to access the storage resources 20, 100 either by the computer platforms 101 to ion to read/write virtual volumes V′1 to V′n in the cache 100, or by the system 1 itself for at least one operation, called a cache flush operation, allowing copying of the data of at least one virtual volume V′1 to V′n from the virtual library V201 to V20n towards at least one virtual volume V1 to Vn of the physical library P20, to P20n. Prior to implementing the above-described steps, the method may integrate at least one installation step (67) to install a plurality of partitions P1 to Pn on a plurality of hard disks 1001 to 100n forming the cache 100. Additionally, as mentioned previously, the system may comprise an organization module 33 in which case the method comprises at least one step (68) to create and update data representing information on the distribution of the partitions P1 to Pn and the distribution of the data recorded on the different partitions P1 to Pn. The organization module 33, on the basis of this information, generates at least one directory RP containing information on the locations and utilization of the virtual volumes V′1 to V′n, the virtual volumes V′1 to V′n on which reading or writing is in progress being identified as “open” virtual volumes, and the virtual volumes on which no reading or writing is in progress being identified as “closed” virtual volumes. Additionally, as mentioned previously, the management module 30 comprises access means to the content of the physical P201 to P20n and virtual V201 to V20n libraries. These access means enable the management module 30 to assign a status to each of the virtual volumes from among the above-described statuses. This information grouped together by the management module 30 is used to determine whether the different virtual volumes are present both in the virtual library V201 to V20n and in the physical library P201 to P20n, and to know whether the different images of the virtual volumes are valid and whether the images V′1 to V′n in the virtual library V201 to V20n are or are not being utilized. In the embodiments in which all the modules 30, 31, 32, 33 and 34 are carried by a software application run on the processing means 11 of the storage system 1, the method evidently comprises an installation step of this software application in the operating system of the storage system 1, by recording the data required for running this application in a memory accessible by the processing means 11 of the system 1. As explained above, this software application will be responsible for the interoperability of the different means of the system 1 and may itself form all the modules 30, 31, 32, 33 and 34 of the system 1. In some embodiments of the invention, the calculation step (62) to calculate the activity index of the cache 100 per determined periods of time consists of calculating a mean, over a determined number of successive determined periods of time, of the maximum number of virtual volumes V′1 to V′n of the cache 100 that are simultaneously opened during each determined period of time. For example, the calculation can be made over 3 successive period of time and the module 31 of cache activity control, controlling the activity of the cache 100, will therefore repeat 3 times the measuring of the number of virtual volumes V′1 to V′n of the cache 100 on which reading or writing is in progress during each of these 3 successive periods of time. Afterwards, the module 31 controlling cache activity will calculate the mean of the 3 values obtained to obtain a mean number of opened volumes representing the reality, since any sudden variations will have been smoothed by this mean calculated over several successive periods. More simply, this calculation could also be made over a single period, but it would be less representative of the reality and might not allow proper estimation of the activity of the cache 100. In some embodiments of the invention, the step (63) to calculate the occupancy rate of the cache 100 at a given time, by the module 32 of cache occupancy control, controlling occupancy of the cache 100, comprises firstly a step (635) to calculate a so-called individual occupancy rate corresponding to calculation of the occupancy on each of the partitions P1 to Pn of the cache 100 individually, and secondly a step (636) to calculate a so-called mean occupancy rate corresponding to calculation of the occupancy rate of all the partitions P1 to Pn of the cache 100. In the embodiments in which the management module 30 assigns statuses to the virtual volumes, this step (636) calculating a mean occupancy rate of the cache 100, by module 32 controlling occupancy of the cache 100, consists of measuring for all partitions P1 to Pn of the cache 100, the sum of the total size of the data present in the closed virtual volumes V′1 to V′n having <<disk only>> status, and the size allocated to the opened virtual volumes V′1 to V′n, irrespective of their status, this sum being compared to the total size available in all the partitions P1 to Pn of the cache 100, to obtain the mean occupancy rate of all the partitions P1 to Pn of the cache 100. Similarly, step (635) to calculate the individual occupancy rate of each partition P1 to Pn of the cache 100, by module 32 controlling occupancy of the cache 100, in this embodiment, consists of measuring for each of the partitions P1 to Pn of the cache 100 individually the total size of the data present in the virtual volumes V′1 to V′n having <<disk only>> status, whether they are open or closed, this size being compared to the total size available in the partition P1 to Pn of the cache 100 under consideration, to obtain the mean occupancy rate of each of the partitions P1 to Pn of the cache 100. In some embodiments of the invention, the method also comprises at least one comparison step (65) of the cache activity index with a minimum activity threshold and a maximum activity threshold, a comparison step (661) of the individual occupancy rate of the cache with the maximum occupancy threshold and a comparison step (662) of the mean occupancy rate with a first threshold, called a priority threshold below which occupancy of the cache 100 has priority over flushing, and a second threshold called a flush start threshold above which flushing of the cache 100 can be performed. These comparison steps are implemented by the management module 30 to manage accesses to the cache 100 by means of the cache's access bandwidth management algorithm AG, managing the access bandwidth to the cache 100, implemented in the storage system 1 as explained previously, for the management rules in relation to the different thresholds. These rules and the parameterisation of the algorithm described previously will not be further detailed here. The calculations of the activity index and individual and mean occupancy rates allow precise control over the operations performed by the system 1 in relation to the utilization of the different partitions of the cache 100. The system therefore provides flexible utilization enabling an operator to fix different values for the thresholds and to control the different internal operations performed in relation to the values of the thresholds and parameters chosen in the management algorithm. In the embodiments of the invention in which the system comprises an organization module 33, step (62) to calculate the activity index of the cache 100, by the module 31 of cache activity control, comprises at least one consultation step (621) of the data generated by the organization module 33 in order to calculate the activity of the cache by counting the number of virtual volumes opened in the cache 100. The maximum activity threshold corresponds to the total number of virtual volumes V′1 to V′n of the cache 100 which, when they are opened at the same time, consume a fraction of the access bandwidth to the cache 100 that is considered too high to allow the start of an operation requiring access to the cache 100. When this threshold is reached, an operation requiring access to the cache 100 risks saturating the bandwidth or setting up conflicting access to the different partitions P1 to Pn of the cache 100. Similarly, step (63) to calculate the occupancy rate of the cache 100, by the module 32 of cache occupancy control, comprises at least one consultation step (631) of the data generated by the organization module 33, to know the number of open and closed virtual volumes and to calculate the occupancy rates as explained above. In the embodiments in which the management module 30 assigns statuses to the virtual volumes, this consultation step (631) enables the module 32 of cache occupancy control to calculate firstly the mean occupancy rate of the cache 100 by comparing (632) the sum, for all partitions P1 to Pn of the cache 100, of the total size of the data present in the open virtual volumes V′1 to V′n, irrespective of their status, and the size of the data present in the closed virtual volumes V′1 to V′n having <<disk only>> status, with the total storage capacity of all the partitions P1 to Pn of the cache 100. This consultation step (631) enables the module 32 of cache occupancy control to calculate also the individual occupancy rate of each of the partitions P1 to Pn of the cache 100 by comparing (633), for a given partition P1 to Pn, the size of the data present in the virtual volumes V′1 to V′n having <<disk only>> status, whether they are opened or closed, with the total storage capacity of this partition P1 to Pn of the cache 100. In addition, the emulation step (61) of the virtual volumes V′1 to V′n by the management module 30 may comprise a cooperation step (611) between the organization module 33 and module 31 of cache activity control and module 32 of cache occupancy control, so as to distribute data equitably over the different partitions P1 to Pn of the cache 100, in order to promote homogeneous distribution of the virtual volumes V′1 to V′n over the disks carrying the different partitions P1 to Pn of the cache 100. This distribution also avoids heavy concentrations of access to the different disks carrying the different partitions P1 to Pn of the cache 100. In some embodiments, the flush operation of the cache 100 results from the use, by the management module 30, of the results of the calculations performed by module 32 of cache occupancy control, so as to select those virtual volumes V′1 to V′n of the cache 100 to be copied into the physical library P201 to P20n). The virtual volumes V′1 to V′n of the cache 100 thus selected for a flush operation are closed virtual volumes V′1 to V′n having <<disk only>> status since they are not in the progress of being used and they do not have an image in the physical library or have at least one image in the physical library which is not valid. In some particularly advantageous embodiments, the virtual volumes V′1 to V′n thus selected are the less recently accessed virtual volumes V′1 to V′n, for reading or writing, by the computer platforms 101 to 10n, either in a given partition P1 to Pn of the cache 100 if the value of the individual occupancy rate of this partition is greater or equal to the value of maximum occupancy threshold, or in all the partitions P1 to Pn of the cache 100 if the values of the individual occupancy rates of all the partitions are lower than the value of the maximum occupancy threshold. In the embodiments in which the management module 30 comprises a module 34 controlling the activity of the library, the method comprises at least one step (71) to create and update data representing information on the utilization of readers and/or of the cartridges of the libraries P201 to P20n under the control of the storage system 1. As explained previously, this information enables the management module 30 to manage priorities over time for accesses to the storage resources 20, 100, firstly by the system 1 itself for a flush operation of the cache 100 towards the physical library P20, to P20n, and secondly by the computer platforms 101 to 10n to read/write a virtual volume V′1 to V′n not present in the cache 100 and therefore requiring consultation of the physical library P201 to P20n to copy a volume V1 to Vn from this physical library P201 to P20n to the cache 100, in the form of a virtual volume V′1 to V′n of the virtual library V201 to V20n. In the embodiments in which the management module 30 comprises means for accessing the content of the storage resources 20, 100 of the storage system 1, the management module 30 can conduct at least step (69) to create and update data representing information on the validity of the volumes V1 to Vn present in the cartridges P211 to P21n) of the libraries P20, to P20n under the control of the storage system 1, with respect to any virtual volumes V1 to Vn which may have been modified in the cache 100 by the computer platforms 101 to 10n. This information on validity allows the management module 30 to implement a comparison step (89) of the space occupied by the obsolete volumes V1 to Vn in the cartridges P211 to P21n of the physical library P201 to P20n with a maximum invalidity threshold. When the space occupied by these obsolete virtual volumes physique V1 to Vn reaches this threshold, the management module 30 performs a compacting step (90) of the valid volumes V1 to Vn in the physical library P201 to P20n. Therefore the management module 30 is able to carry out compacting of valid volumes V1 to Vn, taken from cartridges P211 to P21n containing non-utilized volumes V1 to Vn and/or corresponding to closed virtual volumes V′1 to V′n, by controlling a reading (92) of all the valid volumes V1 to Vn of the source cartridges P211 to P21n containing obsolete volumes V1 to Vn and simultaneously a copying (93) of these valid volumes V1 to Vn into target cartridges P211 to P21n, so as to erase these source cartridges P211 to P21n and only obtain cartridges P211 to P21n containing valid volumes V1 to Vn in the physical library P201 to P20n. As mentioned previously, the emulation step (61) of the virtual volumes V1 to Vn of the physical library P201 to P20n into virtual volumes V′1 to V′n of the virtual library V201 to V20n of the cache 100, and the management steps of the cache 100 by the management module 30 offer the possibility that a virtual volume V′1 to V′n of the cache 100 may have multiple copies V1 to Vn, called images, in the physical library P201 to P20n. The creation and updating step (69), by the management module 30, of data representing information on the validity of the volumes V1 to Vn present in the cartridges P211 to P21n of the physical libraries P201 to P20n, allows the virtual volumes V′1 to V′n of the cache 100 taken into account by the module 32 controlling cache occupancy, for calculation of occupancy rate, to be those which correspond to the virtual volumes V′1 to V′n of the cache having <<disk only>> status, i.e. whose images present in the physical library are not all valid. Finally, step (90) to compact the physical library P201 to P20n may comprise a step (91) in which the management module 30 uses the results of the operations performed by the module 31 of cache activity control, by the module 32 cache occupancy control and by the module 34 of activity control of the physical library P201 to P20n. Through this use (91), the compacting of the valid volumes V1 to Vn of the physical library P201 to P20n by the management module 30 will be made in relation to the activity and occupancy of the cache 100, giving preference to accesses to the storage resources 20, 100 by the computer platforms 101 to 10n over accesses required for this compacting. It will be obvious for persons skilled in the art that the present invention allows embodiments under numerous other specific forms without departing from the scope of application of the invention such as claimed. Therefore the described embodiments are to be considered as illustrative but can be modified in the field defined by the scope of the appended claims, and the invention is not to be construed as being limited to the foregoing details.	G	60G06	161G06F	12	00
11799030	US20080270361A1-20081030	Hierarchical metadata generator for retrieval systems	ACCEPTED	20081016	20081030	[]	G06F1730	["G06F1730"]	7895197	20070430	20110222	707	728000	64146.0	NGUYEN	PHONG	[{"inventor_name_last": "Meyer", "inventor_name_first": "Marek", "inventor_city": "Schwalbach", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Hildebrandt", "inventor_name_first": "Tomas", "inventor_city": "Darmstadt", "inventor_state": "", "inventor_country": "DE"}]	A computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, associating the fragments with the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes metadata related to one or more topics of the fragment. A query for one or more documents containing information about a topic is received, and a document is located from the database based on a comparison of the query with the metadata associated with a fragment of the document.	1. A computer-implemented method of locating information in a database of electronic documents, the method comprising: defining fragments of the documents; associating the fragments with the document from which the fragments originated; associating metadata with the fragments, wherein the metadata associated with a fragment includes metadata related to one or more topics of the fragment; receiving a query for one or more documents containing information about a topic; and locating a document from the database based on a comparison of the query with the metadata associated with a fragment of the document. 2. The method of claim 1, wherein defining fragments of the documents comprises defining fragments of the documents based on markup tags that indicate logical components of the documents. 3. The method of claim 1, wherein defining fragments of the documents comprises defining fragments of the documents based on semantic content of different parts of the document. 4. The method of claim 1, wherein dividing the documents into fragments comprises dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on semantic content of different parts of the document, and further comprising: monitoring the frequency with which individual fragments are identified as relevant to search queries; and updating the fragments into which documents are divided based on the monitored frequency with which individual fragments are identified as relevant to search queries. 5. The method of claim 1, wherein the metadata associated with at least one fragment is based on a comparison of information in the fragment with information in an electronic encyclopedia. 6. The method of claim 5, wherein the electronic encyclopedia is a wiki database. 7. A computer-implemented method of locating information in a database of electronic documents, the method comprising: defining fragments of the documents; maintaining an order in which the fragments appear in a document; maintaining an association between the fragments and the document from which the fragments originated; associating metadata with the fragments, wherein the metadata associated with a fragment includes metadata related to one or more topics of the fragment; receiving a query for one or more documents containing information about a first topic and about a second topic; locating a document in the database based on a comparison of the query with the metadata associated with a fragment of the document. 8. The method of claim 7, wherein the query includes a request for one or more documents containing information about the first topic that is located within a certain proximity to information about the second topic and wherein locating the document in the database is based on a comparison of the query with the metadata associated with a fragment of the document and with a comparison to the order in which the fragments appear in the document. 9. The method of claim 7, wherein the first topic corresponds to a context of the document and wherein the second topic corresponds to a topic of a fragment. 10. The method of claim 7, wherein dividing the documents into fragments comprises dividing the documents into fragments based on markup tags that indicate logical components of the documents. 11. The method of claim 7, wherein dividing the documents into fragments comprises dividing the documents into fragments based on dissimilarity measures between parts of the documents. 12. The method of claim 7, wherein dividing the documents into fragments comprises dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on dissimilarity measures between parts of the documents, and further comprising: monitoring the frequency with which individual fragments are identified as relevant to search queries; and updating the fragments into which documents are divided based on the monitored frequency with which individual fragments are identified as relevant to search queries. 13. The method of claim 7, wherein the metadata associated with at least one fragment is based on a comparison of information in the fragment with information in an electronic encyclopedia. 14. The method of claim 7, wherein the electronic encyclopedia is a wiki database. 15. A system for locating information in a database of documents, the system comprising: a document splitting engine adapted for defining fragments of the documents; a metadata generation engine adapted for associating metadata with the fragments, wherein the metadata associated with a fragment relates to one or more topics of the fragment; a memory of storing an order in which the fragments appear in a document and for storing an association between the fragments with the document from which the fragments originated; a query engine adapted for receiving a query for one or more documents containing information about a first topic and about a second topic and for locating a document in the database based on a comparison of the query with the metadata associated with a fragment of the document. 16. The system of claim 15, wherein the query includes a request for one or more documents containing information about the first topic that is located within a predetermined proximity to information about the second topic and wherein locating the document in the database is based on a comparison of the query with the metadata associated with a fragment of the document and with a comparison to the order in which the fragments appear in the document. 17. The system of claim 15, wherein the first topic corresponds to a context of the document and wherein the second topic corresponds to a topic of a fragment. 18. The system of claim 15, wherein the document splitting engine is adapted for dividing the documents into fragments based on markup tags that indicate logical components of the documents. 19. The system of claim 15, wherein the document splitting engine is adapted for dividing the documents into fragments based on dissimilarity measures between parts of the documents. 20. The system of claim 15, wherein the metadata engine is adapted for associating metadata with a fragment based on a comparison of information in the fragment with information in a wiki database.	<SOH> BACKGROUND <EOH>With the advent and proliferation of electronic storage of documents, particularly in networked environment, more and more documents are written, exchanged, modified, and stored. Because of the overwhelming volume of documents that are available to a user, finding a particular document of interest to the user can be very difficult. Therefore, search engines have been developed for locating and retrieving relevant documents. Generally, search engines locate documents through full text searching or through metadata-based searching. In a full text mode, a search engine locates all documents within a specified database that contain the search term(s) specified by the user. In contrast, with metadata-based searching, the search engine looks only for the occurrence of the user's search term(s) in metadata records about documents in the database. Full text searching tends to be overinclusive and often returns too many irrelevant results. One approach to mitigate the overinclusive nature of full text searching is to use ranking methods, such as, for example, Google's® PageRank® method. However, even ranked results often contain too many unsuitable hits in the top positions, sometimes as a result of the ongoing manipulation of search hits. Metadata-based searching provides fewer and generally more relevant search results, but metadata-based searching requires that the contents of a document are described appropriately with relevant metadata tags. However, even when documents are appropriately described, metadata-based has limitations because the metadata used to describe a large document might describe only the main themes and topics of the document but not information about finer-grained details of the documents. Thus, metadata-based searching often is inadequate for locating information in individual parts of a document.	<SOH> SUMMARY <EOH>In a general aspect, a computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, associating the fragments with the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes metadata related to one or more topics of the fragment. A query for one or more documents containing information about a topic is received, and a document is located from the database based on a comparison of the query with the metadata associated with a fragment of the document. In another general aspect, a computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, maintaining an order in which the fragments appear in a document, maintaining an association between the fragments and the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes metadata related to one or more topics of the fragment. A query is received for one or more documents containing information about a first topic and about a second topic, and a document is located in the database based on a comparison of the query with the metadata associated with a fragment of the document. In a further general aspect, a system for locating information in a database of documents includes a document splitting engine adapted for defining fragments of the documents, a metadata generation engine adapted for associating metadata with the fragments, wherein the metadata associated with a fragment relates to one or more topics of the fragment, a memory of storing an order in which the fragments appear in a document and for storing an association between the fragments with the document from which the fragments originated, and a query engine adapted for receiving a query for one or more documents containing information about a first topic and about a second topic and for locating a document in the database based on a comparison of the query with the metadata associated with a fragment of the document. Implementations can include one or more of the following features. For example, defining fragments of the documents can include defining fragments of the documents based on markup tags that indicate logical components of the documents. Defining fragments of the documents can include defining fragments of the documents based on semantic content of different parts of the document. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on semantic content of different parts of the document. In addition, the frequency with which individual fragments are identified as relevant to search queries can be monitored and the fragments into which documents are divided can be updated based on the monitored frequency with which individual fragments are identified as relevant to search queries. The metadata associated with at least one fragment can be based on a comparison of information in the fragment with information in an electronic encyclopedia, for example, a wiki database. The query can include a request for one or more documents containing information about the first topic that is located within a certain proximity to information about the second topic, and locating the document in the database can be based on a comparison of the query with the metadata associated with a fragment of the document and with a comparison to the order in which the fragments appear in the document. The first topic can correspond to a context of the document, and the second topic can correspond to a topic of a fragment. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents. Dividing the documents into fragments can include dividing the documents into fragments based on dissimilarity measures between parts of the documents. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on dissimilarity measures between parts of the documents. In addition, the frequency with which individual fragments are identified as relevant to search queries can be monitored, and the fragments into which documents are divided can be updated based on the monitored frequency with which individual fragments are identified as relevant to search queries. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.	TECHNICAL FIELD This disclosure relates to techniques of automated search and retrieval of information and, in particular, to a hierarchical metadata generator for retrieval systems. BACKGROUND With the advent and proliferation of electronic storage of documents, particularly in networked environment, more and more documents are written, exchanged, modified, and stored. Because of the overwhelming volume of documents that are available to a user, finding a particular document of interest to the user can be very difficult. Therefore, search engines have been developed for locating and retrieving relevant documents. Generally, search engines locate documents through full text searching or through metadata-based searching. In a full text mode, a search engine locates all documents within a specified database that contain the search term(s) specified by the user. In contrast, with metadata-based searching, the search engine looks only for the occurrence of the user's search term(s) in metadata records about documents in the database. Full text searching tends to be overinclusive and often returns too many irrelevant results. One approach to mitigate the overinclusive nature of full text searching is to use ranking methods, such as, for example, Google's® PageRank® method. However, even ranked results often contain too many unsuitable hits in the top positions, sometimes as a result of the ongoing manipulation of search hits. Metadata-based searching provides fewer and generally more relevant search results, but metadata-based searching requires that the contents of a document are described appropriately with relevant metadata tags. However, even when documents are appropriately described, metadata-based has limitations because the metadata used to describe a large document might describe only the main themes and topics of the document but not information about finer-grained details of the documents. Thus, metadata-based searching often is inadequate for locating information in individual parts of a document. SUMMARY In a general aspect, a computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, associating the fragments with the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes metadata related to one or more topics of the fragment. A query for one or more documents containing information about a topic is received, and a document is located from the database based on a comparison of the query with the metadata associated with a fragment of the document. In another general aspect, a computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, maintaining an order in which the fragments appear in a document, maintaining an association between the fragments and the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes metadata related to one or more topics of the fragment. A query is received for one or more documents containing information about a first topic and about a second topic, and a document is located in the database based on a comparison of the query with the metadata associated with a fragment of the document. In a further general aspect, a system for locating information in a database of documents includes a document splitting engine adapted for defining fragments of the documents, a metadata generation engine adapted for associating metadata with the fragments, wherein the metadata associated with a fragment relates to one or more topics of the fragment, a memory of storing an order in which the fragments appear in a document and for storing an association between the fragments with the document from which the fragments originated, and a query engine adapted for receiving a query for one or more documents containing information about a first topic and about a second topic and for locating a document in the database based on a comparison of the query with the metadata associated with a fragment of the document. Implementations can include one or more of the following features. For example, defining fragments of the documents can include defining fragments of the documents based on markup tags that indicate logical components of the documents. Defining fragments of the documents can include defining fragments of the documents based on semantic content of different parts of the document. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on semantic content of different parts of the document. In addition, the frequency with which individual fragments are identified as relevant to search queries can be monitored and the fragments into which documents are divided can be updated based on the monitored frequency with which individual fragments are identified as relevant to search queries. The metadata associated with at least one fragment can be based on a comparison of information in the fragment with information in an electronic encyclopedia, for example, a wiki database. The query can include a request for one or more documents containing information about the first topic that is located within a certain proximity to information about the second topic, and locating the document in the database can be based on a comparison of the query with the metadata associated with a fragment of the document and with a comparison to the order in which the fragments appear in the document. The first topic can correspond to a context of the document, and the second topic can correspond to a topic of a fragment. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents. Dividing the documents into fragments can include dividing the documents into fragments based on dissimilarity measures between parts of the documents. Dividing the documents into fragments can include dividing the documents into fragments based on markup tags that indicate logical components of the documents or based on dissimilarity measures between parts of the documents. In addition, the frequency with which individual fragments are identified as relevant to search queries can be monitored, and the fragments into which documents are divided can be updated based on the monitored frequency with which individual fragments are identified as relevant to search queries. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a system for generating hierarchical metadata for documents in a database and for locating information in the documents based on the hierarchical metadata. FIG. 2 is a block diagram of an example network of computing resources for implementing the system of FIG. 1 FIG. 3 is a block diagram of another example network of computing resources for implementing the system of FIG. 1. FIG. 4 is a flowchart illustrating example operations of a method for generating hierarchical metadata for documents in a database and for locating information in the documents based on the hierarchical metadata. FIG. 5 is a flowchart illustrating additional example operations of another method for generating hierarchical metadata for documents in a database and for locating information in the documents based on the hierarchical metadata. DETAILED DESCRIPTION FIG. 1 is a block diagram of a system 100 for generating hierarchical metadata for documents in a database and for searching for information in the documents based on the hierarchical metadata. The system includes a database 102 in which electronic documents can be stored and from which the documents can be retrieved for analysis or for provision to a user. The database 102 can be a physical or logical database and can be localized or distributed. For example, the database 102 can be one or more storage devices, such as document servers, hard disks, or optical disks that store multiple documents, or the database can be implemented in software, such that documents can be loaded into the software application for retrieval. In one implementation, the database 102 can be a hard disk or flash memory device associated with the personal computer of a user 104. In another example, the database 102 can be one or more networked storage devices storing documents that are available to the user 104. For example, the database 102 can be storage device in a local area network (LAN) of a business or organization to which a number of members of the business or organization have access. In another implementation, the database 102 can be a number of storage devices accessible through a wide area network (WAN). For example, the database 102 can be a number of storage devices accessible through the Internet. The database 102 can be known as a physical document database 102 because it stores actual electronic documents and to distinguish it from a virtual document database, discussed below, which can store representations of the electronic documents. The database is linked to a virtual document generator 106 that can access electronic documents in the physical document database 102 to generate metadata and indexing information about the documents in the database. The virtual document generator 106 includes a spider or web crawler engine 108 or automated script that can access the electronic documents in the database 102 by browsing the documents in a methodical, automated manner. The web crawler engine 108 can access the documents in the database 102 and create copies of the documents for further processing by the virtual document generator 106. Documents can be many different types of files that can be parsed by the virtual document generator 106, and can be stored in many different formats (e.g., PDF, DOC, HTML, XML, RAR, ZIP, TXT, PPT, XLS). Using a copy of an electronic document from the physical document database 102, a document splitter engine 110 operates to divide the document into a number of fragments in order to define multiple document fragments for the document. For a structured document, the document splitting engine 110 can divide the document into fragments based on the document's structure. For example, for an HTML document, the document splitting engine 110 can define fragments of the document based on markup tags within the document, such as tags that define paragraphs, sections, chapters and other logical sections of the document. Similarly, for a text document, such as a document formatted in Microsoft's® Word® format, the document splitting engine 110 can divide the document into fragments based on markup tags indicating paragraphs, sections, chapters, pages, etc. In another implementation, the document splitting engine 110 can divide the document into fragments based on the semantic content of different parts of the document. For example, the splitting engine 110 can parse the text of the document to determine where the subject matter of the document changes (e.g., by identifying dissimilarities in the semantic content of different portions of the document) and then can divide the document into fragments that are bounded by the occurrence of such subject matter changes. Thus, in a document about the effect of globalization on various different businesses, the splitting engine 110 may parse the document to determine that the document contains different parts that discuss the effect of globalization on the auto industry, on the software industry, and on the textile and apparel industry, and may define document fragments that correspond to each of the separate topics. Each fragment can be further subdivided into additional finer-grained fragments. For example, in the above example, the fragment of the document about the effect of globalization on the textile and apparel industry might include sub-fragments about labor conditions for workers in developing markets that make textiles and shoes, about deflation of prices for textiles in developed markets, and about trade relations between developed and developing markets. In still another implementation, the splitting engine 110 can divide the document into fragments based on the size of the document and the size of fragments. For example, for a 200 kb text document, the splitting engine 100 may divided the document into equally sized parts, and may define five parts of the document that each are 40 kb in size. The splitting engine 110 associates the fragments with the documents, for example, in an indexed table or other kind of structured database, such that the identification of fragment can be used to identify a document from which the fragment originated or vice versa. In addition, the splitting engine creates and maintains a unique identification number for the document and fragments of the document that distinguishes the document or fragment from all other documents and fragments and maintains an order in which the fragments appear in the document. For example, as shown in Table 1 below, the splitting engine 110, can create an indexed table that includes information about the location of the document (i.e., http://www.website.org/doc1), the number fragments that have been defined for the document, and the location of the fragments within the document (e.g., the paragraph number at which each document begins, as shown in Table 1). For example, as shown in the first line of Table 1, a document may be located at www.website.org/doc1 and may be assigned unique identification number “1982.0.” Also, for example, a third fragment of the document may be defined to begin at the 13th paragraph of the document and end after the 24th paragraph of the document. The third fragment of the document may be assigned unique identification number “1982.3.” Each fragment can be further subdivided into additional finer-grained fragments. For example, in the above example, the fragment of the document about the effect of globalization on the textile and apparel industry might include sub-fragments about labor conditions for workers in developing markets that make textiles and shoes, about deflation of prices for textiles in developed markets, and about trade relations between developed and developing market countries concerning textiles. For example, a document about the effect of globalization on various different businesses that is located by the URL, www.website.org/doc1, may be assigned the unique ID number 1982.0, and a fragment of the document corresponding to a section about the effect of globalization on the textile and apparel industry may be assigned unique ID number 1982.3. Sub-fragments about labor conditions for workers in developing markets, about deflation of prices for textiles in developed markets, and about trade relations between developed and developing markets could be assigned unique ID numbers 1982.3.1, 1982.3.2, and 1982.3.3, respectively. Information associating the document with the fragments and maintaining an order of the fragments can be stored in a virtual document hierarchy database 112 of the system 100. Thus, the virtual document hierarchy database 112 can, but need not, not store copies of the document or fragments, but can instead maintain pointer information in the virtual document hierarchy database 112 that can be used to locate and retrieve the document or fragments of the document from the physical document database 102. TABLE 1 Document http://www.website.org/doc1 1982.0 Fragment Start Paragraph 1 1 1982.1 2 8 1982.2 3 13 1982.3 4 25 1982.4 5 31 1982.5 6 39 1982.6 7 56 1982.7 8 63 1982.8 9 72 1982.9 The virtual document generator also includes an automatic metadata generator engine 114 for automatically generating semantic metadata about the fragments associated with a document. The metadata generator engine 114 can parse a document and/or fragments of the document and automatically generate metadata using a variety of techniques and algorithms. For example, the frequency with which a word occurs in a document or in a fragment can furnish a useful measurement of word's significance to the document or fragment, and therefore a word that appears frequently can be used as a metadata keyword for the document or fragment. Common words used primarily for syntax purposes (e.g., “a,” “and,” “but,” “the,” “his,” “her,” “it,” etc.) in a document or fragment can be maintained in a black list, such that they are excluded from being used as metadata keywords. In another implementation, metadata keywords can be limited to verbs and nouns. The absolute frequency of appearance of a word can be used as a measure of the significance of the word to the document or fragment, or the frequency of the word's occurrence can be compared to the word's usual frequency of use in the language a generally or in the a relevant context to determine the significance of the word and whether the word should be used as a metadata keyword. Ranking of the significance of frequently occurring words in the document or fragment can be augmented by information derived from markup tags in the document or fragment. For example, if a word appears in a title or URL of the document, the significance of the word to the document or fragment may be increased when ranking the word for use as a metadata keyword. In another implementation, the automatic metadata generator engine 114 can automatically generate metadata by parsing the document or fragment and comparing terms or words found in the document or fragment to predefined terms or clusters of terms representing nodes of a classification hierarchy, for example, a Dewey Decimal Classification hierarchy. The Dewey Decimal Classification (DDC) hierarchy is considered as a useful classification scheme because it provides a universal and widely-accepted classification scheme covering all subject areas and geographically global information, and the hierarchical nature of the DDC allows for defining metadata for a document or fragment at different levels of granularity. A hierarchy of Java classes can be used to model the DDC hierarchy, and documents and fragments can be filtered through this hierarchy according to which class representatives best match the document's or fragment's contents. For example, when filtering a document about the effects of globalization on business that includes a fragment about the textile and apparel industry, and sub-fragments about labor conditions of textile workers in developing markets, about deflation of prices for textiles in developed markets, and about trade relations between developed and developing markets, metadata keywords about the topic of the document can be assigned based on a match of the document's content with keywords associated with one or more DDC categories that correspond to content about business and globalization. Metadata keywords about topics of a fragment can be assigned to the fragment based on a match of the fragment's content with keywords associated with one or more DDC categories that correspond to content about the textile and apparel business, and metadata keywords can be assigned to the sub-fragments based on a match of the sub-fragments' content with keywords associated with one or more DDC categories that correspond to content about labor conditions of textile workers in developing markets, about deflation of prices for textiles in developed markets, and about trade relations between developed and developing markets. In still another implementation, the automatic metadata generator engine 114 can automatically generate metadata by parsing the document or fragment and comparing terms or words found in the document or fragment to the content of entries of an electronic encyclopedia. In implementation, when a term in the document for fragment matches the title of an entry in the encyclopedia, then important words in the content for the entry in the encyclopedia can be used as keywords for the fragment. Thus, for example, a document or fragment containing the phrase “irrational exuberance,” when parsed by the automatic metadata generator engine 114, may result in some of the following metadata keywords being generated for the document or fragment: “Alan Greenspan”; “Federal Reserve”; “Internet”; “Stock Market”; “Bubble”; “dot.com” and “Silicon Valley.” In another implementation, when a relatively high correlation between the content of the document or fragment and an entry of the electronic encyclopedia exists, then the title of the encyclopedia entry can be used as a metadata keyword, or important words and phrases within the entry can be used as metadata keywords. Thus, for example, if a fragment contains the terms “Alan Greenspan,” “Stock Market,” “Bubble,” “Internet,” and “1990's,” then the phrase “irrational exuberance” may be defined as a metadata keyword for the fragment based on a comparison of the content of the fragment with the content of the content of the entry for “irrational exuberance” in the electronic encyclopedia. The encyclopedia can be an encyclopedia that only a limited number of people can edit or change or can be a more open encyclopedia, such as a wiki that allows visitors to add, remove, edit, and change content, typically without the need for registration. Wikis have been successful at providing a collaborative forum for productive interaction and operation among many users to quickly generate relevant information content. Examples of wikis include the WikiWikiWeb and Wikipedia, which are accessible through the Internet. However, other wikis can also be provided for users of a local area network, e.g., people who work together within an organization or business who develop and maintain a wiki abut information concerning topics or interest or relevance to the organization or business. In addition to metadata about the semantic content of a documents or fragment, the automatic metadata generation engine 114 also can add extra additional descriptive metadata about the document or fragment. For example, the engine 114 can extract metadata about the word count, the MIME type, the initial publication date, the latest revision date, the word count, the creator(s), contributor(s), the publisher, and the language of the document or fragment. Once metadata have been identified or generated for a document or a fragment of a document, the metadata can be associated with the pertinent document or fragment, so that the metadata can be used later to locate and retrieve the document or fragment. In one implementation, the metadata can be stored in an XML document about the document or fragment using the Resource Description Framework (RDF) metadata model. For example, metadata keywords can be stored in an RDF Bag container. The XML document also includes a reference pointer to the related document that is located in the physical document database 102 and to information stored in the virtual document hierarchy database 112 about the order in which fragments occur in the physical document. Thus, such an XML document can function as a virtual document that stores meta-information about a document or fragment of a document that exists in the physical database 102. The XML-formatted virtual documents can be stored in a virtual document database 116 and used by a query engine 118 to search for information about the documents in the physical document database 102. For example, the virtual document database 116 can be queried, and matching results of the query can be mapped to associated physical documents in the database 102. By querying the virtual document database 116 that contains metadata for fragments in addition to metadata for documents, queries can be performed on different levels of granularity. The query engine 118 can also be referred to as a “search engine.” However, it should be understood that although a traditional browser-based search engine is one implementation of the query engine 118, the query engine can be any engine that receives query terms from a user and locates information based on the query terms. For example, metadata assigned to a document about the effect of globalization on various different businesses, can include the keywords “globalization,” “business,” “economics,” “markets,” “free trade,” “tariffs,” and “outsourcing.” However, for a fragment within the document dealing with the negative effects of globalization in the textile and apparel industry, the following metadata keywords might be assigned to the fragment: “globalization,” “textiles” “Nike®,” “Indonesia,” “China,” “sweatshops,” “child labor,” “pollution,” “environment.” Clearly, because the metadata assigned to individual fragments varies according to the content of the fragments and is different from the metadata assigned to the document of which the fragment is a part, querying the database 116 that includes virtual documents for fragments yields different, richer search results than if the database 116 included only virtual documents for entire documents. Thus, by splitting a document into fragments, and possibly sub-fragments, and then assigning metadata to the individual fragments, the system creates a virtual document database 116 that allows for richer searching on various levels of granularity. Moreover, metadata in the XML documents stored in the virtual document database 116 are linked to information in the virtual document hierarchy database 112, so that querying the virtual document database 116 can locate and retrieve documents that include particular combinations of fragments. For example, a user 104 might use the search engine 118 to submit a query for documents or documents containing fragments that include information about both the negative effects of globalization in the textile business and the positive effects of globalization on American financial brokerage businesses (i.e., Wall Street). Such a query could be structured as: {FRAG1.contains.(globali?ation AND textiles AND (Nike OR Indonesia OR China) AND (sweatshop OR “child labor” OR pollution)) AND FRAG2.contains.(globali?ation AND profit AND (“Wall Street” OR “Goldman Sachs” OR “Morgan Stanley” OR “Merrill Lynch” or Lehman))} By running such a query on the database of atomized virtual documents 116, the database may return results that point the user to physical documents in the database 102, which contain fragments that are narrowly focused on each topic of interest to the user, without obtaining too many “false positives,” and without missing too many documents that might be missed if the query were run only on the metadata of the document as a whole. In another implementation, the user 104 may use a hierarchical search extension script 120 of the search engine 118 to query for documents containing fragments about particular topics that occur in documents and that are located within a certain proximity of one another. For example, a user may use the hierarchical search extension script 120 of the search engine 118 to query for documents or fragments of documents contain information about the negative effects of globalization in the textile business adjacent to information about the positive effects of globalization on American financial brokerage businesses. Such a query could be structured as: {FRAG1.contains.(globali?ation AND textiles AND (Nike OR Indonesia OR China) AND (sweatshop OR “child labor” OR pollution)) W/IN=1 FRAG2.contains.(globali?ation AND profit AND (“Wall Street” OR “Goldman Sachs” OR “Morgan Stanley” OR “Merrill Lynch” or Lehman))}, where the operator “W/IN—1” specifies that the fragments identified by FRAG1 and FRAG2 must occur within one fragment position of one another within the physical document. In other words, the fragments containing information the negative effect of globalization on the textile business and the positive effect of globalization on Wall Street must be adjacent to each other to satisfy the search query. When such a hierarchical search query is entered by the user 104 into the search engine 118, the search engine may locate virtual documents and fragments in the database 116 based a matching of the query terms with the metadata for the documents and the fragments. Then, the search engine 118 may invoke the hierarchical search extension script 120 to filter the preliminary search results for documents in which the requested fragments appear consecutively in a document by comparing the metadata of the fragments and documents of the preliminary results with the information stored in the document hierarchy database 112 about the location of the fragments in documents. For example, to determine that two fragments found the in preliminary results are adjacent to each other in a document, the hierarchical search extension script 120 may require that the two fragments have consecutive unique identification numbers (e.g., “1982.2” and “1982.3”). In another implementation, the user 104 may use the hierarchical search extension script 120 of the search engine 118 to query for documents containing fragments about particular topics and that occur within a particular order in a document. For example, the operators “>” and “<” can be used to indicate that a first fragment about a first topic or topics must come before or after a second fragment about a second topic or topics in the physical document. Queries using the search engine 118 supplemented by the hierarchical search extension script 120 can be performed on the document level in addition to just on the fragment level. For example, if a user 104 wishes to locate documents containing a discussion of carbon compounds in the context of biology but does not with to receive many “false positive” results of documents containing a discussion of carbon compounds in the context of chemistry or medicine, the user by submit a query for documents containing a discussion of carbon compounds but that also include metadata indicating that the context of the document overall is related to biology. Thus, an example query could be structured as: {document.contains(‘carbon compounds’) AND context.category=’biology’} The strategy of the document splitter 110 for dividing a document into a number of component fragments can affect how useful the virtual document fragments are to the user 104 when searching for documents in the physical document database 102. The splitter should create fragments that have delimitable contents that are distinguishable from the content of the document itself, such that the metadata for the document and fragments of the document are different. Thus, for example, the fragments may need to be sufficiently small, such that their content is focused on one or more topics that differ from the overall topic(s) of the document. On the other hand, fragments that are too small may result in virtual documents for the fragments that are not useful to the user 104 because they are too narrowly focused and because having too many virtual documents in the metadata database 116 may degrade the performance of the system. To improve the success of the splitting engine 110, a virtual document evaluation engine 122 can receive feedback about usage values of virtual documents in the virtual document database 116 and provide feedback to the splitting engine 110 to improve the quality and utility of the virtual documents in the virtual document database 116. Feedback about the usage value of the virtual documents can be obtained in a variety of ways. For example, the evaluation engine 122 can receive direct feedback from a user 104 about whether a virtual document is useful or not, or feedback can be obtained based on the frequency with which a virtual document is used to locate a physical document for a user, which the user subsequently accesses (e.g., by viewing or downloading the document). If a virtual document about a fragment of a document never results in the document being accessed by the user in a certain amount of time, the evaluation engine 122 may conclude that the splitting algorithm used by the document splitter 110 is not optimized and needs to be refined, for example, by creating fragments that are larger or smaller than the existing fragments or by creating fragments based changes in semantic content of the document as opposed to based on a fixed number of paragraphs in each fragment. In another implementation, if a virtual document about a fragment of a document never results in the document being accessed by the user in a certain amount of time, the evaluation engine 122 may conclude that techniques used by the automatic metadata generator 114 is not optimized and need to be refined to create different semantic metadata for the document or fragment. If the evaluation engine 122 determines that a virtual document has a low usage value to the user, the engine may instruct the document splitter 110 to generate fragments of the document anew using a different algorithm than used previously, or may instruct the automatic metadata generator 114 to generate metadata for the document and fragments of the document anew using a different algorithm than used previously. By monitoring the usage value of virtual documents used to represent documents and fragments in the physical document database 102, the evaluation engine 122 can optimize the splitting and metadata generation algorithms used to determine the metadata records of the virtual documents in the virtual document database 116. Optimization techniques may use common machine learning technologies, such as, for example, support vector machines, artificial neural networks, decisions trees or similar systems. Through the optimization process, the evaluation engine can learn what techniques and algorithms work well for creating virtual documents that are predicted to have relatively high usage values. Finally, after the splitter 110 and the metadata generator 114 operate on a document to prepare metadata about the document and its fragments, the evaluation engine 122 may determine an estimated usage value for virtual documents with metadata representing the document or fragment based on prior measurements of usage values for similar virtual documents (e.g., virtual documents for documents or fragments of a similar size, semantic density, semantic content, MIME type, etc). Then, only those virtual documents with an actual or estimated usage value above a certain threshold may be written to the virtual document database 116. FIG. 2 is a block diagram of an example network 200 of computing resources for implementing the system of FIG. 1. The network can include a client computer 202 (e.g., a personal computer or a laptop computer) connected to a WAN 204 to allow the client computer 202 to interact with a server computer 206. The client computer 202 and the server computer 206 are also connected through the WAN 204 to other network storage servers 208a, 208b, 208c, 208d, and 208e. The network storage servers 208a, 208b, 208c, 208d, and 208e can store electronic documents to serve to a user through the WAN 204, and, thus, the network storage servers can implement the physical document database 102 of FIG. 1. The server computer 206 can implement the spider or web crawler engine 108 for accessing physical documents stored in the physical document database, and can implement the document splitter engine 110, the virtual document hierarchy database 112, the automatic metadata generator engines 114, the virtual document metadata database 116 and the virtual document evaluation engine 122. For example, these various engines and databases can be included in a server that provides backend search engine services to a user. The search engine 118 (e.g., a browser-based search engine) and the hierarchical search engine extension 120 can be implemented on the client computer 202, and a user 104 can use the search engine 118 and extension 120 to address queries to the various engines running on the server computer 206. Based on the query parameters, the server computer 206 then can provide the location of electronic documents in the physical document database 102 matching the query terms to the search engine operating on the client computer 202. FIG. 3 is a block diagram of another example network 300 of computing resources for implementing the system of FIG. 1. The network 300 can include a computer 302 (e.g., a personal computer or a laptop computer) that can function as a client computer when connected to a LAN 304 to allow the client computer 302 to interact with a LAN server computer 306. Other client computers 308 and 310 can also be connected to the LAN 304. The LAN 304 can be connected to a WAN 312 that is connected to one or more servers 314a, 314b, and 314c. In this configuration, the computers 302, 308, and 310 and one or more LAN servers 306 can store electronic documents that can be served to a user. For example, the LAN may belong to a business or organization that stores its electronic documents on one or more of the computers 302, 304, 306, and 310, where the electronic documents are accessible to a number of user of the LAN within the business or organization. Thus, one or more of the computers 302, 304, 306, and 310 can implement the physical document database 102 of FIG. 1. The LAN server 306 can implement the spider or web crawler engine 108 for accessing physical documents stored in the physical document database 102, and can implement the document splitter engine 110, the virtual document hierarchy database 112, the automatic metadata generator engines 114, the virtual document metadata database 116 and the virtual document evaluation engine 122. For example, these various engines and databases can be included in a LAN server that provides backend search engine services to a user having access to the LAN. The search engine 118 (e.g., a browser-based search engine) and the hierarchical search engine extension 120 can be implemented on the client computer 202, and a user 104 use the search engine 118 and extension 120 to address queries to the various engines running on the server computer 306. The server computer 306 then can provide the location of electronic documents in the physical document database 102 matching the query terms to the search engine operating on the client computer 202. In another implementation, one of the client computers 302, 308, or 310 can implement the spider or web crawler engine 108 for accessing physical documents stored in the physical document database 102, and can implement the document splitter engine 110, the virtual document hierarchy database 112, the automatic metadata generator engines 114, the virtual document metadata database 116 and the virtual document evaluation engine 122. For example, these various engines and databases can be implemented in a standalone search application (e.g., a “desktop search”) application running on a computer 302, 308, or 310 that indexes electronic documents accessible to the computer. As shown in FIG. 3, computer 302 can include a memory device (e.g., a hard disk) for storing an executable computer program that implements the various engines described with respect to FIG. 1. Executable code can be loaded into a random access memory 324 as one or more applications 326 and 328 for implementing the engines, and the code can be executed by a processor 330 (e.g., a central processing unit). FIGS. 4 and 5 are flowcharts illustrating example computer-implemented methods 400 and 500, respectively, for locating information in a database of electronic documents. These example methods will be described with reference to FIGS. 1-3. It will be appreciated that the example methods of FIGS. 4 and 5 may be applied to either network 200 or network 300, as well as any number of other arrangements of resources. As shown in FIG. 4, in method 400 fragments of the documents are defined (step 402), e.g., with use of the document splitting engine 110 shown in FIG. 1. Fragments are associated with the document from which the fragments originated (step 404). For example, the document splitting engine 110 can stored a table in the document hierarchy database 112 listing associations between fragments and the physical documents from which the fragments originated. Metadata is associated with the fragments, where the associated metadata includes metadata related to one or more topics of the fragment (step 406). For example, the automatic metadata generation engine 114 can define metadata for a document fragment and associate the metadata with the fragment (e.g., in an XML document stored in the virtual document metadata database 116). A query is received for one or more documents containing information about a topic (step 408), e.g., through the search engine 118, and a document is located from the database based on a comparison of the query with the metadata associated with a fragment of the document (step 410). As shown in FIG. 5, in method 500 fragments of the documents are defined (step 502), e.g., with use of the document splitting engine 110 shown in FIG. 1. An order in which the fragments appear in a document is maintained (step 504) and an association between the fragments and the document from which the fragments originated is maintaining (step 506). For example, the order of the fragments in a document and the association between the fragments and the document from which they originated can be maintained in a table stored in the document hierarchy database 112. Metadata is associated with the fragments, where the associated metadata includes metadata related to one or more topics of the fragment (step 508). A query is received for one or more documents containing information about a topic (step 510), e.g., through the search engine 118, and a document is located from the database based on a comparison of the query with the metadata associated with a fragment of the document (step 512). Implementations of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Implementations may implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the computer program(s) described above, can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network. Method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry. To provide for interaction with a user, implementations may be implemented on a computer having a display device, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. Implementations may be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation, or any combination of such back-end, middleware, or front-end components. Components may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet. While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments.	G	60G06	161G06F	17	30
11619047	US20070156934A1-20070705	High-speed PCI Interface System and A Reset Method Thereof	ACCEPTED	20070621	20070705	[]	G06F1342	["G06F1342"]	7549009	20070102	20090616	710	313000	73468.0	AUVE	GLENN	[{"inventor_name_last": "Ho", "inventor_name_first": "Kuan-Jui", "inventor_city": "Taipei", "inventor_state": "", "inventor_country": "TW"}, {"inventor_name_last": "Chen", "inventor_name_first": "Wen-Yun", "inventor_city": "Taipei", "inventor_state": "", "inventor_country": "TW"}]	A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot rest package cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.	1. A high-speed PCI interface system with reset function, comprising: a host controller chipset, comprising at least one root port, used to generate a PCI resetting signal; at least one high-speed PCI device, each of said high-speed PCI devices respectively coupled to said corresponding root port within said host controller chipset through a high-speed PCI bus; and at least one reset signal generator, respectively corresponding with each of said root ports, each of said reset signal generators respectively electricity coupled to said host controller chipset through a PCI reset signal line and a trigger signal line, and electricity coupled to said corresponding high-speed PCI device according to a basic reset signal line; wherein, said reset signal generator for respectively receiving said PCI resetting signal and a triggering signal through said PCI reset signal line and said trigger signal line, generating a basic resetting signal according to the operation of said PCI resetting signal and said triggering signal, sending said basic resetting signal to said corresponding high-speed PCI device through said basic reset signal line, and then commanding said high-speed PCI device to proceed a basic resetting action. 2. The high-speed PCI interface system of claim 1, wherein said triggering signal is generated from one triggering mode of software, firmware, hardware or the combination thereof. 3. The high-speed PCI interface system of claim 1, wherein said host controller chipset comprises a north bridge and a south bridge. 4. The high-speed PCI interface system of claim 3, wherein said root port is placed within said north bridge, and said reset signal is generated by said south bridge. 5. The high-speed PCI interface system of claim 4, wherein said triggering signal is generated from one triggering mode of software, firmware, hardware or the combination thereof. 6. The high-speed PCI interface system of claim 1, wherein said south bridge further comprises at least one general purpose output pin which is corresponding with each of said reset signal generators, and each of said general purpose output pins is coupled to said corresponding reset signal generator through said corresponding triggering signal line. 7. The high-speed PCI interface system of claim 4, wherein each of said reset signal generators is located in a motherboard or said north bridge. 8. The high-speed PCI interface system of claim 1, wherein each of said reset signal generators can be an AND gate. 9. The high-speed PCI interface system of claim 1, wherein said high-speed PCI device is selected from one of a image processing chip, a sound processing chip, a bridge and a complex root port. 10. A reset method for using the high-speed PCI interface system, comprising the following steps of: sending out a hot reset package to a high-speed PCI device for proceeding the hot resetting action through a corresponding high-speed PCI bus; determining whether said high-speed PCI device is ready, if so, then end; if not, then generating a basic resetting signal to said high-speed PCI device for proceeding a basic resetting action; and determining whether said high-speed PCI device is ready, if so, then end; if not, then again generating a basic reset signal to said high-speed PCI device for proceeding said basic resetting action, and forming a circulatory process. 11. The reset method of claim 10, wherein said reset method further comprises: determining whether said high-speed PCI device exists before beginning as the above mentioned step, if so, then proceeding the following step that is determining whether said high-speed PCI device is ready; if not, then end. 12. The reset method of claim 10, wherein said basic resetting signal is generated from said corresponding reset signal generator in operation of a triggering signal sent by said host controller chipset. 13. The reset method of claim 12, wherein said host controller chipset comprises a north bridge and a south bridge. 14. The reset method of claim 13, wherein said triggering signal is generated from one triggering mode of software, firmware, hardware or the combination thereof. 15. The reset method of claim 14, wherein said south bridge further comprises at least one general purpose output pin which is corresponding with each of said reset signal generator, and each of said general purpose output pins is coupled to said corresponding reset signal generator through said corresponding triggering signal line. 16. The reset method of claim 13, wherein said root port is located in said north bridge, and said PCI reset signal is generated by said south bridge. 17. The reset method of claim 12, wherein each reset signal generator is located in a motherboard or in said north bridge. 18. The reset method of claim 12, wherein each reset signal generator is an AND gate respectively. 19. The reset method of claim 10, wherein said high-speed PCI device is selected from one of a image processing chip, a sound processing, a bridge and a complex root port. 20. The reset method of claim 10, wherein said reset method further comprises: determining whether said high-speed PCI device is ready before proceeding said hot reset action.	<SOH> BACKGROUND OF THE INVENTION <EOH>Since the electrical industry has changed with each passing day, the CPU and chipset are promoting upwards constantly that the transmission speed of the PCI interface is the choke point for the whole speed of the computer system. Now the high-speed PCI (PCI Express) is presented, thereof is having more advantages as fast high-performance bandwidth, advanced power management function, hot plug, point to point transmission and serious connection, which are adopted by user such that the manufacturer develops the related electronic product with the high-speed PCI interface. However, since the software and hardware of the computer system are powerful functions and fast speed, the stable operation thereof is the focus to the user, and every manufacturer strives toward. Usually while the user is operating the computer, which may meet the computer crash, for example: the high-speed PCI device falls into endless loop or be unable waked up from Suspend to RAM (STR) of the hibernate mode. Now, if the computer system adopts a high-speed PCI device with PCI Express interface, which sends a hot reset package to the unbounded high-speed PCI device that will be again restarting normal coupled with the computer system. Referring FIG. 1 that is shown of the electricity-coupled diagram of the system with high-speed PCI interface of the prior art. As shown in the figure, the system 10 comprises a north bridge 11 with at least one root port 111 , at least one high-speed PCI device 13 and a south bridge 15 . When turn on the power, the south bridge 15 can transmit a PCI resetting signal (PCI RST#) to a buffer 112 through a PCI reset signal line 151 , and then the buffer 112 can transmit the PCI resetting signal to the high-speed PCI device 13 through a reset signal line 113 such that the system 10 will proceed an initializing action for the high-speed PCI device 13 . After the system 10 is finished the initializing action, the user can normally operate the system 10 . When the high-speed PCI device 13 fails to communicate with the north bridge 11 normally, the system 10 will adopt the root port 111 for transmitting a hot reset package to the high-speed PCI device 13 through a high-speed PCI bus 117 , such that the high-speed PCI device 13 will proceed the initializing action to normally communicate with the north bridge 11 again. However, the high-speed PCI device 13 may not be able to execute the hot reset packet, the only way to reset the high-speed PCI device 13 is to turn off and on the power. In other word, the user wastes much effort but do nothing completely.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a high-speed PCI interface system with reset function, comprising: a host controller chipset, comprising at least one root port, used to generate a PCI resetting signal; at least one high-speed PCI device, each of said high-speed PCI devices respectively coupled to said corresponding root port within said host controller chipset through a high-speed PCI bus; and at least one reset signal generator, respectively corresponding with each of said root ports, each of said reset signal generators respectively electricity coupled to said host controller chipset through a PCI reset signal line and a trigger signal line, and electricity coupled to said corresponding high-speed PCI device according to a basic reset signal line; wherein, said reset signal generator for respectively receiving said PCI resetting signal and a triggering signal through said PCI resetting signal line and said trigger signal line, generating a basic resetting signal according to the operation of said PCI resetting signal and said triggering signal, sending said basic resetting signal to said corresponding high-speed PCI device through said basic reset signal line, and then commanding said high-speed PCI device to proceed a basic resetting action. The present invention also provides a reset method for using the high-speed PCI interface system, comprising the following steps of: a corresponding root port sending out a hot reset package to a high-speed PCI device for proceeding the hot resetting action through a corresponding high-speed PCI bus; determining whether said high-speed PCI device is ready, if so, then end; if not, then generating a basic resetting signal to said high-speed PCI device for proceeding a basic resetting action; and again determining whether said high-speed PCI device is ready, if so, then end; if not, then again generating a basic resetting signal to said high-speed PCI device for proceeding said basic resetting action, and forming a circulatory process.	FIELD OF THE INVENTION The present invention relates to a high-speed PCI interface, more particularly to a high-speed PCI interface system with reset function and a reset method thereof. BACKGROUND OF THE INVENTION Since the electrical industry has changed with each passing day, the CPU and chipset are promoting upwards constantly that the transmission speed of the PCI interface is the choke point for the whole speed of the computer system. Now the high-speed PCI (PCI Express) is presented, thereof is having more advantages as fast high-performance bandwidth, advanced power management function, hot plug, point to point transmission and serious connection, which are adopted by user such that the manufacturer develops the related electronic product with the high-speed PCI interface. However, since the software and hardware of the computer system are powerful functions and fast speed, the stable operation thereof is the focus to the user, and every manufacturer strives toward. Usually while the user is operating the computer, which may meet the computer crash, for example: the high-speed PCI device falls into endless loop or be unable waked up from Suspend to RAM (STR) of the hibernate mode. Now, if the computer system adopts a high-speed PCI device with PCI Express interface, which sends a hot reset package to the unbounded high-speed PCI device that will be again restarting normal coupled with the computer system. Referring FIG. 1 that is shown of the electricity-coupled diagram of the system with high-speed PCI interface of the prior art. As shown in the figure, the system 10 comprises a north bridge 11 with at least one root port 111, at least one high-speed PCI device 13 and a south bridge 15. When turn on the power, the south bridge 15 can transmit a PCI resetting signal (PCI RST#) to a buffer 112 through a PCI reset signal line 151, and then the buffer 112 can transmit the PCI resetting signal to the high-speed PCI device 13 through a reset signal line 113 such that the system 10 will proceed an initializing action for the high-speed PCI device 13. After the system 10 is finished the initializing action, the user can normally operate the system 10. When the high-speed PCI device 13 fails to communicate with the north bridge 11 normally, the system 10 will adopt the root port 111 for transmitting a hot reset package to the high-speed PCI device 13 through a high-speed PCI bus 117, such that the high-speed PCI device 13 will proceed the initializing action to normally communicate with the north bridge 11 again. However, the high-speed PCI device 13 may not be able to execute the hot reset packet, the only way to reset the high-speed PCI device 13 is to turn off and on the power. In other word, the user wastes much effort but do nothing completely. SUMMARY OF THE INVENTION The present invention provides a high-speed PCI interface system with reset function, comprising: a host controller chipset, comprising at least one root port, used to generate a PCI resetting signal; at least one high-speed PCI device, each of said high-speed PCI devices respectively coupled to said corresponding root port within said host controller chipset through a high-speed PCI bus; and at least one reset signal generator, respectively corresponding with each of said root ports, each of said reset signal generators respectively electricity coupled to said host controller chipset through a PCI reset signal line and a trigger signal line, and electricity coupled to said corresponding high-speed PCI device according to a basic reset signal line; wherein, said reset signal generator for respectively receiving said PCI resetting signal and a triggering signal through said PCI resetting signal line and said trigger signal line, generating a basic resetting signal according to the operation of said PCI resetting signal and said triggering signal, sending said basic resetting signal to said corresponding high-speed PCI device through said basic reset signal line, and then commanding said high-speed PCI device to proceed a basic resetting action. The present invention also provides a reset method for using the high-speed PCI interface system, comprising the following steps of: a corresponding root port sending out a hot reset package to a high-speed PCI device for proceeding the hot resetting action through a corresponding high-speed PCI bus; determining whether said high-speed PCI device is ready, if so, then end; if not, then generating a basic resetting signal to said high-speed PCI device for proceeding a basic resetting action; and again determining whether said high-speed PCI device is ready, if so, then end; if not, then again generating a basic resetting signal to said high-speed PCI device for proceeding said basic resetting action, and forming a circulatory process. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the system with high-speed PCI interface of the prior art. FIG. 2 is a block diagram according to a preferred embodiment of the present invention. FIG. 3 is a block diagram according to another embodiment of the present invention. FIG. 4 is a block diagram according to another embodiment of the present invention. FIG. 5 is a timing diagram of each main signal of the present invention. FIG. 6 is a flowchart according to a preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 2, it is a block diagram according to a preferred embodiment of the present invention. As shown in the figure, the high-speed PCI interface system 20 of the present invention comprises a host controller chipset 27, at least one high-speed PCI device 23 (PCI Express) and at least one reset signal generator 29. Wherein, at least one root port 211 is placed within the host controller chipset 27, and each root port 211 is coupled to a corresponding high-speed PCI device 23. Each high-speed PCI device 23 is respectively coupled to the corresponding root port 211 within the host controller chipset 27 through a corresponding high-speed PCI bus 213. In the present embodiment, the numbers of the reset signal generator 29 are corresponding to the numbers of the root port 211, and the reset signal generator 29 and the host controller chipset 27 are separately placed within the motherboard (not shown). The host controller chipset 27 comprises the general-purpose output pin 255; the numbers of the general-purpose output pin 255 are corresponding to the numbers of the reset signal generator 29, each the general-purpose output pin 255 is respectively coupled to a corresponding input end of each reset signal generator 29 through a corresponding trigger signal line 257, and another input end of each reset signal generator 29 is simultaneously coupled to a PCI reset signal line 251. When the system starts, the host controller chipset 27 can transmit the PCI resetting signal (PCI RST#) to the input end of the reset signal generator 29 through the PCI reset signal line 251, and further the reset signal generator 29 operates to generate a basic resetting signal (PERST#), then which transmits to each high-speed PCI device 23 through the basic reset signal line 291, thus, the system can proceed the basic reset action while the system starting. Besides, some high-speed PCI device can't normal operating after the system starting and thereof executes the hot reset also invalid, the host controller chipset 27 can adopt the corresponding general-purpose output pin 255 to transmit a triggering signal to the reset signal generator 29 through the trigger signal line 257. Now, the reset signal generator 29 operates the triggering signal to generate a basic resetting signal (PERST#) that will be transmitted to the high-speed PCI device 23, which will proceed the basic resetting action, and then the high-speed PCI device 23 can restore the normal operating state. In the general computer system, the host controller chipset 27 can often design into the pattern that is consisted of a north bridge 21 and a south bridge 25. The root port 211 is directly placed within the north bridge 21 under the pattern, and the PCI resetting signal (PCI RST#) is transmitted from the south bridge 25 through the PCI reset signal line 251. In addition, each general-purpose output pin 255 is placed above the south bridge 25 and respectively coupled to the corresponding reset signal generator 29 through the corresponding triggering signal line 257. Reference to FIG. 3, there is shown of the electricity-coupled diagram of another embodiment of the present invention. As shown in the figure, the main structure is approximately the same as the embodiment of shown in FIG. 2. However, the structure of FIG. 3 comprises two high-speed PCI devices 33,34, two reset signal generators 38, 39 and two root ports 311,312 that are placed within the north bridge 31, electricity-coupled way of each corresponding component of the present embodiment and the above-mentioned embodiment are the same, no longer discussed here. Wherein, the reset signal generators 38, 39 are coupled in parallel and respectively coupled to south bridge 35 through a PCI reset signal line 351, therefore, those can simultaneously receive the PCI resetting signal that is outputted from the south bridge 35. The south bridge 35 comprises the general-purpose output pins 355, 356, and the numbers of the general-purpose output pins 355, 356 are corresponding to the numbers of the reset signal generators 38 and 39. Thus, the reset signal generators 38 and 39 can respectively one to one electricity-coupled to the corresponding general-purpose output pins 355 and 356 through a triggering signal lines 358 and 359. Moreover, the south bridge 35 can transmit a triggering signal to the corresponding reset signal generator 38 or 39 when any one of the high-speed PCI device 33, 34 happens the problem, the corresponding reset signal generator 38, 39 will transmit a basic resetting signal (PERST#) to the high-speed PCI device 33 or 34 that happens problem, so the high-speed PCI device 33 or 34 can operate the basic resetting action. Referring to FIG. 4, there is shown of the electricity-coupled diagram of another embodiment of the present invention. As shown in figure, besides the north bridge 41, the main structure of the high-speed PCI interface system 40 of the present embodiment is approximately the same as the embodiment of the FIG. 2. The difference thereof is directly integrated the reset signal generator 49 into the north bridge 41, and the high-speed PCI device 43 is coupled to the root port 411 within the high-speed PCI interface system 40 through a corresponding high-speed PCI bus 213. The reset signal generator 49 can receive the PCI reset signal (PCI RST#) from the south bridge 45 and the triggering signal that is outputted from the corresponding general-purpose output pin 455, and further the reset signal generator 49 generates a basic reset signal (PERST#) that will be transmitted to the corresponding high-speed PCI device 43 through the corresponding basic reset signal line 491 such that the high-speed PCI device 43 can be operate the basic resetting action. Therefore, that will help to reduce the circuit layout size of the high-speed PCI interface system 40 and reach the design idea as light, thin, short and small. Each reset signal generator (29, 38, 39 or 49) of the above-mentioned can be a and gate respectively, and each high-speed PCI device (23, 33, 34 or 43) is selected from one of a image processing chip, a sound processing chip, a bridge and a complex root port. Reference to FIG. 5, there is shown of the timing diagram of each main signal of the present invention. As shown in the figure, when the computer system turns on power to operate a starting procedure, besides, the power source leads in initial stage, thus each related circuit is in the unstable state during the T1 transient time. After T1 time end, the system will tend to steady during the T2 time, the system will first proceed the initialize action to each component, and then the south bridge will transmit out the PCI resetting signal. The PCI reset signal is the low voltage enable signal, such the PCI reset signal is in the low-level voltage state during the T2 time. Now, each triggering signal will be without function, and that is in the high-level voltage state. Each reset signal generator simultaneously receives two signals, further the digital logic (as or gate) within the reset signal generator operates to generate a basic resetting signal with low-level voltage, which will be transmitted to each high-speed PCI device, such that each high-speed PCI device can be used to operate the initialize action of the basic resetting according to the basic reset signal. The computer system can enter the normal operation state after all components are finished the initialize action. If some high-speed PCI device falls into endless loop after the following operating process, or can't be normal coupled to the north bridge in the other factor, or can't be unable waked up from STR mode. If the condition of the above-mentioned happens, the high-speed PCI device can adopt the technology of the present invention, that will transmit out a basic reset signal with low-level voltage from the corresponding general-purpose output pin above the south bridge, thus the corresponding reset signal generator can generate a basic reset signal with low-level voltage, as shown in the figure during T3 time. The above-mentioned technology can make the corresponding high-speed PCI device to proceed the basic reset action without restarting power, and then the high-speed PCI device can again normal coupled to the north bridge. Finally, referring to FIG. 6, there is shown of the flowchart of a reset method of a preferred embodiment of the present invention. As shown in the figure, the reset method of the present invention is used on the high-speed PCI device of the system no response or happened error. First, the reset method is proceeding the step 610 that is determining whether the high-speed PCI device exists. If not, it shows that the high-speed PCI device has been already removed and directly ended the reset procedure; if so, it continues to operate the step 620 and the follow up step thereof. Thus, when the high-speed PCI device is removed, the system can avoid always transmitting the command package to the high-speed PCI device in the ignorant condition. If the high-speed PCI device has been already existed actually, the step 610 isn't surely to operate, which can omit according to the condition. Then the step 620 is proceeding, which transmits a hot reset package to the high-speed PCI device through the corresponding high-speed PCI bus for proceeding the hot resetting action. Next the step 630 is proceeding that is determining whether the high-speed PCI device is ready through the root port. If so, it shown that the high-speed PCI device has been already normal coupled to the north bridge and directly ended the reset procedure; if not, the step 640 is proceeding, the south bridge generates a triggering signal from the corresponding general-purpose output pin through disposing in advance of a triggering mode that is selected from one software, firmware, hardware and the combination thereof, thus the triggering signal line will turn into the low-level voltage, and then a basic reset signal with low-level voltage will transmit to the high-speed PCI device after the reset signal generator operating such that the high-speed PCI device can proceed the basic resetting action. Therefore, the system can again generate a basic resetting signal for the high-speed PCI device to operate the initialize action without resetting power. After the basic resetting action is finished, the step 630 will be again detecting to form a circulatory process, which will stop until the high-speed PCI device can be normal coupled to the north bridge. The present technique not only retains the data that is generated by the previously work but also ensures the normal operating for the high-speed PCI device. In summary, it is appreciated that the present invention relates to a high-speed PCI interface system with reset function and a reset method thereof, that adopts a reset signal generator to generate a basic resetting signal, and which directly transmits to the corresponding high-speed PCI device such that the system can be used to operate the basic resetting action without restarting power. The foregoing description is merely one embodiment of present invention and not considered as restrictive. All equivalent variations and modifications in process, method, feature, and spirit in accordance with the appended claims may be made without in any way from the scope of the invention.	G	60G06	161G06F	13	42
11671001	US20080126431A1-20080529	Method and Device for Data Backup	ACCEPTED	20080514	20080529	[]	G06F1730	["G06F1730", "G06F1200"]	7822725	20070205	20101026	707	698000	98964.0	BIBBEE	JARED	[{"inventor_name_last": "Walliser", "inventor_name_first": "Stefan", "inventor_city": "Zimmern o.R.", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Haug", "inventor_name_first": "Oliver", "inventor_city": "Rottweil", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Jiao", "inventor_name_first": "Yu", "inventor_city": "Villingen-Schwenningen", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Volk", "inventor_name_first": "Dejan", "inventor_city": "Rence", "inventor_state": "", "inventor_country": "SI"}, {"inventor_name_last": "Beltram", "inventor_name_first": "Tomaz", "inventor_city": "Nova Gorica", "inventor_state": "", "inventor_country": "SI"}, {"inventor_name_last": "Rejc", "inventor_name_first": "Dario", "inventor_city": "Ljubljana", "inventor_state": "", "inventor_country": "SI"}, {"inventor_name_last": "Lautar", "inventor_name_first": "Igor", "inventor_city": "Trse", "inventor_state": "", "inventor_country": "HR"}]	A method for storing data with a first storage system and a second storage system, wherein the second storage system is used for backing up the data from the first storage system, wherein the first storage system comprises a file system on which the data that is to be backed up is stored, with a client that monitors the first storage system, and a server that administers the second storage system, with the method comprising the following steps: checking the files on the first storage system for any changes by the client, depending on one or several events; if changes have been detected, determining a hash value in relation to the file, which hash value is structured such that the identity of the file can be determined, transmitting the hash value to the server, checking, by means of the hash value, by the server as to whether the identical file is stored on the second storage system, and if the file already exists, the file is not requested, but an annotation is made to the effect that the file is stored on the first storage system, and if the file does not exist, requesting the entire file, or parts of the file that have changed, from the first storage system, and storing the file on the second storage system, with an annotation relating to the first storage system.	1. A method for storing data, with a first storage system and a second storage system, wherein the second storage system is used for backing up the data from the first storage system, wherein the first storage system comprises a file system on which the data that is to be backed up is stored, with a client that monitors the first storage system, and a server that administers the second storage system, with the method comprising the following steps: checking the files on the first storage system for any changes by the client, depending on one or several events; if changes have been detected, determining a hash value in relation to the file, which hash value is structured such that the identity of the file can be determined, transmitting the hash value to the server, checking, by means of the hash value, by the server as to whether the identical file is stored on the second storage system, and if the file already exists, the file is not requested, but an annotation is made to the effect that the file is stored on the first storage system, and if the file does not exist, requesting the entire file, or parts of the file that have changed, from the first storage system, and storing the file on the second storage system, with an annotation relating to the first storage system. 2. The method according to claim 1, wherein the server comprises a database in which the hash values are stored such that a relation to the first storage system and to the file on the second storage system can be established. 3. The method according to claim 2, wherein in addition the position of the file in the file system is stored on the first storage system. 4. The method according to claim 1, wherein the hash is an SHA1 hash. 5. The method according to claim 1, wherein the hash is structured such that by means of the hash value it can be detected which parts, preferably blocks or regions, of the file have changed, so that only those parts that have changed are transmitted, and on the server this file is reconstituted by means of the existing file. 6. The method according to claim 1, wherein the hash value is expanded so that the allocation to a volume on the second storage system is evident from the hash value. 7. The method according to claim 1, wherein the second storage system has been designed so as to be redundant, and the data is stored at least in duplicate. 8. The method according to claim 7, wherein the storage system is set up hierarchically so that the data automatically migrates from one hierarchical level to the next. 9. The method according to claim 7, wherein hard disk systems and tape systems are used. 10. The method according to claim 7, wherein there are at least two independent hard disk systems, each of which is designed so as to be redundant. 11. The method according to claim 9, wherein there are at least two tape drives, which keep the data on different tapes as copies. 12. The method according to claim 10, wherein during storing and loading, by means of the hash value a check is made as to whether the data is correct. 13. The method according to claim 1, wherein for a backup a first time window for the storage period can be determined, and the server keeps the data for such a period of time as determined by the first time window. 14. The method according to claim 1, wherein for archival a second time window can be determined, and the server keeps the data for such a period of time as determined by the second time window. 15. The method according to claim 1, wherein criteria can be determined that selectively determine files or exclude files that are to be backed up or archived. 16. The method according to claim 1, wherein the server provides a web surface, by way of which a user can select files that are to be restored. 17. The method according to claim 1, wherein the server provides a NAS or an iSCSI system on the second storage system. 18. The method according to claim 1, wherein the client, using FindFirstChangeNotification by Microsoft®, monitors the files on the first storage system for changes. 19. The method according to claim 1, wherein the client at predeterminable intervals checks the files for any changes in order to then notify the server of such changes. 20. The method according to claim 1, wherein the client receives a message from the operating system to the effect that a file has been changed, so that subsequently a hash value can be calculated, which hash value is transmitted to the server. 21. A method for the backup or archival of e-mails that are stored on a first storage system, comprising a server that administers a second storage system on which the e-mails are to be backed up and/or archived, comprising a client that has access to the e-mails, involving the following steps: on the basis of a predetermined event, the client calculates a hash value for the e-mails; the hash value is transmitted to the server by the client; the server checks whether an e-mail with the same hash value already exists; if this is not the case the e-mail is requested by the client; otherwise the server makes an entry to the effect that the e-mail has been sent to a further recipient; the client sends a copy of the requested e-mail; the server stores the received e-mail on the second storage system in relation to a recipient. 22. The method according to claim 21, wherein hash values are specially calculated for the e-mail attachments so that the server can determine whether the attachment has already been backed up, so as to then only generate a reference to the attachment in relation to the e-mail, or to back up only the attachment or only the e-mail without attachment if said e-mail is not yet stored on the second storage system. 23. The method according to claim 21, wherein the client accesses the e-mails by way of an API of the mail server or by way of an API of the mail client. 24. The method according to claim 23, wherein the client accesses the e-mails by way of one or several of the following interfaces: journaling mailbox, MAPI, POP, IMAP. 25. The method according to claim 21, wherein the server comprises a database in which the hash values are stored such that a relation to the recipient of the e-mail can be established on the second storage system. 26. The method according to claim 21, wherein the hash is an SHA1 hash. 27. The method according to claim 21 wherein the hash value is expanded so that any allocation to a volume on the second storage system is evident from the hash value. 28. A method for the safe transfer of data in a hierarchical storage system, with the storage system comprising storage devices of different speeds, wherein the data automatically migrates from one hierarchy to another according to predeterminable criteria, comprising the following steps: generating a first hash value for the data, from which hash value the identity of the data can be established prior to migration; checking the integrity of the data after migration by reading the data and generating a second hash value so that it can be compared with the first hash value; and if the hash values do not agree, renewed copying of the data. 29. The method according to the claim 28, wherein the hash value is stored in a database so that fast access is made possible, wherein the database is preferably stored so as to be redundant. 30. The method according to the claim 28, wherein the data relates to files or e-mails. 31. The method according to the claim 28, wherein during storing and loading, checks are made, by means of the hash value, as to whether the data is correct. 32. The method according to the claim 28, wherein the hash is an SHA1 hash. 33. A client system that monitors a first storage system that accesses a network interface in order to transmit data to a server with a second storage system, wherein the second storage system is used for backing up the data of the first storage system, wherein the first storage system comprises a file system on which files are stored that are to be backed up, or is used to store e-mails, wherein the client comprises a processing unit for checking files, or a processing unit for checking e-mails, which processing unit checks whether any files or e-mails on the first storage system have been changed, comprising: a processing unit for generating hash values, which processing unit if any changes are detected generates a hash value in relation to the file or e-mail, which hash value is structured such that the identity of the file or e-mail can be determined; a communication unit which transmits the hash value to the server, which server checks whether a file or e-mail with a corresponding hash value is already stored on the second storage system, and, if the file or e-mail is not yet stored on the second storage system, sends the complete file or e-mail or parts thereof to the server. 34. The client system according to the claim 33, wherein the processing unit for the purpose of generating a hash value generates an SHA1-hash. 35. The client system according to claim 33, wherein the processing unit for hash-value generation creates the hash such that by means of the hash value it can be detected which parts, in particular blocks, of the file have changed, so that only those parts that have changed are transmitted, and on the server this file is reconstituted by means of the existing file. 36. The client system according to claim 33, wherein the processing unit for generating the hash value expands the hash value so that any allocation to a volume on the second storage system is evident from the hash value. 37. The client system according to claim 33, wherein the processing unit is designed to generate hash values in order to monitor e-mails of a mail server by a client, and calculate hash values for the mails that are transmitted to the server so that the server can determine which e-mails are to be transmitted as copies. 38. The client system according to the preceding claim 36, wherein the processing unit for generating hash values calculates hash values only for the e-mail attachments so that the server can determine whether the attachment has already been backed up, in order to then only generate a reference to the attachment. 39. The client system according to claim 33, wherein criteria can be determined that selectively determine files or exclude files that are to be checked for changes. 40. The client system according to claim 33, wherein the client by means of FindFirstChangeNotification by Microsoft® monitors the data on the first storage system for any changes. 41. The client system according to claim 33, wherein the client in predeterminable intervals examines the files for any changes, in order to then notify the server of such changes. 42. The client system according to claim 33, wherein the client receives a message from the operating system to the effect that a file has been changed, so that subsequently a hash value can be calculated that is transmitted to the server. 43. A server system for storing data from a client with a first storage system, wherein the server system administers a second storage system, wherein the second storage system is used for backing up the data from the first storage system, wherein the first storage system comprises a file system or a mail system on which files or e-mails are stored that are to be backed up, comprising a database in which unambiguous hash values of files or e-mails are stored that are stored on the first storage system, and whose copies are stored on the second storage system, wherein the database in relation to each hash value stores the location of storage or the e-mail addressee on one or several of the first storage systems, and stores the place of storage on the second storage system, wherein a file or an e-mail or parts of a file are only requested by the client and stored on the second storage system if the hash value is not yet present in the database. 44. The server system according to claim 43, wherein the hash is an SHA1 hash. 45. The server system according to claim 43, wherein the hash is structured such that by means of the hash value it can be detected which blocks of the file have changed, so that only those blocks that have changed are requested by the server, and on the server this file is reconstituted by means of the existing file. 46. The server system according to claim 43, wherein the hash value is expanded so that an allocation to a volume on the second storage system is evident from the hash value. 47. The server system according to claim 43, wherein the second storage system has been designed so as to be redundant, and the data is backed up at least in duplicate. 48. The server system according to claim 47, wherein the storage system is set up hierarchically so that the data automatically migrates from one hierarchical level to the next. 49. The server system according to claim 47, wherein hard disk systems and tape systems are used. 50. The server system according to claim 47, wherein there are at least two independent hard disk systems that are designed so as to be redundant. 51. The server system according to claim 47, wherein there are at least two tape drives, which keep the data on different tapes as copies. 52. The server system according to claim 50, wherein during storing and loading, by means of the hash value a check is made as to whether the data is correct. 53. The server system according to claim 51, wherein the e-mails of a mail server are copied to the second storage system on the basis of the hash value. 54. The server system according to claim 53, wherein hash values are only calculated in relation to the e-mail attachments, so that it can be determined whether the attachment has already been backed up, in order to then only generate a reference to the attachment. 55. The server system according to claim 54, wherein for backup a first time window for the storage can be determined, and the server keeps the data for such a period of time as determined by the first time window. 56. The server system according to claim 43, wherein for archival a second time window can be determined, and the server keeps the data for such a period of time as determined by the second time window. 57. The server system according to claim 43, wherein criteria can be determined that selectively determine files or exclude files that are to be backed up or archived. 58. The server system according to claim 43, wherein a web surface is provided by way of which a user can select files that are to be restored. 59. The server system according to claim 43, wherein a NAS or an iSCSI system is provided on the second storage system. 60. A hierarchical storage system comprising storage devices of different speeds, which storage devices are arranged in a hierarchy, wherein data automatically migrates between the hierarchies according to predeterminable criteria, comprising the following components: means for generating a first hash value for data, from which hash value the identity of the data is determinable prior to migration; means for checking the integrity of the data after migration by reading the data and generating a second hash value so that it can be compared with the first hash value; and if the hash values do not agree, the means undertake renewed copying of the data. 61. The device according to the preceding claim 60, wherein the hash value is stored in a database so that fast access is made possible, wherein the database is preferably stored so as to be redundant. 62. The device according to claim 60, wherein the data relates to files or e-mails. 63. The device according to claim 60, wherein means are provided which during storing and loading, check the hash value, as to whether the data is correct. 64. The device according to claim 60, wherein the hash is an SHA1 hash. 65. A data carrier with a data structure that is designed such that, when it is loaded by a computer, it implements a method according to the preceding method-related claim 1.	<SOH> FIELD OF THE INVENTION <EOH>The present invention generally relates to a storage system, in particular to a backup- and archival system, which makes it possible to autonomously store and archive data from a multitude of computers and servers (clients). With increased frequency, ecological, political and social aspects of life are administered by way of digital data. Thus, transactions and the prosperity of our society are often generated on the basis of digital information. The quantity of data that has to be administered in the form of computer programs or databases is increasing exponentially. As a result of the increase in the performance of computers and operating systems, applications are becoming larger and larger. Furthermore, there is a desire to have permanent access to large databases, for example multimedia data bases or large files. The growth rate of data resulting from increased file sizes and multiple storage of identical files makes it necessary to back up and administer such files efficiently. Due to the fact that an ever increasing number of data storage devices have to be used, there is continuous pressure on suppliers of storage solutions to reduce the costs of storage systems. Furthermore, data management systems should be scalable. They should not merely be in a position to handle current demand but also any expected future demand. Preferably, storage systems are incrementally scalable so that users can acquire the additional capacity whenever it is required at a corresponding point in time. Moreover, excellent availability and excellent reliability are important aspects because users do not accept data loss or data damage. Furthermore, legal requirements in relation to the archival of data are becoming increasingly more stringent. Archival periods, data integrity, inalterability, data protection guidelines and access authority are increasingly prescribed in regulations and laws. For example, a multitude of documents have to be archived, at times in excess of 10 years, and administered so as to be secure against falsification in order to be able to provide proof of the existence and integrity of these documents. Known storage systems that operate on the basis of hard disks often comprise a number of hard disks that are designed so as to be redundant (RAID: Redundant Array of Independent Disks). However, these systems are permanently online, they consume a considerable amount of electricity and are only of limited suitability for archival because data stored on these systems can be altered many times. These RAIDs often comprise RAID levels 1, 3, 5, 10 or 6 so as to prevent data loss. Furthermore, they comprise several controllers so that there is no single point of failure. Servers can be connected to these RAID systems, with such connection being implemented e.g. by way of TCP/IP/iSCSI (internet Small Computer System Interface), Fibre Channel or SCSI. Individual systems also provide the data via NAS (Network Attached Storage). However, for data backup, tape drives are used which store the data on tapes. Such tape drives can also be installed in robots that transport the tapes to the individual tape drives. Essentially there are standard formats in the context of such tape drives, for example DDS, SDLT, LTO, AIT and SAIT. Other standards are also imaginable. Known systems utilise backup- and archival programs that request data at regular intervals from the computers, and store such data on tapes. There is a central backup- and archival server which requests the data from the computers at regular intervals in order to make a backup of this data. Often however, data backup takes place every 24 hours so that a large part of the data is lost if the computer or the storage system crashes within this period of time. Furthermore, such backup software provides limited options for archiving data permanently and in a way that it cannot be altered. U.S. Pat. No. 6,704,730, U.S. Pat. No. 6,810,398, U.S. Pat. No. 6,826,711 and U.S. Pat. No. 7,000,143 disclose storage systems and attempted solutions which are within the scope of the invention. FalconStor Software (falconstor.com), Quantum (quantum.com), Rocksoft, Sepaton (sepaton.com), DeltaStor, Diligent Technologies (diligent.com) with ProtectTIER VTL software, and Avamar Technologies (avamar.com) are providers of storage solutions in this field.	<SOH> BRIEF DESCRIPTION OF THE FIGURES <EOH>Below, the figures to which the detailed description refers are described in brief. FIG. 1 : shows a network with a central switch to which a number of PCs are connected, which by way of this switch are connected to the backup system on which the server runs; FIG. 2 : shows a network with a central switch to which a number of PCs are connected, which by way of this switch are connected to the backup system, with a structure of the central database (CAS); FIG. 3 : shows a network to which a number of PCs are connected, which by way of the aforesaid are connected to the backup system, wherein only parts of the files are transmitted; FIG. 4 : shows a flow chart for checking the hash values; FIG. 5 : shows a flow chart for checking the hash values after renewed downloading of data. detailed-description description="Detailed Description" end="lead"?	FIELD OF THE INVENTION The present invention generally relates to a storage system, in particular to a backup- and archival system, which makes it possible to autonomously store and archive data from a multitude of computers and servers (clients). With increased frequency, ecological, political and social aspects of life are administered by way of digital data. Thus, transactions and the prosperity of our society are often generated on the basis of digital information. The quantity of data that has to be administered in the form of computer programs or databases is increasing exponentially. As a result of the increase in the performance of computers and operating systems, applications are becoming larger and larger. Furthermore, there is a desire to have permanent access to large databases, for example multimedia data bases or large files. The growth rate of data resulting from increased file sizes and multiple storage of identical files makes it necessary to back up and administer such files efficiently. Due to the fact that an ever increasing number of data storage devices have to be used, there is continuous pressure on suppliers of storage solutions to reduce the costs of storage systems. Furthermore, data management systems should be scalable. They should not merely be in a position to handle current demand but also any expected future demand. Preferably, storage systems are incrementally scalable so that users can acquire the additional capacity whenever it is required at a corresponding point in time. Moreover, excellent availability and excellent reliability are important aspects because users do not accept data loss or data damage. Furthermore, legal requirements in relation to the archival of data are becoming increasingly more stringent. Archival periods, data integrity, inalterability, data protection guidelines and access authority are increasingly prescribed in regulations and laws. For example, a multitude of documents have to be archived, at times in excess of 10 years, and administered so as to be secure against falsification in order to be able to provide proof of the existence and integrity of these documents. Known storage systems that operate on the basis of hard disks often comprise a number of hard disks that are designed so as to be redundant (RAID: Redundant Array of Independent Disks). However, these systems are permanently online, they consume a considerable amount of electricity and are only of limited suitability for archival because data stored on these systems can be altered many times. These RAIDs often comprise RAID levels 1, 3, 5, 10 or 6 so as to prevent data loss. Furthermore, they comprise several controllers so that there is no single point of failure. Servers can be connected to these RAID systems, with such connection being implemented e.g. by way of TCP/IP/iSCSI (internet Small Computer System Interface), Fibre Channel or SCSI. Individual systems also provide the data via NAS (Network Attached Storage). However, for data backup, tape drives are used which store the data on tapes. Such tape drives can also be installed in robots that transport the tapes to the individual tape drives. Essentially there are standard formats in the context of such tape drives, for example DDS, SDLT, LTO, AIT and SAIT. Other standards are also imaginable. Known systems utilise backup- and archival programs that request data at regular intervals from the computers, and store such data on tapes. There is a central backup- and archival server which requests the data from the computers at regular intervals in order to make a backup of this data. Often however, data backup takes place every 24 hours so that a large part of the data is lost if the computer or the storage system crashes within this period of time. Furthermore, such backup software provides limited options for archiving data permanently and in a way that it cannot be altered. U.S. Pat. No. 6,704,730, U.S. Pat. No. 6,810,398, U.S. Pat. No. 6,826,711 and U.S. Pat. No. 7,000,143 disclose storage systems and attempted solutions which are within the scope of the invention. FalconStor Software (falconstor.com), Quantum (quantum.com), Rocksoft, Sepaton (sepaton.com), DeltaStor, Diligent Technologies (diligent.com) with ProtectTIER VTL software, and Avamar Technologies (avamar.com) are providers of storage solutions in this field. OVERVIEW OF THE INVENTION It is the object of the present invention to provide a backup system which makes it possible at the shortest possible intervals to send data to a central storage location so that even users that use a mobile computer, e.g. a laptop, PDA or similar, back up all the data, even if these users work on the computer only for a short time. Furthermore, the quantity of data transferred is to be reduced. It should be noted that the invention is not limited to mobile computers. All types of computers that are connected to a network can be taken into account in the backup. This object is met by an invention with the characteristics of the independent claims. A preferred exemplary embodiment relates to a method for storing data with a first storage system and a second storage system, wherein the second storage system is used for backing up the data from the first storage system. The first storage system can be a PC, a special server such as e.g. an email server or a server hard disk/flash memory whose data is to be backed up. The data is stored as files in a file system. The first system comprises a client/agent which monitors the file system/s. Preferably, this client/agent is a software program. In a preferred embodiment, said client/agent is based on the Microsoft FindFirstChangeNotification® solution, which forms part of Microsoft Directory Management®, and which reports to the controlling client software of the present invention. A server is installed on a second system, which server administers the second storage system. As a rule, the server is software that runs on a computer with an operating system. The server administers the storage of the backed-up data on the second storage system. The second storage system is a hard disk RAID (flash RAID), preferably in combination with tape drives. These components are arranged hierarchically so that data migration can take place. The method comprises the following steps: The client checks the data and preferably the file system on the first storage system for any changes. This includes, in particular but not exclusively, any addition of new data and any change in already existing files and data records. This can occur at regular intervals or in an event-controlled manner (e.g. interrupt by the operating system, which provides notification if files have been changed). If changes have been detected, a hash value in relation to the file is calculated, with the hash value being designed such that the identity of the file can be established. A change in the file can be determined by a change date or by filters or events provided by the operating system. The above are, for example, based on Microsoft FindFirstChangeNotification®, which forms part of Microsoft Directory Management®. Of course it is also imaginable that the change is notified by the hardware. The hash value is structured such that the identity of a file can be determined. In other words, the hash value is identical if the file is identical. In cases where changes to the file have been made, the hash value also changes. After the hash value has been determined it is transmitted to the server, which receives the hash value. As a rule, transmission is by way of a network, such as a LAN or WLAN. By means of the hash value, the server checks whether a corresponding copy of the file is already stored on the second storage system, because in a network there are often duplicates of files. Should this be the case, the server does not request the file anew, but instead establishes on the second storage system a further reference relating to the storage location of the file, as well as an entry which regulates access authorisation. In this process the first storage system is not changed. In concrete terms this means that the reference comprises on the one hand the identity of the client or of the computer and its hard disk, and on the other hand a possible volume and the storage place within the file system that has been established on the volume. In a preferred embodiment the server comprises a fast database (CAS), by means of which it is possible for said server to quickly access the hash values in order to determine whether or not these hash values have already been stored. Furthermore, in this database a reference to the file is stored on one or several client systems. Furthermore, access restrictions within the database can be stored. These access restrictions can also be obtained by way of an interface to the active directory of Windows. Other directory services such as LDAP are of course also imaginable. The invention achieves a situation where the volume of traffic on the network is very small, and where if at all possible each file is stored only once on the second storage system (this does not take into account the redundancy of the second storage system). Explicitly, first of all only hash values are transferred by way of the network; and only in cases where data records and files have not yet been stored on the second storage system are these data records and files transferred once only over the network. In this way duplication and multiple storage of files can be prevented, and the use of the storage space on the second storage system can be optimised. Despite all this, the database makes it possible to make the files available individually to all the systems although the file has physically been stored only once. If a check shows that the hash value does not exist, i.e. that the file is not yet present, then the server requests from the client system the entire file or parts of the file that have changed when compared to a previous file. Thereafter the file is stored on the second storage system, and the necessary information is supplied to the database. In contrast to this, if only part of the file has been transmitted, then either this part is completely reconstructed and stored on the second storage system, or only the changed parts are stored with a reference to the original complete file. However, it is also imaginable that a multitude of references exist, each reference reflecting different file versions in which at various points in time various changes have been made. If a file is to be restored, the server system then reconstructs the desired file in that all the changes are effected in sequence. First the original file is loaded, followed by the respective changes that were effected sequentially, which changes are then to be applied to the original file. Determining the changes or the parts that have been changed can on the one hand be effected by means of the hash value, or on the other hand by the client, which locally calculates the changes of the file on the basis of the original file. In this process the hash value is preferably structured such that it is always prepared for a defined number of bytes of a file (e.g. 1,000 bytes) so as to subsequently compose the total hash value from these individual hash values. In this way it is possible to determine which of the 1,000 byte blocks have changed. Alternative ways of calculating the changes are also imaginable and can be used. In a preferred embodiment only those blocks of the file are transmitted that have changed. In an alternative embodiment, calculation of the change is undertaken by the server. Said server analyses the files and their predecessor versions and calculates the delta. Only the delta is then stored on the second storage system, together with a rule as to how this file is to be reconstituted. While in this way the entire file is transmitted by way of the network, it is, however, ensured that only the changes are stored on the server. In a possible embodiment the hash value is stored such that an unambiguous relation to the clients and to the file on the second storage system can be established. In this process the path is stored on the file system in relation. Furthermore, the access authorisation is stored. In the preferred embodiment the hash is an HSA1 hash based on 256 bits. The calculation method of this manufacturer is likely to be known. Information relating to the literature is provided below. Preferably, the hash value is structured such that by means of the hash value it can be detected which blocks or regions of the file have changed, so that only those blocks that have changed are transmitted, and on the server this file is reconstituted by means of the existing file. Reconstitution can take place directly so that the part is completely stored on the second storage system, or it can be reconstituted only when a restoration copy has been requested. Details relating to this have already been described. In a alternative embodiment the hash value is composed of several individual hash values. Thus the first part of the hash value can determine the first 10 MB of a file; the second part 10-90 MB, and the third part everything above it. It is, of course, also possible to have a finer gradation. In a further alternative embodiment the hash value is expanded so that an allocation to a volume on the second storage system is evident from the hash value. Often, a storage system comprises a multitude of logically separate volumes that extend over one or several storage systems. In Microsoft operating systems, such volumes are, for example, designated by a letter. In Unix operating systems or Linux operating systems these volumes can be accessed by way of a path. In order to ensure the highest possible data protection, the second storage system is set up so as to be redundant. Preferably, the storage system is even set up to provide multiple redundancy, as will be described below. In this arrangement hierarchical storage models are taken into consideration. In hierarchical storage models the fastest and highest-quality storage devices are at the highest positions. These storage devices are fast hard disk systems with Fibre Channel, SCSI or SAS interfaces and fast rotary speeds (10,000 r/min and above). It is also imaginable that in future faster flash memories, holographic storage devices or optical storage technologies will assume this role. At present there is a trend towards combined systems with a hard disk and a flash memory so that it can be expected that in the long term the hard disk in its current form will play a lesser role. These fast and durable storage discs can be interconnected as RAIDs. This ensures high speeds and safe data keeping at the first level of the second storage system. A copy of the data is kept on a second storage region, which is somewhat slower, as part of the second storage system. This can be a SATA storage system or a storage system with lesser access times and with lesser rotary speeds. Permanent synchronisation takes place between these two hard disk systems so that data redundancy is provided: redundancy on the one hand as a result of the hard disk RAIDS on each hierarchical level, and on the other hand redundancy as a result of the use of two hard disk systems that are arranged parallel to each other and that are mirrored. In the next hierarchical level a tape robot is arranged, which preferably but not mandatorily, comprises at least two tape drives, each of which writes data to two tapes in copy. This ensures that the data on the tapes is always present in duplicate independently of the other data. In future, tape technology might also be replaced by some other technology, such as e.g. flash memories, holographic storage devices or optical storage technologies. As soon as the data is redundantly stored on the last hierarchical level it can be deleted, based on settable rules, from the higher-performing and more expensive storage levels so as to clear space thereon for new data. In this arrangement there is an automatic distinction between active and inactive data after the data has been classified. By means of the tape system, which then also keeps the data in duplicate, the above-described data redundancy is obtained even if the data has been deleted from the technology components that rank higher in the hierarchy. During data migration from one hierarchy to the next, an integrity check is carried out on the basis of the hash values. After the file has been written, or after the data to be shifted has been read, the hash value is generated and compared to the hash value stored in the database. If in this process any changes are detected, the copying process is to be carried out anew, or the data is to be loaded from another medium. In a further exemplary embodiment, further duplicates of the tapes can be made, if desired, in order to store a copy of the data at an external location. The system that administers the second storage system is advised that a copy of all archived data is to be made. The tape robot asks the user to provide corresponding tapes onto which a copy of all data is then made and issued. In this arrangement it would also be possible to access an export function with integrated conversion to standard formats, e.g. .pdf data records. Migration of data takes place automatically and can be predetermined in relation to time thresholds or data volumes. The alternative embodiment in addition comprises an archival function in the system, which archival function meets legal requirements and does not allow any change in the data after writing. To this effect, for example, a special tape medium can be used such as the WORM (Write Once Read Multiple) medium. Furthermore, it is imaginable that the data is given a signature that is obtained from a public-key infrastructure (PKI) system. General data verification can also take place by way of the implemented and already described HSA-1 calculation. The detailed process of archival is subject to standard processes which hereinafter are not described in more detail because they are well known to the average person skilled in the art. However, the device ensures that the archived data cannot be changed. The system further provides an option, by way of a user interface, to determine the types of files to be archived and the positions of the first storage system in which positions the files are stored. In this way a user can determine which files are to be backed up, which files are to be archived, and which files are to be indexed for the purpose of a contents search. In order to ensure that data is not damaged during migration between the individual hierarchical levels, the hash values are used to verify the data after it has been copied to the new storage medium or the new hierarchical level. By means of the signature key it is also possible to check that the data has not been changed. This ensures that data integrity and consistency are maintained across all hierarchical levels. Prior to data transmission, the hashes are calculated from the first storage system, stored in a database in the server, and recalculated after the data has been stored in the second storage system. The two values are compared to each other, and data integrity and consistency can thus be ensured. The same process is carried out once more when data is copied and migrated within the storage hierarchy of the second storage system. In a further embodiment, the invention is extended to cover e-mail traffic. In the alternative embodiment the MS ExchangeServer by Microsoft® is supported (however, other mail systems are imaginable). Access to its e-mails is by a predetermined interface, for example the MAPI interface, with data backup and archival of the e-mail being carried out according to the same principle as with files. However, there is a significant difference in that the hash value is not applied to the entire file or e-mail (but separately, in addition, also to its attachments) but instead in each case separately to the e-mail itself and to its attachments. This is because it is often the case that a multitude of identical attachments are located in a mail server, so that their storage entails an enormous overload of the system. Within a mail group, attachments are frequently sent to many participants so that said attachments are held in duplicate or multiple times by users. In order to avoid large storage requirements and increased network load during backup or archival, only those attachments are stored on the second storage system which have previously not been able to be identified by means of the calculated hash values. In relation to this attachment, an annotation/pointer is then made in the database, stating that said attachment belongs to a specific e-mail. Consequently, in relation to a hash value it is possible to reference not only one file to a file system, but also a file within one or several e-mails. This approach can be taken on the one hand by a client which runs on the mail server and accesses the entire mail traffic by way of an interface of the mail server, or on the other hand by a client which runs on the client computers on which a mail client (e.g. Outlook) is installed so as to access all mails by way of an interface of Outlook (or IMAP, POP, MAPI etc.). In this way, for the purpose of monitoring mail traffic, on each client that administers or comprises a mail client, monitoring can take place locally in order to then communicate with the server and in order to transmit the e-mails and their attachments if applicable. In the alternative exemplary embodiment with respect to an exchange server, the access to the journaling mailbox is given by way of a corresponding API. The hash value is calculated (for the mail itself and if applicable for its attachments). If the mail has not yet been backed up, it is indexed for a full-text search and is then copied to the second storage system with a respective reference and access authorisation. The journaling mailbox thus temporarily makes the e-mails available for processing. After a predeterminable period of time the e-mails will then be deleted. However, in parallel to the above, the e-mails have already been transmitted to the recipient. This approach can be further developed for other storage systems such as databases. It is understood that considering the exchange server should not result in any limitations relating to the applicability of this method. Mail servers by IBM®, such as Lotus Notes® or a host of e-mail servers in the Unix® and Linux® fields can also be covered by this approach. With these systems, too, on the basis of the stored information a search takes place to check whether there are files that are present multiple times so that multiple storage is avoided. There are also database structures (BLOBs, Binary Large Objects) that accommodate entire files. For these data structures the avoidance of duplicates would be of interest. Single instancing can thus also be practised for mails and furthermore between all the described applications. Thus application-spanning single instancing is implemented so that for example backup, archive and NAS (Network Attached Storage) access the same physical data level. This approach can also be considered for Fibre Channel systems, iSCSI systems and document management systems. In an alternative embodiment such monitoring is carried out regularly at 30-minute intervals. Of course other intervals, which can be set, are also imaginable. This decisively depends on the daily generated data volume and thus on the load on the computer systems. Basically, the invention makes it possible to specify the interval at which, and the extent to which, data is to be backed up and archived. It is imaginable for a file to be monitored every 30 minutes on the first storage system and to back it up if required. Shorter intervals are also imaginable. Furthermore, the length of time this data or these files are to be kept for a total backup can be specified. For example it can be ensured that the data is to be kept on the first storage system for 3 months. For archival it can for example be specified that the data is to be archived for 10 years. Furthermore, selection criteria can be determined that selectively determine or exclude files that are to be backed up or archived, or that are not to be backed up. This can take place by way of selection patterns with placeholders, or by way of other selection criteria that are determined via a graphic user interface. Furthte a Classification of the data takes place so that a differentiation between active and inactive data can be made, so that the data is on different levels of the HSM, depending on the classification (access frequency, last modification, creation date). This user interface can be addressed by way of a web browser, like a web server. Alternatives by way of software administration clients are of course also imaginable. In order to make it possible to restore files without having to contact the administrator, the server comprises a web server that makes it possible, by way of an input mask, to state selection criteria that are used to determine the files that are to be restored. This can take place either by direct input of the file name or by navigation within a file system in the form of a tree. Access to a file is, of course, limited by way of an authorisation check so that not all available files can be restored by each user, but only those files for which a given user has authorisation. Authorisation can be obtained either by the authorisation system of Microsoft (active directory), or by entering user name and password that are based on the systems own authorisation system. In addition, the server can be integrated by iSCSI or TCP/IP as network-attached storage, NAS (file share) so that said server is not only used for data backup, but in addition also for the provision of storage space in the network. To users it is then not evident that in each case they are dealing with a special backup system. Instead, the characteristic of the operating system that is used on the server system is used to provide further services for the users in the network. A Windows Storage Server® is used, as the alternative operating system, on the backup server which administers the second storage system. This operating system provides the described interfaces and services. It is also imaginable to use some other operating system such as Linux or Unix. Further components of the invention include the monitoring of the mail traffic, the integrity of the files in a hierarchical storage system, and the design of the client, which as a rule runs as software on a PC or computer, or the server itself, which as a rule is implemented as software, or is a combination of software and hardware and is installed on a server that administers several RAID systems. In this case the server in turn is connected to a backup system or to a tape library by way of Fibre Channel, iSCSI or SCSI. BRIEF DESCRIPTION OF THE FIGURES Below, the figures to which the detailed description refers are described in brief. FIG. 1: shows a network with a central switch to which a number of PCs are connected, which by way of this switch are connected to the backup system on which the server runs; FIG. 2: shows a network with a central switch to which a number of PCs are connected, which by way of this switch are connected to the backup system, with a structure of the central database (CAS); FIG. 3: shows a network to which a number of PCs are connected, which by way of the aforesaid are connected to the backup system, wherein only parts of the files are transmitted; FIG. 4: shows a flow chart for checking the hash values; FIG. 5: shows a flow chart for checking the hash values after renewed downloading of data. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 shows a central switch 1 to which a number of workstations A, B, C and D are connected, which in turn have their data stored on file servers 2, 3. Furthermore, a mail server 4 is connected to the network. The device 5 according to the invention is also integrated in the network. On the individual work stations A, B, C and D as well as on the servers 2, 3, 4 the client runs, while the server runs on the device 5 according to the invention. The device 5 according to the invention comprises a hierarchical storage system that is made up from a fast storage system 6, a somewhat slower storage system 7 and a tape system 8. On the workstation B, a file A that is to be backed up is determined by the client. A hash value SS52 is calculated and sent to the server 5. The server checks whether this hash value already exists in the database (CAS). Since this file has already been backed up by the workstation A, no request for the entire file is issued, instead only a new entry is made in the database (CAS), which entry refers to client B. The details of this database entry are shown in FIG. 2. Furthermore, on the mail server there is an item of mail X, which has file A as an attachment. This file, too, is not transferred to the device 5 by the client, because it is already stored on the hierarchical storage system of the device according to the invention. Instead, a reference is entered in the database (CAS). FIG. 2 shows a section of the database (CAS). For each file there is an entry in the table. The entry comprises the hash value and the owner, wherein the owner is the computer on which the client runs. The table shows that for the files with the hash value FD12 and SS52 there are three owners (access authorisations). Furthermore, the table shows where they are stored on the storage system. The information comprises the original path, the time to be stored, which is separated for backup and archival. Indexing information is done to get a fast access to the data. Data can thus be stored on the first level 6, the second level 7, and the third level, namely on the tape backup system 8. The diagram clearly shows that the file with the hash value SS52 is stored on the second level and in addition as a copy on the third level, i.e. on the slower tape system 7. Furthermore there is an overview of the content of these files. FIG. 3 shows a further special characteristic in which the differences of the files are determined, and thus only those parts of a file are transmitted that have been changed. Consequently the delta of the file that is stored on the client is calculated. The method used for calculating the delta has already been described above. Furthermore, this file is stored on the computer. The difference is calculated by the client, which on request transmits the difference to the device 5 according to the invention. As a rule it only makes sense to transmit the difference in those cases where a file is very frequently changed and the backup interval is very short. This can be the case in files where frequent changes are made, for example in database files, so that it is not necessary always to transmit the entire database file but instead only the part of this file that has changed. On the backup server the files are subsequently completely reconstituted, a process which is possible because the history of the delta changes is available, and the file can thus be reconstituted piece by piece. FIG. 4 show a flow chart of the present invention, which flow chart is used for calculating the hash value. SHA1 is a well-known algorithm for calculating the HASH value. This hash value is a value of a fixed size, irrespective of the length of the input. The size is 160 bits. There are also other variants of the SHA, which variants have a larger number of bits, as a rule 256 bits (SHA-256 . . . ). Methods for calculation are described in RFC 3174 (http://www.rfc-archive.org/getrfc.php?rfc=3174) so that there is no need to discuss them in this document. However, in the alternative embodiment an expanded ABSHASH is used. This expanded ABSHASH is used to improve the efficiency of the backup system. The backup system according to the invention comprises a number of volumes depending on the storage capacity of the hard disk systems that are used. In the end the database (CAS) has to make a decision as to the volume on which the files that are transmitted are to be stored. To avoid frequent copying operations the HASH value has been adapted accordingly so that it shows the volume in which the objects or files are to be filed. To this effect two additional bytes are used, whose purpose it is to determine the volume on which the file is to be stored. This results in the complete hash value then comprising 176 bits. The volume is calculated taking into account the total number of volumes. To this effect a corresponding modulo operation is used. FIG. 4 shows that the client transmits data. The server receives the data and checks whether the hash has been calculated in respect of this data. If this is not the case, the server checks whether a certain number of N-bytes have already been received. If this is also not the case, data is further received by the client. If N-bytes have already been received, the volume is calculated. The same occurs if the hash value has already been calculated. A check is made whether a temporary file has already been created in the corresponding volume. If this is the case the data is stored in the temporary file. If this is not the case, first a temporary file is created in which the data is then stored. After this file has been backed up the file is moved to the correct position within the volume. As a rule this can be achieved very easily because it is only a matter of changing the pointer, while there is no need to carry out a copy operation. FIG. 5 shows a transfer of the files from different storage levels. Externally, a request for restoring a certain file is made. The corresponding file is located on storage level 7. A check is made whether the newly calculated hash tallies with the name and the hash from the database. If this is the case, the file is provided; if this is not the case, the file is loaded from the storage system 8, in this case from the tape level, in order to make said file available. The alternative embodiments described in this document are not intended to limit the invention in any way. Instead, they have been provided to help understand the invention. The scope of protection of the invention is to be determined solely by the enclosed claims.	G	60G06	161G06F	17	30
11861642	US20080082681A1-20080403	Programmable logic control device with integrated database driver	ACCEPTED	20080318	20080403	[]	G06F15173	["G06F15173"]	8205005	20070926	20120619	709	232000	66195.0	HUSSAIN	FARRUKH	[{"inventor_name_last": "Leseberg", "inventor_name_first": "Gerd", "inventor_city": "Bad Pyrmont", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Pollmann", "inventor_name_first": "Werner", "inventor_city": "Hoexter", "inventor_state": "", "inventor_country": "DE"}]	The invention relates, in particular, to an automation system (10; 110), in which a programmable logic control device (20; 120) can be connected via a network (100; 200) to a database system (60; 160). So that the programmable logic control device (20; 120) can exchange data directly with the database system (60; 160), the programmable logic control device (20; 120) has a first driver module (42; 132) associated with a physical interface (50; 150) for controlling data transmission via the network (10; 110) and also a second driver module (41; 132) for controlling the data exchange with the database device (60; 160).	1. Data transmission system (10; 110) with at least one memory-programmable control device (20; 120) and at least one database device (60; 160) that are connected to each other via a network (100; 200), wherein the memory-programmable control device (20; 120) has the following features: a first driver module (42; 133) associated with a physical interface (50; 150) for controlling data transmission via the network (100; 200) and a second driver module (41; 132) for controlling the data exchange with the database device (60; 160). 2. Data transmission system according to claim 1, characterized in that the second driver module (132) is implemented in the application level (130) of the memory-programmable control device (120). 3. Data transmission system according to claim 2, characterized in that the second driver module (132) contains a database communications protocol that is written in a language according to the IEC 61131 standard. 4. Data transmission system according to claim 3, characterized in that the first driver module (133) is implemented in the user level (130) or is part of the operating system or the firmware of the memory-programmable control device (120). 5. Data transmission system according to claim 4, characterized in that the first driver module (133) contains a communications protocol that is written in a language of the IEC 61131 standard. 6. Data transmission system according to claim 2, characterized in that the database device (160) contains a standard database driver (181) for communications with the second driver module (132) of the memory-programmable control device (120). 7. Data transmission system according to claim 1, characterized in that the second driver module (41) is part of the operating system or the firmware (40) of the memory-programmable control device (20). 8. Data transmission system memory system according to claim 1, characterized in that the second driver module (41; 132) can execute commands and functions of a conventional communications protocol for database systems. 9. Database transmission system according to claim 1, characterized in that the network (100; 200) is a TCP/IP based network. 10. Memory-programmable control device (20; 120) comprising: a first driver module (42; 133) associated with a physical interface (50; 150) for controlling data transmission via a network (100; 200); and a second driver module (41; 132) for controlling the data exchange with an external database device (60; 160). 11. Memory-programmable control device (20; 120) according to claim 10, characterized in that the second driver module (132) is implemented in the application level (130) of the memory-programmable control device (120). 12. Memory-programmable control device (20; 120) according to claim 11, characterized in that the second driver module (132) contains a database communications protocol that is written in a language according to the IEC 61131 standard. 13. Memory-programmable control device (20; 120) according to claim 12, characterized in that the first driver module (133) is implemented in the user level (130) or is part of the operating system or the firmware of the memory-programmable control device (120). 14. Memory-programmable control device (20; 120) according to claim 13, characterized in that the first driver module (133) contains a communications protocol that is written in a language of the IEC 61131 standard. 15. Memory-programmable control device (20; 120) according to claim 10, characterized in that the second driver module (41) is part of the operating system or the firmware (40) of the memory-programmable control device (20).			The invention relates to a data transmission system with at least one programmable logic control device and at least one database device, which are connected to a network, for example, Ethernet. The invention further relates to a programmable logic control device, which is constructed preferably for use in such a data transmission system. In general, it is known to store large amounts of data, which occur, for example, in businesses, in database systems. In this way, the data generated, for example, by a personal computer, can be written into the database and also read out again by the personal computer. The data in the database is managed by data management software, which can include, among other things, a database language, for example, SQL (Structured Query Language). The data management software and thus also the database language are implemented in a database driver and allow, among other things, personal computers to store data in the database and to request data from the database. Large amounts of data also occur in the control, monitoring, and configuration of automation systems. The control and monitoring tasks are here performed, for example, by programmable logic controller (PLC), which provide corresponding input and output interfaces to which sensors or actuators can be connected. A disadvantage of the programmable logic controller that are used is to be seen in that the data to be managed must be stored in an internal data memory. Consequently, the invention is based on the task of making available a data transmission system, especially an automation system, in which all of the accumulating data, and also the data delivered by a programmable logic controller, can be stored in a separate database. A core idea of the invention is to be seen in that a programmable logic controller is equipped with an additional driver module that allows direct communications with a database device, so that the PLC can transfer data to the database device and can read it out again from the database device. The technical problem named above is solved, for one, by the features of claim 1. Accordingly, a data transmission system is provided that has at least one programmable logic control device and at least one database device, which are connected to each other via a network. The programmable logic control device has a first driver module associated with a physical interface for controlling data transmission via the network and also a second driver module for controlling the data exchange with the database device. Consequently, the programmable logic control device advantageously no longer requires an internal data memory of a large capacity in order to store all of the essential data, for example, control parameters, sensor data, and the like. Advantageous improvements are the subject matter of the subordinate claims. Advantageously, the second driver module, also called database driver below, is implemented in the application level of the programmable logic control device. To be able to keep the programming expense low and to be able to keep programmable logic control devices open for a plurality of database systems, the second driver module includes a database communications protocol which is written in a language according to the IEC 61131 standard typical for programmable logic control devices. Advantageously, all of the necessary functions and protocols for exchanging data with the database device are written in one of the IEC 61131 languages. If the second driver module is created in the application level, advantageously there is the possibility that the first driver module, also called hardware driver for short below, can be created in the application level, advantageously in a language of the IEC 611131 standard. In this case, the programmable logic control device can access the database device independent of its firmware or operating system. Alternatively, the hardware driver could also be created in the operating system of the programmable logic control device in a high-level language. As a rule, the database devices connected to the network use a standardized database driver as part of the operating system. To allow an open data exchange between the programmable logic control device and the database device, the second driver module of the programmable logic control device is constructed such that it can execute commands and functions of a conventional communications protocol for database systems. Alternatively, the second driver module of the programmable logic control device can be part of the operating system or the firmware of the programmable logic control device. In this case, the second driver module involves a manufacturer-dependent, that is, a proprietary, database driver. In this case, data exchange with the database device is only possible when the corresponding proprietary database driver is also implemented in the database device. Thanks to the measure of implementing an IEC 61131-based database driver in a programmable logic control device, it is possible to integrate essentially each programmable logic control device based on the IEC 61131 standard into a network in order to exchange data with a database device. The operating system or the firmware of the programmable logic control device must then still contain only a rudimentary hardware driver, which is necessary for setting up a physical connection between the programmable logic control device and the database device via the network. If, for example, Ethernet is used as the network, the hardware driver must support only an Ethernet connection between the programmable logic control device and the database server. In this way, it is sufficient for the first driver module of the programmable logic control device to contain only one Ethernet chipset. The necessary TCP/IP protocol driver can then be realized in the IEC 61131 application level or in the operating system/firmware environment of the programmable logic control device. The technical problem named above is also solved by the features of claim 10. Accordingly, a programmable logic control device is provided that has a first driver module associated with a physical interface for controlling data transmission via a network and also a second driver module for controlling the data exchange with an external database device. Advantageous refinements are described in the subordinate claims. The invention is described in more detail below with reference to two embodiments in connection with the enclosed drawings. Shown are: FIG. 1, an example data transmission system with a PLC and a database system, which can exchange data via a corresponding database driver, and FIG. 2, an alternative embodiment of a data transmission system, in which a PLC can exchange data with a database device. FIG. 1 shows schematically a section from an example automation system 10, in which a programmable logic control device 20, called PLC for short below, can exchange data directly with a database system 60 via a network. The network is shown schematically in the present example by a connection line 100, which can be, for example, an Ethernet connection. Conventionally, the programmable logic control device 20 has an application level 30, in which application software, for example for controlling, monitoring, and configuring the automation system 10, is stored. In the application level 30, a function block 31 is additionally shown which can start and terminate function calls for reading data from a database and/or for writing data into a database. It should be noted that the software in the application level 30 is preferably written in a language of the IEC 61131 standard. Furthermore, in a known way the PLC 20 contains an operating system and/or firmware level 40. So that the PLC 20 can transmit data to the database system 60 and can request data from this system, a proprietary database driver 41, which converts the function calls from the function block 31 into corresponding database control commands, is implemented in the operating system or the firmware level 40 of the PLC 20. With the help of the proprietary database driver 41, the PLC 20 is in the position to exchange data with the database system 60 via the network 100. In particular, the PLC 20 can request data from the database system 60 by means of the proprietary database driver 41. Furthermore, implemented in the operating system or firmware level 40 is a hardware driver that feeds the commands coming from the proprietary database driver 41 to a physical interface 50. The database control commands are then transmitted from the physical connection 100 via the network 100 to a corresponding physical interface 90 of the database system 60. In a known way, the database system 60 contains an operating system that has a hardware driver 82 and a proprietary database driver 81, which can exchange data with the proprietary database driver 41 of the PLC 20. In addition, the database system 60 contains a data memory, that is, the actual database 70. An alternative embodiment of a data transmission system 110 is shown in FIG. 2. A network is shown schematically, in turn, by a connection 200, which connects a programmable logic control device 120, called PLC for short, and a database system 160 to each other. An essential difference from the programmable logic control device 20 shown in FIG. 1 consists in that the PLC 120 contains a database driver 132 in the application level 130 of the PLC 120 instead of a proprietary database driver arranged in the firmware or in the operating system of PLC 20. Implemented in the database driver 132 is a communications protocol, for communications with the database system 160, that is written in a language of the IEC 61131 standard. Both the application software of the PLC 120 and also the function call module 131 are written in a language of the IEC 61131 standard. The function call module 131 comprises control software, with whose help application programs of the PLC 120 can be transmitted to the database system 160 and can be read from the database system 160 or a database 170 implemented in the database system. Because the database driver 132 has been written independent of the firmware or the operating system of the PLC 120, the PLC 120 can communicate with usual standard database drivers. Consequently, such a standard database driver 181 is implemented in the database system 160 in the operating system level 180. If the database driver 132 is written in an IEC 61131 language, it is also possible to write a hardware driver 133 in an IEC 61131 language and to implement it in the application level 130 of the PLC 120. Alternatively, the hardware driver 133 can also be a component of the firmware or the operating system of the PLC 120. This variant is not shown. Similarly to the system 10 shown in FIG. 1, both the PLC 120 and also the database system 160 have a physical interface 150 or 190, by means of which the data can be transmitted via the network 200. Similarly to the database system 60, the database system 160 also has a hardware driver 182 in the operating system level in addition to the standard database driver 181. Furthermore, the PLC 120 has at least one input interface 152, to which a sensor (not shown) can be connected. Furthermore, at least one output interface 154 is provided, to which an actuator (also not shown) can be connected. If the network is Ethernet, the hardware driver of the PLC and the database system contain the required TCP-IP protocol driver, which converts the data to be transmitted to the Ethernet format in a known way. As an example, the function of the database transmission system 110 is explained below in connection with FIG. 2. First, it shall be assumed that a temperature sensor, which regularly transmits temperature data to the PLC 120, is connected to the input interface 152 of the PLC 120. To be able to store the temperature data received at the PLC 120 in the database 170, a control program running in the PLC 120 accesses the function call module 131 in order to signal to the database driver 132 that data is now to be transmitted to the database system 160. The corresponding database write instruction is transmitted from the database driver 132 to the hardware driver 133, which converts the database write instruction into a data format that can be transmitted via the physical interface 150 and the Ethernet 200 to the physical interface 190 of the database system 160. From there, the database write instruction is forwarded via the hardware driver 182 to the standard database driver 181. Now it is signaled to the database system 160 that temperature data, which is to be stored in the database 170, is arriving from the PLC 120. The temperature data is transmitted from the PLC 120 either together with the database write instruction or writing at a later time to the database system 160 and written into the database 170. Under the control of a data management program, which is implemented in the standard database driver 181, the received temperature data is stored at corresponding locations in the database 170. Thanks to the database driver 132, an application program running in the PLC 120 can also read data from the database 170. For this purpose, the application program accesses the function call module 131 in order to prompt the PLC 120 to transmit a database read instruction via the database driver 132, the hardware driver 133, and the physical interface 150 to the physical interface 190 of the database system 160, and from there via the hardware driver 182 to the standard database driver 181 of the database system 160. The database read instruction contains information on the data that the application software of the PLC 120 would like to request. Then the corresponding data is read out from the database 170 under the control of the standard database driver 181 and transmitted to the PLC 120.	G	60G06	161G06F	151	73
11764559	US20070290795A1-20071220	DIGITAL ELECTROCHROMIC CIRCUIT WITH A VEHICLE NETWORK	ACCEPTED	20071205	20071220	[]	G06F1342	["G06F1342"]	7679488	20070618	20100316	340	425500	66587.0	CROSLAND	DONNIE	[{"inventor_name_last": "Drummond", "inventor_name_first": "John", "inventor_city": "Glenageary", "inventor_state": "", "inventor_country": "IE"}, {"inventor_name_last": "Lynam", "inventor_name_first": "Niall", "inventor_city": "Holland", "inventor_state": "MI", "inventor_country": "US"}]	A vehicular rearview mirror system includes an interior rearview mirror assembly having an interior electrochromic reflective element, a housing for the interior electrochromic reflective element, and digital circuitry supplying a drive signal to the interior electrochromic reflective element. The interior electrochromic reflective element assumes an interior mirror partial reflectance level in response to the interior mirror electrochromic reflective element drive signal. The digital circuitry includes a microcontroller for controlling over a vehicle network at least one other vehicle function. One of the at least one other vehicle function includes an exterior mirror assembly that may include an exterior electrochromic reflective element that assumes an exterior mirror partial reflectance level in response to an exterior mirror electrochromic reflective element drive signal. The microcontroller may control the exterior mirror partial reflectance level of the exterior electrochromic reflective element over the vehicle network.	1. (canceled) 2. A vehicular rearview mirror system suitable for use in a vehicle, said vehicular rearview mirror system comprising: an interior rearview mirror assembly comprising an interior electrochromic reflective element, said interior electrochromic reflective element assuming an interior mirror partial reflectance level in response to an interior mirror electrochromic reflective element drive signal; a housing for said interior electrochromic reflective element; said interior rearview mirror assembly comprising digital circuitry, said digital circuitry supplying said interior mirror electrochromic reflective element drive signal to said interior electrochromic reflective element; said digital circuitry comprising a microcontroller; said microcontroller controlling over a vehicle network at least one other vehicle function; wherein one of said at least one other vehicle function comprises an exterior mirror assembly that includes an exterior electrochromic reflective element that assumes an exterior mirror partial reflectance level in response to an exterior mirror electrochromic reflective element drive signal; wherein said microcontroller controls said exterior mirror partial reflectance level of said exterior electrochromic reflective element over said vehicle network; and wherein said interior rearview mirror assembly includes at least one of a garage door opener and a forward-facing camera. 3. The vehicular rearview mirror system of claim 2, wherein said vehicle network comprises at least one wired network connection. 4. The vehicular rearview mirror system of claim 3, wherein said vehicle network comprises a protocol selected from the group consisting of a LIN, a CAN and a LAN. 5. The vehicular rearview mirror system of claim 4, wherein said vehicle network comprises at least one of a wire, a cable and a fiber-optic connection. 6. The vehicular rearview mirror system of claim 2, wherein said vehicle network at least partially comprises a wireless network. 7. The vehicular rearview mirror system of claim 6, wherein said wireless network comprises a short-range wireless connection. 8. The vehicular rearview mirror system of claim 7, wherein said wireless network comprises a BLUETOOTH protocol. 9. The vehicular rearview mirror system of claim 6, wherein said wireless network comprises at least one of an infrared and a radio-frequency connection. 10. The vehicular rearview mirror system of claim 2, wherein said interior mirror partial reflectance level of said interior electrochromic reflective element assumed in response to said interior mirror electrochromic reflective element drive signal differs from said exterior mirror partial reflectance level of said exterior electrochromic reflective element assumed in response to said exterior mirror electrochromic reflective element drive signal. 11. The vehicular rearview mirror system of claim 2, wherein said at least one other vehicle function includes a function associated with at least one of an instrument panel and a headlight control circuit. 12. The vehicular rearview mirror system of claim 2, wherein said at least one other vehicle function comprises a reverse gear detection function and wherein said digital circuitry responds to reverse gear information sent over said vehicle network to establish a high reflectance level of said interior electrochromic reflective element. 13. The vehicular rearview mirror system of claim 2, wherein said microcontroller comprises a microprocessor. 14. The vehicular rearview mirror system of claim 2, wherein said vehicle network comprises at least a wired connection comprising no more than three wires. 15. The vehicular rearview mirror system of claim 2, wherein said at least one other vehicle function comprises at least one of (a) a remote keyless entry function, (b) a navigational system function, (c) a global-positioning system function, (d) a telematics function and (e) a display function. 16. The vehicular rearview mirror system of claim 2, wherein said interior rearview mirror assembly includes a user control, actuation of which is transmitted over said vehicle network. 17. The vehicular rearview mirror system of claim 16, wherein said user control comprises a user-operable button. 18. The vehicular rearview mirror system of claim 2, wherein said interior rearview mirror assembly comprises a forward-facing camera and wherein said forward-facing camera is at least partially controlled by said microcontroller. 19. A vehicular rearview mirror system suitable for use in a vehicle, said vehicular rearview mirror system comprising: an interior rearview mirror assembly comprising an interior electrochromic reflective element, said interior electrochromic reflective element assuming an interior mirror partial reflectance level in response to an interior mirror electrochromic reflective element drive signal; a housing for said interior electrochromic reflective element; said interior rearview mirror assembly comprising digital circuitry, said digital circuitry supplying said interior mirror electrochromic reflective element drive signal to said interior electrochromic reflective element; said digital circuitry comprising a microprocessor; said microprocessor controlling over a vehicle network at least one other vehicle function; wherein one of said at least one other vehicle function comprises a driver-side exterior mirror assembly that includes a driver-side exterior electrochromic reflective element that assumes a driver-side mirror partial reflectance level in response to an exterior mirror electrochromic reflective element drive signal; wherein said microcontroller controls said driver-side mirror partial reflectance level of said driver-side exterior electrochromic reflective element over said vehicle network; and wherein said interior rearview mirror assembly comprises a forward-facing camera and wherein said forward-facing camera is at least partially controlled by said microprocessor. 20. The vehicular rearview mirror system of claim 19, wherein said vehicle network comprises at least one wired network connection, and wherein said vehicle network comprises a protocol selected from the group consisting of a LIN, a CAN and a LAN. 21. The vehicular rearview mirror system of claim 19, wherein said interior mirror partial reflectance level of said interior electrochromic reflective element assumed in response to said interior mirror electrochromic reflective element drive signal differs from said driver-side mirror partial reflectance level of said driver-side exterior electrochromic reflective element assumed in response to said exterior mirror electrochromic reflective element drive signal. 22. A vehicular rearview mirror system suitable for use in a vehicle, said vehicular rearview mirror system comprising: an interior rearview mirror assembly comprising an interior electrochromic reflective element, said interior electrochromic reflective element assuming an interior mirror partial reflectance level in response to an interior mirror electrochromic reflective element drive signal; a housing for said interior electrochromic reflective element; said interior rearview mirror assembly comprising digital circuitry, said digital circuitry supplying said interior mirror electrochromic reflective element drive signal to said interior electrochromic reflective element; said digital circuitry comprising a microprocessor; said microprocessor controlling over a vehicle network at least one other vehicle function; wherein one of said at least one other vehicle function comprises a driver-side exterior mirror assembly that includes a driver-side exterior electrochromic reflective element that assumes a driver-side mirror partial reflectance level in response to an exterior mirror electrochromic reflective element drive signal; wherein said microcontroller controls said driver-side mirror partial reflectance level of said driver-side exterior electrochromic reflective element over said vehicle network; and wherein said interior rearview mirror assembly comprises a garage door opener and wherein said garage door opener is at least partially controlled by said microprocessor. 23. The vehicular rearview mirror system of claim 22, wherein said vehicle network comprises at least one wired network connection, and wherein said vehicle network comprises a protocol selected from the group consisting of a LIN, a CAN and a LAN. 24. The vehicular rearview mirror system of claim 22, wherein said interior mirror partial reflectance level of said interior electrochromic reflective element assumed in response to said interior mirror electrochromic reflective element drive signal differs from said driver-side mirror partial reflectance level of said driver-side exterior electrochromic reflective element assumed in response to said exterior mirror electrochromic reflective element drive signal.	<SOH> BACKGROUND OF THE INVENTION <EOH>This invention relates generally to vehicle rearview mirror systems and, more particularly, to digital electrochromic rearview mirror systems. Digital electrochromic mirror systems are described in commonly assigned U.S. Pat. No. 6,089,721 entitled DIGITAL ELECTROCHROMIC MIRROR SYSTEM and U.S. Pat. No. 6,056,410 entitled DIGITAL ELECTROCHROMIC MIRROR SYSTEM, the disclosures of which are hereby incorporated herein by reference. Such systems are capable of controlling the reflectance level of an electrochromic element from the output of a microcomputer. Various forms of vehicle communication systems have been developed including wired networks, or busses, operating one of several known protocols. These include a LIN (Local Interconnect Network), a LAN (Local Area Network), a CAN (Car or Controlled Area Network), and the like. An advantage of such vehicle networks is that the wire harness to the mirror can be minimized to as few as three wires or so, yet provide a variety of functions. Wireless communication networks utilizing radio frequency and/or infrared communication for vehicles have also been proposed, such as those utilizing the BLUETOOTH protocol. Such wireless communication and the BLUETOOTH protocol are described in more detail in commonly assigned U.S. patent application Ser. No. 09/793,002, filed Feb. 26, 2001, entitled VIDEO MIRROR SYSTEMS INCORPORATING AN ACCESSORY MODULE, now U.S. Pat. No. 6,690,268, the disclosure of which is hereby incorporated herein by reference. Trainable garage door openers, such as a universal garage door opener available from Johnson Controls/Prince Corporation, Holland, Mich. under the trade name HOMELINK™, include a transmitter for a universal home access system, which replaces the switch in a household garage door opener that opens/closes the garage door. A garage door opener communicating with a smart switch that is programmable to a household specific code that is of the rolling code type, such as is available from TRW Automotive, Farmington Hills, Mich. under the trade name KWIKLINK™, is known to be mounted within vehicles. As described in commonly assigned U.S. Pat. No. 6,172,613 B1, the disclosure of which is hereby incorporated herein by reference, the universal garage door opener HOMELINK™ unit or the universal home access KWIKLINK™ unit may be mounted at, within, or on an interior rearview mirror assembly. The KWIKLINK™ system is a low-current device that can, optionally, be operated off of a battery source, such as a long-life lithium battery. It is also compact and lightweight as executed on a single- or double-sided printed circuit board.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a new and unique combination of a digital electrochromic mirror system, a vehicle accessory and a vehicle network, and, more particularly, a combination of a digital electrochromic mirror system, a garage door opener and a vehicle network. According to an aspect of the invention, a vehicular rearview mirror system includes a digital electrochromic mirror system having a digital drive circuit and an electrochromic reflective element. The reflective element assumes a partial reflectance level in response to a drive signal. The drive circuit provides a drive signal to the reflectance element. The mirror system further includes a garage door opener including a transmitter and a logic circuit. The logic circuit supplies signals to the transmitter for transmitting garage door opening signals. The mirror system further includes a microcontroller which defines, at least in part, the digital drive circuit and the logic circuit. In this manner, the digital electrochromic mirror system has components in common with the garage door opener. According to this aspect of the invention, the microcontroller communicates over a vehicle network with at least a module performing at least one other vehicle function. The vehicle network may have at least wired network connections and may further have wireless connections. The vehicle network may have a protocol selected from the group consisting of a LIN, a CAN, or a LAN. According to this aspect of the invention, the digital drive circuit and the logic circuit may be mounted on a common circuit board. Power to the digital drive circuit and logic circuit may be supplied from a battery, preferably a rechargeable battery, that is separate from the vehicle ignition. The battery may be charged from a solar power system. According to another aspect of the invention, a vehicle rearview mirror system includes an interior rearview mirror system made up of an electrochromic reflective element, a housing for the electrochromic reflective element and a circuit board in the housing. The electrochromic reflective element assumes a partial reflectance level in response to a drive signal. A digital electrochromic drive circuit is provided on the circuit board and supplies a drive signal to the reflective element. The mirror system further includes a garage door opener. The garage door opener includes a transmitter and a logic circuit, at least one of which (and preferably, both) is on the circuit board, and share components with, the electrochromic drive circuit. The logic circuit supplies signals to the transmitter for transmitting garage door opening signals. The garage door opener may, optionally and preferably, also serve as a receiver or a transceiver for a tire pressure status monitoring/display system, such as disclosed in commonly assigned U.S. patent application Ser. No. 09/513,941, filed Feb. 28, 2000, entitled TIRE INFLATION ASSISTANCE MONITORING SYSTEM, now U.S. Pat. No. 6,294,989, and U.S. patent application Ser. No. 09/710,016, filed Nov. 10, 2000, entitled TIRE INFLATION ASSISTANCE MONITORING SYSTEM, now U.S. Pat. No. 6,445,287, the disclosures of which are hereby incorporated herein by reference, and thus have a dual tire pressure monitoring/display and garage door opener function. The mirror system further includes a microcontroller which defines, at least in part, the digital drive circuit and the logic circuit. The digital electrochromic mirror system has components in common with the garage door opener. The microcontroller communicates over a vehicle network with at least one module performing at least one other vehicle function. These and other objects, advantages and features of this invention will become apparent upon review of the following specification in conjunction with the drawings.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 11/288,649, filed Nov. 29, 2005, now U.S. Pat. No. 7,233,230 (Attorney Docket DON01 P-1256), which is a continuation of U.S. patent application Ser. No. 10/694,595, filed Oct. 27, 2003, now U.S. Pat. No. 6,970,073 (Attorney Docket DON01 P-1120), which is a continuation of U.S. patent application Ser. No. 10/134,716, filed on Apr. 29, 2002, now U.S. Pat. No. 6,639,519, which is a continuation of U.S. patent application Ser. No. 09/820,013, filed on Mar. 28, 2001, now U.S. Pat. No. 6,396,408, which claims priority from United States provisional patent application Ser. No. 60/196,577, filed on Mar. 31, 2000, the disclosures of which are hereby incorporated herein by reference in their entireties. BACKGROUND OF THE INVENTION This invention relates generally to vehicle rearview mirror systems and, more particularly, to digital electrochromic rearview mirror systems. Digital electrochromic mirror systems are described in commonly assigned U.S. Pat. No. 6,089,721 entitled DIGITAL ELECTROCHROMIC MIRROR SYSTEM and U.S. Pat. No. 6,056,410 entitled DIGITAL ELECTROCHROMIC MIRROR SYSTEM, the disclosures of which are hereby incorporated herein by reference. Such systems are capable of controlling the reflectance level of an electrochromic element from the output of a microcomputer. Various forms of vehicle communication systems have been developed including wired networks, or busses, operating one of several known protocols. These include a LIN (Local Interconnect Network), a LAN (Local Area Network), a CAN (Car or Controlled Area Network), and the like. An advantage of such vehicle networks is that the wire harness to the mirror can be minimized to as few as three wires or so, yet provide a variety of functions. Wireless communication networks utilizing radio frequency and/or infrared communication for vehicles have also been proposed, such as those utilizing the BLUETOOTH protocol. Such wireless communication and the BLUETOOTH protocol are described in more detail in commonly assigned U.S. patent application Ser. No. 09/793,002, filed Feb. 26, 2001, entitled VIDEO MIRROR SYSTEMS INCORPORATING AN ACCESSORY MODULE, now U.S. Pat. No. 6,690,268, the disclosure of which is hereby incorporated herein by reference. Trainable garage door openers, such as a universal garage door opener available from Johnson Controls/Prince Corporation, Holland, Mich. under the trade name HOMELINK™, include a transmitter for a universal home access system, which replaces the switch in a household garage door opener that opens/closes the garage door. A garage door opener communicating with a smart switch that is programmable to a household specific code that is of the rolling code type, such as is available from TRW Automotive, Farmington Hills, Mich. under the trade name KWIKLINK™, is known to be mounted within vehicles. As described in commonly assigned U.S. Pat. No. 6,172,613 B1, the disclosure of which is hereby incorporated herein by reference, the universal garage door opener HOMELINK™ unit or the universal home access KWIKLINK™ unit may be mounted at, within, or on an interior rearview mirror assembly. The KWIKLINK™ system is a low-current device that can, optionally, be operated off of a battery source, such as a long-life lithium battery. It is also compact and lightweight as executed on a single- or double-sided printed circuit board. SUMMARY OF THE INVENTION The present invention provides a new and unique combination of a digital electrochromic mirror system, a vehicle accessory and a vehicle network, and, more particularly, a combination of a digital electrochromic mirror system, a garage door opener and a vehicle network. According to an aspect of the invention, a vehicular rearview mirror system includes a digital electrochromic mirror system having a digital drive circuit and an electrochromic reflective element. The reflective element assumes a partial reflectance level in response to a drive signal. The drive circuit provides a drive signal to the reflectance element. The mirror system further includes a garage door opener including a transmitter and a logic circuit. The logic circuit supplies signals to the transmitter for transmitting garage door opening signals. The mirror system further includes a microcontroller which defines, at least in part, the digital drive circuit and the logic circuit. In this manner, the digital electrochromic mirror system has components in common with the garage door opener. According to this aspect of the invention, the microcontroller communicates over a vehicle network with at least a module performing at least one other vehicle function. The vehicle network may have at least wired network connections and may further have wireless connections. The vehicle network may have a protocol selected from the group consisting of a LIN, a CAN, or a LAN. According to this aspect of the invention, the digital drive circuit and the logic circuit may be mounted on a common circuit board. Power to the digital drive circuit and logic circuit may be supplied from a battery, preferably a rechargeable battery, that is separate from the vehicle ignition. The battery may be charged from a solar power system. According to another aspect of the invention, a vehicle rearview mirror system includes an interior rearview mirror system made up of an electrochromic reflective element, a housing for the electrochromic reflective element and a circuit board in the housing. The electrochromic reflective element assumes a partial reflectance level in response to a drive signal. A digital electrochromic drive circuit is provided on the circuit board and supplies a drive signal to the reflective element. The mirror system further includes a garage door opener. The garage door opener includes a transmitter and a logic circuit, at least one of which (and preferably, both) is on the circuit board, and share components with, the electrochromic drive circuit. The logic circuit supplies signals to the transmitter for transmitting garage door opening signals. The garage door opener may, optionally and preferably, also serve as a receiver or a transceiver for a tire pressure status monitoring/display system, such as disclosed in commonly assigned U.S. patent application Ser. No. 09/513,941, filed Feb. 28, 2000, entitled TIRE INFLATION ASSISTANCE MONITORING SYSTEM, now U.S. Pat. No. 6,294,989, and U.S. patent application Ser. No. 09/710,016, filed Nov. 10, 2000, entitled TIRE INFLATION ASSISTANCE MONITORING SYSTEM, now U.S. Pat. No. 6,445,287, the disclosures of which are hereby incorporated herein by reference, and thus have a dual tire pressure monitoring/display and garage door opener function. The mirror system further includes a microcontroller which defines, at least in part, the digital drive circuit and the logic circuit. The digital electrochromic mirror system has components in common with the garage door opener. The microcontroller communicates over a vehicle network with at least one module performing at least one other vehicle function. These and other objects, advantages and features of this invention will become apparent upon review of the following specification in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a vehicle having a vehicular rearview mirror system, according to the invention; FIG. 2 is an electronic block diagram of a digital electrochromic mirror system, according to the invention; and FIG. 3 is an electronic block diagram of a vehicular rearview mirror system, according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now specifically to the drawings, and the illustrative embodiments depicted therein, a vehicular rearview mirror system 10 is illustrated with a vehicle 11 and includes an interior rearview mirror assembly 16 and one or more exterior rearview mirror assemblies, such as driver side exterior rearview mirror assembly 12 and/or passenger side exterior rearview mirror assembly 14 (FIG. 1). Interior rearview mirror assembly 16 includes a digital electrochromic mirror system 18 which is preferably supplied according to the principles disclosed in commonly assigned U.S. Pat. Nos. 6,089,721 and 6,056,410, the disclosures of which are hereby incorporated herein by reference. Although the particulars of the invention are illustrated with an interior rearview mirror assembly 16, it should be understood that the principles of the invention could be equally applied to either or both exterior rearview mirror assemblies 12, 14. Digital electrochromic mirror system 18 includes a microcontroller 20 and an electrochromic mirror reflective element 22. As is disclosed in the '721 and '410 patents, microcontroller 20 receives inputs from light sensors 24 (preferably phototransistors or photodiodes) and supplies digital outputs 26a, 26b which control solid-state switches 28a, 28b in order to provide a drive signal at 30 thereby establishing a partial reflectance level of electrochromic reflective element 22. Microcontroller 20 includes a microprocessor. Digital electrochromic mirror system 18 further includes a bus interface 32 which interfaces with a vehicle network, or bus, 34. Items on network 34 can be connected by wired or wireless connection. Wired connection may include wire, cables, fiber-optic cables, and the like. Wireless connection can be by infrared (IR) or radio-frequency (RF) communication, and, preferably, may be a short-range RF interconnection using the BLUETOOTH protocol. Vehicle network, or bus, 34 may utilize various buss protocols including a Local Internet Network (LIN), a Local Area Network (LAN), a Car (a/k/a Controlled) Area Network (CAN), or other vehicle network protocol. The BLUETOOTH protocol is a low-cost, low-power radio-based cable replacement or wireless link based on short-range radio-based technology. BLUETOOTH enables creation of a short-range (typically 30 feet or so, although longer and shorter ranges are possible), wireless personal area network via small radio transmitters built into various devices. For example, transmission can be on a 2.45 gigahertz band, moving data at about 721 kilobits per second, or faster. In the illustrated embodiment, network 34 is a multi-drop bus which requires three or fewer wires for communication between a plurality of other vehicle functions 36, as illustrated in FIG. 3. In situations where timing and power consumption system constraints may cause network 34 wakeup time to be too slow for an automobile maker system response requirement, suitable adjustments may be made in the architecture of network 34. The network may be configured as disclosed in commonly assigned U.S. patent application Ser. No. 09/341,450 filed Jul. 8, 1999, by Drummond et al. for a VEHICLE REARVIEW MIRROR AND A VEHICLE CONTROL SYSTEM INCORPORATING SUCH MIRROR, now U.S. Pat. No. 6,291,905, the disclosure of which is hereby incorporated herein by reference. Other vehicle functions 36 include, by way of example, a seatbelt warning status 38, which status may be displayed on a mirror-based display 40. Preferably, mirror-based display 40 may be located on, at or adjacent interior rearview mirror assembly 16. Mirror-based display 40 may be of various forms including that disclosed in commonly assigned U.S. patent application Ser. No. 09/799,414, filed on Mar. 5, 2001, by McCarthy et al., entitled COMPLETE MIRROR-BASED GLOBAL-POSITIONING SYSTEM (GPS) NAVIGATION SOLUTION, now U.S. Pat. No. 6,477,464, the disclosure of which is hereby incorporated herein by reference. Additionally, display 40 may display magnetic vehicle heading information from a magnetic sensor 42, the information being supplied over network 34. Additionally, reverse gear status from a reverse gear sensor 44 may be supplied over network 34 to cause digital electrochromic mirror 18 to assume a high reflectance level when vehicle 11 is placed in reverse gear. Rearview mirror system 10 may additionally receive engine information 46 and/or door opener information at 48 over network 34 and activate general lighting 50 located in, at or on interior rearview mirror assembly 16, such as when a door of vehicle 11 is opened. Status from an alarm assembly 52 may also be conveyed over network 34 and displayed by display 40. Dim ratios, or partial reflectance levels developed from light sensors 24, can be transmitted over network 34 for use to drive exterior mirrors 12, 14. Optionally, a dim ratio or partial reflectance level chosen for a driver-side exterior mirror may be different from (and typically greater than) a dim ratio or partial reflectance level chosen for a passenger-side exterior mirror, and both may be different from a dim ratio or partial reflectance level chosen for a interior electrochromic mirror. Ambient light information, sensed by an ambient light sensor 57, can also be transmitted over network 34 for use in dimming of instrument panel 54 or automatic headlight functions 56. Alternatively, ambient light information can be developed by interior rearview mirror assembly 16 as disclosed in commonly assigned U.S. Pat. 5,715,093, the disclosure of which is hereby incorporated herein by reference. The interior rearview mirror assembly includes microcontroller 20 and a printed circuit board 61, that are common to both the digital electrochromic mirror system 18 and garage door opener function 66. Sharing of components and circuit board space can facilitate a reduction of susceptibility to RF/EMI interference and reduce cost and avoid duplication of both the network interface hardware 32, communication software and some processing power. The interior rearview mirror assembly may also include a video display system, such as disclosed in commonly assigned U.S. patent application Ser. No. 09/793,002, filed Feb. 26, 2001, entitled VIDEO MIRROR SYSTEM INCORPORATING AN ACCESSORY MODULE, now U.S. Pat. No. 6,690,268, the disclosure of which is hereby incorporated herein by reference. Components may be shared between the video display system, the digital electrochromic mirror system and/or the garage door opener. Additionally, microcontroller 20 may control a forward-facing camera system and headlight control which may also share components with the digital electrochromic mirror system and/or the garage door opener. Such forward-facing camera system and headlight control may be of the type disclosed in commonly assigned U.S. Pat. No. 5,796,094 entitled VEHICLE HEADLIGHT CONTROL USING IMAGING SENSOR, the disclosure of which is hereby incorporated herein by reference. An imaging sensor based rain sensor of the type disclosed in commonly assigned U.S. patent application Ser. No. 09/530,306, filed Apr. 27, 2000, entitled RAIN SENSOR WITH FOG DISCRIMINATION, now U.S. Pat. No. 6,353,392, may also be incorporated in circuit board 61 and share components with the digital electrochromic mirror system and/or the garage door opener. With microcomputer 20 driving digital electrochromic mirror system 18, and with vehicle status information available over network 34, it is possible to have a circuit assembly 61 in or at interior rearview mirror assembly 16 that is powered by a battery 62 that is separate from the vehicle ignition storage battery. As an example, battery 62 may be of a long-life lithium type battery. Moreover, because of its relatively small size, battery 62 may be recharged by a separate dedicated solar-powered rechargeable battery source 64 of the type described in commonly assigned patent application Ser. No. 09/793,002, filed Feb. 26, 2001, entitled VIDEO MIRROR SYSTEMS INCORPORATING AN ACCESSORY MODULE, now U.S. Pat. No. 6,690,268, the disclosure of which is hereby incorporated herein by reference. By powering mirror system 10 by a separate-dedicated solar-powered rechargeable battery source, mirror system 10 can consume power from its dedicated/local battery source, and any power used up during nighttime hours can be replenished by day via solar cell/panel that is a part of battery charger 64 and is connected to the dedicated battery 62 so as to recharge/charge during daytime hours. Furthermore, microcomputer 20 can be put into various power-saving modes thereby enabling electronic assembly 61 to be used for control of a garage door opener 66, such as a HOMELINK™ unit or the universal home access KWIKLINK™ unit. Also, a mirror-mounted microphone/digital sound-processing system 68, as disclosed in commonly assigned patent application Ser. No. 09/466,010, filed by DeLine et al., on Dec. 17, 1999, for an INTERIOR REARVIEW MIRROR SOUND-PROCESSING SYSTEM, now U.S. Pat. No. 6,420,975, the disclosure of which is hereby incorporated herein by reference, may be also powered by battery 62. Preferably, sound-processing system 68 is incorporated in circuit assembly 61 and, most preferably, shares microcontroller 20 with garage door opener 66 and digital electrochromic mirror 18. Communication button press information 58 can be transmitted over network 34 for various uses by other electronic control units, such as activation of a rescue system 60, such as General Motors' ONSTAR™ system, a Ford Motor Company's RESCU™ system, or the like. Use of digital signal-processing and a single mirror-mounted microphone (such as is described in U.S. patent application Ser. No. 09/396,179, filed Sep. 14, 1999, entitled INDICATOR FOR VEHICLE ACCESSORY, now U.S. Pat. No. 6,278,377, the disclosure of which is incorporated by reference herein) is particularly advantageous for economical achievement of clear and error-free transmission from the vehicle, while operating along a highway, to a remote receiver, particularly in speech-recognition mode. This use of network 34 facilitates location of button 58 in interior mirror assembly 16. Microcomputer 20 may receive memory information 70 over network 34 and actuate an actuator 72 to position reflective element 24. Principles, disclosed in commonly assigned U.S. Pat. 5,796,176 entitled MEMORY MIRROR SYSTEM FOR VEHICLES, the disclosure of which is hereby incorporated herein by reference, may be utilized for communicating such memory information over network 34. Microcomputer 20 may also use network 34 to measure values of light sensed by light sensors 24, supply drive signals to the electrochromic reflective element, and the like, on the network 34. Partial reflectance levels may be communicated to exterior rearview mirror assemblies 12, 24 over network 34. In this manner, if the interior digital electrochromic mirror system 18 develops a fault, incorrect information will not be transmitted to exterior rearview mirror systems. This also allows exterior reflective elements to have different peak voltages and provides more precise control over each of the mirror assemblies 12, 14, 16. Other functions may be controlled over network 34 such as remote keyless entry 74 and global positioning system information/navigational system as described in commonly assigned co-pending application Ser. No. 09/799,414, filed on Mar. 5, 2001, by McCarthy et al., entitled COMPLETE MIRROR-BASED GLOBAL-POSITIONING SYSTEM (GPS) NAVIGATION SOLUTION, now U.S. Pat. No. 6,477,464, the disclosure of which is hereby incorporated herein by reference. In addition to placement at, on or in exterior rearview mirror assembly 18, circuit board 61 may be positioned at a location (and preferably in a housing) separate from interior mirror assemblies, such as disclosed in commonly assigned U.S. Pat. No. 6,099,131 entitled ELECTRO-OPTIC MIRROR SYSTEM, the disclosure of which is hereby incorporated herein by reference. Also, the concepts of the present invention provides a new and unique combination of a digital electrochromic mirror system, a vehicle accessory and a vehicle network when the vehicle accessory comprises a tire pressure monitoring/display system. Changes and modifications in the specifically described embodiments can be carried out without departing from the principles of the invention which is intended to be limited only by the scope of the appended claims, as interpreted according to the principles of patent law including the doctrine of equivalents.	G	60G06	161G06F	13	42
11981333	US20080066151A1-20080313	Locally adaptable central security management in a heterogeneous network environment	ACCEPTED	20080227	20080313	[]	G06F1700	["G06F1700"]	8181222	20071031	20120515	726	001000	69571.0	LOUIE	OSCAR	[{"inventor_name_last": "Thomsen", "inventor_name_first": "Daniel", "inventor_city": "Minneapolis", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "O'Brien", "inventor_name_first": "Richard", "inventor_city": "Brooklyn Park", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Bogle", "inventor_name_first": "Jessica", "inventor_city": "White Bear Lake", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Payne", "inventor_name_first": "Charles", "inventor_city": "Oakdale", "inventor_state": "MN", "inventor_country": "US"}]	A system and method for defining and enforcing a security policy. Security mechanism application specific information for each security mechanism is encapsulated as a key and exported to a semantic layer. Keys are combined to form key chains within the semantic layer. The key chains are in turn encapsulated as keys and passed to another semantic layer. A security policy is defined by forming key chains from keys and associating users with the key chains. The security policy is translated and exported to the security mechanisms. The security policy is then enforced via the security mechanisms.	1. In a system having a workflow management system and a central policy management system, a computer-implemented method of controlling workflow, comprising: creating a workflow class definition; exporting the workflow class definition to the central policy management system; binding resources and roles to steps within the central policy management system; creating a workflow instance in both the workflow management system and the central policy management system; and executing the workflow instance within a computer. 2. The method of claim 1, wherein creating a workflow class definition includes creating an access control policy for the workflow class, and wherein binding resources and roles to steps within the central policy management system includes: encapsulating security mechanism application specific information for each security mechanism, wherein encapsulating includes forming a key for each security mechanism; combining keys to form key chains; and associating workflow steps with the key chains. 3. The method of claim 2, wherein binding resources and roles to steps within the central policy management system includes: importing a key chain from a first semantic layer to a local access policy layer; and enforcing the access control policy on the computer via the security mechanisms. 4. The method of claim 3, including encapsulating key chains as keys and passing the key chain keys from a second semantic layer to the first semantic layer. 5. The method of claim 1, wherein creating a workflow instance includes determining an appropriate workflow in response to a triggering event and generating the appropriate workflow instance in both the workflow management system and the central policy management system. 6. The method of claim 5, wherein creating a workflow instance includes: generating a workflow instance policy that identifies specific objects that can be accessed and specific users that may access the objects; and storing the workflow instance policy in the workflow management system. 7. The method of claim 1, wherein executing the workflow instance includes activating a workflow step according to the workflow management system and granting access control for the workflow step according to the central policy management system. 8. The method of claim 7, wherein executing the workflow instance includes deactivating a workflow step according to the workflow management system and revoking access control for the workflow step according to the central policy management system. 9. An article comprising a computer readable medium having instructions thereon, wherein the instructions, when executed in a computer, create a system for executing the method comprising: creating a workflow class definition; exporting the workflow class definition to the central policy management system; binding resources and roles to steps within the central policy management system; creating a workflow instance in both the workflow management system and the central policy management system; and executing the workflow instance. 10. The article of claim 9, further including instruction which, when executed on the computer, create a system for executing the method further including: encapsulating security mechanism application specific information for each security mechanism, wherein encapsulating includes forming a key for each security mechanism; combining keys to form key chains; associating workflow steps with the key chains; importing a key chain from a first semantic layer to a local access policy layer; and enforcing the access control policy on the computer via the security mechanisms. 11. A workflow control system, comprising: a workflow management system; and a central policy management system; wherein the workflow management system is configured to create a workflow class definition and export the workflow class definition to the central policy management system; and wherein the central policy management system is configured to bind resources and roles to workflow steps. 12. The system of claim 11, wherein the central policy management system is configured to: encapsulate security mechanism application specific information for each security mechanism, including forming a key for each security mechanism; combine keys into key chains; associate workflow steps with the key chains; and assign roles to the workflow steps. 13. The system of claim 12, wherein the central policy management system is configured to: import a key chain from a first semantic layer to a local access policy layer; and enforce the local access policy via the security mechanisms. 14. The system of claim 13, wherein the central policy management system is configured to encapsulate key chains as keys and pass the key chain keys from a second semantic layer to the first semantic layer. 15. The system of claim 11, wherein the workflow management system is configured to: receive a trigger for workflow; determine an appropriate workflow in response to the trigger; and generate an instance of the appropriate workflow in both the workflow management system and the central policy management system. 16. The system of claim 15, wherein the workflow management system is configured to: generate a workflow instance policy that identifies specific objects that can be accessed and identifies specific users that may access the objects; and store the workflow instance policy in a memory of the workflow management system. 17. The system of claim 11, wherein the workflow management system is configured to activate a workflow step to execute a workflow instance, and wherein the central policy management system is configured to grant access control for the workflow step. 18. The system of claim 11, wherein the workflow management system is configured to deactivate a workflow step, and wherein the central policy management system is configured to revoke access control for the workflow step when the workflow is completed. 19. An apparatus comprising: a network interface; and a processing unit communicatively coupled to the interface, wherein the processing unit is configured to implement a workflow manager that creates a workflow class definition and exports the workflow class definition to a remote central policy management system that is configured to bind resources and roles to workflow steps. 20. The apparatus of claim 19, including a memory coupled to the processing unit, wherein the processing unit is configured to: generate a workflow instance that includes a workflow instance policy that identifies specific objects that can be accessed and specific users that may access the objects; store the workflow instance policy in the memory; and activate a workflow step according to the workflow instance, wherein access to a resource needed for the workflow step is granted by the central policy management system. 21. The apparatus of claim 19, including an input configured to receive a trigger for workflow, and wherein the processing unit is configured to: determine an appropriate workflow in response to the trigger; generate a workflow instance of the appropriate workflow; and export the workflow instance to the central policy management system. 22. The apparatus of claim 21, wherein the processing unit is configured to: activate a workflow step according to the triggered workflow, wherein access to a resource needed for the workflow step is granted by the central policy management system; deactivate the workflow step when the workflow step is completed, wherein the central policy management system is configured to revoke the access to the resource, and activate a subsequent workflow step according to the workflow instance.	<SOH> BACKGROUND INFORMATION <EOH>Administrating security systems is a complex task. In order to enforce a tight security policy many security constraints must be expressed. Security constraints can be classified in to two broad categories: those required by the application and those required by the local security policy. It can be very difficult for local network administrators to administer security constraints for applications. At the same time, it is also very difficult for the application developer to create security policies that apply to all sites. The problem becomes even more complex when users are dispersed across networks or applications are installed by different vendors. What is needed is a system and method for defining and enforcing a security policy across a heterogenous set of applications, each having different security mechanisms.	<SOH> SUMMARY OF THE INVENTION <EOH>The above mentioned problems with defining and enforcing a security policy across a heterogenous set of applications and other problems are addressed by the present invention and will be understood by reading and studying the following specification. According to one aspect of the invention, in a system having one or more security mechanisms, a system and method is described for defining and enforcing a security policy. Security mechanism application specific information for each security mechanism is encapsulated as a key and exported to a semantic layer. Keys are combined to form key chains within the semantic layer. The key chains are in turn encapsulated as keys and passed to another semantic layer. A security policy is defined by forming key chains from keys and associating users with the key chains. The security policy is translated and exported to the security mechanisms. The security policy is then enforced via the security mechanisms. According to another aspect of the present invention, a security system has a model comprising one or more semantic layers for defining different security policies and constraints for each type of user, a tool for manipulating the model and a translator for translating security policies from the model to security mechanisms in one or more computer resources. According to yet another aspect of the present invention, a system and method are described for defining a security policy. An application policy layer and a semantic policy layer are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the semantic policy layer. One or more keys in the semantic policy layer are combined to form a key chain and the key chains are exported from the semantic layer as keys. At least one key from the semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. According to yet another aspect of the present invention, a system and method are described for defining a security policy. An application policy layer and a plurality of semantic policy layers, including a first semantic policy layer and a second semantic layer, are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the first semantic policy layer. One or more keys in the first semantic policy layer are combined to form a key chain and the key chains are exported from the first semantic layer as keys. One or more keys are imported into the second semantic policy layer and combined to form a key chain. The key chains are exported from the second semantic layer as keys. At least one key from the second semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. According to yet another aspect of the present invention, a system and method are described for modifying a security policy. An application policy layer and a semantic policy layer are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the semantic policy layer. One or more keys in the semantic policy layer are combined to form a key chain and the key chains are exported from the semantic layer as keys. At least one key from the semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. A role hierarchy is constructed by sorting the key chains into a partial ordering based on set containment. The partial ordering is displayed as a role hierarchy graph and keys are added and deleted from the role hierarchy graph. According to yet another aspect of the present invention, in a system having a workflow management system and a central policy management system, a method of controlling workflow is described. A workflow class definition is created and exported to the central policy management system. Resources and roles are bound to steps within the central policy management system. A workflow instance is created in both the workflow management system and the central policy management system. The workflow instance is then executed.	PRIORITY CLAIM This application is a divisional of U.S. patent application Ser. No. 09/483,164, filed Jan. 14, 2000, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60/168,656, filed on Dec. 2, 1999, both of which are incorporated herein by reference. STATEMENT OF GOVERNMENT RIGHTS This invention was made with Government support under Contract F30602-97-C-0245 awarded by the Air Force. The Government has certain rights in this invention. FIELD OF THE INVENTION The present invention is related to computer security, and more particularly to a security management framework for controlling access to computer resources. BACKGROUND INFORMATION Administrating security systems is a complex task. In order to enforce a tight security policy many security constraints must be expressed. Security constraints can be classified in to two broad categories: those required by the application and those required by the local security policy. It can be very difficult for local network administrators to administer security constraints for applications. At the same time, it is also very difficult for the application developer to create security policies that apply to all sites. The problem becomes even more complex when users are dispersed across networks or applications are installed by different vendors. What is needed is a system and method for defining and enforcing a security policy across a heterogenous set of applications, each having different security mechanisms. SUMMARY OF THE INVENTION The above mentioned problems with defining and enforcing a security policy across a heterogenous set of applications and other problems are addressed by the present invention and will be understood by reading and studying the following specification. According to one aspect of the invention, in a system having one or more security mechanisms, a system and method is described for defining and enforcing a security policy. Security mechanism application specific information for each security mechanism is encapsulated as a key and exported to a semantic layer. Keys are combined to form key chains within the semantic layer. The key chains are in turn encapsulated as keys and passed to another semantic layer. A security policy is defined by forming key chains from keys and associating users with the key chains. The security policy is translated and exported to the security mechanisms. The security policy is then enforced via the security mechanisms. According to another aspect of the present invention, a security system has a model comprising one or more semantic layers for defining different security policies and constraints for each type of user, a tool for manipulating the model and a translator for translating security policies from the model to security mechanisms in one or more computer resources. According to yet another aspect of the present invention, a system and method are described for defining a security policy. An application policy layer and a semantic policy layer are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the semantic policy layer. One or more keys in the semantic policy layer are combined to form a key chain and the key chains are exported from the semantic layer as keys. At least one key from the semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. According to yet another aspect of the present invention, a system and method are described for defining a security policy. An application policy layer and a plurality of semantic policy layers, including a first semantic policy layer and a second semantic layer, are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the first semantic policy layer. One or more keys in the first semantic policy layer are combined to form a key chain and the key chains are exported from the first semantic layer as keys. One or more keys are imported into the second semantic policy layer and combined to form a key chain. The key chains are exported from the second semantic layer as keys. At least one key from the second semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. According to yet another aspect of the present invention, a system and method are described for modifying a security policy. An application policy layer and a semantic policy layer are defined. A set of access rights for a computer resource is encapsulated as a key. Keys are combined to form one or more key chains within the application policy layer. Key chains from the application policy layer are exported as keys and imported into the semantic policy layer. One or more keys in the semantic policy layer are combined to form a key chain and the key chains are exported from the semantic layer as keys. At least one key from the semantic policy layer is imported into a local policy layer and combined with other keys in the local policy layer to form one or more local policy key chains. Users are assigned to local policy key chains in the local policy layer. A role hierarchy is constructed by sorting the key chains into a partial ordering based on set containment. The partial ordering is displayed as a role hierarchy graph and keys are added and deleted from the role hierarchy graph. According to yet another aspect of the present invention, in a system having a workflow management system and a central policy management system, a method of controlling workflow is described. A workflow class definition is created and exported to the central policy management system. Resources and roles are bound to steps within the central policy management system. A workflow instance is created in both the workflow management system and the central policy management system. The workflow instance is then executed. BRIEF DESCRIPTION OF THE DRAWINGS In the following drawings, where the same number reflects similar function in each of the drawings, FIG. 1 illustrates a centralized security management system 10; FIG. 2 illustrates a security management system having a multi-layered role-based access control model for unifying diverse access control mechanisms into a single environment; FIG. 3 illustrates one embodiment of a security management system according to FIG. 1; FIG. 4 illustrates another embodiment of a security management system according to FIG. 1; FIG. 5 illustrates a method of defining a security policy in a security management system according to FIG. 1; FIG. 6 illustrates another embodiment of a security management system having a multi-layered role-based access control model; FIG. 7 illustrates linking of keys and key chains within layers of the multi-layered role-based access control model of FIG. 6; FIG. 8 illustrates a CORBA application key having four sub-layers and a constraint; FIGS. 9a and 9b illustrate two ways at looking at the relationship between semantic layers; FIG. 10 illustrates a CORBA-based model 20 having two semantic layers used to transfer security mechanisms to the system administration layer; FIG. 11 illustrates a GUI screen which could be used to define handles; FIG. 12 illustrates a key chain having three keys; FIGS. 13a and 13b illustrates inheritance; FIG. 14 illustrates how keys and key chains are used to build semantic layers; FIG. 15 illustrates an RBAC policy modeled as three layers; FIG. 16 illustrates a role-based perspective of workflow; FIG. 17 illustrates a workflow enforcement system; FIG. 18 illustrates a simple workflow example; and FIG. 19 illustrates how a new workflow layer is defined in the workflow enforcement system of FIG. 17. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Some portions of the detailed description which follows are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. FIG. 1 illustrates a centralized security management system 10. System 10 includes a computer 12 connected to nonvolatile memory 14. The term “computer” is defined here to include any digital or analog data processing unit. Examples include personal computers, workstations, set top boxes, mainframes, servers, supercomputers, laptops or personal digital assistants capable of embodying the inventions described herein. In one embodiment, computer 12 is capable of reading program code such as computer instructions and data from computer readable medium 16. Examples of articles comprising computer readable media are read-write or read-only memory devices such as floppy disks, hard drives, CD-ROM or DVD. In one embodiment, computer 12 is capable of reading information and receiving commands and data from a network 18 and of writing data and commands to network 18. System 10 uses an layered approach to Role-Based Access Control (RBAC). In one embodiment, as is shown in FIG. 2, security management system 10 includes a multi-layered RBAC model 20 for unifying diverse access control mechanisms into a single environment, a Graphical User Interface (GUI) 22 for manipulating model 20, and translation software 24 for translating a security policy defined by GUI 22 to specific access control mechanisms 26.1 through 26.N. In one embodiment, system 10 provides centralized security policy management for many different access control mechanisms. System 10 is not designed to be a centralized clearinghouse for security decisions. Instead, applications are responsible for enforcement. Each application will have one or more access control mechanisms 26. System 10 is used to load the applications with the policy they are going to enforce. To be effective, a centralized security management system 10 should be able to abstract security mechanism application specific information from each security mechanism 26 and present it to the local system administrator in a clearly understandable manner. Administrating security systems can be a complex task. In order to enforce a tight security policy many security constraints must be expressed. In one embodiment, detailed permission sets are grouped into related sets. These sets are grouped into larger sets, which may in turn be incorporated into still larger sets. Creating arbitrary sets of sets allows any policy to be expressed. However, while this offers the greatest degree of flexibility the lack of organization makes it difficult to understand and maintain the policy. In one embodiment, therefore, RBAC model 20 is divided into well-defined layers. Each layer has a well-defined set of semantics and constraints. In one embodiment, security constraints are classified into two broad categories: those required by the application, and those required by the local security policy. A first step in designing a system to model complex security systems is to define these two broad categories and devise a consistent interface between them. One such approach is shown in FIG. 3. In the embodiment shown in FIG. 3, RBAC model 20 includes an application developer layer 30, a local system administration layer 32, and an interface 34 for communication security constraints between layers 30 and 32. The RBAC model 20 shown in FIG. 3 applies a divide and conquer principle to the tough problem of security management. Rather than place all the burden of security management on a system administrator in the field, the application developers share the burden by creating basic security building blocks. These building blocks capture complex application specific security constraints, freeing the local system administrators from configuring the many detailed constraints. The application developers are the people who best understand the application and can best describe the application security constraints. Only the local administrators know the local security policies, thus they are the only ones who can describe their security constraints. The application designers cannot create security policies that apply to all sites. Thus the local system administrators must have the capability to create their own building blocks, should those prepared by the application developer be insufficient. The goal of the RBAC framework is to centrally control access to a wide variety of network resources. This means incorporating diverse applications on a variety of hosts, legacy applications, and applications with unsophisticated security mechanisms. In another embodiment, interface 34 includes one or more semantic layers 36. Such an approach allows policy creation to be split between many different groups based on their assigned, or defined, semantic layers. Multiple layers allow users to work with a layer they understand. Thus a balance can be struck between fine grained access control and ease of management. The goal is to provide easy security management for a wide variety of network applications. Before access to network resources can be granted those resources must be understood. This means that the network applications must be incorporated into the model. Applications are written in different languages and run on a variety of hosts with different security mechanisms. A universal description of applications is needed that is independent of their implementations. Currently there are two widely accepted frameworks for developing distributed network applications: CORBA and Microsoft's COM/DCOM. Both frameworks use an interface definition language (IDL) to describe how an application can be accessed. The IDL definition expresses the application in an object oriented framework by listing each object's publicly available methods. Thus, in one embodiment, an object oriented approach is used for the RBAC framework. In one such embodiment, access is either granted to an object method or it is denied. Creating this object oriented model of the application is simple in the CORBA and COM/DCOM environments. The IDL file that describes an object's publicly available methods can be parsed and automatically incorporated into a security management tool. To incorporate a legacy application into the framework, an IDL file must be created. This involves defining the legacy application in terms of objects and object methods. This approach is similar to the method used to wrap applications with a CORBA interface for the CORBA environment. Here, however, the interface does not have to connect to the legacy application. The concern for the RBAC framework is, IF a method can be accessed not HOW. Instead, a component can be created to translate between the RBAC framework and the legacy applications enforcement mechanism. The RBAC framework is especially useful in a heterogeneous network environment. Making access control decisions centrally for the entire enterprise would likely create a performance bottleneck. Centralized decision making also leads to a single point of failure that could shutdown the entire network. While these performance problems could be mitigated by duplicate security servers, performance would still lag local enforcement. In one embodiment, as is shown in FIG. 5, there are three steps in defining a security policy with system 10. First GUI 22 is used in conjunction with RBAC model 20 to define the policy. Next translator 24 translates the policy to application security mechanisms 26 within each application. Finally the application security mechanisms enforce the security policy. It is preferable to centralize management of the policy, with the security decisions being enforced as close as possible to the application. The centralized management tool of FIG. 5 grants users access to objects. Once a change is made the tool translates the security policy from the RBAC framework to the target's native security mechanism, which is then transported to the target. For example, if a user was given access to the Internet via the security management tool, the tool translates that request into a number of modifications to a firewall Access Control List (ACL). These modifications are then communicated to the firewall, which implements the changes. The location of each application is known. The tool must push the security information out to the application making the access control decisions. Since we are assuming a heterogeneous network the central security policy must be translated into security mechanisms for each host making up the enterprise. If the target host already has an understanding of roles, or has a unified access control mechanism like CORBA, the translation process is easy. If the host does not understand roles the translation of the policy becomes more difficult. For legacy applications the translation from the RBAC framework to the legacy application's security mechanisms is harder still. For example, protecting an FTP server on a Unix host first requires describing the FTP server in object oriented terms. For enforcement the policy must be translated to the equivalent user accounts and file permissions. While this translation is difficult, the important point is that the legacy applications can be included into the centralized policy management, albeit at a higher cost. As noted above, system 10 can be designed to serve two primary users: application developers and local system administrators. In one such embodiment, application developers, using their in-depth knowledge of the application, create generic security components. These security components serve to hide the application-specific details. The local system administrators use these security components as the security building blocks to customize the security policy for their organization. Just as it is important to document software design to facilitate application maintenance, it is important to document the security components of the application. When the application developers create the security building blocks not only are they creating tools for the local system administrators, but they are also documenting security design and usage. Permanent documentation is critical for the long term maintenance of an application, since application developers may leave or may forget details of their implementation. Semantic layers such as the semantic layers 36 shown in FIG. 4 provide even more flexibility. For instance, applications in an application suite may have common constraints and semantics (e.g., they may all use a clipboard to move data between applications). The pattern of accesses to the clipboard is the same for each application. The architect of the application suite, therefore, is the person best suited to design the clipboard policy. In one embodiment, the architect combines the policy components created by the application developer into a new semantic layer that spans all the applications in the suite. This prevents the local system administrator from having to understand the clipboard policy. Another example is a policy layer based on the environment in which the application runs. If a client application must communicate with a server before it can execute in a certain environment, the policy interactions between the client and server are best captured in a policy layer for the system architect rather than the local system administrator. By providing semantic layers 36, the underlying structure of each layer remains the same. Pieces of policy from supporting layers were combined to produce policy for higher layers. The number of semantic layers for a given target environment depends only on the target environment. For example, some enterprises may not have organized applications into suites; thus they don't need the application suite layer. In most discussions of security policy there is an underlying assumption that a small set of users define the policy from start to finish. The approach used in system 10 is that distinct sets of users maintain different parts of the policy based on their understanding and responsibilities. In the model of FIG. 3, there were two target users, local system administrators and application developers. The expanded model of FIG. 4 divides policy maintenance between any number of users. Each user combines policy pieces from the supporting layers to capture the policy constraints and semantics of their layer. These security building blocks are then available for other layers to build on. As is shown in FIG. 6, multiple semantic layers (36.1 through 36.N) can be used to provide as many layers of abstraction as are needed. In one embodiment, the building blocks of system 10 are called keys. A key represents the ability to access some resource, just like in the real world where having a key allows a person to open a door. Keys become an atomic unit of the security policy. A key cannot be divided into smaller access control pieces. As shown in FIG. 7, application keys 40 formed at the application developer layer are passed up to semantic layers 36 and combined and passed to the next layer. The process continues up top layer 32, which binds users to the policy pieces. Keys are not capabilities. A key is an abstract representation of some rights, independent of the implementation mechanism. A capability is data that states the bearer has the rights defined in the capability. Capabilities can be passed to other users. System 10 manipulates keys to define the policy. Once the policy is defined it is translated into access control mechanisms. Another common construct to all the layers is the concept of a key chain. A key chain is, not surprisingly, a collection of keys. A key chain can also contain other key chains. This allows the user to create a Partially Ordered Set (POSET) equivalent to a role hierarchy. Key chains 42 may also have constraints 44 associated with them. If the constraint is satisfied, access in the key chain is granted, otherwise it is denied. A final common construct to all layers is the concept of abstract key chains. The concept behind abstract key chains is very similar to the object-oriented concept of an abstract class. An abstract key chain is an intermediary grouping of keys to reflect some common policy elements. For example, there may be an abstract key chain called “health care provider” that contains permissions common to doctors and nurses. A user must never be assigned to the “health care provider” key chain rather to either a doctor or a nurse. System 10 therefore, as is shown in FIG. 6, includes a base layer 30 providing application specific access control information, middle layers 36 which are flexible semantic layers, and a top layer 32 used by the local system administrator to assign users to the policy pieces. The first layer 30 of RBAC model 20 is the application specific access control mechanism. The goal of this bottom layer is to encapsulate application specific information so that it can be incorporated into the higher layers in a uniform manner. This data could be Unix permission bits, Access Control Lists (ACLs) on a firewall, or sets of CORBA methods. The approach is for the application developer to use their in depth knowledge of the application to create security policy pieces that can be used to assign access to users. For example, in a health care system the application developer groups the accesses needed by a physician into a key. A doctor assigned to this key has all the necessary permission to a patient record. Internal to the application key the policy information may be organized in any way that is convenient for the application. In one embodiment, GUI 22 is able to display and manipulate the information in the key. In another embodiment, policy information is displayed in text. Each key has a text description of the key's intended use, and the kind of access it grants. In one embodiment, a CORBASEC version 2 provides access control to a CORBA application. In one such embodiment, as is shown in FIG. 8, a CORBA application key has four sub-layers (1-4) plus constraints 6. In the approach shown, constraints 6 are bound directly to CORBA key chains 4. In one such embodiment, GUI 22 reads in the CORBA Interface Definition Language (IDL) file for the application. From this file the tool discovers the objects that have been defined for the application and their public methods. Object methods 1 are grouped into sets (object handles 2) based on the semantics of the object. Handles, in turn, are grouped into keys 3. In one embodiment, to control the scope of the key, keys 3 can only contain handles from within a single IDL file. Finally key chains are groups of keys that can span several IDL files. This allows the application developer to structure their code independent of system 10 and incorporate all the necessary privileges. Each key chain corresponds to an application role and defines the methods that are allowed to that role. For CORBA in the DTEL++ environment the interface is very similar. DTEL++ is NAI Labs implementation of Domain Type Enforcement for the CORBA object oriented environment (see, D. Sterne et al., “Scalable Access Control for Distributed Object Systems,” to appear in Proceedings of the 8th USENIX Security Symposium, Washington, DC, August 1999). In addition to controlling who can access methods DTEL++ also controls who can implement the method. This is designed to protect the CORBA client from using hostile servers masquerading as legitimate servers. In one embodiment, the key viewer for DTEL++ is identical to the CORBA viewer described above except that when a key is created it can be marked as an implement key. When the policy is translated all the users assigned an implement key get implement permission to the methods contained in the key. As noted in FIG. 8, constraints 6 can optionally be associated with key chains 4. Constraints 6 are used to capture policy information that cannot be represented as sets. Consider, for example, the fact that a role of doctor can easily describe the kinds of access a doctor needs to a patient record. However, it cannot express the fact that a doctor can only access patient records that have been assigned to them. These problems parallel the object oriented concepts of class and instance. Once the application specific information has been encapsulated into an application key, it can be combined with other keys to form semantic layers 36 such as are shown in FIG. 7. Each layer 36 starts with a set of keys 40 and uses them to build up key chains 42 representing the policy at that level. Once key chains have been built, constraints 44 may be associated with them. The key chains for one layer become keys 40 of other layers 36. Within a layer 36 keys 40 are atomic units of policy. By drilling down to another layer 36 the user can determine how the key was composed. In one embodiment, semantic layers 36 are not just stacked one on top of the other; the relationship between semantic layers must be explicitly defined. For example, the workflow policy for a specific site may only cover the accounting and medical record applications. Thus the workflow layer only needs to use the policy components from accounting and medical records. In one such embodiment, model 20 requires each policy layer to explicitly import the policy components from the layers on which they depend. The result is much like the diagrams used to discuss layers in a software system (see FIG. 9a). However, a poset more accurately describes the relationship between semantic layers (see FIG. 9b), where the dotted line shows the local sysadmin may need to bypass certain layers 36 of policy to give people direct access to the firewall. Since in one embodiment semantic layers 36 form a poset, a single layer 36 could represent any policy represented in many layers 36. The advantage of semantic layers over a standard role hierarchy is that they impose well-defined structure. Adding semantic layers to a role hierarchy does not increase the depth of the hierarchy. However, the depth of the hierarchy in each semantic layer is small, usually two or three. While hierarchies are excellent tools for programmers and researchers to use, a depth of seven starts to tax the limits of understanding. Deep hierarchies are even more problematic for system administrators without a programming background. Semantic layers allow users to focus on specific portions of the hierarchy increasing policy understanding. In one embodiment, each semantic layer 36 has the following properties: 1. Each layer produces a set of key chains that can be exported to other layers as keys. 2. Each layer explicitly lists the other layers it is importing keys from. 3. Keys cannot be modified within a layer. Only the layer that created the key can modify it. 4. Keys can be combined within a layer to form key chains. 5. Key chains can contain other key chains (from the same layer). 6. Key chains can be marked as abstract, meaning they are structural place holders like abstract classes. In this context what this means is that these key chains are not exported to the next layer. 7. A key chain may have constraints associated with it. If constraints are associated with a key chain the constraints must be satisfied before access is granted. Semantic layers 36 clearly divide responsibility for policy creation between several different users. However, it is a static type of administration. The import and export of policy components make semantic layers more static. The static nature of semantic layers has little impact because they are closely tied to static application descriptions. In fact, the application keys are a part of the application interface that deals with policy. The application keys change as frequently as the application interface. As is shown in FIG. 6, starting from the bottom of RBAC model 20, there is a general trend for the lower layers to be more static because they are tied closely with the application, and the upper layers to be more dynamic. System administration can be simplified by limiting decisions to ranges of roles to be managed in the role hierarchy. A semantic layer is equivalent to a range of roles. Many of the challenging problems in maintaining policy consistency are avoided in such an approach because the new policy is installed at the same time the latest version of the application is. Changes to the underlying applications will, however, on occasion require changes at the top level of model 20. For example, if the sysadmin depends on a “browse” key and the latest version of the application does not have it, the sysadmins must recreate their policy to compensate for the loss of the key. In one embodiment, migration tools are provided to guide the sysadmin into choosing a new key to replace the deleted key. The final layer of RBAC model 20 is identical to the other layers except that at this level users can be associated with key chains 42. The top layer is the only layer where such user role binding takes place. The top layer is also assumed to be under the control of the local sysadmin. As noted above, the top layer is more dynamic than the lower layers as it must respond to the day-to-day operations of network 18. One embodiment of a CORBA-based model 20 is shown in FIG. 10, where two semantic layers (Application Suite and Wrappers) are used to transfer security mechanisms to the system administration layer. A GUI 22 screen which could be used to define handles is shown in FIG. 11. In one embodiment, it is assumed that the local sysadmins are not familiar with the applications and that they must, therefore, depend on the application developer to create policy pieces they can use to set up local policies. Invariably some pieces will not be sufficient. When this is the case, in one embodiment, GUI 22 allows the sysadmin to “drill down” to other layers 36 and create a new key chain that meets their requirements. In one such embodiment, sysadmins are limited to drilling down only one semantic layer 36. The next section looks at the issues that arise from trying to clearly display system 10 concepts to different users with different responsibilities and varying levels of sophistication. When considering how to display policy information to a user, an important distinction must be made between policies that are designed and policies that evolve over time. A basic premise of RBAC model 22 is that semantic levels 36 are designed. The application developers and system architects must put as much time developing the security policy pieces as they would in generating a good API. Application developers and system architects are familiar with object-oriented hierarchies. Thus building and maintaining a good role hierarchy is a task they are well suited to do. On the other hand the skills of the local sysadmin can vary greatly. They may have little or no experience with inheritance concepts used by the role hierarchy. More importantly sysadmins usually have a large number of responsibilities that keep them extremely busy. As a result they do not have a great deal of time to devote to learning a new tool, and in particular they do not have time to design a role hierarchy. In fact, a role hierarchy for a local enclave can quickly change due to the introduction of new applications or policy directives. As a result, a policy created by a sysadmin evolves over time to meet the needs of the organization. In one embodiment, GUI 22 is designed to accommodate both a design and an evolutionary approach to policy development. The local sysadmin needs a simplified way to create and maintain the local policy. A role hierarchy may be needed to express the potential policies, but a poset is a confusing data structure for the sysadmin to maintain. The most effective role hierarchies must be carefully designed, which the sysadmin does not have time to do. To simplify the GUI, in one embodiment key chains 42 are prevented from containing other key chains 42 within local system administration layer 32. This results in each key chain simply having a list of keys. One such representative key chain 42 is shown in FIG. 12, where three keys 40 are combined to form a standard user key chain 42. Limiting key chains at local system administration layer 32 to combinations of keys 40 may seem like a drastic measure but, if the lower semantic layers have done their job, all the policy pieces should be there for the local sysadmin. As a result the role hierarchy for the top layer is very shallow. Practical experience in other environments shows that the role hierarchy is not very deep, rarely more than three. For such shallow structures the benefit of the role hierarchy is small compared to the gain in simplification. Simplicity does, however, come with a cost. Lack of a role hierarchy makes three operations more difficult: 1) visualizing the relationship between roles; 2) creating a new role; and 3) global policy changes that affect more than one role. Each of these drawbacks are discussed in more detail below. The drawbacks of eliminating role inheritance can be mitigated by a hybrid approach that constructs a role hierarchy from the lists of keys. In such an embodiment, each key chain 42 is a set of keys 40; GUI 22 sorts the key chains into a partial ordering based on set containment. For example, a key chain with keys {a, b, c} is more powerful than a key chain with {b, c}. Key chains with the most keys appear on top, key chains with fewer keys on the bottom. Once the partial ordering is calculated the information is shown to the sysadmin via a standard role hierarchy graph. The benefit of this approach is that the sysadmin does not have to maintain the role to role relationships explicitly, the tool constructs the role hierarchy for the user. The first problem is visualization. A role hierarchy is an excellent way to get a quick snapshot of the relative privileges between roles. For a shallow role hierarchy visualization is probably not an issue. Furthermore, the constructed role hierarchy easily can be displayed as a standard role hierarchy with all the proper visual semantics. The second problem is in creating a new role. In a role hierarchy, the new role is created by first determining its parent. The role derives most of its content from the parent. Without a role hierarchy there is no parent so all of the keys for the new role have to be specifically added. To make role creation simpler without a role hierarchy, in one embodiment, the user is allowed to select keys or key chains to add to new key chains. Since the underlying structure is based on sets, duplicate keys are eliminated during the process. In one such embodiment, creating a new role starts with creating an empty key chain. The user can then select a set of keys from other key chains or a set of key chains to copy into the new key chain. The third difficulty arises from the fact that low level constraints 44 could be modified in a single place and that these changes would directly impact all the senior roles. Consider the policy in FIGS. 11a and b. In FIG. 13a, system 10 includes role inheritance. In such an approach, the local policy has changed; now, all employees were allowed to browse the web. With a role hierarchy the “browse” key could be added to the employee node and the permission would automatically flow up the hierarchy. On the other hand, as can be seen in FIG. 13b, without role inheritance there would only be three roles: primary physician, consulting physician and nurse (because the abstract roles do not exist). Without role inheritance the “browse” key must be added directly to the three roles. Initially, adding two extra keys does not seem like a great burden compared to eliminating the complexity of maintaining a poset. In one embodiment, the user makes global policy changes by adding or deleting keys from the constructed role hierarchy. System 10 then translates the operation from the constructed hierarchy to the underlying roles. Creating a new role could also be done using the constructed hierarchy to indicate the parent and the role's context. The constructed hierarchy obtains the advantages of the role hierarchy without the complexity of designing and maintaining it. Eliminating the role hierarchy only makes sense, however, when the security policy is evolving. Clearly a designed policy is more desirable, but design takes effort and so it is best suited for a static environment. A well-designed role hierarchy represents constraints, such as “all employees can access the online vending machine”. When GUI 22 calculates the partial ordering, however, there are no semantics associated with the relationship between roles. Eliminating role inheritance simplifies maintenance only if the operations of creation of new roles, and adding global constraints are rare. If they happened frequently a role hierarchy is the best approach. Scale is another factor. Role hierarchies scale better than flat lists as the number of roles goes up. So if assumptions about the number of sysadmin roles are wrong, a role hierarchy may be a better approach. In fact, a hybrid approach is possible. A sophisticated sysadmin may create a new semantic layer 36 just below top layer 32. The new layer would have a role hierarchy for capturing the more static sysadmin's constraints. The top layer retains the simplified interface for the rapidly changing portions of the policy. While each semantic layer has to meet the conditions outlined above, how each semantic layer 36 is presented to the user can very greatly. The distinguishing characteristic of each layer is semantics, which implies each layer 36 could be presented differently based on those semantics. For example, in a workflow layer the order of the steps is important to the user but not to the model. The viewer must include the step order information to provide the user with the context they need. Thus, in one embodiment, GUI 22 supports a separate viewer for each layer. Sometimes, however, it is simply the grouping of keys that provides semantics, such as in the case of an application suite layer. In these cases a generic viewer is needed that provides an interface for manipulating keys and key chains. Often the cost of creating a specific viewer for a layer is prohibitive. In these cases the generic viewer can also be used. Application development layer keys pose an interesting problem. Each security mechanism, for the most part, has already developed a way for viewing its policy. Rather than duplicate the GUI of the original mechanism, in one embodiment it is possible to use the security mechanism's native GUI remotely from GUI 22. For example, a firewall GUI can be used to manipulate user ACLs on a proxy. At other times the native viewing mechanism is too complex or does not lend itself well to being encapsulated. In such cases an opaque key can be created. An opaque key is a construct for representing policy pieces that cannot be manipulated by the user in system 10. The administrator cannot “drill down” into the key, only the key's description of its intended use is provided. The opaque key represents some access privilege. No access control information resides, however, in the opaque key. The access control details are filled in when the policy is translated to the target mechanism. The opaque key approach lets the user assign predefined privileges for complex access control mechanisms. Once a security policy has been specified in system 10 it must be translated to the application specific security mechanisms. In one embodiment, the translation process works much like a compiler. A great deal depends on the security mechanism supported. In one CORBA embodiment, the entire policy is translated to each target mechanism. In another embodiment, parts of the policy are translated to different security mechanisms. For example, Pledge enforces part of the policy and DTEL++ enforces the rest. A translator can also be designed for Microsoft's COM/DCOM distributed object protocol. To enforce access control on methods in DCOM, DCOM interceptors were designed to access requests, providing fine-grained access control. The work with policy translation has provided two important lessons. First, sets provide an excellent starting point for combining and working with policy. Building a translator once the security mechanism is in place is usually a simple matter of conversion taking less that two weeks. Second, a relational database is useful for converting set-based policies. The database allows one to construct queries to pull out the relevant pieces. For example, the DTEL++ translation relies heavily on a relational database to calculate the minimum number of equivalence classes for DTEL++ types. Workflow System 10 also provides a practical solution for business process control, or workflow, policy management. System 10 addresses two challenges posed to workflow technology developers: simplify policy management and support distributed computing systems. The layered model of system 10 simplifies policy management by dividing the burden among all principals in the system's development. System 10 supports distributed computing systems by providing policy translators for the various enforcement mechanisms in the distributed system. Modeling workflow in system 10 is simple, because the underlying concepts of workflow are consistent with the RBAC model. However, implementing workflow is more complicated. RBAC policies are primarily class-based, but workflow policies are very much instance-based. As discussed above, each model 20 policy layer can be fashioned by a different person. In one embodiment, system 10 uses a role-based access control (RBAC) modeling environment. The environment consists of a policy model and a software tool for defining and managing the model. In one such embodiment, the software tool is implemented in Java with a model-view-controller architecture. As discussed above, model 20 is multilayered (see, e.g., FIGS. 3, 4 and 6). In one embodiment, each layer defines a set of roles that become policy building blocks for all layers dependent on that layer. The bottom policy layer defines the most primitive access control policy. This policy layer is typically application specific and is defined in terms of the access control mechanisms that manage the application's resources. The second through penultimate layers use the roles defined at other layers to create even more abstract roles that simplify policy management. There can be an arbitrary number of layers; new layers can be introduced as required. Roles defined in the top layer are assigned to users. Each policy layer can be fashioned by a different designer. Application designers define the bottom layer because they understand best what their resources are and how access to these resources should be constrained. Several designers may contribute to a single layer (e.g., there may be several applications represented in the bottom layer). System administrators define the top layer since they know who their users are. Intermediate layers may be designed by a number of people. As noted above, an application suite designer may group the roles of participating applications into roles for the suite. A system integrator may create more abstract roles based on the suite roles. It is important to note that layers in model 20 may not be strictly one above the other. A particular layer may, for instance, build on roles defined in any layer below it, not just the layer immediately below it. For example, the local system administrator is not restricted to roles defined in the penultimate layer. Roles assigned to users can be culled from any layer as needed. As noted above, model 20 uses the metaphor of a key to simplify policy management. A key corresponds to a role. Within each layer, keys are collected into key chains for easier handling. Keys cannot be exported directly to higher layers, but they can be incorporated into a key chain with only one key. In one embodiment, key chains can also contain other key chains. Such an approach supports role hierarchies. In one embodiment, model 20 is capable of associating a constraint with each key chain. The constraints place additional restrictions on the use of the key chain. For example, a key chain may allow access to patient medical records, but constraints may prevent the holder of the key chain from accessing any records for which the holder is not the primary care physician. FIG. 14 illustrates how keys and key chains are used to build semantic layers 36 in RBAC model 20. By building semantic layers with keys and key chains, system 10 enables the use of a graphic user interface such as GUI 22. In one embodiment, GUI 22 includes a viewer for each layer of the model. As noted above, while the middle layers of the model are identical structurally, they may differ semantically depending on the designer, so a different viewer is supported in each case. The tool manages the export and import of keys between layers and directs the policy translators to convert the policy rules of model 20 into the enforcement languages of the underlying policy enforcement mechanisms. In one embodiment, GUI 22 is very modular; new viewers and policy translators can be added easily. Consider a simple example of a hospital data system that is composed of two applications: a CORBA application used by the medical staff to record and share patient information and a COM billing application. The hospital purchased these applications from a third party integrator. The system's RBAC policy is modeled in system 10 as three layers, which are illustrated in FIG. 15. In the bottom layer, the designers of the CORBA application and the COM application define their application policies independently. For CORBA and COM-based applications, system 10 gathers a list of supported operations, or methods, automatically from the application's interface definition language (IDL) files. In one embodiment, each application designer uses GUI 22 to group these methods into convenient sets called handles and then to assign handles to keys. A key designates that the holder has permission to execute the associated methods. Since CORBA and COM are object based, controlling access to an object's methods is sufficient for controlling access to the object itself. To define the application security policy, the application designer uses GUI 22 to collect keys into key chains and marks the key chains for export to higher model layers. By marking key chains for export, the application developer creates policy building blocks for other layers to build upon. It is similar to creating a software interface. In one embodiment, anything not explicitly included in the interface is not available for use outside the layer. For our simple example, the CORBA-based, patient information application designer exports two key chains: a CAREGIVER key chain 50 for creating and modifying patient records and a CONSULTING key chain 52 for only viewing patient records. The COM-based billing application designer also exports two key chains: an ACCOUNTANT key chain 54 for generating billing data and an AUDITOR key chain 56 for only viewing billing data. These four key chains represent application-specific roles that are available as building blocks for higher layer policies. In the middle layer, an application suite integrator imports the four key chains from the application layer. Once a key chain is exported, it is considered an atomic entity, so it is considered a key by all higher layers. The application suite integrator is charged with defining a policy that spans all applications in the suite. In this example, the application suite builds three key chains for export: the ADMIN key chain 58 that contains the CONSULTING key 60 and the ACCOUNTANT key 62, a PROVIDER key chain 64 that contains the CAREGIVER key 66, and a REVIEWER key chain 68 that contains the CONSULTING key 60 and the AUDITOR key 70. PROVIDER key chain 64 includes a constraint 72 that the holder must be a primary care provider for the patient whose records are being accessed. At the top layer, the three key chains 58, 64 and 68 exported from the middle layer (ADMIN, PROVIDER and REVIEWER) are available as simple keys. In one embodiment, the four key chains 50, 52, 54 and 56 exported from the bottom layer (CAREGIVER, CONSULTING, ACCOUNTANT and AUDITOR) are also available in the event that ADMIN, PROVIDER and REVIEWER are not sufficient, but they are not immediately visible. While the hospital is tied to a regional information net work, it employs a small staff that must wear many hats. The system administrator uses system 10 to create three key chains to assign to users: the DOCTOR key chain 74 contains only the PROVIDER key 76, the INSURANCE key chain 78 contains only the REVIEWER key 80, and the CLERK key chain 82 contains only the ADMIN key 84. In one embodiment, constraints applied to any keys contained in a key chain apply to the key chain also. For example, a user in the DOCTOR role can only modify patient records for which the user is the primary care physician. Once the hospital's security policy is defined, the system administrator directs Napoleon to translate the policy for the CORBA and COM object managers. These object managers enforce the policy for their respective objects. In other words, as users attempt to access patient records or billing data, the object managers ensure that the users have the appropriate role and that stated constraints are satisfied. A workflow is “the computerized facilitation or automation of a business process, in whole or part.” Workflow technology is a promising solution for protecting business assets, because it controls not only who has access to what but when that access occurs. Workflow can be represented as a directed graph with one entry. Each node in the graph is a workflow activity, or step; the edges determine the order in which steps must occur. One or more objects to be accessed are associated with each step (e.g., “check request”), as are the operation or operations to be performed (e.g., “approve check request” and the performer (“MANAGER”). Riddle [W. Riddle, “Fundamental process modeling concepts”, Workshop on Workflow and Process Automation in Information Systems, National Science Foundation, May 1996] identifies the fundamental concepts of workflow and describes the relationships between them. According to Riddle, a “step” is a unit of work. It may require several resources to complete. Associated with the step are those resources and the role required to perform it. A “work product” is an artifact created or modified by steps. Steps use and produce work products. A “role” represents the accesses that are required to per form a step. A “workflow condition” is a predicate that must be satisfied during step performance. It is often expressed as entry and exit conditions on the step, that is, the step can begin when and can end when the conditions are true. A “performer” is a person or tool with the skills necessary to complete the step. A role may require special skills and therefore a specific performer. Finally, a “method” is an approach for carrying out a step. A step can be performed using one of several methods. The performer can do these methods. Several of these concepts, such as roles, methods and performers, are also fundamental concepts for RBAC. Even the concept of work products is familiar; it is just a different name for the resources to be accessed. Only steps and workflow conditions are really new. FIG. 16 illustrates Riddle's concepts using a role-based perspective, rather than a more traditional step-based view. From this perspective, steps 100 are like sub-roles. That is, steps define a group of accesses that are specific to a task. Workflow conditions determine when the sub-roles are active. A role 102, then, is a collection of steps 100 and their associated workflow conditions. Workflows are enforced by a workflow management system (WMS). The user interacts with the WMS to gain access to resources controlled by the workflow. Automated workflow technology has evolved significantly since it was introduced thirty years ago for office automation systems. Early workflow systems did not acknowledge the variety of ways that humans perform a task. So researchers focused on better modeling techniques, and today workflow research is more interdisciplinary: a combination of computer science and social science. The WMS must encompass non-computer activities such as meetings, handle unexpected contingencies, and allow new workflows to be constructed from existing workflows. Workflow process models must be reconciled with the rich variety of activities and behaviors that comprise “real work”. In short, workflow management is a complex activity, and we want to leverage existing technology as much as possible. Workflow management can be simplified considerably by adopting an RBAC model. Many role-based models, however, fail to include the role authorization constraints that are required for workflow. Since system 10 is capable of defining and applying role constraints, it is a good candidate for workflow policy management. In one embodiment, as is shown in FIG. 17, a workflow enforcement system 200 includes a system 10 connected to a workflow management system 202. System 10 is a policy management tool. While it may be tempting to extend system 10 with workflow management features, the complexity of workflow management would overwhelm it. Instead, system 10 is used as the policy management engine for a WMS 202. System 10 is used simply to specify and enforce certain aspects of the workflow policy. In one embodiment, workflow in system 200 is defined in WMS 202 and imported into system 10. In one such embodiment, workflow is imported as a collection of steps. It is not necessary to import the workflow conditions associated with each step, although such conditions could be modeled in system 10. In one embodiment, workflow is modeled as a new layer in system 10. The new layer looks structurally like the other layers; that is, it has keys and key chains with associated constraints. The difference is in how the layer is built and interpreted. The new layer is called “the workflow layer” and a new designer, the workflow administrator, is responsible for its design. In one embodiment, the workflow administrator begins by assessing the keys that are available for the workflow. The workflow often will require certain operations to be performed. If those operations are not represented in the available keys, the workflow administrator must create new keys. Once the necessary keys are imported, the workflow administrator collects the keys required for each step into a key chain that represents the step. The collection of key chains defined in this layer map one to one to the collection of steps in the workflow. The workflow administrator marks each step for export to the next layer, where they are assigned to the roles that will perform them. Several steps may be performed by the same role. To illustrate this process, let us return to the hospital scenario described above. Suppose the system administrator, who also happens to be the workflow administrator, wants to specify the simple workflow illustrated in FIG. 18. This workflow states that whenever a DOCTOR updates a patient's medical record with treatment information, the CLERK must prepare a bill for the treatment. The bill must then be reviewed by the INSURANCE representative, who may authorize partial payment. Finally, the CLERK bills the patient for the remaining balance. This workflow ensures that all bills are reviewed by the insurance representative before they are mailed to the patients, and it ensures that no insurance payment is authorized without a bill. FIG. 19 illustrates how a new workflow layer within model 300 is constructed. The bottom and second layers are constructed as before. Then the workflow administrator (who may be the system administrator) imports the keys (PROVIDER 76, ADMIN 84 and REVIEWER 80) necessary to perform the workflow from the second layer. (If these keys are insufficient to adequately describe the workflow, the workflow administrator could revisit the lower layers and construct additional keys.) Keys 76, 80 and 84 are collected according to the steps that require them. Step 1 requires only PROVIDER key 76. Steps 2 and 4 require ADMIN key 84, so ADMIN key 84 appears on two separate key chains (302 and 304). If different operations are required between the two steps, we could introduce constraints on one or both of the key chains 302 or 304. Finally, step 3 requires only REVIEWER key 80. The workflow administrator marks these four steps for export to system administrator level 310, where they are assigned to the roles (DOCTOR 74, CLERK 82 and INSURANCE 78) that will perform them. In the case of a role that can perform multiple steps (for example, CLERK), constraints are used to determine the appropriate step. The main difference between a system 10 model without workflow and a system 10 model with workflow is that the latter divides roles into sub-roles by task. A system 10 model simply describes sets of sets, so the division is natural. However, as we will discuss next, there are huge differences in how these models are enforced. System 10 is designed to provide central policy management with distributed policy enforcement. Once the policy is defined, it is “pushed out”’ to the various enforcement mechanisms in the distributed system. If the policy changes, the new version is pushed out. System 10 makes no access decisions itself. Workflow management, on the other hand, requires some central policy enforcement. First, there can be many instances of a workflow active simultaneously. The accesses permitted a specific user may vary depending on the instance. Each access request must be bound to the appropriate instance, and that binding must occur in the WMS. Second, for each workflow instance only one step (the current step) is active at any time. From an access control perspective, the permissions associated with the current step are granted only when the step begins and are revoked immediately after the step concludes. Each instance of a workflow may have a different current step at any point in time. The WMS must track the current step for each workflow instance in order to determine appropriate accesses. Our initial investigation focused on ways to enforce work flow entirely within the local enforcement mechanisms. To satisfy workflow's central enforcement needs, it was thought that a workflow object would track the current step for each instance of a workflow. That is, system 10 would create the workflow object and bind it to the resources it controls. For each access request, the local enforcement mechanism would ex amine the corresponding workflow object and verify that the request is approved for the current step. If the request is approved, the local policy (“pushed out” as usual by system 10) would be enforced for that resource. The local enforcement mechanism would update the workflow object's indicator of current step as required. There are several disadvantages with this approach. First, system 10 must be modified considerably to create and distribute workflow objects. Second, each access request requires an additional permission check to the workflow object, which may be expensive. Third, the enforcement mechanisms must be trusted to update the current step correctly. An enforcement mechanism could circumvent the workflow policy with malicious updates. Fourth, this approach would duplicate much of the workflow management processing already handled by WMS 202. Clearly this approach is very invasive, so we refocused our efforts on a solution that leaves system 10 and the local enforcement mechanisms relatively unchanged. Policy enforcement can be partitioned into three layers, from lowest to highest: controlling access to resources, controlling access to steps and application-specific enforcement. A useful split occurs in the middle, or step, layer. Steps are a natural primitive for workflow designers. A WMS is specialized to create steps, determine their proper order and control execution of work flow instances according to that order. These operations are unique to workflow technology. However, access for a particular role to the resources associated with a particular step can be controlled by mechanisms that are commonly available in non workflow domains. Our solution exploits these partitions by assigning the step layer and the application-specific layer to WMS 202 and by assigning the resource layer to system 10. Workflows, their steps and workflow conditions are specified within WMS 202. The steps are then exported to system 10, where resources and roles are bound to them. During workflow execution, WMS 202 manages workflow instances and directs system 10 to grant and revoke access, as appropriate, to specific steps. Workflow conditions are enforced by WMS 202 because they determine when the access grantings and revocations should occur. A high-level design of our solution is illustrated in FIG. 19. This design illustrates two modes: policy specification mode and workflow execution mode. Operations for policy specification mode are noted in italics, while operations for workflow execution mode are noted in ordinary text. A classical workflow management system will isolate these modes into two modules: a specification module, which enables administrators to specify the workflow, and an execution module, which assists in coordinating and performing the procedures and activities. Traditionally the specification module is used only in pre-execution; however, researchers are recognizing the need for the two modules to co-evolve to handle dynamic change and exception handling. The best way to explain the architecture is with a simple scenario for creating and executing a workflow. The workflow designer begins by specifying an access control policy that will apply to all instances of the workflow. The designer creates the workflow and its steps using the specification tools in WMS 202. This information is then exported to system 10, where the binding of resources and roles to steps (as described above) occurs. System 10 has already gathered a list of available object classes from the IDL files of its object managers. This list is also provided to WMS 202 for creating workflow instances as described below. When this process is complete, the designer has created an access control policy for a particular class of workflow. This policy names the roles required, it identifies the steps that each role may take and the class of resources that can be accessed at each step. The policy is, however, incomplete. It does not have enough information to control a workflow instance. For example, it does not name individual objects. The objects that may be accessed will depend on the current step of a workflow instance. Therefore, system 10 holds onto the policy for now; that is, it does not “push out” the policy for the enforcement engines. Creating a workflow instance will be discussed next. At this point, system 10 is loaded with a set of access control policies for workflow classes. A workflow instance gets created when some event occurs to trigger it. For example, a user requests a check reimbursement form, or a notification appears in a user's in-box. When such an event occurs, WMS 202 determines the appropriate workflow for the event and creates a new instance of that workflow. The workflow instance is stored locally at WMS 202. The instance names the specific objects that may be accessed and the specific users that may access them. When a workflow instance is created in WMS 202, it must also be created in system 10. In one embodiment, WMS 202 provides system 10 with the necessary information to instantiate the appropriate workflow's class access control policy, which means providing constraints such as “if object is named foo.txt” that will be added to the instance copy in system 10. The instance policy names (via constraints) the specific objects that can be accessed. If all specific objects are not known when the instance is created, WMS 202 may provide additional constraints for that instance later. In summary, the workflow instance definition in system 10 looks like the class definition except that it also contains the constraints that name specific objects. Executing the workflow instance will be discussed next. The execution phase highlights the simplicity of this solution. WMS 202 controls the execution of the workflow instance. It determines the proper sequence of steps (e.g., what branches are executed), and it knows which steps are active. It decides when a step should start (become active) and when it is completed (and thus become inactive). WMS 202 does what it implies: it manages the workflow. However, it relies on system 10 to manage the access control policy. As the workflow executes, WMS 202 directs system 10 to grant access to the active steps and revoke access to inactive steps. No policy is translated for the object managers unless directed by WMS 202. For example, suppose that step 1 of workflow instance P is active. Once step 1 is complete, WMS 202 directs system 10 as follows: Revoke access to step 1 in instance P, then grant access to step 2 in instance P. Note that system 10 runs in tandem with WMS 202. With regard to policy translation, the only change in system 10's behavior is that it now “pushes out” the policy a step at a time rather than all at once. CONCLUSION The use of semantic layers within RBAC model 20 simplifies the structure and allows the model to clearly divide the process of creating security policy among several different users. One of the benefits of model 20 as defined above is the encapsulation of application specific security mechanisms into a unified environment. GUI 22 and the key/key chain paradigm provide a flexible approach for manipulating a security policy across a heterogeneous population of security mechanisms. System 10 greatly simplifies the task of policy creation and maintenance for the overworked systems administrator. In addition, system 10 provides a method for adding an removing applications with minimal impact on other semantic layers, or on the local system administration layer. In a manner similar to the OSI TCP/IP model, clearly defined semantic boundaries can be used to create plug-and-play system security. We have described a workflow management architecture that incorporates system 10 for workflow policy management. The architecture exploits the natural partitions in workflow policy management by assigning workflow specific tasks to the WMS and workflow-generic tasks to system 10. This approach lets each tool do what it does best. System 10 offers many benefits to workflow management, including simplified policy management and support for heterogeneous, distributed computing systems. System 10's flexible model lets workflow be introduced at any layer. The support for distributed systems lets a workflow's control extend beyond the local system or local network. For instance, a business's divisions may be flung far across the Internet; workflows may span several divisions or even several companies (supplier, distributor, etc.). Also, a workflow may need to control resources under the purview of legacy enforcement mechanisms as well as resources managed by newer standards like CORBA. In fact, the WMS does not have to know how the resources under its control are managed. System 10 acts as a “universal adapter”’ between the WMS and the policy enforcement mechanisms. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.	G	60G06	161G06F	17	00
11928495	US20090112562A1-20090430	USER GUIDED GENERATION OF NETWORK LINK OPTIMIZATION PROFILES	ACCEPTED	20090416	20090430	[]	G06F944	["G06F944"]	9112806	20071030	20150818	709	221000	59439.0	PATEL	HARESH	[{"inventor_name_last": "Holcomb", "inventor_name_first": "Justin H.", "inventor_city": "Durham", "inventor_state": "NC", "inventor_country": "US"}]	Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation method can be provided. The method can include ranking different performance criterion for a target network, testing the target network for the different performance criterion, weighting results of the testing according to the ranking of the different performance criterion, generating a set of target network configuration parameters through optimization of the weighted results, for instance simulated annealing, and applying the set of target network configuration parameters to the target network as a profile.	1. A network optimization profile generation method comprising: ranking different performance criterion for a target network; testing the target network for the different performance criterion; weighting results of the testing according to the ranking of the different performance criterion; generating a set of target network configuration parameters through optimization of the weighted results; and, applying the set of target network configuration parameters to the target network as a profile. 2. The method of claim 1, further comprising: repeating the testing of the target network subsequent to applying the set of target network configuration parameters; weighting the results of the testing according to the ranking of the different performance criterion; generating a new set of target network configuration parameters through optimization of the weighted results; and, applying the new set of target network configuration parameters to the target network as a profile. 3. The method of claim 2, further comprising continuing to perform testing of the target network, to weight results of the testing, to generate new sets of target network configuration parameters, and to apply the new sets of target network configuration parameters in order to converge on an optimized profile for the target network considering the rankings of the different performance criterion. 4. The method of claim 2, further comprising continuing for a threshold number of iterations to perform testing of the target network, to weight results of the testing, to generate new sets of target network configuration parameters, and to apply the new sets of target network configuration parameters in order to converge on an optimized profile for the target network considering the rankings of the different performance criterion. 5. The method of claim 1, wherein testing the target network for the different performance criterion, comprises: attaching a test device to the target network; executing a plurality of tests for the different performance criterion in a test suite for the test device on live network traffic in the target network; and, transmitting results of the tests to a profile generation engine communicatively coupled over a computer communications network. 6. The method of claim 1, wherein generating a new set of target network configuration parameters through optimization of the weighted results, comprises generating a new set of target network configuration parameters through simulated annealing of the weighted results. 7. The method of claim 6, wherein generating a new set of target network configuration parameters through optimization of the weighted results, comprises generating a new set of target network configuration parameters through simulated annealing of the weighted results utilizing an energy function defined as E(s)=w(c1)C1(s)+w(c2)C2(s)+ . . . +w(cN)CN(s) for N ones of the weighted results. 8. A network optimization profile generation data processing system comprising: a test device configured for coupling to a target network, the test device comprising a test suite and a plurality of tests each directed to a different network performance criterion for the target network; a profile generation engine configured for communicative coupling to the test device over the target network, the engine comprising program code enabled to iteratively apply a profile of network configuration parameters to the target network, to signal the test device to initiate testing of the target network, and to receive test results from the test device; and, simulated annealing logic coupled to the profile generation engine, the logic comprising program code enabled to generating a profile of network configuration parameters through simulated annealing of weighted ones of the test results. 9. The system of claim 8, wherein the simulated annealing of the weighted ones of the test results comprises a simulated annealing of the weighted ones of the test results utilizing an energy function defined as E(s)=w(c1)C1(s)+w(c2)C2(s)+ . . . +w(cN)CN(s) for N ones of the weighted ones of the test results. 10. A computer program product comprising a computer usable medium embodying computer usable program code for network optimization profile generation, the computer program product comprising: computer usable program code for ranking different performance criterion for a target network; computer usable program code for testing the target network for the different performance criterion; computer usable program code for weighting results of the testing according to the ranking of the different performance criterion; computer usable program code for generating a set of target network configuration parameters through optimization of the weighted results; and, computer usable program code for applying the set of target network configuration parameters to the target network as a profile. 11. The computer program product of claim 8, further comprising: computer usable program code for repeating the testing of the target network subsequent to applying the set of target network configuration parameters; computer usable program code for weighting the results of the testing according to the ranking of the different performance criterion; computer usable program code for generating a new set of target network configuration parameters through optimization of the weighted results; and, computer usable program code for applying the new set of target network configuration parameters to the target network as a profile. 12. The computer program product of claim 10, further comprising, computer usable program code for continuing to perform testing of the target network, to weight results of the testing, to generate new sets of target network configuration parameters, and to apply the new sets of target network configuration parameters in order to converge on an optimized profile for the target network considering the rankings of the different performance criterion. 13. The computer program product of claim 10, further comprising, computer usable program code for continuing for a threshold number of iterations to perform testing of the target network, to weight results of the testing, to generate new sets of target network configuration parameters, and to apply the new sets of target network configuration parameters in order to converge on an optimized profile for the target network considering the rankings of the different performance criterion. 14. The computer program product of claim 10, wherein the computer usable program code for testing the target network for the different performance criterion, comprises: computer usable program code for attaching a test device to the target network; computer usable program code for executing a plurality of tests for the different performance criterion in a test suite for the test device on live network traffic in the target network; and, computer usable program code for transmitting results of the tests to a profile generation engine communicatively coupled over a computer communications network. 15. The computer program product of claim 10, wherein the computer usable program code for generating a new set of target network configuration parameters through optimization of the weighted results, comprises computer usable program code for generating a new set of target network configuration parameters through simulated annealing of the weighted results. 16. The computer program product of claim 14, wherein the computer usable program code for generating a new set of target network configuration parameters through simulated annealing of the weighted results, comprises computer usable program code for generating a new set of target network configuration parameters through simulated annealing of the weighted results utilizing an energy function defined as E(s)=w(c1)C1(s)+w(c2)C2(s)+ . . . +w(cN)*CN(s) for N ones of the weighted results.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to the field of network connectivity for roaming mobile end users and more particularly to the field of network optimization profile generation in performance optimizing network connections during roaming. 2. Description of the Related Art In a mobile computing environment, it is often required that users be allowed to connect to computing resources over a variety of types of network technologies with minimal disruption of the application environment. Virtual private network (VPN) tunneling enables mobile users to connect to different computing resources from remote locations, as a VPN can provide a tunnel for passing traffic to a backend network through an application-transparent virtual connection. Advantageously, VPN tunneling can support roaming in which an established VPN tunnel can switch from one physical network to another seamlessly so that client applications remain connected as the VPN tunnel switches between physical networks. In this regard, roaming involves switching between physical networks while keeping the VPN tunnel open and undisrupted. Yet, because the performance characteristics of each different physical network may vary widely, for each virtual connection it is preferred to optimize the manner in which the traffic is handled for each physical network as much as possible. To with, performance optimization includes adjusting connectivity settings such as compression levels, header reduction, packet buffering and packet joining, and transport control protocol (TCP) retransmission suppression. Performance optimization for each different physical connection can be expressed in a network optimization profile in which preconfigured sets of optimization settings can be stored for application to a VPN tunnel at connection time or roam time based upon the physical network from which a roaming device connects. Still, very often it can be difficult for the operator of the virtual network to obtain a properly configured optimization profile. In this regard, network optimization profiles ordinarily are manually created either in a lab environment by the vendor of the virtual network, or in the field by the operator of the virtual network. In the former circumstance, the efficacy of a generated network optimization profile is limited to the physical network represented in the lab environment and not in the field. In the latter circumstance, a level of expertise can be lacking. Consequently, successfully deployed network optimization profiles tend to be tuned for general performance rather than for the specific application needs of the virtual network operator. To the extent that the end user attempts to tune the optimization profile to meet the specific needs of the field, the end user tends to lack enough specialized expertise necessary to create optimization profiles for each carrier network that may be serviced by the virtual network, for example a virtual network serving 802.11, code division multiple access (CDMA), and a non-Internet protocol (IP) Mobitex network, that it is common for the end user to degrade network performance by mis-configuring the optimization settings of the profile during manual tuning.	<SOH> BRIEF SUMMARY OF THE INVENTION <EOH>Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a novel and non-obvious method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation method can be provided. The method can include ranking different performance criterion for a target network, testing the target network for the different performance criterion, weighting results of the testing according to the ranking of the different performance criterion, generating a set of target network configuration parameters through optimization of the weighted results, for instance simulated annealing, and applying the set of target network configuration parameters to the target network as a profile. In another embodiment of the invention, a network optimization profile generation data processing system can be provided. The system can include a test device configured for coupling to a target network. The test device can include a test suite and a set of tests each directed to a different network performance criterion for the target network. The system also can include a profile generation engine configured for communicative coupling to the test device over the target network. The engine can include program code enabled to iteratively apply a profile of network configuration parameters to the target network, to signal the test device to initiate testing of the target network, and to receive test results from the test device. Finally, the system can include simulated annealing logic coupled to the profile generation engine. The logic can include program code enabled to generating a profile of network configuration parameters through simulated annealing of weighted ones of the test results. Additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The aspects of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of network connectivity for roaming mobile end users and more particularly to the field of network optimization profile generation in performance optimizing network connections during roaming. 2. Description of the Related Art In a mobile computing environment, it is often required that users be allowed to connect to computing resources over a variety of types of network technologies with minimal disruption of the application environment. Virtual private network (VPN) tunneling enables mobile users to connect to different computing resources from remote locations, as a VPN can provide a tunnel for passing traffic to a backend network through an application-transparent virtual connection. Advantageously, VPN tunneling can support roaming in which an established VPN tunnel can switch from one physical network to another seamlessly so that client applications remain connected as the VPN tunnel switches between physical networks. In this regard, roaming involves switching between physical networks while keeping the VPN tunnel open and undisrupted. Yet, because the performance characteristics of each different physical network may vary widely, for each virtual connection it is preferred to optimize the manner in which the traffic is handled for each physical network as much as possible. To with, performance optimization includes adjusting connectivity settings such as compression levels, header reduction, packet buffering and packet joining, and transport control protocol (TCP) retransmission suppression. Performance optimization for each different physical connection can be expressed in a network optimization profile in which preconfigured sets of optimization settings can be stored for application to a VPN tunnel at connection time or roam time based upon the physical network from which a roaming device connects. Still, very often it can be difficult for the operator of the virtual network to obtain a properly configured optimization profile. In this regard, network optimization profiles ordinarily are manually created either in a lab environment by the vendor of the virtual network, or in the field by the operator of the virtual network. In the former circumstance, the efficacy of a generated network optimization profile is limited to the physical network represented in the lab environment and not in the field. In the latter circumstance, a level of expertise can be lacking. Consequently, successfully deployed network optimization profiles tend to be tuned for general performance rather than for the specific application needs of the virtual network operator. To the extent that the end user attempts to tune the optimization profile to meet the specific needs of the field, the end user tends to lack enough specialized expertise necessary to create optimization profiles for each carrier network that may be serviced by the virtual network, for example a virtual network serving 802.11, code division multiple access (CDMA), and a non-Internet protocol (IP) Mobitex network, that it is common for the end user to degrade network performance by mis-configuring the optimization settings of the profile during manual tuning. BRIEF SUMMARY OF THE INVENTION Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a novel and non-obvious method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation method can be provided. The method can include ranking different performance criterion for a target network, testing the target network for the different performance criterion, weighting results of the testing according to the ranking of the different performance criterion, generating a set of target network configuration parameters through optimization of the weighted results, for instance simulated annealing, and applying the set of target network configuration parameters to the target network as a profile. In another embodiment of the invention, a network optimization profile generation data processing system can be provided. The system can include a test device configured for coupling to a target network. The test device can include a test suite and a set of tests each directed to a different network performance criterion for the target network. The system also can include a profile generation engine configured for communicative coupling to the test device over the target network. The engine can include program code enabled to iteratively apply a profile of network configuration parameters to the target network, to signal the test device to initiate testing of the target network, and to receive test results from the test device. Finally, the system can include simulated annealing logic coupled to the profile generation engine. The logic can include program code enabled to generating a profile of network configuration parameters through simulated annealing of weighted ones of the test results. Additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The aspects of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. The embodiments illustrated herein are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown, wherein: FIG. 1 is a pictorial illustration of a process for user guided generation of network link optimization profiles; FIG. 2 is a schematic illustration of a data processing system configured for user guided generation of network link optimization profiles; and, FIG. 3 is a flow chart illustrating a process for user guided generation of network link optimization profiles. DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention provide a method, system and computer program product for user guided generation of network link optimization profiles. In accordance with an embodiment of the present invention, an optimization profile for a target network can be generated in an iterative fashion according to the prioritization of performance factors for the target network as specified by an end user. In particular, a test suite in the target network can iteratively test the target network using parameters suggested by a profile generation engine according to weights assigned by the end user in respect to prioritized network performance criteria. The parameters can be computed according to the weights provided by the end user and the results of the tests as applied to an optimization algorithm, for instance a simulated annealing algorithm. In this way, the target network can be configured in an automated fashion according to the performance criteria most important to the end user. In illustration, FIG. 1 pictorially depicts a process for user guided generation of network link optimization profiles. As shown in FIG. 1, weighted performance criteria 140 can be defined by an end user for a target network 110 and provided to a profile generation engine 130 in the creation of an optimized network configuration profile 150. The weighted performance criteria 140, for example, can include a set of weights each applied to a different aspect of network performance to indicate a preference of which aspects of network performance are most important subjectively to the end user. The profile 150 can be applied to the target network 110 and a test suite 120 coupled to the target network 110 can conduct a series of tests on live traffic in the target network 110 to determine the performance of the target network 110 as configured according to the profile 150. Thereafter, the results 160 of the tests can be provided to the profile generation and combined with the weighted performance criteria to produce an iteratively refined set of network configuration parameters in a profile 150. Again, the profile 150 can be applied to the target network 110 and the process can begin anew. Notably, the generation of the profile can result from the execution of a simulated annealing algorithm. In this regard, the simulated annealing algorithm can compute different energy states for the observed performance of the target network 110, each of the energy states further accounting for the weighted performance criteria 140 specified by the end user. In this regard, each energy state can include a weighted sum of the results of each different test applied to the target network 110 having a configuration set forth according to the parameters of the profile 150. Each different test in turn can correspond to a different one of the weighted performance criteria set forth by the end user. In more particular illustration, FIG. 2 is a schematic illustration of a data processing system configured for user guided generation of network link optimization profiles. The system can include a test device 210 coupled to a target network 240 and communicatively linked to a profile generation host 250 over the target network 240. The test device 210 can include a test suite 220 programmed to test the target network 240 according to one or more tests 230, each of the tests 230 addressing different network performance criteria. The profile generation host 250, by comparison, can host the operation of a profile generation engine 300 providing network configuration parameters 270 to configure the target network 240 according to user preferences for network performance criteria, and to interoperate with the test suite 220 to iteratively test the target network 240. Simulated annealing logic 260 can be coupled to the profile generation engine 300. The simulated annealing logic 260 can include program code enabled to generate optimal network configuration parameters 290A according to results 290B provided by a prior iteration of the tests 230 and weights 280 for network performance criteria. Specifically, an energy function can be implemented by the program code of the simulated annealing logic 260 according to E(s)=w(c1)C1(s)+w(c2)C2(s)+ . . . +w(cN)*CN(s) for N test results 290B for N corresponding network performance criterion, each being weighted by an end user based upon a specified end user ranking of the network performance criterion. In illustration of the operation of the profile generation engine 300, FIG. 3 is a flow chart illustrating a process for user guided generation of network link optimization profiles. Beginning in block 310, a test device can be connected to the target network. In block 320, rankings for performance criteria for the target network can be loaded reflecting an end user preference of which performance criterion are more or less important than other performance criterion. In block 330, initial optimization parameters for the target network can be determined based upon the ranked performance criterion. Thereafter, the parameters in the form of a profile can be applied to the test device in block 340 and the test device can execute a series of performance tests on the target network using live traffic flowing over the target network. Each test can target a different performance criterion. In block 350, the results of the tests can be received from the test device according to the different performance criterion. Subsequently, in block 360 a new set of optimization parameters can be computed using simulated annealing according to the received results weighted by the different rankings for the different performance criterion. In decision block 370, if a threshold number of iterations have not yet been surpassed, in block 380 the new set of optimization parameters can be applied to the target network in the form of a profile and the process can continue through block 340. In decision block 370, when a threshold number of iterations have come to pass, in block 390 the converged, final set of optimization parameters can be stored as a profile for the target network. Embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, and the like. Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.	G	60G06	161G06F	9	44
11858030	US20080016152A1-20080117	METHOD OF CONTROLLING SERVER APPARATUS WHICH STORES IMAGE DATA RECEIVED VIA NETWORK IN MEMORY, PROGRAM FOR CAUSING COMPUTER APPARATUS TO EXECUTE THE METHOD, STORAGE MEDIUM WHICH STORES THE PROGRAM, AND COMPUER APPARATUS	ACCEPTED	20080102	20080117	[]	G06F1516	["G06F1516"]	8204894	20070919	20120619	707	104100	90324.0	HOLLAND	SHERYL	[{"inventor_name_last": "MORISADA", "inventor_name_first": "Chikara", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "MITANI", "inventor_name_first": "Shigeyuki", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}]	An object of this invention is to provide a method of controlling a server apparatus for disclosing image data with a representation effect to a third party without any operation of a user, a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer apparatus. The server apparatus which stores image data received from the user via a network in a memory sets a representation effect used to disclose image data. The server apparatus creates page information for displaying the image data with the representation effect, and notifies a third party of the URL of the page information. The third party can browse the image data with the representation effect on the basis of the URL.	1.-8. (canceled) 9. A method of controlling a server apparatus which stores in a memory image data received via a network, comprising the steps of: setting a disclosure date of a received image represented by the received image data; processing the received image data so as to create a processed image represented by the received and processed image data; comparing a time ticked in the server apparatus and the set disclosure date; creating Web page information linked to the processed image represented by the received and processed image data when the time ticked in the server apparatus is determined to be earlier than the set disclosure date, and creating Web page information linked to the received image represented by the received image data when the time ticked in the server apparatus is determined to be the set disclosure date; and transmitting, via the network, the created Web page information linked to the processed image represented by the received and processed image data before the set disclosure date, and transmitting the created Web page information linked to the received image represented by the received image data on the set disclosure date, to a specified recipient. 10. The method according to claim 9, wherein said processing step creates a plurality of processed images, and further comprising a step of setting a level of processing performed for the received image data to create each of the plurality of processed images. 11. The method according to claim 9, wherein a same address in the network is assigned for transmitting the Web page information linked to the processed image represented by the received and processed image data and the Web page information linked to the received image represented by the received image data. 12. The method according to claim 9, wherein said processing includes at least one of mosaic processing, emboss processing, and wipe processing. 13. A computer-readable storage medium on which is stored a computer-executable program for a method of controlling a server apparatus which stores in a memory image data received via a network, the program comprising computer-executable code for performing the steps of: setting a disclosure date of a received image represented by the received image data; processing the received image data so as to create a processed image represented by the received and processed image data; comparing a time ticked in the server apparatus and the set disclosure date; creating Web page information linked to the processed image represented by the received and processed image data when the time ticked in the server apparatus is determined to be earlier than the set disclosure date, and creating Web page information linked to the received image represented by the received image data when the time ticked in the server apparatus is determined to be the set disclosure date; and transmitting, via the network, the created Web page information linked to the processed image represented by the received and processed image data before the set disclosure date, and transmitting the created Web page information linked to the received image represented by the received image data on the set disclosure date, to a specified recipient. 14. A server apparatus which stores image data received via a network in a memory, comprising: a setting unit configured to set a disclosure date of a received image represented by the received image data; a processing unit configured to process the received image data so as to create a processed image represented by the received and processed image data; a comparing unit configured to compare a time ticked in the server apparatus and the set disclosure date; a page creating unit configured to create Web page information linked to the processed image represented by the received and processed image data when the time ticked in the server apparatus is determined to be earlier than the set disclosure date, and to create Web page information linked to the received image represented by the received image data when the time ticked in the server apparatus is determined to be the set disclosure date; and a transmitting unit configured to transmit, via the network, the created Web page information linked to the processed image represented by the received and processed image data before the set disclosure date, and to transmit the created Web page information linked to the received image represented by the received image data on the set disclosure date, to a specified recipient. 15. The method according to claim 9, further comprising a mode selecting step of selecting a first mode in which the processing of the received image data in said processing step is performed or a second mode in which the processing of the received image data in said processing step is not performed. 16. The server apparatus according to claim 14, further comprising a mode selecting unit configured to select a first mode in which the processing of the received image data by said processing means is performed or a second mode in which the processing of the received image data by said processing means is not performed.	<SOH> BACKGROUND OF THE INVENTION <EOH>There is a network service which provides a service of storing image data photographed by the user with an image input device in the storage area of a server in a network and allowing the user to browse the image data at desired time. Also, there is a network service which provides a service capable of disclosing stored image data to a third party permitted by the user (U.S. Publication No. US-2003-0065531-A1). Application software which performs mosaic processing for image data in the client apparatus of the user, and at desired time, cancels mosaic processing to reproduce the original image data is also available. In the use of this application software, however, only the user who holds a mosaic image and the application software in the client apparatus can see the image. The image cannot be disclosed to a third party. A representation of disclosing almost the same image data as an original along the lapse of time cannot be made to a third party.	<SOH> SUMMARY OF THE INVENTION <EOH>According to an aspect of the present invention, there is provided a method of controlling a server apparatus which stores image data received via a network in a memory, comprising the steps of setting a disclosure date of the image data, processing the image data to create processed image data and store the processed image data in the memory, determining whether a time ticked in the server apparatus and the disclosure date coincide with each other, when the time ticked in the server apparatus is determined to be earlier than the disclosure date, creating page information for displaying the processed image data, when the time ticked in the server apparatus is determined to be the disclosure date, creating page information for displaying the image data, and transmitting the created page information via the network. The present invention further provides a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer apparatus. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.	FIELD OF THE INVENTION The present invention relates to a method of controlling a server apparatus which stores image data received via a network in a memory, a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer apparatus. BACKGROUND OF THE INVENTION There is a network service which provides a service of storing image data photographed by the user with an image input device in the storage area of a server in a network and allowing the user to browse the image data at desired time. Also, there is a network service which provides a service capable of disclosing stored image data to a third party permitted by the user (U.S. Publication No. US-2003-0065531-A1). Application software which performs mosaic processing for image data in the client apparatus of the user, and at desired time, cancels mosaic processing to reproduce the original image data is also available. In the use of this application software, however, only the user who holds a mosaic image and the application software in the client apparatus can see the image. The image cannot be disclosed to a third party. A representation of disclosing almost the same image data as an original along the lapse of time cannot be made to a third party. SUMMARY OF THE INVENTION According to an aspect of the present invention, there is provided a method of controlling a server apparatus which stores image data received via a network in a memory, comprising the steps of setting a disclosure date of the image data, processing the image data to create processed image data and store the processed image data in the memory, determining whether a time ticked in the server apparatus and the disclosure date coincide with each other, when the time ticked in the server apparatus is determined to be earlier than the disclosure date, creating page information for displaying the processed image data, when the time ticked in the server apparatus is determined to be the disclosure date, creating page information for displaying the image data, and transmitting the created page information via the network. The present invention further provides a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer apparatus. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. FIG. 1 is a block diagram showing the schematic arrangement of an entire information providing system according to an embodiment of the present invention; FIG. 2 is a flow chart showing a setting processing sequence of disclosing image data with a representation effect by a server apparatus according to the embodiment; FIG. 3 is a view showing a disclosure date & image disclosure mode setting window according to the embodiment; FIG. 4 is a view showing an image processing type selection & disclosure unit setting window according to the embodiment; FIG. 5 is a view showing an image data order setting window according to the embodiment; FIG. 6 is a view showing an image data order confirmation window according to the embodiment; and FIG. 7 is a flow chart showing a processing sequence of disclosing image data with a representation effect to the PC of the browsing user by the server apparatus according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be illustratively described in detail below with reference to the accompanying drawings. The relative arrangement and display window of building components and the like described in the embodiment may not be construed to limit the scope of the present invention to only themselves unless otherwise specified. A system which provides an image data sharing service as an information providing system will be representatively explained. As described above, the present invention is not limited to this, and is an invention which solves problems common to services using networks. The present invention also includes these services. An information providing system which provides an image data sharing service via the Internet will be described as an embodiment of the present invention. In the following description, an interested party who saves image data in a network server will be simply referred to as a user. A third party designated by the user as a partner to whom image data is disclosed will be referred as a browsing user. FIG. 1 is a block diagram showing an example of an entire information providing system according to the embodiment. Reference numeral 101 denotes an image input device such as a digital still camera capable of photographing a still picture and recording it as image data, or a digital video camera capable of photographing a moving picture and recording it as moving picture data. The image input device 101 converts an optical signal serving as image information into an electrical signal, performs predetermined image processing, and then records/reproduces the image as digital information. Reference numeral 102A denotes a user personal computer (to be simply referred to as a user PC hereinafter). The user personal computer 102A incorporates a Web browser 120A for browsing the Internet, as an application program. Reference numeral 116 denotes a data transfer interface for transferring, photographed image data between the image input device 101 and the user PC 102A. The data transfer interface 116 may be a wire interface such as USB or IEEE 1394, or a wireless interface such as IrDA or Bluetooth. Image data which is photographed by the image input device 101 and stored as digital information is transferred via the data transfer interface 116 to the storage area of an information storage such as the HDD of the user PC 102A. As for image data transfer from the image input device 101 to the user PC 102A, image data stored in the information storage of the image input device 101 are transferred at once in accordance with an instruction from an OS or application software installed in the user PC 102A. Alternatively, the OS or application software of the user PC 102A ensures a data recording area in the information recording unit of the user PC 102A in accordance with a transfer command from the image input device 101, and then image data is transferred. (Example of Upload of Image Data) Image data transferred to the user PC 102A is uploaded to an image database (DB) 117 of a photo site 105 connected to Internet 104 by the following sequence. The Web browser 120A of the user PC 102A accesses the photo site 105 by using a standard protocol such as the http protocol. The Web browser 120A displays information which is created in a description language such as HTML or XML, linked to multimedia information such as images and sound, and managed by the server PC of the photo site 105. By this operation, the user PC 102A can receive a service provided by the photo site 105 via the Internet 104. Image data stored in the information storage area of the user PC 102A is uploaded from the user PC 102A to the photo site 105. An image is uploaded by selecting image data to be uploaded in the Web browser 120A, transmitting an image data upload request to the photo site 105, and synchronously transferring the image data. An image may be uploaded by selecting image data by using image data upload software or the like installed in the user PC 102A and accessing the photo site 105. In either case, upload is executed on the basis of a protocol such as http or ftp which can be used in the Internet 104. A series of operations are executed by a photo sharing module 106 of the photo site 105. The photo sharing module 106 checks whether uploaded image data is data usable by the photo site 105. If so, the photo sharing module 106 stores the uploaded image data in the image database 117, and stores attribute information or the like in an information database 118. The photo sharing module 106 notifies the user PC 102A that the image data has normally been uploaded. The database 118 centralizes various data such as user attribute information data registered in the photo site 105 in addition to the above-mentioned image data attribute information. The user of the user PC 102A can browse the uploaded image data via the Web browser 120A. Note that uploaded image data may be managed as an album containing one or a plurality of image data. The PC 102A has been exemplified as a terminal which uploads image data to the photo site 105, but the information providing system according to the present invention is not limited to this. An image may be uploaded from a portable terminal, or image data may be directly uploaded from the image input device 101 such as a digital camera, digital video recorder, scanner, or copying machine. <Arrangement Example of Photo Site in Information Providing System According to Embodiment> Processing of setting a representation effect in disclosing image data of the user to the browsing user in the information providing system according to the embodiment will be described in detail. Note that services and functions realized by the information providing system according to the present invention are not limited to those described above. FIG. 2 is a flow chart showing a processing sequence of setting a representation effect by the photo site 105 according to the embodiment in disclosing image data of the user. The photo site 105 is configured by one or a plurality of servers, and the server comprises a module which executes various functions. The following steps are executed by the server or module. Step S201: The photo site 105 transmits to the user PC 102A window information for selecting image data to be disclosed to the browsing user from uploaded image data of the user. The Web browser 120A of the user PC 102A displays an image data selection window on the basis of the window information. The Web browser 120A receives designation of one or a plurality of image data by user operation, and notifies the photo site 105 of the designation. The photo site 105 receives the designation of the image data from the user. The photo site 105 generates a URL (Universal Resource Locator) necessary to access a Web page for displaying the image data designated by the user. At this time, the generated URL is uniquely assigned to original image data. Alternatively, the URL is uniquely assigned to an album containing a plurality of original image data. Step S202: The photo site 105 transmits to the user PC 102A window information for determining whether to set the disclosure date of the image data designated in step S201. The Web browser 120A of the user PC 102A displays a disclosure date setting window on the basis of the window information. The Web browser 120A receives designation by user operation, and notifies the photo site 105 of the designation. The photo site 105 receives from the user the designation of whether to set the disclosure date of the image data. If NO in step S202, the photo site 105 advances to processing in step S211. Step S203: If YES in step S202, the photo site 105 transmits to the user PC 102A window information for inputting a disclosure date and disclosure mode for disclosing the image data. The Web browser 120A of the user PC 102A displays a window 300 for setting a disclosure date and disclosure mode as shown in FIG. 3 on the basis of the window information. In the window 300, a year, month, and date are input to disclosure date regions 301 to 303. Note that the time may be input. A disclosure mode is set in a region 304. In the embodiment, the disclosure mode can be set from an “image processing mode” 305 in which image data undergoes processing such as mosaic processing, emboss processing, or wipe processing, a “sequential image disclosure mode” 306 in which a plurality of image data are sequentially disclosed, and a “non-effect mode” 307 in which no effect is particularly set in disclosure. If an OK button 308 is clicked, the photo site 105 is notified of information on the disclosure mode that is input in the window 300. The window 300 stores the information in the information DB 118. The photo site 105 provides the user PC 102A with window information corresponding to the selected one of the modes 305 to 307. If a setting stop button 309 is clicked, the photo site 105 provides the user PC 102A with window information of a contact address window for notifying the user of normal disclosure of image data. If a cancel button 310 is clicked, all processes interrupt. Step S204: The photo site 105 determines whether the disclosure mode set in step S203 is the image processing mode. Step S205: If YES in step S204, the photo site 105 transmits to the user PC 102A window information for designating the type of image processing to be performed for image data and an interval until image processing is updated. The Web browser 120A of the user PC 102A displays a window 400 for selecting an image processing type and processing update interval as shown in FIG. 4 on the basis of the window information. In the window 400, the disclosure date set in step S203 is displayed in a region 401. Reference numeral 402 denotes a pull-down list for selecting a processing update interval. Selection items in the pull-down list 402 are automatically created by the module of the photo site 105 on the basis of the number of days till the disclosure date 401 from the setting date. For example, “everyday, every other day, every five days” are automatically created when the number of days till the disclosure date from the setting date is 10. “Every month, every three months, or every six months” are automatically created for one year. Reference numeral 403 denotes a pull-down list for selecting an image processing type. In the embodiment, selection items in the pull-down list 403 are, e.g., mosaic processing, emboss processing, and wipe processing processible by the photo site 105. Reference numeral 404 denotes a preview window which prompts the user to confirm an example of performing image processing selected from the pull-down list 403 for sample image data. If an OK button 405 is clicked, the Web browser 120A transmits contents set in the window 400 to the photo site 105. The photo site 105 stores the contents in the information DB 118. If a cancel button 406 is clicked, a series of processes interrupt. Step S206: The photo site 105 calculates the processing degree of one image processing on the basis of the image processing update interval designated in step S206 and the disclosure date designated in step S203. The photo site 105 stores the calculated degree in the information DB 118. More specifically, assume that mosaic processing is to be performed and the processing degree of each stage is set to 100 split. Image data having undergone mosaic processing by 1,000,000 split in the first stage, 10,000 split in the second stage, and 100 split in the third stage is disclosed. In the fourth stage, original image data is disclosed. Assume that the number of pixels in each stage is 1,000,000 in disclosing image data at different numbers of pixels. Image data having 1,000,000 pixels in the first stage, 2,000,000 pixels in the second stage, and 3,000,000 pixels in the third stage is disclosed. In the fourth stage, original image data having 4,000,000 pixels is disclosed. Step S207: The photo site 105 determines whether the disclosure mode set in step S203 is the sequential image disclosure mode. Step S208: If YES in step S207, the photo site 105 transmits to the user PC 102A window information for assigning sequence numbers to a plurality of image data designated in step S201. The Web browser 120A of the user PC 102A displays a window 500 as shown in FIG. 5 for assigning sequence numbers to a plurality of image data on the basis of the window information. In the window 500, the order of current image data is displayed in a region 501. To assign a sequence number, an image data name in the region 501 is selected, and an arrow button 502 is clicked to additionally arrange the image data name in a region 504. Reference numeral 510 denotes a region in which the state of image data, e.g., whether a sequence number has already been assigned, has not been assigned, or is being assigned to the image data is previewed in assigning a sequence number. When an image data name is selected in the region 501, unselected image data 507 in the region 510 is highlighted in a “during selection” color 508. If the image data name is moved to the region 504, the “during selection” color 508 changes to a “selected” color 509. An arrow button 503 cancels an assigned sequence number. Arrow buttons 505 and 506 are used to change a sequence number in an ascending or descending order in the region 504. If an OK button 511 is clicked, settings in the window 500 are determined. If a cancel button 512 is clicked, all processes interrupt. Step S209: The photo site 105 calculates the interval between days and the number of image data to be disclosed (disclosure unit) on the basis of the disclosure date designated in step S203 and the number of image data designated in step S201. The photo site 105 stores the calculation results in the information DB 118. The photo site 105 transmits to the user PC 102A window information for notifying the user of the calculation results. The Web browser 120A of the user PC 102A displays a window 600 as shown in FIG. 6 for notifying the user of the calculation results on the basis of the window information. In the window 600, a region 601 displays the disclosure date, the setting date, the number of disclosure days, the total number of images to be disclosed, and the disclosure unit on the basis of information such as the disclosure date set in step S203, the image data disclosure order set in step S208, and the calculation results in step S209. In a region 602, image data are arranged in the order set in step S208. The user confirms setting contents displayed in the window 600, and if no problem occurs, clicks an OK button 604 to notify the photo site 105 of the settings. The photo site 105 stores the setting contents in the information DB 118. To interrupt processing, a cancel button 605 is clicked. The photo site 105 calculates the disclosure unit in step S209 in the embodiment, but the user may set an arbitrary disclosure unit. The disclosure unit need not be a predetermined number, and a different number of image data may be grouped as a disclosure unit. For example, three image data are disclosed in the first stage, and five image data are newly disclosed in the second stage. The disclosure interval need not be a predetermined period, and may be changed at random such that the disclosure interval from the first stage to the second stage is three days and that from the second stage to the third stage is one week. Step S211: The photo site 105 transmits to the user PC 102A window information for setting browsing user information. The Web browser 120A of the user PC 102A displays a browsing user information setting window on the basis of the window information. The Web browser 120A receives inputs such as the e-mail address and name of the browsing user, and notifies the photo site 105 of them. The photo site 105 receives the e-mail address of the browsing user, and stores it in the information DB 118. The information DB 118 manages image data, albums, and users by assigning IDs. Various pieces of information and processed image data which are stored in the steps of the flow shown in FIG. 2 are stored in correspondence with original image data, albums, and users. FIG. 7 is a flow chart showing a processing sequence of disclosing image data of the user to the browsing user in the photo site 105 according to the embodiment. Step S701: The photo site 105 acquires the time in the information providing system from an OS (Operating System) installed in the server. The photo site 105 compares the acquired time with disclosure date information which is set in step S203 and stored in the information DB 118. Step S702: If the time in the system coincides with the disclosure date information as a result of comparison in step S701, the photo site 105 executes processing for disclosing original image data. The photo site 105 creates Web page information for displaying one or a plurality of original image data stored in the image DB 117, in the Web browser of the user PC 102A. The photo site 105 assigns the URL generated in step S201 to the Web page information. Step S703: If the time in the system does not, coincide with the disclosure date information as a result of comparison in step S701, the server of the photo site 105 looks up the information DB 118, and determines whether the disclosure mode is set to the image processing mode. Step S704: If YES in step S703, the server in the photo site 105 acquires the image processing update interval which is set in step S205 and stored in the information DB 118. The server calculates an update date. Step S705: The server in the photo site 105 compares the time in the system with the update date calculated in step S704. If the time in the system does not coincide with the update date as a result of comparison in step S705, a series of processes end. Step S706: If the time in the system coincides with the update date as a result of comparison in step S705, the server of the photo site 105 acquires the image processing type which is set in step S205 and stored in the information DB 118. The server executes processing of the acquired type (mosaic processing, emboss processing, or wipe processing) for image data. In this case, the server calculates the stage number of the current processing on the basis of update date information and disclosure date information. The server acquires the processing degree which is calculated in step S206 and stored in the information DB 118. The server performs processing for image data on the basis of the stage number and processing degree, and stores the processed image data in the image DB 117. The server creates a Web page for displaying the processed image data stored in the image DB 117, in the Web browser 120A of the user PC 102A. The server assigns the URL generated in step S201 to the Web page. In this manner, stepwise processing is periodically repeated to gradually disclose almost the same image data as original image data till the disclosure date. The original image data is finally disclosed on the disclosure date. Step S707: The server of the photo site 105 looks up the information DB 118, and determines whether the disclosure mode is the sequential image disclosure mode. Step S708: If YES in step S707, the server in the photo site 105 acquires the disclosure unit which is set in step S209 and stored in the information DB 118. The server calculates a partial disclosure date. Step S709: The server in the photo site 105 compares the time in the system with the partial disclosure date calculated in step S708. If the time in the system does not coincide with the partial disclosure date as a result of comparison in step S709, a series of processes end. Step S710: If the time in the system coincides with the partial disclosure date as a result of comparison in step S709, the server of the photo site 105 acquires the disclosure order and disclosure unit which are assigned in step S209 and stored in the information DB 118. The server creates Web page information for displaying the disclosure number of image data stored in the image DB 117 in the disclosure order, in the Web browser 120A of the user PC 102A. Step S711: The server of the photo site 105 acquires the e-mail address of the browsing user from the information DB 118. The Web browser 120A creates e-mail which describes a URL necessary to access the Web page created in step S702, S706, or S710, and sends the e-mail to the e-mail address of the browsing user. If necessary, a password is also described in the e-mail. The browsing user who has received the e-mail from the photo site 105 activates a Web browser 120B of his/her user PC 102B, accesses the Internet 104, and inputs the URL described in the e-mail to the Web browser 120B of the user PC 102B. The Web browser can display original image data, processed image data having undergone image processing, or some of a plurality of image data in accordance with the description of the Web page information. By assigning a URL in this fashion, processed image data of original image data, a plurality of image data contained in an album, and the original image data can be disclosed with the same URL. By repeating the above-described disclosure processing, the browsing user can browse image data which gradually approaches the original quality, and finally browse the original image data. Alternatively, the browsing user can sequentially browse a plurality of image data contained in an album, and finally browse all image data contained in the album. In the present invention, image data is processed in step S706 on an update date to create and save processed image data. The present invention is not limited to this, and image data may undergo processes in a plurality of stages before an update date to create and save a plurality of processed image data. In this case, a Web page for displaying, of processed image data saved in advance, processed image data before the update date that corresponds to an acquisition date in the system is created in step S706. As described above, according to the present invention, a network server performs stepwise editing processing along the lapse of time for original image data of the user. The server also discloses the edited image data to a third party. The user can easily disclose the image data with a representation effect to a third party. The object of the present invention is also achieved when a storage medium (or recording medium) which stores software program codes for realizing the functions of the above-described embodiment is supplied to a system or apparatus, and the computer (or the CPU or MPU) of the system or apparatus reads out and executes the program codes stored in the storage medium. In this case, the program codes read out from the storage medium realize the functions of the above-described embodiment, and the storage medium which stores the program codes constitutes the present invention. The functions of the above-described embodiment are realized when the computer executes the readout program codes. Also, the functions of the above-described embodiment are realized when an OS (Operating System) or the like running on the computer performs part or all of actual processing on the basis of the instructions of the program codes. Furthermore, the present invention includes a case in which, after the program codes read out from the storage medium are written in the memory of a function expansion card inserted into the computer or the memory of a function expansion unit connected to the computer, the CPU of the function expansion card or function expansion unit performs part or all of actual processing on the basis of the instructions of the program codes and thereby realizes the functions of the above-described embodiment. When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flow charts. As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.	G	60G06	161G06F	15	16
11840743	US20090049317A1-20090219	Managing Power in a Parallel Computer	ACCEPTED	20090205	20090219	[]	G06F132	["G06F132"]	7877620	20070817	20110125	713	320000	58660.0	CHOUDHURY	ZAHID	[{"inventor_name_last": "Gara", "inventor_name_first": "Alan", "inventor_city": "Mount Kisco", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Gooding", "inventor_name_first": "Thomas M.", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Inglett", "inventor_name_first": "Todd A.", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Liebsch", "inventor_name_first": "Thomas A.", "inventor_city": "Arlington", "inventor_state": "SD", "inventor_country": "US"}, {"inventor_name_last": "Musta", "inventor_name_first": "Thomas E.", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}]	Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes.	1. A method of managing power in a parallel computer, the parallel computer comprising a power supply and a plurality of compute nodes, each compute node comprising a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through a plurality of direct current to direct current (‘DC-DC’) converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor, the method comprising: monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. 2. The method of claim 1 wherein the power consumption ratios further comprises a ratio of execution cycles to idle cycles. 3. The method of claim 2 further comprising setting, by a service node connected to the plurality of compute nodes through an out-of-band service network, the power consumption ratios, including setting a length of time for the idle cycles. 4. The method of claim 1 wherein the computer processor power consumption ratio is equal to the computer memory power consumption ratio. 5. The method of claim 1 wherein the computer processor power consumption ratio is not equal to the computer memory power consumption ratio. 6. The method of claim 1 wherein the plurality of compute nodes are connected for data communications through a plurality of data communications networks, at least one data communications network optimized for point to point data communications and at least one data communications network optimized for collective operations. 7. Apparatus for managing power in a parallel computer, the parallel computer comprising a power supply and a plurality of compute nodes, each compute node comprising a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through a plurality of direct current to direct current (‘DC-DC’) converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions capable of: monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. 8. The apparatus of claim 7 wherein the power consumption ratios further comprises a ratio of execution cycles to idle cycles. 9. The apparatus of claim 8 further comprising computer program instructions capable of setting, by a service node connected to the plurality of compute nodes through an out-of-band service network, the power consumption ratios, including setting a length of time for the idle cycles. 10. The apparatus of claim 7 wherein the computer processor power consumption ratio is equal to the computer memory power consumption ratio. 11. The apparatus of claim 7 wherein the computer processor power consumption ratio is not equal to the computer memory power consumption ratio. 12. The apparatus of claim 7 wherein the plurality of compute nodes are connected for data communications through a plurality of data communications networks, at least one data communications network optimized for point to point data communications and at least one data communications network optimized for collective operations. 13. A computer program product for managing power in a parallel computer, the parallel computer comprising a power supply and a plurality of compute nodes, each compute node comprising a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through a plurality of direct current to direct current (‘DC-DC’) converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor, the computer program product disposed in a signal bearing medium, the computer program product comprising computer program instructions capable of: monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. 14. The computer program product of claim 13 wherein the power consumption ratios further comprises a ratio of execution cycles to idle cycles. 15. The computer program product of claim 14 further comprising computer program instructions capable of setting, by a service node connected to the plurality of compute nodes through an out-of-band service network, the power consumption ratios, including setting a length of time for the idle cycles. 16. The computer program product of claim 13 wherein the computer processor power consumption ratio is equal to the computer memory power consumption ratio. 17. The computer program product of claim 13 wherein the computer processor power consumption ratio is not equal to the computer memory power consumption ratio. 18. The computer program product of claim 13 wherein the plurality of compute nodes are connected for data communications through a plurality of data communications networks, at least one data communications network optimized for point to point data communications and at least one data communications network optimized for collective operations. 19. The computer program product of claim 13 wherein the signal bearing medium comprises a recordable medium. 20. The computer program product of claim 13 wherein the signal bearing medium comprises a transmission medium.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The field of the invention is data processing, or, more specifically, methods, apparatus, and products for managing power in a parallel computer. 2. Description of Related Art The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago. Parallel computing is an area of computer technology that has experienced advances. Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination. Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes. Parallel algorithms are valuable because it is faster to perform some kinds of large computing tasks via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost. Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm. Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic. Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent, and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers. A torus network lends itself to point to point operations, but a tree network typically is inefficient in point to point communication. A tree network, however, does provide high bandwidth and low latency for certain collective operations, message passing operations where all compute nodes participate simultaneously. Because a parallel computer may include many thousands of compute nodes operating simultaneously during a job, a parallel computer may consume a large amount of power. Electricity providers typically charge a customer at a higher rate than normal after the customer consumes an amount of power greater than a particular amount, the peak power amount. Parallel computers, due to the large number of compute nodes that operate simultaneously during a job, often consume more than the peak power amount. As such, readers will appreciate that room for improvement exists in managing power in a parallel computer.	<SOH> SUMMARY OF THE INVENTION <EOH>Methods, apparatus, and products are disclosed for managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, each compute node including a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through a plurality of direct current to direct current (‘DC-DC’) converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.	BACKGROUND OF THE INVENTION 1. Field of the Invention The field of the invention is data processing, or, more specifically, methods, apparatus, and products for managing power in a parallel computer. 2. Description of Related Art The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago. Parallel computing is an area of computer technology that has experienced advances. Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination. Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes. Parallel algorithms are valuable because it is faster to perform some kinds of large computing tasks via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost. Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm. Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic. Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent, and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers. A torus network lends itself to point to point operations, but a tree network typically is inefficient in point to point communication. A tree network, however, does provide high bandwidth and low latency for certain collective operations, message passing operations where all compute nodes participate simultaneously. Because a parallel computer may include many thousands of compute nodes operating simultaneously during a job, a parallel computer may consume a large amount of power. Electricity providers typically charge a customer at a higher rate than normal after the customer consumes an amount of power greater than a particular amount, the peak power amount. Parallel computers, due to the large number of compute nodes that operate simultaneously during a job, often consume more than the peak power amount. As such, readers will appreciate that room for improvement exists in managing power in a parallel computer. SUMMARY OF THE INVENTION Methods, apparatus, and products are disclosed for managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, each compute node including a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through a plurality of direct current to direct current (‘DC-DC’) converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an exemplary system for managing power in a parallel computer according to embodiments of the present invention. FIG. 2 sets forth a block diagram of an exemplary compute node useful in managing power in a parallel computer according to embodiments of the present invention. FIG. 3A illustrates an exemplary Point To Point Adapter useful in systems capable of managing power in a parallel computer according to embodiments of the present invention. FIG. 3B illustrates an exemplary Global Combining Network Adapter useful in systems capable of managing power in a parallel computer according to embodiments of the present invention. FIG. 4 sets forth a line drawing illustrating an exemplary data communications network optimized for point to point operations useful in systems capable of managing power in a parallel computer in accordance with embodiments of the present invention. FIG. 5 sets forth a line drawing illustrating an exemplary data communications network optimized for collective operations useful in systems capable of managing power in a parallel computer in accordance with embodiments of the present invention. FIG. 6 sets forth a flow chart illustrating an exemplary method for managing power in a parallel computer according to embodiments of the present invention. FIG. 7 sets forth a flow chart illustrating a further exemplary method for managing power in a parallel computer according to embodiments of the present invention. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Exemplary methods, apparatus, and computer program products for managing power in a parallel computer according to embodiments of the present invention are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 illustrates an exemplary system for managing power in a parallel computer according to embodiments of the present invention. The system of FIG. 1 includes a parallel computer (100), non-volatile memory for the computer in the form of data storage device (118), an output device for the computer in the form of printer (120), and an input/output device for the computer in the form of computer terminal (122). Parallel computer (100) in the example of FIG. 1 includes a plurality of compute nodes (102). The compute nodes (102) are coupled for data communications by several independent data communications networks including a high speed Ethernet network (174), a Joint Test Action Group (‘JTAG’) network (104), a global combining network (106) which is optimized for collective operations, and a torus network (108) which is optimized point to point operations. The global combining network (106) is a data communications network that includes data communications links connected to the compute nodes so as to organize the compute nodes as a tree. Each data communications network is implemented with data communications links among the compute nodes (102). The data communications links provide data communications for parallel operations among the compute nodes of the parallel computer. In addition, the compute nodes (102) of parallel computer are organized into at least one operational group (132) of compute nodes. An operational group of compute nodes is a subset of all compute nodes and I/O nodes in the parallel computer that participate in carrying out a job. Operational groups may be configured for collective parallel operations or point-to-point operations. Collective operations are implemented with data communications among the compute nodes of an operational group. Collective operations are those functions that involve all the compute nodes of an operational group. A collective operation is an operation, a message-passing computer program instruction that is executed simultaneously, that is, at approximately the same time, by all the compute nodes in an operational group of compute nodes. Such an operational group may include all the compute nodes in a parallel computer (100) or a subset all the compute nodes. Collective operations are often built around point to point operations. A collective operation requires that all processes on all compute nodes within an operational group call the same collective operation with matching arguments. A ‘broadcast’ is an example of a collective operation for moving data among compute nodes of an operational group. A ‘reduce’ operation is an example of a collective operation that executes arithmetic or logical functions on data distributed among the compute nodes of an operational group. An operational group may be implemented as, for example, an MPI ‘communicator.’ ‘MPI’ refers to ‘Message Passing Interface,’ a prior art parallel communications library, a module of computer program instructions for data communications on parallel computers. Examples of prior-art parallel communications libraries that may be improved for use with systems according to embodiments of the present invention include MPI and the ‘Parallel Virtual Machine’ (‘PVM’) library. PVM was developed by the University of Tennessee, The Oak Ridge National Laboratory, and Emory University. MPI is promulgated by the MPI Forum, an open group with representatives from many organizations that define and maintain the MPI standard. MPI at the time of this writing is a de facto standard for communication among compute nodes running a parallel program on a distributed memory parallel computer. This specification sometimes uses MPI terminology for ease of explanation, although the use of MPI as such is not a requirement or limitation of the present invention. Some collective operations have a single originating or receiving process running on a particular compute node in an operational group. For example, in a ‘broadcast’ collective operation, the process on the compute node that distributes the data to all the other compute nodes is an originating process. In a ‘gather’ operation, for example, the process on the compute node that received all the data from the other compute nodes is a receiving process. The compute node on which such an originating or receiving process runs is referred to as a logical root. Most collective operations are variations or combinations of four basic operations: broadcast, gather, scatter, and reduce. The interfaces for these collective operations are defined in the MPI standards promulgated by the MPI Forum. Algorithms for executing collective operations, however, are not defined in the MPI standards. In a broadcast operation, all processes specify the same root process, whose buffer contents will be sent. Processes other than the root specify receive buffers. After the operation, all buffers contain the message from the root process. In a scatter operation, the logical root divides data on the root into segments and distributes a different segment to each compute node in the operational group. In scatter operation, all processes typically specify the same receive count. The send arguments are only significant to the root process, whose buffer actually contains sendcount*N elements of a given data type, where N is the number of processes in the given group of compute nodes. The send buffer is divided and dispersed to all processes (including the process on the logical root). Each compute node is assigned a sequential identifier termed a ‘rank.’ After the operation, the root has sent sendcount data elements to each process in increasing rank order. Rank 0 receives the first sendcount data elements from the send buffer. Rank 1 receives the second sendcount data elements from the send buffer, and so on. A gather operation is a many-to-one collective operation that is a complete reverse of the description of the scatter operation. That is, a gather is a many-to-one collective operation in which elements of a datatype are gathered from the ranked compute nodes into a receive buffer in a root node. A reduce operation is also a many-to-one collective operation that includes an arithmetic or logical function performed on two data elements. All processes specify the same ‘count’ and the same arithmetic or logical function. After the reduction, all processes have sent count data elements from computer node send buffers to the root process. In a reduction operation, data elements from corresponding send buffer locations are combined pair-wise by arithmetic or logical operations to yield a single corresponding element in the root process's receive buffer. Application specific reduction operations can be defined at runtime. Parallel communications libraries may support predefined operations. MPI, for example, provides the following pre-defined reduction operations: MPI_MAX maximum MPI_MIN minimum MPI_SUM sum MPI_PROD product MPI_LAND logical and MPI_BAND bitwise and MPI_LOR logical or MPI_BOR bitwise or MPI_LXOR logical exclusive or MPI_BXOR bitwise exclusive or In addition to compute nodes, the parallel computer (100) includes input/output (‘I/O’) nodes (110, 114) coupled to compute nodes (102) through one of the data communications networks (174, 106). The I/O nodes (110, 114) provide I/O services between compute nodes (102) and I/O devices (118, 120, 122). I/O nodes (110, 114) are connected for data communications I/O devices (118, 120, 122) through local area network (‘LAN’) (130). The parallel computer (100) also includes a service node (116) coupled to the compute nodes through one of the networks (104). Service node (116) provides service common to pluralities of compute nodes, loading programs into the compute nodes, starting program execution on the compute nodes, retrieving results of program operations on the computer nodes, and so on. Service node (116) runs a service application (124) and communicates with users (128) through a service application interface (126) that runs on computer terminal (122). As described in more detail below in this specification, the system of FIG. 1 operates generally for managing power in a parallel computer according to embodiments of the present invention. The system of FIG. 1 includes a power supply (134) that powers the compute nodes (102) through a plurality of direct current to direct current (‘DC-DC’) converters (136). Each DC-DC converter of FIG. 1 is configured with a current sensor. Each DC-DC converter supplies current to an assigned group compute nodes. Although each DC-DC converter (136) in the system is depicted as supplying current to eight compute nodes readers of skill in the art will recognize that DC-DC converters useful for managing power in a parallel computer according to embodiments of the present invention may supply current to an assigned group comprising any number of compute nodes. In some embodiments, for example, five DC-DC converters supply power to a group of 32 computer processors in 32 compute nodes while three other DC-DC converters supply power to computer memory in each of the same 32 compute nodes. The system of FIG. 1 operates generally for managing power in a parallel computer according to embodiments of the present invention. The system of FIG. 1 is capable of monitoring, by the current sensor in each DC-DC converter, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied to its assigned group of compute nodes is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes in response to the determination that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and responsive to the notification to reduce power consumption, reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes, the power consumption ratios including a computer processor power consumption ratio and a computer memory power consumption ratio. Power consumption ratios are parameters for controlling a compute nodes node's power consumption during execution of computer program instructions. The power consumption ratios may be expressed as a ratio of execution cycles to idle cycles. An execution cycle is the period in which the computer memory or computer processor executes an instruction. That is, an execution cycle is the period in which the computer memory or computer processor is active. An idle cycle, in contrast, is a period in which the computer processor or computer memory is idle, that is, not executing any instruction. When idling, neither the computer processor nor the computer memory is consuming power, thereby reducing the compute node's power consumption. The arrangement of nodes, networks, and I/O devices making up the exemplary system illustrated in FIG. 1 are for explanation only, not for limitation of the present invention. Data processing systems capable of managing power in a parallel computer according to embodiments of the present invention may include additional nodes, networks, devices, and architectures, not shown in FIG. 1, as will occur to those of skill in the art. Although the parallel computer (100) in the example of FIG. 1 includes sixteen compute nodes (102), readers will note that parallel computers capable of managing power in a parallel computer according to embodiments of the present invention may include any number of compute nodes. In addition to Ethernet and JTAG, networks in such data processing systems may support many data communications protocols including for example TCP (Transmission Control Protocol), IP (Internet Protocol), and others as will occur to those of skill in the art. Various embodiments of the present invention may be implemented on a variety of hardware platforms in addition to those illustrated in FIG. 1. Managing power in a parallel computer according to embodiments of the present invention may be generally implemented on a parallel computer that includes a plurality of compute nodes. In fact, such computers may include thousands of such compute nodes. Each compute node is in turn itself a kind of computer composed of one or more computer processors, its own computer memory, and its own input/output adapters. For further explanation, therefore, FIG. 2 sets forth a block diagram of an exemplary compute node useful in managing power in a parallel computer according to embodiments of the present invention. The compute node (152) of FIG. 2 includes one or more computer processors (164) as well as random access memory (‘RAM’) (156). The processors (164) are connected to RAM (156) through a high-speed memory bus (154) and through a bus adapter (194) and an extension bus (168) to other components of the compute node (152). Stored in RAM (156) is an application program (158), a module of computer program instructions that carries out parallel, user-level data processing using parallel algorithms. The application (158) of FIG. 2 allocates an application buffer for storing a message for transmission to another compute node. Also stored in RAM (156) is a messaging module (160), a library of computer program instructions that carry out parallel communications among compute nodes, including point to point operations as well as collective operations. Application program (158) executes collective operations by calling software routines in the messaging module (160). A library of parallel communications routines may be developed from scratch for use in systems according to embodiments of the present invention, using a traditional programming language such as the C programming language, and using traditional programming methods to write parallel communications routines that send and receive data among nodes on two independent data communications networks. Alternatively, existing prior art libraries may be improved to operate according to embodiments of the present invention. Examples of prior-art parallel communications libraries include the ‘Message Passing Interface’ (‘MPI’) library and the ‘Parallel Virtual Machine’ (‘PVM’) library. Also stored in RAM (156) is an operating system (162), a module of computer program instructions and routines for an application program's access to other resources of the compute node. It is typical for an application program and parallel communications library in a compute node of a parallel computer to run a single thread of execution with no user login and no security issues because the thread is entitled to complete access to all resources of the node. The quantity and complexity of tasks to be performed by an operating system on a compute node in a parallel computer therefore are smaller and less complex than those of an operating system on a serial computer with many threads running simultaneously. In addition, there is no video I/O on the compute node (152) of FIG. 2, another factor that decreases the demands on the operating system. The operating system may therefore be quite lightweight by comparison with operating systems of general purpose computers, a pared down version as it were, or an operating system developed specifically for operations on a particular parallel computer. Operating systems that may usefully be improved, simplified, for use in a compute node include UNIX™, Linux™, Microsoft XP™, AIX™, IBM's i5/OS™, and others as will occur to those of skill in the art. Also stored in RAM (156) is a power management application program (158) a module of compute program instructions capable of managing power in a parallel computer according to embodiments of the present application. The power management application program (158) of FIG. 2 includes computer program instructions capable of reducing power consumption of the compute node (152) in accordance with the power consumption ratios (626), including a computer processor power consumption ratio (628) and a computer memory power consumption ratio (630). Power consumption ratios are parameters for controlling a compute node's power consumption during execution of computer program instructions. The power management application program reduces power consumption of the compute node (152) in response to notification received from a DC-DC converter. The exemplary compute node (152) of FIG. 2 includes several communications adapters (172, 176, 180, 188) for implementing data communications with other nodes of a parallel computer. Such data communications may be carried out serially through RS-232 connections, through external buses such as USB, through data communications networks such as IP networks, and in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a network. Examples of communications adapters useful in systems for managing power in a parallel computer according to embodiments of the present invention include modems for wired communications, Ethernet (IEEE 802.3) adapters for wired network communications, and 802.11b adapters for wireless network communications. The data communications adapters in the example of FIG. 2 include a Gigabit Ethernet adapter (172) that couples example compute node (152) for data communications to a Gigabit Ethernet (174). Gigabit Ethernet is a network transmission standard, defined in the IEEE 802.3 standard, that provides a data rate of 1 billion bits per second (one gigabit). Gigabit Ethernet is a variant of Ethernet that operates over multimode fiber optic cable, single mode fiber optic cable, or unshielded twisted pair. The data communications adapters in the example of FIG. 2 includes a JTAG Slave circuit (176) that couples example compute node (152) for data communications to a JTAG Master circuit (178). JTAG is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. JTAG is so widely adapted that, at this time, boundary scan is more or less synonymous with JTAG. JTAG is used not only for printed circuit boards, but also for conducting boundary scans of integrated circuits, and is also useful as a mechanism for debugging embedded systems, providing a convenient “back door” into the system. The example compute node of FIG. 2 may be all three of these: It typically includes one or more integrated circuits installed on a printed circuit board and may be implemented as an embedded system having its own processor, its own memory, and its own I/O capability. JTAG boundary scans through JTAG Slave (176) may efficiently configure processor registers and memory in compute node (152) for use in managing power in a parallel computer according to embodiments of the present invention. The data communications adapters in the example of FIG. 2 includes a Point To Point Adapter (180) that couples example compute node (152) for data communications to a network (108) that is optimal for point to point message passing operations such as, for example, a network configured as a three-dimensional torus or mesh. Point To Point Adapter (180) provides data communications in six directions on three communications axes, x, y, and z, through six bidirectional links: +x (181), −x (182), +y (183), −y (184), +z (185), and −z (186). The data communications adapters in the example of FIG. 2 includes a Global Combining Network Adapter (188) that couples example compute node (152) for data communications to a network (106) that is optimal for collective message passing operations on a global combining network configured, for example, as a binary tree. The Global Combining Network Adapter (188) provides data communications through three bidirectional links: two to children nodes (190) and one to a parent node (192). Example compute node (152) includes two arithmetic logic units (‘ALUs’). ALU (166) is a component of processor (164), and a separate ALU (170) is dedicated to the exclusive use of Global Combining Network Adapter (188) for use in performing the arithmetic and logical functions of reduction operations. Computer program instructions of a reduction routine in parallel communications library (160) may latch an instruction for an arithmetic or logical function into instruction register (169). When the arithmetic or logical function of a reduction operation is a ‘sum’ or a ‘logical or,’ for example, Global Combining Network Adapter (188) may execute the arithmetic or logical operation by use of ALU (166) in processor (164) or, typically much faster, by use dedicated ALU (170). For further explanation, FIG. 3A illustrates an exemplary Point To Point Adapter (180) useful in systems capable of managing power in a parallel computer according to embodiments of the present invention. Point To Point Adapter (180) is designed for use in a data communications network optimized for point to point operations, a network that organizes compute nodes in a three-dimensional torus or mesh. Point To Point Adapter (180) in the example of FIG. 3A provides data communication along an x-axis through four unidirectional data communications links, to and from the next node in the −x direction (182) and to and from the next node in the +x direction (181). Point To Point Adapter (180) also provides data communication along a y-axis through four unidirectional data communications links, to and from the next node in the −y direction (184) and to and from the next node in the +y direction (183). Point To Point Adapter (180) in FIG. 3A also provides data communication along a z-axis through four unidirectional data communications links, to and from the next node in the −z direction (186) and to and from the next node in the +z direction (185). For further explanation, FIG. 3B illustrates an exemplary Global Combining Network Adapter (188) useful in systems capable of managing power in a parallel computer according to embodiments of the present invention. Global Combining Network Adapter (188) is designed for use in a network optimized for collective operations, a network that organizes compute nodes of a parallel computer in a binary tree. Global Combining Network Adapter (188) in the example of FIG. 3B provides data communication to and from two children nodes through four unidirectional data communications links (190). Global Combining Network Adapter (188) also provides data communication to and from a parent node through two unidirectional data communications links (192). For further explanation, FIG. 4 sets forth a line drawing illustrating an exemplary data communications network (108) optimized for point to point operations useful in systems capable of managing power in a parallel computer in accordance with embodiments of the present invention. In the example of FIG. 4, dots represent compute nodes (102) of a parallel computer, and the dotted lines between the dots represent data communications links (103) between compute nodes. The data communications links (103) are implemented with point to point data communications adapters similar to the one illustrated for example in FIG. 3A, with data communications links on three axes, x, y, and z, and to and fro in six directions +x (181), −x (182), +y (183), −y (184), +z (185), and −z (186). The links and compute nodes are organized by this data communications network optimized for point to point operations into a three dimensional mesh (105). The mesh (105) has wrap-around links on each axis that connect the outermost compute nodes in the mesh (105) on opposite sides of the mesh (105). These wrap-around links form part of a torus (107). Each compute node in the torus has a location in the torus that is uniquely specified by a set of x, y, z coordinates. Readers will note that the wrap-around links in the y and z directions have been omitted for clarity, but are configured in a similar manner to the wrap-around link illustrated in the x direction. For clarity of explanation, the data communications network of FIG. 4 is illustrated with only 27 compute nodes, but readers will recognize that a data communications network optimized for point to point operations for use in managing power in a parallel computer in accordance with embodiments of the present invention may contain only a few compute nodes or may contain thousands of compute nodes. For further explanation, FIG. 5 sets forth a line drawing illustrating an exemplary data communications network (106) optimized for collective operations useful in systems capable of managing power in a parallel computer in accordance with embodiments of the present invention. The example data communications network of FIG. 5 includes data communications links connected to the compute nodes so as to organize the compute nodes as a tree. In the example of FIG. 5, dots represent compute nodes (102) of a parallel computer, and the dotted lines (103) between the dots represent data communications links between compute nodes. The data communications links are implemented with global combining network adapters similar to the one illustrated for example in FIG. 3B, with each node typically providing data communications to and from two children nodes and data communications to and from a parent node, with some exceptions. Nodes in a binary tree (106) may be characterized as a physical root node (202), branch nodes (204), and leaf nodes (206). The root node (202) has two children but no parent. The leaf nodes (206) each has a parent, but leaf nodes have no children. The branch nodes (204) each has both a parent and two children. The links and compute nodes are thereby organized by this data communications network optimized for collective operations into a binary tree (106). For clarity of explanation, the data communications network of FIG. 5 is illustrated with only 31 compute nodes, but readers will recognize that a data communications network optimized for collective operations for use in systems for managing power in a parallel computer with embodiments of the present invention may contain only a few compute nodes or may contain thousands of compute nodes. In the example of FIG. 5, each node in the tree is assigned a unit identifier referred to as a ‘rank’ (250). A node's rank uniquely identifies the node's location in the tree network for use in both point to point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with 0 assigned to the root node (202), 1 assigned to the first node in the second layer of the tree, 2 assigned to the second node in the second layer of the tree, 3 assigned to the first node in the third layer of the tree, 4 assigned to the second node in the third layer of the tree, and so on. For ease of illustration, only the ranks of the first three layers of the tree are shown here, but all compute nodes in the tree network are assigned a unique rank. For further explanation, FIG. 6 sets forth a flow chart illustrating an exemplary method for managing power in a parallel computer according to embodiments of the present invention. The parallel computer includes a plurality of compute nodes (102). Each compute node (102) includes a computer processor and computer memory operatively coupled to the computer processor. The parallel computer also includes a power supply (134 on FIG. 1) that powers the compute nodes (102) through a plurality of DC-DC converters (136). Each DC-DC converter (136) supplies current to an assigned group (624) of compute nodes (102). Each DC-DC converter includes a current sensor (602). In some embodiments the plurality of compute nodes (102) are connected for data communications through a plurality of data communications networks. The plurality data communications networks may include a data communications network optimized for point to point data communications (104 on FIG. 1). The plurality of data communications networks may also include a data communications network optimized for collective operations (106 on FIG. 1). The method of FIG. 6 includes monitoring (604), by the current sensor (602) in each DC-DC converter (136), an amount (606) of current supplied by that DC-DC converter (136) to its assigned group (624) of compute nodes (102). Monitoring (604), by the current sensor (602) in each DC-DC converter (136), an amount (606) of current supplied by that DC-DC converter (136) to its assigned group (624) of compute nodes (102) may be carried out by periodically summing the amounts of current supplied to each individual compute node (102) in the assigned group (624). The current sensor (602) in the DC-DC converter (136), for example, may be configured to continually sense the current supplied to each compute in its assigned group. If a DC-DC converter supplies current to 8 different compute nodes then the current sensor continually senses 8 different amounts of current, one amount for each compute node in the assigned group. The method of FIG. 6 also includes determining (610), by at least one DC-DC converter (136), that the amount (606) of current supplied to its assigned group (624) of compute nodes (102) is greater than a predefined threshold value (608). Determining (610), by at least one DC-DC converter (136), that the amount (606) of current supplied to its assigned group (624) of compute nodes (102) is greater than a predefined threshold value (608) may be carried out by periodically comparing the amount of current (606) and the predefined threshold value (608). DC-DC converters useful for managing power in a parallel computer according to embodiments of the present invention may be configured with a predefined threshold value. The predefined threshold value represents the maximum amount of current a DC-DC converter may supply to its assigned group before a reduction in power consumption in the compute nodes is required. Although many DC-DC converters may supply power to many assigned groups of compute nodes in a parallel computer it is only necessary that one DC-DC converter determine that the predefined threshold has been exceeded. That is, a single DC-DC converter may initiate a power reduction in many compute nodes, even compute nodes not part of that DC-DC converter's assigned group. The method of FIG. 6 also includes sending (614), by the at least one DC-DC converter (136) to the plurality of compute nodes (102) in response to the determination (612) that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt (620), including notifying (616) the plurality of compute nodes (102) to reduce power consumption. Sending (614), by the at least one DC-DC converter (136) to the plurality of compute nodes (102) in response to the determination (612) that the amount of current supplied to its assigned group of compute nodes is greater than the predetermined threshold value, a global interrupt (620), including notifying (616) the plurality of compute nodes (102) to reduce power consumption is carried out by raising the global interrupt on a global interrupt network. A global interrupt network is a network connecting compute nodes and other devices in the parallel computer that allows a single compute node or device to raise an interrupt on all compute nodes connected to the network. Global interrupt networks useful for managing power in a parallel computer according to embodiments of the present invention may be implemented in many topologies as will occur to those of skill in the art including, for example, a tree topology. When a global interrupt is raised at any point within the network the global interrupt is propagated throughout the network to all compute nodes. The method of FIG. 6 also includes, responsive to the notification (622) to reduce power consumption, reducing (632), by the plurality of compute nodes (102) in accordance with power consumption ratios (626), power consumption of the compute nodes (102), the power consumption ratios (626) including a computer processor power consumption ratio (628) and a computer memory power consumption ratio (630). Reducing power consumption of the compute nodes may be carried out by operating the computer processor and computer memory in accordance with the power consumption ratios. Power consumption ratios are parameters for controlling a compute node's power consumption during execution of computer program instructions. The power consumption ratios are expressed as a ratio of execution cycles to idle cycles. An execution cycle is the period in which the computer memory or computer processor executes an instruction. That is, an execution cycle is the period in which the computer memory or computer processor is active. An idle cycle, in contrast, is a period in which the computer processor or computer memory is idle, that is, not executing any instruction. When idling, neither the computer processor nor the computer memory is consuming power, thereby reducing the compute node's power consumption. For further explanation, FIG. 7 sets forth a flow chart illustrating a further exemplary method for managing power in a parallel computer according to embodiments of the present invention. The method of FIG. 7 is similar to the method of FIG. 6 in that the method of FIG. 7 includes monitoring (604), by the current sensor (602) in each DC-DC converter (136), an amount (606) of current supplied by that DC-DC converter (136) to its assigned group (624) of compute nodes (102); determining (610), by at least one DC-DC converter (136), that the amount (606) of current supplied to its assigned group (624) of compute nodes (102) is greater than a predefined threshold value (608); sending (614), by the at least one DC-DC converter (136) to the plurality of compute nodes (102) in response to the determination (612) that the amount (606) of current supplied to its assigned group (624) of compute nodes (102) is greater than the predetermined threshold value (608), a global interrupt (620), including notifying (616) the plurality of compute nodes (102) to reduce power consumption; and responsive to the notification (622) to reduce power consumption, reducing (632), by the plurality of compute nodes (102) in accordance with power consumption ratios (626), power consumption of the compute nodes (102), the power consumption ratios (626) including a computer processor power consumption ratio (628) and a computer memory power consumption ratio (630). The method of FIG. 7 differs from the method of FIG. 6, in that in the method of FIG. 7 the power consumption ratios (626) are expressed as a ratio of execution cycles (718,722) to idle cycles (722,724). Consider as an example the following power consumption ratios: computer processor power consumption ratio=1/10 computer memory power consumption ratio=2/5 During operation, the compute nodes may reduce power according to the example power consumption ratios above by the compute node's computer processor executing instructions for one cycle then idling ten cycles. The computer memory will execute instructions for two cycles then idle five cycles. The method of FIG. 7 also includes setting (702), by a service node (116) connected to the plurality of compute nodes (102) through an out-of-band service network, such as JTAG network (104 on FIG. 1), the power consumption ratios (626), including setting a length of time (730) for the idle cycles (720,724). Setting (702), by a service node (116) connected to the plurality of compute nodes (102) through an out-of-band service network, such as JTAG network (104 on FIG. 1), the power consumption ratios (626), including setting a length of time (730) for the idle cycles (720,724) may be carried out by configuring the computer memory in each compute node with the power consumption ratios (630,628) and the length of time (730) for the idle cycles. The greater the length of time of an idle cycle the longer a computer processor or computer memory in a compute node idles during such an idle cycle. In the example of FIG. 6, the idle cycle length of time (730) is set to 10 microseconds. That is, when operating in accordance with the power consumption ratios, each cycle that a computer processor or computer memory idles lasts 10 microseconds. In the example of FIG. 7 the computer processor power consumption ratio (628) may equal the computer memory power consumption ratio (630). That is, the service node may set a single ratio for the two power consumption ratios (714, 716). Alternatively, the service node may set a different ratio for each power consumption ratio. In such a case, the computer processor power consumption ratio (628) does not equal the computer memory power consumption ratio (638). Using distinct power consumption ratios (630,628) enables precise control of power consumption in the parallel computer. Exemplary embodiments of the present invention are described largely in the context of a fully functional computer system for managing power in a parallel computer. Readers of skill in the art will recognize, however, that the present invention also may be embodied in a computer program product disposed on signal bearing media for use with any suitable data processing system. Such signal bearing media may be transmission media or recordable media for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of recordable media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Examples of transmission media include telephone networks for voice communications and digital data communications networks such as, for example, Ethernets™ and networks that communicate with the Internet Protocol and the World Wide Web as well as wireless transmission media such as, for example, networks implemented according to the IEEE 802.11 family of specifications. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the invention as embodied in a program product. Persons skilled in the art will recognize immediately that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present invention. It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.	G	60G06	161G06F	1	32
10573043	US20070173999A1-20070726	Controllers for heavy duty industrial vehicle	ACCEPTED	20070712	20070726	[]	G06F1900	["G06F1900"]	7885744	20070223	20110208	701	050000	67987.0	BEAULIEU	YONEL	[{"inventor_name_last": "Shinozaki", "inventor_name_first": "Akiko", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Suzuki", "inventor_name_first": "Hiroyuki", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}]	Hardware of each of controllers (11, 12, 13) for controlling a plurality of instruments to be controlled, which are provided in a reach stacker as a heavy duty industrial vehicle, for example, a vehicle body (3), a spreader (9), and a cabin (10), is rendered common. The configuration of driver software for performing basic control is also rendered common. Only the configuration of minimum required application software is constructed to be suitable for the instrument to be controlled. Because of these features, the software of the controllers (11, 12, 13) can be easily changed. Regardless of the instrument to be controlled, as a subject of control, the controllers can be easily used for any instruments to be controlled.	1. Controllers for a heavy duty industrial vehicle, which are a plurality of controllers provided in said heavy duty industrial vehicle equipped with a working machine for performing predetermined work, said plurality of controllers being adapted to control, independently of each other, a plurality of instruments to be controlled, including said working machine, said instruments being provided in said heavy duty industrial vehicle, and characterized in that a configuration of hardware of said plurality of controllers is entirely common. 2. The controllers for a heavy duty industrial vehicle according to claim 1, characterized in that said plurality of controllers are interconnected by a network. 3. The controllers for a heavy duty industrial vehicle according to claim 1, characterized in that software for controlling each of said instruments to be controlled is of a hierarchical structure, driver software at a lower level for directly controlling each of said instruments to be controlled is common, and only application software at an upper level utilizing said driver software is different according to a function of each of said instruments to be controlled. 4. The controllers for a heavy duty industrial vehicle according to claim 3, characterized in that rewriting means is provided for making only said application software rewritable. 5. The controllers for a heavy duty industrial vehicle according to claim 1, characterized in that limited operation means is provided for enabling an operation by other said controller so that at least said heavy duty industrial vehicle can be run, even if said controller for controlling said working machine fails or is not connected to said network. 6. The controllers for a heavy duty industrial vehicle according to claim 2, characterized in that software for controlling each of said instruments to be controlled is of a hierarchical structure, driver software at a lower level for directly controlling each of said instruments to be controlled is common, and only application software at an upper level utilizing said driver software is different according to a function of each of said instruments to be controlled. 7. The controllers for a heavy duty industrial vehicle according to claim 2, characterized in that limited operation means is provided for enabling an operation by other said controller so that at least said heavy duty industrial vehicle can be run, even if said controller for controlling said working machine fails or is not connected to said network. 8. The controllers for a heavy duty industrial vehicle according to claim 3, characterized in that limited operation means is provided for enabling an operation by other said controller so that at least said heavy duty industrial vehicle can be run, even if said controller for controlling said working machine fails or is not connected to said network. 9. The controllers for a heavy duty industrial vehicle according to claim 4, characterized in that limited operation means is provided for enabling an operation by other said controller so that at least said heavy duty industrial vehicle can be run, even if said controller for controlling said working machine fails or is not connected to said network.	<SOH> BACKGROUND ART <EOH>A heavy duty industrial vehicle not only has a vehicle moving by itself, but also has a working machine unique to the vehicle. Thus, this type of industrial vehicle is adapted to be capable of performing a predetermined working action with the use of the working machine. Some of such heavy duty industrial vehicles use one controller to control not only the moving action of the vehicle, but also the working action of the working machine, thus controlling the entire vehicle. Some other heavy duty industrial vehicles have separate controllers, such as a controller for the moving action of the vehicle, and a controller for the working action of the working machine, and connect these controllers by a network to control the entire vehicle. Patent Document 1: Japanese Patent Application Laid-Open No. 2000-165422	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a view showing a configuration example in which controllers for a heavy duty industrial vehicle according to the present invention are used. FIG. 2 is a table showing a constitution example of input/output signals of the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 3 is a view showing an example of the logic configuration of the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 4 is a flow chart illustrating a procedure in the event of a failure in the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 5 is a flow chart illustrating another procedure in the event of a failure in the controllers for the heavy duty industrial vehicle according to the present invention. detailed-description description="Detailed Description" end="lead"?	TECHNICAL FIELD This invention relates to controllers which are used for heavy duty industrial vehicles, for example, a reach stacker as a cargo handling vehicle, and a motor grader as a road surface maintenance vehicle. BACKGROUND ART A heavy duty industrial vehicle not only has a vehicle moving by itself, but also has a working machine unique to the vehicle. Thus, this type of industrial vehicle is adapted to be capable of performing a predetermined working action with the use of the working machine. Some of such heavy duty industrial vehicles use one controller to control not only the moving action of the vehicle, but also the working action of the working machine, thus controlling the entire vehicle. Some other heavy duty industrial vehicles have separate controllers, such as a controller for the moving action of the vehicle, and a controller for the working action of the working machine, and connect these controllers by a network to control the entire vehicle. Patent Document 1: Japanese Patent Application Laid-Open No. 2000-165422 DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention With a configuration in which the entire vehicle is controlled by use of a single controller, control signals to a plurality of instruments to be controlled can be concentrated on the single controller. Thus, software can be constructed in a simple configuration, even when the instruments to be controlled are caused to cooperate. However, a malfunction in one controller would bring the actions of the entire vehicle to a halt. In the heavy duty industrial vehicle, moreover, wirings for control signals from the controller to the instruments to be controlled extend over long distances, and the number of the wirings is large, thus increasing the complexity of the steps for designing and assemblage. Moreover, the parts to be operated are many. Consequently, possibilities are high for malfunctions due to poor contact of the wiring when in use, a break in the wire, and so on. In recent years, use has been made of a method in which a dedicated controller is provided for each of the instruments to be controlled, and the respective controllers are connected by a network to control the actions of the entire vehicle. According to this method, however, the controller composed of dedicated hardware is used for each of the instruments to be controlled. Thus, software needs to be designed individually, and the design of the software is itself complicated. Furthermore, some of the capabilities of the controller, for example, the communication capability, may be rendered common among the controllers. However, the instrument to be controlled by one controller is limited to a particular instrument, or the position of installation of the controller is limited to a predetermined position, and only the particular instrument to be controlled, which is suitable for the particular position of installation, is controlled. Thus, commonality of hardware is insufficient. Besides, software itself needs to be constructed beforehand individually for each of the controllers, and maintainability at the time of failure remains unchanged from that of the controller having the dedicated hardware. That is, the conventional controller has not achieved complete commonality of hardware itself, and has required individual construction of software adapted for the instrument to be controlled as a subject of control. Hence, none of the conventional controllers have been easily divertible to use on any instruments to be controlled. The aforementioned heavy duty industrial vehicles, in particular, are used under harsh service conditions, and if a partial failure stops the action of the entire vehicle, work may be markedly impeded. Thus, it has been desired that in the event of a partial failure, minimum function could be performed so as not to impede work, and a repair operation could also be promptly carried out. The present invention has been accomplished in light of the above-mentioned problems. An object of the present invention is to provide controllers for a heavy duty industrial vehicle, which have many input/output functions, which are highly versatile, and whose software is easy to change. Means for Solving the Problems Controllers for a heavy duly industrial vehicle according to claim 1 of the present invention, for solving the above problems, are a plurality of controllers which are provided in the heavy duty industrial vehicle equipped with a working machine for performing predetermined work; which control, independently of each other, a plurality of instruments to be controlled, including the working machine, the instruments being provided in the heavy duty industrial vehicle; and which are characterized in that the configuration of hardware of the plurality of controllers is entirely common. Concretely, not only the configuration of the hardware inside each of the controllers is rendered common, but also the positions of disposition, and the numbers, etc., of connectors serving as interfaces with input and output signals (for example, serial signals, analog signals, and digital signals) to and from external instruments to be controlled are rendered common. Depending on the instruments to be controlled, the types, capacities (e.g., voltage), and numbers of the input and output signals required are different. However, the maximum required types, capacities and numbers are provided in common. The controllers for a heavy duty industrial vehicle according to claim 2, which solve the above problems, are the above controllers for a heavy duty industrial vehicle, characterized in that the plurality of controllers are interconnected by a network. As the network, CAN (controller area network) bus, which is used mainly in automobiles, connects the controllers together. Particularly, high speed CANbus with several Mbps or more is desirable. The controllers for a heavy duty industrial vehicle according to claim 3, which solve the above problems, are the above controllers for a heavy duty industrial vehicle, characterized in that software for controlling each of the instruments to be controlled is of a hierarchical structure, driver software at a lower level for directly controlling each of the instruments to be controlled is common, and only application software at an upper level utilizing the driver software is different according to the function of each of the instruments to be controlled. The controllers for a heavy duty industrial vehicle according to claim 4, which solve the above problems, are the above controllers for a heavy duty industrial vehicle, characterized in that rewriting means is provided for making only the application software rewritable. The controllers for a heavy duty industrial vehicle according to claim 5, which solve the above problems, are the above controllers for a heavy duty industrial vehicle, characterized in that limited operation means is provided for enabling an operation by other controller so that at least the heavy duty industrial vehicle can be run, even if the controller for controlling the working machine fails or is not connected to the network. That is, limited operation means, called a degradation mode, is set, whereby even if one of the plurality of controllers fails or is not connected to the network, a limited operation can be performed, permitting the vehicle to run. The subject of the limited operation is not limited to a vehicle run. For example, in order to ensure safety, the action of the working machine may be limited to a minimum required one, which may be operated. Effects of the Invention According to the present invention, the hardware of each of the plural controllers for controlling the instruments to be controlled is rendered common. Thus, by changing only the software installed, the subject of control can be switched, and the controller with the changed software can be diverted to use on the selected instrument. As a result, the types of the parts used in the heavy duty industrial vehicle can be reduced. Moreover, the commonality of the hardware can achieve a unit price reduction due to the economies of mass production. According to the present invention, the plurality of controllers are interconnected by the network (CANbus). Thus, the control function can be distributed among the plural controllers, and the degree of freedom of the locations of arrangement can be improved. That is, the positions of installation of the controllers can be flexibly selected according to the design of the vehicle body of the heavy duty industrial vehicle. The distributed arrangement of the controllers can markedly decrease in-vehicle wirings for operational inputs and outputs for hydraulic selector valves and many signal connections, in comparison with conventional heavy duty industrial vehicles. Also, the effect of cutting down on the wiring cost and the assembly cost is obtained. There is also produced the effect of preventing troubles, such as a break in or poor contact of sensor signal wires of the working machine or the cabin having a slide mechanism. According to the present invention, commonality is achieved of hardware of each controller, and of the lower-level driver software for directly controlling the instruments to be controlled, in the software having the hierarchical structure. Thus, by changing only the upper-level application software utilizing the driver software, the controller with the thus changed application software can be used as a controller for controlling the different instrument to be controlled. Hence, in the event of a damage to one controller, only the application software is rewritten by use of rewriting means such as a maintenance tool. The controller used for other instrument to be controlled, if subjected to such rewriting, can be used as an alternative component for the controller which controls the desired instrument to be controlled. Thus, a step and time, which have been required for emergency saving, can be shortened. According to the present invention, even if one controller, for example, the controller for controlling the working machine, such as the spreader, fails or is not connected to the network, other controller enables vehicle body control and cabin operation of the heavy duty industrial vehicle, thereby permitting a limited operation such as a run operation (degradation mode). Thus, a run of the vehicle becomes possible even during detachment of the working machine at the time of transportation, assemblage, or maintenance. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a configuration example in which controllers for a heavy duty industrial vehicle according to the present invention are used. FIG. 2 is a table showing a constitution example of input/output signals of the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 3 is a view showing an example of the logic configuration of the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 4 is a flow chart illustrating a procedure in the event of a failure in the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 5 is a flow chart illustrating another procedure in the event of a failure in the controllers for the heavy duty industrial vehicle according to the present invention. DESCRIPTION OF THE REFERENCE NUMERALS 1 front wheel, 2 rear wheel, 3 vehicle body, 4 stand, 5 boom cylinder, 6 boom, 7 arm, 8 lock pin, 9 spreader, 10 cabin BEST MODE FOR CARRYING OUT THE INVENTION Controllers for a heavy duty industrial vehicle according to the present invention control a plurality of instruments to be controlled, which are provided in the heavy duty industrial vehicle. Hardware of each of these controllers is rendered common, the basic features of software are also rendered common, and only the minimum required features of the software are constructed to be suitable for the instruments to be controlled. Thus, the software of the controller can be easily changed. Regardless of the instrument to be controlled, as a subject of control, the controllers can be easily diverted to use on any instruments to be controlled. Even if a malfunction happens in other of the controllers, the controllers for the heavy duty industrial vehicle according to the present invention enter a degradation mode by a predetermined procedure, thereby enabling only a limited action, for example, a running action, to be performed. Embodiment 1 FIG. 1 is a view showing a configuration example in which controllers for a heavy duty industrial vehicle according to the present invention are used. In the present invention, the heady duty industrial vehicle is explained, with a reach stacker being taken as an example. However, the present invention is not limited to the reach stacker, but can be applied to other heavy duty industrial vehicles, such as a heavy duty fork lift and a motor grader. The reach stacker, if explained briefly, is a heavy duty, cargo-handling vehicle used for loading and unloading or movement of containers in a port, etc. The reach stacker is low in cost, corners easily, has no limitations on the distance over which it moves the container. The reach stacker can access not only the container placed at the front, but the container located at the back, and is thus a cargo handling vehicle very convenient in transshipping and moving containers. As shown in FIG. 1, the reach stacker has a vehicle body 3 mounted with two front wheels 1 and two rear wheels 2; a boom 6 disposed above the vehicle body 3 so as to be tiltable about a stand 4 by boom cylinders 5; an arm 7 provided within the boom 6 so as to be extensible and contractible, and extended and contracted by a telescopic cylinder (not shown) provided within the boom 6; and a spreader 9 provided at a front end portion of the arm 7, adapted to be capable of making an extending and contracting motion, a rotating motion, an inclining motion, and a paralleling motion, and holding a container by four lock pins 8. A cabin 10 is disposed on the upper surface of the vehicle body 3 and below the boom 6, at a position where visibility during work is satisfactory. An operator can perform a moving action for the reach stacker itself, or a holding action or an installing action for the container, with the use of an operating panel within the cabin 10. In the heavy duty industrial vehicle, the working machine is configured so as to be capable of performing a predetermined working procedure. In the reach stacker, for example, the spreader 9 serves as the working machine. As the controllers, the reach stacker has a controller 11 for controlling the spreader 9, a controller 13 for controlling the vehicle so as to move it, and a controller 12 for controlling an operation performed by the operator. These controllers control, independently of each other, the spreader 9, the vehicle body 3 and the cabin 10, respectively, which are instruments to be controlled. In addition, the reach stacker has a display and J/S (joystick) 14 for indicating information to the operator, and indicating operator guidance from the operator. These controllers are interconnected by a high speed CANbus network (hereinafter referred to simply as CAN) 15. Each controller exchanges necessary control information with one another in real time, and performs a control action for each instrument to be controlled. The controller 13, as a main controller, monitors the other controllers 11 and 12, and controls the entire vehicle in an integrated manner. That is, these three controllers, which are interconnected by the CAN 15, constitute a so-called distributed network having capabilities or functions distributed among them. The above controllers are each composed of CPU (processing circuit), a storage region (having ROM containing control software and data, and RAM serving as an arithmetic work area), and an I/F (interface) circuit which is a processing circuit for input and output signals. Since the plurality of controllers are constituted as the distributed network, the controllers can be arranged in proximity to the instruments to be controlled, as compared with the conventional controller which, singly, controls all the instruments to be controlled. Thus, the wirings between the controllers and the instruments to be controlled can be markedly reduced. Since control signals can be exchanged through a single cable for CAN, moreover, the structures between the instruments are simplified. Thus, the number of man-hours required for assembly can be markedly decreased, and the wirings themselves can be cut down on, so that the rate of failures due to a wire break, etc. can be reduced. Furthermore, a quick response at the time of failure becomes possible. In the reach stacker shown in FIG. 1, the controller 11 for controlling the spreader, the controller for the cabin I/O, and the controller 13 for vehicle body control have an exactly common hardware configuration, and use exactly common driver software for setting the actions of the hardware, and for directly actuating control instruments. However, application software for controlling, by use of the driver software, the instruments to be controlled is the only tool that is different among the different controllers. For example, the controller 11 for controlling the actions of the spreader has spreader control software as the application soft ware, the controller 12 for controlling operations from the operator has cabin I/O software as the application software, and the controller 13 for controlling the actions of the vehicle body has vehicle body control software as the application software. Details for these features will be offered later. In the above features, the controller 11, for controlling the actions of the spreader 9, sends control signals to the respective control instruments for the spreader via a working machine I/F 16 to drive motors, and acquires detection signals from sensors to detect the acting state of the spreader, for example, the positions of the lock pins, the inclination angle of the spreader, and so forth. Moreover, the controller 11 lights a warning lamp for indicating that the operation is in progress. The controller 11 also uses working machine electromagnetic control 17 to exercise action control over an electromagnetic valve, thereby controlling the actions of hydraulic cylinders for effecting an extending and contracting action and an inclining action of the spreader 9. The controller 12 acquires input signals from the cabin 10, such as an accelerator pedal and a brake pedal, via an operator I/F 18, and transmits control information to the controllers 11 and 13 via the CAN 15 to control the action of the vehicle 3 and the spreader 9. The controller 13 takes charge of the integrated control of the vehicle by vehicle integrated control 19, and also controls the vehicle body 3 with the use of vehicle body I/F 19. In addition, the controller 13 uses boom servo valve control 20 to exercise action control over the boom 6, uses T/M (transmission) electromagnetic valve control 21 to exercise action control over T/M, and uses engine control 22 to exercise action control over the engine, concretely, control of the oil pressure of the engine and control over a battery. The display and J/S 14 may be those in a configuration comparable to that of any of the above-described controllers. However, the display and J/S 14, unlike the other controllers, are not required to involve many types of input and output signals, but need to give output signals for indication on the display. Thus, they use a dedicated controller to issue signals to the display and acquire signals from the J/S. Even in this case, they have a common communication capability, and can exchange control signals and vehicle information via the CAN 15, independently of the controllers 11, 12, 13. Concretely, information such as a vehicle posture or an error code during the operation of the spreader is indicated on the display 14 with the use of vehicle information acquired from the controller 11 and the controller 13. Also, an operator guidance from the operator, which has been inputted from the J/S 14, is acquired by the dedicated controller, which transmits such operational information to the controllers 11 and 13 via the CAN 15 to control the action of the spreader 9 and the action of the vehicle 3. In the reach stacker of the above configuration, while referring to the work situation (assembled form of cargo, posture of the vehicle, weight of the container, angle of the boom, extension or contraction of the arm, etc.) and the vehicle situation (rotational speed of the engine, speed of the vehicle, etc.) indicated in colors on the display 14, the operator within the cabin 10 operates the J/S 14 on the operating panel of the cabin 10 to perform a moving action of the vehicle body 3, an inclining action of the boom 6, an extending and contracting action of the arm 7, and an extending or contracting action, a rotating action, and a holding action of the spreader 9. For example, in a run with the container being held, control is exercised such that the vehicle body 3 can run, while the spreader 9 is held in a stable posture which enables the run. The stable state of the vehicle is indicated on the display 14. If there is a possibility that the stable posture of the vehicle will be destroyed by an up-slope or the like, for example, control is exercised such that a warning is issued at once to keep a stable posture automatically or manually. FIG. 2 shows a constitution example of input/output signals of the controllers for the heavy duty industrial vehicle according to the present invention. For comparisons, the table in this drawing also shows the constitution of input/output signals required by the controllers which are used in a general reach stacker, a heavy duty F/L (fork lift), and M/G (motor grader). The controllers for a heady duty industrial vehicle according to the present invention, concretely, have 4 connections for pulse input signals from the instruments to be controlled, 1 connection each for serial signals for synchronous mode, asynchronous mode, and CAN, 5 connections for output signals to the servo valve, 12 connections for outputs to the electromagnetic valve, 12 connections for analog input signals, 2 connections for analog outputs, 24 connections for contact inputs (24V) and 8 connections for contact inputs (5V), and 13 connections for contact outputs (24V) and 5 connections for contact outputs (5V). These are the maximum numbers of connections for inputs and outputs required of the instruments to be controlled, and they are common to these controllers. The capacities of the inputs to and outputs from the contacts (e.g., voltage, etc.) are also the maximum required capacities, and they are common to the controllers. These values correspond to specifications satisfying the requirements for the general reach stacker that are listed in the column on the right of the common controller in FIG. 2. These values also sufficiently fulfill the specifications for the heavy duty F/L and M/G listed at the same time, and can be applied to other heavy duty industrial vehicles as well as the reach stacker. That is, for the commonality of hardware among the controllers, not only the hardware configuration within the controllers, but also the connectors for input and output signals are rendered common, and their positions of arrangement are also rendered exactly identical. Moreover, each of the controllers is entirely boxed to improve dust-proof properties, and when the controller is to be replaced, it suffices to replace its connectors, thereby enabling a predetermined action. FIG. 3 shows an example of the logic configuration of the controllers for the heavy duty industrial vehicle according to the present invention. FIG. 3 illustrates a logic configuration example of the controller for performing vehicle control. However, the controllers for spreader control and cabin control have exactly the same configuration, except for a vehicle control module portion corresponding to application software. In the logic configuration of the controller for the heavy duty industrial vehicle according to the present invention, concretely, the structures of the CPU and I/F circuit corresponding to hardware are exactly common. Not only the portion corresponding to a physical configuration (i.e., hardware), but also the configuration of portions corresponding to the setting of hardware inside the controller, concretely, settings for a clock, an action mode, CPU terminal function, a pulse counter, PWM (pulse width modulator) function, and an A/D conversion mode, are exactly common, and a so-called microcomputer layer is used as a common platform. Furthermore, the zone of the application layer constituting the software is constructed in a hierarchical structure, and the lower level of the application layer, namely, a driver module having driver software for directly receiving and outputting control signals from and to the instruments to be controlled, is constructed in a completely common configuration. Concretely, a general I/O, a servo valve current control PWM output, pulse conversion, and A/D conversion are used as a common configuration. The driver module and the microcomputer layer are of exactly the same configuration among the controllers. On the other hand, a control module, which is the upper level of the application layer and utilizes the driver software, for example, if it is a vehicle control module, has application software for vehicle control. Depending on which of the instruments to be controlled the vehicle control module controls, the configuration of the vehicle control module becomes different. Concretely, the vehicle control module has software for effecting vehicle speed calculation, transmission control, engine control, switch/lamp control, and cargo handling/working machine control. That is, this portion of the control module is installed with application software for a spreader control module in the case of the spreader, or application software for a cabin control module in the case of the cabin. Furthermore, only this control module portion is replaced according to the instrument to be controlled, whereby the control module portion can function as any of the controllers, and its diverted use is facilitated. The common driver module (drive software) is held in the ROM (read only memory) inside the controller. The control module at the level upward of the driver module utilizes this driver module to control the action of the instrument to be controlled. The control module (application software) is rewritable according to a predetermined procedure, and is held in a rewritable ROM (e.g., flash ROM). Next, the procedure in the event of a failure in the controller will be described with reference to flow charts shown in FIG. 4 and FIG. 5. For example, the procedure for a degradation mode in the case of a failure in the controller for spreader control is shown in the flow chart of FIG. 4. (Step S1) A failure detection error code on the display 14 within the cabin 10 is verified. At this time, this code is confirmed to be an error code showing a malfunction in the controller for the spreader. (Step S2) An interlock release key SW on the operating panel within the cabin 10 is turned on. (Step S3) It is confirmed that the failure detection error code is not indicated on the display 14 within the cabin 10. If there is a malfunction in the spreader controller, the interlock release key SW transiently releases interlock in disregard of an error in the spreader controller, instead of disabling an operation of the spreader 9 itself. On this occasion, an indication of the failure detection error code on the display 14 is also transiently stopped. (Step S4) An operation is performed, with the interlock release key SW remaining ON. That is, the operation of the spreader 9 is disabled, and other operation, for example, only an operation for running of the vehicle, is enabled. This is the degradation mode (limited operation means), which enables a limited operation even in a state where one of the three controllers is not connected, or there is no operating machine such as the spreader 9. In the reach stacker, according to the degradation mode, the vehicle is rendered capable of running, with the spreader 9 being located at a safe position. (Step S5) The power source for the vehicle is turned off. (Step S6) After a repair or replacement of the spreader controller is completed, the interlock release key SW is turned off (the key is removed). Then, it is confirmed that the failure detection error code is not indicated on the display 14 within the cabin 10. The procedure for the degradation mode in the case of a failure in the controller for controlling other member than the spreader 9 is shown in the flow chart of FIG. 5. (Step S11) A failure detection error code on the display 14 of the cabin 10 is verified. At this time, this code is confirmed to be an error code showing a malfunction in the controller for other member than the spreader, for example, the vehicle body controller. (Step S12) The power source for the vehicle is turned off. (Step S13) The spreader controller and the failed vehicle body controller are both detached, and the spreader controller is attached as a vehicle body controller for serving as a new vehicle body controller. (Step S14) A mode SW of the new vehicle body controller is switched to a software installation mode (rewriting means). (Step S15) The power source for the vehicle is turned on. (Step S16) An installation cable and PC (computer) are connected to the new vehicle body controller to install application software for the vehicle body controller. (Step S17) The power source for the vehicle is turned off. (Step S18) The mode SW of the new vehicle body controller is switched to a RUN mode (usual state). (Step S19) The power source for the vehicle is turned on. Then, the procedure starting with Step S2 in the flow chart shown in FIG. 4 is performed (point A in FIG. 4). INDUSTRIAL APPLICABILITY The present invention is not limited to the reach stacker, but can be applied to other heavy duty industrial vehicles, including a heavy duty fork lift and a motor grader.	G	60G06	161G06F	19	00
11860532	US20090083618A1-20090326	METHODS OF COMPLETING ELECTRONIC FORMS RELATING TO INTERACTIONS WITH CUSTOMERS BY CARRYING OVER CALL BACK NUMBERS BETWEEN FORMS	ACCEPTED	20090312	20090326	[]	G06F1500	["G06F1500"]	8065602	20070924	20111122	715	224000	94550.0	STORK	KYLE	[{"inventor_name_last": "Campbell", "inventor_name_first": "Michelle", "inventor_city": "North Augusta", "inventor_state": "SC", "inventor_country": "US"}]	Interactions between customers and representatives of a service provider are documented by providing multiple electronic forms for completion. Information that is requested for both forms is carried over from one form to the next rather than requiring the representative to manually enter the same information multiple times. For instance, a call back number of the customer may be entered on one electronic form being used to edit information for a customer and that call back number is automatically carried over to another form being used to document a commitment to handle a request from the customer. The representative is relieved of double-entry, and mistakes that might arise from double-entry are reduced or eliminated. The electronic forms may be submitted to a tracker database that allows for further disposition of the request by the customer.	1. A computer readable medium containing instructions that perform acts comprising: in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed; receiving data into the field for the identification number of the service account; and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number and upon receiving data into the fields of the second form for the customer name and the call back telephone number, then re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. 2. The computer readable medium of claim 1, wherein the acts further comprise: in response to receiving the data into the field for the identification number, looking up the customer name in a customer database; if the customer name is found, then auto-filling the name into the field for the name and upon also receiving data into the field for the call back telephone number, then activating the submission button of the first form; and if the customer name is not found, then displaying the second form. 3. The computer readable medium of claim 1, wherein the service account pertains to telephone service and wherein the identification number of the service account is a telephone number of the telephone service. 4. The computer readable medium of claim 1, further comprising: receiving a selection of the activated submission button; and loading the data from the first form into a tracker database. 5. The computer readable medium of claim 1, wherein displaying the first form and displaying the second form comprises sending a first web page representing the first form and sending a second web page representing the second form from a server to a user terminal over a network. 6. The computer readable medium of claim 5, wherein receiving data into the first and second forms comprises sending data entered into the first and second forms from the user terminal to the server. 7. The computer readable medium of claim 6, wherein the acts further comprise queueing at the server the data received into the second form and wherein re-displaying the first form comprises sending the first web page representing the first form from the server to the user terminal over the network by retrieving the queued data and including the retrieved queued data within the first web page. 8. The computer readable medium of claim 5, wherein receiving data into the first and second forms comprises queueing the data at the user terminal. 9. The computer readable medium of claim 8, wherein re-displaying the first form comprises retrieving the data queued at the user terminal and including the retrieved queued data within the first web page. 10. A computer readable medium containing instructions that perform acts comprising: receiving a selection from a user to open a first form regarding handling an incoming request from a customer relating to a service account for the customer; in response to the request, displaying the first form including fields for receiving user input to specify an identification of the service account, a name of the customer, and a call back number of the customer and further including an inactive submission button; receiving user input to specify the identification of the service account; looking up the identification in a data store to obtain the name of the customer; if the name of the customer is found, then auto-filling the name of the customer into the first form, waiting for user input to specify the call back number, and activating a submission button of the first form upon receiving the call back number; and if the name of the customer is not found, then displaying a second form that includes fields for receiving the name of the user and the call back number for the user, waiting for user input to specify the customer name and the call back number, and re-displaying the first form by including the customer name and call back number received within the second form and by activating the submission button of the first form. 11. The computer readable medium of claim 10, wherein the acts further comprise receiving user input to select the submission button of the displayed first form when in the activated state and then sending the data included in the displayed first form to a tracker database. 12. The computer readable medium of claim 11, wherein the service account pertains to telephone service and wherein the identification of the service account is a telephone number. 13. The computer readable medium of claim 11, further comprising: receiving user input to select the submission button of the first form when in the inactive state; and displaying the second form in response to receiving the selection of the submission button when in the inactive state. 14. The computer readable medium of claim 11, wherein the first form and the second form are separate web pages provided from a server to a user terminal, wherein the data that is received into the first and second forms is sent to the server from the user terminal, is queued at the server, and is sent from the server to the tracker database upon selection of the submission button in the activated state. 15. The computer readable medium of claim 11, wherein the first form and the second form are separate web pages provided from a server to a user terminal, wherein the data that is received into the first and second forms is queued at the user terminal and is sent form the user terminal to the server upon selection of the submission button in the activated state. 16. A computer-implemented method of collecting information needed to handle an incoming request from a customer regarding a service account, comprising: in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed; receiving data into the field for the identification number of the service account; and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number and upon receiving data into the fields of the second form for the customer name and the call back telephone number, then re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. 17. The computer-implemented method of claim 16, further comprising: in response to receiving the data into the field for the identification number, looking up the customer name in a customer database; if the customer name is found, then auto-filling the name into the field for the name and upon also receiving data into the field for the call back telephone number, then activating the submission button of the first form; and if the customer name is not found, then displaying the second form. 18. The computer-implemented method of claim 16, wherein the service account pertains to telephone service and wherein the identification number of the service account is a telephone number of the telephone service. 19. The computer-implemented method of claim 16, further comprising: receiving a selection of the activated submission button; and loading the data from the first form into a tracker database. 20. The computer-implemented method of claim 16, wherein displaying the first form and displaying the second form comprises sending a first web page representing the first form and sending a second web page representing the second form from a server to a user terminal over a network.	<SOH> BACKGROUND <EOH>Departments of service providers take calls from customers for many reasons. Customers may contact a customer service or sales department to place a new order for a service, to request assistance with an existing service, to request maintenance or repair for a service, or to cancel the service. In doing so, a customer service or sales representative must document the telephone call or other interaction that has occurred with the customer. In some cases, the customer service or sales representative is incapable of handling the particular request that the customer is making. In those cases, the representative of the service provider must use electronic forms to document the request that is then electronically submitted to other departments that are better suited to handle the request. In cases such as these where electronic forms are utilized to document the interaction with the customer, information is obtained from the customer and the representative manually enters this information into the electronic forms. There may be instances where multiple electronic forms must be completed, such as where one form is dependent upon another form or where one form is used for editing information such as contact information while the other form is used to document the interaction itself and borrows the contact information from the form used for editing. In such cases, information that is required for completion of one form may also be required for completion of another form relating to the same customer. However, the representative may be required to manually enter the information in one form, and then proceed to the next form where the same information must be manually entered again. While such double-entry of information is time consuming and inefficient, it is also prone to errors where the representative makes a mistake when entering the same information multiple times for multiple forms. The call back number of the customer is one such type of information that must often be entered on multiple forms. The call back number of the customer is particularly burdensome in that it is information that must be requested by the representative, that may change from one interaction with the customer to the next, and that is crucial to effectively handle the request made by the customer.	<SOH> SUMMARY <EOH>Embodiments address issues such as these and others by providing for the carry over of information between fields of one form being completed for a customer interaction to another form being completed for the customer interaction. In particular, the call back number that has been obtained from the customer and that is manually entered in one form is carried over to another form without requiring a representative or the customer to provide the information to the other form. Embodiments provide a computer readable medium containing instructions that perform acts that include, in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed. The acts further include receiving data into the field for the identification number of the service account and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number. Upon receiving data into the fields of the second form for the customer name and the call back telephone number, then the acts further include re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. Embodiments provide a computer readable medium containing instructions that perform acts that include receiving a selection from a user to open a first form regarding handling an incoming request from a customer relating to a service account for the customer. The acts further include, in response to the request, displaying the first form including fields for receiving user input to specify an identification of the service account, a name of the customer, and a call back number of the customer and further including an inactive submission button. Additionally, the acts include receiving user input to specify the identification of the service account and looking up the identification in a data store to obtain the name of the customer. If the name of the customer is found, then the acts include auto-filling the name of the customer into the first form, waiting for user input to specify the call back number, and activating a submission button of the first form upon receiving the call back number. If the name of the customer is not found, then the acts include displaying a second form that includes fields for receiving the name of the user and the call back number for the user, waiting for user input to specify the customer name and the call back number, and re-displaying the first form by including the customer name and call back number received within the second form and by activating the submission button of the first form. Embodiments provide a computer-implemented method of collecting information needed to handle an incoming request from a customer regarding a service account. The method involves, in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed. The method further involves receiving data into the field for the identification number of the service account and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number. Upon receiving data into the fields of the second form for the customer name and the call back telephone number, then the method involves re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. Other systems, methods, and/or computer program products according to embodiments will be or become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional systems, methods, and/or computer program products be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.	TECHNICAL FIELD Embodiments relate to completing electronic forms to document interactions with customers. More particularly, embodiments relate to completing the electronic forms by carrying over call back numbers between multiple forms being completed for a given customer interaction. BACKGROUND Departments of service providers take calls from customers for many reasons. Customers may contact a customer service or sales department to place a new order for a service, to request assistance with an existing service, to request maintenance or repair for a service, or to cancel the service. In doing so, a customer service or sales representative must document the telephone call or other interaction that has occurred with the customer. In some cases, the customer service or sales representative is incapable of handling the particular request that the customer is making. In those cases, the representative of the service provider must use electronic forms to document the request that is then electronically submitted to other departments that are better suited to handle the request. In cases such as these where electronic forms are utilized to document the interaction with the customer, information is obtained from the customer and the representative manually enters this information into the electronic forms. There may be instances where multiple electronic forms must be completed, such as where one form is dependent upon another form or where one form is used for editing information such as contact information while the other form is used to document the interaction itself and borrows the contact information from the form used for editing. In such cases, information that is required for completion of one form may also be required for completion of another form relating to the same customer. However, the representative may be required to manually enter the information in one form, and then proceed to the next form where the same information must be manually entered again. While such double-entry of information is time consuming and inefficient, it is also prone to errors where the representative makes a mistake when entering the same information multiple times for multiple forms. The call back number of the customer is one such type of information that must often be entered on multiple forms. The call back number of the customer is particularly burdensome in that it is information that must be requested by the representative, that may change from one interaction with the customer to the next, and that is crucial to effectively handle the request made by the customer. SUMMARY Embodiments address issues such as these and others by providing for the carry over of information between fields of one form being completed for a customer interaction to another form being completed for the customer interaction. In particular, the call back number that has been obtained from the customer and that is manually entered in one form is carried over to another form without requiring a representative or the customer to provide the information to the other form. Embodiments provide a computer readable medium containing instructions that perform acts that include, in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed. The acts further include receiving data into the field for the identification number of the service account and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number. Upon receiving data into the fields of the second form for the customer name and the call back telephone number, then the acts further include re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. Embodiments provide a computer readable medium containing instructions that perform acts that include receiving a selection from a user to open a first form regarding handling an incoming request from a customer relating to a service account for the customer. The acts further include, in response to the request, displaying the first form including fields for receiving user input to specify an identification of the service account, a name of the customer, and a call back number of the customer and further including an inactive submission button. Additionally, the acts include receiving user input to specify the identification of the service account and looking up the identification in a data store to obtain the name of the customer. If the name of the customer is found, then the acts include auto-filling the name of the customer into the first form, waiting for user input to specify the call back number, and activating a submission button of the first form upon receiving the call back number. If the name of the customer is not found, then the acts include displaying a second form that includes fields for receiving the name of the user and the call back number for the user, waiting for user input to specify the customer name and the call back number, and re-displaying the first form by including the customer name and call back number received within the second form and by activating the submission button of the first form. Embodiments provide a computer-implemented method of collecting information needed to handle an incoming request from a customer regarding a service account. The method involves, in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and containing a submission button that remains inactive until the fields for the name, the identification number, and the call back telephone number are completed. The method further involves receiving data into the field for the identification number of the service account and subsequently displaying a second form containing fields for at least the customer name and the call back telephone number. Upon receiving data into the fields of the second form for the customer name and the call back telephone number, then the method involves re-displaying the first form including the name and call back number received within the second form and activating the submission button of the first form. Other systems, methods, and/or computer program products according to embodiments will be or become apparent to one with skill in the art upon review of the following drawings and detailed description. It is intended that all such additional systems, methods, and/or computer program products be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of an operating environment for various embodiments to handle the completion of electronic forms relating to customer interactions. FIG. 2A shows an example of an electronic forms web server according to various embodiments. FIG. 2B shows an example of a user terminal for completing electronic forms according to various embodiments. FIG. 3 shows an example of a set of logical operations performed to complete electronic forms according to various embodiments. FIG. 4 shows an example of one electronic form for receiving information relating to a customer interaction according to various embodiments. FIG. 5 shows an example of another electronic form for receiving information relating to the customer interaction where information is carried over to this form according to various embodiments. DETAILED DESCRIPTION Embodiments provide for the completion of electronic forms relating to interactions with customers by receiving information including a call back number of a customer into one form and then carrying over that information into another form. Therefore, a representative of the service provider only has to enter the information such as the call back number a single time for a given transaction and the efficiency is increased while the chances of error are decreased, according to exemplary embodiments. FIG. 1 shows one example of an operating environment. Here a sales and service web server 102 is present to provide the electronic forms as web pages that can be completed and submitted by the representatives of the service provider. While the embodiments are described with respect to electronic forms offered as web pages from the web server 102, it will be appreciated that electronic forms may alternatively be non-web based and may be accessed from other server types such as standard file servers. Furthermore, as discussed below, it will be appreciated that the electronic forms may originate from a user terminal that then submits those electronic forms to a tracker database 104 or maintains them internally. The web server 102 of this example is in communication with the tracker database 104 that keeps track of the electronic forms that document the interactions with customers. The tracker database 104 may be internal to the web server 102 or may be remotely located and accessed through an external data connection such as a network connection. The tracker database 104 may maintain the electronic documents for purposes of them being delivered to or accessed by other support personnel of the service provider. These personnel may utilize the information to address the request of the customer, including contacting the customer at the call back number that has been recorded within the electronic form when appropriate. The web server 102 may communicate with other computer systems and databases via one or more data networks 108. The web server 102 may communicate with a user terminal 106 of the representative such as a sales agent to provide the electronic forms to be filled in by the representative during the interaction with the customer. The web server 102 may communicate with a master customer database 110 to find stored information about a customer account. For example, an account number may be manually entered into an electronic form and the web server 102 may then perform a look-up of the account number within the master customer database 110 to find additional information that may be automatically entered into the electronic form. The web server 102 may also communicate with user terminals 112 of others such as support personnel of the service provider who may rely on the information of the electronic forms when handling the request made by the customer during the interaction between the customer and the sales agent. The support person may be notified by the web server 102 of an existing electronic form that has been completed by a sales agent via the user terminal 106, submitted into the tracker database 104, and that requires attention by the support person. The user terminals 106, 112 may be personal computers, thin clients, and the like. The user terminals 106, 112 may access the electronic forms via a web browser that loads a web page provided by the web server 102. As an alternative, the user terminals 106, 112 may access the electronic forms by downloading the forms in a format other than a web page. As yet another alternative, the user terminals 106, 112 may provide views of the electronic forms that are being opened by the server 102 such as through terminal services or similar terminal display techniques. FIG. 2A shows an example of the web server 102 that may provide the electronic forms as web pages, as non-web based documents, or as terminal displays. The web server 102 may be a computer system that includes a processor 202 that performs various logical operations to facilitate the completion of the electronic forms. The processor 202 may be of various forms including a general purpose programmable processor, an application specific processor, hardwired digital logic, and combinations thereof. The processor 202 may communicate with various other components such as a memory 204. The memory 204 may store programming as well as other data that may be utilized by the processor 202 when performing the various logical operations. The processor 202 and memory 204 are examples of computer readable media which store instructions that when performed implement various logical operations. Such computer readable media may include various storage media including electronic, magnetic, and optical storage. Computer readable media may also include communications media, such as wired and wireless connections used to transfer the instructions or send and receive other data messages. The processor 202 may also communicate with other components including input devices 206 such as a keyboard and a mouse as well as output devices such as a display system 210. The processor 202 may utilize a storage device 212 that may provide non-volatile storage space 214 as well as storage of an operating system 216, web pages 218 or other file types that provide the electronic forms, queues 220 for staging information during completion of the electronic forms, and programming that provides logic 222 for submitting the electronic forms to the tracker database 104. FIG. 2B shows an example of the user terminal 106 that a representative may utilize when completing electronic forms during interactions with customers. The user terminal 106 may be a mere terminal display device that receives displays from the web server 102 and sends input signals back to the web server 102 in the conventional terminal sense. Alternatively, the user terminal 106 may be a computer system that also includes a processor 230 that performs various logical operations to facilitate the completion of the electronic forms by displaying the electronic forms, receiving user input to compete the electronic forms, and sends the collected data to the server 102. The processor 230 may also be of various forms including a general purpose programmable processor, an application specific processor, hardwired digital logic, and combinations thereof. The processor 230 may also communicate with various other components such as a memory 232. The memory 232 may store programming as well as other data that may be utilized by the processor 230 when performing the various logical operations. The processor 230 and memory 232 are also examples of computer readable media which store instructions that when performed implement various logical operations. The processor 230 may also communicate with other components including input devices 234 such as a keyboard and a mouse as well as output devices such as a display system 238. The processor 230 may utilize a storage device 240 that may provide non-volatile storage space 242 as well as storage of an operating system 244. The storage device 240 may also store forms 246 such as where the user terminal 106 provides those forms without requesting them from a server or where the user terminal 106 stores completed forms prior to submitting them to the server 102. The storage device 240 may also provide a queue 248 for staging data during the completion of the electronic forms 246. Furthermore, for embodiments where the user terminal 106 acts independently of the server 102, the storage device 240 may store logic 250 for submitting the electronic forms 246 either to the server 102 for further handling and/or directly to the tracker database 104. FIG. 3 shows a set of logical operations that may be performed by the server 102 in conjunction with the user terminal 106 according to various embodiments, or according to other embodiments, by the user terminal 106 independently of the server 102. The discussion will proceed with reference to the server 102 acting in conjunction with the user terminal 106. However, it will be appreciated that operations of the server 102 discussed in relation to FIG. 3 may alternatively be implemented by the user terminal 106 acting independently of the server 102. The logical operations begin at a query operation 302 where the processor 202 detects whether a user has selected to open a first form, referred to herein as a general commitment (GC) form for this example. The GC form in this example provides a representative with various fields to manually complete or to allow some of the information to be automatically completed if such information is available from the master customer database 110. The representative may select to open the GC form upon an interaction with a customer occurring, such as due to an inbound or outbound telephone call, inbound or outbound electronic mail, chat session, and the like. Upon the processor 202 detecting that the representative has selected to open the GC form, the processor 202 then displays the GC form for the user terminal 106 at a display operation 304. As discussed above, this display may be a web page displayed within a browser of the user terminal 106, may be a form used by a specific application for displaying such forms rather than a general web browser, or may even be displayed at the server 102 and then provided as a display to the user terminal through a terminal services approach. An example of the GC form is shown as GC form 400 in FIG. 4. This GC form 400 includes various fields such as a customer telephone number in a field 402 where this number serves as the customer account number for the customer account to which the interaction pertains. The GC form 400 also includes a first name field 404, a last name field 406, a call back number field 408, a due date field 412, and a field 410 where details of the request can be specified. The GC form 400 also includes a submit button 414 which allows the GC form to be submitted to the tracker database 104 for further disposition. In this example, the submit button 414 is inactive until the various fields are completed by the representative. While FIG. 4 shows information already present in the various fields 402, 404, 406, 408, it will be appreciated that at the initial display of the GC form 400, the fields are blank and are awaiting manual input from the representative. At a query operation 306, the processor 202 detects whether the primary number has been entered by the representative into the customer number field 402. The representative may ask the customer for an account number that the customer is concerned about or the representative may obtain a customer account number from a separate system that assigns customer account numbers for new accounts. The user terminal 106, upon receiving the information may upload it to the server 102 as an automatic function of the GC form 400. As an alternative, where the user terminal 106 includes the capability to query external resources for additional customer information or where the user terminal 106 stores additional customer information locally, the user terminal 106 may perform the detection of the query operation 306 for the purposes of doing a look-up of the additional customer information. Upon the processor 202 detecting that the primary customer number has been entered into the customer number field 402, the processor 202 then performs a look-up of the primary customer number in the master customer database 110 at a look-up operation 308. The processor 202 performs this look-up to find information that it may use to auto-fill one or more of the fields of the GC form 400. At a query operation 310, the processor 202 detects whether the primary customer number has been found in the master customer database 1 10. If so, then the processor 202 obtains the first and last name of the customer from the master customer database 110, sends the first name of the customer to the first name field 404, and sends the last name of the customer to the last name field 406. For example, the electronic forms may be provided as active server pages whereby the web page server 102 may dynamically send and receive information from the web pages being displayed on the user terminal 106. After having auto-filled the first and last name fields 404, 406 at a fill operation 312, the processor 202 may then detect whether the call back number has been manually entered into the call back number field 408 at a query operation 314. In this example, the call back number is required to be entered before the submission button 414 can become active since it is desired that the call back number be received from the customer and included in the GC form 400. If the call back number has been received, then the processor 202 displays the GC form 400 with the name and call back number shown in appropriate fields, such as the fields 404, 406, 408, at display operation 326. In this example, the call back number is not auto-filled by looking up the call back number from the master customer database 110 because the call back number is likely to change from one interaction with the customer to the next such that the number is requested each time there is an interaction with this customer. At this point, the submit button 414 may be made active by the processor 202 since all necessary information is included in the GC form 400. Thus, the processor 202 detects whether the submit button 414 has been selected at a query operation 328. If so, then the processor 202 sends the data from the fields, such as the fields 402, 404, 406, 408, of the GC form 400 to the tracker database 104 for further disposition at a database operation 330. At this point, the operational flow terminates for this call and begins again at the query operation 302 for the next call. Back at the query operation 314, if the processor 202 detects that the call back number has not been entered, the processor 202 does not yet activate the submit button 414 but detects whether the submit button 414 has been selected at a query operation 316. Upon detecting that the submit button 414 has been selected, then the processor 202 prompts the representative to enter the call back number at prompt operation 318, such as by providing a pop-up message and/or by changing to a second electronic form discussed below and shown in FIG. 5. Returning to query operation 310, where the processor 202 is unable to find the customer number in the master customer database 110, the processor 202 then displays the second electronic form in a display operation 320. The display of the second electronic form may be in a new browser or application window, in a new tab of an open browser, in place of the first electronic form 400 in the current window, or in some other fashion. In this example, the second electronic form is an add/edit customer (A/E) form 500 as shown in FIG. 5. This A/E form 500 includes various fields that match some of the fields from the GC form 400. These include a primary number field 502, a first name field 504, a last name field 506, and a call back number field 508. The A/E form 500 also includes an OK button 510 that may be selected to accept the information that has been entered for the various fields. When displaying the A/E form 500, the processor 202 may auto-fill the customer primary number that has been previously received into the GC form 400 into the primary customer number field 502. Upon displaying the A/E form 500, the processor 202 then detects whether the representative has manually entered the first and last names in the appropriate fields 504, 506 at a query operation 322. Where the first and last names have been received, the names are queued either at the server 102 or at the user terminal 106 depending upon the chosen implementation. The processor 202 also detects whether the representative has manually entered the call back number in the appropriate field 508 at a query operation 324. Where the call back number has been received, the call back number is queued either at the server 102 or at the user terminal 106 depending upon the chosen implementation. Furthermore, upon finding that both of the name fields 504, 506 and the call back number field 508 have been completed, then upon selection of the OK button 510 by the representative, the processor 202 then re-displays the GC form 400 at the display operation 326. In doing so, the GC form 400 is now displayed with both the name fields 404, 406 completed and with the call back number field 408 completed in accordance with the information that was used to complete the name fields 504, 506 and call back number field 508 of the A/E form 500. The processor 202, or the processor 230 of the user terminal 106 depending upon the implementation, extracts the name and call back number information that has been queued and fills in the name and number fields 404, 406, and 408 when re-displaying the GC form 400. As those name and number fields 404, 406, and 408 are now complete, the processor 202 activates the submit button 414 so that the information of the GC form 400 may be submitted to the tracker database 104. The logical operations proceed as previously described regarding detecting the selection of the submit button 414 and sending the data to the tracker database 104 for further disposition. As discussed above, information may be provided by a representative to document an interaction with a customer. Multiple electronic forms may be necessary to allow the representative to provide the desired information. Information may be carried over from one form to another, e.g., from the second form back to the first form, so that the representative is not required to manually enter the same information in each of the multiple forms. Accordingly, documenting the interaction with the customer may be more efficient and less likely to have errors resulting from double-entry of information. While embodiments have been particularly shown and described, it will be understood by those skilled in the art that various other changes in the form and details may be made therein without departing from the spirit and scope of the invention.	G	60G06	161G06F	15	00
11754419	US20070299974A1-20071227	VIDEO REPRODUCING APPARATUS AND CONTROL METHOD THEREOF	ACCEPTED	20071213	20071227	[]	G06F1516	["G06F1516"]	7640569	20070529	20091229	725	115000	92969.0	LUU	LE	[{"inventor_name_last": "Kitajima", "inventor_name_first": "Kotaro", "inventor_city": "Yokohama-shi", "inventor_state": "", "inventor_country": "JP"}]	A technique for sequentially updating a recording medium as if sub contents, related to a video image as a main content recorded on the recording medium, are stored on the recording medium, such that the sub contents can be reproduced. When reproduction of the video image as a main content recorded on an optical disk has been completed, a content server is accessed in accordance with bind definition designation information stored on the optical disk. Then, bind definition information in which link information to access a sub content such as special video images stored on the content server is described is downloaded. Then, based on the downloaded bind definition information, the link information to access the sub content is stored onto the optical disk, thereby the sub content can be reproduced.	1. A video reproducing apparatus comprising: a reproducing unit to reproduce information recorded on a recording medium; a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquire definition information describing information related to a location of said sub information from said network server, based on predetermined information reproduced by said reproducing unit; and a control unit to change the definition information acquired by said acquisition unit in correspondence with a status of said video reproducing apparatus. 2. The video reproducing apparatus according to claim 1, wherein said definition information is link information to acquire said sub information. 3. The video reproducing apparatus according to claim 1, wherein said acquisition unit acquires said definition information based on said video information or a reproduction status of said sub information. 4. The video reproducing apparatus according to claim 3, wherein said acquisition unit acquires specific definition information at an initial stage of reproduction of video information recorded on said recording medium. 5. The video reproducing apparatus according to claim 4, wherein said acquisition unit acquires definition information different from said specific definition information after completion of reproduction of video information recorded on said recording medium. 6. The video reproducing apparatus according to claims 1, wherein said acquisition unit acquires definition information which differs in correspondence with the number of times of reproduction of video information recorded on said recording medium. 7. The video reproducing apparatus according to claim 1, further comprising an image pickup unit and a recording unit to record video information photographed by said image pickup unit onto said recording medium, wherein upon recording of the video information onto said recording medium by said recording unit, said acquisition unit acquires a definition information based on one or combined photographing information generated by said image pickup unit, position information of said image pickup unit and unique information of said image pickup unit. 8. The video reproducing apparatus according to claim 1, further comprising an image pickup unit, a recording unit to record video information photographed by said image pickup unit onto said recording medium and an editing unit to edit recorded video information, wherein said acquisition unit acquires definition information indicating material information related to editing of video information photographed by said image pickup unit. 9. A video reproducing apparatus for reproducing video information recorded on a recording medium comprising: a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquire definition information describing information related to a location of said sub information from said network server, based on predetermined information recorded on said recording medium; a reproducing unit to reproduce said video information and sub information in accordance with said definition information acquired by said acquisition unit upon reproduction of video information recorded on said recording medium; and a control unit to perform control to acquire new definition information from said network server in correspondence with a reproduction status in said reproducing unit. 10. A control method for a video reproducing apparatus having a communication unit to establish connection with a network, comprising: a reproducing step of reproducing information recorded on a recording medium; an acquisition step of performing communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquiring definition information describing information related to a location of said sub information from said network server, based on predetermined information reproduced at said reproducing step; and a control step of changing the definition information acquired at said acquisition step in correspondence with a status of said video reproducing apparatus. 11. A computer program stored on a computer-readable storage medium, read and executed by a computer having a communication unit to establish connection with a network, thereby causes said computer to function as a video reproducing apparatus, said computer program functioning as: a reproducing unit to reproduce information recorded on a recording medium; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquire definition information describing information related to a location of said sub information from said network server, based on predetermined information reproduced by said reproducing unit; and a control unit to change the definition information acquired by said acquisition unit in correspondence with a status of said video reproducing apparatus. 12. A computer-readable storage medium holding the computer program in claim 11. 13. A control method for a video reproducing apparatus having a communication unit to establish connection with a network, for reproducing video information recorded on a storage medium, comprising: an acquisition step of performing communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquiring definition information describing information related to a location of said sub information from said network server, based on predetermined information recorded on said recording medium; a reproducing step of reproducing said video information and sub information in accordance with said definition information acquired at said acquisition step upon reproduction of video information recorded on said recording medium; and a control step of performing control to acquire new definition information from said network server in correspondence with a reproduction status at said reproducing step. 14. A computer program stored on a computer-readable storage medium, read and executed by a computer having a communication unit to establish connection with a network, thereby causes said computer to function as a video reproducing apparatus for reproducing video information recorded on a storage medium, said computer program functioning as: an acquisition unit to perform communication with a network server holding sub information related to video information recorded on said recording medium via said communication unit and acquire definition information describing information related to a location of said sub information from said network server, based on predetermined information recorded on said recording medium; a reproducing unit to reproduce said video information and sub information in accordance with said definition information acquired by said acquisition unit upon reproduction of video information recorded on said recording medium; and a control unit to perform control to acquire new definition information from said network server in correspondence with a reproduction status in said reproducing unit. 15. A computer-readable storage medium holding the computer program in claim 14.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a technique for reproducing a video image recorded on a recording medium. 2. Description of the Related Art In recent years, digital contents have been distributed in various forms. In one known distribution form, digital contents related to each other are distributed using plural media. For example, a main content such as video image and sound as a cinema motion picture is recorded on an optical disk typified by a DVD (Digital Versatile Disc) and the disk is provided, and sub contents such as captions are provided via a medium such as a Flash Media Server or a network. A user who handles such digital content reproduces the digital content using his/her reproducing apparatus such as a PC (Personal Computer) or a disk player. The reproducing apparatus handles the main content and the sub contents as if they were recorded on one medium (see Japanese Patent Application Laid-Open No. 2005-136762). More particularly, audio information is recorded on the optical disk in addition to the main video image. Further, the sub contents stored on a content server on the network include captions in plural languages and application software. The sub contents are provided to the reproducing apparatus via, for example, the network. The main content and the sub contents recorded on the optical disk are linked with each other. The reproducing apparatus downloads the sub contents linked to the main content, and thereby utilizes the sub contents. The main content requiring a large storage capacity is recorded on the optical disk to be provided, and the sub contents requiring comparatively smaller storage capacity are provided via the network. In this manner, various contents can be provided independently of the storage capacity of optical disk medium. Further, the sub contents can be easily updated only by changing data on the content server. Next, the configuration of the reproducing apparatus to realize the above digital data distribution will be described based on the drawings. FIG. 16 is a block diagram showing the configuration of a reproducing apparatus for video reproduction from an optical disk. In FIG. 16 , reference numeral 1600 denotes a removable optical disk such as a DVD; 1601 , an optical head unit having a motor, an actuator and the like to control an optical head and perform position control on the optical head; 1602 , a drive controller to control driving of the optical head unit 1601 ; 1603 , an error corrector; 1604 , a separator to separate data; 1605 , a product ID decoder to decode a product ID of the optical disk 1600 ; 1606 , a network interface; 1607 , a content decoder to decode content data such as a video image; 1608 , an output unit to output information; 1609 , an operation unit to receive a user's input; 1610 , a content server; and 1620 , a system controller. Next, an operation of the above reproducing apparatus upon reproduction from the optical disk 1600 will be described. The optical disk 1600 holds content data such as a video image and audio information. When the operation unit 1609 receives an optical disk reproduction request from the user, the operation unit 1609 outputs the reproduction request to the system controller 1620 . The system controller 1620 issues a data reading request to the drive controller 1602 . The drive controller 1602 controls the optical head unit 1601 , thereby controls the reading of data from the optical disk 1600 . The optical head unit 1601 reads data from the optical disk 1600 , and outputs the data to the error corrector 1603 . The error corrector 1603 corrects defect(s) of the optical disk medium or error(s) upon recording and reproduction, and outputs a digital data string to the data separator 1604 . The data separator 1604 separates the input digital data to content data such as video data and audio data, and management information such as a product ID to be described later. The data separator 1604 outputs the management information such as a product ID to the product ID decoder 1605 , while outputting the content data to the content decoder 1607 . The content decoder 1607 decodes the input video data and audio data, and outputs the decoded data to the output unit 1608 . The output unit 1608 having a monitor, a speaker and the like outputs the decoded content data. Next, reproduction of contents provided from the content server 1610 will be described. When the operation unit 1609 receives a list display request for display of reproducible contents in the form of list, the system controller 1620 controls the drive controller 1602 to read data including management information recorded in a predetermined area of the optical disk 1600 . The data read from the optical disk 1600 is inputted into the data separator 1604 through a similar process to that described above. The data separator 1604 extracts the management information from the input data and outputs the management information to the product ID decoder 1605 . The product ID decoder 1605 extracts a product ID and content server information from the management information. Note that the product ID means information for identification of a content recorded on the optical disk 1600 , for example, a product ID of the optical disk 1600 . Further, the content server information means data indicating the location of the content server 1610 on the network such as a URL. The product ID decoder 1605 outputs the product ID data and the content server information to the network interface 1606 . The network interface 1606 establishes connection with the content server 1610 specified with the content server information via the network, and outputs the product ID data to the content server 1610 . The content server 1610 returns available bind definition information corresponding to the product ID data to the reproducing apparatus. The bind definition information is a file in which a procedure necessary for bind processing to be described later is described. The system controller 1620 obtains the bind definition information via the network interface 1606 , and binds the sub content data on the content server 1610 based on the bind definition information. Note that “bind” means connecting main content data recorded on the local optical disk 1600 to sub content data provided from the content server 1610 . Hereinbelow, a method for binding content data provided from the content server 1610 will be described. FIG. 17A shows an example of a directory structure of content data stored on the optical disk 1600 . A directory 1700 is a root directory of the content data recorded on the optical disk 1600 ; a directory 1710 , a directory for storing management information; data 1711 is content server information; and data 1712 , product ID data. Further, a directory 1720 is a main video directory for storing video data; and data 1721 , video data. Further, a directory 1730 is a caption directory for storing caption data; and data 1731 , caption data (language A and language B). In a single optical disk having the structure shown in FIG. 17A , a “main video image” as the main video data and caption data “language A” and “language B” corresponding to the main video data are recorded. The reproducing apparatus can select the caption data “language A” or the caption data “language B” for the “main video image” when it performs reproduction. On the other hand, FIG. 17B shows the directory structure of content data stored on the content server 1610 in FIG. 16 . A directory 1740 is a root directory of the content data on the content server 1610 ; and directories 1750 and 1760 , directories holding data corresponding to product IDs. Further, data 1751 is bind definition information; a directory 1770 , a directory holding caption data; and data 1771 , caption data (languages C to F). The reproducing apparatus sends the product ID data 1712 of the optical disk 1600 to the content server 1610 having the above directory structure. The content server 1610 returns bind definition information recorded in a directory corresponding to the product ID of the optical disk 1600 to the reproducing apparatus. For example, when the product ID of the optical disk 1600 is “0001”, the content server 1610 returns the bind definition information 1751 corresponding to the product ID “0001” to the reproducing apparatus. The bind definition information includes a description to add the contents included in the caption directory 1770 of the content server 1610 to the caption directory 1730 of the optical disk 1600 . The reproducing apparatus interprets the bind definition information 1751 , and binds the contents on the content server 1610 to the content on the optical disk 1600 . FIG. 18 shows the directory structure of the optical disk 1600 in which the contents are bound in accordance with the bind definition information 1751 . In FIG. 18 , directories and data 1700 to 1731 correspond to the directories and data having the same reference numerals in FIG. 17A . As a result of binding in accordance with the bind definition information 1751 , caption data 1732 is newly added. The caption data 1732 corresponds to the data 1771 in FIG. 17B . Note that the caption data 1732 after the binding is not actually recorded on the optical disk 1600 , but linkage to the data on the content server 1610 is managed by the reproducing apparatus. By the binding in accordance with the bind definition information, the reproducing apparatus can make a selection from captions in 6 languages, “language A” to “language F”, for the “main video A” when it performs reproduction. Note that the “language C” to “language F” caption data are link information as described above. Accordingly, when the user has given the instruction for reproduction, the reproducing apparatus downloads the content from the content server via the network and perform reproduction. As described above, contents on a network, which are not included in a local optical disk, can be utilized as if they are parts of a content included in the optical disk by binding the content in accordance with bind definition information corresponding to a product ID. However, the bind definition information for binding as described above is provided in correspondence with only a product ID of a package medium. Accordingly, it is impossible to perform addition, change and the like of content to be bound in correspondence with user's content reproducing situation or the like.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made in view of the above problem, and provides a technique for sequentially updating a recording medium as if sub contents linked with a video image as a main content recorded on the recording medium are stored on the recording medium, such that the sub contents can be reproduced. According to a first aspect of the present invention, there is provided a video reproducing apparatus comprising: a reproducing unit to reproduce information recorded on a recording medium; a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquire definition information describing information related to a location of the sub information from the network server, based on predetermined information reproduced by the reproducing unit; and a control unit to change the definition information acquired by the acquisition unit in correspondence with a status of the video reproducing apparatus. According to a second aspect of the present invention, there is provided a video reproducing apparatus for reproducing video information recorded on a recording medium comprising: a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquire definition information describing information related to a location of the sub information from the network server, based on predetermined information recorded on the recording medium; a reproducing unit to reproduce the video information and sub information in accordance with the definition information acquired by the acquisition unit upon reproduction of video information recorded on the recording medium; and a control unit to perform control to acquire new definition information from the network server in correspondence with a reproduction status in the reproducing unit. According to a third aspect of the present invention, there is provided a control method for a video reproducing apparatus having a communication unit to establish connection with a network, comprising: a reproducing step of reproducing information recorded on a recording medium; an acquisition step of performing communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquiring definition information describing information related to a location of the sub information from the network server, based on predetermined information reproduced at the reproducing step; and a control step of changing the definition information acquired at the acquisition step in correspondence with a status of the video reproducing apparatus. According to a fourth aspect of the present invention, there is provided a control method for a video reproducing apparatus having a communication unit to establish connection with a network, for reproducing video information recorded on a storage medium, comprising: an acquisition step of performing communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquiring definition information describing information related to a location of the sub information from the network server, based on predetermined information recorded on the recording medium; a reproducing step of reproducing the video information and sub information in accordance with the definition information acquired at the acquisition step upon reproduction of video information recorded on the recording medium; and a control step of performing control to acquire new definition information from the network server in correspondence with a reproduction status at the reproducing step. According to the present invention, the recording medium can be sequentially updated as if sub contents linked with a video image as a main content recorded on the recording medium are stored on the recording medium, such that the sub contents can be reproduced. Particularly, in the video reproducing apparatus, a bind destination of the sub contents can be added and/or changed in correspondence with reproduction information. In this arrangement, sub contents corresponding to a reproducing situation can be provided. For example, when a user watches the entire main video image, the user is enabled to watch a special video image. Further, as information designating a bind destination is recorded on an optical disk, the sub contents can be utilized in correspondence with reproduction situation, independently of reproducing machine. Further, in an image pickup apparatus according to the present invention, a bind destination of sub contents such as editing contents can be added and/or changed in correspondence with photographing information. In this arrangement, sub contents can be provided in a flexible manner in correspondence with a photographing position, a user's level of usage (beginner or advanced user) or the like. Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reproducing a video image recorded on a recording medium. 2. Description of the Related Art In recent years, digital contents have been distributed in various forms. In one known distribution form, digital contents related to each other are distributed using plural media. For example, a main content such as video image and sound as a cinema motion picture is recorded on an optical disk typified by a DVD (Digital Versatile Disc) and the disk is provided, and sub contents such as captions are provided via a medium such as a Flash Media Server or a network. A user who handles such digital content reproduces the digital content using his/her reproducing apparatus such as a PC (Personal Computer) or a disk player. The reproducing apparatus handles the main content and the sub contents as if they were recorded on one medium (see Japanese Patent Application Laid-Open No. 2005-136762). More particularly, audio information is recorded on the optical disk in addition to the main video image. Further, the sub contents stored on a content server on the network include captions in plural languages and application software. The sub contents are provided to the reproducing apparatus via, for example, the network. The main content and the sub contents recorded on the optical disk are linked with each other. The reproducing apparatus downloads the sub contents linked to the main content, and thereby utilizes the sub contents. The main content requiring a large storage capacity is recorded on the optical disk to be provided, and the sub contents requiring comparatively smaller storage capacity are provided via the network. In this manner, various contents can be provided independently of the storage capacity of optical disk medium. Further, the sub contents can be easily updated only by changing data on the content server. Next, the configuration of the reproducing apparatus to realize the above digital data distribution will be described based on the drawings. FIG. 16 is a block diagram showing the configuration of a reproducing apparatus for video reproduction from an optical disk. In FIG. 16, reference numeral 1600 denotes a removable optical disk such as a DVD; 1601, an optical head unit having a motor, an actuator and the like to control an optical head and perform position control on the optical head; 1602, a drive controller to control driving of the optical head unit 1601; 1603, an error corrector; 1604, a separator to separate data; 1605, a product ID decoder to decode a product ID of the optical disk 1600; 1606, a network interface; 1607, a content decoder to decode content data such as a video image; 1608, an output unit to output information; 1609, an operation unit to receive a user's input; 1610, a content server; and 1620, a system controller. Next, an operation of the above reproducing apparatus upon reproduction from the optical disk 1600 will be described. The optical disk 1600 holds content data such as a video image and audio information. When the operation unit 1609 receives an optical disk reproduction request from the user, the operation unit 1609 outputs the reproduction request to the system controller 1620. The system controller 1620 issues a data reading request to the drive controller 1602. The drive controller 1602 controls the optical head unit 1601, thereby controls the reading of data from the optical disk 1600. The optical head unit 1601 reads data from the optical disk 1600, and outputs the data to the error corrector 1603. The error corrector 1603 corrects defect(s) of the optical disk medium or error(s) upon recording and reproduction, and outputs a digital data string to the data separator 1604. The data separator 1604 separates the input digital data to content data such as video data and audio data, and management information such as a product ID to be described later. The data separator 1604 outputs the management information such as a product ID to the product ID decoder 1605, while outputting the content data to the content decoder 1607. The content decoder 1607 decodes the input video data and audio data, and outputs the decoded data to the output unit 1608. The output unit 1608 having a monitor, a speaker and the like outputs the decoded content data. Next, reproduction of contents provided from the content server 1610 will be described. When the operation unit 1609 receives a list display request for display of reproducible contents in the form of list, the system controller 1620 controls the drive controller 1602 to read data including management information recorded in a predetermined area of the optical disk 1600. The data read from the optical disk 1600 is inputted into the data separator 1604 through a similar process to that described above. The data separator 1604 extracts the management information from the input data and outputs the management information to the product ID decoder 1605. The product ID decoder 1605 extracts a product ID and content server information from the management information. Note that the product ID means information for identification of a content recorded on the optical disk 1600, for example, a product ID of the optical disk 1600. Further, the content server information means data indicating the location of the content server 1610 on the network such as a URL. The product ID decoder 1605 outputs the product ID data and the content server information to the network interface 1606. The network interface 1606 establishes connection with the content server 1610 specified with the content server information via the network, and outputs the product ID data to the content server 1610. The content server 1610 returns available bind definition information corresponding to the product ID data to the reproducing apparatus. The bind definition information is a file in which a procedure necessary for bind processing to be described later is described. The system controller 1620 obtains the bind definition information via the network interface 1606, and binds the sub content data on the content server 1610 based on the bind definition information. Note that “bind” means connecting main content data recorded on the local optical disk 1600 to sub content data provided from the content server 1610. Hereinbelow, a method for binding content data provided from the content server 1610 will be described. FIG. 17A shows an example of a directory structure of content data stored on the optical disk 1600. A directory 1700 is a root directory of the content data recorded on the optical disk 1600; a directory 1710, a directory for storing management information; data 1711 is content server information; and data 1712, product ID data. Further, a directory 1720 is a main video directory for storing video data; and data 1721, video data. Further, a directory 1730 is a caption directory for storing caption data; and data 1731, caption data (language A and language B). In a single optical disk having the structure shown in FIG. 17A, a “main video image” as the main video data and caption data “language A” and “language B” corresponding to the main video data are recorded. The reproducing apparatus can select the caption data “language A” or the caption data “language B” for the “main video image” when it performs reproduction. On the other hand, FIG. 17B shows the directory structure of content data stored on the content server 1610 in FIG. 16. A directory 1740 is a root directory of the content data on the content server 1610; and directories 1750 and 1760, directories holding data corresponding to product IDs. Further, data 1751 is bind definition information; a directory 1770, a directory holding caption data; and data 1771, caption data (languages C to F). The reproducing apparatus sends the product ID data 1712 of the optical disk 1600 to the content server 1610 having the above directory structure. The content server 1610 returns bind definition information recorded in a directory corresponding to the product ID of the optical disk 1600 to the reproducing apparatus. For example, when the product ID of the optical disk 1600 is “0001”, the content server 1610 returns the bind definition information 1751 corresponding to the product ID “0001” to the reproducing apparatus. The bind definition information includes a description to add the contents included in the caption directory 1770 of the content server 1610 to the caption directory 1730 of the optical disk 1600. The reproducing apparatus interprets the bind definition information 1751, and binds the contents on the content server 1610 to the content on the optical disk 1600. FIG. 18 shows the directory structure of the optical disk 1600 in which the contents are bound in accordance with the bind definition information 1751. In FIG. 18, directories and data 1700 to 1731 correspond to the directories and data having the same reference numerals in FIG. 17A. As a result of binding in accordance with the bind definition information 1751, caption data 1732 is newly added. The caption data 1732 corresponds to the data 1771 in FIG. 17B. Note that the caption data 1732 after the binding is not actually recorded on the optical disk 1600, but linkage to the data on the content server 1610 is managed by the reproducing apparatus. By the binding in accordance with the bind definition information, the reproducing apparatus can make a selection from captions in 6 languages, “language A” to “language F”, for the “main video A” when it performs reproduction. Note that the “language C” to “language F” caption data are link information as described above. Accordingly, when the user has given the instruction for reproduction, the reproducing apparatus downloads the content from the content server via the network and perform reproduction. As described above, contents on a network, which are not included in a local optical disk, can be utilized as if they are parts of a content included in the optical disk by binding the content in accordance with bind definition information corresponding to a product ID. However, the bind definition information for binding as described above is provided in correspondence with only a product ID of a package medium. Accordingly, it is impossible to perform addition, change and the like of content to be bound in correspondence with user's content reproducing situation or the like. SUMMARY OF THE INVENTION The present invention has been made in view of the above problem, and provides a technique for sequentially updating a recording medium as if sub contents linked with a video image as a main content recorded on the recording medium are stored on the recording medium, such that the sub contents can be reproduced. According to a first aspect of the present invention, there is provided a video reproducing apparatus comprising: a reproducing unit to reproduce information recorded on a recording medium; a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquire definition information describing information related to a location of the sub information from the network server, based on predetermined information reproduced by the reproducing unit; and a control unit to change the definition information acquired by the acquisition unit in correspondence with a status of the video reproducing apparatus. According to a second aspect of the present invention, there is provided a video reproducing apparatus for reproducing video information recorded on a recording medium comprising: a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquire definition information describing information related to a location of the sub information from the network server, based on predetermined information recorded on the recording medium; a reproducing unit to reproduce the video information and sub information in accordance with the definition information acquired by the acquisition unit upon reproduction of video information recorded on the recording medium; and a control unit to perform control to acquire new definition information from the network server in correspondence with a reproduction status in the reproducing unit. According to a third aspect of the present invention, there is provided a control method for a video reproducing apparatus having a communication unit to establish connection with a network, comprising: a reproducing step of reproducing information recorded on a recording medium; an acquisition step of performing communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquiring definition information describing information related to a location of the sub information from the network server, based on predetermined information reproduced at the reproducing step; and a control step of changing the definition information acquired at the acquisition step in correspondence with a status of the video reproducing apparatus. According to a fourth aspect of the present invention, there is provided a control method for a video reproducing apparatus having a communication unit to establish connection with a network, for reproducing video information recorded on a storage medium, comprising: an acquisition step of performing communication with a network server holding sub information related to video information recorded on the recording medium via the communication unit and acquiring definition information describing information related to a location of the sub information from the network server, based on predetermined information recorded on the recording medium; a reproducing step of reproducing the video information and sub information in accordance with the definition information acquired at the acquisition step upon reproduction of video information recorded on the recording medium; and a control step of performing control to acquire new definition information from the network server in correspondence with a reproduction status at the reproducing step. According to the present invention, the recording medium can be sequentially updated as if sub contents linked with a video image as a main content recorded on the recording medium are stored on the recording medium, such that the sub contents can be reproduced. Particularly, in the video reproducing apparatus, a bind destination of the sub contents can be added and/or changed in correspondence with reproduction information. In this arrangement, sub contents corresponding to a reproducing situation can be provided. For example, when a user watches the entire main video image, the user is enabled to watch a special video image. Further, as information designating a bind destination is recorded on an optical disk, the sub contents can be utilized in correspondence with reproduction situation, independently of reproducing machine. Further, in an image pickup apparatus according to the present invention, a bind destination of sub contents such as editing contents can be added and/or changed in correspondence with photographing information. In this arrangement, sub contents can be provided in a flexible manner in correspondence with a photographing position, a user's level of usage (beginner or advanced user) or the like. Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an optical disk reproducing apparatus according to a first embodiment of the present invention; FIG. 2 is a block diagram showing a file structure of content data stored on an optical disk according to the first embodiment; FIG. 3 is a block diagram showing a file structure of content data stored on a content server according to the first embodiment; FIG. 4 is a block diagram showing the file structure of content data stored on the optical disk after an update according to the first embodiment; FIG. 5 is a flowchart showing an operation of a bind definition designation information generator according to the first embodiment; FIG. 6 is a block diagram showing the file structure of content data stored on the optical disk after a further update according to the first embodiment; FIG. 7 is a block diagram showing the configuration of the reproducing apparatus according to a second embodiment of the present invention; FIG. 8 is a block diagram showing the file structure of content data stored on the optical disk according to the second embodiment; FIG. 9 is a block diagram showing the file structure of content data stored on the content server according to the second embodiment; FIG. 10 is a block diagram showing the file structure of content data stored on the optical disk after the update according to the second embodiment; FIG. 11 is a flowchart showing the operation of the bind definition designation information generator according to the second embodiment; FIG. 12 is a block diagram showing the configuration of the reproducing apparatus according to a third embodiment of the present invention; FIG. 13 is a block diagram showing the file structure of content data stored on the optical disk according to the third embodiment; FIG. 14 is a block diagram showing the file structure of content data stored on the content server according to the third embodiment; FIG. 15 is a block diagram showing the file structure of content data stored on the optical disk after the update according to the third embodiment; FIG. 16 is a block diagram showing the configuration of the disk reproducing apparatus according to the conventional art; FIGS. 17A and 17B are block diagrams showing the file structures of content data stored on the optical disk and the content server according to the conventional art; and FIG. 18 is a block diagram showing the file structure of content data stored on the optical disk according to the conventional art. DESCRIPTION OF THE EMBODIMENTS Hereinbelow, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. First Embodiment As a first embodiment, an optical disk reproducing apparatus capable of reproducing video and audio data recorded on a recording medium such as an optical disk will be described. FIG. 1 is a block diagram showing the configuration of an optical disk reproducing apparatus as the reproducing apparatus according to the present embodiment. In FIG. 1, the constituent elements from a writable optical disk 100 to a system controller 120 are the same as those described in the background art denoted by numerals 1600 to 1620 in FIG. 16. In the present embodiment, a reproduction information manager 130 and a bind definition designation information generator 131 are added to the above elements. [Content Reproduction Operation] Next, an operation of the reproducing apparatus having the above configuration when it reproduces a content recorded on an optical disk 100 will be described. The optical disk 100 holds content data such as main video image and main audio data. Further, data can be read/written from/to the optical disk 100 using an optical head unit 101. At an operation unit 109, when an optical disk reproduction request has been received from the user, the optical head unit 101 reads data, then an error corrector 103 performs error correction on the data, and then a separator 104 extracts content data and outputs the content data to a content decoder 107. The decoding by the content decoder 107 and output of the decoded data to an output unit 108 are the same as those in the above-described background art, accordingly, the detailed explanations of these operations will be omitted. Further, as in the case of the background art, sub contents such as caption data are recorded on a content server 110, and the reproducing apparatus can utilize the sub contents via a network. Note that as sub contents provided on the content server 110, computer graphics (CG), sub audio data and the like may be handled in addition to the caption data. Next, an operation of the reproducing apparatus upon reproduction of the sub contents recorded on the content server 110 will be described. The reproducing apparatus reads management information data recorded in a predetermined area of the optical disk 100 at a predetermined timing such as starting. The data read from the optical disk 100 is inputted into the separator 104. The separator 104 extracts management information data from the input data and outputs the extracted data to a management information decoder 105. The management information decoder 105 extracts bind definition designation information, product ID data and content server information from the management information data. Note that the bind definition designation information means information designating bind definition information (to be described later) recorded on the content server 110. The content server information and the product ID data are the same as those in the above-described background art. A network interface 106 establishes connection with the content server 110 designated with the content server information via the network, and outputs the product ID data and the bind definition designation information to the content server 110. The content server 110, holding plural bind definition information corresponding to product IDs, and returns one or plural bind definition information corresponding to the input bind definition designation information. The system controller 120 binds data on the content server 110 based on the bind definition information received from the content server 110. Next, the binding of data on the content server 110 will be more particularly described. FIG. 2 shows a file structure of content data stored on the optical disk 100. A directory 200 is a root directory of the content data stored on the optical disk 100; and a directory 210, a directory for storing management information. Data 211 is content server information; and data 212, product ID data. Further, a directory 213 is a directory for storing bind definition designation information; and data 214, the bind definition designation data. Further, a directory 220 is a main video directory holding video data; and data 221, the video data. Further, a directory 230 is a caption data directory holding caption data; and data 231, caption data (language A and language B). Further, a directory 240 is a directory for storing a special video image (e.g., in a cinema content, a video clip not related to a main part of the cinema). In the single optical disk having the structure shown in FIG. 2, main video data “main video image” and corresponding caption data “language A” and “language B” are recorded. Accordingly, the reproducing apparatus can make a selection from “language A” or “language B” captions for the “main video image” when it performs reproduction. As nothing is recorded in the special video image directory 240, any special video image cannot be reproduced from the single optical disk. On the other hand, FIG. 3 shows a file structure of content data stored on the content server 110. A directory 300 is a root directory of the content server 110; directories 310 and 320, directories holding content data corresponding to product IDs; a directory 330, a directory holding bind definition information; data 331, bind definition information; a directory 340, a directory holding caption data; and data 341, the caption data (C to F). Further, a directory 350 is a special video image directory holding a special video image; and data 351, special video data. When the contents on the content server having the structure shown in FIG. 3 are bound to the content on the optical disk 100, the reproducing apparatus sends the product ID data 212 and the bind definition designation information 214 recorded on the optical disk 100 to the content server 110 as described above. The content server 110 returns bind definition information specified with the product ID data 212 and the bind definition designation information 214 to the reproducing apparatus. For example, when the product ID of the optical disk 100 is “0001” and the bind definition designation information 214 designates “bind definition information 1”, the content server 110 returns “bind definition information 1” in the bind definition information directory 330 to the reproducing apparatus. The bind definition information is a file in which a procedure for bind processing is described. In this case, the “bind definition information 1” is a file in which a bind procedure for adding the contents, the “language C”, “language D” and “language E” caption data included in the caption directory 340 of the content server 110 to the caption directory 230 of the optical disk 100 is described. The reproducing apparatus binds the contents on the content server 110 to the content on the optical disk 100 in accordance with the received bind definition information. FIG. 4 shows the directory structure of the optical disk 100 in which the contents on the content server 110 are bound in accordance with the “bind definition information 1” in FIG. 3 (data structure after update). In FIG. 4, the directories and data correspond to the directories and data having the same numerals in FIG. 2. As a result of binding of the contents in accordance with the “bind definition information 1”, caption data 232 is newly added to the caption directory 230. The caption data 232 corresponds to the “language C”, “language D” and “language E” caption data 341 in FIG. 3. The caption data 232 after the binding is not actually recorded on the optical disk 100, but the caption data 232 is managed by the reproducing apparatus as link information to data on the content server 110. Further, since the “language C” to “language F” caption data are link information, upon issuance of reproduction instruction, they are downloaded via the network and reproduced. After the binding of the contents on the content server 110, the reproducing apparatus can make a selection from captions in 5 languages, “language A” to “language E” for the “main video image A” when it performs reproduction. [Addition of Bind Definition Designation Information] In the above description, the method for designating bind definition information used for binding based on bind definition designation information previously recorded on the optical disk 100 has been described. Next, additional recording of new bind definition designation information onto the optical disk 100 in correspondence with reproduction information will be described. In FIG. 1, when reproduction of content recorded on the optical disk 100 is performed, reproduction information indicating the reproduced content is recorded in the reproduction information manager 130. Next, by completion of reproduction of one content, the system controller 120 reads program data for determination of bind definition designation information from the optical disk 100. The program data for determination bind definition designation information is read from the optical disk 100, then extracted by the separator 104 and outputted to the bind definition designation information generator 131. In the program data for determination bind definition designation information, a procedure for determining bind definition designation information in accordance with the above-described reproduction information is described. The bind definition designation information generator 131 generates bind definition designation information by execution of the program. Next, the operation of the bind definition designation information generator 131 will be described in detail using FIG. 5. FIG. 5 is a flowchart showing the operation of the bind definition designation information generator 131. In step S501, reproduction information managed by the reproduction information manager 130 is obtained. As described above, the reproduction information is data indicating a reproduced content recorded on the optical 100. In step S502, bind definition information (331 in FIG. 3) recorded on the content server 110 to be designated is determined in accordance with the obtained reproduction information. The determination is made by executing the above-described program for determination of bind definition designation information. The program designates one or more pieces of bind definition information 331 stored on the content server 110 based on the reproduction information inputted from the reproduction information manager 130. For example, when reproduction of main video data 221 recorded on the optical disk 100 has been completed, new bind definition designation information “bind definition designation information 2” corresponding to the completion of reproduction of the main video data 221 is generated. The “bind definition designation information 2” designates the “bind definition information 2” among the bind definition information (331 in FIG. 3) included in the content server 110. In step S503, it is examined whether or not the bind definition designation information generated in step S502 is unrecorded on the optical disk 100. When the bind definition designation information is not recorded, the process proceeds to step S504. On the other hand, when the bind definition designation information is recorded, the process ends. In FIG. 2, in the bind definition designation information directory 213, only the “bind definition designation information 1” is recorded as bind definition designation information. In this case, as the “bind definition designation information 2” generated in step S502 is unrecorded, the process proceeds to step S504. In step S504, to record the bind definition designation information generated in step S502 onto the optical disk 100, the information is outputted to the optical head unit 101. By the above operation, when new bind definition designation information is outputted from the bind definition designation information generator 131, the system controller 120 records the bind definition designation information onto the optical disk 100. In the above description, the newly generated “bind definition designation information 2” is written onto the optical disk 100. The bind definition information on the content server 110 designated with the “bind definition designation information 2” is the “bind definition information 2” among the bind definition information 331 in FIG. 3. In the “bind definition information 2”, information to bind a “special video image A” and a “special video image B” among the special video images 351 to the special video image directory 240 of the optical disk 100 is described. Accordingly, the reproducing apparatus adds a “special video image A” and a “special video image B” to the special video image directory 240 by performing binding in accordance with the “bind definition information 2”. Note that the written “special video image A” and “special video image B” are not contents but information describing addresses of the special video image A and the special video image B on the content server 110. As the “bind definition designation information 2” has been newly added, the reproducing apparatus binds data on the content server 110 in accordance with information designated with the “bind definition information 1” and the “bind definition information 2”. FIG. 6 shows the file structure after the binding. In FIG. 6, the directories and the data correspond to those having the same numerals described in FIG. 4. In FIG. 6, “bind definition designation information 2” 215 and special video images 241 are newly added to the elements in FIG. 4. The special video images 241 are added by binding contents corresponding to the “bind definition information 2”. The reproducing apparatus in the status shown in FIG. 6 can make a selection from the captions in 5 languages i.e. “language A” to “language E” captions when it performs reproduction. Further, the contents of the special video images 241 (“special video image A” and “special video image B”) can be reproduced. As described above, the reproducing apparatus according to the present embodiment manages reproduction information of main video or sub contents, performs a program to generate bind definition designation information based on the reproduction information, thereby generates bind definition designation information. Then the generated bind definition designation information is written onto a recording medium. In this arrangement, contents which can be bound in accordance with reproduction condition can be additionally registered. In the above example, when all the main video image 221 has been reproduced, the special video images 241 newly provided from the content server 110 can be reproduced. In this manner, a user's watching unintended by a content producer, e.g., watching a special video image prior to a main part of a cinema (main video image 221) and knowing the end of the cinema, can be prevented. Further, contents provided from the content server 110 can be changed only by changing the bind definition information 331. Further, as the bind definition designation information 214 and 215 designating the bind definition information 331 stored on the content server 110 are recorded on the optical disk 100, contents reflecting a reproducing situation can be bound even upon reproduction by another reproducing apparatus. In the above embodiment, the program for determination of bind definition designation information is recorded on the optical disk 100, however, the program may be recorded on any other medium than the optical disk 100. For example, the program may be stored in a nonvolatile memory such as a ROM in the reproducing apparatus. In this case, condition information indicating bind definition information to be obtained upon completion of reproduction of corresponding content is stored on the optical disk 100. Further, the program may be recorded on the content server 110. Further, it may be arranged such that the reproducing apparatus sends reproduction information to the content server 110, and the content server 110 returns bind definition designation information based on the reproduction information. Further, in the above embodiment, bind definition designation information is determined based on whether or not a predetermined content has been reproduced, however, any other information, such as the number of reproduction times, reproduction time, reproduction information of plural contents, can be used as reproduction information. For example, it may be arranged such that bind definition designation information to bind a special video image is generated when a CM content has been reproduced a predetermined number of times. Further, the content server 110 may not be a single server but plural servers may be used. Further, in the above embodiment, audio data content is omitted for the sake of simplification of explanation. The content recorded on the optical disk 100 may other forms of data than video data such as audio data. Further, the contents provided from the content server 110 are not limited to video contents but other data such as audio data and application software may be used. Further, in the above embodiment, the reproducing apparatus having a network interface establishes connection with the content server via the network interface. However, as the feature of the present invention is generation of bind definition designation information based on content reproduction information and writing the bind definition designation information onto a recording medium, it is not necessary for the video reproducing apparatus to have a unit for connection with the content server. Second Embodiment As a second embodiment, a reproducing apparatus, having an image pickup function, capable of recording/reproducing video and audio data stored on a recording medium such as an optical disk will be described. FIG. 7 is a block diagram showing the configuration of a digital video camera as a reproducing apparatus having an image pickup function and a data recording and reproduction function according to the present embodiment. In FIG. 7, the constituent elements from a writable optical disk 700 to a system controller 720 are the same as those described in the background art denoted by numerals 1600 to 1620 in FIG. 16. In the present embodiment, an image pickup unit 750 including an optical system such as a lens and image pickup device such as a CCD, a video signal processor 751, a content encoder 752, a multiplexer 753, a photographing information manager 754 and a bind definition designation information generator 755 are provided in addition to the above elements. Further, as a particular photographing information generation unit, a position detection unit 760 using a GPS (Global Positioning System) to obtain position information upon photographing is provided. Further, a microphone to obtain an audio signal and an audio signal processor are provided in addition to the image sensing system, however, these elements are not shown for the sake of simplification of explanation. [Operation Upon Photographed Data Reproduction] First, an operation in the reproducing apparatus upon reproduction of photographed video data recorded on the optical disk 700 will be described. The optical disk 700 holds video data photographed by the image pickup unit 750 (an operation upon photographing will be described later). Data can be read/written from/onto the optical disk 700 using an optical head unit 701. When an operation unit 709 receives an optical disk reproduction request from a user, the optical head unit 701 reads the data, then an error corrector 702 performs error correction on the read data, and a separator 704 extracts video data from the data. Further, a content decoder 707 decodes the video data and outputs the decoded data to an output unit 708. As the operations upon reproduction are the same as those upon optical disk reproduction in the above-described the first embodiment, the detailed explanations of the operations will be omitted. [Operation Upon Content Reproduction On Content Server] Next, an operation upon reproduction of content recorded on a content server 710 will be described. The content server 710 holds video contents corresponding to photographing positions (e.g., area information video images corresponding to position information) as sub contents. When the operation unit 709 receives a sub content display instruction from the user, the content data recorded on the content server 710 are bound. Hereinbelow, an operation of the content server 710 upon binding will be described. The optical head unit 701 reads data including management information recorded in a predetermined area of the optical disk 700. The data read from the optical disk 700 is inputted into the separator 704. The separator 704 extracts management information data from the input data and outputs the extracted data to a management information decoder 705. The management information decoder 705 extracts bind definition designation information, a maker ID data and content server information from the management information data. As in the case of the first embodiment, the bind definition designation information is information designating bind definition information recorded on the content server 710. The generation of the bind definition designation information and recording of the information onto the optical disk 700 will be described later. In this example, the bind definition designation information is previously recorded on the optical disk. Further, the maker ID is the ID of a maker of the reproducing apparatus that recorded data on the disk. The maker ID is recorded on the optical disk 700 upon recording of photographed data as described later. Note that the content server information indicates the location of the content server 710. A network interface 706 establishes connection with the content server 710 designated with the content server information via the network, and outputs the bind definition designation information to the content server 710. The content server 710, holding plural bind definition information, returns bind definition information designated with the bind definition designation information from the plural bind definition information. The system controller 720 obtains the bind definition information from the content server 710 via the network interface 706, and binds data on the content server 710 based on the bind definition information. Next, the file structure upon binding will be described using FIGS. 8 to 10. FIG. 8 shows an example of the directory structure of the data stored on the optical disk 700. In FIG.8, a directory 800 is a root directory of content data recorded on the optical disk 700; a directory 810, a directory holding disk management information; data 811, content server information; data 812, a maker ID; a directory 813, a directory holding bind definition designation information; and data 814, bind definition designation information. Further, a directory 820 is a directory holding video data; data 821, video data; and a directory 830, a directory holding sub content data. In the single optical disk in FIG. 8, only photographed video data 821 is recorded as a content. In the status of FIG. 8 where data on the content server 710 are not bound, no sub video content is recorded in the directory 830. Accordingly, at this stage, no sub video content can be reproduced. On the other hand, FIG. 9 shows the directory structure of content data stored on the content server 710. A directory 900 is a root directory of the content server 710; directories 910 and 920, directories holding content data corresponding to maker IDs; a directory 930, a directory holding bind definition information; data 931, bind definition information; directories 940 and 950, directories holding sub video contents; and data 941 and 951, sub video contents. Upon binding of the data on the content server 710 having the directory structure shown in FIG. 9, the reproducing apparatus sends the maker ID and the bind definition designation information 814 recorded on the optical disk 700 to the content server 710 as described above. The content server 710 returns bind definition information 931 designated with the bind definition designation information 814 to the reproducing apparatus. As in the case of the first embodiment, the bind definition information is a file where a binding procedure is described. For example, when the maker ID is “maker 0001” and the bind definition designation information designates “bind definition information 1”, the content server 710 returns “bind definition information 1” in the bind definition information directory 930 to the reproducing apparatus. In the “bind definition information 1”, information to add sub video contents 941, “sub video image A-1” to “sub video image A-4”, included in the sub video content directory 940 of the content server 710, to the sub video directory 830 of the optical disk 700 is described. The reproducing apparatus binds the contents on the content server 710 to the content on the optical disk 700 in accordance with the received “bind definition information 1”. FIG. 10 shows the directory structure of the optical disk 700 in which the contents on the content server 710 are bound. In FIG. 10, the directories and data correspond to the directories and data having the same numerals in FIG. 8. As a result of binding of the contents in accordance with the “bind definition information 1”, sub video contents 831 are newly added. The sub video contents 831 are data corresponding to the sub video contents 941 in FIG. 9. As in the case of the first embodiment, the sub video contents 831 after the binding are not actually recorded on the optical disk 700 but managed by the reproducing apparatus as link information to the data stored on the content server 710. After the binding of the contents on the content server 710, the reproducing apparatus can reproduce the photographed data 821 and the sub video data 831. [Operation Upon Photographing] Next, returning to FIG. 7, an operation upon recording of photographed video data obtained by the image pickup unit 750 onto the optical disk 700 will be described. The reproducing apparatus according to the second embodiment generates the above-described bind definition designation information and records the information onto the optical disk 700 upon recording of photographed video data. When the operation unit 709 receives an operation instruction to start photographing from the user, the image pickup unit 750 converts an optical image of a subject through the optical system into a video signal using the image pickup device, and outputs the signal to the video signal processor 751. The video signal processor 751 converts the video signal into digital data, performs video signal processing such as gamma correction and outline emphasis on the data, and outputs the data to the output unit 708 and the content encoder 752. The output unit 708 outputs the video data to an output device such as a liquid crystal monitor. The content encoder 752 compression-encodes the video data into predetermined code format data such as MPEG 2, and outputs the compression-coded data to the multiplexer 753. The multiplexer 753 multiplexes the compression-coded data of the video signal and compression-coded data of an audio signal (not shown), and outputs the multiplexed data to the optical head unit 701. The optical head unit 701 records the data onto the optical disk 700. Next, when the operation unit 709 receives a photographing completion operation from the user, the system controller 720 stops the photographed video data recording operation. Further, the system controller 720 controls the GPS 755 to obtain positional data. The GPS 755 receives a radio wave from a GPS satellite and analyzes the wave, obtains data on the location of the apparatus, and outputs the data to the system controller 720. The system controller 720 outputs photographing position information from the GPS 755 to the photographing information manager 754. The photographing information manager 754 manages the photographed video data and the photographing position as data linked to each other. The bind definition designation information generator 755 generates information designating bind definition information recorded on the content server 710. Next, the operation of the bind definition designation information generator 755 will be described in detail using FIG. 11. FIG. 11 is a flowchart showing the operation of the bind definition designation information generator 755. At step S1101, photographing information managed by the photographing information manager 754 is obtained. In this example, photographing position information is obtained as the photographing information. At step S1102, bind definition information to be designated is determined among the bind definition information recorded on the content server 710 (931 in FIG. 9). The reproducing apparatus has a ROM holding a program to determine bind definition information to be designated. The reproducing apparatus performs the program thereby generates information designating bind definition information recorded on the content server 710 based on the maker ID of the reproducing apparatus and the photographing information (photographing position information). For example, when the maker ID of the reproducing apparatus according to the second embodiment is “0001” and the photographing position information of newly photographed video data is “area A”, the program to generate bind definition designation information selects bind definition information included in the directory 910 corresponding to the maker ID “0001”, from the contents recorded on the content server 710. In this case, the “bind definition information 1” referring to the sub video content 941 related to the “area A” is selected from the bind definition information 931. Then, “bind definition designation information” as information designating the selected “bind definition information 1” is generated. Then, at step S1103, it is examined whether or not the bind definition designation information generated at step S1102 is unrecorded on the optical disk 700. When the bind definition designation information is unrecorded on the optical disk 700, the process proceeds to step S1104. On the other hand, when the bind definition designation information is recorded on the optical disk 700, the process ends. At step S1104, the bind definition designation information generated at step S1102 is outputted to the optical head unit 701 such that the information is recorded onto the optical disk 700. Further, the maker ID of the reproducing apparatus is also outputted to the optical head unit 701 such that the ID is recorded onto the optical disk 700. As a result of the above operation, new bind definition designation information is outputted from the bind definition designation information generator 755, then the system controller 720 records the generated bind definition designation information onto the optical disk 700. As described above, the reproducing apparatus having an image pickup function and a recording and reproducing function according to the present embodiment, having the image pickup unit and a unit to record photographed video data, manages photographing information on video data photographed by the image pickup unit 750. Further, the program to generate bind definition designation information based on the photographing information is performed, thereby bind definition designation information is generated, and the generated bind definition designation information is written onto the recording medium. In this arrangement, sub contents corresponding to the photographing information of the video data can be bound and reproduced. In the above description, the program to generate bind definition designation information is previously stored in the internal ROM, however, the program is not necessarily stored in the internal ROM. For example, the program may be obtained from the content server 710. Further, it may be arranged such that the reproducing apparatus sends the photographing position information and the ID maker to the content server 710, and the content server 710 returns bind definition designation information based on the photographing position information. Further, it may be arranged such that the program to determine bind definition designation information is recorded on a removable recording medium such as a memory card and the program is read from the recording medium. Further, in the above embodiment, the bind definition designation information is determined in accordance with the maker ID of the reproducing apparatus and the photographing position. However, the bind definition designation information may be determined in accordance with any other information upon photographing, such as photographing time, a total photographing period, a photographer, a photographing subject or a photographing mode as long as the bind definition designation information is determined. For example, it may be arranged such that it is determined whether or not the user is an advanced user in correspondence with total photographing period and/or photographing mode (auto photographing or manual photographing) as an image pickup apparatus, and when it is determined that the user is an advanced user, more editing contents are provided. Further, the bind definition designation information may be determined based on only the maker ID. Further, in the above example, the newly generated bind definition designation information is added to the bind definition designation information directory (812 in FIG. 8), however, it may be arranged such that in the bind definition designation information directory, existing bind definition designation information is replaced with the newly generated bind definition designation information. Further, in the above embodiment, the data on the content server 710 are bound upon reproduction of the data on the content server 710, however, the timing of the binding is not limited. For example, the binding may be performed upon power-on of the reproducing apparatus, or upon mode change to a photographing mode. Further, in the above embodiment, the sub video data are provided as sub contents from the content server, however, the sub contents are not limited to the video data. For example, application software may be provided from the content server as sub contents. Further, in the above embodiment, the reproducing apparatus having a network interface establishes connection with the content server via the network interface. However, as the feature of the present invention is writing of bind definition designation information onto a recording medium based on photographing information, it is not necessary to provide a unit to establish connection with the content server. Further, in the above embodiment, the contents recorded on the content server 710 are bound for the optical disk 700, however, the subject of binding is not limited to the optical disk. For example, the contents on the content server may be bound for a content recorded in an internal memory of the reproducing apparatus. Third Embodiment Next, as a third embodiment, the reproducing apparatus in which a video editing function is further added to the above-described second embodiment will be described. FIG. 12 is a block diagram showing the configuration of a digital video camera as the reproducing apparatus having an image pickup function, a data recording and reproducing function and an editing function according to the present embodiment. In FIG. 12, the constituent elements from a writable optical disk 1200 to a bind definition designation information generator 1255 are the same as those described in the second embodiment denoted by numerals 700 to 755. Further, as in the case of the second embodiment, a GPS (Global Positioning System) 1260 to obtain position information is provided as a particular photographing information generation unit. In the third embodiment, the difference from the second embodiment is that an editor 1270 for editing video data is provided. [Operation Upon Reproduction] First, an operation of the reproducing apparatus having the above configuration upon reproduction of photographed video data recorded on the optical disk 1200 will be described. The optical disk 1200 holds video data photographed by an image pickup unit 1250 (the operation upon photographing will be described later). Data can be read/written to/from the optical disk 1200 using an optical head unit 1201. When an operation unit 1209 receives an optical disk reproduction request from a user, the optical head unit 1201 reads data, and an error corrector 1203 performs error correction, and a separator 1204 extracts video data. Further, a content decoder 1207 decodes the video data, and outputs the data to an output unit 1208. As the operations upon reproduction are the same as those upon optical disk reproduction in the above-described first and second embodiments, the detailed explanations of the operations will be omitted. [Operation Upon Editing] Next, an operation when video data recorded on the optical disk 1200 is edited using content(s) recorded on a content server 1210 will be described. The content server 1210 holds editing contents for editing video data. As the editing contents, image contents to be combined with photographed video images, special effect contents in which special effects such as fading and wiping to connect video images are described are held. When the operation unit 1209 receives a mode change instruction to switch to an editing mode from the user, the apparatus switches to the editing mode, and bind the content data recorded on the content server 1210. Hereinbelow, the operation of the content server 1210 upon binding will be described. The optical head unit 1201 reads management information data recorded in a predetermined area of the optical disk 1200. The data read from the optical disk 1200 is inputted into the separator 1204. The separator 1204 extracts the management information data from the input data, and outputs the extracted data to a management information decoder 1205. The management information decoder 1205 extracts bind definition designation information, maker ID data and content server information from the management information data. As in the case of the second embodiment, the bind definition designation information is information to designate bind definition information recorded on the content server 1210. The generation of the bind definition designation information and recording of the information onto the optical disk 1200 will be described later. In this example, the bind definition designation information is previously recorded on the optical disk 1200. Further, the maker ID is a maker ID of the reproducing apparatus recorded data onto the optical disk. The maker ID is recorded onto the optical disk 1200 upon recording of the photographed data as described later. Note that the content server information is data indicating the location of the content server 1210. A network interface 1206 establishes connection with the content server 1210 designated with the content server information via the network, and outputs the bind definition designation information to the content server 1210. As in the case of the first and second embodiments, the content server 1210 holding plural bind definition information returns bind definition information corresponding to the input bind definition designation information from the plural bind definition information. The system controller 1220 binds the data on the content server 1210 based on the bind definition designation information received from the content server 1210. Next, the file structure upon binding will be described using FIGS. 13 to 15. FIG. 13 shows an example of the directory structure of data stored on the optical disk 1200. In FIG. 13, a directory 1300 is a root directory of the content data recorded on the optical disk 1200; a directory 1310, a directory holding disk management information; data 1311, content server information; data 1312, a maker ID; a directory 1313, a directory holding bind definition designation information; and data 1314, bind definition designation information. These information are generated under the control of the system controller 1220 upon setting of a new optical disk 1200. Further, a directory 1320 is a directory holding video data; data 1321, video data; and a directory 1330, a directory holding editing content data. In the single optical disk shown in FIG. 13, only the photographed video data 1321 is recorded as a content. In FIG. 13 showing a status where no data on the content server 1210 is bound, no data is recorded in the editing material content directory 1330. Accordingly, at this stage, no editing material content can be used. On the other hand, FIG. 14 shows an example of the directory structure of content data stored on the content server 1210. A directory 1400 is a root directory of the content data on the content server 1210; directories 1410 and 1420, directories holding content data corresponding to maker IDs; a directory 1430, a directory holding bind definition information; data 1431, bind definition information; directories 1440 and 1450, directories holding editing contents; and data 1441 and 1451, editing contents. As in the case of the above embodiments, upon binding of data on the content server 1210 having the directory structure shown in FIG. 14, the reproducing apparatus sends the maker ID and the bind definition designation information 1313 recorded on the optical disk 1200 to the content server 1210. The content server 1210 returns bind definition information designated with the bind definition designation information 1313 to the reproducing apparatus. As in the case of the above-described first embodiment, the bind definition information is a file in which a bind procedure is described. For example, when the maker ID of the reproducing apparatus according to the third embodiment is “maker 0001” and the bind definition designation information designates “bind definition information 1”, the content server 1210 returns “bind definition information 1” in the bind definition information directory 1430 to the reproducing apparatus in response to a request from the reproducing apparatus. In the “bind definition information 1”, information to add editing material contents 1441, “editing material A-1” to “editing material A-4” in the editing content directory 1440 of the content server 1210 to the editing material directory 1330 of the optical disk 1200 is described. The reproducing apparatus binds the contents on the content server 1210 to the content on the optical disk 1200 in accordance with the received “bind definition information 1”. FIG. 15 shows the directory structure of the optical disk 1200 in which the contents on the content server 1210 are bound. In FIG. 15, the directories and data correspond to the directories and data having the same reference numerals in FIG. 13. As a result of binding the contents in accordance with the “bind definition information 1”, editing material contents 1331 are newly added. The editing material contents 1331 are data corresponding to the editing material contents 1441 in FIG. 18. As in the case of the above-described first and second embodiments, the editing material contents 1331 after the binding are not actually recorded onto the optical disk 1200, but managed by the reproducing apparatus as link information to the data stored on the content server 1210. After the binding of the contents on the content server 1210, the reproducing apparatus can edit a video image utilizing the editing material contents 1331. The operation upon binding has been described as above. Next, returning to FIG. 12, an operation upon editing photographed video data using the bound contents on the content server 1210 will be described. In an editing mode, when a photographed image is selected by the user's operation as the subject of editing, the subject photographed image is read from the optical disk 1200. The content decoder 1207 decodes the read photographed image data, and outputs the decoded image to the editor 1270. Further, when the bound editing material content(s) on the content server 1210 are selected by the user's operation, the selected editing material content(s) are downloaded from the content server 1210 via the network interface 1206. The content decoder 1207 decodes the downloaded editing material content(s), then outputs the decoded content(s) to the editor 1270. The editor 1270 performs editing such as coupling of plural photographed images or combining photographed image and editing material content, thereby generates edited video data. The edited video data is outputted to a content encoder 1252 and the output unit 1208. The output unit 1208 outputs the edited video data to an output device such as a liquid crystal monitor. On the other hand, the content encoder 1252 encodes the edited video data to predetermined format data such as MPEG 2, and outputs the coded data to a multiplexer 1253. The multiplexer 1253 multiplexes the edited video data with audio data or the like (not shown) and outputs the multiplexed data to the optical head unit 1201. The optical head unit 1201 records the combined video data onto the optical disk 1200. In this manner, the bound data on the content server 1210 can be utilized in editing. [Operation Upon Photographing] Next, an operation upon recording of photographed video data obtained by the image pickup unit 1250 onto the optical disk 1200 will be described. The operation upon photographing is basically the same as that in the second embodiment. Upon recording of photographed video data, the reproducing apparatus according to the present embodiment generates bind definition designation information corresponding to photographing information and records the information onto the optical disk 1200. When the operation unit 1209 receives a photographing start operation instruction from a user, the image pickup unit 1250 converts an optical image of a subject through the optical system into a video signal using the image pickup device, and outputs the signal to the video signal processor 1251. The video signal processor 1251 converts the video signal into digital data, performs video signal processing such as gamma correction and outline emphasis on the data, and outputs the data to the output unit 1208 and the content encoder 1252. The output unit 1208 outputs the video data to an output device such as a liquid crystal monitor. The content encoder 1252 compression-encodes the video data into predetermined code format data such as MPEG 2, and outputs the compression-coded data to the 1253. The multiplexer 1253 multiplexes the compression-coded data of the video signal and compression-coded data of an audio signal (not shown), and outputs the multiplexed data to the optical head unit 1201. The optical head unit 1201 records the photographed data onto the optical disk 1200. Next, when the operation unit 1209 receives the user's photographing termination operation, the system controller 1220 stops recording operation of photographed video data. Further, the system controller 1220 obtains positional data from the GPS 1260, and outputs photographing position information to a photographing information manager 1254. The photographing information manager 1254 manages the photographed video data and the photographing position information as data linked to each other. Next, an operation of the bind definition designation information generator 1255 will be described. The bind definition designation information generator 1255 generates information designating bind definition information recorded on the content server 1210. The bind definition designation information generator 1255 generates bind definition designation information corresponding to photographing position information managed by the photographing information manager 1256. For example, when the maker ID of the reproducing apparatus according to the present embodiment is “0001” and the photographing position information of newly photographed video data is “area A”, in the program to generate bind definition designation information, bind definition information included in the directory 1410 corresponding to the maker ID “0001” is selected from the contents recorded on the content server 1210. In this case, “bind definition information 1” referring to the editing content 1441 related to the “area A” is selected from the bind definition information 1431. Then, “bind definition designation information” as information designating the selected “bind definition information 1” is generated. When the new bind definition designation information is outputted from the bind definition designation information generator 1255, the system controller 1220 records the generated bind definition designation information onto the optical disk 1200. As described above, the reproducing apparatus according to the third embodiment manages the photographing information of video data, and performs the program to generate bind definition designation information based on the photographing information, thereby generates bind definition designation information. Then, the apparatus writes the generated bind definition designation information onto a recording medium. In this arrangement, upon editing of photographed data, editing content(s) corresponding to a photographing position can be bound and utilized. Further, in the above embodiment, the data on the content server 1210 is bound upon switching to the editing mode, however, the binding may be performed at any timing. For example, the binding may be performed at timing of power-on of the reproducing apparatus or a timing of switching to the photographing mode. Further, in the above embodiment, the editing contents are provided from the content server as sub contents, however, the sub contents provided from the content server are not limited to the editing contents. For example, application software and the like may be provided. Further, in the above embodiment, as the network interface, a cable network interface or a radio network interface may be employed. In the above-described embodiments of the present invention, the respective processings according to the embodiments are performed by the system controller, which generally has a CPU and a memory holding a program to realize its processings. Accordingly, the present invention includes such computer program in its scope. Further, generally, a computer program is stored on a computer-readable storage medium such as a CD-ROM and is executable when it is installed or copied in a computer system. Accordingly, it is apparent that the present invention includes such computer-readable storage medium in its scope. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. This application claims the benefit of Japanese Patent Application No. 2006-175787, filed Jun. 26, 2006, which is hereby incorporated by reference herein in its entirety.	G	60G06	161G06F	15	16
11802015	US20080288677A1-20081120	KVM switch system with a simplified external controller	ACCEPTED	20081105	20081120	[]	G06F1312	["G06F1312"]	7730243	20070518	20100601	710	062000	84674.0	CHEN	ALAN	[{"inventor_name_last": "Kirshtein", "inventor_name_first": "Philip M.", "inventor_city": "New Market", "inventor_state": "AL", "inventor_country": "US"}]	A KVM switch system with external control functionality is described. A KVM switch is able to be controlled from an external device. The external device can either include a single button dedicated to controlling the desktop KVM switch or indicate a state of the KVM switch. The external device can be connected to the desktop KVM switch through a plurality of communication media. The external device can be small in size and attached to an object on a user's desktop.	1. An external controller for use with a peripheral switch coupling user peripheral devices to a plurality of target devices, the external controller comprising: a communications interface for coupling the external controller to the peripheral switch; a selector switch for requesting that the external controller change which of the plurality of target devices is connected to the user peripheral devices; control circuitry for commanding, via the communications interface, the peripheral switch to couple the user peripheral devices to at least one of the plurality of target devices; and a display adapted to indicate which of the plurality of target devices is coupled to the user station hub, wherein the external controller does not include an interface for receiving video signals from the plurality of target devices. 2. The external controller of claim 1, wherein said communications interface is an RJ45 interface. 3. The external controller of claim 1, wherein said communications interface is a wireless interface. 4. The external controller of claim 1, wherein said display comprises a series of LEDs. 5. The external controller of claim 1, wherein said display comprises an LCD display. 6. The external controller of claim 1, wherein said external controller is integrated into a mouse pad. 7. The external controller of claim 1, wherein said selector switch and said display encompass substantially all of one face of the external controller. 8. The external controller of claim 1, wherein said control circuitry commands the peripheral switch to couple the user peripheral devices to at least one of the plurality of target devices by converting an actuation of said selector switch into a keystroke sequence receivable by said peripheral switch for causing the KVM switch to change which of plural target devices the KVM switch connects the user peripheral devices to. 9. A micro-receiver comprising: an input interface adapted to couple a computer peripheral to said micro-receiver; an output interface adapted to couple said micro-receiver to a computer peripheral port of a KVM switch; a command interface, separate from the input interface, for receiving commands from an external controller; and a converter for converting commands received from the external controller to commands that can be received by a KVM switch and applying the converted commands to the output interface. 10. The micro-receiver of claim 9, wherein the command interface comprises a wireless interface. 11. The micro-receiver of claim 9, wherein said converter is reprogrammable such that the converter can convert commands received from the external controller into commands that can be received by a particular KVM switch of a plurality of possible KVM switches. 12. The micro-receiver of claim 9, wherein said converter converts commands received by an external controller into a keystroke sequence receivable by a KVM switch for causing the KVM switch to change which of plural target devices the KVM switch connects the user peripheral devices to. 13. A peripheral switch system comprising: a peripheral switch coupling user peripheral devices to a plurality of target devices; an external controller for use with the peripheral switch coupling user peripheral devices to a plurality of target devices, the external controller comprising: a communications interface for coupling the external controller to the peripheral switch; a selector switch for requesting that the external controller change which of the plurality of target devices is connected to the user peripheral devices; control circuitry for commanding, via the communications interface, the peripheral switch to couple the user peripheral devices to at least one of the plurality of target devices; and a display adapted to indicate which of the plurality of target devices is coupled to the user station hub, wherein the external controller does not include an interface for receiving video signals from the plurality of target devices.	<SOH> FIELD OF DISCLOSURE <EOH>This disclosure relates to a simplified external controller for controlling a KVM (Keyboard, Video, Mouse) switch.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The following description, given with respect to the attached drawings, may be better understood with reference to the non-limiting examples of the drawing, wherein the drawings show: FIG. 1 : a prior art single user desktop KVM switch with an onboard selection mechanism; FIG. 2 : a prior art single user desktop KVM switch system that supports multiple keyboards; FIG. 3 : a prior art single user desktop KVM switch system that supports an external keypad; FIG. 4 : a prior art desktop KVM switch system with an external selection mechanism where the external selection mechanism interfaces all of the user's KVM devices; FIG. 5 : a prior art KVM switch system where multiple users' KVM devices are connected directly to the KVM switch; FIG. 6 : a prior art KVM switch system where multiple users are connected to the KVM switch through user stations; FIG. 7 : a prior art KVM switch system where a remote terminal can access the switch through a network; FIG. 8 : an exemplary embodiment of a KVM switch system with an external controller; FIG. 9 : an exemplary external controller; FIG. 10 : an exemplary block diagram of an exemplary external controller; FIG. 11 : an exemplary external controller built-into a mouse pad; FIG. 12 : an alternative exemplary embodiment of a KVM switch system with an external controller; FIG. 13 a : a KVM switch system incorporating an alternative exemplary external controller; FIG. 13 b : a KVM switch system incorporating an alternative exemplary external controller; FIG. 13 c : an exemplary block diagram of an exemplary external controller; FIG. 14 : an exemplary embodiment of a KVM switch system with external controllers; FIG. 15 : an exemplary KVM switch system incorporating an external controller and a micro-receiver; FIG. 16 : an exemplary external controller with a micro-receiver; FIG. 17 : a block diagram of an exemplary micro-receiver; FIG. 18 : a diagram illustrating various ways to configure a KVM switch system with an external controller and a micro-receiver; and FIG. 19 : an exemplary KVM switch system incorporating an external controller and a micro-receiver. detailed-description description="Detailed Description" end="lead"?	FIELD OF DISCLOSURE This disclosure relates to a simplified external controller for controlling a KVM (Keyboard, Video, Mouse) switch. BRIEF DESCRIPTION OF THE DRAWINGS The following description, given with respect to the attached drawings, may be better understood with reference to the non-limiting examples of the drawing, wherein the drawings show: FIG. 1: a prior art single user desktop KVM switch with an onboard selection mechanism; FIG. 2: a prior art single user desktop KVM switch system that supports multiple keyboards; FIG. 3: a prior art single user desktop KVM switch system that supports an external keypad; FIG. 4: a prior art desktop KVM switch system with an external selection mechanism where the external selection mechanism interfaces all of the user's KVM devices; FIG. 5: a prior art KVM switch system where multiple users' KVM devices are connected directly to the KVM switch; FIG. 6: a prior art KVM switch system where multiple users are connected to the KVM switch through user stations; FIG. 7: a prior art KVM switch system where a remote terminal can access the switch through a network; FIG. 8: an exemplary embodiment of a KVM switch system with an external controller; FIG. 9: an exemplary external controller; FIG. 10: an exemplary block diagram of an exemplary external controller; FIG. 11: an exemplary external controller built-into a mouse pad; FIG. 12: an alternative exemplary embodiment of a KVM switch system with an external controller; FIG. 13a: a KVM switch system incorporating an alternative exemplary external controller; FIG. 13b: a KVM switch system incorporating an alternative exemplary external controller; FIG. 13c: an exemplary block diagram of an exemplary external controller; FIG. 14: an exemplary embodiment of a KVM switch system with external controllers; FIG. 15: an exemplary KVM switch system incorporating an external controller and a micro-receiver; FIG. 16: an exemplary external controller with a micro-receiver; FIG. 17: a block diagram of an exemplary micro-receiver; FIG. 18: a diagram illustrating various ways to configure a KVM switch system with an external controller and a micro-receiver; and FIG. 19: an exemplary KVM switch system incorporating an external controller and a micro-receiver. INTRODUCTION Desktop KVM (Keyboard, Video, and Mouse) switches are designed to allow a single user control of multiple PCs (targets) using a single keyboard, monitor, and mouse. Desktop KVM switches can be designed to interface with either PS/2 or USB type control devices and can be designed to allow a user control of any number of targets through such connections. Desktop KVM switches control a target by simply providing a connection between the target's KVM ports and a user's respective keyboard, monitor, and mouse. Examples of such KVM switches are Avocent KVM switches sold under the trademark SWITCHVIEW. SwitchView KVM switches are described in submitted document entitled “SwitchView Desktop KVM Switches,” published by Avocent 2005, Document No. 1105-SV-BRO, which is incorporated by reference in its entirety. FIG. 1 shows a prior art 4-port desktop KVM switch 100 capable of controlling four targets. Switch 100 receives video signals from respective targets (not shown) at video ports 104 and accesses keyboard and mouse ports from respective targets at ports 106. Switch 100 allows a user to control a designated target by coupling the communication path from a selected target interfaced at 104 and 106 to user KVM port 102. KVM port 102 includes a video connection, a keyboard connection, and a mouse connection. Such switches include an onboard control interface 108 which typically includes a display 108a. Typically displays, as shown for display 108a, consist of an LED for each target device KVM port, where an illuminated LED indicates that the corresponding KVM port is being coupled to port 102 and as such a corresponding target is being controlled by the user. Such switches are typically designed to be placed within reach of the user (e.g. on a desktop) so that a user can switch which target is being controlled using an onboard control mechanism 108b. Control mechanism 108b is typically a select button that when pressed cycles through KVM ports corresponding to the targets. U.S. Pat. No. 6,073,188 to Fleming, which is incorporated by reference in its entirety, discloses a KVM switch with an onboard control interface for controlling which target is coupled to the user and a display indicating which target device is coupled to the user. Other KVM switch boxes with on-board displays have also been manufactured and sold in prior art switches of Avocent Corporation of Huntsville, Ala. and its predecessors Apex Computer Products of Redmond, Wash. and Cybex Corporation products of Huntsville, Ala. In addition to using the control mechanism 108b to switch between targets, some prior art desktop KVM switches enable the user to switch between targets at the user station with the user's keyboard by using hotkey commands. For example, a user may switch to a target by pressing the ScrLk Key twice and then pressing a number (1-4) corresponding to the set of KVM ports a target is connected to. U.S. Pat. No. 5,721,842 to Beasley, which is commonly owned by the assignee of the present application, Avocent Corporation of Huntsville, Ala., and is incorporated by reference in its entirety, describes a KVM switch that can be controlled at a user station by using hotkey commands in combination with a graphical user interface that is displayed on the user's monitor. Beasley describes that the user can switch which target device is coupled to the user's KVM port by using a keystroke (Print Screen key) to activate an onscreen menu and selecting a command from the onscreen menu. Hotkey commands have the drawback of requiring a user to memorize a sequence of keystrokes or have access to a reference which specifies which keystrokes correspond to which functions. Hotkeys also suffer from the drawback that the user may inadvertently activate a hotkey command through keystrokes that occur within the normal course of controlling a target. Further, when the switch 100 is not within the user's view, the user is unable to use the display 108a to confirm which target is coupled to the KVM port 102, which could cause a user to inadvertently control the wrong target. Although hotkey commands incorporating a graphical user interface displayed on the user's monitor have been highly successful and commercially advantageous, especially in medium and large scale installations, when the graphical user interface is displayed it must be overlayed on the image being displayed on the user's monitor and as such might obscure important information. For small installations (such as 1×2 and 1×4), using a graphical user interface to switch which target is being controlled is not as simple as using an onboard control interface since a user must enter keystrokes and then select a target from a menu as opposed to just manipulating a physical access mechanism. Further, hotkey commands incorporating a graphical user interface require some type of video output generating circuit to create the graphical user interface which adds significant cost to the switch system, especially where USB peripheral devices are supported. The following paragraphs and accompanying FIGS. 2-7 describe additional prior art KVM switch systems and the ways that such systems allow for a user to be connected to a target. FIG. 2 shows a prior art single user KVM switch 200 with a plurality of keyboard and mouse connections where each of a plurality of targets 112 is connected to switch 200 via respective KVM connections 114a, 114b, 114c, and 114d. KVM switch 200 is similar to KVM switch 100 described in accordance with FIG. 1 and is designed for a single user. Switch 200 does not provide multiple monitor connections, but provides multiple sets of keyboard and mouse connections—typically a set of PS/2 ports and a USB port to allow a user to connect either type of keyboard/mouse devices. Since switch 200 has two sets of ports, a user can connect multiple keyboards to switch 200 simultaneously. Although KVM switch 200 allows a user to have multiple keyboards connected to KVM switch 200 simultaneously (with one keyboard controlling a target and the other switching which target is being controlled), KVM switch 200 does not solve the drawbacks of hotkey commands and has the additional drawback that two keyboards may clutter the user's workspace 110. Further, standard keyboards will not provide the user with an indication as to which target is being controlled. An example of such a switch is the Avocent SWITCHVIEW MM1/MM2 switches which are described in submitted document entitled “SwitchView Desktop KVM Switches” published by Avocent Corporation in 2005, Document No. 1105-SV-BRO, which is incorporated by reference in its entirety. FIG. 3 shows a prior art single user KVM switch 300 with a plurality of keyboard and mouse connections where each of a plurality of targets 112 is connected to switch 300 via respective KVM connections 114a, 114b, 114c, and 114d. KVM switch 300 includes an auxiliary port (not shown) for connecting external keypad 308. Auxiliary port of KVM switch 300 is an RJ-45 port. External keypad 308 allows the user to switch which target device is being controlled without using the keyboard. Keypad 308 does not include a display indicating which of the targets 112 the user is controlling. Examples of such KVM switches are KVM switches that were sold under the under the name Apex Outlook. Apex Outlook KVM switches are described in submitted document entitled “Outlook User Guide” Fourth Edition, August 1998, which is incorporated by reference in its entirety. U.S. Pat. No. 5,499,377 to Lee, which is incorporated by reference in its entirety, describes a desktop KVM switch where a user can switch which target is being controlled by using a control mechanism that is similar to the onboard control interface 108 described in accordance with FIG. 1. That control mechanism is on a selector device that is external to the KVM switch. The selector device described in Lee is located intermediate to the user and the KVM switch and interfaces all of the user's KVM devices and the switch. The selector device in Lee includes circuitry that allows a user to adjust the color intensity of the video signal. FIG. 4 shows an exemplary prior art switch where selector 408 comprises a rocker switch 408b that allows the user to control the switch 400 and a display 408a that displays which target is coupled to the user's workspace 110. Selector 408 is connected to switch 400 via cable 416 which comprises KVM cables and a data cable for control signals. Selector 408 is also connected directly to all of the user's KVM devices. Selector 408 includes circuitry for adjusting the intensity level of the received video signals. Intensity levels are adjusted with color dials 408c. Such a configuration is disadvantageous because it limits where selector 408 can be placed and requires selector 408 to have ports and circuitry for respective KVM cables which adds costs to the selector 408. FIG. 5 shows a KVM switch 500 that supports two local users, with one user using workspace 110a and the other user using workspace 110b. Switch 500 allows each user to switch which target is being controlled by using hotkey commands and an accompanying graphical user interface as described in accordance with FIG. 1. In addition, switch 500 provides the additional functionality of allowing a user to view which target the other user is connected to and to disconnect the other user from the target using the graphical user interface. Examples of such KVM switches are Avocent KVM switches sold under the trademark AUTOVIEW. AutoView KVM switches are described in submitted document entitled “AutoView 2020/2030 Installer/User Guide” published by Avocent Corporation in 2005, Document No. 590-495-501A, which is incorporated by reference in its entirety. FIG. 6 shows a KVM switch 600 that is similar to KVM switch 500 in that switch 600 supports multiple users. KVM switch 600 differs from switch 500 in that users are connected to switch 600 through user stations 620a and 620b. Through the user stations a user can either connect or disconnect another user from a target by entering a command specifying the user and the target. An example of such KVM switches are Avocent KVM switches sold under the AMX trademark. AMX KVM switches are described in submitted document entitled “AMX Switch Series Installer/User Guide” published by Avocent Corporation in 2006, Document No. 590-222-501K, which is incorporated by reference in its entirety. FIG. 7 shows an example of a KVM switch 700 that has a network interface 700a which allows switch 700 to be accessed by a remote terminal 730 via network 720. Remote terminal 730 uses a graphical user interface to change which target the user workspace 110 is connected to. Since multiple switches 700 can be connected to network 720, when remote terminal 730 accesses KVM switch 700 via network 720 control information sent from remote terminal 730 must be logically addressed to KVM switch 700. To send and receive logically addressed information the system requires the appropriate hardware/software which adds cost to the system. In addition to the KVM switches described above some KVM switches that allow remote access include a setup port for allowing a local terminal to configure a KVM switch. Known setup ports provide only limited control of the KVM switch such as initial network settings and the like and do not control which targets are coupled to a user device. Examples of such KVM switches are Avocent KVM switches sold under the DSR trademark. The setup port of a DSR switch is described in chapter three of submitted document entitled “DSR Switch Installer/User Guide” published by Avocent Corporation in 2005, Document No. 590-419-501B, which is incorporated by reference in its entirety. Although the KVM switches described above offer many alternative ways for a user to be connected to a target device without using an onboard control mechanism, none provide the user with a low cost mechanism to switch between targets or otherwise control a KVM switch when the switch is not within reach that is simple to use, not prone to inadvertent switching, easily placed within a user's workspace, and provides confirmation as to which target is being controlled. Thus, it is desirable to provide a user with a low cost mechanism that allows switching between targets or provides other control functions to a desktop KVM switch when the switch is not within reach that is: simple to use, not prone to inadvertent switching, easily placed within a user's workspace, and provides confirmation as to which target is being controlled. BRIEF DESCRIPTION OF THE PRESENTLY PREFERRED EXEMPLARY EMBODIMENTS FIG. 8 shows KVM switch 800 that is similar to KVM switch 100 where switch 800 receives video signals from respective targets (not shown) at video ports 104 and accesses keyboard and mouse ports from respective targets at ports 106 and allows a user to control a designated target by coupling the communication path from a selected target interfaced at 104 and 106 to user KVM port 102. It should be noted that although user's video, keyboard, and mouse ports are shown as a VGA port, a USB port, and a USB port respectively, this is not intended to be limiting and similar types of ports could be used as would be appreciated by one of ordinary skill in the art, e.g. keyboard ports and mouse port could be PS/2 ports. It should also be noted that keyboard and mouse can be bundled so that switch 800 has a single port for a keyboard and mouse of a respective target (e.g. combining keyboard and mouse into a single USB connection) and that video, keyboard, and mouse can be bundled so that switch 800 has a single port for each target device. KVM switch 800 differs from KVM switch 100 in that KVM switch 800 does not include an onboard control interface. Instead KVM switch 800 includes an external control interface 840 that allows external controller 850 to communicate with KVM switch 800 via communication medium 860. KVM communication interface 840 is typically a USB port and the communication medium 860 is typically a USB cable, but alternative types could be used. For example, interface 840 could be any type of interface that allows external controller 850 to communicate with switch 800 including but not limited to: a CAT5 connection, twisted pair connection, a single wire connection, a coax cable connection, an optical connection, an IR connection or any other type of wireless connection. Moreover, communication medium 860 could be any medium compatible with the chosen interface i.e. the appropriate cabling or, in the event of wireless communication, simply air. It should be noted that communication medium 860 may also provide power to external controller 850 from KVM switch 800, when the type of communication medium 860 (e.g. USB cable) is capable of providing power. In the event that communication medium 860 cannot provide power to external controller 850 from KVM switch 800, external controller 850 must receive its power from another source. In this instance, external controller 850 would typically receive power from batteries within the external controller 850, from another device, or from an alternative power supply such as a transformer. As shown in FIG. 8, external controller 850 includes exemplary control mechanism 850b (similar to control mechanism 108b) and a select button that allows the user to cycle through the targets. Likewise, exemplary display 850a (similar to display 108a) includes an illuminated LED corresponding to a target indicating that the target is coupled to the user. It should be noted that although control mechanism 850b of external controller 850 is shown with a single button that cycles through targets, this is for exemplary purposes only. Control mechanism 850b of external controller 850 can include alternative configurations that provide the same or additional functionality. For example, external controller 850 could have rocker or accordion switches, each corresponding to a KVM port where, when a switch is depressed the corresponding KVM port is coupled to the port 102. As an alternative, the external controller 850 could have buttons in addition to the select button that provide control functions to the switch 800. Any combination of known KVM switch commands (e.g. reset, autoscan, etc.) can be incorporated into external controller 850. It should also be noted that exemplary display 850a is shown as a set of LEDs for exemplary purposes only. Display 850a is not limited to a set of LEDs and could be any appropriate display mechanism. Display 850a could be a seven segment LED display where a number representing which target is coupled to the user is displayed or a small LCD display that graphically represents which target is coupled to the user. Further, display 850a could be configured to display more information than simply which target is coupled to the user e.g. whether switch 800 is scanning or the status of other switch functions. Display 850a could also incorporate control mechanism 850b e.g. providing both functions through a touch screen. External controller 850 also includes communication interface 850c that is similar to communication interface 840 in that it interfaces external controller 850 to communication medium 860. Communication interface 850c can be any type of communication interface compatible with communication medium 860. It should be noted that communication interface 840 and communication interface 850c need not be the same type. For example, a wireless transmitter can be built into external controller 850 and communication interface 840 can be a USB port that interfaces communications medium 860 with a USB receiver. This is similar to a wireless mouse communicating with a PC via the PC's USB port where the wireless mouse transmits signals to a receiver docked to the PC's USB port. It should be noted that external controller 850 is typically designed to communicate only with KVM switch 800 and as such, information sent from the external controller 850 to switch 800 need not be logically addressed. FIG. 9 shows an alternative exemplary embodiment of an external controller 850. In FIG. 9, display 850a is a display that uses a GUI to indicate which targets are connected to the user station. In FIG. 9, control mechanism 850b is shown as a navigation pad that allows a user to select commands displayed on display 850a. It should be noted that external controllers used to control switch 800 can incorporate any combination of the displays and access mechanisms described in accordance with FIGS. 8 and 9. FIG. 10 shows an exemplary block diagram of external controller 850. In addition to elements of external controller 850 previously described, FIG. 10 shows microprocessor 850d and display controller 850d. Microprocessor 850d processes commands received from user, communicates with interface, and sends display information to display controller 850e. Display controller 850e allows display 850a to be updated as would be appreciated be one of ordinary skill in the art. External controller 850 is typically designed to be smaller than KVM switch 800 while still being large enough so that a user can manipulate it. External controller 850 is typically small enough to comfortably fit within one's pocket. External controller 850 can also include an adhesive (not shown) on a side which is not the side with display 850a so that external controller 750 can be adhered to an object within the user's workspace (e.g. a display or a keyboard while still allowing the user to view the display). The adhesive can be designed to provide permanent attachment (e.g. glue) or temporary/removable attachment (e.g. a Velcro strip, a magnet, a suction cup, a clip, or any other suitable mechanical or chemical means). When external controller 850 is designed to adhere to an object on a user's desktop (e.g. a user's display), external controller 850 should be small enough as to be discreet. Further, external controller 850 can be built into objects that are placed within a user's workspace. FIG. 11 shows an external controller 850 built into a mouse pad. FIG. 12 shows an alternative embodiment of a KVM switch that, like KVM switch 100, includes: (1) video ports 104 that receive target video signals, (2) ports 106 that receive keyboard and mouse signals, (3) a user KVM port 102, and (4) an onboard control interface 108. KVM switch 900 also incorporates the external control functionality of KVM switch 800. That is, KVM switch 900 comprises a communication interface 840, communication medium 860, and an external controller 850. Thus, KVM switch 900 provides all the functionality of KVM switch 100 but can also be controlled remotely, like KVM switch 800, if a user desires. It should be noted that although onboard control interface 108 and external controller 850 are both shown as having a set of LEDs and a select button, this is for exemplary purposes only and not intended to be limiting. Display 108a and/or control mechanism 108b of onboard control interface 108 do not need to be the same as display 850a and control mechanism 850b of external controller 850. Display 108a, control mechanism 108b, display 850a, and control mechanism 850b can be any combination of types of displays and control mechanisms described above. For example, display 108a may be a seven segment display and display 850a may be a set of LEDs where both control mechanisms include a select button. It should be noted that KVM switch 900, like any of the KVM switch embodiments described above, does not need to include hotkey control, but can optionally include hotkey control. FIG. 13a shows a KVM switch system with an alternative external controller 950. External controller 950 is designed to interface a user's keyboard or be built into a user's keyboard. External controller 950 includes display 850a, selection mechanism 850b, and interface 850c which are similar to respective parts described in accordance with external controller 850. External controller 950 also includes interface 850f which allows controller 950 to interface a user's keyboard. By being directly coupled to or built into a user's keyboard, external controller 950 is within a user's reach but does not have the drawbacks of hotkey commands and provides the additional benefit of indicating which target a user is connected to. Further, by only interfacing a user's keyboard and not a user's monitor or mouse, controller 950 can be more easily placed at various locations on a user's desktop. It should also be noted that external controller 950 can be interfaced or be built into a user's mouse as an alternative to being interfaced or built into the user's keyboard. FIG. 13c shows a block diagram of external controller 950. FIG. 13b shows a KVM switch system that is similar to the KVM switch system described in accordance with FIG. 13a where external controller 950 interfaces user's keyboard and mouse. The KVM switch system shown in FIG. 13b is particularly advantageous when keyboard and mouse come from a common connection as is the case with USB type devices. It should be noted that although the exemplary embodiments have been described in accordance with a 4-to-1 desktop KVM switch (4 targets, 1 user) such a description is for exemplary purposes only. It should be appreciated that a desktop KVM switch with any number of targets and number of users could be used. Where the desktop KVM switch incorporates multiple users, each user could be provided an external controller. FIG. 14 shows an exemplary embodiment where multiple users are connected to a KVM switch and each user has an external controller within their respective workspace. The KVM devices of each workspace 110a, 110b, and 110c are connected to KVM switch 1000 through standard connections as described in accordance with FIG. 1. Each workspace is shown including respective external controllers 850, 850, and 950. It should be noted that any combination of types of external controllers could be used with switch 1000. When external controllers are used in a multi-user KVM switch the external controllers can be configured to allow users to control only which target their respective KVM devices are connected to or the controllers can be configured to control which target any of the other users are connected to. It is also recognized that it would be useful to use external controllers 850 and 950 with prior art KVM switches. FIGS. 15-18 describe exemplary embodiments where an external controller 850 is used with a prior art KVM switch. FIG. 15 shows where external controller 850 can control prior art KVM switch 100 by passing supported switch commands through micro-receiver 1050. FIG. 16 shows a more detailed view of an exemplary micro-receiver 1050. Micro-receiver 1050 interfaces a user peripheral (e.g. a user keyboard) through a peripheral interface 1050b (e.g. USB or PS/2 port). Micro-receiver 1050 also interfaces a KVM switch at KVM interface 1050a (e.g. USB or PS/2 connector). Interfaces 1050a and 1050b transparently pass communications between a user peripheral and a KVM passed through the micro receiver 1050. That is, the user peripheral and the KVM switch operate as if they were directly connected. Micro-receiver 1050 also communicates with external controller 850 through communication medium 860, described above. The KVM switch is able to be controlled by external controller 850 by the micro-receiver 1050 receiving commands from external controller 850 and passing those commands to the KVM switch in an appropriate format. FIG. 17 shows an exemplary block diagram of an exemplary micro-receiver 1050 that illustrates how commands from an external controller 850 can be received by a KVM switch. Commands are received from external controller 850 at the communication interface 1050c. Communication interface 1050c is similar to control interface 840 described above and for the sake of brevity will not be described herein. The received commands are passed from communication interface 1050c to translator 1050d. Translator 1050d translates the commands into an appropriate form so they can be processed by the KVM switch. An example of the translation process is as follows: assuming a prior art KVM switch supports hotkey commands, a command received at the communication interface 1050c can be translated by translator 1050d into the hotkey command corresponding to the received command and passed to the KVM switch at KVM switch interface 1050a. In the example described above, the micro-receiver 1050 spoofs the KVM switch that all received commands (including hotkey commands) are generated from a keyboard that is directly connected to the KVM switch. For an external controller 850 to command a prior art KVM switch, the KVM switch must be capable of accepting such a command through a peripheral port and micro-receiver 1050 must be able to transfer commands from external controller 850 in a compatible format for the specific prior art KVM switch. Thus, reconfiguration of micro-receiver 1050 and/or KVM switch is required. For example, if a KVM switch can execute commands through hotkeys sequences, the micro-receiver 1050 must be programmed to use these sequences, This requires reconfiguration as different KVM switches may have different hotkey sequences for the same function. FIG. 18 shows a diagram illustrating various ways to configure a KVM switch system with an external controller and a micro-receiver. FIG. 18 shows four alternative methods. Methods 1, 2, and 3 show configuration of micro-receiver 1050. Thus, methods 1, 2, and 3 only require configuration of micro-receiver 1050. In method 1, a user is able to configure micro-receiver through a PC. An example of how this can occur is as follows: micro-receiver 1050 is coupled to a PC using KVM interface 1050a (e.g. plugging micro-receiver into USB port of a PC) and the user programs the micro-receiver 1050 using software on the PC. For example, the software can allow the user to specify the model number of a KVM switch and the PC will program the micro-receiver 1050 accordingly. In method 2, the user configures the micro-receiver 1050 using external controller 850. An example of this method is the user manipulating the control interface of the external controller 850 as to indicate the model of the KVM switch. After the model is indicated micro-receiver 1050 is configured in a manner similar to that of method 1. Once micro-receiver 1050 is configured, it may not be necessary to configure the KVM switch, for example, when KVM switch supports all necessary commands through hotkeys sequences or the like. In method 3, the user configures the micro-receiver 1050 using a keyboard connected to the micro-receiver 1050. This can be achieved by using a hotkey sequence to specify a particular KVM switch or by using hotkey sequences to program individual commands of the micro-receiver 1050. Methods 4 and 5 show configuration of a KVM switch. In method 4, a firmware update of the KVM switch allows KVM switch to process commands from micro-receiver 1050. This process is similar to updating keyboard and mouse drivers in a KVM switch so a KVM switch is compatible with a new device. In method 5, micro-receiver 1050 is automatically programmed when it is inserted into the KVM switch. That is, micro-receiver 1050 polls KVM switch for identification information and KVM switch responses to the poll with its identification information. After identification information is indicated micro-receiver 1050 is configured in a manner similar to that of method 1. After the model is indicated micro-receiver 1050 is configured in a manner similar to that of method 1. Once KVM switch is configured, it may not be necessary to configure micro-receiver 1050, for example, when micro-receiver 1050 issues commands to a KVM switch in a generic format. Any of the methods described above can be used in any number of combinations. For example, before method 4 can be implemented it may be required to update the firmware of the KVM switch as described in method 3 (e.g. micro-receiver does not need to be configured or already is configured). FIG. 19 shows an alternative embodiment of a micro-receiver 1060. Micro-receiver 1060 interfaces a user monitor (not shown) and the video port of a prior art KVM switch 100. It should be noted that micro-receiver 1060 can interface a user monitor and KVM switch 100 by being connected at either end of a video cable, either near KVM switch 100 or near the monitor. Micro-receiver 1060 responds to wireless commands received from external control 850 via communications medium 860 (e.g., wirelessly) to temporarily or permanently superimpose via the monitor an indication of the status of the KVM switch (e.g. which target the user is connected to and/or whether the KVM switch is in scanning mode). While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.	G	60G06	161G06F	13	12
11729792	US20080244285A1-20081002	Method to control core duty cycles using low power modes	ACCEPTED	20080917	20081002	[]	G06F126	["G06F126"]	7774626	20070329	20100810	713	300000	65323.0	BROWN	MICHAEL	[{"inventor_name_last": "Fleming", "inventor_name_first": "Bruce L.", "inventor_city": "Beaverton", "inventor_state": "OR", "inventor_country": "US"}]	A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt.	1. A method comprising: A processor starting a duty cycle timer with a specified duty cycle period and a specified power state; If the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer; and If the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer in response to the interrupt other than a timer tick interrupt. 2. The method of claim 1 further comprising The processor executing an instruction to start the duty cycle timer of the processor. 3. The method of claim 1 further comprising The processor starting the duty cycle timer in response to receiving a timer tick interrupt in a low power state. 4. The method of claim 1 further comprising: The processor canceling the duty cycle timer in response to an indication of an idle condition being received by the processor. 5. The method of claim 1 further comprising The processor starting the duty cycle timer in response to receiving a timer tick interrupt in a low power state. 6. The method of claim 1 further comprising The processor starting the duty cycle timer in response to detecting a change of thermal state of the processor to a state outside a specified range of thermal states; and canceling the duty cycle in response to the thermal state of the processor returning to a state within the specified range of thermal states. 7. The method of claim 1 wherein the duty cycle timer is incorporated into the logic circuits of the processor. 8. The method of claim 1 wherein: the processor and the duty cycle timer are hardware components of a processor based platform. 9. A processor comprising: a processor bus; fetch logic to receive an instruction and to receive an operand; decode logic to decode the instruction; and a logic circuit to perform, at least in part in response to the decoding of the instruction, starting a duty cycle timer with a specified duty cycle period and a specified power state; If the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer; and If the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle timer being in response to the interrupt other than a timer tick interrupt. 10. The processor of claim 9 wherein the logic circuit comprises a logic circuit operating at least in part based on microcode instructions. 11. The processor of claim 9 wherein: the logic circuit is further to perform starting the duty cycle timer in response to receiving a timer tick interrupt in a low power state. 12. The processor of claim 9 wherein: the logic circuit is further to perform canceling the duty cycle timer in response to an indication of an idle condition being received by the processor. 13. The processor of claim 9 wherein: the logic circuit is further to perform starting the duty cycle timer in response to receiving a timer tick interrupt in a low power state. 14. The processor of claim 9 wherein: the logic circuit is further to perform starting the duty cycle timer in response to detecting a change of thermal state of the processor to a state outside a specified range of thermal states; and to perform canceling the duty cycle in response to the thermal state of the processor returning to a state within the specified range of thermal states. 15. The processor of claim 9 wherein: The processor is an x86 processor; The specified power state is an ACPI power state. 16. The processor of claim 15 wherein: The instruction is based at least in part on the MWAIT instruction; and The specified power state is the C6 power state. 17. A platform comprising: a processor a memory a bus interconnecting the processor and the memory; the processor further comprising: a processor bus; fetch logic to receive an instruction and to receive an operand; decode logic to decode the instruction; and a logic circuit to perform, at least in part in response to the decoding of the instruction, starting a duty cycle timer with a specified duty cycle period and a specified power state; If the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer; and If the timer has not expired and if an interrupt other than a timer tick interrupt is received, canceling the duty cycle. 18. The platform of claim 17 wherein: the logic circuit is further to perform starting the duty cycle timer in response to receiving a timer tick interrupt in a low power state. 19. The platform of claim 17 wherein: the logic circuit is further to perform canceling the duty cycle timer in response to an indication of an idle condition being received by the processor. 20. The platform of claim 17 wherein: the logic circuit is further to perform starting the duty cycle timer in response to detecting a change of thermal state of the processor or system; and to perform canceling the duty cycle in response to the thermal state of the processor returning to a state within the specified range of thermal states.	<SOH> BACKGROUND <EOH>Low power features of processor based platforms are useful for mobile computing, to increase battery life of devices such as notebook computers, handheld computers, “smart” phones, among many others. Similarly thermal requirements in processor based platforms such as densely packed servers may make it important to control power use in such environments. Power efficiency is important for processor based platforms in general, and therefore features to support lower power use may be incorporated into many different types of platforms. Such features may include, for example, gating or turning off portions of logic, lowering operating frequency, dimming displays, and many others. These features may be incorporated into chipset and processor cores. Current implementations rely upon stringent control over applications and services which are run on a platform such as in current mobile handset designs for low power use. This may not be practical for an open platform which needs to support very long standby times. The Advanced Configuration and Power Interface (ACPI) specification defines an Operating System (OS) directed power management interface which includes system and device power states, as is well known. The specification is available at www. acpi.info on the World Wide Web. In typical processor based platforms, there at least two types of interrupts that may cause a processor to exit an idle or low power state and become active. The first type of interrupt is caused by various types of timers that may be used by an operating system, as is known in the art. Other types of interrupts are event driven and caused by events such as an external input event, failure conditions, among many others. In some processor based platforms the duty cycle of a processor may be varied. For each time slice, the processor may be operated in a fully active mode only for a fraction of the time in the time slice, and be idled for the remainder of the time in the time slice. This fraction is termed a duty cycle.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 depicts a processor based system in one embodiment. FIG. 2 depicts a processor in one embodiment. FIG. 3 depicts the flow of processing in one embodiment. detailed-description description="Detailed Description" end="lead"?	BACKGROUND Low power features of processor based platforms are useful for mobile computing, to increase battery life of devices such as notebook computers, handheld computers, “smart” phones, among many others. Similarly thermal requirements in processor based platforms such as densely packed servers may make it important to control power use in such environments. Power efficiency is important for processor based platforms in general, and therefore features to support lower power use may be incorporated into many different types of platforms. Such features may include, for example, gating or turning off portions of logic, lowering operating frequency, dimming displays, and many others. These features may be incorporated into chipset and processor cores. Current implementations rely upon stringent control over applications and services which are run on a platform such as in current mobile handset designs for low power use. This may not be practical for an open platform which needs to support very long standby times. The Advanced Configuration and Power Interface (ACPI) specification defines an Operating System (OS) directed power management interface which includes system and device power states, as is well known. The specification is available at www. acpi.info on the World Wide Web. In typical processor based platforms, there at least two types of interrupts that may cause a processor to exit an idle or low power state and become active. The first type of interrupt is caused by various types of timers that may be used by an operating system, as is known in the art. Other types of interrupts are event driven and caused by events such as an external input event, failure conditions, among many others. In some processor based platforms the duty cycle of a processor may be varied. For each time slice, the processor may be operated in a fully active mode only for a fraction of the time in the time slice, and be idled for the remainder of the time in the time slice. This fraction is termed a duty cycle. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts a processor based system in one embodiment. FIG. 2 depicts a processor in one embodiment. FIG. 3 depicts the flow of processing in one embodiment. DETAILED DESCRIPTION In some embodiments a processor based platform includes a hardware component which may be referred to as a Duty Cycle Timer (DCT). This component may be incorporated into a chipset as part of the power management functionality of the processor, or directly into the processor itself, or in some other hardware component of the platform. FIG. 1 depicts a processor based system or platform 100 incorporating a duty cycle timer as part of a chipset of the processor. The system 100 consists of a processor 105 with two cores 140. The processor is connected to internal storage such as a disk drive system 115 and a memory 110 by one or more buses in an internal bus system 112. The internal bus system is also interconnected to an external bus or buses 135 that may connect to peripherals such as an external display device 125, external mass storage devices such as a CDROM or DVD-RW device 120 and other peripherals, 130. Many different embodiments of a processor based system like the one depicted in FIG. 1 are possible. In some embodiments there may be more or less than two cores present in processor 105. Specifically, the processor in some embodiments may be a single-core processor. In yet other embodiments, a multi-processor system may be used with a cache system that allows threads executing on each of the processors concurrent shared access to the cache. The specific organization of the memory, storage, and peripherals in some embodiments may differ. In some embodiments, certain peripherals may be omitted, or the system may include other interfaces not shown in the Figure such as network connectors, audio i/o and many others. Many other embodiments may be employed as would be appreciated by the artisan. The platform depicted in FIG. 1 includes a chipset 117 also connected to the bus 135, which may control features or functionality of the platform including power management functionality. In this embodiment the chipset may incorporate a Duty Cycle Timer (DCT). In general the DCT logic is to manage the duty cycle of the processor of the platform in response to power management requirements, interrupts, thermal events, among other parameters. FIG. 2 depicts at a high level some block level features of processor 218 in the embodiment of FIG. 2. In general, a processor such as the one depicted in FIG. 2 at 218 may include a processor bus or buses such as the one indicated at 237 in FIG. 2a. Furthermore, as depicted in FIG. 2, a processor may include registers 250 in one or multiple banks, and each register may have the capacity to store 32, 64, 128 or another number of bits of data as is known. Each register bank may further have several registers, such as e.g. 8, 32, 64 registers. Some registers may be dedicated to control and status use for example to store the CR bits as in an x86 embodiment. In other embodiments, other control registers and flags may be stored in the processor to allow different modes of operation and status checking as is known in the art. In general a processor such as the one depicted in the embodiment of FIG. 2 would include logic or logic circuitry 230 to fetch instructions and data from memory, cache or other storage; logic or logic circuitry to decode instructions and execution units such as 234 to perform the instructions. Many variations on these functional units are possible, e.g. execution in the execution unit may be pipelined; or include speculation, and branch prediction; or have other features as related to a particular processor or application. Other functional logic 265 may be present in the processor such as logic for arithmetic, graphics processing, and many other specific functions of the processor as is known. An on-board cache 260 may be present in some embodiments. This cache may have various sizes such as 128 MB, 1 GB, etc. as is known As previously indicated with reference to FIG. 2, the processor 218 includes a duty cycle timer (DCT) unit or logic circuit 222. As discussed with reference to FIG. 1, the DCT logic is generally to manage the duty cycle of the processor of platform in response to power management requirements, interrupts, thermal events, among other parameters. In each of the above discussed embodiments, the DCT may be used in conjunction with an instruction of the processor, which defines the desired duty cycle of the core for a specific time slice. During normal usage, processor based systems may occasionally enter a grossly idle state. In this embodiment, the entry into the grossly idle state would cause the DCT embodied in either the power management logic of the system or chipset 117 of the embodiment depicted in FIG. 1, or in the processor logic 222 depicted in FIG. 2, to cause the system to use a low power core state. In a system that follows the ACPI protocol this state may be the C6 state as defined in the ACPI specification. In general, interrupts could bring the processor out of this low power mode. A common source of such interrupts would be a timer tick in such a grossly idle system. The new instruction would be used upon the detection of a timer tick received while the core was in the lowest state retentive power mode. The instruction would indicate the desired duty cycle of the core, and the core power mode to be entered once the duty cycle was consumed. The instruction may then cause the DCT to be armed and start ticking. If the active threads are executing when the duty cycle expires, the power management facilities of the system would halt the core and force the core and system into the specified state, such as a C6 state in an ACPI compliant system or its equivalent in others. Upon the next timer tick interrupt, which would bring the system out of the forced low power state, it would appear to the OS and any executing thread that it had consumed the entire quantum and would likely be pushed to the end of the reschedule queue. If the operating system indicates an idle condition prior to the duty cycle being consumed, the power management code in the OS could request moving to a new low power mode. The action of requesting to move to the new low power mode would cancel the DCT. In some embodiments, DCT logic may enable a platform to quickly adapt to a non-idle, or attended workload. This type of workload in general may require an external event to cause the transition. This external event may be in the form of user input such as a keyboard event, mouse event, touch screen input, speech reception, among many others, a power management event such as a change to a less efficient and higher performance mode, for one example, or a network driven event such as a voice call, a push upgrade, or push email. In this case, any interrupt source which is not a timer interrupt may then cancel any previously instantiated duty cycle timer. Once the DCT is cancelled, the processor may now allow time sensitive threads or processes such as driver and interrupt code to execute to completion. Unlike driver and external interrupt handlers, timer tick interrupt or period timer based threads typically do not have rigid time deadlines to complete but rather a fixed set of functions which are desired to be completed on a synchronous fashion and so may be delayed or preempted to the following scheduling quantum of the OS. The functionality of DCT logic as embodied either in platform hardware or in processor hardware is depicted in FIG. 3. In the figure, processing within the DCT logic circuit is depicted at a high level. The relevant processing begins in an idle state of a processor based system 310. Power management logic may then place the system in a low power consuming state such as for example C6 in an ACPI compliant platform, 320. An interrupt may then arrive, 330. If the interrupt is a standard period or timer interrupt, 350, the power management instruction is issued to arm the DCT and to specify the low power core state for the core to enter upon DCT expiry, at 350-340. Otherwise, the interrupt is processed without a DCT arming, 350-360. If the interrupt was a timer interrupt, the interrupt is still processed along path 340-360, but is subject to interruption and idling by the DCT timer expiration event, 380. The thread handling the interrupt then continues execution in either scenario, 370. When the DCT expires, 380, it forces the system into the specified low power state and processing returns to the state at 320. In some embodiments, the DCT may also be used for active thermal management on a platform. Thermal sensors may in these embodiments be used as input into a policy that may continually change the duty cycle of the core. This may in some embodiments provide quicker dissipation of heat due to the ability to substantially affect the average power consumption (and associated thermal generation) of the platform. The use of the DCT in embodiments provides a low overhead capability to maintain high granularity control over the duty cycle and subsequent average standby power of the platform. The DCT allows the platform to adapt to the idle characteristics of the platform and without significantly affecting standby and battery life requirements. The mechanism also provides for time critical execution as well as deferred execution of threads to completion once the platform is in an active state. It should be noted than many variations on the above described embodiments are possible. DCT logic may be incorporated into different components in different platforms, e.g. in the chipset, in the processor, in BIOS firmware, among others. The actual power states available to a platform for the idle state specified after timer expiration may depend on the platform. States other than ACPI states may be used in non-ACPI compliant systems. Many variations of the logical organization of the system of FIG. 1 and the processor of FIG. 2 are possible. The flowchart of FIG. 3 is at a high level and may be implemented in a very large variety of different ways in logic circuits, microcode, or in programs embedded in firmware and may be downloadable from a medium such as a disk or other storage. In the preceding description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the described embodiments, however, one skilled in the art will appreciate that many other embodiments may be practiced without these specific details. Some portions of the detailed description above are presented in terms of algorithms and symbolic representations of operations on data bits within a processor-based system. These algorithmic descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others in the art. The operations are those requiring physical manipulations of physical quantities. These quantities may take the form of electrical, magnetic, optical or other physical signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the description, terms such as “executing” or “processing” or “computing” or “calculating” or “determining” or the like, may refer to the action and processes of a processor-based system, or similar electronic computing device, that manipulates and transforms data represented as physical quantities within the processor-based system's storage into other data similarly represented or other such information storage, transmission or display devices. In the description of the embodiments, reference may be made to accompanying drawings. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made. Moreover, it is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described in one embodiment may be included within other embodiments. Further, a design of an embodiment that is implemented in a processor may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, data representing a hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. An optical or electrical wave modulated or otherwise generated to transmit such information, a memory, or a magnetic or optical storage such as a disc may be the machine readable medium. Any of these mediums may “carry” or “indicate” the design or software information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may make copies of an article (a carrier wave) that constitute or represent an embodiment. Embodiments may be provided as a program product that may include a machine-readable medium having stored thereon data which when accessed by a machine may cause the machine to perform a process according to the claimed subject matter. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, DVD-ROM disks, DVD-RAM disks, DVD-RW disks, DVD+RW disks, CD-R disks, CD-RW disks, CD-ROM disks, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. Moreover, embodiments may also be downloaded as a program product, wherein the program may be transferred from a remote data source to a requesting device by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection). Many of the methods are described in their most basic form but steps can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the claimed subject matter. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The particular embodiments are not provided to limit the claimed subject matter but to illustrate it. The scope of the claimed subject matter is not to be determined by the specific examples provided above but only by the claims below.	G	60G06	161G06F	1	26
11840450	US20090049129A1-20090219	REAL TIME COLLABORATION FILE FORMAT FOR UNIFIED COMMUNICATION	ACCEPTED	20090205	20090219	[]	G06F1516	["G06F1516"]	8583733	20070817	20131112	709	204000	71704.0	GOLDBERG	ANDREW	[{"inventor_name_last": "Faisal", "inventor_name_first": "Adil", "inventor_city": "Redmond", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Sethi", "inventor_name_first": "Aaron", "inventor_city": "Bellevue", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Wolfe", "inventor_name_first": "Ken", "inventor_city": "Redmond", "inventor_state": "WA", "inventor_country": "US"}]	The claimed subject matter provides a system and/or a method that facilitates enhancing real time unified communications. An interface can receive a portion of data associated with at least one of a client application or an environment that hosts a client application. A real time collaboration (RTC) component can employ an RTC file package to seamlessly initiate a real time collaboration session with the client application, wherein the RTC file package can include a portion of data that relates to at least one of the client application, the host environment, or a modality of the client application.	1. A system that facilitates enhancing real time unified communications, comprising: an interface that receives a portion of data associated with at least one of a client application or an environment that hosts a client application; and a real time collaboration (RTC) component that employs an extensible RTC file package to seamlessly initiate a real time collaboration session with the client application, the RTC file package incorporates the portion of data that relates to at least one of the client application, the host environment, or a modality of the client application. 2. The system of claim 1, the client application invokes the real time collaboration session with at least one of the following modalities: an audio communication, a video communication, a voice over Internet protocol (VoIP) communication, an instant messaging communication, a desktop sharing communication, a modality of collaboration, or a file sharing communication. 3. The system of claim 1, further comprising two or more clients participating in the real time collaboration session independent of each version of client application. 4. The system of claim 3, the RTC file package is specifically tailored for each client and client environment participating in the real time collaboration session. 5. The system of claim 1, further comprising an evaluation component that collects a portion of data to build the RTC file package, wherein the portion of data is associated with at least one of a client, the client application, a client application versioning, a client application availability, the host environment, and/or an input parameter associated with the client application. 6. The system of claim 5, the portion of data is at least one of an existing client application associated with a client, an environment associated with a client, an operating system, a computer, an input device, a display device, a graphic card, a portion of memory, a processor, a client preference, an available client application listing, a security preference, a digital signature detail, a real time communication setting, a real time collaboration preference, an optimal setting, a versioning associated with a client application, a hardware/software configuration, or an input parameter associated with a particular client application. 7. The system of claim 5, further comprising a build component that generates the RTC file package for a client based at least in part upon the portion of data collected by the evaluation component. 8. The system of claim 1, the RTC component implements the RTC file package to initiate the client application utilizing multipurpose Internet mail Extension (MIME) association, the RTC file package is a browser, communication modality, platform and vendor agnostic file format to implement initiation of real time communication. 9. The system of claim 1, further comprising a signature component that can incorporate a security mechanism into the RTC file package. 10. The system of claim 9, the security mechanism is a signature that authenticates an origin of the RTC file package, the signature ensures the RTC file package correlates to a client. 11. The system of claim 1, further comprising a server that utilizes the RTC file package to implement the real time collaboration session. 12. The system of claim 1, further comprising a browser that utilizes the RTC file package to implement the real time collaboration session. 13. The system of claim 1, further comprising a router that utilizes the RTC file package to route to an appropriate client application for the intended real time collaboration session. 14. The system of claim 1, the RTC file package defines at least one of a password, a ticket, a user name, an AiccSid, a lobby location, a role, a meeting start time, a meeting end time, a meeting identification, a meeting password, a meeting subject, a recording agreement, a uniform resource indicator (URI), a portion of company data, a user name, a user email, or a token to identify at least one of the intended server entity or the intended user entity (client) for the collaboration session. 15. The system of claim 1, the RTC file package includes a version, the version is at least one of an XML version, an RTC version, a server version, a server authentication ticket, or a modality version. 16. A computer-implemented method that facilitates employing a real time data communication, comprising: receiving a portion of data related to at least one of a client, a client application, or a client environment; creating an RTC file package based at least in part upon a portion of received data; and employing a real time collaboration with the RTC file package, the RTC file package identifies the client application for real time communication and a modality utilized for real time communication. 17. The method of claim 16, the modality for the real time communication is at least one of an audio communication, a video communication, a voice over Internet protocol (VoIP) communication, an instant messaging communication, a desktop sharing communication, or a file sharing communication with a disparate modality of collaboration. 18. The method of claim 16, further comprising: evaluating at least one of a client, a client application or a client environment; building the RTC file package specifically for the client based upon the evaluation; enabling seamless real time communication between two or more clients utilizing the RTC file package; and utilizing an extensible, XML based format for the RTC file package that accommodates support for a future modality of collaboration. 19. The method of claim 16, further comprising enabling at least one of a server, a router or a browser to utilize the RTC file package to employ the real time communication. 20. A computer-implemented system that facilitates seamlessly initiating a real time data communication between two or more clients, comprising: means for receiving a portion of data associated with at least one of a client application or an environment that hosts a client application; means for incorporating the portion of data into an RTC file package; and means for employing the RTC file package to seamlessly initiate a real time collaboration session with the client application.	<SOH> BACKGROUND <EOH>As computing and network technologies have evolved and have become more robust, secure and reliable, more consumers, wholesalers, retailers, entrepreneurs, educational institutions, and the like have and are shifting business paradigms and are employing the Internet to perform business rather than utilizing traditional means. For example, today consumers can access their bank accounts on-line (e.g., via the Internet) and can perform an ever growing number of banking transactions such as balance inquiries, fund transfers, bill payments, and the like. With the tightening of browser and operating system security, it has become increasingly more difficult to detect and launch client applications from browsers with minimal user intervention. To exacerbate matters users can encounter significantly disparate experiences depending on operating system and/or browser security settings. Conventionally, the detection and launch of client applications has involved a combination of nonstandard approaches, such as browser plug-ins, ActiveX, signed Java Applets, etc. to obtain users consent to run client applications on their machines. While such nonstandard approaches may have achieved their ends, such approaches elicited a multitude of additional security dialogs generated by the operating system and/or browser making a user's experience extremely unpleasant, tedious, and daunting. Additionally, conventional means of detecting and launching client applications can significantly compromise computer, operating system, and/or browsers security (e.g., installing ActiveX control, even from trust sources, can open up possibilities for malicious sites to exploit any security holes that might exist in the ActiveX control).	<SOH> SUMMARY <EOH>The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the claimed subject matter. It is intended to neither identify key or critical elements of the claimed subject matter nor delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the claimed subject matter in a simplified form as a prelude to the more detailed description that is presented later. The subject innovation relates to systems and/or methods that facilitate employing a real time collaboration session utilizing an RTC file package. A real time collaboration (RTC) component can receive and/or collect a portion of data related to a client application for real time communication and/or a host environment for the client application, wherein the portion of data can be incorporated into an RTC file package to seamlessly enable real time communications between two or more clients or a client and a server. The RTC file package can include data that defines which client application to utilize for real time communication, a modality for the real time communication, and/or at least one input parameter utilized by the client application for real time communication. With the implementation of the RTC file package, the RTC component can initiate a real time collaborative session between two or more clients (or a client and a server) independent of versioning conflicts, host environment disparities, and/or input parameter requirements. Thus, the RTC file package can include streamlined data necessary for a real time collaboration to be executed. The RTC component can utilize a signature component that can incorporate a signature and/or security mechanism into the RTC file package. Such signature and/or security mechanism can be utilized to authenticate and/or verify an origin for the RTC file package. Thus, an RTC file package associated with a user and/or a session can be validated prior to utilizing the RTC file package to initiate the real time collaboration. Moreover, the RTC file package can be an agnostic flexible file format that can invoke a family of applications utilized for real time communications. In other aspects of the claimed subject matter, methods are provided that facilitate creating an RTC file package associated with at least one client application and respective environment. The following description and the annexed drawings set forth in detail certain illustrative aspects of the claimed subject matter. These aspects are indicative, however, of but a few of the various ways in which the principles of the innovation may be employed and the claimed subject matter is intended to include all such aspects and their equivalents. Other advantages and novel features of the claimed subject matter will become apparent from the following detailed description of the innovation when considered in conjunction with the drawings.	CROSS REFERENCE TO RELATED APPLICATION(S) This application relates to U.S. Application Ser. No. 11/081806, entitled, “Method and System for Installing Applications via a Display Page,” filed Mar. 15, 2005. BACKGROUND As computing and network technologies have evolved and have become more robust, secure and reliable, more consumers, wholesalers, retailers, entrepreneurs, educational institutions, and the like have and are shifting business paradigms and are employing the Internet to perform business rather than utilizing traditional means. For example, today consumers can access their bank accounts on-line (e.g., via the Internet) and can perform an ever growing number of banking transactions such as balance inquiries, fund transfers, bill payments, and the like. With the tightening of browser and operating system security, it has become increasingly more difficult to detect and launch client applications from browsers with minimal user intervention. To exacerbate matters users can encounter significantly disparate experiences depending on operating system and/or browser security settings. Conventionally, the detection and launch of client applications has involved a combination of nonstandard approaches, such as browser plug-ins, ActiveX, signed Java Applets, etc. to obtain users consent to run client applications on their machines. While such nonstandard approaches may have achieved their ends, such approaches elicited a multitude of additional security dialogs generated by the operating system and/or browser making a user's experience extremely unpleasant, tedious, and daunting. Additionally, conventional means of detecting and launching client applications can significantly compromise computer, operating system, and/or browsers security (e.g., installing ActiveX control, even from trust sources, can open up possibilities for malicious sites to exploit any security holes that might exist in the ActiveX control). SUMMARY The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the claimed subject matter. It is intended to neither identify key or critical elements of the claimed subject matter nor delineate the scope of the subject innovation. Its sole purpose is to present some concepts of the claimed subject matter in a simplified form as a prelude to the more detailed description that is presented later. The subject innovation relates to systems and/or methods that facilitate employing a real time collaboration session utilizing an RTC file package. A real time collaboration (RTC) component can receive and/or collect a portion of data related to a client application for real time communication and/or a host environment for the client application, wherein the portion of data can be incorporated into an RTC file package to seamlessly enable real time communications between two or more clients or a client and a server. The RTC file package can include data that defines which client application to utilize for real time communication, a modality for the real time communication, and/or at least one input parameter utilized by the client application for real time communication. With the implementation of the RTC file package, the RTC component can initiate a real time collaborative session between two or more clients (or a client and a server) independent of versioning conflicts, host environment disparities, and/or input parameter requirements. Thus, the RTC file package can include streamlined data necessary for a real time collaboration to be executed. The RTC component can utilize a signature component that can incorporate a signature and/or security mechanism into the RTC file package. Such signature and/or security mechanism can be utilized to authenticate and/or verify an origin for the RTC file package. Thus, an RTC file package associated with a user and/or a session can be validated prior to utilizing the RTC file package to initiate the real time collaboration. Moreover, the RTC file package can be an agnostic flexible file format that can invoke a family of applications utilized for real time communications. In other aspects of the claimed subject matter, methods are provided that facilitate creating an RTC file package associated with at least one client application and respective environment. The following description and the annexed drawings set forth in detail certain illustrative aspects of the claimed subject matter. These aspects are indicative, however, of but a few of the various ways in which the principles of the innovation may be employed and the claimed subject matter is intended to include all such aspects and their equivalents. Other advantages and novel features of the claimed subject matter will become apparent from the following detailed description of the innovation when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of an exemplary system that facilitates employing a real time collaboration session utilizing an RTC file package. FIG. 2 illustrates a block diagram of an exemplary system that facilitates creating an RTC file package associated with at least one client application and respective environment. FIG. 3 illustrates a block diagram of an exemplary system that facilitates employing an RTC file package to seamlessly communicate with a server for real time collaboration session. FIG. 4 illustrates a block diagram of an exemplary system that facilitates implementing an RTC file package to seamlessly communicate with a server for real time collaboration session via a browser. FIG. 5 illustrates a block diagram of exemplary system that facilitates providing real time communications between two or more users independent of varying client application versions. FIG. 6 illustrates a block diagram of an exemplary system that facilitates employing a real time collaboration session utilizing an RTC file package. FIG. 7 illustrates an exemplary methodology for creating an RTC file package associated with at least one client application and respective environment. FIG. 8 illustrates an exemplary methodology that facilitates providing real time communications between two or more users independent of varying client application versions. FIG. 9 illustrates an exemplary networking environment, wherein the novel aspects of the claimed subject matter can be employed. FIG. 10 illustrates an exemplary operating environment that can be employed in accordance with the claimed subject matter. DETAILED DESCRIPTION As utilized herein, terms “component,” “package,” “interface,” “server,” “data store,” “browser,” and the like are intended to refer to a computer-related entity, either hardware, software (e.g., in execution), and/or firmware. For example, a component can be a process running on a processor, a processor, an object, an executable, a program, a function, a library, a subroutine, and/or a computer or a combination of software and hardware. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and a component can be localized on one computer and/or distributed between two or more computers. Now turning to the figures, FIG. 1 illustrates a system 100 that facilitates employing a real time collaboration session utilizing an RTC file package. The system 100 can utilize an agnostic file format and/or file package, such as an RTC file package 104, in order to initiate and employ a real time collaboration session between at least two or more clients independent of versions for client application(s). The system 100 can include a real time collaboration (RTC) component 102 that can receive a portion of data via an interface component 106 (discussed below) in order to create the RTC file package 104. In particular, the portion of data received by the RTC component 102 can relate to a client application, an environment that hosts the client application, and/or any other suitable data related to a client application. Such portion of data received can be incorporated into the RTC file package 104, wherein the RTC file package 104 can be utilized to seamlessly enable a real time collaboration session. In general, the RTC component 102 can create the RTC file package 104 to facilitate implementing a real time collaboration session with a client application between two or more clients independent of versioning issues between such client applications. Thus, the RTC component 102 can employ real time collaborations with disparate versions of client applications in a seamless manner by utilizing the RTC file package 104. For example, various client applications with differing versions can be utilized for real time collaboration sessions. Thus, difficulties can arise with implementing real time collaboration between a first client having a first version of a client application and a second client with a second version of the similar client application. For instance, a video conferencing application can include numerous versions and/or firmware upgrades with respective compatibility issues. Furthermore, each client can include specific environments and/or operating systems. Generally, the RTC component 102 can employ real time collaboration sessions across varying/disparate host environments (e.g., machines, computers, operating systems, hardware, etc.) and/or client application versions. Thus, by utilizing the RTC file package 104 seamless real time collaboration sessions between various versions and/or environments can be allowed. The RTC component 102 can be utilized with a plurality of client applications, wherein the client applications can be any suitable application or software related to real time communications for collaboration between two or more clients. As discussed, the client applications can include numerous versions and can be hosted by a plurality of host environments (e.g., machines, computers, local locations, remote locations, operating environments, operating systems, etc.). Furthermore, the client application(s) can receive various types of input parameters, wherein such input parameters can be further included in the RTC file package 104. It is to be appreciated that the client application can be any suitable client application that can employ real time communications and/or collaborations via the Internet between two or more clients. For example, the client application can provide real time collaboration sessions for various modalities such as, but not limited to, audio communications, video communications, voice over Internet protocol (VoIP) communications, instant messaging communications, desktop sharing communications, file sharing communications, etc. In one example, the system 100 can utilize the RTC file package 104 to invoke any suitable client application through multipurpose Internet mail Extension (MIME) association and remain true to a vision of unified communication (e.g., by employing the RTC file package 104 as an agnostic file format to implement for real time communication). The RTC component 102 can utilize the RTC file package 104 to invoke a corresponding client application with a correct behavior/modality based on the specifics of thereof. Moreover, the RTC file package 104 can include any suitable input parameters associated with the client application. For example, the RTC file package 104 can specify the modality of the communication based on defining the client application for real time collaboration, wherein such modality can be at least one of launch chat application for chat, launch video conferring application for video meeting, launch application sharing software for application sharing, etc. In addition, the system 100 can include any suitable and/or necessary interface component 106 (herein referred to as “interface 106”), which provides various adapters, connectors, channels, communication paths, etc. to integrate the RTC component 102 into virtually any operating and/or database system(s) and/or with one another. In addition, the interface 106 can provide various adapters, connectors, channels, communication paths, etc., that provide for interaction with the RTC component 102, RTC file package 104 and any other device and/or component associated with the system 100. FIG. 2 illustrates a system 200 that facilitates creating an RTC file package associated with at least one client application and respective environment. The system 200 can include the RTC component 102 that can employ the RTC file package 104 that specifies definitions and/or signatures related to client applications and/or environments to facilitate seamless real time collaborating. The RTC file package 104 can define at least one of a client application, a client application version, an environment related to a client application, a modality associated with a client application, at least one input parameter related to the client application, and/or any other suitable data that can be utilized to implement the client application. In general, the RTC file package 104 can be an application agnostic flexible portion of collected data that can invoke a family of real time collaboration applications (e.g., client applications). The RTC file package 104 can further facilitate routing of inputs. In particular, the RTC component 102 can utilize MIME association with the RTC file package 104 to enable application agnostic routing. The RTC file package 104 can further include data to identify a client application to launch and to perform an intended purpose (e.g., initiate a chat, utilize a video conference, etc.). The RTC component 102 can utilize an evaluation component 202 that can collect client specific data to create the RTC file package 104. For example, the evaluation component 202 can evaluate existing client applications associated with a client, an environment associated with a client (e.g., an operating system, a computer, input devices, display devices, graphic cards, memory, processor, etc.), a client preference (e.g., available client application listing, security preference, digital signature details, communication settings, collaboration preferences, optimal and/or default settings, etc.), a versioning associated with a client application, a hardware/software configuration, input parameters associated with a particular client application, and/or any other data related to the system 200. For instance, the evaluation component 202 can identify and/or collect data to enable the RTC file package 104 to a) invoke a particular application from a family of client applications related to real time collaboration and/or b) automatic routing of the data associated with the client application. The gathered information from the evaluation component 202 can be utilized by a build component 204 to generate the RTC file package 104 accordingly. In other words, the build component 204 can create the RTC file package 104 based at least in part upon the specific details collected from the evaluation component 202. Therefore, each client with particular client applications, client application versions, hosting environments, etc. can include client-specific RTC file packages in order to facilitate seamless employment of real time collaboration sessions. The build component 204 can create the RTC file package 104 to include information that identifies which client application to launch and/or utilize for a real time collaboration session. Moreover, the build component 204 can compose the RTC file package 104 with information for the identified application to perform a desired purpose and/or functionality. For example, the build component 204 can create the RTC file package 104 to include information that defines a particular client application to employ, and any additional information necessary for the client application to perform and/or be utilized (e.g., input parameters, settings configurations, client information, invitee information, etc.). The RTC component 102 can also utilize a signature component 206 that can include a signature for the RTC file package 104 in order to validate its origin. The signature component 206 can incorporate a security mechanism such as a signature for the RTC file package 104 in order to ensure integrity and/or origin which defer possible malicious input attempts. The signature component 206 can provide verifiability of RTC file package 104 origin. For example, a first RTC file package can be created based upon evaluating client A's environment and/or client applications. The signature component 206 can incorporate a signature for the first RTC file package in order to ensure integrity and origin of such real time collaboration definition data (e.g., the RTC file package). In particular, the signature component 206 can incorporate information for a router (not shown) to validate its origin prior to passing the package to a target application. In another example, the signature of the RTC file package can be validated by a server (not shown), the RTC component 102, a browser (not shown), and/or any other suitable component and/or device that can validate the origin of data. The system 200 can further include a data store 208 that can include any suitable data related to the RTC component 102, RTC file package 104, the interface 106, the evaluation component 202, the build component 204, the signature component 206, etc. For example, the data store 208 can include, but not limited to including, client applications, client application versioning data, client settings, client preferences, client application listings, real time collaboration preferences, client environments, host environments, server settings, browser settings, a portion of the RTC file package 104, a plurality of RTC file packages, data collected and/or gathered from the evaluation component 202, RTC file package build data, signature data, origin data, and/or any other suitable data related to the generation of the RTC file package 104 and/or employment of a real time collaboration session. It is to be appreciated that the data store 208 can be, for example, either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). The data store 208 of the subject systems and methods is intended to comprise, without being limited to, these and any other suitable types of memory. In addition, it is to be appreciated that the data store 208 can be a server, a database, a hard drive, a pen drive, an external hard drive, a portable hard drive, and the like. FIG. 3 illustrates a system 300 that facilitates employing an RTC file package to seamlessly communicate with a server for real time collaboration session. The system 300 can include the RTC component 102 that can enable seamless implementation of real time collaboration between two or more clients utilizing the RTC file package 104. As discussed, the RTC component 102 can create the RTC file package 104 which can define a client application to employ for real time collaboration, a type of modality and/or functionality to employ for the real time collaboration (e.g., based upon the client application defined, audio, video, instant messaging, etc.), and various versioning information related to the client application and/or environment. The RTC file package 104 can be utilized by a server 302 to initiate a real time collaboration session 304. In particular, the server 302 can receive the RTC file package 104 to identify at least one of a client application to utilize for the real time collaboration session, a versioning associated with the client application, an input parameter associated with the client application identified, and/or a particular modality to utilize for the real time collaboration. By utilizing the RTC file package 104, the server 302 can enable a seamless interaction between numerous clients within the real time collaboration session 304 utilizing each client's respective RTC file package of data. For example, user A can initiate a real time collaboration with user B, wherein each user can include corresponding RTC file package data that can be utilized by the server 302 for compatibility and seamless employment of the real time collaboration session 304. In other words, the RTC file package for each participant within the real time collaboration session 304 can provide any suitable data (e.g., client application type, modality of collaboration, input parameters for the collaboration, invitee information, validity of RTC file package origin, etc.) regardless of disparate versions, environments, locations, etc. of participants. For example the RTC file package 104 can be utilized by a client application that enables live conferencing with real time audio, video, instant messaging, etc. The RTC file package 104 can include at least a portion of the following data in order to employ a real time collaboration: <Param authPasword =“” /> <Param authTicket =“” /> <Param authUserName =“” /> <Param customAiccSid =“” /> <Param customExtra1 =“” /> <Param customExtra2 =“” /> <Param customExtra3 =“” /> <Param customSource =“” /> <Param isLobby = “”/> <Param role = “”/> <Param meetingEndTime =“” /> <Param meetingID =“” /> <Param meetingPassword =“” /> <Param meetingStartTime =“” /> <Param meetingSubject =“” /> <Param recordingAgreement =“” /> <Param startURI =“” /> <Param userCompany =“” /> <Param userDisplayName =“” /> <Param userEmail =“” /> Moreover, it is to be appreciated that there can be various versions of the RTC file package 104 included within itself in order to universally applicable for real time collaborations. For instance, the RTC file package 104 can include an extensible markup language (XML) version as a cue for an XML parser (not shown) used by a router and/or an application. The RTC file package 104 can further include a version as a cure for supportability for a router. In another example, the RTC file package 104 can include a server version as a cure for a router to pick up a target application in case of multiple versions of the application residing side-by-side. Additionally, the RTC file package 104 can include a server authentication ticket as a technique to allow a router to “call home” and verify the integrity of the originating server. Furthermore, the RTC file package 104 can include a modality as a cue for a router to pick up and/or launch an application that can handle a desired real time communication mode (e.g., audio, video, chat, instant messaging, etc.). FIG. 4 illustrates a system 400 that facilitates implementing an RTC file package to seamlessly communicate with a server for real time collaboration session via a browser. The system 400 mitigates complications associated with employing a real time communication and/or collaboration between clients with differing versions of real time collaboration client applications. The system 400 can include the RTC component 102 that can receive data via the interface 106 in order to generate the RTC file package 104 which includes client application identifying data, client application versioning data, environment specifying data, input parameters data, modality defining data, and/or any other suitable data that can be utilized to implement a real time collaboration. In general, it is to be appreciated that the RTC file package 104 can enhance online collaboration between clients by providing an agnostic file package that is flexible with sufficient data to employ real time communications. The RTC file package 104 can be utilized by a browser 402 to employ the real time collaboration session 304 via the server 302. For example, the browser 402 can be any suitable browsing application and/or software that can enable interaction and/or display of text, images, and/or other information located on a website, the Internet, the World Wide Web, and/or a local area network. The browser 402 can utilize the RTC file package 104 in order to identify a client application to launch for real time communications, a modality associated with the real time communication, input parameters for the real time communication, and/or a signature and/or verification of the RTC file package 104 origin. With the agnostic and flexible RTC file package 104, the real time collaboration session 304 can be utilized independent of file format, application versioning, and/or environment characteristics for each client. The browser 402 can further utilize the server 302 to initiate the real time collaboration session 304. FIG. 5 illustrates a system 500 that facilities providing real time communications between two or more users independent of varying client application versions. The system 500 illustrates an exemplary scenario involving at least one client utilizing a real time collaboration application for real time communications. It is to be appreciated that the system 500 can include the RTC component (not shown), the interface (not shown) as described in previous figures. In general, the system 500 can enable at least two clients to seamlessly participate in a real time collaboration with a particular client application regardless of the client application versions, environments, and/or various input parameters. It is to be appreciated that the system 500 is just one example of implementing the subject innovation and that there can be various nuances and/or subtleties which are intended to be included under the scope of the claimed subject matter. For example, the RTC file package can be utilized by a server (as illustrated), a browser, and/or any suitable combination thereof. A client 502 can desire to initiate a real time communication such as a real time collaboration utilizing a client application. An RTC file package can be specifically tailored and created for the client 502. For example, the RTC file package can include data related to any available RTC client applications, input parameters for the client applications, environments hosting a client application, modalities associated with the client application for real time communication, and/or a signature validating origin and/or integrity. The client 502 can request and/or initiate a real time collaboration utilizing the RTC file package to a server 506. The RTC file package can be communicated to an intended participant such as a client 504. In response to the real time collaboration request from client 502, the client 504 can employ his/her respective RTC file package to a server 508. It is to be appreciated that the system 500 is described with client 502 and client 504 being on disparate networks. However, it is to be appreciated that if client 502 and client 504 were on a similar network, there would be a single server receiving respective RTC file package data. The server 506 and the server 508 can communicate and/or utilize the RTC file package data via the Internet 510 in order to employ a real time collaboration session 512. FIG. 6 illustrates a system 600 that employs intelligence to facilitate employing a real time collaboration session utilizing an RTC file package. Accordingly, as illustrated, system 600 can include an intelligent component 602 that can be utilized, for example, to infer RTC file package data, environment settings/characteristics, client application, client application settings, versioning with client application, real time collaboration settings/options, input parameters associated with a client application for real time collaboration, modality associated with client application, client application to launch, etc. The intelligent component 6002 can employ a probabilistic based or statistical based approach, for example, in connection with making determinations or inferences. Inferences can be based in part upon explicit training of classifiers (not shown) before employing system 600, or implicit training based at least in part upon system feedback and/or users previous actions, commands, instructions, and the like during use of the system. The intelligent component 602 can employ any suitable scheme (e.g., neural networks, expert systems, Bayesian belief networks, support vector machines (SVMs), Hidden Markov Models (HMMs), fuzzy logic, data fusion, etc.) in accordance with implementing various automated aspects described herein. Intelligent component 602 can factor historical data, extrinsic data, context, data content, state of the user, and can compute cost of making an incorrect determination or inference versus benefit of making a correct determination or inference. Accordingly, a utility-based analysis can be employed with providing such information to other components or taking automated action. Ranking and confidence measures can also be calculated and employed in connection with such analysis. The RTC component 102 can further utilize a presentation component 604 that provides various types of user interfaces to facilitate interaction between a user and any component coupled to the RTC component 102. As depicted, the presentation component 604 is a separate entity that can be utilized with the RTC component 102. However, it is to be appreciated that the presentation component 604 and/or similar view components can be incorporated into the RTC component 102 and/or a stand-alone unit. The presentation component 604 can provide one or more graphical user interfaces (GUIs), command line interfaces, and the like. For example, a GUI can be rendered that provides a user with a region or means to load, import, read, etc., data, and can include a region to present the results of such. These regions can comprise known text and/or graphic regions comprising dialogue boxes, static controls, drop-down-menus, list boxes, pop-up menus, as edit controls, combo boxes, radio buttons, check boxes, push buttons, and graphic boxes. In addition, utilities to facilitate the presentation such as vertical and/or horizontal scroll bars for navigation and toolbar buttons to determine whether a region will be viewable can be employed. For example, the user can interact with one or more of the components coupled and/or incorporated into the RTC component 102. The user can also interact with the regions to select and provide information via various devices such as a mouse, a roller ball, a keypad, a keyboard, a pen and/or voice activation, for example. Typically, a mechanism such as a push button or the enter key on the keyboard can be employed subsequent entering the information in order to initiate the search. However, it is to be appreciated that the claimed subject matter is not so limited. For example, merely highlighting a check box can initiate information conveyance. In another example, a command line interface can be employed. For example, the command line interface can prompt (e.g., via a text message on a display and an audio tone) the user for information via providing a text message. The user can then provide suitable information, such as alpha-numeric input corresponding to an option provided in the interface prompt or an answer to a question posed in the prompt. It is to be appreciated that the command line interface can be employed in connection with a GUI and/or API. In addition, the command line interface can be employed in connection with hardware (e.g., video cards) and/or displays (e.g., black and white, and EGA) with limited graphic support, and/or low bandwidth communication channels. FIGS. 7-8 illustrate methodologies and/or flow diagrams in accordance with the claimed subject matter. For simplicity of explanation, the methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts. For example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts may be required to implement the methodologies in accordance with the claimed subject matter. In addition, those skilled in the art will understand and appreciate that the methodologies could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. FIG. 7 illustrates a method 700 that facilitates creating an RTC file package associated with at least one client application and respective environment. In general, the methodology 700 can create an RTC file package that can enable real time collaboration based upon its agnostic and flexible characteristics. At reference numeral 702, a portion of data related to at least one of a client, a client application, or a client environment can be received. It is to be appreciated that the client applications can be any suitable application or software related to real time communications for collaboration between two or more clients. Thus, the client application can be any suitable client application that can employ real time communications and/or collaborations via the Internet between two or more clients. For example, the client application can provide real time collaboration sessions for various modalities such as, but not limited to, audio communications, video communications, voice over Internet protocol (VoIP) communications, instant messaging communications, desktop sharing communications, file sharing communications, etc. At reference numeral 704, an RTC file package can be created based at least in part upon the received portions of data. The RTC file package can include data corresponding to client application, client application versioning, client application modality, client environment, input parameters associated with the client application, client application identification to launch for a real time collaboration, etc. For example, the RTC file package can be created to include information that defines a particular client application to employ, and any additional information necessary for the client application to perform and/or be utilized (e.g., input parameters, settings configurations, client information, invitee information, etc.). At reference numeral 706, a real time collaboration can be employed with the RTC file package, wherein the RTC file package identifies the client application and modality for the real time communication. In other words, the RTC file package can include sufficient data in order to seamlessly initiate a real time collaboration utilizing a client application. For example, the RTC file package can define data such as, a client application to utilize for real time collaboration, a client application version, an environment related to a client application, a modality associated with a client application, at least one input parameter related to the client application, and/or any other suitable data that can be utilized to implement the client application for real time communication. In general, the RTC file package can be an application agnostic flexible portion of collected data that can invoke a family of real time collaboration applications (e.g., client applications). FIG. 8 illustrates a method 800 for utilizing real time communications between two or more users independent of varying client application versions. At reference numeral 802, an RTC file package can be built for a client. For example, a client and respective client applications and/or environment can be evaluated in order to build a client-specific RTC file package. Therefore, each client with particular client applications, client application versions, hosting environments, etc. can include client-specific RTC file packages in order to facilitate seamless employment of real time collaboration sessions. For example, the following can be defined within the RTC file package: existing client applications associated with a client; an environment associated with a client (e.g., an operating system, a computer, input devices, display devices, graphic cards, memory, processor, etc.); a client preference (e.g., available client application listing, security preference, digital signature details, communication settings, collaboration preferences, optimal and/or default settings, etc.); a versioning associated with a client application; a hardware/software configuration; and/or input parameters associated with a particular client application. At reference numeral 804, a signature can be incorporated into the RTC file package for origin authentication. The RTC file package can include the signature in order to validate origin and authenticity of the source of the RTC file package, wherein such signature ensures a particular RTC file package accurately correlates to a specific client. Therefore, prior to exposing a client to a real time communication, the RTC file package can provide a security mechanism that protects data and/or system integrity. At reference numeral 806, the RTC file package can be utilized to enable seamless real time collaboration between two or more clients. The RTC file package can be cracked open to expose data specific to a particular real time collaboration utilizing a client application, wherein such data exposed can provide at least a portion of the following: identification of a client application to utilize for real time collaboration; an input parameter required for real time collaboration utilizing the client application; a modality suggested and/or desired for the real time collaboration; a client application to utilize based on a desired modality; and/or verification of origin utilizing a signature. At reference numeral 808, the at least one of a server, a router, or a browser can be enabled to implement the RTC file package for the real time collaboration. In order to provide additional context for implementing various aspects of the claimed subject matter, FIGS. 9-10 and the following discussion is intended to provide a brief, general description of a suitable computing environment in which the various aspects of the subject innovation may be implemented. For example, an RTC component that facilitates employing a real time collaboration application with an RTC file package, as described in the previous figures, can be implemented in such suitable computing environment. While the claimed subject matter has been described above in the general context of computer-executable instructions of a computer program that runs on a local computer and/or remote computer, those skilled in the art will recognize that the subject innovation also may be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc., that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive methods may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, as well as personal computers, hand-held computing devices, microprocessor-based and/or programmable consumer electronics, and the like, each of which may operatively communicate with one or more associated devices. The illustrated aspects of the claimed subject matter may also be practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of the subject innovation may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in local and/or remote memory storage devices. Referring to FIG. 9, there is illustrated a schematic block diagram of an exemplary computing environment 900 for processing the disclosed architecture in accordance with another aspect. The system 900 includes one or more client(s) 9 10. The client(s) 910 can be hardware and/or software (e.g., threads, processes, computing devices). The client(s) 910 can house cookie(s) and/or associated contextual information by employing the claimed subject matter, for example. The system 900 also includes one or more server(s) 920. The server(s) 920 can also be hardware and/or software (e.g., threads, processes, computing devices). The servers 920 can house threads to perform transformations by employing the claimed subject matter, for example. One possible communication between a client 910 and a server 920 can be in the form of a data packet adapted to be transmitted between two or more computer processes. The data packet may include a cookie and/or associated contextual information, for example. The system 900 includes a communication framework 940 (e.g., a global communication network such as the Internet) that can be employed to facilitate communications between the client(s) 910 and the server(s) 920. Communications can be facilitated via a wired (including optical fiber) and/or wireless technology. The client(s) 910 are operatively connected to one or more client data store(s) 950 that can be employed to store information local to the client(s) 910 (e.g., cookie(s) and/or associated contextual information). Similarly, the server(s) 920 are operatively connected to one or more server data store(s) 930 that can be employed to store information local to the servers 920. With reference to FIG. 10, an exemplary environment 1000 for implementing various aspects disclosed herein includes a computer 1012 (e.g., desktop, laptop, server, hand held, programmable consumer or industrial electronics . . . ). The computer 1012 includes a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components including, but not limited to, the system memory 1016 to the processing unit 1014. The processing unit 1014 can be any of various available microprocessors. It is to be appreciated that dual microprocessors, multi-core and other multiprocessor architectures can be employed as the processing unit 1014. The system memory 1016 includes volatile and nonvolatile memory. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer 1012, such as during start-up, is stored in nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM). Volatile memory includes random access memory (RAM), which can act as external cache memory to facilitate processing. Computer 1012 also includes removable/non-removable, volatile/non-volatile computer storage media. FIG. 10 illustrates, for example, mass storage 1020. Mass storage 1020 includes, but is not limited to, devices like a magnetic or optical disk drive, floppy disk drive, flash memory or memory stick. In addition, mass storage 1020 can include storage media separately or in combination with other storage media. FIG. 10 provides software application(s) 1022 that act as an intermediary between users and/or other computers and the basic computer resources described in suitable operating environment 1000. Such software application(s) 1022 include one or both of system and application software. System software can include an operating system, which can be stored on mass storage 1020, that acts to control and allocate resources of the computer system 1012. Application software takes advantage of the management of resources by system software through program modules and data stored on either or both of system memory 1016 and mass storage 1020. The computer 1012 also includes one or more interface components 1024 that are communicatively coupled to the bus 1018 and facilitate interaction with the computer 1012. By way of example, the interface component 1024 can be a port (e.g., serial, parallel, PCMCIA, USB, FireWire . . . ) or an interface card (e.g., sound, video, network . . . ) or the like. The interface component 1024 can receive input and provide output (wired or wirelessly). For instance, input can be received from devices including but not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, camera, other computer and the like. Output can also be supplied by the computer 1012 to output device(s) via interface component 1024. Output devices can include displays (e.g., CRT, LCD, plasma . . . ), speakers, printers and other computers, among other things. What has been described above includes examples of the subject innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the claimed subject matter, but one of ordinary skill in the art may recognize that many further combinations and permutations of the subject innovation are possible. Accordingly, the claimed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims. In particular and in regard to the various functions performed by the above described components, devices, circuits, systems and the like, the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., a functional equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary aspects of the claimed subject matter. In this regard, it will also be recognized that the innovation includes a system as well as a computer-readable medium having computer-executable instructions for performing the acts and/or events of the various methods of the claimed subject matter. There are multiple ways of implementing the present innovation, e.g., an appropriate API, tool kit, driver code, operating system, control, standalone or downloadable software object, etc. which enables applications and services to use the advertising techniques of the invention. The claimed subject matter contemplates the use from the standpoint of an API (or other software object), as well as from a software or hardware object that operates according to the advertising techniques in accordance with the invention. Thus, various implementations of the innovation described herein may have aspects that are wholly in hardware, partly in hardware and partly in software, as well as in software. The aforementioned systems have been described with respect to interaction between several components. It can be appreciated that such systems and components can include those components or specified sub-components, some of the specified components or sub-components, and/or additional components, and according to various permutations and combinations of the foregoing. Sub-components can also be implemented as components communicatively coupled to other components rather than included within parent components (hierarchical). Additionally, it should be noted that one or more components may be combined into a single component providing aggregate functionality or divided into several separate sub-components, and any one or more middle layers, such as a management layer, may be provided to communicatively couple to such sub-components in order to provide integrated functionality. Any components described herein may also interact with one or more other components not specifically described herein but generally known by those of skill in the art. In addition, while a particular feature of the subject innovation may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes,” “including,” “has,” “contains,” variants thereof, and other similar words are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.	G	60G06	161G06F	15	16
11776332	US20090019514A1-20090115	METHOD AND SYSTEM FOR ENFORCING PASSWORD POLICY IN A DISTRIBUTED DIRECTORY	ACCEPTED	20081230	20090115	[]	G06F1700	["G06F1700"]	8935805	20070711	20150113	726	001000	77989.0	JOHNSON	CARLTON	[{"inventor_name_last": "Hazlewood", "inventor_name_first": "Kristin Marie", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Feng", "inventor_name_first": "Daw", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Williams", "inventor_name_first": "Gary Dale", "inventor_city": "Driftwood", "inventor_state": "TX", "inventor_country": "US"}]	The invention describes techniques for enforcing password policy within a distributed directory environment that includes one or more distributed directory servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. In one aspect, the proxy server is enhanced to support the passing (from the backend server to the client) of password policy controls. In particular, controls returned from a backend server are parsed and cached (for re-use) for the life of a given client connection. According to another aspect, the proxy server ensures that all compare operations for a single user's password are directed to the same backend server in the distributed directory environment. This insures that a user's most current password is used, and that failed operation counts, resets and operational attributes are up-to-date. According to still another aspect, the proxy server enforces password policy on bind plug-ins and, in particular, through a pair of pre-bind and post-bind extended operations. In particular, pre-bind processing includes checking if an account is locked. Post-bind processing includes checking for expired passwords, grace logins and updating failed/successful bind counters.	1. A method for enforcing password policy within a distributed directory that includes a set of directory servers, and a proxy server that acts as an intermediary between a client and the set of directory servers, comprising: at the proxy server, receiving and parsing a password policy response control; at the proxy server, storing given information obtained from the parsing step to facilitate policy enforcement upon any subsequent receipt at the proxy server of a password policy request control; and forwarding the password policy response control from the proxy server to the client. 2. The method as described in claim 1 wherein the password policy response control is returned from a given one of the directory servers in response to receipt at the directory server of a password policy request control. 3. The method as described in claim 2 wherein the password policy response control comprises one of: an error code, and a warning. 4. The method as described in claim 2 wherein the password policy response control comprises one of: an error code, a warning, an extended error code, and an extended warning. 5. The method as described in claim 1 wherein the given information obtained from the parsing step is state information that is cached at the proxy server. 6. The method as described in claim 5 wherein the given information is cached for a time period associated with a given connection between the client and the proxy server. 7. The method as described in claim 1 wherein the distributed directory is an LDAP directory. 8. The method as described in claim 1 further including: for a given user password, forwarding all password compare requests from the proxy server to a given one of the directory servers; and for the given user password, maintaining at the given one of the directory servers all information associated with a given password policy operational attribute. 9. The method as described in claim 1 further including: in response to a receipt at the proxy server of a given request, calling a directory server to perform a given bind operation. 10. The method as described in claim 9 wherein the give bind operation is an external bind. 11. A method for enforcing password policy within a distributed directory that includes a set of directory servers, and a proxy server that acts as an intermediary between a client and the set of directory servers, comprising: interacting password compare requests at the proxy server; for a given user password, forwarding password compare requests from the proxy server to a given one of the directory servers; and for the given user password, maintaining at the given one of the directory servers information associated with the given password policy operational attribute. 12. The method as described in claim 11 wherein the given password policy operational attribute is one of: a failed login count, and a password reset count. 13. The method as described in claim 11 wherein the given one of the directory servers is a write server associated with a directory partition. 14. The method as described in claim 11 wherein the given one of the directory servers is a read server associated with a directory partition. 15. The method as described in claim 11 further including: at the proxy server, passing to the client a password policy response control returned from a directory server. 16. The method as described in claim 11 further including: in response to a receipt at the proxy server of a given request, calling a directory server to perform a given external bind operation. 17. A method for enforcing password policy within a distributed directory that includes a proxy server and a set of directory servers, comprising: proxying a password policy response control through the proxy server so that, for a given client connection, the proxy server can determine whether a subsequent password operation is permitted; and forwarding one or more password compare requests from the proxy server to a given one of the directory servers so, for a given user password, information associated with a password policy operational attribute is maintained on the given one of the directory servers. 18. A computer-readable medium having computer-executable instructions for performing the method steps of claim 1. 19. A computer-readable medium having computer-executable instructions for performing the method steps of claim 17. 20. A proxy server for enforcing password policy within a distributed directory that includes a set of directory servers, comprising: means for parsing password policy controls; and means for storing given information for policy enforcement. 21. The proxy server as described in claim 20 wherein the means for parsing password policy controls includes means, responsive to receipt from a directory server of a password policy request control on an error, for sending a corresponding password policy response control. 22. The proxy server as described in claim 20 wherein the means for storing given information for policy enforcement comprises means for caching state information derived by the parsing means. 23. The proxy server as described in claim 20 further including means for forwarding one or more password compare requests to a given one of the directory servers so, for a given user password, information associated with a password policy operational attribute is maintained on the given one of the directory servers. 24. The proxy server as described in claim 20 further including means responsive to a receipt of a given request for calling a directory server to perform an external bind operation. 25. The proxy server as described in claim 20 wherein the external bind operation is a pre-bind operation. 26. The proxy server as described in claim 20 wherein the external bind operation is a post-bind operation. 27. The proxy server as described in claim 20 wherein the distributed directory is an LDAP distributed directory. 28. A distributed directory, comprising: a set of directory servers; and a proxy server for enforcing password policy within a distributed directory, comprising: means for parsing password policy controls; and means for storing given information for policy enforcement. 29. The distributed directory as described in claim 28 wherein the means for parsing password policy controls includes means, responsive to receipt from a directory server of a password policy request control on an error, for sending a corresponding password policy response control. 30. The distributed directory as described in claim 28 wherein the means for storing given information for policy enforcement comprises means for caching state information derived by the parsing means. 31. The distributed directory as described in claim 28 wherein the proxy server further includes means for forwarding one or more password compare requests to a given one of the directory servers so, for a given user password, information associated with a password policy operational attribute is maintained on the given one of the directory servers. 32. The distributed directory as described in claim 28 wherein the proxy server further includes means responsive to a receipt of a given request for calling a directory server to perform an external bind operation. 33. The distributed directory as described in claim 32 wherein the external bind operation is a pre-bind operation. 34. The distributed directory as described in claim 32 wherein the external bind operation is a post-bind operation. 35. The distributed directory as described in claim 28 wherein the set of directory servers are LDAP-compliant.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field The present invention relates to enforcing password policy in a distributed directory environment. 2. Background of the Related Art A directory is a special type of database for managing information about people, organizations, data processing systems, and other information sources. Information within a directory is organized within a hierarchical namespace. Each entry is a named object and consists of a set of attributes. Each attribute has a defined attribute type and one or more values. Each entry is identified by an unambiguous distinguished name (DN), wherein a distinguished name is a concatenation of selected attributes from an entry. A directory service provides a mechanism for searching a directory and for retrieving information from a directory. Various standards have been promulgated for defining directories and directory services. For example, the X.500 specifications define a directory standard; more information can be found in Weider et al., “Technical Overview of Directory Services Using the X.500 Protocol”, Internet Engineering Task Force (IETF) RFC 1309, March 1992. As another example, the Lightweight Directory Access Protocol (LDAP) specifications define a protocol for accessing a directory that supports the X.500 directory model; more information can be found in Wahl et al., “Lightweight Directory Access Protocol (v3),” IETF RFC 225 1, December 1997. A logical representation of a directory does not necessarily reflect an organization of the physical storage of the directory. In a manner similar to many types of memory systems, a directory may be logically supported as a cohesive whole yet physically supported in a distributed manner. For example, a single “distributed” directory may be stored across many servers, wherein each server supports a subtree of the directory. In particular, a known distributed directory environment includes one or more LDAP “backend” servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. Clients bind to the proxy server instead of directly binding to the backend LDAP servers. A set of rules that controls how passwords are used and administered in this type of directory environment is known as a “password policy.” These rules enforce various security requirements, e.g., that a user change his or her password periodically, that the user's selected password meets certain requirements for construction, that re-use of an old password is prevented, that entities are locked out after a certain number of failed attempts to use a given password, and so on. A “user” refers to any LDAP client application that has an identity in the directory. In an LDAP distributed directory environment, a given password policy is defined according to an object-oriented schema that defines a password policy object class, which includes a set of administrative password policy attributes, together with a set of operational attributes that hold general policy state information for each user. The policy also includes one or more “controls” that are used while enforcing password policy. In particular, a “request control” is defined as a control that is sent by a client with a request operation to elicit a “response control.” The “response control” typically contains one or more warnings and errors associated with password policy. Further details of how to implement password policy in this manner is described in Behera et al., “Password Policy for LDAP Directories”, Internet Drafi RFC, October 2001.	<SOH> BRIEF SUMMARY OF THE INVENTION <EOH>A method, system, apparatus, or computer program product is presented for enforcing password policy within a distributed directory environment that includes one or more distributed directory servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. According to one aspect, the proxy server is enhanced to support the passing (typically from the backend server to the client) of password policy controls, which are controls that supply information to a user about policy errors and warnings. In this aspect, the proxy server accepts a password policy request control, preferably on all operations. When a request control is received as a result of an error case, the proxy server sends a corresponding response control containing the errors that a backend server provides; if a client does not send a password policy request control, the proxy server provides “extended” error information. This aspect of the invention ensures that password policy controls returned from a backend server are parsed and cached (for policy enforcement) for the life of a given client connection. Thus, the proxy server parses the control and, if there are any warnings that apply, that state is stored on the connection. According to another aspect, the proxy server ensures that all compare operations for a single user's password are directed to the same backend server in the distributed directory environment. This insures that a user's most current password is used, and that failed operation counts, resets and operational attributes are up-to-date. According to still another aspect, the proxy server enforces password policy on bind plug-ins and, in particular, through a pair of pre-bind and post-bind extended operations. In particular, pre-bind processing includes checking if an account is locked. Post-bind processing includes checking for expired passwords, grace logins and updating failed/successful bind counters. The proxy server uses the password policy control preferably on all operations to detect and enforce warning information. The pre- and post-bind password policy extended operations provide a remote mechanism to force the proxy server to perform pre- and post-bind password policy validations and updates. The above features enforce password policy across the distributed directory environment. The password policy is local to each backend directory server; thus, the policy that applies to a single user is on the same system where the user's entry (in the distributed directory) resides. The foregoing has outlined some of the more pertinent features of the invention. These features should be construed to be merely illustrative. Many other beneficial results can be attained by applying the disclosed invention in a different manner or by modifying the invention as will be described.	CROSS-REFERENCE TO RELATED APPLICATION This application is related to Ser. No. 11/______, filed July 2007, titled “Method and system for enforcing password policy for an external bind operation in a distributed directory.” BACKGROUND OF THE INVENTION 1. Technical Field The present invention relates to enforcing password policy in a distributed directory environment. 2. Background of the Related Art A directory is a special type of database for managing information about people, organizations, data processing systems, and other information sources. Information within a directory is organized within a hierarchical namespace. Each entry is a named object and consists of a set of attributes. Each attribute has a defined attribute type and one or more values. Each entry is identified by an unambiguous distinguished name (DN), wherein a distinguished name is a concatenation of selected attributes from an entry. A directory service provides a mechanism for searching a directory and for retrieving information from a directory. Various standards have been promulgated for defining directories and directory services. For example, the X.500 specifications define a directory standard; more information can be found in Weider et al., “Technical Overview of Directory Services Using the X.500 Protocol”, Internet Engineering Task Force (IETF) RFC 1309, March 1992. As another example, the Lightweight Directory Access Protocol (LDAP) specifications define a protocol for accessing a directory that supports the X.500 directory model; more information can be found in Wahl et al., “Lightweight Directory Access Protocol (v3),” IETF RFC 225 1, December 1997. A logical representation of a directory does not necessarily reflect an organization of the physical storage of the directory. In a manner similar to many types of memory systems, a directory may be logically supported as a cohesive whole yet physically supported in a distributed manner. For example, a single “distributed” directory may be stored across many servers, wherein each server supports a subtree of the directory. In particular, a known distributed directory environment includes one or more LDAP “backend” servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. Clients bind to the proxy server instead of directly binding to the backend LDAP servers. A set of rules that controls how passwords are used and administered in this type of directory environment is known as a “password policy.” These rules enforce various security requirements, e.g., that a user change his or her password periodically, that the user's selected password meets certain requirements for construction, that re-use of an old password is prevented, that entities are locked out after a certain number of failed attempts to use a given password, and so on. A “user” refers to any LDAP client application that has an identity in the directory. In an LDAP distributed directory environment, a given password policy is defined according to an object-oriented schema that defines a password policy object class, which includes a set of administrative password policy attributes, together with a set of operational attributes that hold general policy state information for each user. The policy also includes one or more “controls” that are used while enforcing password policy. In particular, a “request control” is defined as a control that is sent by a client with a request operation to elicit a “response control.” The “response control” typically contains one or more warnings and errors associated with password policy. Further details of how to implement password policy in this manner is described in Behera et al., “Password Policy for LDAP Directories”, Internet Drafi RFC, October 2001. BRIEF SUMMARY OF THE INVENTION A method, system, apparatus, or computer program product is presented for enforcing password policy within a distributed directory environment that includes one or more distributed directory servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. According to one aspect, the proxy server is enhanced to support the passing (typically from the backend server to the client) of password policy controls, which are controls that supply information to a user about policy errors and warnings. In this aspect, the proxy server accepts a password policy request control, preferably on all operations. When a request control is received as a result of an error case, the proxy server sends a corresponding response control containing the errors that a backend server provides; if a client does not send a password policy request control, the proxy server provides “extended” error information. This aspect of the invention ensures that password policy controls returned from a backend server are parsed and cached (for policy enforcement) for the life of a given client connection. Thus, the proxy server parses the control and, if there are any warnings that apply, that state is stored on the connection. According to another aspect, the proxy server ensures that all compare operations for a single user's password are directed to the same backend server in the distributed directory environment. This insures that a user's most current password is used, and that failed operation counts, resets and operational attributes are up-to-date. According to still another aspect, the proxy server enforces password policy on bind plug-ins and, in particular, through a pair of pre-bind and post-bind extended operations. In particular, pre-bind processing includes checking if an account is locked. Post-bind processing includes checking for expired passwords, grace logins and updating failed/successful bind counters. The proxy server uses the password policy control preferably on all operations to detect and enforce warning information. The pre- and post-bind password policy extended operations provide a remote mechanism to force the proxy server to perform pre- and post-bind password policy validations and updates. The above features enforce password policy across the distributed directory environment. The password policy is local to each backend directory server; thus, the policy that applies to a single user is on the same system where the user's entry (in the distributed directory) resides. The foregoing has outlined some of the more pertinent features of the invention. These features should be construed to be merely illustrative. Many other beneficial results can be attained by applying the disclosed invention in a different manner or by modifying the invention as will be described. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIG. 1A depicts a typical distributed data processing system in which the present invention may be implemented; FIG. 1B depicts a typical computer architecture that may be used within a data processing system in which the present invention may be implemented; FIG. 1C depicts a block diagram that shows a typical distributed data processing system for an enterprise domain; FIG. 2 depicts a block diagram that shows a typical distributed directory environment; FIG. 3 depicts a block diagram that shows a typical dataflow between a client or a client application and a directory proxy server; FIG. 4 illustrates a typical distributed directory configuration; FIG. 5 illustrates a request control and its associated response control; FIG. 6 is a process flow illustrating a simple bind case according to the present invention; FIG. 7 is a process flow illustrating an external bind case according to the present invention; FIG. 8 is a table illustrating representative password policy rules and their order of selection for evaluating a user's group password policy; FIG. 9 is a table describing how restrictive attribute values are determined in one embodiment; FIG. 10 is a table showing examples of how a user's group password policy is determined in one embodiment; and FIG. 11 is a table showing examples of how effective password policies are determined. DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT In general, the devices that may comprise or relate to the present invention include a wide variety of data processing technology. Therefore, as background, a typical organization of hardware and software components within a distributed data processing system is described prior to describing the present invention in more detail. With reference now to the figures, FIG. 1A depicts a typical network of data processing systems, each of which may implement a portion of the present invention. Distributed data processing system 100 contains network 101, which is a medium that may be used to provide communications links between various devices and computers connected together within distributed data processing system 100. Network 101 may include permanent connections, such as wire or fiber optic cables, or temporary connections made through telephone or wireless communications. In the depicted example, server 102 and server 103 are connected to network 101 along with storage unit 104. In addition, clients 105-107 also are connected to network 101. Clients 105-107 and servers 102-103 may be represented by a variety of computing devices, such as mainframes, personal computers, personal digital assistants (PDAs), and the like. Distributed data processing system 100 may include additional servers, clients, routers, other devices, and peer-to-peer architectures that are not shown. In the depicted example, distributed data processing system 100 may include the Internet with network 101 representing a worldwide collection of networks and gateways that use various protocols to communicate with one another, such as Lightweight Directory Access Protocol (LDAP), Transport Control Protocol/Internet Protocol (TCP/IP), File Transfer Protocol (FTP), Hypertext Transport Protocol (HTTP), Wireless Application Protocol (WAP), and so on. Of course, distributed data processing system 100 may also include a number of different types of networks, such as, for example, an intranet, a local area network (LAN), or a wide area network (WAN). For example, server 102 directly supports client 109 and network 110, which incorporates wireless communication links. Network-enabled phone 111 connects to network 110 through wireless link 112, and PDA 113 connects to network 110 through wireless link 114. Phone 111 and PDA 113 can also directly transfer data between themselves across wireless link 115 using an appropriate technology, such as Bluetooth wireless technology, to create so-called personal area networks (PAN) or personal ad-hoc networks. In a similar manner, PDA 113 can transfer data to PDA 107 via wireless communication link 116. The present invention could be implemented on a variety of hardware platforms; FIG. 1A is intended as an example of a heterogeneous computing environment and not as an architectural limitation for the present invention. With reference now to FIG. 1B, a diagram depicts a typical computer architecture of a data processing system, such as those shown in FIG. 1A, in which the present invention may be implemented. Data processing system 120 contains one or more central processing units (CPUs) 122 connected to internal system bus 123, which interconnects random access memory (RAM) 124, read-only memory 126, and input/output adapter 128, which supports various I/O devices, such as printer 130, disk units 132, or other devices not shown, such as an audio output system, and the like. System bus 123 also connects communication adapter 134 that provides access to communication link 136. User interface adapter 148 connects various user devices, such as keyboard 140 and mouse 142, or other devices not shown, such as a touch screen, stylus, microphone, etc. Display adapter 144 connects system bus 123 to display device 146. Those of ordinary skill in the art will appreciate that the hardware in FIG. 113 may vary depending on the system implementation. For example, the system may have one or more processors, such as an Intel® Pentium®-based processor and a digital signal processor (DSP), and one or more types of volatile and non-volatile memory. Other peripheral devices may be used in addition to or in place of the hardware depicted in FIG. 1B. The depicted examples are not meant to imply architectural limitations with respect to the present invention. In addition to being able to be implemented on a variety of hardware platforms, the present invention may be implemented in a variety of software environments. A typical operating system may be used to control program execution within each data processing system. For example, one device may run a UNIX operating system, while another device contains a simple Java runtime environment. A representative computer platform may include a browser, which is a well known software application for accessing hypertext documents in a variety of formats, such as graphic files, word processing files, Extensible Markup Language (XML), Hypertext Markup Language (HTML), Handheld Device Markup Language (HDML), Wireless Markup Language (WML), and various other formats and types of files. The present invention may be implemented on a variety of hardware and software platforms, as described above with respect to FIG. 1A and FIG. 1B. More specifically, though, the present invention is directed to an improved distributed data processing environment. Prior to describing the present invention in more detail, some aspects of typical distributed data processing environments are described. The descriptions of the figures herein may involve certain actions by either a client device or a user of the client device. One of ordinary skill in the art would understand that responses and/or requests to/from the client are sometimes initiated by a user and at other times are initiated automatically by a client, often on behalf of a user of the client. Thus, when a client or a user of a client is mentioned in the description of the figures, it should be understood that the terms “client” and “user” can be used interchangeably without significantly affecting the meaning of the described processes. Certain computational tasks may be described below as being performed by functional units. A functional unit may be represented by a routine, a subroutine, a process, a subprocess, a procedure, a function, a method, an object-oriented object, a software module, an applet, a plug-in, an Active control, a script, or some other component of firmware or software for performing a computational task. The descriptions of the figures herein may involve an exchange of information between various components, and the exchange of information may be described as being implemented via an exchange of messages, e.g., a request message followed by a response message. It should be noted that an exchange of information between computational components, which may include a synchronous or asynchronous request/response exchange, may be implemented equivalently via a variety of data exchange mechanisms, such as messages, method calls, remote procedure calls, event signaling, or other mechanism. The present invention is described below with respect to terminology and functionality as associated with X.500 directories and Lightweight Directory Access Protocol (LDAP) operations, but it should be noted that the present invention may be implemented using a variety of directory implementation schemes and protocols. With reference now to FIG. 1C, a block diagram depicts a typical distributed data processing system for an enterprise domain. As in a typical corporate computing environment or an Internet-based computing environment, enterprise domain 150 hosts controlled resources that user 151 can access, e.g., by using browser application 152 on client device 153 through network 154. Enterprise domain 150 supports multiple servers. Application servers 155 support accessible resources through web-based applications or other types of applications, including legacy applications. Authentication servers 156 support various authentication mechanisms, such as username/password, X.509 certificates, secure tokens, or an SSL session. Proxy server 157 performs a wide range of functions for enterprise domain 150. Proxy server 157 can be administratively configured through configuration files and enterprise policy database 158 to control the functionality of proxy server 157, e.g., caching web pages in order to mirror the content from an application server or filtering the incoming and outgoing datastreams through input datastream filter unit 159 and output datastream filter unit 160. Input datastream filter unit 159 may perform multiple checks on incoming requests while output datastream filter unit 160 may perform multiple checks on outgoing responses; each check may be performed in accordance with goals and conditions that are specified within various enterprise policies. Enterprise domain 150 comprises entitlements server 161, which accepts information within user registry database 162, access control list (ACL) database 163, and third-party datastreams 164 from other domains. Entitlements server 161 determines whether users are authorized to access certain services that are provided by application servers 155 within domain 150 by checking policies and/or access control lists against user requests for those services. A set of user-specific entitlements is used by proxy server 157, entitlement server 161, or a combined or coordinated effort between proxy server 157 and entitlement server 161 to determine or control access to application servers 155 and other controlled resources in response to user requests. The above-noted entities within enterprise domain 150 represent typical entities within many computing environments. Web-based applications can utilize various means to prompt users to enter authentication information, often as a username/password combination within an HTML form. In the example that is shown in FIG. 1C, user 151 may be required to be authenticated before client 153 may have access to resources, after which a session is established for client 153. In FIG. 1C, after receiving an incoming request from client 153, input datastream filter unit 159 may determine whether client 153 has already established a session; if not, an authentication service on authentication servers 156 can be invoked in order to authenticate user 151. If client 153 has already established a session, then additional checks may be performed on an incoming request prior to granting access to a controlled resource; the additional checks may be specified in an enterprise authentication policy. With reference now to FIG. 2, a block diagram depicts a typical distributed directory environment. User 202 operates client application 204, which may execute on a client device such as client 153 as shown in FIG. 1C. Client application 204 interacts with directory servers through a proxied directory server, also known as a directory proxy server or a proxy directory server, which is shown as proxy server 206; proxy server 206 may execute on the user's client device or elsewhere within a network of connected devices, such as those shown in FIG. 1A. Proxy server 206 may be associated with configuration files 208 that contain information that is managed via an administrative user application to control the functionality of proxy server 206. Proxy server 206 acts as an intermediate agent (an “intermediary”) to the distributed directory environment. Although only one proxy server is shown, there may be multiple such proxy servers or proxy server instances running on one or more physical machines. Proxy server 206 is able to perform operations in accordance with a variety of directory schemes and protocols, including LDAP specifications. Proxy server 206 contains proxy authorization control functional unit 210, which generates proxy authorization controls, also called proxied authorization controls, that are employed by proxy server 206 to perform an operation with respect to the distributed directory on behalf of client application 204, or equivalently, on behalf of user 202. As described in Wahl et al., “Lightweight Directory Access Protocol (v3)”, IETF RFC 2251, December 1997, a control is a way to specify extension information for use with an LDAP operation. Controls can be sent as part of an LDAP request and apply only to the accompanying request. If the server recognizes the control type and it is appropriate for the operation, the server will make use of the control when performing the requested operation; various optional parameters can be used to inform the server whether or not to ignore the control if it is unrecognized or it is inappropriate. The control also contains an object identifier that has been assigned to the control. Hence, proxy authorization control functional unit 210 can present an application programming interface (API) that accepts a proxy distinguished name (DN) as an input parameter; this input parameter specifies the DN of the entry of the identity that proxy server 206 is to assume when performing an operation on behalf of client application 204 or user 202. The provided API can be used by the caller to create an LDAP control containing the proxy authorization identity; the created proxy authorization control would then be included in LDAP operations to request an operation from a directory server. Using the proxy authorization control mechanism, a client, or in this case, proxy server 206, can bind to the directory engine using its own identity, but is granted proxy authorization rights of another user, i.e. user 202 or client application 204, to access the target directory. When the LDAP server receives an operation with proxy authorization control, the bind DN is validated against the administrative group and/or the predefined proxy authorization group to determine whether the bind DN should be granted the proxy authorization right. In other words, the bound application client, which is proxy server 206 in this example, must be a member of the administrative group or proxy authorization group to request a proxy authorization operation. More information about using a proxy authorization control can be found in Weltman, “LDAP Proxied Authorization Control,” IETF Internet-Drafi, draft-weltman-1dapv3-proxy-12.txt, April 2003. The LDAP protocol also supports an extension mechanism that allows additional operations to be defined for services that are not defined within the LDAP specification. An extended operation allows clients to make requests and receives responses with predefined syntaxes and semantics that may be specific to particular implementations. The distributed directory environment includes multiple directory servers 212-216 that interoperate within the same distributed data processing environment as proxy server 206 and client application 204, e.g., in a manner similar to the distributed data processing environments that are shown in FIG. 1A and FIG. 1C. Directory servers 212-216 support functionality for accessing datastores that contain portions of a distributed directory, i.e. portions of a directory information tree, shown as distributed directory datastores 218-222. Directory servers 212-216 also contain functionality, which is not shown in FIG. 2, that supports the receipt and processing of proxied authorization controls, e.g., as may be sent by proxy server 206 or other directory clients. A typical directory server is a relational database management (RDBM) server. In a manner similar to the scenario that was described further above, user entries, group entries, and target object entries that arc of interest to a particular directory operation may reside in different portions of a distributed directory that are supported on different systems. In the example that is shown in FIG. 2: target object entry 224 resides within distributed directory datastore 218; user entry 226 resides within distributed directory datastore 220; and group entry 228 resides within distributed directory datastore 222. These locations are merely representative. With reference now to FIG. 3, a block diagram depicts a typical dataflow between a client or a client application and a directory proxy server. Client 302 sends request message 304 that represents a request for a directory operation to proxy server 306. After performing the requested directory operation, proxy server 306 returns response message 308 that represents a response for the requested directory operation to client 302. Client 302 then performs some additional computation task on the information that it has received. In this manner, the exchange of a request and response with respect to a directory operation between a client and a directory proxy server is similar to a dataflow that would be found within a typical distributed directory environment. It may be assumed that proxy server 306 obtains or has previously cached a user identity and any necessary authentication credentials for performing an authentication operation (not shown) for the user or the client for which the directory operation is being performed. In summary, a distributed directory is a directory environment in which data is partitioned across multiple directory servers. As illustrated in FIG. 3, the distributed directory typically comprises a collection of machines including relational database management (RDBM) servers holding data, and one or more proxy servers managing the topology. A representative proxy server may be an IBM® Tivoli® Directory Server that provides, among other functions, request routing, load balancing, failover, distributed authentication and support for distributed/membership groups and partitioning of containers. As described above, the directory proxy server sits at the front-end of a distributed directory and provides efficient routing of user requests thereby improving performance, and providing a unified directory view to the client. The proxy server also provides data support for groups and ACLs that are not affected by partitioning, and support for partitioning of flat namespaces. The proxy server is configured with connection information to connect to each of the backend servers for which it is proxying. Typically, the connection information comprises of host address, port number, bind DN, credentials and a connection pool size. Each of the back-end servers is configured with the DN and credentials that the proxy server uses to connect to it. The DN must be a member of the backend server's (local) administration group or local administrator. In particular, the DN must have administrative and proxy authorization authority. The proxy server is configured with the same schema as the backend servers for which it is proxying. The proxy server also is configured with partition information, which determines how the data is distributed between the backend servers. FIG. 4 illustrates a typical distributed directory configuration 400 in more detail. In this setup, three servers 402, 404 and 406 have their data split within a “container” (under some entry in the directory tree). Because the proxy server 408 handles the routing of requests to the appropriate servers, no referrals are used. Client applications need only be aware of the proxy server. The client applications never have to authenticate with servers A, B, or C. Typically, data is split evenly across the directories by hashing on the RUN just below the base of the split. In this example, the data within the subtree is split based on the hash value of the RDN. Hashing is only supported on the RDN at one level in the tree under a container. Nested partitions are allowed. In the case of a compound RDN, the entire normalized compound RDN is hashed. The hash algorithm assigns an index value to the DN of each entry. This value is then used to distribute the entries across the available servers evenly. The parent entries across multiple servers must remain synchronized. It is the administrator's responsibility to maintain the parent entries. ACLs must be defined at the partition base level on each server. The hash value enables the proxy server to locate and retrieve entries. For example: Data under o=ibm,c=us is split across three servers. This means that the proxy server is configured to hash RDN values immediately after o=ibm,c=us among 3 servers, or “buckets.” This also means that RDN values more than 1 away from o=ibm,c=us will map to the same server as values immediately after o-ibm,c=us. For example, cn=test,o=ibm,cus and cn=user1,cn=test,o=ibm,c=us will always map to the same server. Server A 402 holds all the entries with a hash value of 1, server B 404 holds all the entries with a hash value of 2, and server C 406 holds all the entries with a hash value of 3. The proxy server receives an add request for an entry with DN cn=Test,o=ibm,c=us. The proxy server then uses the configuration information (specifically that there are 3 partitions with a base at o=ibm,c=us) and the cn=Test RDN as inputs to the internal hashing function. If the function returns 1, the entry resides on Server A 402 and the add request is forwarded there. With the use of LDAP servers for authentication, is important that a LDAP server support policies regarding password expiration, failed login attempts, and password rules. The proxy server provides configurable support for all three of these kinds of policies. This policy is applied to all directory entries having a given (e.g., “userPassword”) attribute. The proxy server also provides a mechanism for clients to be informed of password policy related conditions (password expires in three days), and a set of operational attributes that an administrator can use to search for certain conditions, such as users with expired passwords or locked out accounts. An administrator can configure behavior of the proxy server with respect to passwords in one or more of the following areas. a global “on/off” switch for enabling or disabling password policy, rules for changing passwords, rules for password expiration, rules for password validation, rules for failed logins, and the like. Typically, the password policy settings for the directory server are stored in a named object, such as “cn=pwdpolicy” or “cn=pwdpolicy,cn=-policies”. The proxy server password policy support includes a set of LDAP controls that can be used by a password policy aware application to receive notification of additional password policy related conditions. An application can be informed of one or more warning conditions, such as: “Time remaining before password expiration,” “Number of grace logins remaining after the password has expired,” and the like. An application can also be informed of one or more error conditions, such as: “password has expired,” “account is locked,” “password has been reset and must be changed,” “user is not allowed to change their password,” “old password must be supplied when changing password,” “new password violates syntax rules,”. new password is too short,” “password has been changed too recently,” “new password is in history,” and the like. Preferably, two controls are used. As described above, a password policy request control is used to inform the server that the application wishes to be informed of password policy related conditions. This control must be specified by the application on all operations for which it is interested, typically an initial bind request and any password change requests. If the password policy request control is present, a password policy response control is returned by the server when any of the above error conditions are present. The proxy server may provide client APIs that can be used by C applications to work with these controls. In the alternative, LDAP directory client APIs may be used to process the controls. For example, the Java Naming and Directory Interface (JNDI) has built-in support for some well-known controls, and it also provides a framework for supporting controls that JNDI does not recognize. FIG. 5 illustrates a representative password policy request control 500 and its corresponding response control 502. By way of additional background, the backend directory server also maintains a set of operational attributes for each entry that has a userPassword attribute. These attributes can be searched by authorized users, either used in search filters, or returned by the search request. In a representative embodiment, these attributes include, for example: pwdChangedTime, a GeneralizedTime attribute containing the time the password was last changed; pwdAccountLockedTime, a GeneralizedTime attribute containing the time at which the account was locked; pwdExpirationWarned, a GeneralizedTime attribute containing the time at which the password expiration warning was first sent to the client; pwdFailureTime, a multi-valued GeneralizedTime attribute containing the times of previous consecutive login failures; pwdGraceUseTime, a multi-valued GeneralizedTime attribute containing the times of the previous grace logins, and pwdReset, a Boolean attribute containing the value TRUE if the password has been reset and must be changed by the user. Password policy information is replicated by supplier servers to consumers. Changes to the named entry are replicated as global changes, like changes to the schema. Password policy state information for individual entries is also replicated, so that, for example, if an entry is locked on a supplier server, that action will be replicated to any consumers. Typically, password policy state changes on a read-only replica typically do not replicate to any other servers. In the prior art, the proxy server does not provide password policy enforcement; in effect, such enforcement is done entirely on the backend servers. This approach is problematic for several reasons. It does not support the passing (from the backend to the client) of password policy controls to communicate warnings and extended error codes. Moreover, because user entries and target entries can reside on different backend systems, the directory cannot insure consistent policy enforcement in many circumstances. As just one example, if the proxy server round robins compare operations, it is likely that different backend servers will end up having inconsistent operational attributes. This makes it difficult for the directory to keep such attributes (e.g., failed counts, resets, or the like) up-to-date. In addition, in the prior art, external bind mechanisms bypass the bind code by performing search and compare requests that have the effect of bypassing both the proxy server and backend server password policy enforcement. The present invention addresses these and other such deficiencies. In particular, the present invention describes a set of techniques that serve to enforce distributed password policy within a distributed directory environment such as described above. Preferably, there are three (3) distinct enhancements to the proxy server, although the present invention contemplates that any one or more of these enhancements may be implemented. In one aspect, the proxy server is enhanced to support the passing (typically from the backend server to the client) of password policy controls. In particular, controls returned from a backend server are parsed and cached (to store state information, for policy enforcement) for the life of a given client connection. According to another aspect, the proxy server ensures that all compare operations for a single user's password are directed to the same backend server in the distributed directory environment. This enhancement insures that a user's most current password is used, and that failed operation counts, resets and operational attributes are up-to-date. According to still another aspect, the proxy server enforces password policy on bind plug-ins and, in particular, using a pair of pre-bind and post-bind extended operations. In particular, pre-bind processing includes checking if an account is locked. Post-bind processing includes checking for expired passwords, grace logins and updating failed/successful bind counters. When these policy server enhancements are used collectively, the distributed directory environment provides robust and scalable password policy enforcement. Each of these enhancements is now described in more detail. Password Policy Control Support According to a feature of the present invention, the proxy server is enhanced to support the passing of password policy controls. In particular, as noted above the password policy control supplies necessary information to a user about errors and warnings. An error is a condition that prevents a bind or feature operation; a warning merely is informational. The proxy server is enhanced to accept the password policy request control, preferably on all operations. When the request control is received from a client, the proxy server passes it to one of the backend servers; the proxy server then sends to the client a corresponding response control containing the errors and/or warnings that a baekend server provides. Extended error and/or warning information may be provided if the client did not send the password policy request control. Where the response control is the same as would be provided by the backend server directly, the proxy server can take that control directly from the backend server and return it to the client. There are several cases, however, where the proxy server generates the response control without contacting a backend server. These are discussed in more detail below. The net result is that the client receives the same result from the proxy server as it would from a backend server that contained all the information locally (to the backend server). When a backend server receives a request without a password policy control and a password policy error or warning needs to be sent, the error or warning is returned to the proxy as additional information (preferably in a text format). If, however, a client did not send a password policy control but an error or warning needs to be returned to the client, the proxy server translates the request from a control format to provide the client such additional information. If password policy is disabled, the passing of the controls is skipped. FIG. 6 is a process flow diagram illustrating this operation for a simple bind case. The routine begins at step 600 when the client requests a simple bind to the proxy server. The proxy server, at step 602, routes the compare request to an appropriate one of the backend servers and sends the password policy control. At step 604, the backend directory server that receives the compare request performs pre-bind checking. A determination is then made at step 606 to determine if the account is locked. If so, the backend directory server generates a return error code at step 608. If the account is not locked, the backend directory server performs a password compare at step 610, using the post-bind password policy 612. A test is performed at step 614 to determine whether the password compare is true. If not, the routine branches back to step 608 to generate the return error code. If, however, the password compare returns true, the backend directory server generates a return success code at step 616. The return error or return success, as the case may be, is then forwarded back to the proxy server. At step 618, the proxy server parses the return code and the password policy control. The proxy server also caches this state information. At step 620, the proxy server returns the result back to the client. The client receives and parses the result at step 622 to complete the process. Thus, in this operation, a user binds to the proxy server, which then performs a compare request for the user's password attribute, sending the password policy control. The backend server performs the pre-bind password policy checking; if the user's account is not locked and the password is correct the compare succeeds and the bind is allowed. If the compare succeeds but a warning (e.g., grace login, password must change, or the like) is returned, the proxy server returns the warning to the client. If, however, the password is invalid, the failed login count is incremented in the backend server. When the user requests a password modify, the modify operation is performed on the backend server using a proxy authentication control. Preferably, the backend server enforces all of the password policy rules related to the modification. Thus, no special processing is needed at the proxy server for modifies. The password policy control handling routine of the present invention is conveniently implemented as software, i.e., as a set of program code or instructions. This code may be native to the proxy server codebase or associated therewith. The code enables the proxy server to parses the response control, to cache it for re-use for the life of the client connection, and to pass the control through to the requesting client. By caching the response control, the proxy server determines whether given operations (e.g., password must change) are permitted to be performed, e.g., during a subsequent request. The following two sections provide additional description of how the password policy control enhancement is implemented. Honoring Password must Change In a common scenario, a password policy has an option configured that when a specific set of events occurs a user must change their password before they can perform any other operations. On a backend server must change is calculated at bind time; in particular, if a user must change his or her password before performing other operations, the connection is marked as must change and a warning is returned in the password policy control. As also noted above, the proxy server uses compare operations to authenticate users. When the backend server receives a compare operation for a user's password on a connection that is bound as an administrator, password must change is calculated for the target user. If must change is required, a warning is returned in the password policy control. According to the first feature as described above, the proxy server then parses the response password policy control looking for must change. If the user is required to change their password, the client connection is marked must change, and the appropriate warning is returned (by the proxy server) to the client in the password policy control. Because the proxy server is using the password policy control to gain information about password policy status, the proxy server always sends the password policy control on compare operations to the backend server, even if the requesting client did not send a password policy control. Once must change is determined for a specific client connection, only modify operations that impact the target user's password are allowed by the proxy server. The checking must happen at the proxy server level because operations could target a backend that is not aware of the users' account status. If password policy is disabled, however, this checking is skipped. Grace Logins not Honored As noted above, preferably the proxy server sends the password policy control on all compare requests. In this example, the response control contains a number of grace logins left for a user and returns success if the password is valid and the account is one of the following: not locked, not expired, expired but grace logins are left. This is not a change to the password compare on a backend server. Thus, the proxy server uses the password policy control to gain information about the account status instead in lieu of an account status extended operation. This information is cached at the proxy server, as has been previously described. Password Policy Compares Directed to a Single Write Server As noted above, according to the second aspect of the present invention, preferably the proxy server always routes all compare requests to a single backend server, e.g., to keep the failed login count on one backend server in the distributed directory. Once again, a convenient way to implement this feature is in proxy server code. All bind requests results in directing compare operations to the current primary write server for the target partition. According to this feature, all compare operations for a single user's password are directed to the same backend server, which insures a most current password is used and failed operation counts, reset and all operational attributes are up-to-date. If no write server is available for a partition, the proxy server targets the compare to a single read backend server for the partition. If a user requests a password compare, the proxy server also directs this compare directly to the primary write server. If the primary write server goes down, the proxy server fails over to another write server. If no write servers are available for the partition, the compare request is sent to a read only server. This ensures that users can still bind, even when all the write servers have failed. Preferably, all compares are directed to a single read server in this case. Supporting Bind Plug-Ins As also noted, a further enhancement enables the proxy server to provide support for bind plug-ins in the context of password policy enforcement. Generally, a bind plug-in is a library that extends the capabilities of the proxy server or a backend directory server. It is dynamically loaded into the server's address space when started. Once the plug-in is loaded, the server calls one or more functions in a shared library by using function pointers. In an illustrative embodiment the bind plug-in is a pre-operation plug-in, which is a plug-in that can execute a function before a directory operation is performed. A pre-operation plug-in may extend the available mechanisms that can be used to facilitate a bind operation. A pre-operation bind plug-in can be added to the proxy server, for example, to facilitate user credential validation. Such a bind plug-in has the ability to authenticate a user without ever calling into the proxy backend. (The proxy server backend should not be confused with the directory server, which is sometimes referred to herein as a backend server). This presents a unique problem in the proxy server environment because the bind plug-ins bypass the password policy code implemented in the proxy backend and therefore bypass password policy enforcement. A pre-operation bind plug-in needs the ability to access the pre- and post-bind password policy processing. On a normal backend directory server this can be done with simple API calls that directly access the RDBM backend library. On the proxy server, however, there needs to be a mechanism for the proxy server to call into the backend servers to tell the server to do pre- or post-bind processing. Two API functions are provided for the password policy support for bind plug-ins feature. These functions call into the primary backend, preferably using two different function pointers. The proxy server adds support for these two function pointers. A first function call (e.g., _prebind_accountcheck) should be called once the DN is known and before authentication is completed. A_postbind_pwdpolicycheck function is called once authentication is determined. A_prebind_accountcheck call determines password policy access. A _postbind_pwdpolicycheck call updates the password policy counters as necessary. On an RDBM server, the API functions call into an RDBM library and perform the appropriate processing. On a proxy server, the API functions call into a proxy server backend, which makes extended operation calls to the backend servers. The following sections outline the pre- and post-bind functions behavior on a proxy server. Remote Password Policy Extended Operations The proxy server includes a mechanism to tell a backend server to perform password policy verification/updates both before and after a bind request. Two extended operations are implemented in the RDBM backend server; they are a Password Policy Initialize and Verify Bind Extended Operation, and a Password Policy Finalize and Verify Bind Extended Operation. Both extended operations can be enabled or disable via a setting in an LDAP configuration file, e.g., in the cn=Directory, cn=RDBM Backends, cn=Company Directory, cn=Schernas, cn=Configuration entry. Password Policy Initialize and Verify Bind Extended Operation This extended operation accepts a Bind DN and is performed when bound as an administrator. Preferably, the extended operation is implemented on an RDBM backend server and simply calls in to the RDBM to the pre-bind password policy code. The extended operation checks to see if the target user's account is locked. Possible return codes include codes for internal server error, the users account is locked, invalid DN or password, requester does not have permission to perform the request, and the like. Password Policy Finalize and Verify Bind Extended Operation This extended operation accepts a Bind DN and return code and is performed when bound as an administrator. The extended operation is implemented on an RDBM backend server and calls in to the RDBM to the post-bind password policy code. The extended operation checks if a password is expired and if any grace logins are left. The extended operation also updates the success and failure counts/times on the entry. Thus, the present invention provides a mechanism for the proxy server to support bind plug-ins. Pre-bind processing includes checking if an account is locked. Post-bind processing includes checking for expired passwords, grace logins and updating failed/successful bind counters. A representative pre-operation bind plug-in may implement any convenient mechanism for validating a user's credentials where the credentials are other than merely a DN and a password. One such bind plug-in is a digest MD5 bind plug-in. FIG. 7 is a process flow diagram illustrating this proxy server enhancement in the context of an external bind operation. The routine begins at step 700 when the client requests an external bind to the proxy server. The proxy server plug-in, at step 702, initiates a pre-bind extended operation and routes the request to an appropriate one of the backend servers. At step 704, the backend directory server that receives the compare request performs pre-bind checking. A determination is then made at step 706 to determine if the account is locked. If so, the backend directory server generates a return error code at step 708. If the account is not locked, the backend directory server generates a return success code 710. At step 712, the proxy server plug-in performs a credential validation. The plug-in then initiates a post-bind extended operation at step 714, using the post-bind password policy 716. At step 718, the proxy server parses the return code and the password policy control. The proxy server also caches this state information. At step 720, the proxy server returns the result back to the client. The client receives and parses the result at step 722 to complete the process. Thus, the proxy server bind plug-in calls pre- and post-bind processing functions that, in turn, call into the backend, resulting in extending operation calls. In particular, a Password Policy Initialize and Verify Bind Extended Operation accepts a bind DN and checks to see if the target user's account is locked. The extended response value indicates if the bind request should be allowed, and any warnings are returned using the password policy control. The Password Policy Finalize and Verify Bind Extended Operation accepts a bind DN and checks if a password is expired and if any grace logins are left. The extended operation also updates the success and failure counts/times on the entry. Any warnings are returned using the password policy control. The extended response value indicates if the request processing succeeded; preferably, it does not prevent the request. These extended operations can be used by any client application to force the proxy server to do pre- and post-bind password policy processing remotely. The following sections provide additional details regarding the bind plug-in support. API Functions Two API functions are provided may be used, for example, by bind plug-in writers. Preferably, these functions are called for all bind plug-ins that handle binds. In the RDBM server, the functions simply call the _prebind_accountcheck and _postbind_pwdpolicycheck functions. In the proxy server, the functions call into the proxy server backend, which in turn makes extended operation calls into the RDBM backend. Two API functions are provided to access and set response controls. Plug-in writers may require access to get the response controls generated from other API calls. In addition the plug-in writer may need to update the response controls in some way. The _get_response_controls and _set_response_controls functions provide this necessary access. Get Response Control The _get_response_controls function returns a copy of the list of response controls. As noted above, response controls are the controls that the proxy server sends in the response to the client. Set Response Control The_set_response_controls function allows the caller to replace the entire list of response controls associated with a single operation. The present invention provides several advantages. As noted above, password policy communicates warnings and extended return codes using controls. In prior distributed directory schemes, the proxy server did not support the passing (and, in particular, from the backend server to the requesting client) of the password policy controls to communicate the warnings and extended error codes. The present invention enhances the proxy server to support the parsing, caching (for policy enforcement) and passing of such controls. In addition, the prior art proxy schemes were deficient in managing several other aspects of password policy (e.g., password must change warning, password policy lockout, inability of administrators to modify a user's password while bypassing policy rules, lack of support for extended return codes and warnings, failure to honor grace logins, inconsistent tracking of failed attempts before account locking, and the like). The present invention addresses these deficiencies as well, in part by ensuring that all compare operations for a single user's password are directed (by the proxy server) to the same backend server. This insures that a user's most current password is used, and that failed operation counts, resets and operational attributes remain up-to-date. Further, as noted above bind plug-ins present a unique challenge in a distributed directory environment. The present invention presents a series of extended operations that address the problem, to enable full support for bind plug-ins. The present invention provides the further advantage that it does not impact password policy in the backend server. In particular, password policy will work in the backend server as designed. Preferably, all policy information is stored locally on the same backend server as the user. Thus, any policy information that applies to a specific user preferably resides on the same server as the user's entry. The above discussion assumes a single password policy entry in the directory and that all users (except perhaps directory administrators or members of administrative groups) comply with the rules defined in this entry. It would be desirable to enable each user in the directory to have his or her individual password policy. Furthermore, to assist administrators, it would be desirable to support group password policy to enable effective password management. Thus, when it is time to decide to which set of password rules a user should adhere, all three policies, if they exist, may be taken into consideration. The following sections describe how and when these rules are determined for a given user in a multiple password polices environment. In this environment, there may be various types of password policies, including individual, group and global. Group Password Policy Preferably, an association between a group object and a password policy entry is supported so that the members of the group can be controlled by a set of special password rules. In an embodiment, an operational attribute (e.g., pwdGroupPolicyDN) points to a password policy entry and can be used in any user group object, such as accessgroup, accessRole, groupOfNames, groupOfliniqueNames, and the like. This approach leverages existing group-related functionalities, such as group membership determination, group referential integrity and the like, but extends the functions to support a group-related password policy. If the DN of a directory administrator and/or the DN of a local administrator group member are specified as one of the members of a password policy group, preferably the DN is ignored. The password of a directory administrator or a member of a administrator group is governed by the administrator password policy defined in a configuration file. Because a user entry may belong to more than one group, multiple group password policy entries preferably are evaluated before the user's group policy can be determined. In a representative embodiment, attributes in all the group password policy entries are combined to form a union of attributes with the most restrictive attribute values taking precedence. How a user's composite group policy is determined is described below. An administrator may exempt a group's policy from being used in the evaluation of the composite group policy. Thus, if a user belongs to a group to which a cn=noPwdPolicy is assigned, then the user's effective policy will not include any attributes from this group policy. Other group policies as well as the global policy and the individual policy will still be evaluated Individual Password Policy According to this feature, every user is allowed to have his or her individual password policy. This feature is implemented with an operational attribute, e.g., pwdIndividualPolicyDN, which points to a password policy entry; in this way, a user entry is extended to have its own password policy entry. This named reference password policy design provides an efficient way to associate multiple user entries to the same policy entry. By changing the attributes of the password policy entry, an administrator can effectively manage a set of users without modifying any of the user entries. It is not required that all of the password policy attributes need to be defined in a user's individual or group password policy entry. During password policy evaluation time, a user's individual group and global password policy are searched, preferably in order. If an attribute is not defined in the individual password policy entry, it will be searched in the composite group password policy entry. If the attribute is not found, an attribute in the global password policy entry will be used. In the event the attribute is not defined in the global password policy entry either, then a default value may be assumed. By assigning a value of cn=noPwdPolicy to attribute pwdIndividualPolicyDN for a password policy extended user entry, an administrator may exempt a user from any password policy controls. This is different from not defining the attribute in the entry. If the attribute is not defined, the user's effective password policy is derived from the user's group (if it exists) and the global policy. If the attribute is defined with the special value, however, then the effective password policy is not evaluated at all, and the user is not controlled by any password rules. Password Evaluation Preferably, a global password policy entry is created if it does not exist when the proxy server starts up. Typically, the global password policy entry is created with an pwdPolicy attribute set to false. When the attribute is set to true the effective password 15 policy is evaluated for a user. The evaluation of a user's password policy preferably takes place at the beginning of a connection if the bind user is not a local administrative user. Once the user's effective password policy has been determined, preferably it is stored to a local structure for the user. Preferably, this local copy is used for the life of the entire connection. After a connection is established, and depending on the type of the operation, the effective password policy of the target entry may need to be evaluated. Preferably, this effective password policy is also stored in a local structure and used by the operation. Evaluation of a User's Group Password Policy Because a user entry may belong to more than one group, multiple group password policy entries may be evaluated before the user's group policy is determined. The following are one or more sample rules that may be used to determine a user's composite group password policy (not all are required): (i) attributes in all the group password policy entries are combined to form a union of attributes with the most restrictive attribute values taking precedence; (ii) If -pwdPolicy is set to false in a password policy entry, all the attributes defined in the entry will not be used to calculate the composite group password policy; if the attribute is not set, it is defaulted to false; (iii) if -pwdGroupPolicyDN has a value of cn=noPwdPolicy in all of the groups that a user belongs to, no composite group password is evaluated for the user. In this case, unless the user has an individual password policy defined, no policy (not even the global) is applied; (iv) An attribute defined with a non-default value is more restrictive than if defined with a default value which, in turn, is more restrictive than if it is not defined; (v) Some password policy attributes may be dependent on each other. Thus, for example, the value of passwordMinAlphaChars is set to less than or equal to the value in pwdMinLength minus the value in passwordMinOtherChars. If one attribute is selected from a policy, then preferably the other two attributes are also selected from the same policy. A preferred order of selection is pwdMinLength, passwordMinOtherChars, and passwordAlphaChars. Thus, in this example, the selection is based on picking a largest value for pwdMinLength. If there are two with the same value for that attribute, then the one with the largest value for passwordMinOtherChars may be selected. Once an attribute is selected, preferably the other two attributes are selected automatically. This all-or-none selection guarantees the validity of the values of a composite group password policy. Although not meant to be limiting, FIG. 8 is a table that lists the rules among password policy attributes and one illustrative embodiment detailing an order of selection of these attributes. FIG. 9 is a table describing how the most restrictive attribute values are determined in an illustrative embodiment. FIG. 10 is a table showing examples of how a user's group password policy is determined using the above sample rules. In particular, the first three columns in this table identify representative group policies (for groups X, Y and Z) and how a composite group password policy results (in the fourth column) from an evaluation of the respective values in the manner described above. Evaluation of a User's Effective Password Policy A user's effective password policy is evaluated if -pwdPolicy is set to true in the global password policy entry. Other password policies, such as individual and group policy, may be permitted when global policy is disabled, but these policy rules preferably will have no effect on the user. The three kinds of password policies (individual, group and global) preferably are evaluated in this order (if they exist) while evaluating a user's effective password policy. When a password policy attribute is found in any of the password policy entries, preferably the evaluation of that attribute stops and the attribute value is used as part of the user's effective policy. In this implementation, not all attributes have to be defined in a password policy. If a given attribute is not defined in one password policy, then the next password policy in order is searched until the global password policy is evaluated. If the attribute is still absent from the global policy, a default value may be assumed. As a result, preferably the final effective password policy contains all attributes that pertained to a user's password. The attribute -pwdPolicyStartTime is set to the current system time when—pwdPolicy is turned to true. This can be done even if the global password policy entry is set to false. The -pwdPolicyStartTime values, however, preferably are not be used for effective policy evaluation unless the global policy is enabled. Once the global policy is enabled, the value of this attribute preferably is selected from a user's individual, then group, and then the global policy. Because -pwdPolicyStartTime exists in every active password policy, the start time of an individual policy, if it exists, will always override any other policy start time as the start time of the user's effective password policy. The all-or-none attribute selection rules for selecting attributes, such as pwdMinLength, as described in the above section, preferably are also applied to a user's effective password policy evaluation. FIG. 11 is a table showing several examples of how effective password policies are determined. In particular, each of the first three columns include respective individual, group and global password policies, and the fourth column illustrates the effective password policy that results from the evaluation of the individual, group and global policies in the manner described above. Evaluation of a Group's Effective Password Policy The effective password policy of a group entry preferably is calculated by merging the group's password policy attributes with those in the global password policy with the group policy attributes taking precedence. This effective policy can be queried by using an extended operation. Interaction with other Directory Components During a bind operation, if the global password policy is enabled, the bind user's individual password policy is searched first. Then, based on the password policy group entries, the bind user's group policy can be determined once the user's group membership has been resolved. Together with the global password policy, the user's effective policy can be determined at this time. This effective policy controls if the bind user can be authenticated. Once the user is authenticated, the effective policy preferably is stored in a connection structure for later use. Preferably, the evaluation process takes place in a pre-bind process routine that can be called by the RDBM backend as well as by other bind plug-ins, such as DIGEST-MD5 pre-bind plug-in, to determine the authenticity of a user. For any operation that is used to add or modify a password attribute including an extended operation, if the updated entry is different than the bind entry, the updated entry's effective password policy is evaluated just like the one for the bind entry, and it is stored in an RDBM request structure; otherwise, the bind entry's effective policy stored in the connection structure will be used. The effective policy is the one that decides if the password update operation is allowed. For a modify operation modifying password attributes, such as resetting a password and unlocking a user account, if the bind user is a password administrator, no effective password policy evaluation will take place for the target user. This means a password administrator can ignore the target user's password policy when modifying password attributes associated with the above two actions. If a password administrator modifies his or her own password, however, the administrative password policy defined in the configuration file is used to make sure the passwords of the administrative users are properly modified. In a distributed directory environment, a backend server may not be able to locate all the group entries to which a user belongs locally on the server. Without the group entries, information such as the password policy DN of a group cannot be found, and therefore, a user's effective password policy cannot be evaluated. To address this, the proxy server will send to the backend server a list of password policy DNs that apply to the user in the format of an LDAP control (e.g., a Group Password Policy DN control). In other words, for add, modify, compare and extended operations (such as effective password policy extended operation) a list of password policy DNs is expected in the request protocol from a proxy server. Based on the received password policy DNs, a backend server then is able to evaluate the effective password policy for the target user. In the alternative, the group entries reside in each backend servers to ensure the correct evaluation of a user's/group's effective password policy. Thus, according to the above-described feature, password policy can be configured on per user, per group, or at the system wide (global) level. Multiple password policy definitions can apply to a single user, and the definitions can be distributed across different servers. Password policy evaluation cannot be done at a single server level when the data is distributed. Instead, the proxy server must work with the backend servers to determine the complete effective password policy and to enforce that policy. As described, typically there are two required steps to password policy enforcement when multiple password policy definitions apply to a single user. The first step is to determine the effective policy. The second step is to have the effective password policy available when enforcing the policy. A third step (which is optional) reduces overhead and improves performance by minimizing the number of operations where policy information is needed for enforcement. In the embodiment illustrated above, the proxy server collects all the policy information that applies to a given user and combines it to determine the effective password policy. To this end, the proxy server first collects the policy definitions that apply to the target user. The proxy server then collects all the policy definitions that apply to the groups to which the target user is a member. To perform this step, the proxy server performs a search for the user's entry requesting the policy attribute. A search is then done for the policy entry. The proxy server then performs a group evaluation extended operation to determine the user's group membership. It passes along a control to indicate that, in addition to group membership, each policy definition associated with the group should also be returned. This control should be sent to each partition in the distributed directory. The proxy server also collects a global level policy. Finally, the proxy server combines the policies to determine the effective password policy. This can be done by the proxy server using a local algorithm, or it can done via an extended operation to a backend server. In either case, the input would be all the policies defined (individual, group and global), and the output is the effective policy. Examples of this process are shown in FIG. 11. Preferably, the proxy server determines the effective policy and passes the policy information to the target servers. Preferably, the policy is supplied on the operations where policy definitions are needed. The proxy server sends the effective policy information in a control on all needed operations. Variants In a distributed directory environment the proxy server establishes connections to the backend servers using an administrative identity. Operations are performed on behalf of the requesting client by using a proxy authorization control. When the backend servers get the proxy authorization control, they look up the password policy to determine if lockout or must change is required for the user. This means that policy information would be required for every operation. This is sometimes inefficient and can be avoided. In particular, after a bind request the proxy server has already determined if lockout or must change is required for the user. The proxy server needs a way to communicate to the backend server that password policy checking can be skipped. According to an optimization, a skip password policy control is used to communicate this with the backend servers. Preferably, only administrators are allowed to send this control, although this is not a limitation. Preferably, every operation sent to a backend server either has the skip password policy control, or the effective password policy control. Typically, the effective password policy control is needed on bind operations, on any modify operation done to a password, and on the pre- and post-bind password policy extended operations used for external binds in a distributed directory. Another alternative is to implement partially distributed policy information. According to this feature, policy definitions are stored in a (e.g., cn=-policies) subtree that is then replicated across all servers in the system. By doing this, the step of collecting the actual policies may be avoided. Instead, the proxy server only needs to collect the policy DNs that apply to the target user. Then, the policy DNs are sent on the subsequent operations, and the evaluation and enforcement is done on the backend server. The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, and the like. Furthermore, as noted above, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD. While the above describes a particular order of operations performed by certain embodiments of the invention, it should be understood that such order is exemplary, as alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, or the like. References in the specification to a given embodiment indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Finally, while given components of the system have been described separately, one of ordinary skill will appreciate that some of the functions described may be combined or shared in given instructions, program sequences, code portions, and the like.	G	60G06	161G06F	17	00
11888597	US20080046846A1-20080221	System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization	ACCEPTED	20080207	20080221	[]	G06F1750	["G06F1750"]	7886262	20070801	20110208	716	132000	98137.0	TAT	BINH	[{"inventor_name_last": "Chew", "inventor_name_first": "Marko P.", "inventor_city": "Palo Alto", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Yang", "inventor_name_first": "Yue", "inventor_city": "Cupertino", "inventor_state": "CA", "inventor_country": "US"}]	A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication process compliance analysis tools. The modification of layout is performed adaptively and iteratively to make an IC layout less susceptible to yield issues while maintaining design rule correctness and minimal circuit performance impact.	1. A method of improving the manufacturing yield of integrated circuit comprising the steps: receiving a plurality of integrated circuit layout elements; constructing and allocating a plurality of position variables to a plurality of layout elements, wherein position variables represent the location of edges or points of the plurality of layout elements; constructing a constraint system using the positional variables, wherein the constraints represent relationships of edges or points of the plurality of layout elements; constructing a fabrication process compliance analysis undesirability function with inputs consisting of position variables; establishing an objective function composed of fabrication process compliance analysis undesirability function and weighted sum of plurality of position variables; solving the optimization problem of minimizing the objective function subject to the constraint system requirements; and generating new layout from the new position variable values. 2. The method of claim 1, wherein the integrated circuit layout is organized in a hierarchical manner consisting of master cells, plurality of instances of master cells, and plurality of instance arrays of master cells. 3. The method of claim 2 further comprising the step of: constructing and allocating a plurality of position variables to a plurality of master cell instances and to a plurality of instance arrays of master cells. 4. The method of claim 1, wherein the step of constructing the fabrication process compliance analysis undesirability function incorporates lithographic considerations. 5. The method of claim 1, wherein the step of constructing the fabrication process compliance analysis undesirability function incorporates critical area considerations. 6. The method of claim 1, wherein the step of constructing the fabrication process compliance analysis undesirability function incorporates chemical mechanical polishing related considerations. 7. The method of claim 1, wherein the step of constructing the fabrication process compliance analysis undesirability function incorporates weighted sum of lithographic, critical area and chemical mechanical polishing considerations. 10 8. A system of improving the manufacturing yield of integrated circuit comprising the steps: means of receiving a plurality of integrated circuit layout elements; means of constructing and allocating a plurality of position variables to a plurality of layout elements, wherein position variables represent the location of edges or points of the plurality of layout elements; means of constructing a constraint system using the positional variables, wherein the constraints represent relationships of edges or points of the plurality of layout elements; means of constructing a fabrication process compliance analysis undesirability function with inputs consisting of position variables; means of establishing an objective function composed of fabrication process compliance analysis undesirability function and weighted sum of plurality of position variables; means of solving the optimization problem of minimizing the objective function subject to the constraint system requirements; and means of generating new layout from the new position variable values. 9. The system of claim 8, wherein the integrated circuit layout is organized in a hierarchical manner consisting of master cells, plurality of instances of master cells, and plurality of instance arrays of master cells. 10. The system of claim 9 further comprising the step of: means of constructing and allocating a plurality of position variables to a plurality of master cell instances and to a plurality of instance arrays of master cells. 11. The system of claim 8, wherein the means of constructing the fabrication process compliance analysis undesirability function incorporates lithographic considerations. 12. The system of claim 8, wherein the means of constructing the fabrication process compliance analysis undesirability function incorporates critical area considerations. 13. The system of claim 8, wherein the means of constructing the fabrication process compliance analysis undesirability function incorporates chemical mechanical polishing related considerations. 14. The system of claim 8, wherein the means of constructing the fabrication process compliance analysis undesirability function incorporates weighted sum of lithographic, critical area and chemical mechanical polishing considerations.	<SOH> BACKGROUND OF THE INVENTION <EOH>The electronic circuit of an integrated circuit (“IC”) consists of connected components such as transistors, diodes and resistors. The description of the components and their interconnections is called a netlist. Each component is mapped to one or more layout objects that are two-dimensional geometrical objects such as, but not limited to, rectangles, polygons, and paths. Two-dimensional objects also exist for the connections among the components. In turn, these layout objects are used to define regions within a semiconductor die, which will receive different processing steps such as, but are not limited to, dopant implants to produce N-type or P-type regions and thin oxidation regions for transistor gate areas. Typically, layout objects are assigned to specific layers associated with an IC fabrication step such as P-implant or poly deposition. The collection of two-dimensional objects for a given layer is called a layout mask and the collection of layout masks for all layers is called a layout mask data. Every layout object must satisfy so called design rules that specify geometrical requirements for each object as well as the relationship of an object to other objects. Examples of such requirements include, but are not limited to, such items as minimum width and minimum spacing from one object to another object. The IC fabrication process is such an extremely complex process so that the sequence of IC fabrication process steps indicated by an IC mask data might not produce the semiconductor structures with sufficient accuracy to assure correct circuit operation. If the circuit performance of a fabricated IC does not meet the required product specifications, then the IC must be discarded. If there are too many discard ICs, then the yield or fraction of good IC will be low and results in higher overall cost for the good ICs. Any issue with the various steps in IC fabrication procedure could cause the resulting semiconductor structures to deviate sufficiently to cause the fabricated IC to be bad. Examples of important process steps include, but are not limited to lithography, random defect control, and chemical mechanical polishing (“CMP”). Fabrication process engineers are tasked with ensuring that the resulting fabricated semiconductor structures are accurate as possible as in order to maximize IC yield. Starting at the 130 nm process node and continuing to the current process nodes, the interaction of process and design has made this task much more difficult. This is because it is no longer possible to have a fabrication process recipe that produces the optimal yield for all possible mask layout data. Since it is very difficult to tune fabrication process recipe for each layout mask data, the trend is to adjust mask layout data to ensure the highest yield for a given fabrication process recipe. IC fabrication process software simulators can model the various steps of an IC fabrication procedure. Traditionally, fabrication process engineers have used these process simulators to guide the development of new fabrication process recipes. Due to the negative effect of the interactions between mask layout and process on IC yield, the use of process simulation has expanded beyond process engineers to mask data preparation and design engineers(“design engineers”). These engineers use process simulations to guide mask layout data creation so that mask data is more compatible with a given process recipe. In effect, mask data is modified in order to increase the eventual fabricated IC yield. Examples of process simulation software increasingly used by design engineers include, but are not limited to lithography simulation, CMP modeling, and defect sensitivity simulations. The results of these process simulations are used to identify layout configurations with potential yield limiting manufacturing issues and to adjust the mask layout correspondingly. The next sequence of discussions describe several examples of how process simulations are used to modify the mask layout data. Those versed in the art will recognize that the descriptions are not exhaustive and could be easily extended to other scenarios where mask layout data is adjusted to avoid manufacturing issues using process simulation results.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a system and a method of maximizing IC manufacturing yield with IC fabrication process simulation driven layout optimization. An IC design layout is adaptively and iteratively modified in a layout optimization system consisting of a layout fabrication process compliance analysis (“LFPCA”) composed of IC fabrication process simulators and layout process compliance analysis, along with a layout optimization step. It is an object of the present invention to utilize the LFPCA information during the layout optimization step to reduce the design layout susceptibility to LFPCA identified issues so as to improve manufacturing yield. It is a further object of the present invention to produce an optimized layout which is design rule correct as well as being layout versus schematic (LVS) correct with fewer fabrication process issues than the original layout. It is another object of the present invention to allow an optimized layout to have the same design hierarchy as that of the starting layout. In a hierarchical layout, the potential exists for LFPCA issues to be resolved by adjusting instance locations rather than layout edges during the layout optimization step of the present invention. It is a further object of the present invention to have a optimized layout with none or slight perturbation to design performance and other metrics including, but not limited to, area and timing from the starting layout. These and other objects, features and advantages in accordance with the present invention are provided by a system and a method of maximizing manufacturing yield by using automatic layout optimization driven by LFPCA analysis.	CLAIM OF BENEFIT TO PROVISIONAL APPLICATION This patent application claims the benefit of the earlier filed U.S. Provisional Patent Application entitled “System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization”, having Ser. No. 60/838,023, and filed Aug. 15, 2006. TECHNICAL FIELD OF APPLICATION This invention relates generally to the design and manufacture of integrated circuitry and more particularly to a system and a method of maximizing manufacturing yield by using layout optimization driven by integrated circuit fabrication process simulation. BACKGROUND OF THE INVENTION The electronic circuit of an integrated circuit (“IC”) consists of connected components such as transistors, diodes and resistors. The description of the components and their interconnections is called a netlist. Each component is mapped to one or more layout objects that are two-dimensional geometrical objects such as, but not limited to, rectangles, polygons, and paths. Two-dimensional objects also exist for the connections among the components. In turn, these layout objects are used to define regions within a semiconductor die, which will receive different processing steps such as, but are not limited to, dopant implants to produce N-type or P-type regions and thin oxidation regions for transistor gate areas. Typically, layout objects are assigned to specific layers associated with an IC fabrication step such as P-implant or poly deposition. The collection of two-dimensional objects for a given layer is called a layout mask and the collection of layout masks for all layers is called a layout mask data. Every layout object must satisfy so called design rules that specify geometrical requirements for each object as well as the relationship of an object to other objects. Examples of such requirements include, but are not limited to, such items as minimum width and minimum spacing from one object to another object. The IC fabrication process is such an extremely complex process so that the sequence of IC fabrication process steps indicated by an IC mask data might not produce the semiconductor structures with sufficient accuracy to assure correct circuit operation. If the circuit performance of a fabricated IC does not meet the required product specifications, then the IC must be discarded. If there are too many discard ICs, then the yield or fraction of good IC will be low and results in higher overall cost for the good ICs. Any issue with the various steps in IC fabrication procedure could cause the resulting semiconductor structures to deviate sufficiently to cause the fabricated IC to be bad. Examples of important process steps include, but are not limited to lithography, random defect control, and chemical mechanical polishing (“CMP”). Fabrication process engineers are tasked with ensuring that the resulting fabricated semiconductor structures are accurate as possible as in order to maximize IC yield. Starting at the 130 nm process node and continuing to the current process nodes, the interaction of process and design has made this task much more difficult. This is because it is no longer possible to have a fabrication process recipe that produces the optimal yield for all possible mask layout data. Since it is very difficult to tune fabrication process recipe for each layout mask data, the trend is to adjust mask layout data to ensure the highest yield for a given fabrication process recipe. IC fabrication process software simulators can model the various steps of an IC fabrication procedure. Traditionally, fabrication process engineers have used these process simulators to guide the development of new fabrication process recipes. Due to the negative effect of the interactions between mask layout and process on IC yield, the use of process simulation has expanded beyond process engineers to mask data preparation and design engineers(“design engineers”). These engineers use process simulations to guide mask layout data creation so that mask data is more compatible with a given process recipe. In effect, mask data is modified in order to increase the eventual fabricated IC yield. Examples of process simulation software increasingly used by design engineers include, but are not limited to lithography simulation, CMP modeling, and defect sensitivity simulations. The results of these process simulations are used to identify layout configurations with potential yield limiting manufacturing issues and to adjust the mask layout correspondingly. The next sequence of discussions describe several examples of how process simulations are used to modify the mask layout data. Those versed in the art will recognize that the descriptions are not exhaustive and could be easily extended to other scenarios where mask layout data is adjusted to avoid manufacturing issues using process simulation results. Lithography One process simulation increasingly being used by design engineers is lithography simulation. The lithography step is used to transfer mask patterns onto a semiconductor substrate. Any loss of fidelity on the transferred pattern from that of the mask may result in decreased in IC yield. The accuracy of the translation depends on factors including, but not limited to, the optical distortion that depends on layout feature sizes relative to lithography wavelength; the distortion introduced by resist development; the distortion introduced by resist etching process. In modern day lithography, the shrinking of feature size has by far outpaced the shrinking of wavelength of light sources used in lithography. For current process nodes of 90 nm and below, the distortion introduced by lithography imaging is becoming a dominant factor in accuracy in the translation of design data to wafer images. Various technologies have been developed to solve this problem, including optical proximity correction (“OPC”) and use of phase shift mask (“PSM”). OPC is performed on design data by adding/removing features to layout geometries, in order to compensate the distortion introduced by lithography imaging. PSM is performed by arranging out-of-phase of light waves at the alternative sides of critical dimension (“CD”) features, in order to enhance image printing of these features. The various techniques to improve the printability is collectively called resolution enhancement technique (“RET”) and includes, but is not limited to, OPC, PSM, and line width biasing. There are two major categories of OPC: rule-based and model-based. Rule-based OPC is performed based on certain preset rules on how OPC features are constructed. It has the advantage of short run time. However, since it does not consider design context of layout geometries, its functionality and effectiveness is very much limited. Model-based or simulation-based OPC is performed based on lithography simulation of layout geometries and features, so it is much more accurate and effective. Prior development of several fast lithography simulators makes model-based OPC practical. One prior art performs OPC iteratively in order to ensure simulation consistent with changes of OPC features; another prior art performs so called aggressive OPC by directly performing inverse transform from desired target printed shapes. The results and performance of model-based OPC depends on certain “recipes” used including, but not limited to, lithography simulation approach and edge fragmentation methodology. This makes it necessary to verify the results of OPC using so called “OPC verification” tools. OPC verification tools checks how accurately post-OPC layout data print on wafer during lithography process and whether disastrous problems such as, but not limited to, opens and shorts happen to images printed on wafers. OPC verification is performed at one process corner or across a process window. OPC verification tools may find OPC violations that happen due to reasons such as, but not limited to, design patterns beyond usage under which OPC recipes are developed; limitation of OPC recipes on various process corners; and certain design patterns are inherently difficult to be adjusted for OPC. While it is possible to fix OPC violations that are due to limited OPC recipes or incomplete design pattern coverage of OPC recipes through use of specifically design OPC recipes; there are certain OPC violations due to certain design patterns that cannot possibly be fixed by modifying OPC process recipes. OPC violations are normally called “hotspots”; the hotspots that cannot be fixed by adjusting OPC recipes are called “OPC hard hotspots” in design layout. “OPC hard hotspots” can only be fixed by adjusting pre-OPC design layout. For IC manufacturing process nodes prior to 90 nm process node, the occurrences of OPC hard hotspots are rare. What are identified as “OPC hotspots” with rule-based OPC are likely fixable through use of model-based OPC. Since imaging distortion of layout geometries introduced by lithography does not greatly depend on surrounding geometries; design layout that passes design rule check (“DRC”) are expected to be free of OPC hotspots by using correctly tuned OPC recipes, with very few or none exceptions. For IC manufacturing process nodes starting from 90 nm process node, the image distortion of layout geometries introduced by lithography depends at a higher degree on its surrounding layout geometries. The implication of this fact is that, in order to generate layouts that have high manufacturing yield, IC fabrication foundries have to provide numerous context-dependent physical design rules that are much more complex than what have been used so far, especial for CD layers. Context-dependent physical design rules not only put a great amount of burden on mask layout designers and layout tools; they are also inherently incomplete. There is virtually no way to capture all possible design patterns with various contexts in a reasonable number of design rules, in the format that may be understood and suitable for use by mask layout designers and layout tools. Chemical Mechanical Polishing Another example of process simulation increasingly being used is chemical mechanical polishing (CMP) process simulation to predict such effects as interlayer dielectric(“ILD”) variations. The ILD variations are important since these variations could cause a circuit's interconnection parasitic capacitances to vary significantly from design specifications and results in circuit performances not meeting the design specifications. The minimum and maximum density design rules are one attempt to mitigate too wide a range of ILD variations. In this approach, dummy geometries called fill are inserted into empty regions in a mask layout in order to get the preferred range of pattern density values. One of the issues with this technique is that a mask layout with a pattern density value within the allowed range may still have ILD variations significant enough to cause circuit performance issues. This is because ILD variations are mostly localized phenomena involving layout geometry and its neighbors while pattern density is computed over a much larger layout region involving much more layout geometries. CMP process simulators model the ILD variations for a mask layout. These ILD variations can then be fed back to the design phase to make adjustments to mitigate effects on circuit performance. Without the ILD feedback results, the IC circuit designer would be forced to assume overly conservative assumptions that could result in excessive layout area penalty and eventually higher product cost. Even with ILD variation feedback, IC circuit designers would have to accommodate the worst-case ILD variations reported by CMP simulators. A better solution would be to guide the mask layout generation to avoid widely divergent ILD variations. Particle Defect Density Control Particle defects are either missing or extra materials caused by particles during fabrication process that could cause such circuit issues as, but not limited to, opens and shorts in a fabricated IC. Defects are random phenomenon that is characterized by a defect density distribution. The lower the defect density distributions for a given fabrication process, the lower the probability of defects causing issues in the fabricated circuits. Different mask layout data have different sensitivities to particle defects. These sensitivities are a function of such characteristics as, but not limited to, spacing between layout geometries and layout geometry widths. The larger the spacing between geometries, the less susceptible layout geometries are to defects causing electrical shorts. Likewise, the larger a geometry's width, the less susceptible the geometry to the occurrence of opens due to missing material defects. There are several techniques to gauge the sensitivities of a mask layout to particle defects. One method is to utilize Monte Carlo sampling techniques to inject a sample population of defects into a mask layout and evaluate the occurrence of shorts and opens in the actual mask layout. Another method is to use a critical area analysis(“CAA”) of the mask layout to generate statistics of susceptibility for particles of given size and type. The CAA results are then weighed by the defect density distribution to generate the defect sensitivity for the given mask layout. For any method, a mask layout with a lower defect susceptibility would have a higher probability of higher IC yield. The standard method of decreasing the susceptibility of a mask layout to defects is increasing the spacing between geometries (“wire spreading”) for extra particle defects and increasing layout geometry widths for missing particle defects. In either scenario, the mask layout must be modified to reduce the sensitivity for the specified defect density distribution. SUMMARY OF THE INVENTION The present invention provides a system and a method of maximizing IC manufacturing yield with IC fabrication process simulation driven layout optimization. An IC design layout is adaptively and iteratively modified in a layout optimization system consisting of a layout fabrication process compliance analysis (“LFPCA”) composed of IC fabrication process simulators and layout process compliance analysis, along with a layout optimization step. It is an object of the present invention to utilize the LFPCA information during the layout optimization step to reduce the design layout susceptibility to LFPCA identified issues so as to improve manufacturing yield. It is a further object of the present invention to produce an optimized layout which is design rule correct as well as being layout versus schematic (LVS) correct with fewer fabrication process issues than the original layout. It is another object of the present invention to allow an optimized layout to have the same design hierarchy as that of the starting layout. In a hierarchical layout, the potential exists for LFPCA issues to be resolved by adjusting instance locations rather than layout edges during the layout optimization step of the present invention. It is a further object of the present invention to have a optimized layout with none or slight perturbation to design performance and other metrics including, but not limited to, area and timing from the starting layout. These and other objects, features and advantages in accordance with the present invention are provided by a system and a method of maximizing manufacturing yield by using automatic layout optimization driven by LFPCA analysis. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a computing environment used in some embodiments of the present invention. FIG. 2 illustrates a general flow 200 of fabrication driven layout optimization of the present invention. FIG. 3 illustrates an LFPCA flow in a lithography process simulation embodiment of the present invention. FIG. 4 illustrates a CMP process simulation based embodiment of the present invention. FIG. 5 illustrates a particle defect process simulation based embodiment of the present invention. FIG. 6 illustrates a generalized LFPCA flow for some embodiment of the present invention. FIG. 7 illustrates an exemplary implementation of representing the location of an edge with variables in a flat design layout. FIGS. 8-9 illustrates an exemplary implementation of a transform at one level of hierarchical design. FIG. 10 illustrates how gradients of position variables of LUF are approximately obtained from some embodiment of the current invention. FIG. 11 illustrates a sub-design containing two edges. FIG. 12 illustrates two instances of the sub-design of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This invention relates to an integrated circuit mask layout optimization system and an integrated circuit mask layout optimization method, and more to a methodology for maximizing manufacturing yield by using automatic layout optimization driven by IC fabrication process simulation and layout fabrication process compliance analysis. The present invention describes a system and a method of representing layout using a set of variables; formulating metrics of fabrication process quality which is directly correlated to manufacturing yield through LFPCA; identifying a function of sensitivity of each variable representing design to the metrics of LFPCA quality and formulating an optimization problem to maximize manufacturing yield by changing the variables representing a design mask layout data within predefined ranges and within the constraints imposed by design rules and other requirements; iterating the procedure in order to converge to a final optimized result. In the preferred embodiment, a method of formulation and a method of maximizing manufacturing yield by using layout optimization driven by IC fabrication process simulation and layout fabrication process compliance check is presented. In the following description, numerous details are set forth for purpose of explanation. However, one of skill in the art will realize that the invention may be practiced with the variations of these specific details. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. Computing Environment FIG. 1 illustrates a block diagram of the computing environment that one embodiment of the present invention is implemented. Even though the computer system is described with specific components and architecture for illustration, it should be understood that the present invention might be implemented in several other types of embodiments. For example, the invention can be implemented on single computer with a processor chip containing 2 or more processor cores with each core containing additional hardware to maintain state of two or more threads of execution. In addition, each component can be implemented as a combination of one or more of hardware, software and firmware, even though many features of the present invention are described herein as being implemented in software. The computing environment 100 may contain one or more components such as a communication fabric 110, random access memory (RAM) 120, central processing unit (CPU) 130, read only memory 140 (ROM), secondary memory (Storage) 150, output devices 160, input Devices 170, network interface 180. All the components may communicate with each other over communication fabric 110. The communication fabric 110 collectively represents all systems, peripherals, chipset buses and all other communication pathways that can connect the components of the computing environment 100. The components of FIG. 1 are described below in further detail. CPU 130 retrieves the instructions and data to process in order to execute the processes of this invention from the various storage components of computing environment 100. The ROM 140 stores the static instruction and data not modified during normal operation and are needed by CPU 130 and any other component of the computing environment 100. Read-write memory (RAM) 120 is a volatile storage that requires power to be supplied to store the instructions and data. Storage 150 is nonvolatile storage that doesn't need power to store instructions and data. In some embodiments, storage 150 use fixed mass-storage devices such as disk drives. Other embodiments use removal mass-storage devices such as removable disk drives. The RAM 120 stores some of the instructions and data that the CPU 130 needs. In some embodiments, the invention's processes are stored in the CPU 130, RAM 120, ROM 140, and/or storage 150. The input device 170 enables the user to issue commands to the computing environment. Examples of an input device 170 include but are not limited to, keyboards, mouse, and/or tablet and stylus. The output device 160 is used to display images generate by the computing environment such as but not limited to optimized integrated circuit mask layout. Network interface 180 may be implemented using protocols such as TCP/IP, ATM and/or Ethernet. In this manner, the computer can be a part of a network of computers (such as a local area network (“LAN”), a wide area network (“WAN”), or an Intranet) or a network of networks (such as the Internet). Any, some or all of the components of computing environment 100 may be used in conjunction with the invention. However, one of ordinary skill in the art would appreciate that any other system configuration may also be used in conjunction with the present invention. As noted above, CPU 130 may retrieve the software instructions, and execute the instructions to provide various features of the present invention. The features of the present invention are described below in further details. General Flow The present invention provides a system and a method of maximizing IC manufacturing yield with IC fabrication process simulation driven layout optimization. An IC design layout is adaptively and iteratively modified in a layout optimization system consisting of a layout fabrication process compliance analysis (“LFPCA”) composed of IC fabrication process simulators and layout process compliance analysis, along with a layout optimization step. It is an object of the present invention to utilize the LFPCA information during the layout optimization step to reduce the design layout susceptibility to LFPCA identified issues so as to improve manufacturing yield. It is a further object of the present invention to produce an optimized layout which is design rule correct as well as being layout versus schematic (LVS) correct with fewer fabrication process issues than the original layout. It is another object of the present invention to allow an optimized layout to have the same design hierarchy as that of the starting layout. In a hierarchical layout, the potential exists for LFPCA issues to be resolved by adjusting instance locations rather than layout edges during the layout optimization step of the present invention. It is a further object of the present invention to have a optimized layout with none or slight perturbation to design performance and other metrics including, but not limited to, area and timing from the starting layout. FIG. 2 illustrates a general flow 200 of IC fabrication process simulation driven layout optimization described in the present invention. The starting layout 202 is analyzed at the layout fabrication process compliance analysis (“LFPCA”) step 204. At 206, if there are no LFPCA issues, the process continues to 216 where the process terminates. If there are LPCA issues, the process continues to 208 where formulation of a layout optimization problem to resolve the LPCA issues are constructed using the results of LFPCA analysis as well as design and/or manufacturing layout rules (“design rules”) 218. Layout rules include such rules, but are not limited to, the traditional rules included in design rule documents. The process continues to 210 where a layout optimization problem from 208 is solved to produce the optimized layout 212. At 214, the process determines if the maximum number of iterations or other limits have been reached and returns to 204 with the modified layout if not. If the maximum iterations or other limits have been reached, the process continues to 216 and terminates. FIG. 3 illustrates an embodiment of a lithography simulation based LFPCA process 300 for the present invention. At 304, the process performs resolution enhancement (“RET”) procedure on the mask layout 302 to produce the post RET layout 308. The RET procedure include such operations such as, but not limited to, construction of OPC features and PSM phase assignments. The lithography simulation 310 accepts the post-RET layout 308 and its results are analyzed at 312 for any RET issues. FIG. 4 illustrates an embodiment of a CMP process simulation based LFPCA process 400 for the present invention. At 404, the process inserts dummy fill geometries on mask layout 402 to produce the post fill layout 408 that has the required pattern density range of values. The ILD variation analysis 410 accepts the post fill layout 408 and produces data used in the ILD variation analysis step 412. FIG. 5 illustrates an embodiment of a defect density based simulation based LFPCA process 500 for the present invention. At 504, the process performs a critical area analysis of the mask layout 502. FIG. 6 illustrates an embodiment of a generalized fabrication process simulation LFPCA process 600 for the present invention. At 604, the process takes as input the mask layout 602 to perform all the operations such as, but not limited to, construction of OPC features, geometry phase assignments for PSM, insertion of sub-resolution assist features (“SRAF”) and insertion of dummy fill geometries for pattern density requirements and produces the post process mask layout 608. At 610, the process run various fabrication process simulations such as, but not limited to, lithography simulations (“litho-simulation”), litho-simulation followed by etch models for the actual semiconductor materials such as metal and poly, ILD variation analysis, and critical area analysis. The results of the various process simulations are analyzed at step 612 for any layout fabrication process compliance issues. Layout Optimization Problem Formulation The layout optimization procedure requires a representation for a mask layout data, a collection of constraints to be applied to the mask layout data, and an objective cost function to be optimized. The constraints include such items as, but are not limited to, design rule requirements, circuit requirements, connectivity and preservation of hierarchical design integrity. The mask layout data can either be flat or hierarchical. Mask Layout Data Representation A layout optimization will adjust edges of the initial mask layout data to produce an optimized mask layout data. Consequently, a representation of mask layout data edges is a required component of a layout optimization system. FIG. 7 illustrates an exemplary implementation of representing the location of an edge with variables in a flat design layout. It is recognized that in the integrated circuit layout, the angles of all edges are multiples of 45 degrees. Each edge is represented by an angle, and a position variable. In cases when the edge is horizontal as edge 702, the angle is 0 or 180 degrees depending on the selection of the starting end point, the position variable is the intersection of the edge or its extension and Y-axis; in cases when the edge is vertical as edge 704, the angle is 90 or 270 degrees depending on the selection of the starting end point, the position variable is the intersection of the edge or its extension and X-axis; in cases when the angle is 45 or 225 degrees as edge 706 depending on the selection of the starting end point, the position variable is the intersection of the edge or its extension and Y-axis; in cases when the angle is 135 or 315 degrees as edge 708 depending on the selection of the starting end point, the position variable is the intersection of the edge or its extension and Y-axis. A corner in a mask layout is recognized as an artificial product of the two edges that intersects at the corner. It is represented by the variables defining the two edges. The formulation depends on the orientation of the two edges. A shape in a mask layout database is represented by the location of the vertices defining the shapes. There are, of course, numerous methods of representing layout geometries as long as they are canonical. In a hierarchical design, each leaf design, which has no design descendants, has a chain of design ancestors. Each link of the ancestry carries a transform, which reflects how child design at that level is positioned in parent design. Representation of layout geometries at each design, is then transformed recursively upwards till it gets to top design level. FIG. 8-9 illustrates an exemplary implementation of a transform at one level of hierarchical design. In FIG. 8, a child design instance 804 is positioned inside its parent design 802. The transform is an offset (x0, y0) with no rotation. A variable x representing a geometrical entity is then transformed to: x+x0 in the framework of parent design. A variable y representing a geometrical entity is then transformed to: y+y0 in the framework of parent design. In FIG. 9 , a child design instance 908 is positioned inside its parent design 906. The transform is an offset (x0,y0) with a clockwise rotation of 90 degrees. A variable x representing a geometrical entity is then transformed to: x+y0 in the framework of parent design. A variable y representing a geometrical entity is then transformed to: −y+x0 in the framework of parent design. There are, of course, numerous methods of representing layout geometries in hierarchical design as long as they are canonical. In a flat layout, an edge of a geometrical entity is normally represented by one position variable for the actual edge itself in some embodiments of the present invention. In a hierarchical layout, an edge of a geometrical entity is can be represented by a combination of position variables, as in an example shown in FIGS. 8-9. An important implication for hierarchical design layout is that a layout optimization has the possibility of resolving LFPCA issues just by adjusting instance positions. Cost Function Formulation The present invention requires an LFPCA system produce a value for undesirability of an LFPCA issue. In one embodiment, a lithography simulation based LFPCA could quantify the quality “lithography friendliness” (“LLF”) as the weighted sum of, among others, a function of square of edge placement error (“EPE”) of relevant edges a function of mask enhancement error factor(“MEEF”) of relevant edges a function of normalized image log slope(“NILS”) of the relevant edges. a function of depth of focus (“DOF”) of the relevant edges. LLF litho = - C EPE  ∑ i  func EPE  ( ( EPE i ) 2 ) - C NILS  ∑ i  func NILS  ( NILS i ) - C MEEF  ∑ i  func MEEF  ( MEEF i ) - C DOF  ∑ i  func DOF  ( DOF i ) In another embodiment, a CMP process simulation based LFPCA system could quantify the ILD variations in a similar fashion as a function of the fabricated ILD thickness from the target ILD thickness. VARCMP=ΣfuncILD(ILDsimulated,ILDspec) In yet another embodiment, a critical area analysis based LFPCA system is perhaps the simplest since it only has to integrate critical area with the defect density distribution to get the expected defect limited yield number. Yielddefect=∫criticalArea(rd)pdf(rd)drd where criticalArea(rd)—layout regions sensitivity to defect of size rd pdf(rd)—defect size probability density function Some embodiments of the present invention use a generalized LFPCA undesirability function with various components for specific fabrication process LFPCA issues for various mask layout data configurations. Since the mask layout data can be represented by a vector {circumflex over (v)}=(v1, v2, . . . , vn) for edges and instances as illustrated in FIGS. 7-9, an LFPCA undesirability function (“LUF”) is a function of the mask layout. LUF({circumflex over (v)})=k1·LLFlinho({circumflex over (v)})+k2·VARCMP({circumflex over (v)})+k3·Yielddefect({circumflex over (v)})+ Some embodiments of the present invention use LUF as one of the components of the objective cost function for the layout optimization step. In general, the LFPCA procedure is a very complex system involving modeling one or more IC fabrication process steps followed by similarly complex analysis. Some embodiments of the present invention utilize an approximation of an LUF function using response surface modeling (“RSM”) that those versed in the arts will recognized. When all geometries are represented by polynomials (usually linear combinations) of position variables vi illustrated in FIGS. 7-9 exemplarily, LUF may be viewed as an expansion on these variables: LUF = LUF  \| v i = v i  ( 0 )  ∀ i  + ∑ i  ∂ LUF ∂ v i  ( v i - v i  ( 0 ) ) + ∑ i  ∂ 2  LUF ∂ v i 2  ( v i - v i  ( 0 ) ) 2 + … In one embodiment of the present invention, if changes of all variables vi are limited to a reasonably narrow range, only the 1st order gradients are taken into consideration for the evaluation of LUF to be reasonably accurate, i.e. LUF = LUF  \| v i = v i  ( 0 )  ∀ i  + ∑ i  ∂ LUF ∂ v i  ( v i - v ) or Δ   LUF = ∑ i  ∂ LUF ∂ v i  Δ   v i Therefore, construction of LUF is equivalent to construction of the lower-order gradients of all position variables of LUF; it is equivalent to the 1st order gradients of all position variables of LUF, given all vi change within a reasonably narrow range. The advantage of using RSM techniques is that there is a plethora of literature on efficient methods of creating the models. This is especially true for specifying the running of the LFPCA analysis required to build LUF approximate models. Some embodiments utilize the two-level fractional factorial experimental design techniques popularized by Box, Hunter and Hunter. Other embodiments utilize other design of experiment techniques for more complex LUF approximations using such techniques, but not limited to, Latin hypercube and central composite sampling strategies. FIG. 10 illustrates how gradients of position variables of LUF are approximately obtained at certain values of position variables. By measuring LUF using process simulations, the value of variable vi are sampled around its current value x0. The value of LUF is measured at the sampled value of vi. Those versed in the arts will recognize that the sampling strategy is well covered in the design of experiment literature. Optimization Constraints The construction of constraints of the optimization problem is done by enforcing: 1) design constraints including, but not limited to, design area, timing, connectivity for LVS (layout versus schematics) correctness; 2) satisfaction of a set of physical design rules between layout geometries; 3) bounds of position variables due to design requirement limits or step size requirements. These are important for a modified design layout to maintain integrity as far as DRC (design rule correct) and LVS (layout versus schematics) clean, meet reasonable requirements, and to ensure the validity of the constructed optimization problem. After an optimization problem is solved, and an optimal or close to optimal solution is obtained, the design layout from which the optimization problem is constructed is modified by updating the locations of geometrical entities using the value of position values in the solution. As the flow illustrated in FIG. 2, the loop terminates when the modified design pass LFPCA, or certain criteria are met. The end result is a design layout that is modified from an existing layout. The DRC correct and LVS clean modified layout maximizes manufacturing yield with minimal IC design quality and performance impacts. Design Hierarchy Preservation Some embodiments of the present invention preserve the design layout hierarchy. In some cases, a sub-design representation is replicated as one or more instances within the layout hierarchy and presents an opportunity for some embodiments of the present invention to have layout optimization resolve LFPCA issues by adjusting instance locations rather than adjusting layout edges. In other embodiments, a single layout edge adjustment as part of the layout optimization step can resolve multiple LFPCA issues This is because an edge in a hierarchical design layout can be represented by two or more location variables as illustrated in FIGS. 8-9. One variable is associated with the edge within the sub-design while another variable describes the location of the instance of the sub-design. FIG. 11 illustrates a sub-design layout A (1100) containing edges e1 (1102) and e2 (1102) with location variables v0=(x0, y0) and V1=(x1, y1) respectively. The location variables v0 and v1 uniquely identifies edges within the layout 1100 and is adjusted by layout optimization process. FIG. 12 illustrates a layout 1200 that contains two instantiations of sub-design A at 1204 and 1214 respectively. The sub-design A instance 1204 has location variable v10=(x10,y10) and sub-design A instance 1214 has location variable v20=(x20,y20). The four edges 1202, 1206, 1212, and 1216 have position variables which are v0+v10, v1+v10, v0+v20, and v1+v20, respectively. Some embodiments of the present invention could have the layout optimization place a higher weight on adjusting position variables v10 and v20 of FIG. 12. A change in variable v10, for example, could result in changes in edges 1202 and 1206. Another embodiments of a layout optimization of the present invention could place a higher weight on adjusting variable associated only with edges so that sub-design changes are favored over adjustment of instance position variables. For example, a layout optimization embodiment of the present invention adjusting FIG. 12's v0 variable would change edges 1202 and 1212. These examples illustrate flexibility for layout optimization embodiment of the present invention in resolving LFPCA issues. This flexibility is a consequence of the present invention's approach to modeling the mask data layout as well as retaining the layout hierarchy. Although the description above contains many specificities, these should be not be construed as limiting the scope of the invention but merely providing illustrations of some of the presently preferred embodiments of this invention. Thus the scope of the invention should be determined by the appended claims and their equivalents, rather than by the examples given.	G	60G06	161G06F	17	50
11833018	US20080126318A1-20080529	Method and Apparatus for Remotely Monitoring a Social Website	ACCEPTED	20080514	20080529	[]	G06F15173	["G06F15173", "G06F1730"]	9858341	20070802	20180102	707	010000	66381.0	MITIKU	BERHANU	[{"inventor_name_last": "Frankovitz", "inventor_name_first": "Jason", "inventor_city": "Los Angeles", "inventor_state": "CA", "inventor_country": "US"}]	A computer method, apparatus, system and computer program product for remotely monitoring a social website includes monitoring user activity (events) and producing user activity data. The resulting data may be processed separately from the social website. The processed user activity data may be stored and information indicative of the data may be reported. Monitoring user activity may be in response to a call from a social website. Thus, a plurality of websites may be monitored and data from these websites may be normalized. Remotely monitoring a plurality of social websites allows the invention system to identify activity/data trends, such as individual or group user trends, or larger societal trends identifiable across the plurality of websites. The invention may monitor user activity in a substantially real-time manner or alternatively may store indicative user activity data for later processing. User activity data may also be encrypted/decrypted and/or authenticated to ensure data integrity.	1. A method to remotely monitor a social website, comprising: monitoring user activity on a remote social website, resulting in user activity data; processing the user activity data separate from the social website; storing the processed user activity data; and reporting information indicative of the processed user activity data. 2. The method according to claim 1 wherein monitoring user activity is in response to a call from the social website triggered by user activity at the social website. 3. The method according to claim 2 wherein the call is an API call. 4. The method according to claim 1 wherein monitoring includes polling a monitoring service installed on the remote social website periodically, aperiodically, or on an event driven basis. 5. The method according to claim 1 wherein the step of monitoring effectively logs or records user activity. 6. The method according to claim 5 wherein user activity data is represented in the form of a uniform resource locator (URL). 7. The method according to claim 1 wherein processing includes parsing the user activity data from at least one social website and normalizing the parsed user activity data. 8. The method according to claim 1 wherein storing includes storing the processed results in a centralized, searchable data store. 9. The method according to claim 1 wherein processing includes performing on-the-fly analysis of the user activity data. 10. The method according to claim 1 further including querying a classification service (CS) prior to displaying a requested web page at the social website, wherein the CS determines user target information. 11. The method according to claim 1 wherein reporting includes communicating the stored processed user activity data to a third-party location. 12. The method according to claim 1 wherein monitoring includes locally tracking and accumulating user activity at the social website and communicating the resulting user activity data to a classification service (CS), wherein the CS determines user target information periodically, aperiodically, or on an event-driven basis. 13. The method according to claim 1 wherein reporting includes reporting user activity data represented by metadata. 14. The method according to claim 1 wherein reporting includes generating a targeted advertisement based on user activity data. 15. The method according to claim 1 wherein reporting includes communicating data representative of user activity to an advertisement server. 16. The method according to claim 1 wherein processing includes processing user activity data in a substantially real-time manner. 17. The method of claim 1 wherein the method remotely monitors a plurality of social websites. 18. The method of claim 1 wherein the social website is a website allowing use of tagging or bookmarking associated with website content. 19. An apparatus to remotely monitor a social website, comprising: a monitoring unit configured to monitor user activity on a remote social website, resulting in user activity data; a processing unit configured to process the user activity data separate from the social website; a storage unit configured to store the processed user activity data; and a reporting unit configured to report information indicative of the processed user activity data. 20. The apparatus according to claim 19 wherein the monitoring unit is configured to monitor user activity in response to a call from the social website triggered by user activity at the social website. 21. The apparatus according to claim 20 wherein the call is an Application Programming Interface (API) call. 22. The apparatus according to claim 19 wherein the monitoring unit configured to poll a monitor service installed on the remote social website on a periodic, aperiodic, or event-driven basis. 23. The apparatus according to claim 19 wherein monitoring unit configured to effectively log or record user activity. 24. The apparatus according to claim 23 wherein user activity data is represented in the form of a uniform resource locator (URL). 25. The apparatus according to claim 19 wherein the processing unit is configured to parse the user activity data from at least one social website and normalize the parsed user activity data. 26. The apparatus according to claim 19 wherein the storage unit is configured to store the processed results in a centralized, searchable data store. 27. The apparatus according to claim 19 wherein the processing unit is configured to perform on-the-fly analysis of the user activity data. 28. The apparatus according to claim 19 further including a querying unit configured to query a classification service (CS) prior to displaying a requested web page at the social website, wherein the CS determines user target information. 29. The apparatus according to claim 19 wherein the reporting unit is configured to communicate the stored processed user activity data to a third-party location. 30. The apparatus according to claim 19 wherein the monitoring unit is configured locally track and accumulate user activity at the social website and communicate the user activity data to a classification service (CS), wherein the CS determines user target information on a periodic, aperiodic, or event-driven basis. 31. The apparatus according to claim 19 wherein the reporting unit is configured to report user activity data represented by metadata. 32. The apparatus according to claim 19 wherein the reporting unit is configured to generate a targeted advertisement based on user activity data. 33. The apparatus according to claim 19 wherein the reporting unit is configured to report data representative of user activity to an advertisement server. 34. The apparatus according to claim 19 wherein the processing unit is configured to process user activity data in a substantially real-time manner. 35. The apparatus according to claim 19 wherein the apparatus is configured to remotely monitor a plurality of social websites. 36. The apparatus according to claim 19 wherein the social website is a website where users associate a tag or bookmark with website content. 37. A computer program product for remotely monitoring a social website, the computer program product comprising a computer readable medium having computer readable instructions stored thereon, which, when loaded and executed by a processor, causes the processor to: monitor user activity on a remote social website, resulting in user activity data; process the user activity data separate from the social website; store the processed user activity data; and report information indicative of the processed user activity data. 38. A system to remotely monitor a social website, comprising: means for monitoring user activity on a remote social website, resulting in user activity data; means for processing the user activity data separate from the social web site; means for storing the processed user activity data; and means for reporting information indicative of the processed user activity data.	<SOH> BACKGROUND OF THE INVENTION <EOH>The amount of time that consumers spend on the Internet has steadily increased, as has the variety of web content, such that the Internet is often the first place many people turn to when searching for information, news, or entertainment. Consumers use a variety of methods to search for desired information on the Internet such as entering terms in a search engine. When a site of interest is found, users often times will bookmark the site to facilitate return visits. Over time, a user may develop a list of relevant sites based on a number of different topics. However, the constantly increasing number of websites has increased the time and effort it takes to weed through relevant websites. Social networks provide another method for consumers to more quickly locate websites of interest. One example of social websites are social bookmark sites where users share their bookmarks with other users. The user will save bookmarks or tags associated with a web page of interest at the bookmark website. Users may also “tag” a website by associating a term or label with the website allowing the categorization of different sites based on the tag. Thus, rather than using a search engine where software alone searches for a website based on content, social bookmark sites effectively use human beings (i.e., the users themselves) to rate and sort websites. Consequently, because a user found a webpage relevant enough to bookmark or tag, websites based on a particular topic are likely to be more relevant than software generated searches. Users may search other users' bookmarks based on the topic they are interested in to quickly locate relevant web sites. In addition, the very nature of a user's bookmarking and tagging behavior inherently identifies a user's interest in particular topics—much more than current methods which rely on page content, often, a simple “keyword presence” or in some cases, a more sophisticated linguistic processing of the page the user is viewing. Furthermore, while the user may arrive at a page of interest, most techniques do little to “know” the actual intentions of the user. While there are some techniques that try to deduce actual intention by performing tracking on a user's past behavior, they do so on the basis of identifying which pages have already been browsed by the user, thereby assuming that viewing a page indicates significant personal interest in the topics on that page where no such significant interest may actually exist.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention addresses the foregoing problems in the prior art. In particular, the invention provides a method and apparatus for remotely monitoring a social website for the purpose of centrally aggregating activity. In a preferred embodiment, the inventive computer implemented method and system for remotely monitoring a social website comprises (a) monitoring user activity on a remote social website that results in user activity data, (b) processing the user activity data separately from the social website that is being monitored, and (c) storing the processed user activity data. Information indicative of the processed user activity data may be reported. In accordance with an example embodiment of the invention, monitoring user activity may be a response to a call from the social website triggered by user activity at the social website, for example, an application programming interface (API) call. Alternatively, the system may monitor user activity by polling a monitoring service installed on the remote social website on a periodic, aperiodic, or event driven basis. Monitoring may effectively log or record user activity, and may be further represented in the form of a uniform resource locator (URL). In accordance with another example embodiment, the invention may parse user activity data from a plurality of social websites and then “normalize” or “standardize” the parsed user activity data. The processed results may be stored in, for example, a searchable data store such as a database. The results from the plurality of websites may also be centralized in a common database. Processing user activity data may include performing on-the-fly analysis of the data or the data may be stored and analyzed at a later time. In another embodiment, a classification system (CS) may be queried prior to displaying a requested web page at the social website. The classification system determines user target information as a part of the invention processing user activity data. A report may be communicated to a remote third-party or back to the social website, and may communicate the stored processed user activity data. In accordance with yet another example embodiment, user activity may be monitored by locally tracking and accumulating user activity at the social website. The accumulated activity may be communicated to a classification service (CS), and may be performed in a substantially real-time manner, or in a periodic, aperiodic, or event driven basis. The classification system determines user target information as a part of the invention processing user activity data. The reported user activity data may be in the form of metadata, and may take the form of, for example, user ID, timestamp information, IP address, etc. According to one example embodiment of the invention the report may include communicating data representative of other user activity to a third party, such as an advertisement server. According to another embodiment, communicated information may be encrypted prior to communicating or transmitting the data, and may similarly be decrypted at a receiving location. In addition, or alternatively, data may also be authenticated in order to, for example, circumvent requests from unauthorized third parties. In another embodiment, user activity data may be processed in a substantially real-time manner. The invention may remotely monitor a plurality of social websites, where, for example, tagging all bookmarking website content by the user is allowed.	RELATED APPLICATION This application claims the benefit of U.S. Provisional Application No. 60/835,257, filed on Aug. 2, 2006. The entire teachings of the above application(s) are incorporated herein by reference. BACKGROUND OF THE INVENTION The amount of time that consumers spend on the Internet has steadily increased, as has the variety of web content, such that the Internet is often the first place many people turn to when searching for information, news, or entertainment. Consumers use a variety of methods to search for desired information on the Internet such as entering terms in a search engine. When a site of interest is found, users often times will bookmark the site to facilitate return visits. Over time, a user may develop a list of relevant sites based on a number of different topics. However, the constantly increasing number of websites has increased the time and effort it takes to weed through relevant websites. Social networks provide another method for consumers to more quickly locate websites of interest. One example of social websites are social bookmark sites where users share their bookmarks with other users. The user will save bookmarks or tags associated with a web page of interest at the bookmark website. Users may also “tag” a website by associating a term or label with the website allowing the categorization of different sites based on the tag. Thus, rather than using a search engine where software alone searches for a website based on content, social bookmark sites effectively use human beings (i.e., the users themselves) to rate and sort websites. Consequently, because a user found a webpage relevant enough to bookmark or tag, websites based on a particular topic are likely to be more relevant than software generated searches. Users may search other users' bookmarks based on the topic they are interested in to quickly locate relevant web sites. In addition, the very nature of a user's bookmarking and tagging behavior inherently identifies a user's interest in particular topics—much more than current methods which rely on page content, often, a simple “keyword presence” or in some cases, a more sophisticated linguistic processing of the page the user is viewing. Furthermore, while the user may arrive at a page of interest, most techniques do little to “know” the actual intentions of the user. While there are some techniques that try to deduce actual intention by performing tracking on a user's past behavior, they do so on the basis of identifying which pages have already been browsed by the user, thereby assuming that viewing a page indicates significant personal interest in the topics on that page where no such significant interest may actually exist. SUMMARY OF THE INVENTION The present invention addresses the foregoing problems in the prior art. In particular, the invention provides a method and apparatus for remotely monitoring a social website for the purpose of centrally aggregating activity. In a preferred embodiment, the inventive computer implemented method and system for remotely monitoring a social website comprises (a) monitoring user activity on a remote social website that results in user activity data, (b) processing the user activity data separately from the social website that is being monitored, and (c) storing the processed user activity data. Information indicative of the processed user activity data may be reported. In accordance with an example embodiment of the invention, monitoring user activity may be a response to a call from the social website triggered by user activity at the social website, for example, an application programming interface (API) call. Alternatively, the system may monitor user activity by polling a monitoring service installed on the remote social website on a periodic, aperiodic, or event driven basis. Monitoring may effectively log or record user activity, and may be further represented in the form of a uniform resource locator (URL). In accordance with another example embodiment, the invention may parse user activity data from a plurality of social websites and then “normalize” or “standardize” the parsed user activity data. The processed results may be stored in, for example, a searchable data store such as a database. The results from the plurality of websites may also be centralized in a common database. Processing user activity data may include performing on-the-fly analysis of the data or the data may be stored and analyzed at a later time. In another embodiment, a classification system (CS) may be queried prior to displaying a requested web page at the social website. The classification system determines user target information as a part of the invention processing user activity data. A report may be communicated to a remote third-party or back to the social website, and may communicate the stored processed user activity data. In accordance with yet another example embodiment, user activity may be monitored by locally tracking and accumulating user activity at the social website. The accumulated activity may be communicated to a classification service (CS), and may be performed in a substantially real-time manner, or in a periodic, aperiodic, or event driven basis. The classification system determines user target information as a part of the invention processing user activity data. The reported user activity data may be in the form of metadata, and may take the form of, for example, user ID, timestamp information, IP address, etc. According to one example embodiment of the invention the report may include communicating data representative of other user activity to a third party, such as an advertisement server. According to another embodiment, communicated information may be encrypted prior to communicating or transmitting the data, and may similarly be decrypted at a receiving location. In addition, or alternatively, data may also be authenticated in order to, for example, circumvent requests from unauthorized third parties. In another embodiment, user activity data may be processed in a substantially real-time manner. The invention may remotely monitor a plurality of social websites, where, for example, tagging all bookmarking website content by the user is allowed. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the invention. FIG. 1 is a flow diagram of an example embodiment of the present invention. FIG. 2 is a flow diagram of an alternative example embodiment of the present invention. FIG. 3 is a flow diagram of another alternative embodiment of the present invention. FIG. 4 is a block diagram illustrating different components of a remote monitor system embodying the present invention. FIG. 5 is a schematic illustration depicting dataflow according to one embodiment of the present invention. FIG. 6 is a schematic illustration depicting dataflow according to an alternative embodiment of the present invention. FIG. 7 is a schematic view of a computer network environment in which the principles of the invention may be implemented. FIG. 8 is a block diagram of the internal structure of a computer from the FIG. 7 computer network environment. DETAILED DESCRIPTION OF THE INVENTION A description of example embodiments of the invention follows. The popularity of social networks and social bookmarking websites has grown dramatically such that they now number in the hundreds. The higher the number and variety of users a social bookmark site attracts, the more likely relevant websites will be found. However, recent analysis of a number of social websites has revealed that large number of bookmarks and tags are from a disproportionately small number of highly active users, thus, potentially skewing a particular website's effectiveness across the general public. To make better use of social networks, it would be useful to remotely monitor and centrally aggregate social websites to provide a larger number and variety of user bookmarks and tags from which to derive and analyze user activity thereby improving trend identification and targeting advertisements. A user's bookmark and tag information may be valuable as market research data. For example, a user who has bookmarked or tagged digital photography sites would be of interest to photographic equipment suppliers. Furthermore, as discussed above, aggregating user activity data across the large number of social websites would facilitate the identification of user and societal trends. For example, if webpages associated with the term “water parks” are bookmarked/tagged at a high frequency, ads displayed to users with those bookmarks could command an additional cost premium. The current invention provides a technique for remotely monitoring one or more social websites 410 (FIG. 4) where the resulting user activity data is processed and stored remotely, i.e., separately from the social website 410. To monitor user activity data or “events” on a remote social website 410, the technique may install a small amount of software code into the social website's operating code. The code generates a specially-formed “Observer” uniform resource locator (URL) that is sent to a remote monitor 415 when an event occurs. The parameters in the Observer URL describe the event that a user 405 performs on the social website 410. The monitoring process tracks multiple kinds of bookmark and tag events, so the code may be installed in the subject social website's code where those events actually happen and may be invoked using, for example, UNIX's “curl”, “lynx”, or “wget” programs, or any compatible application that can reliably generate a standards-compliant HTTP GET query. The format of the Observer URL may be as follows: http://obl.seethroo.us:8000/event/lg?user=a&bookmark=b&title=c&tag-d&eve nt=e&ipnum-f&timestamp=g&sting=h&site=i&adtag=j Each parameter of the Observer URL holds a different piece of information about the event being monitored. The letters ‘a’ through ‘j’ in the example Observer URL above will be replaced with actual values when installing it on the social website's server, such as the following: In user=a, the “a” may be replaced with the escaped (Web-safe) user ID of the person performing the event. For example, if the user is “jsmith”, the parameter would be “user=jsmith”. The monitoring process does not require an actual user name any unique identifier that is consistently associated with the same user on the social website is permitted. For example, if the user is “jsmith” and a unique ID for jsmith is 05b7f505fb63e9737ddcfce86d8ca2a97d21654f, the parameter would be “user=05b7f505fb63e9737dd1fce86d8ca2a97d21654f”. In bookmark=b, the “b” may be replaced with the escaped (Web-safe) URL of the bookmark involved in the event, if any. If the event is exclusively tag-related (see below) and there is no bookmark involved, the parameter is left blank in one embodiment. For example: if the bookmark is “http://www.cnn.com/health”, the parameter would be “bookmark=http%3A//www.cnn.com/health” In title=c, the “c” may be replaced with the escaped (Web-safe) title of the bookmark involved in the event. If the event is exclusively tag-related (see below) and there is no bookmark title involved, the parameter is left blank in one embodiment. For example, if the title is “CNN.com—Health”, the parameter would be “title=CNN.com%20-%20Health”. In tag=d, the “d” may be replaced with the escaped (Web-safe) tag (or comma-separated list of tags) involved in the event. If the event is exclusively bookmark-related (see below) and there is no tag involved, the parameter is left blank in one embodiment. If there is only one tag, the trailing comma may be omitted. For example, if there are three tags named “news, health, exercise”, the parameter would be “tag=news %2Chealth%2Cexercise”. If there is one tag named “microsoft”, the parameter would be “tag=microsoft”. In event=e, the “e” may be replaced with the escaped (Web-safe) text describing what the event is and may include a variety of event-specific tokens, such as these examples: add_bkmk (used when a new bookmark is added to the user's account) click_bkmk (used when the user clicks on one of their bookmarks) del_bkmk (used when the user erases a bookmark) add_tag (used when the user first adds a tag onto a bookmarks), or to their account in general) view_tag (used when the user views bookmarks assigned with the same tag) del_tag (used when the user erases a tag from a bookmark or their account) search (used when a search is performed, either of the user's own bookmarks/tags or across the entire social website) import (used when the user uploads or imports their bookmarks) For example, if the user is adding a bookmark to his account, the parameter would be “event=add_bkmk.” Users may also import large files containing several bookmarks. In ipnum=f, the “f” may be replaced with the escaped (Web-safe) IP number of the remote host using the social website. For example, if the user's remote computer has an IP number of “207.69.101.5”, the parameter would be “ipnum=207.69.101.5”. In timestamp=g, the “g” may be replaced with the escaped (Web-safe) timestamp of when the event occurred, using any suitable format, such as the ISO8601 format. The timestamp “Sat Sep 02 2006 00:21:13 GMT-0400 (EDT)” would be “2006-09-02T00:21:13-04:00” in ISO8601 format, for example. Thus, if the event has a timestamp of “Sat Sep 02 2006 00:21:13 GMT-0400 (EDT)” the parameter would be “timestamp=2006-09-02T00%3A21%3A13-04%3A00. In string-h, the “h” may be replaced with the escaped (Web-safe) text the user performed a search on. For example, if the event is “search” and the user performed a search for “electronic arts bond”, the parameter would be “string=electronic%20arts%20bond”. If the event parameter does not indicate a search, then this parameter may be left blank. In site=i, the “i” may be replaced with the escaped (Web-safe) id of the social website. For example, if the website is “Connectedy.com”, the parameter would be “site=connectedy.” As in the user parameter (above), the monitoring process does not require the actual name of the social website—any unique identifier that is consistently associated with the same social website is permitted. In adtag=j, the “j” may be replaced with any value, including “y” or “n”, indicating that a targeted ad should be sent back to the social website after the Observer URL has been processed by the monitoring server. Thus, using the above examples, the complete TJRL could look like the following: http://obl.seethroo.us:8000/event/lg?user=05b7f505fb63e9737dd1fce86d8ca2a97d21654f&bookmark=http%3A//www.cnn.com/health&title=CNN.com%20-%20Health&tag=news%2Chealth%2Cexercise&event=add_bkmk&ipnum=207.6 9.101.5&timestamp=2006-09-02T0003A21%3A13-04%3A00&string=&site-connectedy&adtag=y In this manner, the event of “adding a new bookmark” on the social website may be monitored by performing the following sequence of actions: 1. A developer locates the specific commands in the social website's 410 program code that are invoked when a user 405 adds a new bookmark to his account. 2. Immediately preceding or following these commands, the developer edits the program to insert an additional command. This additional command, when executed, sends the Observer URL to the remote monitor 415. The exact command used to send the Observer URL is dependent on the programming language and web serving environment used by the social website 410. 3. The developer associates each parameter in the Observer URL with whatever specific variables are used by the social website 410 to describe the event. For example, the parameter in the Observer URL that holds the name of the bookmark is called “title”. If the subject social website's code normally uses “$bookmark_name” to represent this, the developer would edit the Observer URL to say “title=$bookmark_name”. Note that the specifics of this will also vary, depending on the programming language and web serving environment used by the social website 410. 4. The developer repeats this process, adding the Observer URL to each place in the program code that performs each of the events that the remote monitor tracks, and adding the correct names of variables used by the social website 410 that match the Observer URL's parameters. 5. Once the command that sends the Observer URL to the remote monitor 415 has been installed into the correct places in the social website's code, the remote monitor 415 can begin receiving events in real-time from the social website 410. 6. When a user 405 of the social website 410 adds a bookmark to his account, the social website 410 performs the task as normal. At virtually the same moment (either immediately preceding or following), the Observer URL is sent via a global computer network 70 (e.g., the Internet) to the remote monitor 415. The parameters in the Observer URL contain all the details describing the event, such as the name of the bookmark, the encrypted ID of the person who is adding the bookmark, the bookmark's URL, any tags used with the bookmark, the time the bookmark is being added, the IP number of the person's computer, and whatever other metadata have been included in the Observer URL. 7. The remote monitor 415 continually waits for Observer URLs to be sent. When the remote monitor 415 receives a request containing the Observer URL, it accepts the URL as input and the monitoring program 455, 470 runs. 8. The monitoring program 455, 470 accepts the request and parses the text of the URL to assign each parameter into a dedicated field in a local database 480. The UKL's parameters are separated, decoded/unescaped and used to construct a new data record in memory 480. 9. Once the data record is assembled and stored in memory, the record is written into the storage unit (e.g., database) 480. At this point the original event at the social website 410 has been effectively duplicated and recorded by the remote monitor 415. 10. Once the record has been saved in, for example, a storage unit (e.g., database) 480, the remote monitor 415 may or may not reply. If the “adtag” parameter in the Observer URL has a value of ‘n’, the monitoring server 415 may close the network connection without any reply to the social website 410. This is to ensure that the social website 410 will continue performing its normal tasks as quickly as possible, without waiting for a monitoring response that may not arrive, perhaps due to a network error, programming bug, or some other problem. Alternately, if the “adtag” parameter in the Observer URL has a value of ‘y’, then the remote monitor 415 will use the information from the Observer URL to choose an advertisement that is a suitable match. 11. The selection of the ad can be done either locally, by accessing a store of ads to be sent to the social website 410 in reply to the monitored event, or remotely, by sending a descriptive token or keyword to a third-party ad server 420, which then selects an ad and returns it to be displayed on the social website 410. Referring now to FIG. 1, a flow diagram illustrating an example embodiment of the invention is depicted. The process 100 begins 105 and monitors user activity on a social website at step 110. The monitoring step/process results in user activity data such as that described above. The resulting user activity data is processed separately or remotely from the social website that step 115. After processing step 115, the invention process 100 may store (step 120) processed user activity data in, for example, a searchable data store. Information indicative of the processed user activity data may be reported at step 125. The process 100 may then end 130. FIG. 2 is a flow diagram illustrating an alternative example embodiment of the invention. The invention process 200 begins 205 with a user accessing a social website 210 whereby a variety of events are generated (step 210). For example, users 405 of a social bookmarking site 410 may access their bookmarks thereby generating events involving bookmark links and tags, such as “add bookmark,” “click bookmark,” and “add tag.” These events may be sent to a social website (step 215) via a computer or other communication network, such as the Internet, as requests to the social bookmarking server. The social website 410 may act on the events (step 220). For example, a social bookmarking site 410 may receive the bookmarking and/or tag events and the server may perform actions to process the request. The social bookmarking site 410 records the request (or otherwise acts on it, executing whatever code is programmed). The social bookmarking site 410 may also parse the details of the request and construct a representation of user activity (step 225), such as a GET-style URL (such as that discussed above) to describe the event that was just recorded. Next, the social website 410 sends the representation of user activity (e.g., the GET URL) to a classification service (CS) 460 (in FIG. 4) at step 230 in FIG. 2. The classification service 460 receives the representation of user data and parses it to extract generated events (step 235), such as parameters describing the event that was just recorded, or the URL can remain unparsed and recorded unchanged, for later processing. The classification service 460 then acts on the events (step 240), such as recording the request (or executing whatever code is programmed). The process 200 then ends 245. FIG. 3 is a more detailed flow diagram illustrating an example embodiment of the present invention. The process 300 begins 305 with a user 405 at a social website 410 requesting content (step 310) via a web browser, for example, a page containing the user's bookmarks. The social website 410 then calls a classification service 460 to get targeting information for the user (step 315). To ensure integrity of the received data, the social website 410 may authenticate the information at step 320. The process 300 continues and at step 325 the social website 410 sends either a signed token describing the user 405 and request to the classification service 460, or at step 330 sends an unauthenticated version of the information describing the user 405 and request to the classification service 460. The classification service 460 determines target information at step 335′ such as appropriate keywords and may also record the event. The classification system 460 then sends target information to the social website at step 345, or may optionally authenticate the information at step 340 and send a digitally signed token describing the target information to the social website at step 350. The social website 410 then constructs a webpage combining its own content, the target information and advertisement server code and delivers it to the user at step 355. The user's browser interprets the returned page's content and executes the advertisement server's code to request an ad from the advertisement server 420. Next, the advertisement server 420 selects a targeted ad based on the targeted information or token and then sends the ad back to the user's browser at step 365. After receiving the targeted ad, the users browser renders the content, for example, the combined requested bookmark page and the targeted ad at step 370. The process 300 then ends 375. FIG. 4 is a block diagram of a remote monitoring system 400 according to an example embodiment of the invention. The remote monitoring system 400 may contain a remote monitor 415 which includes a monitoring unit 455, classification service (CS) 460, reporting unit 465, processing unit 470, storage unit 480, encryption/decryption unit 485, and digital signature unit 490. The system 400 may remotely monitor user 405 activity on at least one remote social website 410. The social website 410 may include an encryption/decryption unit 425, digital signature unit 430, storage unit 435, querying unit 440, monitor service 445, and calling unit 450. A monitoring service unit 445 may be configured to monitor user activity 405 on a remote social website 410, resulting in user activity data. The processing unit 470 is configured to process the results user activity data separately from the social website 410, in a substantially real-time manner, or processed at a later time. The user activity data may be stored in the storage unit 480. The reporting unit 465 may be configured to report information indicative of the processed user activity data. The monitoring unit 455 may be configured to monitor user 405 activity in response to a call from the social website's 410 calling unit 450 that may be triggered by the user's activity at the social website. The call may be an application programming interface (API) call, or similar call known in the art. Alternatively the monitoring unit 455 may be configured to poll the monitor service 445 that is installed on the remote social website 410 on a periodic, aperiodic, or event-driven basis. In either case, the monitoring unit 455 effectively logs or records the user's activity. In one embodiment the user activity data may be represented in the form of a uniform resource locator (URL). And in another example embodiment, a monitoring unit 455 may be configured to locally track and accumulate user activity at the remote social website 410, and may communicate the user activity data to the CS 460 where the CS determines user target information on a periodic, aperiodic, or event-driven basis. The processing unit 470, through use of a parsing unit 472 may parse the user activity data results from the remotely monitored social websites(s) 410. The normalizing unit 474 may “normalize” or “standardize” the parsed user activity data. That is, social websites 410 may store particular data fields using slightly different identifiers. For example, one social website 410 may store the user's identity in a field labeled “user” and another social website 410 may store the same information in a field “userID” and still another social website may use the label “username.” Thus, the invention normalizing unit 474 effectively standardizes non-standardized field names from a variety of social websites 410 using a common label or identifier allowing the aggregation of user activity data from virtually every social website, Advantageously, the invention aggregates data from a plurality of social websites 410 allowing the identification of trends not currently identifiable, such as trends across a large number of users or more broadly such as societal trends. To facilitate this analysis, the storage unit 480 may be configured to store the processed results in a centralized, searchable data store such as a database where the normalizing unit 474 has standardized the results data. Alternatively this information may be distributed across multiple storage units 480 to provide data redundancy, increased search speeds, and other benefits known in the art. The processing unit 470 may also be configured to perform on-the-fly analysis of the user activity data, or alternatively, may store the user activity data for analysis at a later time. The querying unit 440 of the social website 410 may also be configured to query the CS 460 before the social website displays the user requested page where the CS 460 determines user target information. In an example embodiment, the reporting unit 465 may be further configured to communicate and transmit the stored process user activity data to a third party, such as an advertisement server 420. The reporting unit 465 may also be configured to report user activity data represented in the form of metadata or other data or file formats known in the art. Alternatively, or in addition, the reporting unit 465 may also be configured to generate a targeted advertisement based on user activity data and may communicate that advertisement to a third-party 420 or to the social website 410 for display in the user's 405 browser. The user activity data may be protected using a variety of data protection techniques known to those skilled in the art. For example, the encryption/decryption unit 485 of remote monitor 415 may encrypt data prior to transmitting the data to the social website 410 where in turn the encryption/decryption unit 425 of the social website 410 will then decrypt the information. It should be understood that in order to provide effective data protection the encryption/decryption process may occur throughout the entire chain of data transmission, including but not limited to, from the social website 410 to the remote monitor 415, from the remote monitor 415 to the third-party server 420, from the third-party server 420 to the remote monitor 415, and from the remote monitor 415 to the social website 410. Alternatively, or in addition, the digital signature unit 490 may be used to authenticate data according to data authentication techniques known in the art. This may be useful in circumventing fraudulent requests (e.g., metadata, spam, etc.) from unauthorized third parties, for example, preventing a third-party from writing bogus data to the remote monitoring unit 415. The social website 410 may be a website where users are allowed to associate a tag or bookmark to the social website's content. Social websites have proliferated at an increasingly rapid rate such that there are now hundreds of social websites currently in operation. The invention 400 may also be used in conjunction with other social web sites 410, such as blogs or any other website that allows the use of tags to be added and/or associated with content. FIG. 5 is a schematic diagram representing data flow in an example embodiment 500 of the invention. The remote monitoring system 500 may comprise a classification system (CS) 515 implemented using, for example, a processor (not shown). A user 505 may request a bookmark page from a social website 510 (step 1). The social website 510 then calls the CS 515 in order to obtain user targeting information (step 2). As mentioned above this communication may be encrypted, and digitally signed or otherwise made secure. The CS 515 may record the event in a storage unit 530, such as a searchable database. The CS 515 may also analyze previous and/or current activity data for the user 505 as previously recorded in storage unit 530 in order to determine an appropriate keyword or multiple keywords (step 3). In this embodiment, the CS 515 is guaranteed to record the event before the CS performs its ad selecting analysis. The CS 515 then returns the determined keyword(s) either as it is, or encrypted, or as a digitally signed token back to the social website 510 (step 4). The social website 510 then combines its page with the CS keyword/token and advertisement server code (step 5). Alternatively, the CS can return both the keyword(s) and the advertisement server code together. Next, in response the user's browser interprets the received combined page and executes the advertisement server code (step 6). The advertisement server code may then request an ad using the received keyword/token (step 7). The advertisement server 520 may determine the best ad based on the subject keyword/token (step 8). The advertisement server 520 then delivers the determined ad to the user's browser (step 9) where the user's browser then renders the user's requested page (step 10). FIG. 6 is a schematic diagram representing data flow in and alternative example embodiment 600 of the invention. This embodiment similarly begins with the user 605 requesting, for example, a bookmark page from a social website 610 (step 1). Here, however, the social website 610 constructs a webpage and returns the page to the user 605 with additional scripting code (step 2). The users browser 605 executes the scripting code while preparing the requested webpage for display (step 3). Next, the scripting code may use a forked process to request the advertisement server 620 to display in the ad where the request includes a representation indicating a specific user (step 4A) and may also send a message to the CS 615 recording the action just performed by the user (step 4B). Because this embodiment 600 uses a forked process, the CS 615 is not guaranteed to record the event before the CS performs its ad selecting analysis. Next, the advertisement server 620 receives a request from the user's web browser 605 (step 5) and then calls the CS 615 for targeted information for that specific user (step 6). The CS 615 responsively analyzes the request and determines an appropriate keyword (step 7). The CS 615 then returns a keyword or digitally signed token to the advertisement server 620 (step 8). If the data was authenticated the advertisement server 620 confirms the token's authenticity using CS's public key or other authentication techniques known to one skilled in the art. Next, the advertisement service 620 selects a targeted ad based on the received token/keyword (step 9) and returns the determined ad to the user's browser 605 (step 10). Then the page returned by the social website 610 (step 2) is combined with the targeted ad and sent to the user's browser 605 for rendering (step 11). As mentioned previously, various communications may be made secured digitally signed encrypted/decrypted between the various modules (405, 410, 415, 420, 505, 510, 515, 520, 605, 610, 615, 620) in FIGS. 4, 5 and 6. The block diagrams of FIGS. 4, 5, and 6 are merely representative and that more or fewer units may be used, and operations may not necessary be divided up as described herein. Also, a processor executing software may operate to execute operations performed by the units, where various units, separately or in combination may represent a processor, field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like. It should be understood that the block diagrams may, in practice, be implemented in hardware, firmware, or software. If implemented in software, the software may be any form capable of performing operations described herein, stored on any form of computer readable-medium, such as RAM, ROM, CD-ROM, and loaded and executed by a general purpose or application specific processor capable of performing operations described herein. FIG. 7 illustrates a generalized computer network 700 or similar digital processing environment in which the invention may be implemented. Client computer(s)/devices 50 and server computer(s) 60 provide processing, storage, and input/output devices executing application programs and the like. Client computer(s)/devices 50 can also be linked through communications network 70 to other computing devices, including other client devices/processes 50 and server computer(s) 60. Communications network 70 can be part of a remote access network, a global network (e.g., the Internet), a worldwide collection of computers, Local area or Wide area networks, and gateways that currently use respective protocols (TCP/IP, Bluetooth, etc.) to communicate with one another. Other electronic device/computer network architectures are suitable. FIG. 8 is a diagram of the internal structure of a computer 50, 60 (e.g., client processor/device 50 or server computers 60) in the computer system of FIG. 7. Each computer 50, 60 contains system bus 79, where a bus is a set of hardware lines used for data transfer among the components of a computer or processing system. Bus 79 is essentially a shared conduit that connects different elements of a computer system (e.g., processor, disk storage, memory, input/output ports, network ports, etc.) that enables the transfer of information between the elements. Attached to system bus 79 is I/O device interface 82 for connecting various input and output devices (e.g., keyboard, mouse, displays, printers, speakers, etc.) to the computer 50, 60. Network interface 86 allows the computer to connect to various other devices attached to a network (e.g., network 70 of FIG. 7). Memory 90 provides volatile storage for computer software instructions 92 and data 94 used to implement an embodiment of the present invention (e.g., remote monitoring, processing, storing and reporting code 63 detailed above). Disk storage 95 provides non-volatile storage for computer software instructions 92 and data 94 used to implement an embodiment of the present invention. Central processor unit 84 is also attached to system bus 79 and provides for the execution of computer instructions. In one embodiment, the processor routines 92 and data 94 are a computer program product (generally referenced 92), including a computer readable medium (e.g., a removable storage medium such as one or more DVD-ROM's, CD-ROM's, diskettes, tapes, etc.) that provides at least a portion of the software instructions for the invention system. Computer program product 92 can be installed by any suitable software installation procedure, as is well known in the art. In another embodiment, at least a portion of the software instructions may also be downloaded over a cable, communication and/or wireless connection. In other embodiments, the invention programs are a computer program propagated signal product 107 embodied on a propagated signal on a propagation medium (e.g., a radio wave, an infrared wave, a laser wave, a sound wave, or an electrical wave propagated over a global network such as the Internet, or other network(s)). Such carrier medium or signals provide at least a portion of the software instructions for the present invention routines/program 92. In alternate embodiments, the propagated signal is an analog carrier wave or digital signal carried on the propagated medium. For example, the propagated signal may be a digitized signal propagated over a global network (e.g., the Internet), a telecommunications network, or other network. In one embodiment, the propagated signal is a signal that is transmitted over the propagation medium over a period of time, such as the instructions for a software application sent in packets over a network over a period of milliseconds, seconds, minutes, or longer. In another embodiment, the computer readable medium of computer program product 92 is a propagation medium that the computer system 50 may receive and read, such as by receiving the propagation medium and identifying a propagated signal embodied in the propagation medium, as described above for computer program propagated signal product. Generally speaking, the term “carrier medium” or transient carrier encompasses the foregoing transient signals, propagated signals, propagated medium, storage medium and the like. In some embodiments computer system 40 employs a Windows™ (Microsoft) operating system, in other embodiments a Linux operating system, and in other embodiments a UNIX™ operating system. Other operating systems and system configurations are suitable. Applicant claims trademark rights to the terms “Seethroo”, “Seethroo Observer”, and “Observer URL.” While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims. For example, the present invention may be implemented in a variety of computer architectures. The computer network of FIGS. 7 and 8 are for purposes of illustration and not limitation of the present invention.	G	60G06	161G06F	151	73
11866484	US20090094087A1-20090409	MULTI-TIER CROSS-DEPARTMENT SCHEDULING MODEL FOR ORDER PROCESSING OPERATIONS	ACCEPTED	20090325	20090409	[]	G06F1900	["G06F1900", "G06F1710", "G06Q1000"]	8117052	20071003	20120214	705	007110	57223.0	CLARK	DAVID	[{"inventor_name_last": "Chung", "inventor_name_first": "Casey", "inventor_city": "MCKINNEY", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Sriskandarajah", "inventor_name_first": "Chelliah", "inventor_city": "PLANO", "inventor_state": "TX", "inventor_country": "US"}]	A multi-tier cross-department scheduling model for order processing operations. A scheduling model for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments and the departments share finite capacity resources, includes a programmable computer system having loaded therein an objective function, and the computer system being operable to minimize a value of the objective function; and wherein the objective function comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting.	1. A scheduling model for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments, and the departments share finite capacity resources, the model comprising: a programmable computer system having loaded therein an objective function, and the computer system being operable to minimize a value of the objective function; and wherein the objective function comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting. 2. The scheduling model of claim 1, wherein the cost to ship containers in at least one of consolidated and unconsolidated forms is represented in the objective function by the expression P 1  ∑ k = 1 n  ∑ i = 1 r  X i , k , j   1 + P 1  ∑ k = 1 n  ∑ i = 1 r  ∑ j ∈ j   2  X _ i , k , j wherein P1 is a shipping cost per container, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Xi,k,j1 is a number of containers of job k processed in a selected merge department j1 during shift i, Xi,k,j is a number of containers of job k diverted direct to shipping from department j during shift i, and j2 is a subset of departments including the selected departments. 3. The scheduling model of claim 1, wherein the cost for each of a container equivalent not completed in a selected scheduling horizon is represented in the objective function by the expression ∑ k = 1 n  P 2  C k B k  ( B k - ∑ j ∈ R  ∑ i = 1 r  Y ikj ) wherein P2 is a cost of shipping by an alternative mode of transportation, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Ck is a number of containers to be generated by job k, Bk is a number of pieces to be shipped in job k, Yikj is a number of pieces of job k shipped during shift i in department j, and R is a set of picking and processing departments other than merging or sorting departments. 4. The scheduling model of claim 1, wherein the cost to process each job in each department is represented in the objective function by the expression ∑ j ∈ R  ∑ k = 1 n  ∑ i = 1 r  ( d kj  Y ikj ) . wherein i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Yikj is a number of pieces of job k shipped during shift i in department j, dkj is a unit cost to process job k in department j, and R is a set of picking and processing departments other than merging or sorting departments. 5. The scheduling model of claim 1, wherein the cost for setup due to at least one of shift crossing and job splitting is represented in the objective function by the expression P 3  ∑ k = 1 n  ∑ i = 1 r  M ik wherein P3 is a setup cost accounting for labor needed to switch between jobs or shifts, i is a shift index number from 1 to r, k is a job index number from 1 to n, and Mik is equal to 1 if job k is processed in shift i, and is equal to 0 if job k is not processed in shift i. 6. A method of scheduling discrete jobs for shipment from multiple departments which share finite capacity resources, the method comprising the steps of: constructing an objective function which comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting; and programming a computer system to minimize a value of the objective function. 7. The method of claim 6, wherein the objective function constructing step includes representing the cost to ship containers in at least one of consolidated and unconsolidated forms by the expression P 1  ∑ k = 1 n  ∑ i = 1 r  X i , k , j   1 + P 1  ∑ k = 1 n  ∑ i = 1 r  ∑ j ∈ j   2  X _ i , k , j wherein P1 is a shipping cost per container, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Xi,k,j1 is a number of containers of job k processed in a selected merge department j1 during shift i, Xi,k,j is a number of containers of job k diverted direct to shipping from department j during shift i, and j2 is a subset of departments including the selected departments. 8. The method of claim 6, wherein the objective function constructing step includes representing the cost for each of a container equivalent not completed in a selected scheduling horizon by the expression ∑ k = 1 n  P 2  C k B k  ( B k - ∑ j ∈ R  ∑ i = 1 r  Y ikj ) wherein P2 is a cost of shipping by an alternative mode of transportation, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Ck is a number of containers to be generated by job k, Bk is a number of pieces to be shipped in job k, Yikj is a number of pieces of job k shipped during shift i in department j, and R is a set of picking and processing departments other than merging or sorting departments. 9. The method of claim 6, wherein the objective function constructing step includes representing the cost to process each job in each department by the expression ∑ j ∈ R  ∑ k = 1 n  ∑ i = 1 r  ( d kj  Y ikj ) wherein i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Yikj is a number of pieces of job k shipped during shift i in department j, dkj is a unit cost to process job k in department j, and R is a set of picking and processing departments other than merging or sorting departments. 10. The method of claim 6, wherein the objective function constructing step includes representing the cost for setup due to at least one of shift crossing and job splitting by the expression P 3  ∑ k = 1 n  ∑ i = 1 r  M ik wherein P3 is a setup cost accounting for labor needed to switch between jobs or shifts, i is a shift index number from 1 to r, k is a job index number from 1 to n, and Mik is equal to 1 if job k is processed in shift i, and is equal to 0 if job k is not processed in shift i.	<SOH> BACKGROUND <EOH>The present invention relates generally to scheduling models and, in an embodiment described herein, more particularly provides a multi-tier cross-department scheduling model for order processing operations. A hypothetical Company B will be used herein to demonstrate the types of problems faced in typical complex order processing operations. Suppose, for example, that Company B is the industry leader in rentable DVD and game media with over 9,000 stores worldwide (over 5,600 in the United States including franchisees) and over $5.8 billion in annual revenue for fiscal year 2005 (over $3.9 billion in the United States including franchisees). The data used in this application is specific to the United States order processing and distribution operations and does not include any international activities. The DVD and electronic game industries are highly peculiar when compared to others as they are characterized by an extremely compressed life cycle due to the release date structure imposed by the movie studios and to the short active life span inherent in any entertainment media product. As such it is very customary to see a great majority of sales activity in the first week a specific title is offered with very little activity in subsequent weeks. The only exception to this pattern would be titles that have a seasonal aspect such as Holiday genre as the individual holidays approach (for example Horror movies as Halloween approaches) or if there are complimentary titles offered (such as a part 3 of a movie trilogy causing increased activity for parts 1 and 2). In this sense it is convenient to look at the industry as one with 52 distinct “seasons” as the new release offerings change on a weekly basis. We find from history that these weekly “seasons” have virtually no correlation with each other but there is a weak correlation to the calendar seasons. An example of the life cycle for a single product along with Company B's niche can be seen in the FIG. 1 . It is important to notice that in both the theatrical release and the release on DVD the revenue decay curve is extremely steep. We find that a product's life cycle can also take multiple paths based on when/how it is being used. As seen in FIG. 2 a product can move from a high volume new release title (region I) to a low volume catalog title (region IV) through the normal decay curve. Also, when seasonal activity and complimentary titles are considered product can shift from low volume to high even for older titles (region IV to region II). Likewise some titles may never leave the low volume range even if it is a new release product (region III to region IV). History has shown that due to the continually changing product mix, the weekly aggregate volumes can drop to as low as 50% from one week to the next or can just as easily double. Forecasting this change in volumes is difficult as each new product is truly a new release with no history, forcing the industry to predict activity based on historical performance of “similar products” as well as product performance in theatrical venues. However, even the best models result in a high degree of error. To accommodate the supply chain requirements of this highly specialized industry, logistic networks in the game and DVD rental industry have adopted methods and processes that are flexible enough to handle this extreme level of volatility while creating methods and processes that are robust enough to virtually eliminate late product deliveries. This is critical in this industry as with a nearly nonexistent maturity/decline phase in the product life cycle, any delays in product delivery would have the net effect of eliminating any potential for revenue to be gained from the product. Simply stated, any late deliveries have a tremendous cost impact. Company B, as an industry leader has pioneered many of the initiatives necessary to remain competitive in this arena. Focusing specifically on Company B's distribution organization we can see in the process flow diagram shown in FIG. 3 that Company B has developed a system of 12 picking/processing departments followed by a total of 9 merge/sortation points in addition to a recursive product infeed as the cornerstone for its distribution model. This process flow diagram represents picking and processing departments denoted by a “P” (P 1 , P 2 , etc.), conveyor merge points denoted by an “M”, and system sortation points denoted by an “S.” Picking and production activities include activities that range from simple retail picking to light manufacturing where raw discs and artwork (received in bulk) are built into the rental units as found in Company B stores. Conveyor merge points are used to route multiple conveyor lines to a single conveyor, and sortation points are used to route containers from a single conveyor line to multiple lines/departments. Here ( FIG. 3 ) sortation point S 1 is being used to sort outbound containers direct to individual shipping doors and sortation point S 2 is being used to sort orders that have been picked/processed to locations in the consolidation department (M 3 ). Ideally all product would flow through Merge 3 (M 3 ) and would exit the system through sorter 1 (S 1 ) using the recursive infeed through Merge 2 (M 2 ) as shown by the bold arrows in FIG. 3 . If capacity constraints were exceeded at any of the merge/sortation points along the process we would expect product to exit the system as the capacity constraints were encountered (for example at M 1 , M 2 , S 1 , S 2 , M 3 , etc.), thereby bypassing subsequent system constraints. This “system bypass” potential is shown on FIG. 3 by the arrows at the merge/sortation points labeled as X i,k,M1 , X i,k,M2 , X i,k,S1 , X i,k,S2 , X i,k,M3 . The system bypass potential is undesirable as doing so would prevent containers from taking advantage of the consolidation process at merge point M 3 which yields a much lower system cost by reducing the number of containers shipped. The nature of this consolidation relationship (merge M 3 ) will be discussed more thoroughly below. As cumbersome as these process flow diagrams appear, these are the result of multiple planned process improvement initiatives which are strategically designed to maximize throughput, while maintaining a very high level of flexibility and service level execution. In reality this process flow diagram is similar to environments that can be found at large “big box” retailers and package delivery companies. Once orders are produced either through picking or manufacturing and exit the conveyor system, outbound containers are shipped to stores primarily through a pool point network of over 40 regional pool points. These regional pool points crossdock containers from the Company B distribution center to the stores. As Company B maintains one distribution facility and ships to over 5,600 stores within the United States, this “hub and spoke” design has proven to be more cost effective than creating multiple distribution facilities or shipping direct to stores. It should be noted that shipping by pool point adds additional constraints (as each pool point location has a set weekly trailer departure schedule regardless of volume), and complexity (through having to coordinate with multiple carriers and pool point operators as they are regional in nature), with the trade off of a greatly reduced cost per piece shipped. The transit time from the distribution center to an individual store ranges from 2 to 7 days using the pool point shipping method (depending on region being shipped to) versus 1 to 5 days using other direct to store methods. Expense of shipping product using pool points is a fixed cost per container and is contract dependent. For purposes of illustration, we will use an estimated cost of $2.50 per container shipped via pool point (independent of container dimension) and $6.00 as an estimated charge per container if the shipment is made direct to store (dependent on container dimension). Although we can already see the benefit here of using the pool point network ($2.50 vs. $6.00 per container), we will see during the problem formulation that the true benefit when combining pool points with a consolidation process dwarfs these initial cost savings. From a complexity standpoint, a typical week in this environment can experience as many as 400 jobs which must be worked across 12 processing departments where individual jobs may be completed in anywhere from 1 to 5 different departments depending on job requirements which must then compete for capacity in up to 9 subsequent shared resources. The operating schedule consists of two 12 hour shifts per day across 6 days per week for a total of 12 shifts per week. As breaks, lunches, shift start up meetings, etc. must also be considered, we can normally assume 10.5 available production hours per employee per shift. Jobs that can be completed in multiple departments may experience higher processing costs in some departments over others. Roughly 5% of the overall demand is based on point of sale activity and 95% is based on forecasted allocation. Even though the 95% forecasted allocation is deterministic, the detailed planning window is still very short due to the nature of the business resulting in the need for a very flexible and dynamic solution. Until now, the planning tools available at Company B were confined to the following— 1. A long range model (3-18 months) which plans aggregate activity for budgeting purposes; 2. An intermediate range model (1-3 months) which plans aggregate capacity by department (excluding merge/sortation constraints); and 3. A short range tactical model (1 week) which plans aggregate capacity by department (excluding merge/sortation constraints) including labor planning As a result of these three planning tools used at Company B, their distribution operation has been characterized by intermittent situations where capacity limits at critical nodes in the production and product handling processes have been exceeded due to unexpected activity spikes. Visibility to these activity spikes are typically known up to a couple of days in advance but as all scheduling previously took place in aggregate their ability to effectively control the operation at the discrete job level did not exist. This resulted in additional transportation costs, poor system utilization and a high cost of labor. This problem as described at Company B is common in practice but has yet to be treated. Not only are there no available software packages on the market to address this problem, but there is also no available theoretical research on this topic. There exists a great deal of literature regarding scheduling theory (Pinedo, 2002; Graves, 1981), most of which does not sufficiently address the problem stated above. Likewise, there is existing literature regarding scheduling models applied in practice (Brown et al. 2002; Moss et al. 2000; Olson et al. 2000) which, again, are different from the problem addressed in this application. Dobson et al. (2001) deal with the problem of minimizing the scheduling cost (defined as the product of the holding cost and the flow time of a particular batch) which they state is similar to a weighted flow time. In doing so Dobson et al. consider an environment where jobs are organized into batches which must then be processed through a processing center. This is typical of many scheduling examples, however it does not consider parallel processing centers which must then compete for subsequent processing capacities. Similarly, Kuchta et al. (2004) uses mixed integer programming to schedule parallel operations to maintain consistent output. Here their objective function is to minimize the sum of the excess production and the deficit production volume (not the net difference but rather the sum of “absolute values”). However, their approach does not address competition between multiple production departments which compete for shared downstream capacities. Chen and Pundoor (2006) considers four problems with different cost related objective functions and assumes product that is time sensitive, with high variety, short life cycle and schedules them through parallel processing sites with a transportation cost. In this example Chen and Pundoor addresses an environment much more similar to what we find in this application (scheduling across production departments in parallel) but again stops short of addressing the possibility of the parallel departments competing for subsequent resources. Keskinocak et al. (2002) state that they provide the first system to provide an integrated solution to consider interactions between different stages of the manufacturing and distribution process. In their application they use integer program formulation to maximize profit while meeting demand within specified time segments. They get past an integer programming hurdle (introduced by the need to prevent order splitting) through the use of a number of heuristic “fixes” and are successful in scheduling orders along a single serial path. They do not take into consideration an environment where orders are processed in parallel departments which must then compete for shared constrained resources. Agnetis et al. (2004) also have an interesting problem where they present the goal of scheduling competing agents using a common resource. They use a set of nonpreemptive jobs to generate nondominating schedules which is a useful concept as this application also considers multiple jobs competing for a shared resource as one component of the stated problem. However the main focus for Agnetis et al. is to analyze the complexity of a number of scenarios where the objective function is to minimize the total weighted completion time and number of late jobs. They do not provide a solution or formulation to solve this problem, they merely analyze the complexity. Watanabe et al. (2001) seek to schedule product through a shipping sorter, treated as a finite capacity queue, which is used to hold product until all outbound orders are present at which point they are shipped. They accomplish this through the use of a genetic algorithm. The problem that Watanabe et al. presents is one where orders that are fed into this queue must be properly sequenced before entering the system in order to prevent the queue from becoming filled with partial orders which consume physical space on the shipping sorter which reduces its effectiveness. This problem is quite different from the one presented in the present application as their model does not consider the possibility of scheduling multiple queues of this nature in series nor does it consider the scheduling of jobs across parallel departments as part of their order sequencing objective. Chen and Vairaktarakis (2005) considers a situation where jobs are processed and then delivered to customers with no interim staging in an attempt to find a joint production and distribution schedule which optimizes an objective function. The stated goal of their objective function is to minimize the sum of the total distribution cost and a function measuring customer service. However, different from the problem for this application, Chen and Vairaktarakis do not consider an environment where the processing and distribution volumes are constrained. This is an aspect which is a necessity in this application. Lee et al. (1996) and Pinto and Grossmann (1998) both present mixed integer linear programming models for petroleum and chemical processing applications. In both applications the common goal is to schedule a multiple stage environment where there are elements of parallel processing functions set up in series. However different from our application, their applications did not deal with the situation where there is competition for constrained subsequent resources. Based on the available academic literature, a thorough evaluation of an environment where constrained parallel production competes for multiple levels of subsequent shared resources as found at Company B does not exist. In fact, the Company B operation is somewhat unique in how it mixes distribution with a heavy augmentation of light manufacturing and in how the change in product mix creates an increasingly more complex environment. We should also point out here that the product life cycle at Company B differs greatly from traditional “big box” retailers, as these companies schedule activities based on a much smaller set of variables. Scheduling parameters at a big box retailer is typically confined to container picks, no production activities and very traditional and stable product seasonalities. Likewise SKU volatility is typically low, product life cycles are long and there are few strict in store date requirements. However, it should be noted that one significant aspect of the big box retailers environment is similar to what is found at Company B, specifically the parallel picking environment which competes for shared subsequent resources which is manifested in the form of multiple picking “modules” which proceed to a high speed sorter which separates product by shipping lane. Even though the problem presented in this application exists in many companies today in one form or another, it is a problem that is often simply glossed over during discussions of operational improvement strategies. An example of this can be found in a white paper prepared by Dematic (formerly Rapistan), a premier logistics support/solutions provider which services large manufacturing companies. In their white paper they state that “ . . . A properly executed wave management strategy will decrease order fulfillment time, boost productivity, and lower operational costs. Wave management is all about balancing and optimizing the work presented to the distribution center to perform: proper mix of small and large orders in a wave, # of expected containers, # of diverts off the sorter, etc. . . . ” This statement (“ . . . balancing and optimizing work presented . . . # of diverts off the sorter . . . ”) sounds promising, but in reality we find that the scheduling software packages available on the market today are either ERP tools which depend on a well disciplined delivery schedule or tools which treat subsequent constraints as time delays with infinite capacity. Given this, it is clear that what is absent is a short range planning solution that schedules discrete jobs to parallel picking/processing departments while allowing preferred departments by job, in addition to taking into consideration that these parallel departments compete for subsequent shared resources (merge and sortation points) which have finite capacity. The solution would preferably include an improved level loading of the workload which reduces the cost of labor and increases available capacity, and would preferably be easily adaptable to a variety of organizations with similar short range scheduling needs.	<SOH> SUMMARY <EOH>In carrying out the principles of the present invention, a short range planning solution is provided which schedules discrete jobs to parallel picking/processing departments while allowing preferred departments by job, in addition to taking into consideration that these parallel departments compete for subsequent shared resources (merge and sortation points) which have finite capacity. One example is described below in which the key problem is formulated as a mixed integer program model with a primary objective of minimizing the total processing and transportation costs, and a secondary goal of balancing the workload throughout the planning horizon. Some unexpected benefits from this model include an improved level loading of the workload which reduces the cost of labor and increases available capacity, and an easy adaptability to other organizations with similar short range scheduling needs. In one aspect, a scheduling model is provided for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments, and the departments share finite capacity resources. The model preferably includes a programmable computer system having loaded therein an objective function, and the computer system being operable to minimize a value of the objective function. The objective function comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting. The cost to ship containers in at least one of consolidated and unconsolidated forms may be represented in the objective function by the expression P 1  ∑ k = 1 n   ∑ i = 1 r   X i , k , j   1 + P 1  ∑ k = 1 n   ∑ i = 1 r   ∑ j ∈ j   2   X _ i , k , j wherein P 1 is a shipping cost per container, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, X i,k,j1 is a number of containers of job k processed in a selected merge department j 1 during shift i, X i,k,j is a number of containers of job k diverted direct to shipping from department j during shift i, and j 2 is a subset of departments including the selected departments. The cost for each of a container equivalent not completed in a selected scheduling horizon may be represented in the objective function by the expression ∑ k = 1 n   P 2  C k B k  ( B k - ∑ j ∈ R   ∑ i = 1 r   Y ikj ) wherein P 2 is a cost of shipping by an alternative mode of transportation, C k is a number of containers to be generated by job k, B k is a number of pieces to be shipped in job k, Y ikj is a number of pieces of job k shipped during shift i in department j, and R is a set of picking and processing departments other than merging or sorting departments. The cost to process each job in each department may be represented in the objective function by the expression ∑ j ∈ R   ∑ k = 1 n   ∑ i = 1 r   ( d kj  Y ikj ) . wherein Y ikj is a number of pieces of job k shipped during shift i in department j, and d kj is a unit cost to process job k in department j. The cost for setup due to at least one of shift crossing and job splitting may be represented in the objective function by the expression P 3  ∑ k = 1 n   ∑ i = 1 r   M ik wherein P 3 is a setup cost accounting for labor needed to switch between jobs or shifts, and M ik is equal to 1 if job k is processed in shift i, and is equal to 0 if job k is not processed in shift i. These and other features, advantages, benefits and objects will become apparent to one of ordinary skill in the art upon careful consideration of the detailed description of representative embodiments of the invention hereinbelow and the accompanying drawings, in which similar elements are indicated in the various figures using the same reference numbers.	BACKGROUND The present invention relates generally to scheduling models and, in an embodiment described herein, more particularly provides a multi-tier cross-department scheduling model for order processing operations. A hypothetical Company B will be used herein to demonstrate the types of problems faced in typical complex order processing operations. Suppose, for example, that Company B is the industry leader in rentable DVD and game media with over 9,000 stores worldwide (over 5,600 in the United States including franchisees) and over $5.8 billion in annual revenue for fiscal year 2005 (over $3.9 billion in the United States including franchisees). The data used in this application is specific to the United States order processing and distribution operations and does not include any international activities. The DVD and electronic game industries are highly peculiar when compared to others as they are characterized by an extremely compressed life cycle due to the release date structure imposed by the movie studios and to the short active life span inherent in any entertainment media product. As such it is very customary to see a great majority of sales activity in the first week a specific title is offered with very little activity in subsequent weeks. The only exception to this pattern would be titles that have a seasonal aspect such as Holiday genre as the individual holidays approach (for example Horror movies as Halloween approaches) or if there are complimentary titles offered (such as a part 3 of a movie trilogy causing increased activity for parts 1 and 2). In this sense it is convenient to look at the industry as one with 52 distinct “seasons” as the new release offerings change on a weekly basis. We find from history that these weekly “seasons” have virtually no correlation with each other but there is a weak correlation to the calendar seasons. An example of the life cycle for a single product along with Company B's niche can be seen in the FIG. 1. It is important to notice that in both the theatrical release and the release on DVD the revenue decay curve is extremely steep. We find that a product's life cycle can also take multiple paths based on when/how it is being used. As seen in FIG. 2 a product can move from a high volume new release title (region I) to a low volume catalog title (region IV) through the normal decay curve. Also, when seasonal activity and complimentary titles are considered product can shift from low volume to high even for older titles (region IV to region II). Likewise some titles may never leave the low volume range even if it is a new release product (region III to region IV). History has shown that due to the continually changing product mix, the weekly aggregate volumes can drop to as low as 50% from one week to the next or can just as easily double. Forecasting this change in volumes is difficult as each new product is truly a new release with no history, forcing the industry to predict activity based on historical performance of “similar products” as well as product performance in theatrical venues. However, even the best models result in a high degree of error. To accommodate the supply chain requirements of this highly specialized industry, logistic networks in the game and DVD rental industry have adopted methods and processes that are flexible enough to handle this extreme level of volatility while creating methods and processes that are robust enough to virtually eliminate late product deliveries. This is critical in this industry as with a nearly nonexistent maturity/decline phase in the product life cycle, any delays in product delivery would have the net effect of eliminating any potential for revenue to be gained from the product. Simply stated, any late deliveries have a tremendous cost impact. Company B, as an industry leader has pioneered many of the initiatives necessary to remain competitive in this arena. Focusing specifically on Company B's distribution organization we can see in the process flow diagram shown in FIG. 3 that Company B has developed a system of 12 picking/processing departments followed by a total of 9 merge/sortation points in addition to a recursive product infeed as the cornerstone for its distribution model. This process flow diagram represents picking and processing departments denoted by a “P” (P1, P2, etc.), conveyor merge points denoted by an “M”, and system sortation points denoted by an “S.” Picking and production activities include activities that range from simple retail picking to light manufacturing where raw discs and artwork (received in bulk) are built into the rental units as found in Company B stores. Conveyor merge points are used to route multiple conveyor lines to a single conveyor, and sortation points are used to route containers from a single conveyor line to multiple lines/departments. Here (FIG. 3) sortation point S1 is being used to sort outbound containers direct to individual shipping doors and sortation point S2 is being used to sort orders that have been picked/processed to locations in the consolidation department (M3). Ideally all product would flow through Merge 3 (M3) and would exit the system through sorter 1 (S1) using the recursive infeed through Merge 2 (M2) as shown by the bold arrows in FIG. 3. If capacity constraints were exceeded at any of the merge/sortation points along the process we would expect product to exit the system as the capacity constraints were encountered (for example at M1, M2, S1, S2, M3, etc.), thereby bypassing subsequent system constraints. This “system bypass” potential is shown on FIG. 3 by the arrows at the merge/sortation points labeled as Xi,k,M1, Xi,k,M2, Xi,k,S1, Xi,k,S2, Xi,k,M3. The system bypass potential is undesirable as doing so would prevent containers from taking advantage of the consolidation process at merge point M3 which yields a much lower system cost by reducing the number of containers shipped. The nature of this consolidation relationship (merge M3) will be discussed more thoroughly below. As cumbersome as these process flow diagrams appear, these are the result of multiple planned process improvement initiatives which are strategically designed to maximize throughput, while maintaining a very high level of flexibility and service level execution. In reality this process flow diagram is similar to environments that can be found at large “big box” retailers and package delivery companies. Once orders are produced either through picking or manufacturing and exit the conveyor system, outbound containers are shipped to stores primarily through a pool point network of over 40 regional pool points. These regional pool points crossdock containers from the Company B distribution center to the stores. As Company B maintains one distribution facility and ships to over 5,600 stores within the United States, this “hub and spoke” design has proven to be more cost effective than creating multiple distribution facilities or shipping direct to stores. It should be noted that shipping by pool point adds additional constraints (as each pool point location has a set weekly trailer departure schedule regardless of volume), and complexity (through having to coordinate with multiple carriers and pool point operators as they are regional in nature), with the trade off of a greatly reduced cost per piece shipped. The transit time from the distribution center to an individual store ranges from 2 to 7 days using the pool point shipping method (depending on region being shipped to) versus 1 to 5 days using other direct to store methods. Expense of shipping product using pool points is a fixed cost per container and is contract dependent. For purposes of illustration, we will use an estimated cost of $2.50 per container shipped via pool point (independent of container dimension) and $6.00 as an estimated charge per container if the shipment is made direct to store (dependent on container dimension). Although we can already see the benefit here of using the pool point network ($2.50 vs. $6.00 per container), we will see during the problem formulation that the true benefit when combining pool points with a consolidation process dwarfs these initial cost savings. From a complexity standpoint, a typical week in this environment can experience as many as 400 jobs which must be worked across 12 processing departments where individual jobs may be completed in anywhere from 1 to 5 different departments depending on job requirements which must then compete for capacity in up to 9 subsequent shared resources. The operating schedule consists of two 12 hour shifts per day across 6 days per week for a total of 12 shifts per week. As breaks, lunches, shift start up meetings, etc. must also be considered, we can normally assume 10.5 available production hours per employee per shift. Jobs that can be completed in multiple departments may experience higher processing costs in some departments over others. Roughly 5% of the overall demand is based on point of sale activity and 95% is based on forecasted allocation. Even though the 95% forecasted allocation is deterministic, the detailed planning window is still very short due to the nature of the business resulting in the need for a very flexible and dynamic solution. Until now, the planning tools available at Company B were confined to the following— 1. A long range model (3-18 months) which plans aggregate activity for budgeting purposes; 2. An intermediate range model (1-3 months) which plans aggregate capacity by department (excluding merge/sortation constraints); and 3. A short range tactical model (1 week) which plans aggregate capacity by department (excluding merge/sortation constraints) including labor planning As a result of these three planning tools used at Company B, their distribution operation has been characterized by intermittent situations where capacity limits at critical nodes in the production and product handling processes have been exceeded due to unexpected activity spikes. Visibility to these activity spikes are typically known up to a couple of days in advance but as all scheduling previously took place in aggregate their ability to effectively control the operation at the discrete job level did not exist. This resulted in additional transportation costs, poor system utilization and a high cost of labor. This problem as described at Company B is common in practice but has yet to be treated. Not only are there no available software packages on the market to address this problem, but there is also no available theoretical research on this topic. There exists a great deal of literature regarding scheduling theory (Pinedo, 2002; Graves, 1981), most of which does not sufficiently address the problem stated above. Likewise, there is existing literature regarding scheduling models applied in practice (Brown et al. 2002; Moss et al. 2000; Olson et al. 2000) which, again, are different from the problem addressed in this application. Dobson et al. (2001) deal with the problem of minimizing the scheduling cost (defined as the product of the holding cost and the flow time of a particular batch) which they state is similar to a weighted flow time. In doing so Dobson et al. consider an environment where jobs are organized into batches which must then be processed through a processing center. This is typical of many scheduling examples, however it does not consider parallel processing centers which must then compete for subsequent processing capacities. Similarly, Kuchta et al. (2004) uses mixed integer programming to schedule parallel operations to maintain consistent output. Here their objective function is to minimize the sum of the excess production and the deficit production volume (not the net difference but rather the sum of “absolute values”). However, their approach does not address competition between multiple production departments which compete for shared downstream capacities. Chen and Pundoor (2006) considers four problems with different cost related objective functions and assumes product that is time sensitive, with high variety, short life cycle and schedules them through parallel processing sites with a transportation cost. In this example Chen and Pundoor addresses an environment much more similar to what we find in this application (scheduling across production departments in parallel) but again stops short of addressing the possibility of the parallel departments competing for subsequent resources. Keskinocak et al. (2002) state that they provide the first system to provide an integrated solution to consider interactions between different stages of the manufacturing and distribution process. In their application they use integer program formulation to maximize profit while meeting demand within specified time segments. They get past an integer programming hurdle (introduced by the need to prevent order splitting) through the use of a number of heuristic “fixes” and are successful in scheduling orders along a single serial path. They do not take into consideration an environment where orders are processed in parallel departments which must then compete for shared constrained resources. Agnetis et al. (2004) also have an interesting problem where they present the goal of scheduling competing agents using a common resource. They use a set of nonpreemptive jobs to generate nondominating schedules which is a useful concept as this application also considers multiple jobs competing for a shared resource as one component of the stated problem. However the main focus for Agnetis et al. is to analyze the complexity of a number of scenarios where the objective function is to minimize the total weighted completion time and number of late jobs. They do not provide a solution or formulation to solve this problem, they merely analyze the complexity. Watanabe et al. (2001) seek to schedule product through a shipping sorter, treated as a finite capacity queue, which is used to hold product until all outbound orders are present at which point they are shipped. They accomplish this through the use of a genetic algorithm. The problem that Watanabe et al. presents is one where orders that are fed into this queue must be properly sequenced before entering the system in order to prevent the queue from becoming filled with partial orders which consume physical space on the shipping sorter which reduces its effectiveness. This problem is quite different from the one presented in the present application as their model does not consider the possibility of scheduling multiple queues of this nature in series nor does it consider the scheduling of jobs across parallel departments as part of their order sequencing objective. Chen and Vairaktarakis (2005) considers a situation where jobs are processed and then delivered to customers with no interim staging in an attempt to find a joint production and distribution schedule which optimizes an objective function. The stated goal of their objective function is to minimize the sum of the total distribution cost and a function measuring customer service. However, different from the problem for this application, Chen and Vairaktarakis do not consider an environment where the processing and distribution volumes are constrained. This is an aspect which is a necessity in this application. Lee et al. (1996) and Pinto and Grossmann (1998) both present mixed integer linear programming models for petroleum and chemical processing applications. In both applications the common goal is to schedule a multiple stage environment where there are elements of parallel processing functions set up in series. However different from our application, their applications did not deal with the situation where there is competition for constrained subsequent resources. Based on the available academic literature, a thorough evaluation of an environment where constrained parallel production competes for multiple levels of subsequent shared resources as found at Company B does not exist. In fact, the Company B operation is somewhat unique in how it mixes distribution with a heavy augmentation of light manufacturing and in how the change in product mix creates an increasingly more complex environment. We should also point out here that the product life cycle at Company B differs greatly from traditional “big box” retailers, as these companies schedule activities based on a much smaller set of variables. Scheduling parameters at a big box retailer is typically confined to container picks, no production activities and very traditional and stable product seasonalities. Likewise SKU volatility is typically low, product life cycles are long and there are few strict in store date requirements. However, it should be noted that one significant aspect of the big box retailers environment is similar to what is found at Company B, specifically the parallel picking environment which competes for shared subsequent resources which is manifested in the form of multiple picking “modules” which proceed to a high speed sorter which separates product by shipping lane. Even though the problem presented in this application exists in many companies today in one form or another, it is a problem that is often simply glossed over during discussions of operational improvement strategies. An example of this can be found in a white paper prepared by Dematic (formerly Rapistan), a premier logistics support/solutions provider which services large manufacturing companies. In their white paper they state that “ . . . A properly executed wave management strategy will decrease order fulfillment time, boost productivity, and lower operational costs. Wave management is all about balancing and optimizing the work presented to the distribution center to perform: proper mix of small and large orders in a wave, # of expected containers, # of diverts off the sorter, etc. . . . ” This statement (“ . . . balancing and optimizing work presented . . . # of diverts off the sorter . . . ”) sounds promising, but in reality we find that the scheduling software packages available on the market today are either ERP tools which depend on a well disciplined delivery schedule or tools which treat subsequent constraints as time delays with infinite capacity. Given this, it is clear that what is absent is a short range planning solution that schedules discrete jobs to parallel picking/processing departments while allowing preferred departments by job, in addition to taking into consideration that these parallel departments compete for subsequent shared resources (merge and sortation points) which have finite capacity. The solution would preferably include an improved level loading of the workload which reduces the cost of labor and increases available capacity, and would preferably be easily adaptable to a variety of organizations with similar short range scheduling needs. SUMMARY In carrying out the principles of the present invention, a short range planning solution is provided which schedules discrete jobs to parallel picking/processing departments while allowing preferred departments by job, in addition to taking into consideration that these parallel departments compete for subsequent shared resources (merge and sortation points) which have finite capacity. One example is described below in which the key problem is formulated as a mixed integer program model with a primary objective of minimizing the total processing and transportation costs, and a secondary goal of balancing the workload throughout the planning horizon. Some unexpected benefits from this model include an improved level loading of the workload which reduces the cost of labor and increases available capacity, and an easy adaptability to other organizations with similar short range scheduling needs. In one aspect, a scheduling model is provided for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments, and the departments share finite capacity resources. The model preferably includes a programmable computer system having loaded therein an objective function, and the computer system being operable to minimize a value of the objective function. The objective function comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting. The cost to ship containers in at least one of consolidated and unconsolidated forms may be represented in the objective function by the expression P 1  ∑ k = 1 n   ∑ i = 1 r   X i , k , j   1 + P 1  ∑ k = 1 n   ∑ i = 1 r   ∑ j ∈ j   2   X _ i , k , j wherein P1 is a shipping cost per container, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Xi,k,j1 is a number of containers of job k processed in a selected merge department j1 during shift i, Xi,k,j is a number of containers of job k diverted direct to shipping from department j during shift i, and j2 is a subset of departments including the selected departments. The cost for each of a container equivalent not completed in a selected scheduling horizon may be represented in the objective function by the expression ∑ k = 1 n   P 2  C k B k  ( B k - ∑ j ∈ R   ∑ i = 1 r   Y ikj ) wherein P2 is a cost of shipping by an alternative mode of transportation, Ck is a number of containers to be generated by job k, Bk is a number of pieces to be shipped in job k, Yikj is a number of pieces of job k shipped during shift i in department j, and R is a set of picking and processing departments other than merging or sorting departments. The cost to process each job in each department may be represented in the objective function by the expression ∑ j ∈ R   ∑ k = 1 n   ∑ i = 1 r   ( d kj  Y ikj ) . wherein Yikj is a number of pieces of job k shipped during shift i in department j, and dkj is a unit cost to process job k in department j. The cost for setup due to at least one of shift crossing and job splitting may be represented in the objective function by the expression P 3  ∑ k = 1 n   ∑ i = 1 r   M ik wherein P3 is a setup cost accounting for labor needed to switch between jobs or shifts, and Mik is equal to 1 if job k is processed in shift i, and is equal to 0 if job k is not processed in shift i. These and other features, advantages, benefits and objects will become apparent to one of ordinary skill in the art upon careful consideration of the detailed description of representative embodiments of the invention hereinbelow and the accompanying drawings, in which similar elements are indicated in the various figures using the same reference numbers. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a notebook computer embodying principles of the present invention; FIG. 2 is an enlarged scale cross-sectional view through the computer, taken along line 2-2 of FIG. 1; FIG. 3 is a top plan view of the computer illustrating a bottom surface of an input device in the computer; FIG. 4 is an isometric view of a computer input device embodying principles of the present invention illustrating a keyboard orientation; and FIG. 5 is an isometric view of the computer input device illustrating a digitizer orientation. DETAILED DESCRIPTION It is to be understood that the various embodiments of the present invention are described herein merely as examples of useful applications of the principles of the invention, which is not limited to any specific details of these embodiments. The principles of the invention will be described below as applied to the scheduling problems of the hypothetical Company B. Of course, the specifics of the Company B operation and the manner in which the principles of the invention are described as applying to the associated scheduling problems do not limit the applicability of the principles of the invention to other scheduling problems experienced by other companies. As discussed above, Company B is a leader in the rental DVD and game media industry, and has developed a highly specialized distribution network. Company B operates in an environment where there is a high SKU base, and product is time sensitive with an extremely short life cycle. The SKU base and volume is highly volatile from week to week and there are short lead times due to manufacturing delays from the suppliers. To accommodate this, Company B maintains a single source distribution network where these products are processed and packed for shipping to over 5,600 stores across the United States based on a demand forecast. Thus, Company B must schedule these processing and packing operations through a variety of parallel departments which compete for subsequent merge conveyors and sortation system so that business and store service level requirements are met with a primary objective of minimizing the total processing and transportation costs with a secondary objective of balancing workload throughout the planning horizon. To address this and other similar problems, we provide here the creation of a short range scheduling model which uses mixed integer programming techniques, and which is expected to result in substantial annual cost savings in addition to an increased system capacity as compared to current methods. This model is programmed in the AMPL programming language using a CPLEX version 10.1 mathematical formula solver, although other programming languages and mathematical formula solvers may be used if desired. As the need and desire to continually reduce costs while maintaining capacities is a common thread across all supply chain practitioners, we also discuss the adaptability of this model to other organizations as this system of multiple processing departments which must then compete for subsequent shared constraints is very typical in industry. Additionally, to the best of our knowledge, this is to be the first model developed in theory and in practice to address a multiple department scheduling environment which competes for shared subsequent processing capacities and we are the first to implement such a mixed integer model in practice. Formulating this problem involves the creation of a mixed integer program. Our main focus is on identifying how many containers (Xikj) are produced of a particular product in a particular department on a given shift (similarly for pieces produced as denoted by Yikj) so as to minimize the cost of producing and transporting the product through effective system utilization. Departments in this application will refer to picking/processing departments as well as process merge and sortation points, and a job will refer to any request for picking/processing activity encompassing single and multiple products. A summary of the basic notations used is as follows. Xikj=number of cartons of job k processed in department j during shift i in cartons/shift, Xikj=number of cartons of job k diverted direct to shipping from department j during shift i in cartons/shift, Yikj=number of pieces of job k processed during shift i in department j, N k = { 1   if   job   k   processed   in   primary   processing   department 0   otherwise   ( processed   in   secondary   processing   department ) ,  M i , k = { 1   if   job   k   processed   on   shift   i 0   otherwise  , S=Lower bound for total cartons created by shift, T=Upper bound for total cartons created by shift, Ck=number of cartons to be generated by job k, Bk=number of pieces to be processed in job k, dkj=unit cost to process job k in picking/processing department j in dollars/piece, pkj=processing time of job k in picking/processing department j in hours, rkj=pick/processing rate for job k in picking/processing department j in pieces/hour, ai=scaling value to adjust department M3 capacity by shift to accommodate purge activities, e=parameter expressing the maximum staffing level allowed per shift, qik=indicator parameter introduced to allow job k to be completed on specific shifts only, bk=indicator parameter used to allow job k to bypass the normal product flow, i=shift (1, . . . , r, r=scheduling horizon utilized in number of shifts), j=pick/processing department (1, . . . , m, m=21 departments, including merge/sortation points), k=job (1, . . . , n, n=number of jobs), j is a number indicating a department. For purposes of clarity j will be replaced by a department name if the context is specific to one department only (such as M3, S2, etc). This notation is used interchangeably. R=set of picking/processing department excluding merge/sortation points. Let set Q(k)=P(k)∪S(k) where P(k) is the set of primary processing departments for job k and S(k) is the set of secondary processing departments for job k. It is noteworthy to point out that Xikj, Xikj, Yikj, Nk, Mik, S, T are variables, Ck, Bk, dkj, pkj, rkj, ai, e, qik, bk are parameters which are known and i, j, k are indices. At Company B there are up to 12 shifts per week (2 per day at 6 days per week), picking and processing departments range from 1, . . . , 12 and total departments including merge and sortation points (j) range from 1, . . . , 21. We then formulate an objective function (Equation (1)) which seeks to minimize the total cost of manufacturing, handling and shipping. It is helpful to refer back to FIG. 3 when reviewing the formulation. Min   P 1  ∑ k = 1 n   ∑ i = 1 r   X i , k , j   1 + P 1  ∑ k = 1 n   ∑ i = 1 r   ∑ j ∈ j   2   X _ i , k , j + ∑ k = 1 n  P 2  C k B k  ( B k - ∑ j ∈ R   ∑ i = 1 r   Y ikj ) + ∑ j ∈ R   ∑ k = 1 n   ∑ i = 1 r   ( d kj  Y ikj ) + P 3  ∑ k = 1 n   ∑ i = 1 r   M ik . ( 1 ) In this paper for Company B we shall define P1=2.5 P2=6.0 P3=20.0 j1ε{M3} j2ε{M1, M2, M3, S1, S2} We can better understand the meaning of this objective function if we review it in parts. Here, as applied to the Company B problem, the first part 2.5  ∑ k = 1 n  ∑ i = 1 r  X i , k , M   3 + 2.5  ∑ k = 1 n  ∑ i = 1 r  ( X _ i , k , M   1 + X _ i , k , M   2 + X _ i , k , S   1 + X _ i , k , S   2 + X _ i , k , M   3 ) , represents the cost to ship containers either in their consolidated form or unconsolidated direct from a merge/sortation point. Xikj represents the number of consolidated containers shipped at a cost of $2.50 per container (value given above as an estimated cost of using Company B's pool point transportation network) and the series of Xikj variables represents the number of containers shipped direct from a merge/sortation point without the benefit of consolidation. The nature of this relationship (consolidated versus unconsolidated) will be explained in greater detail once we begin discussing Constraint (9). The second part of the objective function ∑ k = 1 n  6.0  C k B k  ( B k - ∑ j ∈ R  ∑ i = 1 r  Y ikj ) + ∑ j ∈ R  ∑ k = 1 n  ∑ i = 1 r  ( d kj  Y ikj ) + 20.0  ∑ k = 1 n  ∑ i = 1 r  M ik , shows three additional cost components which have been added to preference the desired solution based on activity costs. The first component calculates an estimated container equivalent (Ck/Bk) of any piece volume not completed (Bk−ΣΣYikj) in the given scheduling horizon of r shifts. Here a cost penalty of $6.00 per container is used (again, presented above as an estimated cost of shipping direct to stores using an alternative mode of transportation) for each container equivalent not completed in the given planning horizon. The second component (ΣΣΣdkjYikj) represents the cost to process job k in the department jεR. This is important as we allow a job to be produced in multiple departments (primary where the cost is lowest, secondary where the cost is higher). This option is the result of assigning primary processing departments for each job as well as maintaining a secondary overflow department for select departments in the event capacity maximums are hit. The third and last component of the objective function (20.0Mik) represents a job/shift setup cost which accounts for the labor needed to switch over from picking or processing for one job to the next. As this model allows jobs to be processed across multiple shifts, this last component adds a penalty if unnecessary shift “crossing” or job splitting occurs. For purposes of confidentiality, we use a value of $20.0 for each job change over which is different from the actual value. Next we have the beginning of a set of balance equations (Constraints (2) through (9) in the Appendix A) which are used to ensure that product entering each of the merge/sortation nodes from a preceding picking/processing/merge/sortation equates to what leaves these nodes. Each of the balance equations are consistent with the product flows as shown in FIG. 3 and only Constraint (9) will be discussed explicitly here as this is where the true benefit of utilizing the consolidation function appears. 6aiXi,k,M3+ Xi,k,M3=Xi,k,S2 ∀i,k. (9) As we can see in Constraint (9), allowing containers to follow the path that flows through Xi,k,M3 results in a 6:1 reduction (compression) in the number of containers shipped through sortation point S1 if we ignore the scaling parameter ai (this parameter will be discussed in detail shortly). Merge point M3 is the only point where this reduction in container volume takes place in this system and from the objective function formulation, maximizing flow through this point will have a significant effect on minimizing the system cost. In practice, merge point M3 functions as a large physical container queue where multiple orders for a single destination are staged until either 6 containers are held in queue or until right before a pool point departure takes place, at which point a “purge” is generated. The value of 6 containers was selected due to the physical size of the queue in relation to the number of destinations shipped to. Once a purge is generated the contents of all containers held in queue are placed into a single large shipping container. This effect is particularly important as we discussed above that the pool point charge per container was a fixed rate. When combined, the 6:1 compression rate and the fixed cost per container shipped effectively generates a ⅙ cost per container adjustment for product shipped. In essence this further reduces the shipping cost of a $2.50 container to $0.416. The scaling parameter ai was introduced above to more appropriately represent the inter-shift dynamics present in the consolidation process. As consolidation purges can take place before the six container threshold is reached, this additional purge has the net effect of reducing the compression ratio which the ai parameter is intended to simulate. As we can see from historical data in FIG. 4 this compaction ratio at merge point M3 for a 3 month period from Sep. 21, 2006 through Dec. 23, 2006 maintains some consistency by shift with an upper bound of 6.0. As the model has been created for a compaction ratio of 6.0 and if we are to assume that the actual compaction ratios by shift follows the bold line (mean compaction ratio by shift in FIG. 4) then we can expect to experience ai values by shift as shown in Table 1. These values for ai range anywhere from 0.72 to 0.98, where a lower scaling factor would indicate less than a 6:1 compression implying an increase in early purges due to pool point departures. TABLE 1 Scaling Parameter ai Values by Shift. Shift Compaction Ratio ai 1 5.50 0.92 2 5.30 0.88 3 5.90 0.98 4 5.50 0.92 5 5.90 0.98 6 5.80 0.97 7 5.50 0.92 8 5.30 0.88 9 5.00 0.83 10 4.90 0.82 11 4.30 0.72 12 5.00 0.83 Looking at the flow constraints shown on FIG. 3 we can now intuitively expect that the merge point M3 constraint at 35 containers per hour is a likely primary system bottleneck as it is at the end of the system, has one of the lowest throughput capacity constraints and experiences a cyclic pattern of reduced container compaction based on ongoing shipping activity, all of which we find to be true. Based on this it would be desirable to level load the activity at the node as much as possible to thoroughly utilize its capacity. In the absence of the scaling factor ai which varies by shift we could simply focus on balancing the number of containers entering or exiting merge point M3. However, as we do have the scaling factor ai to consider, and as it varies by shift which causes the inbound/outbound ratio at merge point M3 to vary by shift as well, we must now seek to balance the total flow at merge point M3 as shown in FIG. 5. From FIG. 5 it is clear that any container flow through merge point M3 (in to and out of) must be planned to be as level loaded as possible across the multiple shift planning horizon in order to best utilize the capacity at this merge point. To accomplish this we define two variables, S and T, to represent arbitrary upper and lower bounds for the number of containers being planned through this point as shown in Constraints (10) and (11). Constraint (12) is then used to maintain this window between upper and lower bounds at an acceptable level. S ≤ ∑ k = 1 n  ( X i , k , M   3 + X _ i , k , M   3 + X i , k , S   2 )  ∀ i , ( 10 ) T ≥ ∑ k = 1 n  ( X i , k , M   3 + X _ i , k , M   3 + X i , k , S   2 )  ∀ i , ( 11 ) T - S ≤ 500. ( 12 ) As the total volume at merge point M3 can reach 25,200 containers per 12 hour shift (based on the constraint of 35 containers per minute) we can see that this 500 container window as shown in Constraint (12) will allow at most a 2% variation from shift to shift which is deemed by management to be acceptable as they currently experience an average shift to shift variation of 22.7%. This reduction in volume volatility at merge point M3 will be of great benefit in reducing labor costs as well as increasing available capacities which will be discussed below. Following this we have an array of system constraints (Constraints (13) through (41) found in Appendix A) which are used to ensure that capacity violations across any processing/picking/merge/sortation departments are not violated. Our next step is to require jobs to be completed in either their primary or secondary processing departments. This is achieved through introducing the Nk integer variable where we allow Nk=1 if it is completed in its primary processing department and Nk=0 otherwise. This can be seen in Constraints (42) and (43). In using this indicator variable we state that the product CkNk (where Ck is the total containers to be produced for job k) cannot be less than the number of containers produced (Xikj) for job k in department j across all shifts. Given this, job k is either produced Xi,k,j≦CkNk jεP(k) ∀i,k, where P(k) is a set of primary processing department for job k, (42) Xi,k,j≦Ck(1−Nk) jεS(k) ∀i,k, where S(k) is a set of secondary processing department for job k. (43) entirely in its primary department or entirely in its secondary processing department. Similarly, in Constraints (44) and (45) we require that pieces processed for each job takes place in either its primary or secondary processing department and not both. Here Yikj is the pieces for job k processed in department j during shift i and Bk is the total pieces to be produced for job k. Yi,k,j≦BkNk jεP(k) ∀i,k, where P(k) is a set of primary processing department for job k, (44) Yi,k,j≦Bk(1−Nk) jεS(k) ∀i,k, where S(k) is a set of secondary processing department for job k. (45) Now that jobs are assigned to specific departments, they need to be assigned to specific shifts. To do this we introduce the Mik integer variable in Constraint (46), where Mik=1 if job k is performed on shift i and Mik=0 otherwise, and state that the product CkMik (number of containers for job k completed on shift i) cannot be less than the sum of the containers produced across all departments for each shift and job (Xikj). We then perform a similar operation for pieces produced as shown in Constraint (48). At this point we also see a new parameter qik which is used to allow work to be completed on specific shifts based on the business needs, where qik takes on the value of 0 or 1 (a qik value of 1 stating a job can be performed on a specific shift and a value of 0 stating the job cannot take place). The inclusion of a parameter such as qik is important in order to accommodate rush orders and specialized scheduling requirements. To limit the number of shifts a job can be performed on to a maximum of 2 shifts (again based on business requirements which will be explained in the implementation section) we have added Constraint (47) which states that the sum of the indicator variable Mik across all shifts in the planning horizon must not be greater than 2. ∑ j ∈ Q  ( k )  X i , k , j ≤ C k  M i , k  q ik  j ∈ Q  ( k )  ∀ i , k , ( 46 ) ∑ i = 1 r  M i , k ≤ 2  ∀ k , ( 47 ) ∑ j ∈ Q  ( k )  Y i , k , j ≤ B k  M i , k  q ik  j ∈ Q  ( k )  ∀ i , k . ( 48 ) In Constraint (47) the value of a 2 shift maximum was used because that was most appropriate at Company B. In other applications this number may be varied based on the application requirements. Our next step is to ensure that if a job must be performed on multiple shifts that the shifts are consecutive to prevent unnecessary long term staging of orders and job change over time. To accomplish this we use the following logic assuming a 12 shift scheduling horizon. M 1 , k + M 3 , k ≤ 1  ∀ k ,  M 1 , k + M 4 , k ≤ 1  ∀ k ,  M 1 , k + M 5 , k ≤ 1  ∀ k ,   ⋮ M 1 , k + M 12 , k ≤ 1  ∀ k ,  M 2 , k + M 4 , k ≤ 1  ∀ k ,  M 2 , k + M 5 , k ≤ 1  ∀ k ,  M 2 , k + M 6 , k ≤ 1  ∀ k ,   ⋮ M 2 , k + M 12 , k ≤ ∀ k ,   ⋮ M 10 , k + M 12 , k ≤ 1  ∀ k . Using this methodology, a job that is completed across multiple shifts is forced to be worked on consecutive shifts. If we were to state all necessary constraints in this manner for a 12 shift operation we would require 55 additional constraints. In Appendix A we can see additional constraints which are used to ensure a shift's production capacity in a given department is not exceeded (Constraint (60)), that the pieces produced in a given shift (Yikj) cannot exceed the available work (Bk), and that the containers produced in a given shift (Xikj) cannot exceed the available work (Ck) which are shown in Constraints (61) and (62), respectively. Lastly, we must ensure that the ratio of pieces completed per shift matches favorably with the containers completed per shift for each job and department. If we were to not control this explicitly we found that results ended up with pieces being completed independent of containers which for example could result in 10% of the pieces produced in a given shift for a particular job, but with 90% of the container load completed for that same job in that same shift. This would not be appropriate. To address this we introduced Constraint (63) which requires the pieces per container ratio (Yikj/Xikj) to be bounded by the following limit: [Bk/Ck−0.5/Xikj, Bk/Ck+0.5/Xikj] in pieces per container. In this manner we now have a total piece window of +/−0.5 which is sufficiently tight. This constraint now provides that if a job was completed on multiple shifts, the ratio of pieces per container completed on one shift for a job is sufficiently close to the total pieces per container for that job. X ikj  ( B k C k ) - 0.5 ≤ Y ikj ≤ X ikj  ( B k C k ) + 0.5  ∀ i , k , j . ( 63 ) Data used in this model for parameters dkj (cost per piece to process), Pkj (processing time), rkj (pick/processing rate), Ck (number of containers generated) and Bk (number of pieces generated) are all outputs generated from a warehouse management system (WMS). It should be noted that although this raw data is readily available, neither the existing WMS package nor any competitive WMS packages currently on the market provide the functionality needed to address the problem presented in this application. Parameters ai are based on actual historical data and parameter e (maximum worker staffing allowed per shift) is based on historical/future constraints on maximum staffing levels that can be expected to be supported. A complete listing of the formulation developed in this application can be found in Appendix A. A conventional programmable computer system with CPLEX (version 10.1) was utilized to solve this problem with code written in AMPL, and with live data hypothetically pulled directly from the Company B warehouse management system (WMS) for testing. Doing this allowed us to assess the results of the formulation against a data set that had the variability it would encounter once implemented. As this scheduling model is a complex mixed integer program, we should not be surprised that the computational requirements grow exponentially as the number of shifts used in the planning horizon increases. In fact, we found that the computational speed (in seconds) using a 42 job data set comprised of 86,295 containers and 771,025 pieces which was planned for Dec. 13, 2006 night shift through Dec. 15, 2006 day shift (data set can be found in Appendix B) across the work landscape outlined earlier resulted in the computing times found in Table 2 with run time given in seconds with the objective function given in dollars. A variety of T-S values (range between the maximum and minimum containers processed through merge point M3) and planning horizons in number of shifts were used to illustrate the model sensitivity to these parameters. TABLE 2 Computational speed (run time in seconds) based on various shift and (T-S) values for Dec. 13, 2006 through Dec. 15, 2006 data set. (T-S) = 500 (T-S) = 1,000 (T-S) = 1,500 objective objective objective shifts run time function run time function run time function 4 22 81,110 40 81,064 39 81,018 5 381 81,745 162 81,691 560 81,639 6 1,561 82,175 4,397 82,115 1,963 82,052 7 60,476 82,486 39,714 82,414 79,253 82,353 8 NA NA NA NA NA NA As we can see in Table 2, when we defined the T-S value to be 500 with a 7 shift scheduling horizon, the computational time was 60,476 seconds, or roughly 16.8 hours, which involved 1,249,690 branch and bound nodes and 54,273,904 MIP simplex iterations and returned an objective function of $82,486. Schedules for this data set were not run across an 8 shift horizon due to the computing times involved. Understanding that the rates of increase for these computing times are exponential with regards to the number of shifts being planned across, routine planning for time periods over 6 shifts could become prohibitive. To improve the program run time without significantly affecting the optimality of the objective functions, we also ran the same model (in AMPL) with the same data set using CPLEX “options” (described below) which are designed to reduce computing times. Results of this model using CPLEX with options can be found in Table 3 with the options used as follows. ‘probe’—using this option prompts CPLEX to removes redundant variables and constraints in order to reduce the problem size before starting branch and bound algorithms. ‘mipgap’—this option terminates the search when the difference between the objective value is within a specified distance from the optimal value (  best   node - best   integer  1.0 +  best   node  ) < mipgap   value ‘repeatpresolve’—this option allows repeated presolves with cuts and allows new root cuts TABLE 3 Computational speed (run time in seconds) using CPLEX processing options based on various shift and (T-S) values for Dec. 13, 2006 through Dec. 15, 2006 data set. (T-S) = 500 (T-S) = 1,000 (T-S) = 1,500 objective objective objective shifts run time function run time function run time function 4 62 81,105 62 81,058 63 81,017 5 64 81,748 63 81,700 63 81,657 6 65 82,194 65 82,123 64 82,071 7 66 82,487 66 82,422 68 82,363 8 80 82,841 69 82,674 70 82,596 As we can see in Table 3, the computing times of this scheduling model has been greatly reduced. This result should not be surprising as the three options specified above work together to reduce the complexity and terminate the program when the solution is sufficiently close to the best solution. In comparing the objective function results from Table 2 to that of Table 3, we can also see the difference in objective function values as shown in Table 4. Here it is very easy to see that the difference in the normal CPLEX processing and the CPLEX processing with options yields nearly identical results with a worst case scenario of a $19 out of $82,175 (T-S value of 500 and 6 shifts) which differs by only 0.019% which is not significant in this application. When computing times are taken into consideration (66 seconds in Table 3 for T-S of 500 and 7 shifts versus 60,476 seconds in Table 2) it is clear that running this scheduling model in CPLEX using the options as shown above is preferred as the results are so close to optimal. TABLE 4 Difference in objective function values for data set Dec. 13, 2006 through Dec. 15, 2006 for Tables 2 and 3 based on various shift and (T-S) values. (T-S) Values shifts 500 1000 1500 4 0 0 0 5 −3 −9 −18 6 −19 −8 −19 7 −1 −8 −10 8 NA NA NA As the existing planning environment at Company B is highly volatile with jobs being added to the scheduling horizon daily, and as the typical visibility to what is able to be scheduled is confined to roughly 4 shifts worth of volume, we settled on running this application on a daily basis for a rolling 4 shift horizon. Additionally, to be usable in a real world application the formulation should be able to run in under 5 minutes which is easily accomplished as shown by the results in Table 3. As the importance of minimizing the inter-shift workload volatility at merge point M3 is paramount this also allows us to maintain a low (T-S) value of 500 when solving this problem. If a longer scheduling horizon were needed (such as a full 12 shift period), this model could be processed independently using forecasted data instead of actual orders. As visibility to discrete job workload is normally given for a 4 shift horizon only, a full 12 shift horizon could be planned as a rough plan through using the available longer range forecasts. Information from this rough planning would be valuable for identifying potential system capacity shortfalls in advance so that alternative solutions could be developed ahead of time. A sample of a 12 shift data set using forecasted data only can be found in Appendix C. In testing this 12 shift horizon from Appendix C using the CPLEX options as shown above we found that the model took 1,066 seconds (18 minutes) to run using a T-S value of 500 returning an objective function value of $241,655. Running the same model using CPLEX without options with the same data set and parameters this program took in excess of 73 hours. At 73 hours the program had to be terminated manually due to the tree size exceeding 2.4 gigabytes which exceeded the computer memory size (at this point the computer began using hard disc space as added memory which greatly slowed down the computing speed). Upon program termination the model had arrived at an objective function value of $241,618 with a MIP gap of 0.04% with a best node (not necessarily feasible) objective function value of $241,523. Given this, running CPLEX with options yielded a solution that was at worst 0.05% ($132) higher than the best possible (best node) solution at a computing time of only 18 minutes. Clearly this program can feasibly be applied in situations where a scheduling horizon much greater than the 4 shift window required at Company B is needed while returning a solution that is not significantly different from an optimal solution. Analyzing the results from the data found in Appendix B further, if we take the 42 job data set which was scheduled across the 4 shift period Dec. 13, 2006 night shift through Dec. 15, 2006 day shift we find that the results can be summarized in Table 5. Even though the maximum and minimum Xikj values at merge point M3 initially appear to exceed 500, considering the impact of the ai scaling parameter we can see the total workload at this point is being maintained as expected. Also notice that for containers we display results for the full set of departments j (including merge/sortation points), and for pieces processed we only display results for departments jεR (excluding merge/sortation points). TABLE 5 Summary results for workload planned Dec. 13, 2006 night shift through Dec. 15, 2006 day shift (see Appendix B for full data set). ΣX = Total number of cartons processed by department shift P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 1 0 0 14,082 0 4,156 2,348 463 0 0 0 2,769 0 2 0 0 10,019 1,826 0 1,249 1,907 3,484 0 0 2,043 1,915 3 0 1,179 9,318 557 0 0 0 5,805 0 0 3,358 1,711 4 0 8,129 0 0 0 0 0 9,041 0 0 936 0 Total 0 9,308 33,419 2,383 4,156 3,597 2,370 18,330 0 0 9,106 3,626 ΣX = Total number of cartons processed through each merge/sortation point shift M1 M2 M3 M4 M5 M6 M7 S1 S2 1 14,082 18,045 3,963 14,082 4,156 2,811 5,580 18,045 23,776 2 13,519 17,536 4,017 10,019 1,826 3,156 7,114 17,536 22,459 3 16,712 20,039 4,016 10,497 557 0 5,069 20,039 21,689 4 17,170 15,308 3,125 8,129 0 0 936 15,308 13,121 Total 61,483 70,928 15,121 42,727 6,539 5,967 18,699 70,928 81,045 ΣY = Total number of pieces processed by department shift P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 1 0 0 69,562 0 37,344 48,000 4,593 0 0 0 11,523 0 2 0 0 31,288 48,000 0 25,540 48,000 29,448 0 0 4,234 48,000 3 0 13,158 38,661 14,651 0 0 0 203,099 0 0 8,731 42,866 4 0 39,503 0 0 0 0 0 3,252 0 0 1,572 0 Total 0 52,661 139,511 62,651 37,344 73,540 52,593 235,799 0 0 26,060 90,866 Likewise in Table 6 we can see the raw data which comes directly from the AMPL program. Here we can see that all jobs have been scheduled to an available shift with only 4 jobs scheduled over multiple shifts, where a value of “1” indicates the job was scheduled for the shift. Although valuable, this information in its present form is very cumbersome and is not very useable by the operations group. We will display a more “user friendly” version of this data in the implementation section below. TABLE 6 Job schedule for workload planned Dec. 13, 2006 night shift through Dec. 15, 2006 day shift (see Appendix B for full data set). Mik Job Shift 1 Shift 2 Shift 3 Shift 4 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 1 14 1 1 15 1 16 1 17 1 18 1 19 1 20 1 21 22 1 1 23 1 1 24 1 25 1 26 1 27 1 28 1 29 1 30 1 31 1 32 1 33 1 34 1 35 1 36 1 37 1 38 1 39 1 40 1 41 1 42 1 During the implementation phase, while working with the Company B Production Planning department and the Operations Management teams, additional requirements were identified which are useful to provide solutions that better fit existing business requirements. A summary of key additional requirements are discussed below. 1. Several of the picking/processing departments had piece volume limitations in addition to the system imposed container constraints. As a result there needed to be piece volume limiting constraints in addition to those required by container. This resulted in the addition of Constraints (25a) and (32a) (found in Appendix A) which are identical to their respective container constraints (Constraints (25) and (32)) except that they are intended to address piece capacities at select department jεR for a given shift i. 2. As stated early in this application, merge point M3 was identified as the primary bottleneck which needed to be evaluated with regards to over capacity concerns. Initial problem formulation results yielded solutions which had highly variable volumes at this point at each shift (albeit below capacity) and it was deemed desirable to keep the throughput at this point as level loaded as possible. In order to minimize this volume fluctuation for constraint M3 across shifts, the limiting value of “T-S” was added (Constraints (10), (11), (12)). As T-S equates to the difference between the largest container volume at merge point M3 and the lowest, specifying explicitly that this value should be less than or equal to 500 added a level loading effect at this critical point. Once again, the value of 500 was selected because based on historical data it allowed at most a 2% variation from shift to shift which was deemed by management to be acceptable. 3. Initial formulation results provided solutions where there was a great imbalance between the ratio of pieces and the ratio of containers completed by shift for jobs that crossed shifts. This was found to be due to pieces being scheduled completely independent of containers as there was no tie between the piece completion rate by shift and that of the containers. As a result we found that we could arrive at a schedule where we could have 10% of the pieces produced in a given shift for a particular job, but with 90% of the container load completed for that same job in that same shift. This expectation was not appropriate. Constraint (63) was added to ensure that if a job was completed on multiple shifts, the ratio of pieces per container completed on one shift for a job was sufficiently close to the total pieces per container for that job. This is explained in detail in the formulation section where Constraint (63) is discussed. 4. During implementation jobs were found that needed to be completed on specific shifts only. This was largely due to certain rush orders which needed special handling or other special requirements. To accommodate this, the qik parameter was introduced with the Mik variable (integer variable which equates to 1 if job is k is performed on shift i and 0 otherwise) as shown in Constraints (46) and (48). Here the qik parameter takes on the value of “1” if job k is allowed to be performed on a specific shift i and takes on a value of “0” otherwise. 5. Similar to a job needing to be completed before the end of the scheduling horizon is the need to freeze capacity in specific departments and shifts. This need is a result of the high incidence of late arrival expedited work. To accommodate this requirement for “placeholders” for expected work, a technique of adding “dummy” jobs to the data file was used in conjunction with the qik parameter as shown in requirement #4 above. This effectively allowed expected work to be scheduled in the midst of known jobs. 6. On an intermittent basis there was the need to be able to force specific jobs to specific departments and/or shifts due to special job requirements. This need was handled through forcing Mik variable to take on the required values. As can be seen in Constraints (46) and (48) this would has the net effect of “turning off” individual shifts and departments as the need arises. 7. As Company B utilizes pool points for a majority of their outbound shipments to reduce cost, trailers ship to different regions on different days based on their in transit lead time. As a result of this, any containers that are held in queue in merge M3 immediately before a pool point departure (trailer departure) must be purged on a weekly basis before it has reached the 6:1 compression threshold to ensure that they meet their ship date. In practice we find that this purge activity can affect the capacity of this node by anywhere from 0% to 30% through the course of a single week. As a result of this, Constraints (9) and (41) were modified to add the scaling parameter ai which varies by shift depending on the purge activity level which better represents the actual environment. The parameter values for ai were derived from historical data and were found to range anywhere from 0.72 to 0.98 where the lower scaling factor would indicate less than a 6:1 compression ratio at merge point M3 implying more purges than would occur due to normal consolidation activity (purges taking place before 6 containers are collected in queue) and a value of 1.0 would represent a pure 6:1 compression ratio when there are no early purges. 8. As we must consider that the total number of available employees is a limiting factor, Constraint (60a) was added where on any given shift the hours utilized must be less than or equal to the product of e (parameter for the maximum number of people allowed per shift) and 10.5 (available hours per 12 hour shift taking into account breaks, lunches, start up meetings, etc.). If in time we find there is a need to further constrain the number of workers per shift per department (such as no more than 50 employees per shift for processing department P2), then we could simply add another parameter (such as ejmax) to Constraint (60) as shown below. Here we can see that ejmax represents the maximum allowed staffing for department j. ∑ k = 1 n  Y i , k , j r k , j ≤ 10.5  e j max , ∀ i , j 9. The initial problem formulation considered that the desired (ideal) state was to have all containers produced flow through merge M3 and follow the recursive infeed to exit the system through sortation point S1. However in a live environment we must also consider jobs where bypassing all internal merges is desired in order to accommodate planned expedited orders (due to short lead times, etc.). This requirement is handled by adding the constraint that the sum of the containers bypassed at points Xi,k,M1+ Xi,k,M2+ Xi,k,S1+ Xi,k,S2 is greater than or equal to the number of containers (Ck) for job k if the job k is identified as one that is required to bypass the normal product flow path. This can be seen by the introduction of the bk parameter in conjunction with Constraint (41a) (see Appendix A). In this manner intentional system bypasses can be handled. 10. As the intended users of this model have no integer/linear programming experience, the program input and output will need to be very user friendly stating which jobs are to be completed on which shift along with expected volumes and total worker staffing requirements by department. This requirement is needed to make the output useable and was accomplished using widely available conventional office suite software programs. As a result of the implementation we have been successful in generating shift production schedules for the distribution operation at Company B using the formulation described. This production schedule is run daily for a rolling 4 shift horizon and is used to specify which jobs are to be completed on each shift and in what quantity. As the bottlenecks are based on containers and department capacities are based on individual pieces processed, both are displayed on the production schedule. In Table 7 we see the shift production schedule by piece count in each shift, specified by a “wave name” which is synonymous with “job” in Company B nomenclature and is used interchangeably. This level of detail and simplicity of information makes it very useable by the distribution operations team. Once again, the source data set which was used to create both Table 7 and Table 8 can be found in Appendix B. Similarly, in Table 8 we can see the same schedule broken out by container count. As Company B employs a system throughput Gantt chart to track containers that pass through each department throughout each shift, this data helps management make tactical decisions by allowing them to identify where attention should be placed to help keep the flow within a shift as level as possible. This data is also useful for troubleshooting process constraint issues as well as granting management visibility of which jobs are expected to be primary volume contributors by shift. TABLE 7 Shift production schedule (piece count) - jobs by department and shift. Wed D Dec. 13, 2006 Thu B Dec. 14, 2006 Thu D Dec. 14, 2006 Fri B Dec. 15, 2006 Wave (Job) Pieces Wave (Job) Pieces Wave (Job) Pieces Wave (Job) Pieces P11 AFRR121302_APR 7,432 AFRE121102 17 AFRR121301_AFR 1,207 AFRR121306_AFR 1,572 AFRR121303_AFR 4,091 AFRR121305_AFR 4,217 AFRR121304_AFR 7,524 Total 11,523 4,234 8,731 1,572 P1 Total 0 0 0 0 P3 AFRR121301_CLU 4,575 AFRR121306_CLU 9,479 AFRR121304_CLU 23,549 AFRR121302_CLU 14,440 KSG1217C_CLU 20,945 AFRR121305_CLU 14,903 AFRR121303_CLU 7,641 KSI1214B_CLU 864 KEQ146350 209 KSGYL1217C_CLU 935 KSI1212C_CLU 83 PRP1211C 3,025 PRP1212A 528 PRP1215B 17,398 PRP1215D 17,910 PRPYL1215 3,027 Total 69,562 31,288 38,661 0 P6 DVD31212A 48,000 DVD31212A 25,540 Total 48,000 25,540 0 0 P7 DVD21212A 3,542 DVD11212A 48,000 DVD11212A 1,051 Total 4,593 48,000 0 0 P4 DVD41211A 48,000 DVD41211A 14,651 Total 0 48,000 14,651 0 P5 DVD51214B1 37,344 Total 37,344 0 0 0 P12 DVD21212C 48,000 DVD21212C 42,811 DVD51212C3 55 Total 0 48,000 42,866 0 P2 BSGYL1217C 935 BSG1217C 20,945 BSI1208001 1 MNG1213D 18,558 BSI1208002 103 BSI1214B 11,910 REQ146350 209 Total 0 0 13,158 39,503 P9 0 Total 0 0 0 0 P8 PMWN0729B 8 PMWN1213D 1,549 PMWN1213D2 3,252 PMWN1213D1 29,440 PMWNOL1213 201,550 Total 0 29,448 203,099 3,252 P10 Total 0 0 0 0 As an additional feature, the total employee staffing requirements at each of the picking/processing departments have been added to help distribution operation management maneuver the labor force to support the production plan and can be found in Table 9. We can see here that although the staffing at any department may vary greatly from shift to shift, in this example the total employee staffing requirements across all departments varies by at most 4.6%. TABLE 8 Shift production schedule (container count) - jobs by department and shift. Wed D Dec. 13, 2006 Thu B Dec. 14, 2006 Thu D Dec. 14, 2006 Fri B Dec. 15, 2006 Wave (Job) Cartons Wave (Job) Cartons Wave (Job) Cartons Wave (Job) Cartons P11 AFRR121302_AFR 1,596 AFRE121102 1 AFRR121301_AFR 746 AFRR121306_AFR 936 AFRR121303_AFR 1,173 AFRR121305_AFR 2,042 AFRR121304_AFR 2,612 Total 2,769 2,043 3,358 936 P1 Total 0 0 0 0 P3 AFRR121301_CLU 746 AFRR121306_CLU 1,872 AFRR121304_CLU 5,224 AFRR121302_CLU 3,192 KSG1217C_CLU 7,884 AFRR121305_CLU 4,084 AFRR121303_CLU 2,346 KSI1214B_CLU 263 KEQ146350 10 KSGYL1217C_CLU 316 KSI1212C_CLU 20 PRP1211C 1,272 PRP1212A 510 PRP1215B 2,560 PRP1215D 2,636 PRPYL1215 484 Total 14,082 10,019 9,318 0 P6 DVD31212A 2,348 DVD31212A 1,249 Total 2,348 1,249 0 0 P7 DVD21212A 421 DVD11212A 1,907 DVD11212A 42 Total 463 1,907 0 0 P4 DVD41211A 1,826 DVD41211A 557 Total 0 1,826 557 0 P5 DVD51214B1 4,156 Total 4,156 0 0 0 P12 DVD21212C 1,915 DVD21212C 1,708 DVD51212C3 3 Total 0 1,915 1,711 0 P2 BSGYL1217C 158 BSG1217C 3,942 BSI1208001 1 MNG1213D 4,187 BSI1208002 13 BSI1214B 997 REQ146350 10 Total 0 0 1,179 8,129 P9 Total 0 0 0 0 P8 PMWN0729B 1 PMWN1213D 4,958 PMWN1213D2 9,041 PMWN1213D1 3,483 PMWNOL1213 847 Total 0 3,484 5,805 9,041 P10 Total 0 0 0 0 TABLE 9 Total worker staffing requirements by department. Staffing Requirements (number of employees) Dec. 13, Dec. 14, Dec. 14, Dec. 15, 2006 2006 2006 2006 Wed D Thu B Thu D Fri B P11 12 12 12 12 P1 3 3 3 3 P3 42 21 25 0 P4/5/6/7/12 15 19 11 3 P2 0 0 21 62 P9 0 0 0 0 P8 0 25 6 4 P10 0 0 0 0 M3 36 33 33 24 Total 108 113 111 108 The benefits from implementing this model fall into three primary categories. First and foremost, we will enjoy cost savings due to reduced staffing at the merge point M3 which is a result of less volatility in activity at this primary bottleneck. This is expected as we are moving towards a more balanced work schedule which will allow operations to experience improved productivity levels due to fewer changes in staffing on a shift by shift basis. Secondly, we will see improved capacity utilization due to the “smoothing” effect of our scheduling model. Instead of having to maintain capacity for wide fluctuations in peak volumes, we have now effectively minimized these peaks resulting in improved capacity utilization. Third, we will realize savings due to more product being able to flow through the entire process without expensive bypassing which will maximize the volume of product that flows through merge point M3 which will reduce transportation costs. In FIG. 6 we can see actual historical container volume at merge point M3 for a 54 shift time frame (Nov. 10, 2006 through Dec. 12, 2006) as compared against the volume from the previous model and the volume that would have resulted using our model. It is noteworthy to point out the significant difference between the actual volume and the results from the previous model. Similar to what can be found in most distribution environments across many companies, the previous scheduling model worked to manually fit aggregate workloads into full shift capacity “buckets” in an attempt to level load overall shift staffing levels. As this was accomplished without the benefit of any software this was truly an art form, heavily dependent on the skills of individuals within the production planning department. Using this process there was no cost effective means of scheduling discrete jobs by department and shift and as a result, overall volume requirements were outlined for the operations management teams with few specific requirements. Consequently, there was often a tendency by the operation departments to work ahead and when the work ran out, to experience a lull in activity which created an “accordion” effect, resulting in exaggerated peaks and valleys in the previous model's volume. Additionally, if we were to look past the effect on the individual department scheduling we would also see that as there was no previous visibility as to the effect the previous scheduling methods and “work ahead mentality” had on subsequent constraints such as merge point M3. Given this we are not surprised when we see the very noticeable difference between the previous model's volume line and the actual volume line. An added benefit of our scheduling model which uses a more scientific approach is an improved ability to minimize this accordion effect through the scheduling of discrete jobs by department and shift. As our model is being used to schedule a rolling 4 shift horizon the net effect is a “smoothed” workload at merge point M3 as the jobs being planned change at each new planning event. Likewise in FIG. 7 we can see the staffing levels (actual, previous model, our scheduling model) for the same time period and same merge point. Once again we can see the smoothing effect of our scheduling model. One difference in the staffing comparison for merge point M3 (FIG. 7) as compared to the FIG. 6 is that in the staffing level chart we see a much wider gap between the actual and previous model staffing levels than we would expect given the gaps seen in FIG. 6. This is due largely to the high penalty for not completing work on schedule in this industry. As discussed above, the prevalent product at Company B is very time sensitive with a very steep decay curve. Any service level failures at the distribution center (i.e. late shipments) would have the net effect of virtually eliminating the potential for realizing any revenue for new release titles. As a result, we find that the management team in Company B operations has a strong tendency to over-react to volume spikes. As the volume swings become more significant, additional labor is often added as a safety factor in the absence of a more elegant scheduling and staffing solution, even though doing so has a significant impact on production costs. We can see that the actual staffing trend loosely follows that of the previous model but is more exaggerated in its response to spikes in activity. Once again, using our scientific approach to scheduling, we end up with a plan that assigns discrete jobs to departments and individual shifts which stabilizes the staffing level as shown by the smoother line from our scheduling model. To quantify these results we can review them by major category: 1. Reduced Staffing at Merge Point M3—Tabulating the over staffing results across the 51 shifts of actual data as shown in the FIG. 7 we find that the actual staffing requirement was 2,630 (average of 51.5 per shift) whereas our scheduling model resulted in only 1,904 (average of 37.3 per shift) for a net reduction in staffing levels of 726 employee-shifts which equates to 8,712 labor hours (at 12 paid hours per shift). Understanding that the data presented above was collected during the fall season which typically experiences higher volumes than others, we can deseasonalize this 8,712 labor hours by adjusting it down by 20%. If this deseasonalized value of 7,260 labor hours is annualized for 624 shifts per year this would translate to roughly an 88,828 labor hour reduction per year. Assuming a fully loaded labor rate of $14.00 per hour this equates to $1.24 million annually. Once again it should be pointed out that the results from the previous model (based in aggregate containers using individual expertise to develop a plan) created significant spikes in activity which resulted in a more exaggerated actual staffing level and reduced employee productivity through more frequent and larger staffing changes from shift to shift. Truly, the plan resulting from the previous model was not implementable. Also, as will be seen later, the previous scheduling model resulted in much poorer system utilization. 2. Improved Capacity—As the constraint on capacity utilization is measured by the peak capacity utilized, any reduction in the peak will free up additional excess capacity for other uses. In this instance the data shown above in FIG. 6 represents an actual maximum volume of 51,075 containers on a given shift whereas the previous model shows a maximum volume of 42,672 and our scheduling model returns a maximum of 37,355. Once again, the appropriate comparison should be made against the actual activity which yields a 36.7% increase in capacity. Comparing our scheduling model against the historical actuals is clearly more appropriate as history has shown that the previous scheduling model resulted in a plan that could not be achieved as evidenced by the very significant gap between the actual data and previous model data as presented in FIGS. 6 and 7. This increase in available capacity has the net result in reducing instances where product flow must bypass merge point M3 thereby minimizing the transportation costs. 3. Reduced Process Bypass—Bypassing the desired process flow occurs in an estimated 12 weeks out of 52 per year either as a planned or unplanned event and would require both additional labor for the special handling of containers shipped in addition to higher transportation costs. An estimated cost per bypass event is roughly $6,050 for labor (12 people per shift for 3 shifts per week of bypass at an estimated $14.00 labor rate) and $20,800 in freight charges, assuming 10,000 containers per bypass event resulting in a loss of consolidation only. Note that such an event would yield 10,000 containers shipped versus 1,667 if consolidation were utilized. This increase in containers shipped equates to an additional 8,333 containers shipped at $2.50 each. In total this equates to $26,850 per event, or roughly $322,200 annually in labor and transportation costs. Using our scheduling model would eliminate these process bypass events thus resulting in the annualized savings of $322,200 annually in labor and transportation costs. In total these impacts net to over $1.5 million in annual savings while freeing up an additional 36% system capacity solely through the implementation of this new scheduling model which is rooted in OR methodology. In this application we have presented a unique scheduling model based in OR methodology which was designed, developed and implemented to plan discrete jobs to departments while allowing preferred departments by job, in addition to taking into consideration parallel departments competing for subsequent shared resources which have finite capacity. The impetus for the model design is important to understand as not only does the basic problem that existed at Company B continue to plague other companies, but there are also no tools currently available on the market which can address this need in the distribution arena. The primary objective of the model developed here was to minimize the total processing and transportation costs with a secondary goal of balancing the workload throughout the planning horizon. To the best of our knowledge this is the first model developed in theory and in practice to address this problem. We have shown that not only does this model perform exceedingly well to the expectations presented, but that it is also capable of being run for a wide range of scenarios (shifts, parameter ranges, etc.) with very favorable computational times and objective function values that are close to optimal. We have seen that this model on its own is capable of reducing costs in this one application by over $1.5 million annually while increasing system capacity by over 36% without the addition of any physical process or equipment changes. It is also expected that this basic model could easily be modified and applied to many other organizations with similar processes to yield desired results. As the Company B model as described in this application is more complex than most distribution processes it is anticipated that any application to other organizations would yield models that are less complex. Additionally, considering the run times afforded by using the CPLEX options as experienced in the live computational experiments, this model has proven to be very capable of handling much larger scheduling horizons than what was used in this application with very reasonable computational times and virtually no impact to the objective function values. One facet of supply chain practitioners which is common across all organizations is the need and desire to continually reduce costs while maintaining or increasing capacities. This application presents to all supply chain practitioners how the correct application of OR methodology not only meets this need in practice, but that it is also flexible and robust enough for application to a variety of environments. It may now be fully appreciated that the principles of the present invention provide a scheduling model for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments, and the departments share finite capacity resources. The model preferably includes a programmable computer system having loaded therein an objective function, and the computer system being operable to minimize a value of the objective function. The objective function comprises a sum of cost to ship containers in at least one of consolidated and unconsolidated forms, cost for each of a container equivalent not completed in a selected scheduling horizon, cost to process each job in each department, and cost for setup due to at least one of shift crossing and job splitting. The cost to ship containers in at least one of consolidated and unconsolidated forms may be represented in the objective function by the expression P 1  ∑ k = 1 n  ∑ i = 1 r  X i , k , j   1 + P 1  ∑ k = 1 n  ∑ i = 1 r  ∑ j ∈ j   2  X _ i , k , j wherein P1 is a shipping cost per container, i is a shift index number from 1 to r, j is a department index number from 1 to m, k is a job index number from 1 to n, Xi,k,j1 is a number of containers of job k processed in a selected merge department j1 during shift i, Xi,k,j is a number of containers of job k diverted direct to shipping from department j during shift i, and j2 is a subset of departments including the selected departments. The cost for each of a container equivalent not completed in a selected scheduling horizon may be represented in the objective function by the expression ∑ k = 1 n  P 2  C k B k  ( B k - ∑ j ∈ R  ∑ i = 1 r  Y ikj ) wherein P2 is a cost of shipping by an alternative mode of transportation, Ck is a number of containers to be generated by job k, Bk is a number of pieces to be shipped in job k, Yikj is a number of pieces of job k shipped during shift i in department j, and R is a set of picking and processing departments other than merging or sorting departments. The cost to process each job in each department may be represented in the objective function by the expression ∑ j ∈ R  ∑ k = 1 n  ∑ i = 1 r  ( d kj  Y ikj ) wherein Yikj is a number of pieces of job k shipped during shift i in department j, and dkj is a unit cost to process job k in department j. The cost for setup due to at least one of shift crossing and job splitting may be represented in the objective function by the expression P 3  ∑ k = 1 n  ∑ i = 1 r  M ik wherein P3 is a setup cost accounting for labor needed to switch between jobs or shifts, and Mik is equal to 1 if job k is processed in shift i, and is equal to 0 if job k is not processed in shift i. Of course, a person skilled in the art would, upon a careful consideration of the above description of representative embodiments of the invention, readily appreciate that many modifications, additions, substitutions, deletions, and other changes may be made to these specific embodiments, and such changes are within the scope of the principles of the present invention. Accordingly, the foregoing detailed description is to be clearly understood as being given by way of illustration and example only, the spirit and scope of the present invention being limited solely by the appended claims and their equivalents. APPENDIX A Formulation Objective function for Company B application: Min   2.5  ∑ k = 1 n  ∑ i = 1 r  X i , k , M   3 + 2.5   ∑ k = 1 n  ∑ i = 1 r  ( X _ i , k , M   1 + X _ i , k , M   2 + X _ i , k , S   1 + X _ i , k , S   2 + X _ i , k , M   3 ) + ∑ k = 1 n  6.0  C k B k  ( B k - ∑ j ∈ R  ∑ i = 1 r  Y ikj ) + ∑ j ∈ R  ∑ k = 1 n  ∑ i = 1 r  ( d kj  Y ikj ) + 20.0  ∑ k = 1 n  ∑ i = 1 r  M ik . ( 1 ) Balance equations used in problem formulation: X i , k , M   4 = M i , k , P   1 + X i , k , P   2 + X i , k , P   3  ∀ i , k , ( 2 ) X i , k , M   1 + X _ i , k , M   1 = X i , k , P   8 + X i , k , M   4  ∀ i , k , ( 3 ) X i , k , M   2 + X _ i , k , M   2 = X i , k , P   9 + X i , k , M   1 + X i , k , M   3  ∀ i , k , ( 4 ) X i , k , S   1 + X _ i , k , S   1 + X i , k , M   3 = X i , k , P   10 + X i , k , M   2  ∀ i , k , ( 5 ) X i , k , M   5 = X i , k , P   4 + X i , k , P   5  ∀ i , k , ( 6 ) X i , k , M   6 = X i , k , P   6 + X i , k , P   7  ∀ i , k , ( 7 ) X i , k , S   2 + X _ i , k , S   2 = X i , k , P   11 + X i , k , M   6 + X i , k , P   12 + X i , k , S   1 + X i , k , M   5  ∀ i , k , ( 8 ) 6  a i  X i , k , M   3 + X _ i , k , M   3 = X i , k , S   2  ∀ i , k . ( 9 ) Variables installed to level load work flow through the most prominent system bottleneck: S ≤ ∑ k = 1 n  ( X i , k , M   3 + X _ i , k , M   3 + X i , k , S   2 )  ∀ i , ( 10 ) T ≥ ∑ k = 1 n  ( X i , k , M   3 + X _ i , k , M   3 + X i , k , S   2 )  ∀ i , ( 11 ) T - S ≤ 500. ( 12 ) Processing/picking/merge/sortation constraints: ∑ k = 1 n  ( X i , k , P   11 + X i , k , M   6 + X i , k , P   12 ) ≤ 60 × 10.5 × 60   i = 1 , 2 , …  , r , ( 13 ) ∑ k = 1 n  ( X i , k , P   6 + X i , k , P   7 ) ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 14 ) ∑ k = 1 n  ( X i , k , M   5 + X i , k , S   1 ) ≤ 60 × 10.5 × 60   i = 1 , 2 , …  , r , ( 15 ) ∑ k = 1 n  ( X i , k , P   4 + X i , k , P   5 ) ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 16 ) ∑ k = 1 n  ( X i , k , P   8 + X i , k , M   4 ) ≤ 120 × 10.5 × 60   i = 1 , 2 , …  , r , ( 17 ) ∑ k = 1 n  ( X i , k , P   1 + X i , k , P   2 + X i , k , P   3 ) ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 18 ) ∑ k = 1 n  ( X i , k , M   1 + X i , k , P   9 + X i , k , M   3 ) ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 19 ) ∑ k = 1 n  ( X i , k , M   2 + X i , k , P   10 ) ≤ 80 × 10.5 × 60   i = 1 , 2 , …  , r , ( 20 ) ∑ k = 1 n  ( X i , k , S   1 + X i , k , M   5 + X i , k , P   11 + X i , k , M   6 + X i , k , P   12 ) ≤ 120 × 10.5 × 60   i = 1 , 2 , …  , r , ( 21 ) ∑ k = 1 n  X i , k , P   8 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 22 ) ∑ k = 1 n  X i , k , M   4 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 23 ) ∑ k = 1 n  X i , k , P   1 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 24 ) ∑ k = 1 n  X i , k , P   2 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 25 ) ∑ k = 1 n  Y i , k , P   2 ≤ 65 , 000   i = 1 , 2 , …  , r , ( 25  a ) ∑ k = 1 n  X i , k , P   3 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 26 ) ∑ k = 1 n  X i , k , P   9 ≤ 45 × 10.5 × 60   i = 1 , 2 , …  , r , ( 27 ) ∑ k = 1 n  X i , k , P   10 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 28 ) ∑ k = 1 n  X i , k , M   5 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 29 ) ∑ k = 1 n  X i , k , P   4 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 30 ) ∑ k = 1 n  X i , k , P   5 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 31 ) ∑ k = 1 n  X i , k , P   11 ≤ 7 × 10.5 × 60   i = 1 , 2 , …  , r , ( 32 ) ∑ k = 1 n  Y i , k , P   11 ≤ 40 , 000   i = 1 , 2 , …  , r , ( 32  a ) ∑ k = 1 n  X i , k , M   6 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 33 ) ∑ k = 1 n  X i , k , P   6 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 34 ) ∑ k = 1 n  X i , k , P   7 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 35 ) ∑ k = 1 n  X i , k , P   12 ≤ 64 × 10.5 × 60   i = 1 , 2 , …  , r , ( 36 ) ∑ k = 1 n  X i , k , M   1 ≤ 120 × 10.5 × 60   i = 1 , 2 , …  , r , ( 37 ) ∑ k = 1 n  X i , k , M   2 ≤ 40 × 10.5 × 60   i = 1 , 2 , …  , r , ( 38 ) ∑ k = 1 n  X i , k , S   1 ≤ 80 × 10.5 × 60   i = 1 , 2 , …  , r , ( 39 ) ∑ k = 1 n  X i , k , S   2 ≤ 120 × 10.5 × 60   i = 1 , 2 , …  , r , ( 40 ) ∑ k = 1 n  X i , k , M   3 ≤ ( 35 × 10.5 × 60 )  a j   i = 1 , 2 , …  , r . ( 41 ) Constraint added during implementation to allow containers for a particular job to bypass the normal product flow using parameter bk: ∑ i = 1 r  ( X _ i , k , M   1 + X _ i , k , M   2 + X _ i , k , S   1 + X _ i , k , S   2 ) ≥ C k  b k . ( 41  a ) Constraints used to force a job to a primary or secondary processing department: Xi,k,j≦CkNk jεP(k) ∀i,k, where P(k) is a set of primary processing department for job k, (42) Xi,k,j≦Ck(1−Nk) jεS(k) ∀i,k, where S(k) is a set of secondary processing department for job k, (43) Yi,k,j≦BkNk jεP(k) ∀i,k, where P(k) is a set of primary processing department for job k, (44) Yi,k,j≦Bk(1−Nk) jεS(k) ∀i,k, where S(k) is a set of secondary processing department for job k. (45) Formulation used to force a job to a specific shift and to limit the number of shifts a job can be completed on to 2 or less: ∑ j ∈ Q  ( k )  X i , k , j ≤ C k  M i , k  q ik  j ∈ Q  ( k )  ∀ i , k , ( 46 ) ∑ i = 1 r  M i , k ≤ 2  ∀ k , ( 47 ) ∑ j ∈ Q  ( k )  Y i , k , j ≤ B k  M i , k  q ik  j ∈ Q  ( k )  ∀ i , k . ( 48 ) Constraints to prevent unnecessary job splitting assuming a 12 shift scheduling horizon: M1,k+M1+h,k≦1 ∀k h=2, . . . , 11, (49) M2,k+M2+h,k≦1 ∀k h=2, . . . , 10, (50) M3,k+M3+h,k≦1 ∀k h=2, . . . , 9, (51) M4,k+M4+h,k≦1 ∀k h=2, . . . , 8, (52) M5,k+M5+h,k≦1 ∀k h=2, . . . , 7, (53) M6,k+M6+h,k≦1 ∀k h=2, . . . , 6, (54) M7,k+M7+h,k≦1 ∀k h=2, . . . , 5, (55) M8,k+M8+h,k≦1 ∀k h=2, . . . , 4, (56) M9,k+M9+h,k≦1 ∀k h=2,3, (57) M10,k+M12,k≦1 ∀k h=2. (58) Or more generally: Mr−g,k+Mr−g+h,k≦1 ∀k r=1, . . . , 12 g=2, . . . , r−1 h=2, . . . , g. (59) Constraint to ensure a shift capacity (10.5 available hours during a 12 hour shift after breaks, lunches, start up meetings, etc. are considered) is not exceeded as well as a total staffing capacity where e represents the maximum staffing level allowed per shift: ∑ k = 1 n  Y i , k , j r k , j ≤ 10.5  ∀ i , j   j ∈ h , ( 60 ) ∑ j ∈ h  ∑ k = 1 n  Y i , k , j r k , j ≤ 10.5  e  ∀ i . ( 60  a ) Constraint (61) requires that the pieces produced for job k in total are less than or equal to what is expected for job k. This constraint can be relaxed from equality since the objective function will prefer that Yikj be as close to Bk as possible. ∑ j ∈ h  ∑ i = 1 r  Y i , k , j ≤ B k   k = 1 , 2 , 3 , …  , n . ( 61 ) Constraint (62) requires that the containers produced for job k in total are less than or equal to what is expected for job k. This restriction can be relaxed from equality due to Constraint (64) where containers produced are tied directly to pieces produced (Constraint (61)) which is controlled by the objective function. ∑ j = 1 m  ∑ i = 1 r  X i , k , j ≤ C k  ∀ k . ( 62 ) Constraint used to ensure that the ratio of pieces completed per shift is similar to the ratio of containers X ikj  ( B k C k ) - 0.5 ≤ Y ikj ≤ X ikj  ( B k C k ) + 0.5  ∀ i , k , j . ( 63 ) APPENDIX B Data Set for Computational Analysis Actual 4 shift data set for time period Dec. 13, 2006 through Dec. 15, 2006. Job Primary Processing Pool Point (Wave Infeed # Pieces # Cartons Processing Time (hrs) Job (k) Departure Date Name) Group (Bk) (Ck) Dept (pkj) 1 15-Dec AFRR121302_AFR P11 7,432 1,596 P11 17 2 15-Dec AFRR121303_AFR P11 4,091 1,173 P11 10 3 15-Dec AFRR121301_CLU P3 4,575 746 P3 37 4 15-Dec AFRR121302_CLU P3 14,440 3,192 P3 116 5 15-Dec AFRR121303_CLU P3 7,641 2,346 P3 61 6 15-Dec KSGYL1217C_CLU P3 935 316 P3 7 7 15-Dec KSI1212C_CLU P3 83 20 P3 1 8 15-Dec PRP1211C P3 3,025 1,272 P3 24 9 15-Dec PRP1212A P3 528 510 P3 4 10 15-Dec PRP1215B P3 17,398 2,560 P3 139 11 15-Dec PRP1215D P3 17,910 2,636 P3 143 12 15-Dec PRPYL1215 P3 3,027 484 P3 24 13 15-Dec DVD31212A P6 73,540 3,597 P6 210 14 15-Dec DVD21212A P7 3,542 421 P7 10 15 15-Dec DVD51214B1 P5 37,344 4,156 P5 107 16 15-Dec AFRE121102 P11 17 1 P11 0 17 15-Dec AFRR121305_AFR P11 4,217 2,042 P11 10 18 15-Dec AFRR121306_CLU P3 9,479 1,872 P3 76 19 15-Dec KSG1217C_CLU P3 20,945 7,884 P3 168 20 15-Dec KSI1214B_CLU P3 864 263 P3 7 21 15-Dec DVD11212A P7 49,051 1,949 P7 140 22 15-Dec DVD41211A P4 62,651 2,383 P4 179 23 15-Dec DVD21212C P12 90,811 3,623 P12 259 24 15-Dec PMWN0729B P8 8 1 P8 0 25 15-Dec PMWN1213D1 P8 29,440 3,483 P8 346 26 15-Dec AFRR121301_AFR P11 1,207 746 P11 3 27 15-Dec AFRR121304_AFR P11 7,524 2,612 P11 18 28 15-Dec AFRR121304_CLU P3 23,549 5,224 P3 188 29 15-Dec AFRR121305_CLU P3 14,903 4,084 P3 119 30 15-Dec KEQ146350 P3 209 10 P3 2 31 15-Dec DVD51212C3 P12 55 3 P12 0 32 15-Dec BSGYL1217C P2 935 158 P2 14 33 15-Dec BSI1208001 P2 1 1 P2 0 34 15-Dec BSI1208002 P2 103 13 P2 2 35 15-Dec BSI1214B P2 11,910 997 P2 183 36 15-Dec REQ146350 P2 209 10 P2 3 37 15-Dec PMWN1213D P8 4,958 1,549 P8 58 38 15-Dec PMWNOL1213 P8 201,550 847 P8 2,371 39 15-Dec AFRR121306_AFR P11 1,572 936 P11 4 40 15-Dec BSG1217C P2 20,945 3,942 P2 322 41 15-Dec MNG1213D P2 18,558 4,187 P2 286 42 15-Dec PMWN1213D2 P8 9,041 3,252 P8 106 Processing Processing Rate Processing Secondary Processing Rate Processing (pcs/hr) Cost ($/pc) Processing Time (hrs) (pcs/hr) Cost ($/pc) Job (k) (rkj) (dkj) Dept (pkj) (rkj) (dkj) 1 425 0.0348 P3 59 125 0.1184 2 425 0.0348 P3 33 125 0.1184 3 125 0.1184 na — — — 4 125 0.1184 na — — — 5 125 0.1184 na — — — 6 125 0.1184 na — — — 7 125 0.1184 na — — — 8 125 0.1184 na — — — 9 125 0.1184 na — — — 10 125 0.1184 na — — — 11 125 0.1184 na — — — 12 125 0.1184 na — — — 13 350 0.0423 P2 1,131 65 0.2277 14 350 0.0423 P2 54 65 0.2277 15 350 0.0423 P2 575 65 0.2277 16 425 0.0348 P3 0 125 0.1184 17 425 0.0348 P3 34 125 0.1184 18 125 0.1184 na — — — 19 125 0.1184 na — — — 20 125 0.1184 na — — — 21 350 0.0423 P2 755 65 0.2277 22 350 0.0423 P2 964 65 0.2277 23 350 0.0423 P2 1,397 65 0.2277 24 85 0.1741 P10 0 55 0.2691 25 85 0.1741 P10 535 55 0.2691 26 425 0.0348 P3 10 125 0.1184 27 425 0.0348 P3 60 125 0.1184 28 125 0.1184 na — — — 29 125 0.1184 na — — — 30 125 0.1184 na — — — 31 350 0.0423 P2 1 65 0.2277 32 65 0.2277 na — — — 33 65 0.2277 na — — — 34 65 0.2277 na — — — 35 65 0.2277 na — — — 36 65 0.2277 na — — — 37 85 0.1741 P10 90 55 0.2691 38 85 0.1741 P10 3,665 55 0.2691 39 425 0.0348 P3 13 125 0.1184 40 65 0.2277 na — — — 41 65 0.2277 na — — — 42 85 0.1741 P10 164 55 0.2691 APPENDIX C Data Set for 12 Shift Plan Based on Forecasted Data Forecasted 12 shift data set for time period Dec. 13, 2006 through Dec. 19, 2006. Job Primary Processing Pool Point (Wave Infeed # Pieces # Cartons Processing Time (hrs) Job (k) Departure Date Name) Group (Bk) (Ck) Dept (pkj) 1 NA Job 1 P11 7,432 1,596 P11 17 2 NA Job 2 P11 4,091 1,173 P11 10 3 NA Job 3 P3 4,575 746 P3 37 4 NA Job 4 P3 14,440 3,192 P3 116 5 NA Job 5 P3 7,641 2,346 P3 61 6 NA Job 6 P3 935 316 P3 7 7 NA Job 7 P3 83 20 P3 1 8 NA Job 8 P3 3,025 1,272 P3 24 9 NA Job 9 P3 528 510 P3 4 10 NA Job 10 P3 17,398 2,560 P3 139 11 NA Job 11 P3 17,910 2,636 P3 143 12 NA Job 12 P3 3,027 484 P3 24 13 NA Job 13 P6 73,540 3,597 P6 210 14 NA Job 14 P7 3,542 421 P7 10 15 NA Job 15 P5 37,344 4,156 P5 107 16 NA Job 16 P11 17 1 P11 0 17 NA Job 17 P11 4,217 2,042 P11 10 18 NA Job 18 P3 9,479 1,872 P3 76 19 NA Job 19 P3 20,945 7,884 P3 168 20 NA Job 20 P3 864 263 P3 7 21 NA Job 21 P7 49,051 1,949 P7 140 22 NA Job 22 P4 62,651 2,383 P4 179 23 NA Job 23 P12 90,811 3,623 P12 259 24 NA Job 24 P8 8 1 P8 0 25 NA Job 25 P8 29,440 3,483 P8 346 26 NA Job 26 P11 1,207 746 P11 3 27 NA Job 27 P11 7,524 2,612 P11 18 28 NA Job 28 P3 23,549 5,224 P3 188 29 NA Job 29 P3 14,903 4,084 P3 119 30 NA Job 30 P3 209 10 P3 2 31 NA Job 31 P12 55 3 P12 0 32 NA Job 32 P2 935 158 P2 14 33 NA Job 33 P2 1 1 P2 0 34 NA Job 34 P2 103 13 P2 2 35 NA Job 35 P2 11,910 997 P2 183 36 NA Job 36 P2 209 10 P2 3 37 NA Job 37 P8 4,958 1,549 P8 58 38 NA Job 38 P8 201,550 847 P8 2,371 39 NA Job 39 P11 1,572 936 P11 4 40 NA Job 40 P2 20,945 3,942 P2 322 41 NA Job 41 P2 18,558 4,187 P2 286 42 NA Job 42 P8 9,041 3,252 P8 106 43 NA Job 43 P11 7,432 1,596 P11 17 44 NA Job 44 P11 4,091 1,173 P11 10 45 NA Job 45 P3 4,575 746 P3 37 46 NA Job 46 P3 14,440 3,192 P3 116 47 NA Job 47 P3 7,641 2,346 P3 61 48 NA Job 48 P3 935 316 P3 7 49 NA Job 49 P3 83 20 P3 1 50 NA Job 50 P3 3,025 1,272 P3 24 51 NA Job 51 P3 528 510 P3 4 52 NA Job 52 P3 17,398 2,560 P3 139 53 NA Job 53 P3 17,910 2,636 P3 143 54 NA Job 54 P3 3,027 484 P3 24 55 NA Job 55 P6 73,540 3,597 P6 210 56 NA Job 56 P7 3,542 421 P7 10 57 NA Job 57 P5 37,344 4,156 P5 107 58 NA Job 58 P11 17 1 P11 0 59 NA Job 59 P11 4,217 2,042 P11 10 60 NA Job 60 P3 9,479 1,872 P3 76 61 NA Job 61 P3 20,945 7,884 P3 168 62 NA Job 62 P3 864 263 P3 7 63 NA Job 63 P7 49,051 1,949 P7 140 64 NA Job 64 P4 62,651 2,383 P4 179 65 NA Job 65 P12 90,811 3,623 P12 259 66 NA Job 66 P8 8 1 P8 0 67 NA Job 67 P8 29,440 3,483 P8 346 68 NA Job 68 P11 1,207 746 P11 3 69 NA Job 69 P11 7,524 2,612 P11 18 70 NA Job 70 P3 23,549 5,224 P3 188 71 NA Job 71 P3 14,903 4,084 P3 119 72 NA Job 72 P3 209 10 P3 2 73 NA Job 73 P12 55 3 P12 0 74 NA Job 74 P2 935 158 P2 14 75 NA Job 75 P2 1 1 P2 0 76 NA Job 76 P2 103 13 P2 2 77 NA Job 77 P2 11,910 997 P2 183 78 NA Job 78 P2 209 10 P2 3 79 NA Job 79 P8 4,958 1,549 P8 58 80 NA Job 80 P8 201,550 847 P8 2,371 81 NA Job 81 P11 1,572 936 P11 4 82 NA Job 82 P2 20,945 3,942 P2 322 83 NA Job 83 P2 18,558 4,187 P2 286 Processing Processing Rate Processing Secondary Processing Rate Processing (pcs/hr) Cost($/pc) Processing Time (hrs) (pcs/hr) Cost($/pc) Job (k) (rkj) (dkj) Dept (pkj) (rkj) (dkj) 1 425 0.0348 P3 59 125 0.1184 2 425 0.0348 P3 33 125 0.1184 3 125 0.1184 na — — — 4 125 0.1184 na — — — 5 125 0.1184 na — — — 6 125 0.1184 na — — — 7 125 0.1184 na — — — 8 125 0.1184 na — — — 9 125 0.1184 na — — — 10 125 0.1184 na — — — 11 125 0.1184 na — — — 12 125 0.1184 na — — — 13 350 0.0423 P2 1,131 65 0.2277 14 350 0.0423 P2 54 65 0.2277 15 350 0.0423 P2 575 65 0.2277 16 425 0.0348 P3 0 125 0.1184 17 425 0.0348 P3 34 125 0.1184 18 125 0.1184 na — — — 19 125 0.1184 na — — — 20 125 0.1184 na — — — 21 350 0.0423 P2 755 65 0.2277 22 350 0.0423 P2 964 65 0.2277 23 350 0.0423 P2 1,397 65 0.2277 24 85 0.1741 P10 0 55 0.2691 25 85 0.1741 P10 535 55 0.2691 26 425 0.0348 P3 10 125 0.1184 27 425 0.0348 P3 60 125 0.1184 28 125 0.1184 na — — — 29 125 0.1184 na — — — 30 125 0.1184 na — — — 31 350 0.0423 P2 1 65 0.2277 32 65 0.2277 na — — — 33 65 0.2277 na — — — 34 65 0.2277 na — — — 35 65 0.2277 na — — — 36 65 0.2277 na — — — 37 85 0.1741 P10 90 55 0.2691 38 85 0.1741 P10 3,665 55 0.2691 39 425 0.0348 P3 13 125 0.1184 40 65 0.2277 na — — — 41 65 0.2277 na — — — 42 85 0.1741 P10 164 55 0.2691 43 425 0.0348 P3 59 125 0.1184 44 425 0.0348 P3 33 125 0.1184 45 125 0.1184 na — — — 46 125 0.1184 na — — — 47 125 0.1184 na — — — 48 125 0.1184 na — — — 49 125 0.1184 na — — — 50 125 0.1184 na — — — 51 125 0.1184 na — — — 52 125 0.1184 na — — — 53 125 0.1184 na — — — 54 125 0.1184 na — — — 55 350 0.0423 P2 1,131 65 0.2277 56 350 0.0423 P2 54 65 0.2277 57 350 0.0423 P2 575 65 0.2277 58 425 0.0348 P3 0 125 0.1184 59 425 0.0348 P3 34 125 0.1184 60 125 0.1184 na — — — 61 125 0.1184 na — — — 62 125 0.1184 na — — — 63 350 0.0423 P2 755 65 0.2277 64 350 0.0423 P2 964 65 0.2277 65 350 0.0423 P2 1,397 65 0.2277 66 85 0.1741 P10 0 55 0.2691 67 85 0.1741 P10 535 55 0.2691 68 425 0.0348 P3 10 125 0.1184 69 425 0.0348 P3 60 125 0.1184 70 125 0.1184 na — — — 71 125 0.1184 na — — — 72 125 0.1184 na — — — 73 350 0.0423 P2 1 65 0.2277 74 65 0.2277 na — — — 75 65 0.2277 na — — — 76 65 0.2277 na — — — 77 65 0.2277 na — — — 78 65 0.2277 na — — — 79 85 0.1741 P10 90 55 0.2691 80 85 0.1741 P10 3,665 55 0.2691 81 425 0.0348 P3 13 125 0.1184 82 65 0.2277 na — — — 83 65 0.2277 na — — — APPENDIX C Data Set for 12 Shift Plan Based on Forecasted Data (continued) Forecasted 12 shift data set for time period Dec. 13, 2006 through Dec. 19, 2006. Job Primary Processing Job Pool Point (Wave Infeed # Pieces # Cartons Processing Time (hrs) (k) Departure Date Name) Group (Bk) (Ck) Dept (pkj) 84 NA Job 84 P8 9,041 3,252 P8 106 85 NA Job 85 P11 7,432 1,596 P11 17 86 NA Job 86 P11 4,091 1,173 P11 10 87 NA Job 87 P3 4,575 746 P3 37 88 NA Job 88 P3 14,440 3,192 P3 116 89 NA Job 89 P3 7,641 2,346 P3 61 90 NA Job 90 P3 935 316 P3 7 91 NA Job 91 P3 83 20 P3 1 92 NA Job 92 P3 3,025 1,272 P3 24 93 NA Job 93 P3 528 510 P3 4 94 NA Job 94 P3 17,398 2,560 P3 139 95 NA Job 95 P3 17,910 2,636 P3 143 96 NA Job 96 P3 3,027 484 P3 24 97 NA Job 97 P6 73,540 3,597 P6 210 98 NA Job 98 P7 3,542 421 P7 10 99 NA Job 99 P5 37,344 4,156 P5 107 100 NA Job 100 P11 17 1 P11 0 101 NA Job 101 P11 4,217 2,042 P11 10 102 NA Job 102 P3 9,479 1,872 P3 76 103 NA Job 103 P3 20,945 7,884 P3 168 104 NA Job 104 P3 864 263 P3 7 105 NA Job 105 P7 49,051 1,949 P7 140 106 NA Job 106 P4 62,651 2,383 P4 179 107 NA Job 107 P12 90,811 3,623 P12 259 108 NA Job 108 P8 8 1 P8 0 109 NA Job 109 P8 29,440 3,483 P8 346 110 NA Job 110 P11 1,207 746 P11 3 111 NA Job 111 P11 7,524 2,612 P11 18 112 NA Job 112 P3 23,549 5,224 P3 188 113 NA Job 113 P3 14,903 4,084 P3 119 114 NA Job 114 P3 209 10 P3 2 115 NA Job 115 P12 55 3 P12 0 116 NA Job 116 P2 935 158 P2 14 117 NA Job 117 P2 1 1 P2 0 118 NA Job 118 P2 103 13 P2 2 119 NA Job 119 P2 11,910 997 P2 183 120 NA Job 120 P2 209 10 P2 3 121 NA Job 121 P8 4,958 1,549 P8 58 122 NA Job 122 P8 201,550 847 P8 2,371 123 NA Job 123 P11 1,572 936 P11 4 124 NA Job 124 P2 20,945 3,942 P2 322 125 NA Job 125 P2 18,558 4,187 P2 286 126 NA Job 126 P8 9,041 3,252 P8 106 Processing Processing Rate Processing Secondary Processing Rate Processing Job (pcs/hr) Cost ($/pc) Processing Time (hrs) (pcs/hr) Cost ($/pc) (k) (rkj) (dkj) Dept (pkj) (rkj) (dkj) 84 85 0.1741 P10 164 55 0.2691 85 425 0.0348 P3 59 125 0.1184 86 425 0.0348 P3 33 125 0.1184 87 125 0.1184 na — — — 88 125 0.1184 na — — — 89 125 0.1184 na — — — 90 125 0.1184 na — — — 91 125 0.1184 na — — — 92 125 0.1184 na — — — 93 125 0.1184 na — — — 94 125 0.1184 na — — — 95 125 0.1184 na — — — 96 125 0.1184 na — — — 97 350 0.0423 P2 1,131 65 0.2277 98 350 0.0423 P2 54 65 0.2277 99 350 0.0423 P2 575 65 0.2277 100 425 0.0348 P3 0 125 0.1184 101 425 0.0348 P3 34 125 0.1184 102 125 0.1184 na — — — 103 125 0.1184 na — — — 104 125 0.1184 na — — — 105 350 0.0423 P2 755 65 0.2277 106 350 0.0423 P2 964 65 0.2277 107 350 0.0423 P2 1,397 65 0.2277 108 85 0.1741 P10 0 55 0.2691 109 85 0.1741 P10 535 55 0.2691 110 425 0.0348 P3 10 125 0.1184 111 425 0.0348 P3 60 125 0.1184 112 125 0.1184 na — — — 113 125 0.1184 na — — — 114 125 0.1184 na — — — 115 350 0.0423 P2 1 65 0.2277 116 65 0.2277 na — — — 117 65 0.2277 na — — — 118 65 0.2277 na — — — 119 65 0.2277 na — — — 120 65 0.2277 na — — — 121 85 0.1741 P10 90 55 0.2691 122 85 0.1741 P10 3,665 55 0.2691 123 425 0.0348 P3 13 125 0.1184 124 65 0.2277 na — — — 125 65 0.2277 na — — — 126 85 0.1741 P10 164 55 0.2691	G	60G06	161G06F	19	00
11839714	US20090048700A1-20090219	METHOD FOR REPORTING THE STATUS OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT	ACCEPTED	20090205	20090219	[]	G06F1900	["G06F1900"]	7493236	20070816	20090217	702	185000	97661.0	WACHSMAN	HAL	[{"inventor_name_last": "Mock", "inventor_name_first": "Michael W.", "inventor_city": "St. George", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Moore", "inventor_name_first": "Gray R.", "inventor_city": "Milton", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Wong", "inventor_name_first": "Justin W.", "inventor_city": "South Burlington", "inventor_state": "VT", "inventor_country": "US"}]	Disclosed are embodiments that provide near real-time monitoring of a control application in a manufacturing environment to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within the control application during events (i.e., transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application. These summary reports can further be generated with drill downs to provide a user with direct access to the records upon which the reports were based.	1. A method for monitoring a control application, said method comprising: accessing a plurality of data sources for said control application; retrieving, from said data sources, data regarding events occurring in a manufacturing environment monitored by said control application; compiling said data to generate, for said events, records of dataflow paths within said control application, each of said records of said dataflow paths corresponding to a specific event, indicating a type of said specific event and further indicating at least one specific data source to which a data posting was made during said specific event; storing said records of said dataflow paths in a data storage device; and performing an analysis of said records to detect a dataflow interruption within said control application, said analysis comprising comparing a current dataflow path record to historical dataflow path records for same type events to identify differences in data postings indicative of said dataflow interruption. 2. The method of claim 1, further comprising notifying a user of said dataflow interruption. 3. The method of claim 1, further comprising generating a summary report indicating a status of said control application based on said analysis, wherein said summary report quantifies at least one of performance and effectiveness of said control application. 4. The method of claim 3, wherein said generating of said summary report comprises quantifying said performance of said control application by indicating in said summary report at least a percentage of said events for which said control application should have collected said data and failed out of a total number of said events. 5. The method of claim 3, wherein said generating of said summary report comprises quantifying said effectiveness of said control application by indicating in said summary report at least a percentage of said events for which said control application had inhibit ability out of a total number of said events. 6. (canceled) 7. The method of claim 1, wherein said performing of said analysis further comprises analyzing said records to determine a location within said control application of said dataflow interruption and, based on said location, determining a root cause of a failure in said control application. 8. The method of claim 1, wherein said performing of said analysis further comprises analyzing said records in response to at least one of a specific query and a continual query. 9. A method for monitoring a fault detection and classification (FDC) application, said method comprising: accessing a plurality of data sources for said fault detection and classification (FDC) application; retrieving, from said data sources, data regarding wafer-chamber passes in an integrated circuit manufacturing environment monitored by said fault detection and classification (FDC) application; compiling said data to generate, for said wafer-chamber passes, records of dataflow paths within said fault detection and classification (FDC) application, each of said records of said dataflow paths corresponding to a specific wafer-chamber pass and indicating at least one specific data source to which a data posting was made during said specific wafer-chamber pass; storing said records in a data storage device records; and performing an analysis of said records to detect a dataflow interruption within said fault detection and classification (FDC) application, said analysis comprising comparing a current dataflow path record for a given wafer-chamber pass to historical dataflow path records for the same wafer-chamber pass to identify differences in data postings indicative of said dataflow interruption. 10. The method of claim 9, further comprising notifying a user of said dataflow interruption. 11. The method of claim 9, further comprising generating a summary report indicating a status of said fault detection and classification application based on said analysis, wherein said summary report quantifies at least one of performance and effectiveness of said fault detection and classification (FDC) application. 12. The method of claim 11, wherein said summary report quantifies said at least one of said performance and said effectiveness of said fault detection and classification (FDC) application by at least one of tool type, technology, and technology center. 13. The method of claim 11, wherein said generating of said summary report further comprises quantifying said performance of said fault detection and classification (FDC) application by indicating in said summary report at least a percentage of said wafer-chamber passes for which said fault detection and classification (FDC) application should have collected said data and failed out of a total number of said wafer-chamber passes. 14. The method of claim 11, wherein said generating of said summary report further comprises quantifying said effectiveness of said fault detection and classification (FDC) application by indicating in said summary report at least a percentage of said wafer-chamber passes for which said fault detection and classification (FDC) application had inhibit ability out of a total number of said wafer-chamber passes. 15. (canceled) 16. The method of claim 9, wherein said performing of said analysis further comprises analyzing said records to determine a location within said fault detection and classification (FDC) application of said dataflow interruption and, based on said location, determining a root cause of a failure in said fault detection and classification (FDC) application. 17. The method of claim 9, wherein said performing of said analysis further comprises analyzing said records in response to at least one of a specific query and a continual query. 18. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a method of monitoring a control application, said method comprising: accessing a plurality of data sources for said control application and retrieving, from said data sources, data regarding events occurring in a manufacturing environment monitored by said control application; compiling said data to generate, for said events, records of dataflow paths within said control application, each of said records of said dataflow paths corresponding to a specific event, indicating a type of said specific event and further indicating at least one specific data source to which a data posting was made during said specific event; storing said records of said dataflow paths in a data storage device; and performing an analysis of said records to detect a dataflow interruption within said control application, said analysis comprising comparing a current dataflow path record to historical dataflow path records for same type events to identify differences in data postings indicative of said dataflow interruption; and at least one of notifying a user of said dataflow interruption and generating a summary report indicating a status of said control application based on said analysis, wherein said summary report quantifies at least one of performance and effectiveness of said control application. 19. The program storage device of claim 18, wherein said performing of said analysis further comprises analyzing said records to determine a location within said control application of said dataflow interruptions and, based on said location, determining a root cause of a failure in said control application. 20. A service for monitoring a control application, said service comprising: accessing a plurality of data sources for said control application; retrieving, from said data sources, data regarding events occurring in a manufacturing environment monitored by said control application, each of said records of said dataflow paths corresponding to a specific event, indicating a type of said specific event and further indicating at least one specific data source to which a data posting was made during said specific event; compiling said data to generate, for said events, records of dataflow paths within said control application; storing said records of said dataflow paths in a data storage device; performing an analysis of said records to detect a dataflow interruption within said control application, said analysis comprising comparing a current dataflow path record to historical dataflow path records for same type events to identify differences in data postings indicative of said dataflow interruption; and at least one of notifying a user of said dataflow interruption and generating a summary report indicating a status of said control application based on said analysis, wherein said summary report quantifies at least one of performance and effectiveness of said control application.	<SOH> BACKGROUND <EOH>1. Field of the Invention The embodiments of the invention generally relate to control applications and, more particularly, to a system and method for monitoring and reporting the status of a control application, such as a fault detection and classification application, in an automated manufacturing environment. 2. Description of the Related Art Advanced process control (APC) applications are increasingly used in conjunction with manufacturing technology to improve metrics, such as yield, costs, mean time between failures, etc. For example, fault detection and classification (FDC) applications use models to collect and monitor data regarding tool and/or process parameters in order to provide an early warning of tool and/or process faults and, thereby, to avoid having to scrap wafers or entire lots of wafers. However, it is often difficult to identify when a control application has failed or what the root cause of such a control application failure might be. Specifically, it is often difficult to monitor and quantify the effectiveness and performance of a control application in real-time.	<SOH> SUMMARY <EOH>In view of the foregoing, disclosed herein are embodiments of a system, method, and service that provide near real-time monitoring of a control application in a manufacturing environment in order to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within a control application during certain events (i.e., certain transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application (e.g., over a given period of time). These summary reports can, for example, quantify the performance of the control application (e.g., by indicating a percentage of events during a given period of time for which the control application should have collected data and failed) and/or quantify the effectiveness of the control application (e.g., by indicating a percentage of the events during a given period of time for which the control application had inhibit ability). Additionally, these summary reports can be generated with drill downs to provide a user with direct access to the records upon which the reports were based. More specifically, disclosed herein is an embodiment of a system for monitoring an advanced process control (APC) application (e.g., an fault detection and classification (FDC) application). The system embodiment can comprise a data retriever adapted to access a plurality of identified data sources (e.g., data logs and databases) for the control application. The data retriever can further be adapted to retrieve, from those data sources, all relevant data regarding selected events (i.e., regarding selected transactions, stages or process steps, such as selected wafer-chamber passes). That is, each time a selected event (e.g., a selected wafer-chamber pass) occurs on a new item (e.g., a wafer) being manufactured, the data retriever will collect data that is associated with that selected event and that is stored in the data sources of the control application. The system embodiment can further comprise a data compiler adapted to compile this data in order to generate records of dataflow paths within the control application for specific events. Event dataflow path records can be time-stamped and stored by the data compiler on a data storage device. The system embodiment can further comprise a records analyzer adapted to perform an analysis of the records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application. Specifically, a comparison between a dataflow path record for a current event (i.e., a near real-time event) and historical dataflow path records (i.e., dataflow path records of prior events of the same type) can be performed by the analyzer to detect a dataflow interruption. The analyzer can further be adapted to determine the locations of each of the detected dataflow interruptions. Based on the location of a dataflow interruption, the control application failure can be classified. The system embodiment can further comprise a summary report generator and a graphical user interface (GUI). This summary report generator can be adapted to generate a summary report indicating the status of the control application (e.g., over a given period of time), based on the records. More particularly, the summary report can be generated based on the above-described analysis of the records. The GUI can be used to display the report. For example, the summary report generator can be adapted to generate a summary report that quantifies the performance of the control application (i.e., How well did the control application perform its functions?) and/or the effectiveness of the control application (What is the effective coverage of the control application?). In order to quantify the performance of the control application, the summary report can comprise the following entries: an entry that specifies the total number of events, an entry that specifies the number of events covered by a control application model, an entry that specifies the number of broken arrows, an entry that specifies the percentage of broken arrows, etc. In order to quantify the effectiveness of the control application, the summary report can comprise the following entries: an entry that specifies the total number of events, an entry that specifies the number of events covered by control application models, an entry that specifies the best-case percentage of control application coverage, an entry that specifies the number of events covered by control application models where the control application had inhibit ability, an entry that specifies the current percentage of coverage by control application models, etc. Quantification of performance and/or effectiveness of the control application can be based on some user-specified or default grouping (e.g., in wafer processing the grouping can be by tool type, by technology, by technology center, by chamber, by recipe, etc.) Additionally, the summary report generator can be adapted to generate the summary report with drill down functions. Such drill down functions can be used to allow a user to link via the GUI to the records upon which the different line items in the summary report are based. Also disclosed herein are embodiments of a method and an associated service for monitoring an advanced process control (APC) application, such as a fault detection and classification (FDC) application. Generally, the method embodiments can comprise identifying and accessing a plurality of data sources (e.g., data logs and databases) for the control application. The method can further comprise retrieving, from those data sources, all relevant data regarding selected events (i.e., data regarding selected transactions, stages, process steps or the like within the manufacturing environment, such as wafer-chamber passes). That is, each time a selected event occurs (e.g., each time a selected wafer-chamber pass is performed on a new wafer) all relevant data that is associated with the selected event and that is stored by the control application in its data sources will be collected. The method can further comprise compiling this data in order to generate records of dataflow paths within the control application for specific events. Event dataflow path records can be time-stamped and stored on a data storage device. The method can further comprise performing an analysis of the dataflow path records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application. Specifically, the process of analyzing the records can comprise performing a comparison between a dataflow path record of a current event (i.e., a near real-time event) and historical dataflow path records (i.e., the dataflow path records of prior events of the same type) to detect a dataflow interruption. The process of analyzing the records can further comprise analyzing the dataflow path records to determine the location of each dataflow interruption. Based on the location of the dataflow interruption, the control application failure can be classified. Notification (e.g., reports, alarms, etc.) can be provided to users of such control application failures and their root causes. In addition to detecting control application failures and determining the root causes of those failures, the method can comprise generating summary reports indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records, and outputting or displaying (e.g., on a graphical user interface (GUI)) the summary reports. For example, each summary report can quantify the performance and/or the effectiveness of the control application over a given time period, as discussed above. Also, as discussed above, the summary report can be generated according to some grouping (e.g., in wafer processing the grouping can be by tool type, by technology, by technology center, etc.). Furthermore, each summary report can be generated with drill down functions allowing a user to link directly to the dataflow path records, upon which the report was based, using the GUI. Finally, also disclosed are embodiments of a program storage device readable by computer and tangibly embodying a program of instructions executable by the computer to perform the above-described method of monitoring a control application. These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is related to the following co-pending applications filed concurrently herewith by the same Applicants and assigned to the same Assignee, namely, International Business Machines Corporation (IBM Corporation): “A TOOL FOR REPORTING THE STATUS OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT”, Attorney Docket No. BUR920070078US1; “A METHOD FOR REPORTING THE STATUS AND DRILL-DOWN OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT”, Attorney Docket No. BUR920070147US2; and “A TOOL FOR REPORTING THE STATUS AND DRILL-DOWN OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT”, Attorney Docket No. BUR920070147US1. The complete disclosures of these related co-pending applications are incorporated herein by reference. BACKGROUND 1. Field of the Invention The embodiments of the invention generally relate to control applications and, more particularly, to a system and method for monitoring and reporting the status of a control application, such as a fault detection and classification application, in an automated manufacturing environment. 2. Description of the Related Art Advanced process control (APC) applications are increasingly used in conjunction with manufacturing technology to improve metrics, such as yield, costs, mean time between failures, etc. For example, fault detection and classification (FDC) applications use models to collect and monitor data regarding tool and/or process parameters in order to provide an early warning of tool and/or process faults and, thereby, to avoid having to scrap wafers or entire lots of wafers. However, it is often difficult to identify when a control application has failed or what the root cause of such a control application failure might be. Specifically, it is often difficult to monitor and quantify the effectiveness and performance of a control application in real-time. SUMMARY In view of the foregoing, disclosed herein are embodiments of a system, method, and service that provide near real-time monitoring of a control application in a manufacturing environment in order to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within a control application during certain events (i.e., certain transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application (e.g., over a given period of time). These summary reports can, for example, quantify the performance of the control application (e.g., by indicating a percentage of events during a given period of time for which the control application should have collected data and failed) and/or quantify the effectiveness of the control application (e.g., by indicating a percentage of the events during a given period of time for which the control application had inhibit ability). Additionally, these summary reports can be generated with drill downs to provide a user with direct access to the records upon which the reports were based. More specifically, disclosed herein is an embodiment of a system for monitoring an advanced process control (APC) application (e.g., an fault detection and classification (FDC) application). The system embodiment can comprise a data retriever adapted to access a plurality of identified data sources (e.g., data logs and databases) for the control application. The data retriever can further be adapted to retrieve, from those data sources, all relevant data regarding selected events (i.e., regarding selected transactions, stages or process steps, such as selected wafer-chamber passes). That is, each time a selected event (e.g., a selected wafer-chamber pass) occurs on a new item (e.g., a wafer) being manufactured, the data retriever will collect data that is associated with that selected event and that is stored in the data sources of the control application. The system embodiment can further comprise a data compiler adapted to compile this data in order to generate records of dataflow paths within the control application for specific events. Event dataflow path records can be time-stamped and stored by the data compiler on a data storage device. The system embodiment can further comprise a records analyzer adapted to perform an analysis of the records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application. Specifically, a comparison between a dataflow path record for a current event (i.e., a near real-time event) and historical dataflow path records (i.e., dataflow path records of prior events of the same type) can be performed by the analyzer to detect a dataflow interruption. The analyzer can further be adapted to determine the locations of each of the detected dataflow interruptions. Based on the location of a dataflow interruption, the control application failure can be classified. The system embodiment can further comprise a summary report generator and a graphical user interface (GUI). This summary report generator can be adapted to generate a summary report indicating the status of the control application (e.g., over a given period of time), based on the records. More particularly, the summary report can be generated based on the above-described analysis of the records. The GUI can be used to display the report. For example, the summary report generator can be adapted to generate a summary report that quantifies the performance of the control application (i.e., How well did the control application perform its functions?) and/or the effectiveness of the control application (What is the effective coverage of the control application?). In order to quantify the performance of the control application, the summary report can comprise the following entries: an entry that specifies the total number of events, an entry that specifies the number of events covered by a control application model, an entry that specifies the number of broken arrows, an entry that specifies the percentage of broken arrows, etc. In order to quantify the effectiveness of the control application, the summary report can comprise the following entries: an entry that specifies the total number of events, an entry that specifies the number of events covered by control application models, an entry that specifies the best-case percentage of control application coverage, an entry that specifies the number of events covered by control application models where the control application had inhibit ability, an entry that specifies the current percentage of coverage by control application models, etc. Quantification of performance and/or effectiveness of the control application can be based on some user-specified or default grouping (e.g., in wafer processing the grouping can be by tool type, by technology, by technology center, by chamber, by recipe, etc.) Additionally, the summary report generator can be adapted to generate the summary report with drill down functions. Such drill down functions can be used to allow a user to link via the GUI to the records upon which the different line items in the summary report are based. Also disclosed herein are embodiments of a method and an associated service for monitoring an advanced process control (APC) application, such as a fault detection and classification (FDC) application. Generally, the method embodiments can comprise identifying and accessing a plurality of data sources (e.g., data logs and databases) for the control application. The method can further comprise retrieving, from those data sources, all relevant data regarding selected events (i.e., data regarding selected transactions, stages, process steps or the like within the manufacturing environment, such as wafer-chamber passes). That is, each time a selected event occurs (e.g., each time a selected wafer-chamber pass is performed on a new wafer) all relevant data that is associated with the selected event and that is stored by the control application in its data sources will be collected. The method can further comprise compiling this data in order to generate records of dataflow paths within the control application for specific events. Event dataflow path records can be time-stamped and stored on a data storage device. The method can further comprise performing an analysis of the dataflow path records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application. Specifically, the process of analyzing the records can comprise performing a comparison between a dataflow path record of a current event (i.e., a near real-time event) and historical dataflow path records (i.e., the dataflow path records of prior events of the same type) to detect a dataflow interruption. The process of analyzing the records can further comprise analyzing the dataflow path records to determine the location of each dataflow interruption. Based on the location of the dataflow interruption, the control application failure can be classified. Notification (e.g., reports, alarms, etc.) can be provided to users of such control application failures and their root causes. In addition to detecting control application failures and determining the root causes of those failures, the method can comprise generating summary reports indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records, and outputting or displaying (e.g., on a graphical user interface (GUI)) the summary reports. For example, each summary report can quantify the performance and/or the effectiveness of the control application over a given time period, as discussed above. Also, as discussed above, the summary report can be generated according to some grouping (e.g., in wafer processing the grouping can be by tool type, by technology, by technology center, etc.). Furthermore, each summary report can be generated with drill down functions allowing a user to link directly to the dataflow path records, upon which the report was based, using the GUI. Finally, also disclosed are embodiments of a program storage device readable by computer and tangibly embodying a program of instructions executable by the computer to perform the above-described method of monitoring a control application. These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which: FIG. 1 is a diagram illustrating and embodiment of the system of the invention; FIG. 2 is a table illustrating an exemplary technology summary report; FIG. 3 is a table illustrating another exemplary tool type summary report; FIG. 4 is a table illustrating yet another exemplary technology center summary report; FIG. 5 is a table illustrating an exemplary drill down from a tool type summary report; FIG. 6 is a table illustrating an exemplary drill down from the table of FIG. 5; FIG. 7 is a table illustrating an exemplary drill down from the table of FIG. 6; FIG. 8 is a flow diagram illustrating an embodiment of the method of the invention; FIG. 9 is a flow diagram illustrating another embodiment of the method of the invention; and FIG. 10 is a schematic diagram of an exemplary hardware structure that may be used to implement the system and method of the invention. DETAILED DESCRIPTION OF EMBODIMENTS The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention. In view of the foregoing, disclosed herein are embodiments of a system, method, and service that provide near real-time monitoring of a control application in a manufacturing environment in order to detect and determine the root cause of faults within the control application. Specifically, the embodiments monitor dataflow within a control application during certain events (i.e., certain transactions, stages, process steps, etc.) occurring in the manufacturing environment. A comparison of the dataflow path for a current event with the historical dataflow path records can be used to detect dataflow interruptions (i.e., fails) within the control application. The location of such a dataflow interruption can in turn be used to determine the root cause of the control application fail. Additionally, the system and method can generate summary reports indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records. These summary reports can, for example, quantify the performance of the control application (e.g., by indicating a percentage of events during a given period of time for which the control application should have collected data and failed) and/or quantify the effectiveness of the control application (e.g., by indicating a percentage of the events during a given period of time for which the control application had inhibit). These summary reports can further be generated with drill downs providing a user with direct access to the records upon which the reports were based. More specifically, referring to FIG. 1, disclosed herein is an embodiment of a system 100 for monitoring an advanced process control (APC) application (e.g., a fault detection and classification (FDC) application, a run-to-run (R2R) application, a model predictive control (MPC) application, sensor control and feedback application, etc.). Such APC applications generally collect data in a manufacturing environment and act (e.g., generate reports, provide warnings, etc.) based on that data in order to improve metrics, such as yield, costs, mean time between failures, etc. Thus, associated with each control application are data sources containing both raw and summary data. For example, the system embodiment 100 can monitor a fault detection and classification (FDC) application that uses sensors and models to collect and monitor tool and/or process parameter data in an integrated circuit manufacturing environment in order to provide summary reports and early warnings of tool and/or process faults and, thereby, to avoid having to scrap wafers or entire lots of wafers. The system embodiment 100 can comprise a data retriever 102 in communication with and adapted to access a plurality of previously identified data sources 10 associated with the control application. The data sources 10 can comprise, for example, data logs and/or database containing data (e.g., logistic data, raw data, summary data, etc.) acquired by the control application during the manufacturing process. The data logs and/or databases can be stored within storage devices of the various components of the control application and/or within a central data warehouse (e.g., a distributed manufacturing information warehouse (DMIW)). Data sources 10 associated with the control application can include, but are not limited to, the following: data sources 11 containing information from the machines supervisory program (MSP) which provides a code interface between the tools and the manufacturing execution system (MES); data sources 12 containing information about the various tools used during events (i.e., transactions, stages, process steps, etc.) occurring in the manufacturing environment; data sources 13 containing information about the various recipes used in the manufacturing environment; data sources 14 containing information about the control application models used in the manufacturing environment; and data sources 15 containing stored output (e.g., sensor records, statistical process and control (SPC) charts, etc.) of the control application in response to the different events that occur within the manufacturing environment and that are covered by control application models. For example, if the manufacturing process is an integrated circuit manufacturing process and if the control application is a fault detection and classification (FDC) application which uses statistical process control (SPC) techniques, the output data 15 of the FDC application can be entries on SPC charts, in which sensor data from the various manufacturing tools is recorded during a given wafer-chamber pass. A wafer-chamber pass (i.e., a recipe-wafer-chamber pass) refers to each time a single wafer is placed in a chamber and processed within that chamber by one or more tools according to one or more recipe-specific steps. The data retriever 102 can further be adapted to retrieve, from those data sources 10, all relevant data regarding selected events (i.e., regarding selected transactions, stages or process steps that occur during the manufacturing process, e.g., selected wafer-chamber passes that occur during wafer processing). That is, each time a selected event (e.g., a selected wafer-chamber pass) occurs on a new item (e.g., a wafer) being manufactured, the data retriever 102 will collect data that is associated with that selected event and that is stored in the various data sources 10 of the control application. The system embodiment 100 can further comprise a data compiler 104 in communication with the data retriever 102 and adapted to compile this data in order to generate records 105 of dataflow paths within the control application for specific events. For example, the dataflow path records can show that every time a specific event occurs (e.g., each time a given wafer-chamber pass is performed on a new wafer), the same postings are made to the same data sources. Event dataflow path records can be time-stamped and stored by the data compiler 104 in a data storage device 106. The system embodiment 100 can further comprise a records analyzer 108 in communication with the storage device 106 and adapted to access the records 105. The analyzer 108 is further adapted to perform an analysis of the records 105 (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application. Specifically, a comparison between a dataflow path record for a current event (i.e., a near real-time event) and historical dataflow path records for prior events of the same type previously stored in the in storage 106 can be performed by the analyzer 108 to detect a dataflow interruption. That is, such a comparison can be used to detect an interruption in the known dataflow path for that event type, as established based on the historical records stored in the data storage device. For example, if the current event is a specific wafer-chamber pass known to have control application model coverage and if, in the past, this same wafer-chamber pass resulted in the posting of certain data to a data source (e.g., a SPC chart), then no such posting indicates that a dataflow interruption has occurred and, thus, an control application failure has occurred. The analyzer 108 can further be adapted to determine the location within the control application of each dataflow interruption. Based on the location of the dataflow interruption, the control application failure can be classified. That is, a determination can be made by the analyzer 108 as to the root cause of the failure (e.g., a recipe error, model error, missing control chart, etc.). For example, in a given control application the dataflow path may be linear with data posting at different data sources sequentially (i.e., with data posting at one data source, then the next, and so on in succession). For example, in an exemplary FDC application the dataflow path may be from a machine supervisory program (MSP) to a process station for data acquisition (PSDA) to a multivariate analysis engine (e.g., MAE) to a disperser, to an SPC chart, etc. Since the flow of data is linear, failure of the data to post at a given data source will indicate that the failure has occurred upstream as opposed to downstream. While the control application dataflow path, discussed above is linear, non-linear (i.e., branching) control application dataflow paths are also anticipated and those skilled in the art will recognize that various logic applications can similarly be developed to determine the location of the dataflow interruption in such non-linear paths. The system embodiment 100 can further a means by which a user can be automatically notified of a detected control application failure and, optionally, its location. For example, the system can be adapted to send automatically generated emails, sound alarms, etc., in order to notify a user of a detected control application failure. The system embodiment 100 can further comprise a graphical user interface (GUI) 112 as well as a summary report generator 110 in communication with the analyzer 108, the data storage device 106 and the GUI 112. This summary report generator 110 can be adapted to tally up various numbers within the records 105 in order to generate summary reports 111 indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records. Such summary reports 111 can be stored in the data storage 106. The GUI 112 can be used to display the summary reports 111 automatically or in response to user queries. Specifically, the summary report generator 110 can, for example, be adapted to generate a summary report 111 that quantifies, for a given time period, the performance of the control application (i.e., How well did the control application perform its functions?) and/or the effectiveness of the control application (What is the effective coverage of the control application?). Quantification of performance and/or effectiveness of the control application can be for a specified period of time and based on some user-specified or default grouping (e.g., by technology type, by tool type, by technology center, by chamber, by model, by recipe, etc.) as specified in a user query. For example, in integrated circuit manufacturing, one such grouping can be by technology type. Technology type can be defined as an aggregate of processes that define the manufacturing process (e.g., in integrated circuit manufacturing, 300 mm technology refers to processing of 300 mm wafers, 90 nm technology refers to wafer processing during which the minimum gate width is 90 nm, etc.). FIG. 2 provides a table illustrating an exemplary summary report 200 by technology type 210 (300 mm technology) over a given time period 215 (06/02/2007-06/08/2007), where column 220 specifies different technologies within the 300 mm technology type (e.g., 130 nm Logic, 90 nm Logic, 45 nm Logic, etc.). Another grouping in integrated circuit manufacturing can be by tool type. Tool type can be defined as a collection of tools that perform a similar process, for example, reactive ion etch (RIE) tools contain both plasma etch and plasma strip tools. FIG. 3 provides a table illustrating an exemplary summary report 300 by tool type 310 over a given time period 315 (06/02/2007-06/08/2007), where column 320 specifies the different tools by tool identification number (ID) and where each of the identified tools, in this case, is within a given back end of the line reactive ion etch (BEOL_RIE) tool type (i.e., a tool type that performs back end of the line (BEOL) reactive ion etch (RIE) processes). Yet another grouping in integrated circuit manufacturing can be by technology center. Technology center can be defined as a collection of process type (e.g., rapid thermal processing (RTP), ion implantation (ION), chemical mechanical polishing (CMP), metal film deposition (MTL), insulator deposition (INS), wet clean processing (WET), plating (PLT), reactive ion etching (RIE), furnace (FRN), etc. FIG. 4 provides a table illustrating an exemplary summary report 400 by technology center 410 over a given time period 415 (06/02/2007-06/08/2007), where column 420 specifies different processes used. In order to quantify the performance of the control application, the summary report can comprise, for example, the following entries, for each row beginning with a technology, tool or technology center entry in the first column (see columns 220 of FIG. 2, 320 of FIG. 3, and 420 of FIG. 4): (1) an entry that specifies the total number of events performed in that technology, by that tool, with that process, during the given period of time (see columns 225 of FIG. 2, 325 of FIG. 3, and 425 of FIG. 4); (2) an entry that specifies the number of events covered by control application models (see columns 230 of FIG. 2, 330 of FIG. 3, and 430 of FIG. 4); (3) an entry that specifies the number of broken arrows (i.e., the number of events performed in that technology, by that tool or with that process, during the given time period, for which the control application should have collected data and failed); and/or (4) an entry that specifies the percentage of broken arrows (i.e., the percentage of events performed in that technology, by that tool or with that process, during the given period of time, for which the control application should have collected data and failed over the total number of events that occurred during that same time period, see columns 250 of FIG. 2, 350 of FIG. 3, and 450 of FIG. 4), etc. In order to quantify the effectiveness of the control application, the summary report can comprise, for example, the following entries, for each row beginning with a technology, tool or technology center entry in the first column (see columns 220 of FIG. 2, 320 of FIG. 3, and 420 of FIG. 4): (1) an entry that specifies the total number of events performed in technology, by that tool or with that process, during the given period of time (see columns 225 of FIG. 2, 325 of FIG. 3, and 425 of FIG. 4); (2) an entry that specifies the number of events covered by control application models (see columns 230 of FIG. 2, 330 of FIG. 3, and 430 of FIG. 4); (3) an entry that specifies the best-case percentage of control application coverage (i.e., an entry that specifies the percentage of events covered by control application models out of the total number of events, see columns 235 of FIG. 2, 335 of FIG. 3, and 435 of FIG. 4); (4) an entry that specifies the number of events covered by control application models where the control application had inhibit ability (see columns 240 of FIG. 2, 340 of FIG. 3, and 440 of FIG. 4),; and/or (5) an entry that specifies the current percentage of coverage by control application models (i.e., the percentage of events during a given period of time for which the control application had inhibit ability out of the total number of events, see columns 255 of FIG. 2, 355 of FIG. 3, and 455 of FIG. 4), etc. Inhibit ability refers to the control applications ability to stop (i.e., inhibit) the process if a fail is detected (i.e., if a determination is made by an FDC application that a given tool or process is outside set parameters). Additionally, the summary report generator 110 can be adapted to generate summary reports with drill down functions. Such drill down functions can be multi-tiered and can be used to allow a user to link via the graphical user interface to the records upon which the different line items in each summary report are based. That is, referring to FIGS. 2-4, the various entries may be selected providing additional details regarding, status, errors, performance and coverage. For example, from a tool type summary report a user may select a specific Tool ID (e.g., JJ05) in order to pull up the table of FIG. 5. The table of FIG. 5 breaks down the total number of wafer chamber passes performed by tool ID JJ05, according to different recipe-tool-chamber combinations. That is, each row identifies the number of wafer-chamber passes performed by tool ID JJ05, using the same recipe-tool-chamber combination. The first row of FIG. 5 illustrates a recipe-tool-chamber combination in which the recipe is new such that there is no comparison data for broken arrow identification. However, the third row of FIG. 5 illustrates a recipe-tool-chamber combination resulting in a broken arrow (i.e., an error). From the table of FIG. 5, a user may select the specific recipe-tool-chamber that resulted in an error (i.e., row 3) in order to pull up the table of FIG. 6. The table of FIG. 6 breaks down each of the wafer-chamber passes that were performed using the error producing recipe-tool-chamber combination of row 3 of FIG. 5 by wafers. From the table of FIG. 6, a user may select an individual wafer (e.g., 90K0IF3PKOF2) in order to pull up the table of FIG. 7. The table of FIG. 7 provides the root cause details of the error relative to that individual wafer. Referring to FIG. 8, also disclosed herein are embodiments of a method for monitoring an advanced process control (APC) application (e.g., a fault detection and classification (FDC) application, a run-to-run (R2R) application, a model predictive control (MPC) application, sensor control and feedback application, etc.) that collects data in a manufacturing environment and acts based on that data in order to improve metrics, such as yield, costs, mean time between failures, etc. Specifically, a broad embodiment of the method can comprise identifying and accessing a plurality of data sources for the control application (802). The data sources can comprise, for example, data logs and/or databases containing data (e.g., logistic data, raw data, summary data, etc.) acquired by the control application during the manufacturing process. These data logs and/or databases can be stored within storage devices of the various components of the control application and/or within a central data warehouse (e.g., a distributed manufacturing information warehouse (DMIW)). The data sources associated with the control application can include, but are not limited to, the following: data sources containing information from a machines supervisory program (MSP) which provides a code interface between the manufacturing tools and the manufacturing execution system (MES) (803); data sources containing information about the various tools used during events (i.e., transactions, stages, process steps, etc.) occurring in the manufacturing environment) (804); data sources containing information about the various recipes used in the manufacturing environment (805); data sources containing information about the control application models used in the manufacturing environment (806); and data sources containing stored outputs of the control application (e.g., sensor records, statistical process and control (SPC) charts, etc.) following events that occurs within the manufacturing environment and that are covered by control application models (807). The method can further comprise retrieving, from those data sources, all relevant data regarding selected events (i.e., data regarding selected transactions, stages, process steps or the like within the manufacturing environment, such as wafer-chamber passes) (808). That is, each time a selected event occurs (i.e., each time the transaction is performed on a new item, such as a wafer, being manufactured) data that is associated with the selected event and that is stored by the control application in its data sources will be collected. The method can further comprise compiling this data in order to generate records of dataflow paths within the control application for specific events (810). These dataflow path records can show that every time a specific event occurs, the same postings are made to the same data sources. Event dataflow path records can be time-stamped and stored on a data storage device. (812) The method can further comprise performing an analysis of the dataflow path records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect any dataflow interruptions within the control application (814). Specifically, the process of analyzing the records can comprise performing a comparison between a dataflow path record of a current event (i.e., a near real-time event) and historical dataflow path records (i.e., the dataflow path records of prior events of the same type) to detect a dataflow interruption. That is, such a comparison can be used to detect any interruption in the known dataflow path for that event type, as established based on the historical records stored in the data storage device. For example, if a given event is known to have control application coverage and if, in the past, this same event resulted in the posting of certain data to the data sources, then no such posting indicates that a dataflow interruption has occurred and, thus, indicates that a control application failure has occurred. The process of analyzing the records can further comprise analyzing the dataflow path records to determine the location of each dataflow interruption. Based on the location of the dataflow interruption, the control application failure can be classified. That is, a determination can be made as to the root cause of the failure (e.g., a recipe error, model error, missing control chart, etc.). Notification (e.g., reports, alarms, etc.) can be provided to users of such control application failures and their root causes (816). In addition to detecting control application failures and determining the root causes of those failures, the method can comprise generating a summary report indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records, and outputting or displaying (e.g., on a graphical user interface (GUI)) the summary report (818). This summary report can, for example, quantify the performance (819) and/or the effectiveness (820) of the control application. As discussed in detail above and illustrated in the exemplary summary reports of FIGS. 2-4, the process of generating the summary report can comprise quantifying the performance of the control application by providing in the report one or more entries that reflect how well the control application performed its functions and/or quantifying the effectiveness of the control application by providing in the report one or more entries that reflect the coverage of the control application. Also as discussed in detail above and illustrated in FIGS. 2-4, the summary report can be generated according to some grouping (e.g., by tool type, by technology, by technology center, etc.) (821). Furthermore, the summary report can be generated with drill down functions allowing a user to link directly to the dataflow path records, upon which the report is based, using a graphical user interface (GUI) (822-823). Referring to FIG. 9, a more narrow embodiment of the method can specifically monitor a fault detection and classification (FDC) application that uses models to collect and monitor tool and/or process parameter data in an integrated circuit manufacturing environment in order to provide an early warning of tool and/or process faults and, thereby, to avoid having to scrap wafers or entire lots of wafers. This embodiment can similarly comprise identifying and accessing a plurality of data sources for the FDC application (902). The data sources can comprise, for example, data logs and/or databases containing data (e.g., logistic data, raw data, summary data, etc.) acquired by the FDC application during wafer processing. The data logs and/or databases can be stored within storage devices of the various components of the FDC application and/or within a central database (e.g., a distributed manufacturing information warehouse (DMIW)). The data sources associated with the FDC application can include, but are not limited to, the following: data sources containing information from a machines supervisory program (MSP) which provides a code interface between the manufacturing tools and the manufacturing execution system (MES) (903); data sources containing information about the various tools used during wafer-chamber passes (904); data sources containing information about the various recipes used during wafer-chamber passes (905); data sources containing information about the FDC models (906); and data sources containing stored output of the FDC application (907). Specifically, if the FDC application uses statistical process control (SPC) techniques, the output of the FDC application can be SPC charts, in which sensor data from manufacturing tools used during a given wafer-chamber pass is recorded. As mentioned above, a wafer-chamber pass (i.e., a recipe-wafer-chamber pass) refers to each time a single wafer is placed in a chamber and processed within that chamber by one or more tools according to one or more recipe-specific steps. This embodiment can further comprise retrieving, from those data sources, all relevant data regarding selected wafer-chamber passes (908). That is, each time a selected wafer-chamber pass is performed on a new wafer, data that is associated with the selected event and that is stored will be collected from the data sources of the FDC application. This embodiment can further comprise compiling the collected data in order to generate records of dataflow paths within the FDC application for specific wafer-chamber passes (910). These dataflow path records can show that every time a specific wafer-chamber pass is performed on a new wafer, the same postings are made to the same SPC chart. Event dataflow path records can be stored on a data storage device. This embodiment can further comprise performing an analysis of the dataflow path records (e.g., in response to a specific query and/or automatically in response to a continual query) in order to detect a dataflow interruption within the FDC application (914). Specifically, the process of analyzing the records can comprise performing a comparison between a dataflow path record of a current wafer-chamber pass (i.e., a near real-time wafer-chamber pass) and historical dataflow path records for the same wafer-chamber pass to detect a dataflow interruption. That is, such a comparison can be used to detect an interruption in the known dataflow path for that specific wafer-chamber pass, as established based on the records stored in the data storage device. More specifically, if a specific wafer-chamber pass is known to have FDC model coverage and if, in the past, that same wafer-chamber pass resulted in the posting of certain data to a SPC chart, then no such posting indicates that a dataflow interruption has occurred and, thus, indicates that an FDC application failure has occurred. The process of analyzing the records can further comprise analyzing the dataflow path records to determine the location of the FDC application failure. Based on the location of the dataflow interruption, the FDC failure can be classified. That is, a determination can be made as to the root cause of the FDC failure (e.g., a recipe error, model error, missing control chart, etc.). Notification (e.g., reports, alarms, etc.) can be provided to users of such FDC application failures and their root causes (916). In addition to detecting FDC application failures and determining the root causes of those failures, the method can comprise generating a summary report indicating the status of the fault detection and classification application (e.g., over a given period of time), based on the analysis of the records, and outputting or displaying (e.g., on a graphical user interface (GUI)) the summary report (918). This summary report can, for example, quantify the performance and/or the effectiveness of the FDC application (919-920). As discussed in detail above and illustrated in the exemplary summary reports of FIGS. 2-4, the process of generating the summary report can comprise quantifying the performance of the FDC application by providing in the report one or more entries that reflect how well the control application performed its functions (919). In order to quantify the performance of the FDC application the summary report can contain the following: (1) an entry that specifies the total number of wafer-chamber passes performed in that technology, by that tool or with that process, during the given period of time (see columns 225 of FIG. 2, 325 of FIG. 3, and 425 of FIG. 4); (2) an entry that specifies the number of wafer-chamber passes covered by FDC application models (see columns 230 of FIG. 2, 330 of FIG. 3, and 430 of FIG. 4); (3) an entry that specifies the number of broken arrows (i.e., the number of wafer-chamber passes performed in that technology, by that tool or with that process, during the given time period, for which the FDC application should have collected data and failed); and/or (4) an entry that specifies the percentage of broken arrows (i.e., the percentage of wafer-chamber passes performed in that technology, by that tool or with that process, during the given period of time, for which the FDC application should have collected data and failed over the total number of wafer-chamber passes that occurred during that same time period, see columns 250 of FIG. 2, 350 of FIG. 3, and 450 of FIG. 4), etc. Also, as discussed in detail above and illustrated in the exemplary summary reports of FIGS. 2-4, the process of generating the summary report can comprise quantifying the effectiveness of the FDC application by providing in the report one or more entries that reflect the coverage of the FDC application (920). In order to quantify the effectiveness of the FDC application, the summary report can contain the following: (1) an entry that specifies the total number of wafer-chamber passes performed in that technology, by that tool or with that process, during the given period of time (see columns 225 of FIG. 2, 325 of FIG. 3, and 425 of FIG. 4); (2) an entry that specifies the number of wafer-chamber passes covered by FDC application models (see columns 230 of FIG. 2, 330 of FIG. 3, and 430 of FIG. 4); (3) an entry that specifies the best-case percentage of FDC application coverage (i.e., an entry that specifies the percentage of wafer-chamber passes covered by FDC application models out of the total number of wafer-chamber passes, see columns 235 of FIG. 2, 335 of FIG. 3, and 435 of FIG. 4); (4) an entry that specifies the number of wafer-chamber passes covered by control application models where the control application had inhibit ability (see columns 240 of FIG. 2, 340 of FIG. 3, and 440 of FIG. 4); and/or (5) an entry that specifies the current percentage of coverage by FDC application models (i.e., the percentage of wafer-chamber passes during a given period of time for which the FDC application had inhibit ability out of the total number of wafer-chamber passes, see columns 255 of FIG. 2, 355 of FIG. 3, and 455 of FIG. 4), etc. Inhibit ability refers to the control applications ability to stop (i.e., inhibit) the process if a fail is detected (i.e., if a determination is made by an FDC application that a given tool or process is outside set parameters). Also as discussed in detail above and illustrated in FIGS. 2-4, the summary report can be generated according to some grouping (e.g., by tool type, by technology, by technology center, etc.) (921). Furthermore, the summary report can be generated with drill down functions allowing a user to link directly to the dataflow path records, upon which the report is based, using a graphical user interface (GUI) (see FIGS. 5-7 and discussion above, 922-923). In addition to the method embodiments, described above, also disclosed herein are associated service embodiments in which the method of the invention is specifically performed for another, for example, performed by a computer service provider for a manufacturing customer, usually for a fee. The embodiments of the invention can further take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment including both hardware and software elements. In an embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, the embodiments of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk—read only memory (CD-ROM), compact disk—read/write (CD-R/W) and DVD. A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output (I/O) devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters. A representative hardware environment for practicing the embodiments of the invention is depicted in FIG. 10. This schematic drawing illustrates a hardware configuration of an information handling/computer system in accordance with the embodiments of the invention. The system comprises at least one processor or central processing unit (CPU) 10. The CPUs 10 are interconnected via system bus 12 to various devices such as a random access memory (RAM) 14, read-only memory (ROM) 16, and an input/output (I/O) adapter 18. The I/O adapter 18 can connect to peripheral devices, such as disk units 11 and tape drives 13, or other program storage devices that are readable by the system. The system can read the inventive instructions on the program storage devices and follow these instructions to execute the methodology of the embodiments of the invention. The system further includes a user interface adapter 19 that connects a keyboard 15, mouse 17, speaker 24, microphone 22, and/or other user interface devices such as a touch screen device (not shown) to the bus 12 to gather user input. Additionally, a communication adapter 20 connects the bus 12 to a data processing network 25, and a display adapter 21 connects the bus 12 to a display device 23 which may be embodied as an output device such as a monitor, printer, or transmitter, for example. Therefore, disclosed above are embodiments of the invention that provide near real-time monitoring of a control application in a manufacturing environment in order to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within a control application during certain events (i.e., certain transactions, stages, process steps, etc.). By comparing a dataflow path for a near real-time event with historical dataflow path records, dataflow interruptions (i.e., fails) within the control application can be detected. By determining the location of such a dataflow interruption, the root cause of the control application fail can be determined. Additionally, the invention can generate summary reports indicating the status of the control application (e.g., over a given period of time), based on the analysis of the records. For example, the summary reports can quantify the performance of the control application (e.g., by indicating a percentage of events during a given period of time for which the control application should have collected data and failed) and/or can quantify the effectiveness of the control application (e.g., by indicating a percentage of the events during a given period of time for which the control application had inhibit ability). These summary reports can further be generated with drill downs to provide a user with direct access to the records upon which the reports were based. The information made available to users by the disclosed embodiments (i.e., control application failure notices, root cause of failure notices, summary reports and drill downs) will allow users to act in order to ultimately improve yield and enhance productivity. For example, this information may precipitate rerouting of products to different tool types or technology centers with control application coverage. Identification of tools with control application coverage and maximizing use of such tools will minimizes scrap events. The information will allow users to act in order to optimize equipment utilization. That is, the information may be used to track tool performance and availability statistics for production control and management and further to make production decisions, such as fab loading decisions. In an indirect way, the information may be used to monitor equipment availability (i.e., equipment up-time). Finally, the information may be used to identify problem areas within the control application and to prioritize repairs. The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the invention have been described in terms of embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.	G	60G06	161G06F	19	00
11619549	US20080163164A1-20080703	SYSTEM AND METHOD FOR MODEL-DRIVEN DASHBOARD FOR BUSINESS PERFORMANCE MANAGEMENT	ACCEPTED	20080619	20080703	[]	G06F944	["G06F944"]	8843883	20070103	20140923	717	104000	75570.0	WEI	ZHENG	[{"inventor_name_last": "Chowdhary", "inventor_name_first": "Pawan Raghunath", "inventor_city": "Montrose", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Pinel", "inventor_name_first": "Florian Alexandre", "inventor_city": "New York", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Palpanas", "inventor_name_first": "Themistoklis", "inventor_city": "Trento", "inventor_state": "", "inventor_country": "IT"}, {"inventor_name_last": "Chen", "inventor_name_first": "Shyh-Kwei", "inventor_city": "Chappaqua", "inventor_state": "NY", "inventor_country": "US"}]	A system, method, and framework resulting therefrom, for a model-driven dashboard for business performance management, which includes capturing business dashboard model requirements at a business model level by providing at least one user-customizable model for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using the at least one user-customizable model, automatically generating code for a deployable dashboard application.	1. A method of capturing business dashboard model requirements at a business model level, the method comprising: providing at least one user-customizable model for capturing functionality of a deployable dashboard. 2. A method of capturing business dashboard model requirements at a business model level, the method comprising: providing at least one user-customizable model for capturing functionality of a dashboard; and after said user defines the functionality of the dashboard using said at least one user-customizable model, automatically generating code for a deployable dashboard application. 3. The method according to claim 2, wherein the generated code defines at least one of: management of data to be displayed by the dashboard, wherein said management includes creating databases and access to said databases; design of views of the data by the dashboard; navigation among said views of the dashboard; and assignment of access privileges to users of the dashboard, wherein each of said users can only access respective data and views that are relevant to said each of said users. 4. The method according to claim 2, wherein said models define at least one of: data to be displayed by said dashboard, users of said dashboard, roles and access privileges of said users, content of each dashboard page view, and navigation among dashboard page views. 5. The method according to claim 2, wherein said models define at least one of a definition of metrics and related context information to be displayed on the dashboard, organization of dashboard information into pages, and definition of navigation paths among said pages, and assignment of access control privileges to the dashboard information, based on user roles. 6. The method according to claim 2, wherein said at least one user-customizable model includes at least one of a model for modeling data, a model for modeling users and the user's data access privileges, and a model for modeling navigation among data views. 7. The method according to claim 2, further comprising: capturing artifacts of at least one of the user-customizable models from a storage unit; transforming the at least one user-customizable model into a meta-model; and automatically generating said code for said deployable dashboard application based on said meta-model. 8. The method according to claim 2, wherein said dashboard comprises: a business performance management (BPM) dashboard. 9. The method according to claim 2, wherein the deployable dashboard application includes a software component for transformation of at least one of: models to meta models; and meta models to a deployable component. 10. The method according to claim 2, further comprising: grouping artifacts as metagroups of said at least one user-customizable model. 11. The method according to claim 2, further comprising: defining at least one of report templates and page navigation of said at least one user-customizable model. 12. The method according to claim 2, further comprising: defining users' roles and said users' access in said at least one user-customizable model as at least one of: User Role to Metric Group; and User Role to Page Template and Navigation. 13. The method according to claim 2, further comprising: capturing a User Role to Fine grained Data Access of said at least one user-customizable model. 14. A tool for capturing said business dashboard model requirements at said business model level and automatically generating said code for said deployable dashboard application, according to claim 2, wherein said tool comprises a Rational Software Architect (RSA) Modeler. 15. An Extensible Markup Language (XML) Schema for capturing said business model requirements at said business model level and automatically generating said code for said deployable dashboard application, according to claim 2, wherein said Extensible Markup Language (XML) Schema defines an Information Technology (IT) Meta Model for capturing said at least one user-customizable model. 16. A system for model-driven dashboard design, said system comprising: at least one user-customizable model that captures functionality of a dashboard; and a dashboard code generator that automatically generates code for a deployable dashboard application after a user defines the functionality of the dashboard using said at least one user-customizable model. 17. The system according to claim 16, further comprising: a dashboard model editor for editing said at least one user-customizable model to include a dashboard report requirement based on artifacts of the at least one user-customizable model retrieved from a storage unit; and a dashboard meta-model translator that transforms the at least one user-customizable model into a meta-model, wherein said dashboard code generator automatically generates said dashboard code for creating said deployable application based on said meta-model. 18. A dashboard framework for capturing business dashboard model requirements at a business model level and automatically generating code for a deployable dashboard application, said dashboard framework comprising: a dashboard model editor that edits a formal model that represents a dashboard report requirement based on artifacts of the formal model retrieved from a storage unit; a dashboard meta-model translator that transforms the formal model into a meta-model; and a dashboard code generator that automatically generates dashboard code for creating said deployable application. 19. A computer-readable medium tangibly embodying a program of recordable, machine-readable instructions executable by a digital processing apparatus to perform the method according to claim 2. 20. A method of deploying computing infrastructure in which computer-readable code is integrated into a computing system, and combines with said computing system to perform the method according to claim 2.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention generally relates to a system and method of generating code for a model-driven dashboard for business performance management and dashboard resulting therefrom, and more particularly, to a system and method of capturing business model requirements at a business model level, including providing at least one user-customizable model (or a plurality thereof) for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using the at least one user-customizable model, automatically generating code for a deployable dashboard application. 2. Description of the Conventional Art Enterprises are leveraging information technology solutions in order to increase their productivity and their business value in the marketplace. As they adopt the paradigm of describing and monitoring their business operations in a systematic manner, the need for visually representing such processes in a model becomes critical. Nowadays, many vendors provide sophisticated tools to represent business process models and business activity monitoring models. In modern businesses, several of those processes and activities correspond to procedures that monitor and measure the performance of the business. Business Performance Management (BPM) generally includes a suite of components that are used to monitor the health of the business. BPM delivers significant benefits to the businesses, by offering them the ability to react promptly to changes in their environment. BPM is enabled by the level of automation and systems integration that is currently in place in the majority of businesses. The integration of various systems in the business allows for continuous monitoring of business performance, using carefully selected metrics, also known as Key Performance Indicators (KPIs). For purposes of this disclosure, Key Performance Indicators (KPI) generally mean indicators that help organizations achieve organizational goals through the definition and measurement of progress. The KPIs generally are displayed to the analyst through a dashboard. For purposes of this disclosure, a dashboard generally means a user interface that organizes and presents information in a way that is easy to read and interpret. Dashboards can be essential elements in the day-to-day operation of modern enterprises, as they provide to the analysts the view of all the critical business metrics that reflect the performance of the business. In contrast to the usefulness, and ease of use, that dashboards represent, the amount of effort that is required for their development can sometimes be daunting. User interface development in general, and dashboard development too, can require a considerable investment of time, and can often take as much as 65-80% of the overall development time in a model-driven business transformation project.	<SOH> SUMMARY OF THE INVENTION <EOH>The present inventors have recognized that business process and business performance modeling are becoming increasingly important as modern enterprises seek ways to exploit high level design and reasoning, as well as some degree of automation in the code generation process. For example, the present inventors have recognized that the development of software using business and Information Technology (IT) models are gaining market share. Model-driven Business Performance Management (BPM) is one such example. The present inventors also have recognized that BPM Dashboards are a critical component of business process and business performance modeling. However, conventional dashboards are custom designed with large development cycles and are not connected to Business Models. The present inventors have recognized that a higher cost is needed to build and maintain such a dashboard if developed with conventional techniques. The present inventors have recognized a lack of business and IT dashboard models for representing business requirements. Also, it is difficult to translate such conventional dashboard models (if existing) into actual dashboard reports due to a lack of Meta Models. The present inventors also have recognized that the problem of defining dashboard report templates as the structure of input data is unknown, and has not been addressed, in the conventional systems and methods. The inventors have recognized that, while there may be a significant research effort towards these directions, the conventional systems and methods, to date, have focused on the problem of how to effectively model a business process, but have not addressed the problem of modeling the entire business performance monitoring process, from the source data to the dashboard (i.e., the user interface for the monitored metrics). In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional art methods and structures, an exemplary feature of the present invention is to provide an efficient and effective model-driven dashboard design system, method, and dashboard resulting therefrom, and more particularly, to capturing business dashboard model requirements at a business model level, including providing a plurality of user-customizable models for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using at least one of the plurality of user-customizable models, automatically generating code for a deployable dashboard application. The present invention extends the business performance modeling framework by providing a number of new models that enable the process of dashboard design. The model-driven approach, according to the present invention, can render the dashboard design and deployment process less time-consuming and less cumbersome. The present invention can provide automated code generation, and allow fast and easy integration of the dashboard with the final solution. The inventors of the present invention will describe the novel designing and deploying of a dashboard for a real-world business, as well as the results of such experiments, thereby demonstrating the feasibility and effectiveness of the present invention. The present invention can provide a significant reduction in terms of required development time when compared to a conventional dashboard deployment process. In an exemplary aspect, the present invention can provide Business Dashboard Models (Unified Modeling Language 2 (UML2)) and IT level Meta Models. In another exemplary aspect, the present invention can extend existing BPM Models (UML2 Profiles) to, for example: Model User Roles to Metric Access. Model User Roles to Data Access (via dimension). Model User Roles to Report Template Access. Model Metrics to the Report Templates. Model Navigation and Access. The present invention can define Meta Models (Extensible Markup Language (XML) Schema) to capture the modeling and dashboard report elements. In another exemplary aspect, the present invention can provide software components for automatic transformation of the Models to the Actual Reports. In yet another exemplary aspect, the present invention can provide Pre-defined static Data Templates and Plug-in components for defining Report Template. The exemplary aspects of the present invention provide important advantages, such as, the capability of modeling very small set of data elements (facts, dimension, hierarchies, levels). Thus, the structure of the data can be limited to few predefined sets (Data Templates). The data access and filtering logic are deterministic in nature. The exemplary aspects of the present invention can provide a mechanism to provide coarse and fine grain access to the data by roles. The context data to KPI's can be stored as dimensions. The exemplary model can allow roles to dimension level access (coarse grain access). At pre-runtime, the present invention can provide the ability to provide user to actual content access (via an administrator). The present invention can provide a software component, can transform the model into meta models, and finally, into deployable reports. The software component can be provided as a tag library (plug-in) (or equivalent software component) for Report templates, for example, for auto generation of one of the predefined data sets, providing filtering functionality, etc. The present invention can provide assistance to a Report template (user defined), for example, by selecting one of the data structure sets for the template, using provided tag library and Application Programming Interfaces (API's) to access the data, etc. The conventional systems and methods generally deal with the dashboard at the data level, not at the modeling level. One exemplary aspect of the invention is directed to a method of capturing business dashboard model requirements at a business model level, which includes automatically generating code for a deployable dashboard application based on providing a plurality of user-customizable models for capturing the functionality of a the deployable dashboard. Another exemplary aspect of the invention is directed to a method of capturing business dashboard model requirements at a business model level, which includes providing a plurality of user-customizable models for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using at least one of the plurality of user-customizable models, automatically generating code for a deployable dashboard application. Yet another exemplary aspect of the invention is directed to a tool for capturing business dashboard model requirements at a business model level and automatically generating code for a deployable dashboard application, wherein the tool includes a Rational Software Architect (RSA) Modeler. A further exemplary aspect of the invention is directed to an Extensible Markup Language (XML) Schema for capturing business model requirements at a business model level and automatically generating code for a deployable dashboard application, wherein the Extensible Markup Language (XML) Schema defines an Information Technology (IT) Meta Model for capturing the user-customizable models. Yet another exemplary aspect of the invention is directed a system for model-driven dashboard design, which includes at least one user-customizable model for capturing functionality of a dashboard, a dashboard code generator for automatically generating code for a deployable dashboard application after a user defines the functionality of the dashboard using at least one of the plurality of user-customizable models. Still another exemplary aspect of the invention is directed to a dashboard framework for capturing business dashboard model requirements at a business model level and automatically generating code for a deployable dashboard application, which includes a dashboard model editor that edits a formal model that represents a dashboard report requirement based on artifacts of the formal model retrieved from a storage unit, a dashboard meta-model translator that transforms the formal model into a meta-model, and a dashboard code generator that automatically generates dashboard code for creating the deployable application. Another exemplary aspect of the invention is directed to a computer-readable medium tangibly embodying a program of recordable, machine-readable instructions executable by a digital processing apparatus to perform the exemplary method according to the present invention. Still another exemplary aspect of the invention is directed to a method of deploying computing infrastructure in which computer-readable code is integrated into a computing system, and combines with the computing system to perform the method according to the present invention.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a system and method of generating code for a model-driven dashboard for business performance management and dashboard resulting therefrom, and more particularly, to a system and method of capturing business model requirements at a business model level, including providing at least one user-customizable model (or a plurality thereof) for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using the at least one user-customizable model, automatically generating code for a deployable dashboard application. 2. Description of the Conventional Art Enterprises are leveraging information technology solutions in order to increase their productivity and their business value in the marketplace. As they adopt the paradigm of describing and monitoring their business operations in a systematic manner, the need for visually representing such processes in a model becomes critical. Nowadays, many vendors provide sophisticated tools to represent business process models and business activity monitoring models. In modern businesses, several of those processes and activities correspond to procedures that monitor and measure the performance of the business. Business Performance Management (BPM) generally includes a suite of components that are used to monitor the health of the business. BPM delivers significant benefits to the businesses, by offering them the ability to react promptly to changes in their environment. BPM is enabled by the level of automation and systems integration that is currently in place in the majority of businesses. The integration of various systems in the business allows for continuous monitoring of business performance, using carefully selected metrics, also known as Key Performance Indicators (KPIs). For purposes of this disclosure, Key Performance Indicators (KPI) generally mean indicators that help organizations achieve organizational goals through the definition and measurement of progress. The KPIs generally are displayed to the analyst through a dashboard. For purposes of this disclosure, a dashboard generally means a user interface that organizes and presents information in a way that is easy to read and interpret. Dashboards can be essential elements in the day-to-day operation of modern enterprises, as they provide to the analysts the view of all the critical business metrics that reflect the performance of the business. In contrast to the usefulness, and ease of use, that dashboards represent, the amount of effort that is required for their development can sometimes be daunting. User interface development in general, and dashboard development too, can require a considerable investment of time, and can often take as much as 65-80% of the overall development time in a model-driven business transformation project. SUMMARY OF THE INVENTION The present inventors have recognized that business process and business performance modeling are becoming increasingly important as modern enterprises seek ways to exploit high level design and reasoning, as well as some degree of automation in the code generation process. For example, the present inventors have recognized that the development of software using business and Information Technology (IT) models are gaining market share. Model-driven Business Performance Management (BPM) is one such example. The present inventors also have recognized that BPM Dashboards are a critical component of business process and business performance modeling. However, conventional dashboards are custom designed with large development cycles and are not connected to Business Models. The present inventors have recognized that a higher cost is needed to build and maintain such a dashboard if developed with conventional techniques. The present inventors have recognized a lack of business and IT dashboard models for representing business requirements. Also, it is difficult to translate such conventional dashboard models (if existing) into actual dashboard reports due to a lack of Meta Models. The present inventors also have recognized that the problem of defining dashboard report templates as the structure of input data is unknown, and has not been addressed, in the conventional systems and methods. The inventors have recognized that, while there may be a significant research effort towards these directions, the conventional systems and methods, to date, have focused on the problem of how to effectively model a business process, but have not addressed the problem of modeling the entire business performance monitoring process, from the source data to the dashboard (i.e., the user interface for the monitored metrics). In view of the foregoing and other exemplary problems, drawbacks, and disadvantages of the conventional art methods and structures, an exemplary feature of the present invention is to provide an efficient and effective model-driven dashboard design system, method, and dashboard resulting therefrom, and more particularly, to capturing business dashboard model requirements at a business model level, including providing a plurality of user-customizable models for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using at least one of the plurality of user-customizable models, automatically generating code for a deployable dashboard application. The present invention extends the business performance modeling framework by providing a number of new models that enable the process of dashboard design. The model-driven approach, according to the present invention, can render the dashboard design and deployment process less time-consuming and less cumbersome. The present invention can provide automated code generation, and allow fast and easy integration of the dashboard with the final solution. The inventors of the present invention will describe the novel designing and deploying of a dashboard for a real-world business, as well as the results of such experiments, thereby demonstrating the feasibility and effectiveness of the present invention. The present invention can provide a significant reduction in terms of required development time when compared to a conventional dashboard deployment process. In an exemplary aspect, the present invention can provide Business Dashboard Models (Unified Modeling Language 2 (UML2)) and IT level Meta Models. In another exemplary aspect, the present invention can extend existing BPM Models (UML2 Profiles) to, for example: Model User Roles to Metric Access. Model User Roles to Data Access (via dimension). Model User Roles to Report Template Access. Model Metrics to the Report Templates. Model Navigation and Access. The present invention can define Meta Models (Extensible Markup Language (XML) Schema) to capture the modeling and dashboard report elements. In another exemplary aspect, the present invention can provide software components for automatic transformation of the Models to the Actual Reports. In yet another exemplary aspect, the present invention can provide Pre-defined static Data Templates and Plug-in components for defining Report Template. The exemplary aspects of the present invention provide important advantages, such as, the capability of modeling very small set of data elements (facts, dimension, hierarchies, levels). Thus, the structure of the data can be limited to few predefined sets (Data Templates). The data access and filtering logic are deterministic in nature. The exemplary aspects of the present invention can provide a mechanism to provide coarse and fine grain access to the data by roles. The context data to KPI's can be stored as dimensions. The exemplary model can allow roles to dimension level access (coarse grain access). At pre-runtime, the present invention can provide the ability to provide user to actual content access (via an administrator). The present invention can provide a software component, can transform the model into meta models, and finally, into deployable reports. The software component can be provided as a tag library (plug-in) (or equivalent software component) for Report templates, for example, for auto generation of one of the predefined data sets, providing filtering functionality, etc. The present invention can provide assistance to a Report template (user defined), for example, by selecting one of the data structure sets for the template, using provided tag library and Application Programming Interfaces (API's) to access the data, etc. The conventional systems and methods generally deal with the dashboard at the data level, not at the modeling level. One exemplary aspect of the invention is directed to a method of capturing business dashboard model requirements at a business model level, which includes automatically generating code for a deployable dashboard application based on providing a plurality of user-customizable models for capturing the functionality of a the deployable dashboard. Another exemplary aspect of the invention is directed to a method of capturing business dashboard model requirements at a business model level, which includes providing a plurality of user-customizable models for capturing functionality of a dashboard, and after the user defines the functionality of the dashboard using at least one of the plurality of user-customizable models, automatically generating code for a deployable dashboard application. Yet another exemplary aspect of the invention is directed to a tool for capturing business dashboard model requirements at a business model level and automatically generating code for a deployable dashboard application, wherein the tool includes a Rational Software Architect (RSA) Modeler. A further exemplary aspect of the invention is directed to an Extensible Markup Language (XML) Schema for capturing business model requirements at a business model level and automatically generating code for a deployable dashboard application, wherein the Extensible Markup Language (XML) Schema defines an Information Technology (IT) Meta Model for capturing the user-customizable models. Yet another exemplary aspect of the invention is directed a system for model-driven dashboard design, which includes at least one user-customizable model for capturing functionality of a dashboard, a dashboard code generator for automatically generating code for a deployable dashboard application after a user defines the functionality of the dashboard using at least one of the plurality of user-customizable models. Still another exemplary aspect of the invention is directed to a dashboard framework for capturing business dashboard model requirements at a business model level and automatically generating code for a deployable dashboard application, which includes a dashboard model editor that edits a formal model that represents a dashboard report requirement based on artifacts of the formal model retrieved from a storage unit, a dashboard meta-model translator that transforms the formal model into a meta-model, and a dashboard code generator that automatically generates dashboard code for creating the deployable application. Another exemplary aspect of the invention is directed to a computer-readable medium tangibly embodying a program of recordable, machine-readable instructions executable by a digital processing apparatus to perform the exemplary method according to the present invention. Still another exemplary aspect of the invention is directed to a method of deploying computing infrastructure in which computer-readable code is integrated into a computing system, and combines with the computing system to perform the method according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other exemplary purposes, aspects and advantages will be better understood from the following detailed description of an exemplary aspects of the invention with reference to the drawings, in which: FIG. 1 illustrates an exemplary high level architecture 100 of model-driven dashboard framework 155, according to an exemplary, non-limiting aspect of the present invention; FIG. 2 illustrates an exemplary Business Performance Management (BPM) dashboard meta-model (XML schema) 200, according to an exemplary, non-limiting aspect of the present invention; FIG. 3 illustrates an exemplary high-level end-to-end dashboard component flow diagram 300, according to an exemplary, non-limiting aspect of the present invention; FIG. 4 illustrates an exemplary dashboard metric (KPI) group model artifact definition 400, according to an exemplary, non-limiting aspect of the present invention; FIG. 5 illustrates an exemplary dashboard navigation model artifact definition 500, according to an exemplary, non-limiting aspect of the present invention; FIG. 6 illustrates an exemplary dashboard report template model artifact definition 600, according to an exemplary, non-limiting aspect of the present invention; FIG. 7 illustrates an exemplary user role to metric and dimension model artifact definition 700, according to an exemplary, non-limiting aspect of the present invention; FIG. 8 illustrates an exemplary user role to report template model artifact definition 800, according to an exemplary, non-limiting aspect of the present invention; FIG. 9 illustrates an exemplary user role to navigation tree model artifact definition 900, according to an exemplary, non-limiting aspect of the present invention; FIG. 10 illustrates an exemplary pre-modeling activity diagram 1000, according to an exemplary, non-limiting aspect of the present invention; FIG. 11 illustrates an exemplary modeling activity flow chart 1100, according to an exemplary, non-limiting aspect of the present invention; FIG. 12 illustrates an exemplary report template execution scenario 1200, according to an exemplary, non-limiting aspect of the present invention; FIG. 13 illustrates an exemplary post-modeling activity diagram 1300, according to an exemplary, non-limiting aspect of the present invention; FIG. 14 illustrates an exemplary metric groups definition model 1400, according to an exemplary, non-limiting aspect of the present invention; FIG. 15 illustrates an exemplary data model 1500, according to an exemplary, non-limiting aspect of the present invention; FIG. 16 illustrates an exemplary report template model 1600, according to an exemplary, non-limiting aspect of the present invention; FIG. 17 illustrates an exemplary navigation tree model 1700, according to an exemplary, non-limiting aspect of the present invention; FIG. 18 illustrates an exemplary role to data access mapping model 1800, according to an exemplary, non-limiting aspect of the present invention; FIG. 19 illustrates an exemplary role to navigation tree access mapping model 1900, according to an exemplary, non-limiting aspect of the present invention; FIG. 20 illustrates an exemplary role to report template access mapping model 2000, according to an exemplary, non-limiting aspect of the present invention; FIG. 21 illustrates an exemplary generated dashboard page 2100, according to an exemplary, non-limiting aspect of the present invention; FIG. 22 illustrates an exemplary hardware/information handling system 2200 for incorporating the present invention therein; and FIG. 23 illustrates a computer-readable medium (e.g., storage medium 2300) for storing/recording steps of a program of a method according to the present invention. DETAILED DESCRIPTION OF EXEMPLARY ASPECTS OF THE INVENTION Referring now to the drawings, and more particularly to FIGS. 1-23, there are shown exemplary aspects of the method and structures according to the present invention. The present invention generally relates to a system and method of business performance modeling and model-driven business transformation. For example, FIG. 1 illustrates an exemplary high level architecture 100 of model-driven dashboard framework 155, according to an exemplary, non-limiting aspect of the present invention. The present invention can provide business models 105, such as business performance management (BPM) models 115, as well as other models 110, which would be known and understood by the ordinarily skilled artisan. The present invention also can provide a template store 120 and a model store 125. The model-driven dashboard framework 155 can include, for example, a dashboard model editor 130 which can be used to capture a representation of the dashboard models. The dashboard meta-model translator 145 can then be used to transform the dashboard model from the dashboard model editor 130 into a meta-model representation. The meta-model representation can be fed into the dashboard code generator 150, which can automatically generate a deployable dashboard application 160. Moreover, the exemplary aspects of FIGS. 1 also can replace the BPM Observation Model (OM) with other business modeling approaches, without affecting the dashboard model, as exemplarily illustrated by the external modeling 140. FIG. 2 illustrates an exemplary Business Performance Management (BPM) dashboard meta-model (extensible markup language (XML) schema) 200, according to the present invention. The present invention can use a Unified Modeling Language (UML) representation, or for example, an extensible markup language (XML). FIG. 3 illustrates an exemplary high-level end-to-end dashboard component flow diagram 300, according to the present invention. The exemplary dashboard modeling methodology, according to the present invention, can be divided in the following three main activities: 1. Pre-modeling activity (e.g., see also FIG. 10); 2. Modeling activity (e.g., see also FIG. 11); and 3. Post-modeling activity (e.g., see also FIGS. 12 and 13), each of which will be described below. As exemplarily illustrated in FIG. 3, the present invention provides the user with the ability to define report templates 320, based on existing templates, or newly created templates (e.g., including a predetermined number, type, etc. of tables, charts, etc.). That is, the user can select predefined templates 305 or a plug-in component for report templates 310, from the template store 315. Referring to the exemplary pre-modeling activity diagram 1000, which is illustrated in more detail in FIG. 10, the predefined data templates 1010 (e.g., summary, detail, etc.) can include sets of fixed data structures. The view component 1020 (e.g., which can be embedded in the report templates), can include a JavaServer Pages (JSP) tag library software component, which can include, for example, an Application Programming Interface (API) to register the data template, an API to register the user and user role, an API to register the filter information, an API to register Data warehouse related information, a function to form Structured Query Language (SQL) for data extraction by role and filter, and a function to return either the Query or Data template instance to Report, etc. The predefined sample report templates 1030 can includes sets of readily available report templates incorporating framework components. The user interface (UI) designer/modeler defined report templates 1040 can include application specific custom report templates, which can be defined by an appropriate role player (e.g., administrator). The user can chose the data template and embed view components to use the framework. Turning again to the exemplary high-level end-to-end dashboard component flow diagram 300, as illustrated in FIG. 3, the present invention can provide an observation model data warehouse model 325, a dashboard model 330, a dashboard meta-model 335, and a deployment code 340. With reference to the exemplary modeling activity flow chart 1100 in FIG. 11, the observation model data warehouse model 1110 can include, for example, existing models. The dashboard model (UML) 1120 can include stereotypes to create dashboard models, such as Model User Roles to Metric Access, Model User Roles to Data Access (via dimension), Model User Roles to Report Template Access, Model Metrics to the Report Templates, Model Navigation and Access, etc. The dashboard models can be transformed into dashboard meta model (XML) 1130 (e.g., an intermediate dashboard model representation (XML instance)). The dashboard meta-model (XML) 1130 can be transformed into deployable components, such as dashboard databases tables (Data Definition Language (DDL)) 1140, dashboard application 1150 (e.g., EAR file *.ear), etc. Turning again to the exemplary high-level end-to-end dashboard component flow diagram 300, as illustrated in FIG. 3, the present invention can provide deployable dashboard components 345, users to data mapping 350 (e.g., to define access control). The deployable dashboard components 345 can capture data from the data warehouse 360 to generate view dashboard reports 370. FIG. 12 illustrates an exemplary report template execution scenario 1200, according to the present invention. As illustrated in FIG. 12, the present invention can provide a report instance including a view report plug-in (framework) 1220, a rendering component 1215, and a register component 1210, which can register the data template and user role (e.g., 1212). The view report plug-in can query 1235 the data warehouse 1230, which can provide a data template instance 1225 to the view report plug-in 1220. FIG. 13 illustrates an exemplary post-modeling activity diagram 1300, according to the present invention. As shown in FIG. 13, the dashboard (DDL) 1310 can deploy the dashboard model related data schemas at the business performance management (BPM) data warehouse. The dashboard application 1320 can deploy the application onto an appropriate platform, such as WebSphere Portal Server, WebSphere, etc. The fine grained access control 1330 (e.g., which can define actual user to content mapping) can be used by an administrator of the system to further map an actual user, or a plurality of actual users, to the content. An administrative website can be provided to perform such mapping. According to the present invention, the view component can take care of filtering the data, as per the user access. The above exemplary features of the present invention are described in more detail below. The inventors have recognized that, while there is a significant research effort towards these directions, the conventional systems and methods, to date, have focused on the problem of how to effectively model a business process, but have not addresses the problem of modeling the entire business performance monitoring process, from the source data to the dashboard (i.e., the user interface for the monitored metrics). The present invention provides an approach for dashboard development that is model-driven and can be integrated with the business performance models. The present invention adopts the business performance modeling framework, and extends it in order to capture the reporting aspects of the business operation. The present invention can provide models that can effectively represent all the elements necessary for the business performance reporting process, and the interactions among them. The present invention can demonstrate how all these models can be combined and automatically generate the final solution. The present invention can provide dashboard development that can be fast and easy, while maintaining flexibility in the design, and without sacrificing versatility or performance. The framework for dashboard design that is model-driven. The framework, according to the present invention, can include a number of user-customizable models that can effectively capture the functionality of a dashboard. The present invention can provide different models for modeling the data, the users and their data access privileges, and the navigation among the various data views. Once the user has designed the dashboard with the desired functionality using the provided models, the exemplary framework, according to the present invention, can automatically generate code for the deployment of the dashboard, leaving only minor customization issues for the developer. The generated code can cover all the aspects of the dashboard, such as: Management of the data to be displayed, involving the creation of relevant databases and access to them. Design of different views of the data, and of the navigation among those views. Assignment of access privileges to the users of the dashboard, so that each user can only access the data and views that are relevant. The present invention can permit the developer to focus on the dashboard functionality, and can relieve the developer from the burden of the user interface development experience. The benefits of such a model-driven dashboard development, according to the present invention, can include the graphical representation and easy manipulation of the solution, the error free code generation, and the ability to capture the business reporting requirement quickly and cost effectively. The conventional systems and methods have not recognized such an approach for model-driven dashboard design. Thus, the present invention can describe a framework for model-driven dashboard design. The models employed by the present invention can cover the many facets of this process, such as the data to be displayed, the users of the system, the roles and access privileges of each user, the content of each dashboard page view, and the navigation among those views. The method, according to the present invention, is complementary to business process and business performance modeling, and leverages from such models. The present invention describes how such a novel approach can interact with a specific business performance modeling approach, namely, BPM. Nevertheless, the ordinarily skilled artisan would recognize that the present invention is not customized for BPM, and can operate in conjunction with any other business process model as well. The framework, according to the present invention, can enable the automated generation of all the code necessary for the deployment of the dashboard. Therefore, the burden of tedious programming from the dashboard development team can be reduced or eliminated, and the time required for delivering the solution can be greatly reduced. The approach of the present invention can be validated using real-world scenarios. The application of the proposed method to a real problem, and demonstration of the benefits of the present invention with regards to development time and flexibility of the solution, will be described below. As described above, there is a growing trend in using model-driven methodologies for developing large system software, due to their high level abstraction and code re-use (or regeneration). They have been widely applied in related areas, such as software reuse, reverse engineering, and user interface design. The benefits of adopting model-driven design include reduced software development time, enhanced code quality, and improved code maintenance. There are also numerous related works about business processes. Widely considered as an extension of a workflow management system, business process management enables the management and analysis of operational business processes. Recent work has focused on modeling business processes, consistency checking for model integration, and composing Web services and business processes via the model-driven approach. Business processes can be implemented, for example, using a workflow or a state machine model. The workflow model is a natural representation for a business process model, modeling the sequence of tasks corresponding to the business operation. There can also be control logic and data transformations between tasks. Business Process Execution Language (BPEL) defines a program understandable language to represent such a process for web service environments. Yet, BPEL can only orchestrate the flow execution; business data are still not synchronized, correlated, or linked together for the auditing and analysis purposes. An approach that tries to overcome the above shortcomings is the Model-Driven Business Transformation (MDBT). MDBT models business operations from the point of view of a business analyst, without regard to existing or planned information technology solutions. In other words, an MDBT operation model is a truly Computation Independent Model as described by Object Management Group (OMG). The first step in creating an operation model is to identify the primary business artifacts that an enterprise must create and process to conduct its business. The operations can then be described by the set of tasks that must be performed to process those artifacts, and the roles assigned to the tasks. In our experience, such operation models combine artifact lifecycles and data in a way that is more meaningful to business analysts. As described below, MDBT can include a path to implementation of the operation model. There is also much interest around the concept of dashboards, with several conventional solutions. For example, conventional dashboard applications have been specifically designed for doing some analytics and for visualizing data. Nevertheless, these conventional approaches do not integrate with the business process and business performance models. Therefore, the conventional approaches require much effort to develop and maintain. In contrast, the present invention provides a novel method for dashboard design that is model-driven. The high-level models defined by the present invention can be integrated seamlessly with business performance models, leveraging the common parts of the design, and enabling an end-to-end design process. In addition to espousing a business artifact-centric approach to operation modeling, MDBT offers a model-driven development toolkit and technique. The tools automatically transform an operation model into a platform-independent solution composition model in UML2. In this stage of modeling, the solution architect can fill in much of the IT detail that is outside the domain of the business analyst. These details can include integration with external services, as well as role players. At each stage in the lifecycle of the business artifacts, now represented as a state machine, the architect specifies what portion of the data associated with the artifact will be available to the relevant role players and services. Following the completion of the solution composition model, MDBT code generation tools can automatically create Java 2 Platform, Enterprise Edition (J2EE) components that manage the process and provide a simple user interface by which users can interact with the solution. The automated transformations and code generation can enable rapid prototyping, greatly accelerating the development cycle, and allowing for a fast turnaround iterative development regimen. The solution composition model also can provide a platform on which an observation model can be constructed. The elements of the observation model (e.g., events) can be linked to those of the solution composition model (e.g. states and transitions) so as to define how the performance metrics will be gathered. Business Performance Management (BPM) can be an effective means of monitoring business processes. Model-based BPM normally includes an observation model that conforms to a pre-defined meta-model, such as the one provided by MDBT, which we discussed above. Entities such as input events, metrics, outbound events, situation detectors, and actions can be monitored and scheduled through the observation model. Using BPM, the present invention can detect bottlenecks of business operations in real-time or analyze them at a pre-determined schedule, and identify anomalies by correlating event sequences. Based on the observation model, actions triggered by the above situations can involve sending out email alerts or displaying statistics and aggregated information onto a dashboard. The present inventors implemented a BPM solution based on the model-driven development methodology. There are two exemplary approaches that were adopted for representing a BPM solution. The first approach utilizes the Unified Modeling Language (UML) with UML2 profile extension. With a convenient graphic user interface (GUI) tool, BPM entities and relationships can be defined using UML models. The second approach utilizes XML schemas for defining BPM entities and the relationships between the entities. Both approaches can be implemented as plug-ins on Rational Software Architecture (RSA). Although the exemplary aspects of the present invention are described under the general framework of MDBT and BPM, the ordinarily skilled artisan would know and understand that the present invention is not limited to this framework. As described in more detail below, an XML interface, for example, can be used to allow the present invention to operate with any other business process modeling frameworks. Referring now to the drawings, and more particularly to FIGS. 1-23, there are shown exemplary aspects of the method and structures according to the present invention. Model-driven Dashboard Framework With reference to FIG. 1, an exemplary high-level architecture 100 for a model-driven dashboard framework 155 will be described below. Model-driven dashboards aim at automating the reporting capabilities related to business monitoring. Therefore, they have the potential to bridge the gap between BPM models that specify the elements of a dashboard, and dashboard development, which is conventionally a manual effort (i.e., manually performed). FIG. 1 exemplary illustrates a high level architecture 100 of the proposed dashboard framework 155. As mentioned earlier, the framework 155 extends the existing BPM model in order to support the dashboard reporting needs. Specifically, the present invention extends the BPM Observation Model (OM), one of the Unified Modeling Language (UML) Models of MDBT Toolkit that captures the monitoring and alerting requirements of an enterprise. In order to visually represent these requirements as models, the OM makes use of the UML2 profiles to extend the base UML elements. The Dashboard Model employs similar techniques to represent its modeling elements, so that the solution designer can work with consistent models for the entire, end-to-end solution design. The exemplary models can capture aspects of the BPM Dashboard. For example, the model can capture a definition of metrics and related context information to be displayed on the dashboard, organization of information into pages, and definition of navigation paths among these pages, and assignment of access control privileges to the dashboard information, depending on the user roles. The ordinarily skilled artisan would know and understand that the present invention is not limited to representing the dashboard modeling artifacts using UML 2, and that the present invention can represent the dashboard modeling artifacts using other tools and techniques other than UML 2. The present invention can use popular modeling tools, such as Rational Software Architect (RSA), for capturing the UML representation of the dashboard models. The ordinarily skilled artisan would know and understand that RSA can be interchanged with any other editor supporting the UML 2 notations, within the spirit and scope of the present invention. Turning again to FIG. 1, the exemplary dashboard framework 155 can include a dashboard model editor 130, which can receive inputs from a report template storage unit 120 and a model storage unit 125. Business models 105, such as business performance management BPM 115, as well as other business models 110, can be input into the dashboard model editor 130. For illustrative purposes, the present invention uses UML for all the modeling requirements in the exemplary framework. However, the present invention also can provide an equivalent XML representation, which serves as the exemplary meta-model. In fact, the representation that the exemplary approach uses internally is the XML representation. FIG. 2 illustrates an exemplary Business Performance Management (BPM) dashboard meta-model (XML schema) definition 200, according to an exemplary, non-limiting aspect of the present invention. The transformation between the UML and the XML representations is lossless, in the sense that all the modeling elements and the relationships among them are preserved. By providing the Dashboard XML Meta-Model as an additional level of abstraction, the present invention can decouple the dashboard modeling process from the modeling of the rest of the business processes. Therefore, changes in the OM can be prevented from affecting the Dashboard Framework 155. Moreover, the present invention can replace the OM with any other business modeling approach (e.g., 110), without affecting the dashboard model (e.g., external modeling 140). When the dashboard model (e.g., 130) has been transformed into the dashboard meta-model representation (e.g., 145), the present invention can feed this representation to the dashboard code generator 150, which subsequently can produce the deployable dashboard application 160. The generated application can consist of the dashboard Application, which is the set of files that contain the actual code for the application, and the dashboard DDL, which is the set of files that generate the auxiliary structures needed by the application, such as database tables. These tables can be created in the BPM data warehouse. The dashboard application can be readily deployed on a J2EE application server. The particular choice of the application server is orthogonal to the solution of the present invention. It is noted that the exemplary code generator 150, according to the present invention, can be modified to generate deployable components for any application server. FIG. 3 exemplarily illustrates an overview of a high-level end-to-end dashboard-design process 300, according to the present invention. For example, the present invention can begin by defining custom reports (e.g., 320) to be used by the dashboard, or by simply selecting some of the predefined reports from the template data store 305. The present invention can define plug-in components for report templates 310. Atemplate store 315 can be provided. As will be discussed below, the role of these report templates 305 is to retrieve the appropriate data and handle the presentation of these data on the screen. Then, the solution designer can model the dashboard elements using the Model Editor 130, transform the result into the Dashboard Meta-Model representation 145, and invoke the Code Generator 150 to generate the deployable software components (e.g., 160). Once deployed, the Dashboard can be accessed using a web browser. The aspects of exemplary Dashboard Model elements are discussed below. Dashboard Model Artifacts The dashboard model artifacts, according to the present invention, can be classified, for example, into three categories. A first category can be related to modeling the data that are necessary for the dashboard and can include data and metric models. A second category can correspond to an abstract presentation layer, including navigation and report template models. Finally, a third category can be related to user roles and data access privileges, and can include models that define the dashboard access control, by relating user roles to data elements, as well as elements in the presentation layer. Dashboard Model Definition As discussed above, the present invention exemplarily uses UML for the entire dashboard modeling requirements because it is widely accepted in the industry, and also because it provides to the solution developer a consistent platform to work with, across the various MDBT models. The ordinarily skilled artisan would know and understand that the present invention is not limited to representing the dashboard modeling requirements using UML, and that the present invention can represent the dashboard modeling requirements using other tools and techniques other than UML. The present invention can extend the UML meta-classes and relationships by introducing new stereotypes using UML 2 profiles to model the dashboard elements. These stereotypes can then be stored as part of an existing BPM model profile. When modeling an actual solution using a modeling editor, these profiles can be applied in order to take advantage of the BPM Dashboard Model elements. Dashboard Data Model With reference again to FIG. 3, in an exemplary aspect of the present invention, it can be assumed that all the necessary data can be stored in a data warehouse 360, using a star schema. Therefore, the present invention can use the metric group model artifact definition 400, as exemplary illustrated in FIG. 4, where each data element is marked as either a dimension, or a metric. Even though the data model supported by the present invention is simple, its semantics are rich enough to be able to model many real-life scenarios. This is because it is usual for real world data-modeling problems (especially the ones that are being targeted by the present invention) to have a natural star-like representation. An example scenario may be product sale information, where the metrics can include number of units sold and revenue, and the dimensions can include geographies and time. In FIG. 4, the present invention introduces a Metric Group modeling element, which can be used for grouping of relevant metrics. Such a grouping may be useful when modeling relationships to other artifacts, where all the members of the Metric Group participate. FIG. 4 exemplarily illustrates the Metric Group UML class that connects to the Metric class in an aggregation relationship. Dashboard Navigation Model In FIG. 5, the present invention illustrates exemplary GUI modeling Elements (stereotypes), such as, a Navigation Tree, Page, and Menu classes. These three classes can form the Dashboard Navigation Model. In a typical scenario, the analyst can start by defining some pages, and then associating these pages with menus. In a last step, the analyst can introduce a Navigation Tree element, in order to capture the navigation paths among the pages, which eventually form the Dashboard reports. Dashboard Report Template Model Dashboard report templates can be used to define the information content of individual pages. For example, FIG. 6 illustrates that a Report Template can be associated with a page, and may refer to several Metric Groups. When the page is displayed on the dashboard, the information about all the metrics corresponding to the templates can be rendered on the screen. It is noted that each page can be associated with one or more Report Templates. The Report Templates also can define the details for the visual presentation of the data they contain. By creating a report template, the user can choose to display a set of metric data as a table, as a chart, or using both display modes. Dashboard Access Control Model A dashboard access control model can define all the access control properties relevant to the dashboard. Using the various modeling elements, the present invention can specify for each user role the access privileges to different parts of the data, as well to different pages of the dashboard. Thus, the dashboard users, according to their assigned roles, may only have access to a subset of the dashboard reports. FIG. 7 exemplarily illustrates how the present invention can model the above requirements in the framework. The business analyst can model the access privileges to the reporting data according to User Role (such as manager, data administrator, etc.), and by Metric Group and Dimension. The relationships between user roles and metrics, and user roles and dimensions will be exemplarily described below. According to the present invention, a “UserRole-MetricGroup” relationship specifies the access privileges of User Role to Metric Group. When the analyst creates an aggregation link between the above two modeling elements, all the users assigned to User Role gain access to all the metrics described by Metric Group. his lets the model capture the role based access to metrics. At runtime, based on this model, the system can determine what metrics to show on the dashboard based on the User Role (i.e., only those metrics for which the user has access are displayed on the dashboard). According to the present invention, a “UserRole-DimensionScope” relationship can define the User Role access privileges to various dimensions, as well as to the dimension levels in each dimension. This lets the business analyst define fine grained access control at the metric context. When the dashboard has been deployed and is ready for use, the administrator can have the ability to further refine the data access control by the specific data values, as will be described below. An “Access by Report Template” can be another aspect of dashboard-report access-control modeling. A User Role may have access to one or more Report Templates, and the business analyst may select a set of (already defined) templates and associate them to the User Role elements. This lets the dashboard framework filter the templates that are shown to the user of the dashboard. FIG. 8 exemplarily illustrates a “User Role to Report Template” relationship. The framework, according to the present invention, can permit the business analyst to define access control based on Navigation Trees, as exemplarily illustrated in FIG. 9. It is noted that a single Dashboard Model can involve several Navigation Trees. In this exemplary case, the business analyst may wish to provide different access privileges to each one of the navigation trees, according to User Role. The foregoing access control models provide a powerful and flexible toolset. Indeed, not only do the foregoing access control models provide coarse- and fine-grain access control to data, but they also allow the business analyst to design a small set of pages, which at run-time, will display different information, according to the access privileges of the user accessing the dashboard. Dashboard Model Solution Methodology An exemplary dashboard model solution methodology will now be described. Even though the model-driven approach brings efficiency to BPM solutions development, it can be beneficial to understand and follow a specific methodology that can lead to a successful and efficient solution. The exemplary dashboard modeling methodology, according to the present invention, can be divided in the following three main activities: 1. Pre-modeling activity; 2. Modeling activity; and 3. Post-modeling activity, each of which will be described below. Pre-Modeling Activity Before starting to sketch models in order to capture the dashboard requirements, the business analyst is required to understand the predefined components and templates that are included in the Dashboard Framework tool. These components can aid in quickly and efficiently designing the solution. FIG. 10 exemplarily illustrates a diagram of components 1000 which may be relevant to this activity. One of the important aspects of the exemplary framework is the predefined data templates (data structures) 1010. Since the data model generally is only comprised of a well-defined, limited set of data elements (that is, metrics and dimensions), the framework can publish predefined sets of data structures as part of the tool. Then, each report template can choose the data structures that are suitable for its reporting purposes. The framework can provide another software component, e.g., the view component 1020, which is responsible for connecting the data layer with the presentation layer of the dashboard. The view component 1020 can use the data structure and User Role elements to connect to the data sources, and can generate an instance of the data structure, which during runtime is passed to the Report Template instance (discussed below) that finally renders the visual widgets. In order to achieve seamless integration, the view components 1020 may need to be embedded in the Report Templates. In the implementation according to an exemplary aspect of the present invention, the view components can be included as JavaServer Pages (JSP) tag libraries. The present invention also can provide a set of predefined Report Templates 1030. For example, a table and a chart component can be provided. As exemplarily illustrated in FIG. 10, the framework also can support user-defined Report Templates 1040. A restriction (e.g., the only restriction) may be that the new template supports the data templates in its input. FIG. 11 exemplarily illustrates the above process of a Report Template execution scenario, according to the present invention. The view component 1020 can expose the appropriate Application Programming Interfaces (API's) to capture the data template id, user id, user role, data filters, data sources, etc. Modeling Activity After the custom Report Templates have been defined, the next step can be to model the reporting requirements. During this exemplary step, the user may need to perform the following tasks. First, the user can identify the metrics that will become part of the dashboard views, and create Metric Groups by grouping together similar metrics. Second, the user can create report templates for all the different types of information that are to be displayed on the dashboard. Third, the user can create page elements, and associate them to one or more of the report templates defined earlier. Fourth, the user can create the menu elements for the dashboard portal, and link the menu items with the corresponding pages. Finally, the user can introduce navigation tree elements in order to define the navigation flow of the portal. The different user roles that need access to the dashboard portal also can be defined. Individual users can be assigned a role by the portal administrator during the portal configuration time. Each user role can be associated with Metric Groups, Dimensions, Report Templates, and Navigation-Trees, so as to specify the access control privileges. Once the Dashboard Model is ready, it can be automatically transformed into an intermediate XML meta-model representation, according to the present invention, which can be independent of the tool used to build the Dashboard Model. Subsequently, this model can be processed by the Code Generator that produces all the required deployable software components. Post-Modeling Activity FIG. 13 exemplarily illustrates artifacts related to the post-modeling phase. The Code Generator can produce two deployable software components, for example, the Dashboard DDL 1310 and the Dashboard Application 1320. The Dashboard DDL 1310 can contain the definitions for all the tables that need to be created in the BPM Data Warehouse (e.g., 1230). The Dashboard DDL 1310 also can contain necessary SQL scripts for reading data from and inserting data in those tables. The Dashboard Application 1320 can be a J2EE application that needs to be deployed on a J2EE Application Server. The Dashboard Application 1320 can contain the web module that consists of the chosen report templates along with other supporting software components provided by the framework. As another step in the dashboard deployment procedure, the user can define fine-grain data access control 1330, according to specific data values of the warehouse (e.g., 1230). In describing the access control in the dashboard model above, it was described that the model allows access privileges to be defined based on the data dimensions. For example, the present invention can permit a particular user role to roll-up and drilldown on the geography dimension. Even though the above kind of access control can be very useful, in some cases it may not be enough. For example, consider the situation where two different managers are responsible for the Europe and America geographies. In this case, it may be desirable to restrict the access of each manager to the geography for which she is responsible. In order to achieve this fine-level access control, the present invention can augment the User Role to Dimension model with special annotations that specify the levels of each dimension that can be accessed by the User Role. Note that the present invention generally does not perform this step of access control during the modeling phase, because it depends on the specific data of the application, which are only available in the warehouse after the application has been deployed. Exemplary Case Study In order to assess the feasibility and effectiveness of the present invention, the inventors applied exemplary aspects of the present invention to real-world problems. In an exemplary case, the objective was to develop a dashboard to support the business operation of the TeleSale Representatives (TSRs) that are responsible for the sales of the entire range of a particular product across the globe. The TSRs are responsible for the entire life-cycle of a sale. Initially, a customer expresses an interest to buy, to which the TSR responds with a quote. If the customer decides to close the deal, then the quote is turned into an order. In their day-to-day operations, the TSRs need to have a concise view of their business, so as to plan their actions accordingly. The dashboard, according to the present invention, can be used to display information on both, the quotes and the orders, capturing various metrics related to these activities, such as number of quotes and orders, order channel, revenue, and others. These metrics can be organized according to several dimensions, such as time, geography, product type, customer type, and others. Furthermore, access restrictions can be in place, which limit the views of the data offered to the TSRs and the region managers. The steps of the exemplary solution development process, using the Dashboard Framework, will be described below. Dashboard Solution Model The present invention can be started by presenting the models that were created for the dashboard. Note that for brevity, in all the following diagrams, only part of the models that form the complete solution are depicted. As mentioned above, the first step can be to identify the Report Templates that are needed. If the existing, predefined templates are not suitable, then custom Report Templates can be defined. For this case study, pre-defined summary templates (e.g., OrderSummaryTemplate), as well as some custom-made templates (e.g., OrderDetailTemplate) were used. Subsequently, similar metrics were identified and grouped together as MetricGroups. As exemplarily illustrated in FIG. 14, revenue and average revenue for orders can be grouped into OrderMetricGroup, while average number of quotes and average quote value can be grouped into QuoteMetricGroup. The relationships among metrics and dimensions can be captured by a data model, as exemplarily illustrated in FIG. 15. This diagram can contain relationships that connect dimensions to metrics, as well as metric groups. The latter case can be translated as a relationship between the dimension and each one of the metrics under the Metric Group. A link between a metric and a dimension generally means that the metric can be aggregated along this dimension. In order to organize the information into different views (or pages), the present invention can use the Report Template model. FIG. 16 exemplarily shows this model for a summary view, which can display data relevant to orders and quotes. More specifically, this summary page can contain data for orders revenue and average revenue (represented by OrderMetricGroup), and average number and value of quotes (represented by QuoteMetricGroup). Once all of the pages and menus that are going to be used in the dashboard are defined, the present invention can proceed to model the Navigation Trees. The Navigation Trees can represent the paths that the dashboard user can follow when navigating from page to page. As FIG. 17 exemplarily illustrates, the present invention can define several Navigation Trees, and each page can belong to more than one Navigation Tree. Subsequently, the present invention can define all the data access privileges for the dashboard. FIG. 18 can depict the assigned privileges for the Telesales and Manager user roles, with respect to metrics and dimensions. The model that is created can allow Telesales users to access quote metrics and aggregate them along the brand dimension. In addition to the above, Manager users can also access order metrics and aggregate these metrics along the geography dimension. FIG. 18 also illustrates how the present invention can model fine-grain data access control using the dimension levels. In this example, the present invention can limit the access on the Brand and Geography data. In this example, a Telesales user can only be able to aggregate data up to the sub brand level (i.e., level 2) in the Brand dimension hierarchy. (The “own member” annotation only instructs the tool that fine-grain access control is required to be applied.) FIG. 19 and FIG. 20 exemplarily illustrate the User Role access privileges in terms of Navigation Trees and Report Templates, respectively. For the exemplary dashboard, it can be specified that Telesales and Manager users access different Navigation Trees, which translates to a different experience, both visually and content-wise. It also can be specified that Manager users can access the summary templates for the orders and the quotes, while Telesales users only have access to the quote summary template. When the modeling phase is completed, the present invention can initiate the deployment of the different software components, as described below. Dashboard Deployment There can be, for example, two deployable components generated as a result of the modeling activity. The Dashboard DDL component can be the data warehouse schema script that supports the dashboard functionality. This schema can store and manage all of the information relating to metrics, and maintain the fine grained access control to this information by user role. The Dashboard Application component can be an Enterprise Application that can be deployed on a J2EE application server, and can subsequently be accessed using a web browser. In the exemplary implementation according to the present invention, the generated application can be deployed on WebSphere Portal Server, and can use conventional commercial data visualization tools for rendering the reports (the framework provides a tag-library or equivalent software component that allows the report template to connect to various commercial data visualization tools. In FIG. 21, a screen-capture from the deployed dashboard application, according to the present invention, is exemplarily illustrated. This example illustrates a page that uses tables to display two different types of data regarding quotes (left side of the picture), and a graph to visualize these data (right side of the picture). According to the exemplary aspects of the present invention, the model-driven approach for dashboard development can provide significant savings in terms of time and cost. For example, a project that may normally require more than three months, may be completed, for example, in just three weeks using the proposed framework, according to the present invention. In addition, the dashboard developers do not need to have any in-depth knowledge of databases and data warehouses, or access control mechanisms. All these aspects of the dashboard generally can be completely hidden from the developer, and managed by the proposed framework. FIG. 22 illustrates an exemplary hardware/information handling system 2200 for incorporating the present invention therein, and FIG. 23 illustrates a computer-readable medium 2300 (e.g., signal-bearing medium, storage medium, etc.) for storing steps of a program of a method according to the present invention. FIG. 22 illustrates a typical hardware configuration of an information handling/computer system for use with the invention and which preferably has at least one processor or central processing unit (CPU) 2211. The CPUs 2211 are interconnected via a system bus 2212 to a random access memory (RAM) 2214, read-only memory (ROM) 2216, input/output (I/O) adapter 2218 (for connecting peripheral devices such as disk units 2221 and tape drives 2240 to the bus 2212), user interface adapter 2222 (for connecting a keyboard 2224, mouse 2226, speaker 2228, microphone 2232, and/or other user interface device to the bus 2212), a communication adapter 2234 for connecting an information handling system to a data processing network, the Internet, an Intranet, a personal area network (PAN), etc., and a display adapter 2236 for connecting the bus 2212 to a display device 2238 and/or printer 2239. In addition to the hardware/software environment described above, a different aspect of the invention includes a computer-implemented method for performing the above method. As an example, this method may be implemented in the particular environment discussed above. Such a method may be implemented, for example, by operating a computer, as embodied by a digital data processing apparatus, to execute a sequence of machine-readable instructions. These instructions may reside in various types of signal-bearing media. This computer-readable media or signal-bearing media may include, for example, a RAM contained within the CPU 2211, as represented by the fast-access storage for example. Alternatively, the instructions may be contained in another computer-readable media or signal-bearing media, such as a data storage disk/diskette 2300 (FIG. 23), directly or indirectly accessible by the CPU 2211. Whether contained in the disk/diskette 2300, the computer/CPU 2211, or elsewhere, the instructions may be stored on a variety of machine-readable data storage media, such as DASD storage (e.g., a conventional “hard drive” or a RAID array), magnetic tape, electronic read-only memory (e.g., ROM, EPROM, or EEPROM), an optical storage device (e.g. CD-ROM, WORM, DVD, digital optical tape, etc.), paper “punch” cards, or other suitable computer-readable media or signal-bearing media including transmission media such as digital and analog and communication links and wireless. In an illustrative embodiment of the invention, the machine-readable instructions may comprise software object code, compiled from a language such as “C”, etc. While the invention has been described in terms of several exemplary aspects, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. Further, it is noted that, Applicants' intent is to encompass equivalents of all claim elements, even if amended later during prosecution.	G	60G06	161G06F	9	44
11777180	US20080141017A1-20080612	GAMING MACHINE HAVING A SECURE BOOT CHAIN AND METHOD OF USE	ACCEPTED	20080530	20080612	[]	G06F2100	["G06F2100", "G06F15177", "H04L900", "G06F1130"]	7827397	20070712	20101102	713	002000	97901.0	REHMAN	MOHAMMED	[{"inventor_name_last": "McCoull", "inventor_name_first": "James Ross", "inventor_city": "St Peters", "inventor_state": "", "inventor_country": "AU"}, {"inventor_name_last": "Muir", "inventor_name_first": "Robert Linley", "inventor_city": "Artarmon", "inventor_state": "", "inventor_country": "AU"}]	An electronic gaming machine (EGM) comprises a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged to take at least one protective action if the first code does not match the validation code.	1. An electronic gaming machine (EGM) comprising: a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged to take at least one protective action if the first code does not match the validation code. 2. An EGM as claimed in claim 1, wherein the EGM is arranged to monitor reading of the first code by the CPU. 3. An EGM as claimed in claim 1 wherein the monitoring device is arranged to access the memory prior to the memory being accessed by the EGM. 4. An EGM as claimed in claim 1 wherein the monitoring device stores the validation code. 5. An EGM as claimed in claim 1 wherein the protective action is that the monitoring device causes the EGM to terminate or fail booting. 6. An EGM as claimed in claim 1 wherein the boot program code comprises second code and the first code comprises a hash algorithm and a pre-calculated hash of the second code, the first code being arranged such that when the CPU executes the first code, the CPU calculates a hash of the second code and compares it to the pre-calculated hash and proceeds if the hashes match. 7. An EGM as claimed in claim 6 wherein execution halts if the hashes do not match. 8. An EGM as claimed in claim 1 wherein the memory storing the boot program code is read only. 9. An EGM as claimed in claim 5 wherein the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, and the second code comprises a master public key and a decryption algorithm, the second code being arranged such that when executed by the CPU, the CPU calculates a hash of the third code, decrypts the signature to obtain the pre-calculated hash, compares the two hashes and proceeds if the hashes match. 10. An EGM as claimed in claim 9 further comprising a further memory comprising a signature of one or more external BIOS hashes, and the third code is arranged such that the CPU verifies each external BIOS hash before transferring control to any of the one or more external BIOSes. 11. An EGM as claimed in claim 9 wherein the third code is arranged such that the CPU verifies the active boot partition on the active boot device by generating a hash of the boot partition and comparing it to a hash stored on the active boot device before transferring control to the master boot record of the active boot partition. 12. A method of protecting an electronic gaming machine comprising: storing boot program code comprising first code in a memory; and monitoring initiation of a boot process in which a central processing unit reads the first code from the memory by comparing the first code read by the CPU to validation code; and taking at least one protective action if the read first code does not match the validation code. 13. A method as claimed in claim 12, comprising comparing the first code read by the CPU to the validation code. 14. A method as claimed in claim 12 comprising comparing the first code to the validation code prior to the first code being read by the CPU. 15. A method as claimed in claim 12 wherein the boot program code comprises second code and the first code comprises a pre-calculated hash of the second code, and the method comprises calculating a hash of the second code and comparing it to the pre-calculated hash and proceeding if the hashes match. 16. A method as claimed in claim 12 wherein, the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, the second code comprises a master public key (MPK), and the method comprises calculating a hash of the third code, decrypting the signature to obtain the pre-calculated hash, comparing the two hashes and proceeding if the hashes match. 17. An electronic gaming machine (EGM) comprising: a central processing unit (CPU); a memory storing boot program code; and a removable memory device in data communication with the CPU and storing authentication data comprising a public key, the CPU arranged to access the memory and initiate a boot process by reading the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory device. 18. An EGM as claimed in claim 17 wherein the authentication data is a public key. 19. An EGM as claimed in claim 17 wherein the authentication data is a certificate comprising the public key and identity data. 20. An EGM as claimed in claim 17 wherein the at least one set of code comprises the code stored in a disk partition. 21. An EGM as claimed in claim 17 wherein the at least one set of code comprises operating system code. 22. An EGM as claimed in claim 17 wherein the at least one set of code comprises code of a program. 23. An EGM as claimed in claim 17 wherein the CPU authenticates the at least one set of code by employing the authentication data to authenticate intermediate authentication data and employing the intermediate authentication data to authenticate the at least one set of code. 24. An EGM as claimed in claim 17, further arranged to authenticate the removable memory device prior to employing the authentication data. 25. An EGM as claimed in claim 17, wherein the EGM further employs a 15 monitoring device to authenticate the removable memory device. 26. A method of protecting an electronic gaming machine comprising: storing boot program code in a memory; storing authentication data in a removable memory; and initiating a boot process in which a central processing unit reads the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory. 27. A method as claimed in claim 26 wherein the authentication data is a public key. 28. A method as claimed in claim 26 wherein the authentication data is a certificate comprising the public key and identity data. 29. A method as claimed in claim 26 wherein the at least one set of code comprises the code stored in a disk partition. 30. A method as claimed in claim 26 wherein the at least one set of code comprises operating system code. 31. A method as claimed in claim 26 wherein the at least one set of code comprises code of a program. 32. A method as claimed in claim 26 comprising authenticating the at least one set of code by employing the authentication data to authenticate intermediate authentication data and employing the intermediate authentication data to authenticate the at least one set of code. 33. A method as claimed in claim 24, comprising authenticating the removable memory prior to employing the authentication data.	<SOH> BACKGROUND TO THE INVENTION <EOH>The development of an electronic gaming machine and program code to be run on gaming machines requires a great deal of effort. Further, given the nature of gambling regulations, there is a need for a high degree of confidence in the security of an electronic gaming machine. Accordingly, there is a need for electronic gaming machines that have a higher degree of security.	<SOH> SUMMARY OF THE INVENTION <EOH>In a first aspect, the invention provides an electronic gaming machine (EGM) comprising: a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged to take at least one protective action if the first code does not match the validation code. In an embodiment the EGM is arranged to monitor reading of the first code by the CPU. In an embodiment wherein the monitoring device is arranged to access the memory prior to the memory being accessed by the EGM. In an embodiment, the monitoring device stores the validation code. In an embodiment, the monitoring device is a field programmable gate array (FPGA). In an embodiment, the protective action is that monitoring device causes the EGM to terminate or fail booting. In an embodiment, the boot program code comprises second code and the first code comprises a hash algorithm and a pre-calculated hash of the second code, the first code being arranged such that when the CPU executes the first code, the CPU calculates a hash of the second code and compares it to the pre-calculated hash and proceeds if the hashes match. In an embodiment, execution halts if the hashes do not match. In an embodiment, execution proceeds with execution of the second code if the hashes match. In an embodiment, the memory storing the boot program code is read only. In an embodiment, the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, and the second code comprises a master public key (MPK) and a decryption algorithm, the second code being arranged such that when executed by the CPU, the CPU calculates a hash of the third code, decrypts the signature to obtain the pre-calculated hash, compares the two hashes and proceeds if the hashes match. In an embodiment, the gaming machine comprises a further memory comprising a signature of one or more external BIOS hashes, and the third code is arranged such that the CPU verifies each external BIOS hash before transferring control to any of the one or more external BIOSes. In an embodiment, the third code is arranged such that the CPU verifies the active boot partition on the active boot device by generating a hash of the boot partition and comparing it to a hash stored on the active boot device before transferring control to the master boot record of the active boot partition. In a second aspect, the invention provides a method of protecting an electronic gaming machine comprising: storing boot program code comprising first code in a memory; and monitoring initiation of a boot process in which a central processing unit reads the first code from the memory by comparing the first code read by the CPU to validation code; and taking at least one protective action if the read first code does not match the validation code. In an embodiment the method comprises comparing the first code read by the CPU to the validation code. In an embodiment the method comprises comparing the first code to the validation code prior to the first code being read by the CPU. In an embodiment, the boot program code comprises second code and the first code comprises a pre-calculated hash of the second code, and the method comprises calculating a hash of the second code and comparing it to the pre-calculated hash and proceeding if the hashes match. In an embodiment, the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, the second code comprises a master public key (MPK), and the method comprises calculating a hash of the third code, decrypting the signature to obtain the pre-calculated hash, comparing the two hashes and proceeding if the hashes match. In a third aspect, the invention provides an electronic gaming machine (EGM) comprising: a central processing unit (CPU); a memory storing boot program code; and a removable memory device in data communication with the CPU and storing authentication data comprising a public key, the CPU arranged to access the memory and initiate a boot process by reading the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory device. In an embodiment, the authentication data is a public key. In another embodiment, the authentication data is a certificate comprising the public key and identity data. In an embodiment, the at least one set of code comprises the code stored in a disk partition. In an embodiment, the at least one set of code comprises operating system code. In an embodiment, the at least one set of code comprises code of a program. In an embodiment, the CPU authenticates the at least one set of code by employing the authentication data to authenticate intermediate authentication data and employing the intermediate authentication data to authenticate the at least one set of code. In an embodiment, the EGM is arranged to authenticate the removable storage device prior to employing the authentication data. Persons skilled in the art will also appreciate that the first and third aspects may be combined. In an embodiment, the monitoring device may be employed to authenticate the removable storage device. In a fourth aspect, the invention provides a method of protecting an electronic gaming machine comprising: storing boot program code in a memory; storing authentication data in a removable memory; and initiating a boot process in which a central processing unit reads the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory device. Persons skilled in the art will appreciate that the first and second aspects of the invention may be combined with the third and fourth aspects.	CROSS-REFERENCE TO RELATED APPLICATIONS The present application relates to, and claims priority from, U.S. application Ser. No. 10/089,759, which claims priority as a national phase application of PCT/AU00/01192, which are herein incorporated by reference in their entirety. The present application also relates to, and claims priority from, Australian Patent Application No. 2006903776, filed Jul. 13, 2006, Australian Patent Application No. 2006907047, filed Dec. 18, 2006, and Australian Patent Application No. 2007903196, filed Jun. 14, 2007, which are herein incorporated by reference in their entirety. FIELD The present invention relates to a gaming machine and a method of protecting an electronic gaming machine. BACKGROUND TO THE INVENTION The development of an electronic gaming machine and program code to be run on gaming machines requires a great deal of effort. Further, given the nature of gambling regulations, there is a need for a high degree of confidence in the security of an electronic gaming machine. Accordingly, there is a need for electronic gaming machines that have a higher degree of security. SUMMARY OF THE INVENTION In a first aspect, the invention provides an electronic gaming machine (EGM) comprising: a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged to take at least one protective action if the first code does not match the validation code. In an embodiment the EGM is arranged to monitor reading of the first code by the CPU. In an embodiment wherein the monitoring device is arranged to access the memory prior to the memory being accessed by the EGM. In an embodiment, the monitoring device stores the validation code. In an embodiment, the monitoring device is a field programmable gate array (FPGA). In an embodiment, the protective action is that monitoring device causes the EGM to terminate or fail booting. In an embodiment, the boot program code comprises second code and the first code comprises a hash algorithm and a pre-calculated hash of the second code, the first code being arranged such that when the CPU executes the first code, the CPU calculates a hash of the second code and compares it to the pre-calculated hash and proceeds if the hashes match. In an embodiment, execution halts if the hashes do not match. In an embodiment, execution proceeds with execution of the second code if the hashes match. In an embodiment, the memory storing the boot program code is read only. In an embodiment, the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, and the second code comprises a master public key (MPK) and a decryption algorithm, the second code being arranged such that when executed by the CPU, the CPU calculates a hash of the third code, decrypts the signature to obtain the pre-calculated hash, compares the two hashes and proceeds if the hashes match. In an embodiment, the gaming machine comprises a further memory comprising a signature of one or more external BIOS hashes, and the third code is arranged such that the CPU verifies each external BIOS hash before transferring control to any of the one or more external BIOSes. In an embodiment, the third code is arranged such that the CPU verifies the active boot partition on the active boot device by generating a hash of the boot partition and comparing it to a hash stored on the active boot device before transferring control to the master boot record of the active boot partition. In a second aspect, the invention provides a method of protecting an electronic gaming machine comprising: storing boot program code comprising first code in a memory; and monitoring initiation of a boot process in which a central processing unit reads the first code from the memory by comparing the first code read by the CPU to validation code; and taking at least one protective action if the read first code does not match the validation code. In an embodiment the method comprises comparing the first code read by the CPU to the validation code. In an embodiment the method comprises comparing the first code to the validation code prior to the first code being read by the CPU. In an embodiment, the boot program code comprises second code and the first code comprises a pre-calculated hash of the second code, and the method comprises calculating a hash of the second code and comparing it to the pre-calculated hash and proceeding if the hashes match. In an embodiment, the boot program code comprises third code comprising a master private key signature of a pre-calculated hash of the third code, the second code comprises a master public key (MPK), and the method comprises calculating a hash of the third code, decrypting the signature to obtain the pre-calculated hash, comparing the two hashes and proceeding if the hashes match. In a third aspect, the invention provides an electronic gaming machine (EGM) comprising: a central processing unit (CPU); a memory storing boot program code; and a removable memory device in data communication with the CPU and storing authentication data comprising a public key, the CPU arranged to access the memory and initiate a boot process by reading the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory device. In an embodiment, the authentication data is a public key. In another embodiment, the authentication data is a certificate comprising the public key and identity data. In an embodiment, the at least one set of code comprises the code stored in a disk partition. In an embodiment, the at least one set of code comprises operating system code. In an embodiment, the at least one set of code comprises code of a program. In an embodiment, the CPU authenticates the at least one set of code by employing the authentication data to authenticate intermediate authentication data and employing the intermediate authentication data to authenticate the at least one set of code. In an embodiment, the EGM is arranged to authenticate the removable storage device prior to employing the authentication data. Persons skilled in the art will also appreciate that the first and third aspects may be combined. In an embodiment, the monitoring device may be employed to authenticate the removable storage device. In a fourth aspect, the invention provides a method of protecting an electronic gaming machine comprising: storing boot program code in a memory; storing authentication data in a removable memory; and initiating a boot process in which a central processing unit reads the boot program code from the memory, the boot process including authenticating at least one set of code to be executed by the EGM by retrieving and employing the authentication data from the removable memory device. Persons skilled in the art will appreciate that the first and second aspects of the invention may be combined with the third and fourth aspects. BRIEF DESCRIPTION OF THE INVENTION Exemplary embodiments of the invention will now be described in relation to the following drawings in which: FIG. 1 is a perspective view of a gaming machine; FIG. 2 is a schematic diagram of the main components of the gaming machine of a first embodiment that relate to implementation of a secure boot chain; FIGS. 3A and 3B show a flow chart of the secure boot chain in accordance with an embodiment of the present invention; FIG. 4 is a schematic diagram of the main components of a gaming machine of a second embodiment; FIG. 5 is a flow chart of a method of a second embodiment; FIG. 6 is a further schematic diagram of a gaming machine; and FIG. 7 is a memory diagram. The foregoing summary, as well as the following detailed description of certain embodiments of the present invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, certain embodiments are shown in the drawings. It should be understood, however, that the present invention is not limited to the arrangements and instrumentality shown in the attached drawings. DETAILED DESCRIPTION First Embodiment Referring to the drawings, there is shown in FIGS. 1 to 3, a first embodiment of an electronic gaming machine arranged to implement a secure boot chain during which a series of code portions are validated. A gaming machine 10 is illustrated in FIG. 1. The gaming machine 10 includes a console 12 having a display 14 on which is displayed representations of a game 16 that can be played by a player. A mid-trim 20 of the gaming machine 10 houses a bank of buttons 22 for enabling a player to interact with the gaming machine, in particular during game play. The mid-trim 20 also houses a credit input mechanism 24 which in this example includes a coin input chute 24A and a bill collector 24B. Other credit input mechanisms may also be employed, for example, a card reader for reading a smart card, debit card or credit card. A reading device may also be provided for the purpose of reading a player tracking device, for example as part of a loyalty program. The player tracking device may be in the form of a card, flash drive or any other portable storage medium capable of being read by the reading device. A top box 26 may carry artwork 28, including for example pay tables and details of bonus awards and other information or images relating to the game. Further artwork and/or information may be provided on a front panel 29 of the console 12. A coin tray 30 is mounted beneath the front panel 29 for dispensing cash payouts from the gaming machine 10. The display 14 shown in FIG. 2 is in the form of a video display unit, particularly a cathode ray tube screen device. Alternatively, the display 14 may be a liquid crystal display, plasma screen, any other suitable video display unit, or the visible portion of an electromechanical device. The top box 26 may also include a display, for example a video display unit, which may be of the same type as the display 14, or of a different type. As illustrated in FIGS. 2 and 3, the electronic gaming machine has a central processing unit (CPU) 210. Boot program code forms a BIOS and is stored in a read only memory 220. Logically the boot program code consists of first, second and third code referred to hereafter as a pre-boot-loader, a boot-loader and a BIOS-control-program. The different portion of code contains components for different security features. Specifically: the pre-boot-loader contains a SHA 1 hash of the boot-loader; the boot loader contains a DSA master public key; and the BIOS control program contains a DSA signature of the BIOS control program SHA 1 hash that is signed by the DSA master private key corresponding to the DSA master public key. As illustrated in respective FIG. 3, when the electronic gaming machine is reset, the CPU 210 of electronic gaming machine begins executing the first instruction of the pre-boot-loader stored in the BIOS 220. The monitoring device 230 snoops every read access to the pre-boot-loader to thereby monitor reading of the pre-boot-loader by the CPU 305. The monitoring device is implemented by a field programmable gateway and contains a duplicate copy of the pre-boot-loader monitors access to the BIOS 220 that provides validation code that can be used to determine that the pre-boot-loader is valid. The monitoring device verifies that the pre-boot-loader read out by the CPU matches 310 the validation copy of the pre-boot-loader stored in the monitoring device. If it does not match, the monitoring device halts operation in such a manner that this will ultimately cause the electronic gaming machine to fail booting 315. Thus, this ensures that the electronic gaming machine is running a valid, unmodified copy of the pre-boot-loader and hence that the code to check the validity of the boot-loader (as described in further detail below) is still present and will be executed by CPU 210. The pre-boot-loader then copies the boot loader to random access memory 270. The pre-boot-loader calculates a SHA 1 hash of the boot-loader copy that is held in RAM. The pre-boot-loader verifies that the calculated hash matches the pre-calculated hash that is stored in the pre-boot-loader is described above. If following calculation of the hash the boot-loader 320 it is determined at step 325 that there is no match 325, the boot sequence fails 330. If there is a match, execution is transferred to the boot loader copy in RAM. These set of steps ensure that the electronic gaming machine is running an unmodified copy of the boot-loader and that the code to check the validity of the BIOS-control-program is still present and will be executed. The boot-loader runs from RAM to eliminate the risk of removing the boot program stored in the BIOS socketed device between verification and execution. At step 335 the boot-loader calculates a hash of the BIOS control program and copies the BIOS control program to RAM. The boot-loader then retrieves a DSA signature from the BIOS-control-program and retrieves the DSA master public key from the boot-loader. The boot-loader decrypts the signature of the BIOS-control-program hash 340 and determines 345 whether the hashes match. If the hashes fail to match booting is failed 350. Otherwise the verification is successful and execution is transferred to the BIOS-control-program now stored in RAM. The BIOS-control-program then seeks to verify any external BIOS 240 by reference to a signed table of external BIOS hashes 250. The CPU 220 calculates a hash of each external BIOS 360. It decrypts the signed table of external BIOS hashes 250 using DSA and the DSA master public key contained in the boot-loader. Each external bios 240 is hashed and compared to the now decrypted stored hash 365. Any external BIOSES not matched are ignored at step 370. Otherwise control is transferred to the external BIOSes. These steps ensure the electronic gaming machine is running a BIOS control program that has been signed by a master private key. Next before the BIOS-control-program transfers control to the master boot record of the active boot partition on the active boot device 260 it verifies the active boot partition 375 by calculating a hash at the active boot partition and verifying the hash against the DSA signature stored on the active boot device using the DSA master key and DSA. If it does not match at step 380 the boot is failed at 385. Otherwise the process proceeds to load and execute the operating system at step 390. These steps ensure the electronic gaming machine is running an operating system and system software that had previously signed by the DSA master key. Persons skilled in the art will appreciate that the exact sequence of step may vary with a particular BIOS implementation but will in force that code passes a DSA signature verification step before it is executed. Persons skilled in the art will appreciate that there maybe variations on the above boot sequence. For example, while the above embodiment employs SHA 1 hashes and DSA signatures, other crypto graphic hashes and signatures maybe employed. For example SHA 1-HMAC or RSA or a mixture of techniques. Further, while we have described the use of RAM to avoid hot swapping cache memory could be used instead. There may also be some additional steps carried out before software is executed. For example, the signature of system and game software components may be checked by checking the entire disk partitions, directories or individual files. Such checks may be performed on demand, that is immediately prior to a component being loaded or in advance, that is prior to any components being accessed. Further in some instances it may be appropriate to check components with multiple signatures. This allows the loading of a component to be prevented if it has not be signed by all required parties which may include the manufacture of the gaming machine, a regulatory body or a third party developer. Further, certificates rooted in the master public key may be stored with the software components than the public keys. Herein the term “authentication data” is used to refer collectively to a public key, a certificate rooted in the public key, or other authentication data including a public key. Second Embodiment FIG. 4 shows a second embodiment where the boot loader acquires a public key from a removable storage device 410 such as an authenticated smart card. In the remainder of FIG. 4 the same numbering is used as in the first embodiment. As discussed above, the boot loader can be used to verify a signature of system and game software either individually or by verifying the partitions on which they are stored. Accordingly, the key (or alternatively a certificate rooted in the public key) is retrieved from the smart card and employed to verify the signatures of the programs or partitions. This allows the approximation of revocation of previously signed program by not producing any smart cards with the relevant matching public key. This can be used in order to revoke incorrectly signed software before it is released. Further, it allows control of the number of software images in active use. A person skilled in the art will appreciate that while it has been described above that the key stored on the smart card is used to verify signatures of programs/partitions it can equally be used to verify certificates of public keys that are in turn used to verify signatures of programs/partitions. In an embodiment, the credentials of the smart card are as established as earlier as possible in the boot sequence. For example by employing the monitoring device to determine whether the smart card is valid in a similar manner in relation to which the first code is processed above. Further, rather than relying on keys being encoded within the BIOS, in some implementations it may be desirable to retrieve a key or keys stored on the smart card to use in an earlier part of the boot sequence for example, to verify the external BIOSes. The process 500 is summarised in FIG. 5. Boot code is stored in memory 510 and authentication data is stored in a removable memory 520. The boot process is initiated 530 and authentication data is retrieved 540 from the removable storage device. The method then involves authenticating 550 at least one set of code with the authentication data. The key from the smart card is then trusted until the next boot. A person skilled in the art will appreciate that the removable storage device should be readily removable such as a smart card, USB token, or the like. Third Embodiment In a third embodiment an Application Specific Integrated Circuit (ASIC) is used instead of the FPGA of the first embodiment as the monitoring device. As in the first embodiment, a boot memory contains the software that is first executed by the CPU when it exits the reset state. Monitored memory (or hash checked memory) may also be used to store those parts of the software that access critical security functions. For example the ASIC may contain logic which can enable or disable access to cash payment mechanisms or auditing information. By putting the enabling switch in monitored memory it becomes possible to check the security and authentication of the machine software before enabling or disabling these features. The boot program is checked by monitoring the CPU address and data buses 611, as shown in FIG. 6. The ASIC 612, which monitors the buses 611 contains a copy (in internal ROM) of the data in a portion 614 of the boot EPROM 613. When each word of data is fetched from EPROM 613 by the CPU a compare function 616 of the ASIC 612 first checks the address to see if it is within that area duplicated in the internal ROM 617, and if it is it then checks the data word that the CPU 615 is reading from the EPROM 613 against the appropriate word in the internal ROM 617. If the data is the same then the CPU 615 is using the correct data from EPROM 613, but if it is different then there is either an accidental error or deliberate tampering. In this event the ASIC 612 takes appropriate action which may include resetting the board and/or stopping other operations of the ASIC 612 internally. In the an embodiment, the CPU address and data bus 611 are multiplexed together to reduce the number of pins used. Non-multiplexed buses may also be used. The ASIC 612 may also contain logic to ensure that all memory locations in the monitored memory are checked. If all locations within the monitored area are not checked when an inappropriate access is made outside the monitored area the check fails and the board locks up. An inappropriate access is an instruction fetch or write cycle. Read cycles are allowed, to enable the software in the monitored region to check other parts of memory. Two implementations of this are: 1. The address bus 611 is monitored and a register is used to store a scanned address value location. Whenever the address from the CPU matches the value in this register the register is incremented. The memory check is complete when the address register reaches the end of the monitored memory. 2. A signature of address accesses may be implemented. Each address is combined in some form with the previous addresses to generate a fixed pattern. If the sequence of addresses is not the same as the original stored pattern then the check fails. For example each address may be combined using a CRC algorithm with the previous address's although preferably a more secure algorithm would be used. Other implementations of monitored memory are possible: 1. Instead of checking the program as it is executed, the ASIC disables the EPROM and substitutes data to the CPU from its internal ROM. The ASIC thus acts as a memory device. 2. The ASIC reads the contents of the monitored EPROM area before the CPU exits the reset state and generates a cryptographic hash of the data. Only if this hash matches a predefined value is the test passed. 3. Instead of checking the data as it is read from EPROM the ASIC reads the EPROM contents and verifies it before allowing the CPU out of the reset state. 4. In a variation of the above two implementations, the ASIC allows the CPU to fetch the first word of a program after exiting reset, but inserts into this read cycle the verification reads from EPROM. It is more difficult to tamper with this method as the cycles are not separated clearly. To provide further protection the monitored boot area may be read and monitored at a later time after the test has passed and game software is running. This provides protection against some forms of tampering where tampered memory is substituted for the original memory after the test passes. This scheme is most effective with as much functionality of the board as possible implemented in the ASIC. One method of tampering is to replace the entire ASIC, but if significant other functionality is included it becomes a serious technical problem to redesign the ASIC. Additionally the more critical the ASIC is to the functioning of the board then the more difficult it is to get the board working again if the monitoring circuit disables the operation of the ASIC internally. If the monitored memory test fails, the board and ASIC are typically reset to protect the gaming machine. Alternately program execution is allowed to continue but certain features of the ASIC are disabled, preventing the board from being used in its full capacity. This allows the software to display appropriate errors messages (especially in the case of accidental memory errors), but effectively stops tampering having any real consequence. In the case of gaming machines, certain critical functions will also be inhibited such as software access to hardware meters 641, and inhibiting input and output of credit or the like, such as by way of the credit card reader 642 or ticket reader/writer 643. The internal ROM of the ASIC is expected to be small compared to the size of the boot EPROM to reduce cost, although it could be the same size. Alternately, and as described above, the cryptographic hash check may be embedded in the ASIC. The size of the EPROM to be securely checked can be increased to the total size of the memory in the system without increasing the size of the ASIC internal ROM by embedding a checking program in the area of EPROM that is checked by the ASIC. The checking program generates a cryptographic hash over the entire memory area to be checked (which may include the area monitored by the ASIC) and compares it to a pre-computed value. If it matches then the entire region is assumed to be unmodified. The method relies on it being difficult to tamper with the data which is included in the hashed area while retaining the same hash value and that the ASIC monitors the program which generates and checks the hash. An advantage of this method is that the hash checking program is relatively small, and can be expected to be smaller than a comparable signature checking program. Therefore the size of the ROM in the ASIC may be reduced in size with this method. A non-cryptographic checking algorithm may be used instead of the hash function, but algorithms such as checksum or CRC are relatively easy to tamper with and are not preferred. The data to be checked, either directly by the ASIC or included in the hash-checked region, may include program or data. The data may include text messages such as “(© Aristocrat Leisure Industries” or “This software is authorized by Aristocrat Leisure Industries”. Once the initial part of the boot memory has been authorized it can then securely check the rest of the memory in the system. The monitored memory area may use a hash mechanism to check more memory as described in the previous section or it may implement a digital signature check. The advantage with a digital signature check is in minimizing the amount of boot code that can never be changed without changing the ASIC. The advantage of a hash check is that a hash is simpler and therefore requires less program space for monitored memory than digital signature software. Digital signatures are also used to authorize all other modules of software and data in the system, including system software and games. Each authorized EPROM or file has an associated digital signature which is checked. If invalid signatures are found the data will not be used and appropriate action will be taken, such as the machine locking up and displaying a message. FIG. 7 shows a schematic of a memory map in which a first section of the memory space 721 is checked by the ASIC 612, a second part of the memory space 722 is checked by a hashed code and a third part of the memory space 623 is checked by digital signature. The memory space checked by the checking software may include or exclude the area in which the checking software resides. In the example illustrated in FIG. 7 the signature checked memory space 723 does not encompass the memory space 721 containing the checking software (i.e. the space monitored by the ASIC) but the hash checked memory space 722 does encompass the memory space 721. In an embodiment, continuous monitoring of the authenticity of software provides extra security. The memory contents are periodically rechecked to ensure that changes have not occurred. Continuous monitoring requires a method of getting the CPU to start executing software within the monitored (or alternately hash checked, although this is not as secure) memory area. Once the CPU starts executing software within this secure area it can again perform authorization checks of the system as required. A watchdog type monitor is implemented in the ASIC which must be accessed periodically from software executing within the secured memory area otherwise the ASIC will force the system to shutdown. This transfer to secure area may be simply by software jumping to an address periodically or caused by an interrupt from the ASIC. The ASIC is able to detect that software is executing from the monitored area. The method used depends on the processor implementation. For processors which support identification of external bus cycles an instruction fetch from a predefined address is used. For processors without identification of bus cycles and also without internal cache memory a sequence of memory accesses is detected that may only be generated by software executing within the monitored area. For CPU without bus cycle identification and also with cache it may not be possible to guarantee detection of monitored area software execution. Tampering could take place by execution of software within the cache so that external cycles appeared to be the correct software accesses. An alternate method of guaranteeing execution within monitored memory is to periodically reset the CPU. In this implementation the CPU is able to be reset separately from the rest of the system. Prior to being reset, the CPU saves it's operational state in memory for restoration after the authentication checks have been completed. After the ASIC has reset the CPU then the CPU must be executing from monitored memory. A flag in the ASIC indicates the cause of the reset so the CPU knows whether to execute cold start reset code or continuous monitoring code. While the CPU is in the reset state the ASIC checks the state of the relevant pins to ensure that the CPU actually has been reset. In the preferred implementation the ASIC contains a timer which is initialized after each reset and which locks up the board when it reaches a predefined count. The timer would require that the CPU be reset every five minutes for example. Periodically and at least less than every 5 minutes the system software saves the system state and instructs the ASIC to reset the CPU and also timer. The system software can choose a point in it's operation where a slight delay while the CPU resets is not noticeable. Alternately the ASIC generates an interrupt periodically which the system software responds to by saving the CPU state and then the CPU resets. These authentication checks are as described in the rest of the document. The authentication check can be divided into a number of these execution periods to divide the CPU loading over time. In this case the check software may need to store information between the periods (such as the last memory location checked). Although this data may be stored in RAM, it is accessible by any software running on the machine and could be tampered with. Preferably the ASIC implements some RAM that is only accessible by software running within the monitored memory area. One possible method of tampering is to find start execution code within the monitored area, which was not intended as a start address for the routine and which has side effects unintended by the system programmers. This side effect would access the flag in the ASIC without running the security check. One method of preventing this is to implement an address signature check as described for “ASIC Monitored Memory”. A significant section of code must be executed correctly for the signature to be correct and it must be from the correct address. Many other methods are possible. One method of tampering with the system is to allow the correct boot code to be executed after reset and during authentication, then at an appropriate point map into the program memory a new section of code (e.g. in hardware swap EPROMS with a multiplexer circuit). This memory may be automatically mapped in an out of memory space depending on where program execution is being performed. The authentication check reads the original data and passes, but when control is passed elsewhere a different program is executed. To prevent this attack, at a random time the ASIC reads from the CPU data bus the instruction fetched from memory, and stores it in a register together with the address from which it was read. When the periodic authentication check is performed it reads these registers and compares them with the data it reads from the same location. If the data is different then tampering has taken place. This test will eventually, at a random time, detect tampering. To speed up this test more than one data location may be sampled. Because it may take some time before tampering is detected it is preferable that when tampering is detected this information is stored so that the machine cannot be used until this condition is acknowledged by the operator and fixed. It should be stored in non-volatile memory, and preferably non-erasable memory. True random number generation is not usually feasible in an ASIC and instead pseudo-random numbers are typically used instead. The pseudo-random number may be randomized further by combining it with some external information, such as the contents of the data or address bus. An alternate method is to use DMA or bus mastering by the ASIC to automatically read the contents of memory and verify the data. This method is most suitable for the boot code, as the complexity of the design for more equivalent functionality to that easily achieved in secure software to very high—although it is possible. These methods allow the verification of programs and data in boot memory and which is not possible to tamper with by simply changing the program memory. An advantage of these security systems is that non-volatile re-writable memory can be used to hold the boot program. Even if tampered code were somehow loaded into memory the security mechanisms would prevent it being executed. An advantage of Application Specific Integrated Circuit (ASIC) monitored memory and hash checked memory security mechanisms is that relatively simple logic is required in the ASIC and the rest of the security mechanism is in software. If the entire mechanism were placed in the ASIC it would be far more complex, costly, less flexible and take longer to design. Fourth Embodiment The above methods may also be supplemented by a further method that involves embedding into the authorized software a message which makes a legal statement about that software and it's ownership or authorization. Such a statement might include a text message such as “This Software Is Authorized By Aristocrat Leisure Industries” or “C Aristocrat Leisure Industries”. The authentication hardware or software expects that the message be embedded in the program/data it is authenticating. If the message is not present in the appropriate place the authentication test fails and the data/program is not used. Unlike digital signatures this method is technically easy to cheat, by embedding the message, but provides legal recourse to the manufacturer if it is detected. Digital signatures are technically difficult but potentially legally weak. The two methods may be combined to provide both legal and technical security. Referring to FIG. 6, components of a gaming machine are shown. After the secure boot routines held in the EPROM 613 have been verified as discussed below, these routines can be used to load programs from a mass storage system 631 such as a hard disk drive 633 and controller/interface 632. Other mass storage systems can also be used such as a CD or DVD ROM drive, a floppy disk drive or ZIP™ drive. The mass storage system 631 may be local to the CPU and read via the buses 611, or may be remote and data sent to a writable memory local to the CPU over a network. The program will be loaded from the mass storage device into RAM by a loader program, which is preferably held in EPROM 613, but could also be held in a ROM associated with a logic circuit such as the ROM 617 of the Application Specific Integrated Circuit (ASIC) 612. In alternative embodiments, the ASIC 612 may be replaced by a Field Programmable Gate Array (FPGA). As the program is read from the mass storage device 631, the loaded code is scanned for a predetermined text string embedded in the code such as “© Aristocrat Leisure Industries”. The scanning may either be performed in software by a routine in the loader program, or alternatively the ASIC 612 may be programmed to scan the data flowing over the buses 611 and locate the text string. In another embodiment, a hard wired scanning circuit can be connected to the busses 611 to scan for the string. This method of verification may be used instead of a hash code or encrypted signature, but in the preferred embodiment is used as well as an encrypted signature or hash code verification method. Once the loaded program has been verified, the embedded text string will be displayed on a display device 634 such as the video display screen of a gaming machine on which the program is running, such that visual confirmation of the validation is provided. This display function is performed by the loaded program thereby also enabling detection of fraudulent use of software on other manufacturers hardware. The loaded program also performs internal consistency checks to prevent alteration or deletion of the text string. Fifth Embodiment The Multigame authorization system allows games to be used only on the system for which they are authorized. The System program confirms the authorization of the game before it is allowed to be used. Preferably game authorization comprises one or more of the following steps: The header section of the game memory is checked to confirm that it is an appropriate game (e.g. not another system EPROM incorrectly used, has valid version numbers, etc). The game header is checked for the legal authorization message. The game header checksum or CRC is checked to ensure memory integrity. If the games are digitally signed, then the digital signature(s) are validated. The authorization of the game to run on this particular gaming machine is checked. If the authorization fails the gaming machine may either continue without allowing that game to be used, stop and ask the operator to remove the game from the machine, or run that game only in demonstration mode. Preferably each gaming machine contains a unique identification number which the CPU can read and use as part of the authorization code. This can be implemented using a Dallas Semiconductor serial identification chip (e.g. DS2401). If the authorization fails games may run in a limited mode and display an appropriate message on the screen. The limited mode may prevent the machine accepting or paying out money or updating critical auditing information. Sixth Embodiment An EPROM authorization message is created by applying a digital signature to a message composed of the unique Game Identifier, a unique Gaming Machine identifier and any usage restrictions that may be required (e.g. date restriction on game operation). The signature is generated in a secure environment and sent to the gaming machine where it is stored in non-volatile memory for later use. The secure environment may be: Within a smartcard. A service technician or operator may authorize the game to run on the machine by connecting the smartcard to the machine where the game is installed. To limit accidental or deliberate fraud the smartcard preferably contains a limit on the number of games that can be authorized. The smartcard may be inserted into a special purpose interface on the gaming machine, a general purpose interface such as is used for player marketing cards or via a PC and communication interface (e.g. RS232 or Ethernet) with a smartcard reader. The gaming machine supplier may generate the authorization key and supply it to the service technician/operator for entry into the gaming machine. The authorizations may be encoded into a removable EEPROM chip which is supplied to the operator with the new games. Persons skilled in the art will appreciate that various of the above embodiments may be combined with other embodiments or modified to incorporate features of other embodiments. These and other variations will be apparent to persons skilled in the art and should be considered as falling within the invention described herein.	G	60G06	161G06F	21	00
11882514	US20090037973A1-20090205	Policy-enabled aggregation of IM User communities	ACCEPTED	20090122	20090205	[]	G06F2100	["G06F2100"]	8266671	20070802	20120911	726	001000	81891.0	ARMOUCHE	HADI	[{"inventor_name_last": "Gustave", "inventor_name_first": "Christophe", "inventor_city": "Ottawa", "inventor_state": "", "inventor_country": "CA"}, {"inventor_name_last": "McFarlane", "inventor_name_first": "Brad", "inventor_city": "Ottawa", "inventor_state": "", "inventor_country": "CA"}, {"inventor_name_last": "Chow", "inventor_name_first": "Stanley TaiHai", "inventor_city": "Ottawa", "inventor_state": "", "inventor_country": "CA"}]	A method of automatically aggregating an online user community, and graphical user interface for same, the method including one or more of the following: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the service provider applying the aggregation policy to an other user; determining whether the other user fits the aggregation policy; adding the other user to the online user community; the user defining an anti-aggregation policy; the service provider retrieving the anti-aggregation policy; determining whether the other user fits the anti-aggregation policy; and removing the other user from the online user community when the other user fits the anti-aggregation policy.	1. A method of automatically aggregating an online user community, comprising: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the service provider applying the aggregation policy to an other user; determining whether the other user fits the aggregation policy; adding the other user to the online user community; the user defining an anti-aggregation policy; the service provider retrieving the anti-aggregation policy; determining whether the other user fits the anti-aggregation policy; and removing the other user from the online user community when the other user fits the anti-aggregation policy. 2. The method of automatically aggregating an online user community, according to claim 1, further comprising the user triggering aggregation for the online user community. 3. The method of automatically aggregating an online user community, according to claim 1, further comprising the service provider sending an add request to the other user. 4. The method of automatically aggregating an online user community, according to claim 3, further comprising the other user accepting the add request. 5. The method of automatically aggregating an online user community, according to claim 1, further comprising determining that an additional other user exists and repeating the service provider applying the aggregation policy to the additional other user. 6. The method of automatically aggregating an online user community, according to claim 1, wherein defining the aggregation policy includes defining a criteria selected from the list consisting of one or more interests of the user, a physical location of the user, a gender of the user, and an age of the user. 7. The method of automatically aggregating an online user community, according to claim 1, further comprising the user creating a plurality of online communities, wherein the user has a unified view of all of the plurality of online communities. 8. The method of automatically aggregating an online user community, according to claim 1, further comprising the user creating a plurality of online communities, and the service provider providing the user and automated view of the plurality of online communities. 9. The method of automatically aggregating an online user community, according to claim 1, wherein a membership of the online community is determined transparently from a peer perspective. 10. The method of automatically aggregating an online user community, according to claim 1, wherein private information about the user is not available to the other user and private information about the other user is not available to the user. 11. The method of automatically aggregating an online user community, according to claim 1, further comprising communicating through a communication network. 12. The method of automatically aggregating an online user community, according to claim 11, wherein the communication network is the Internet. 13. The method of automatically aggregating an online user community, according to claim 11, wherein the communication network is an instant messaging network. 14. The method of automatically aggregating an online user community, according to claim 1, wherein an identity of the user and an identity of the other user correspond to an e-mail address of the user and an e-mail address of the other user. 15. The method of automatically aggregating an online user community, according to claim 1, further comprising determining whether a pre-determined maximum capacity of the online community has been reached. 16. A graphical user interface for an online user community, comprising: a list of a user's online user communities, wherein each of the user's online user communities lists other users that are members of each of the user's online user communities; and a list of an other user's other communities consisting of the user's online user communities. 17. The graphical user interface, according to claim 16, wherein a service provider initiates a delete request to users in the other communities whose aggregation policy no longer matches a profile of the user when the user modifies the profile. 18. The graphical user interface, according to claim 16, wherein a service provider initiates an add request to communities having an aggregation policy that matches a profile of the user when the user modifies the profile. 19. The graphical user interface, according to claim 16, wherein a service provider initiates a delete request to users in the list of the user's online communities when a profile of the user is deleted. 20. The graphical user interface, according to claim 16, wherein a service provider initiates a delete request to users in the other communities when a profile of the user is deleted.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention This invention relates generally to policy enabled aggregation of user communities. 2. Description of Related Art Communication service providers enable communication between pluralities of users in many different ways. An example of communications enabled between the plurality of users by a service provider is instant messaging (IM). Often, the users of communication services desire to be aggregated into communities. The desire of users to be aggregated in communities exists for many reasons. Thus, there is a need for a social networking service with a robust approach to the formation of user communities. The foregoing objects and advantages of the invention are illustrative of those that can be achieved by the various exemplary embodiments and are not intended to be exhaustive or limiting of the possible advantages which can be realized. Thus, these and other objects and advantages of the various exemplary embodiments will be apparent from the description herein or can be learned from practicing the various exemplary embodiments, both as embodied herein or as modified in view of any variation which may be apparent to those skilled in the art. Accordingly, the present invention resides in the novel methods, arrangements, combinations and improvements herein shown and described in various exemplary embodiments.	<SOH> SUMMARY OF THE INVENTION <EOH>In light of the present need for policy enabled aggregation of user communities, a brief summary of various exemplary embodiments is presented. Some simplifications and omission may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit its scope. Detailed descriptions of a preferred exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the invention concepts will follow in later sections. Various exemplary embodiments are a method of automatically aggregating an online user community, including one or more of the following: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the service provider applying the aggregation policy to an other user; determining whether the other user fits the aggregation policy; adding the other user to the online user community; the user defining an anti-aggregation policy; the service provider retrieving the anti-aggregation policy; determining whether the other user fits the anti-aggregation policy; and removing the other user from the online user community when the other user fits the anti-aggregation policy. Various exemplary embodiments include one or more of the following: the user triggering aggregation for the online user community; the service provider sending an add request to the other user; the other user accepting the add request; determining that an additional other user exists and repeating the service provider applying the aggregation policy to the additional other user; defining the aggregation policy includes defining a criteria selected from the list consisting of one or more interests of the user, a physical location of the user, a gender of the user, and an age of the user; the user creating a plurality of online communities, wherein the user has a unified view of all of the plurality of online communities; the user creating a plurality of online communities, and the service provider providing the user and automated view of the plurality of online communities; a membership of the online community is determined transparently from a peer perspective; private information about the user is not available to the other user and private information about the other user is not available to the user; communicating through a communication network, such as, for example, the Internet, including, for example, an instant messaging network; an identity of the user and an identity of the other user correspond to an e-mail address of the user and an e-mail address of the other user; and determining whether a pre-determined maximum capacity of the online community has been reached. Various exemplary embodiments are a graphical user interface for an online user community, including a list of a user's online user communities, wherein each of the user's online user communities lists other users that are members of each of the user's online user communities, and a list of an other user's other communities consisting of the user's online user communities. In various exemplary embodiments, a service provider initiates a delete request to users in the other communities whose aggregation policy no longer matches a profile of the user when the user modifies the profile. In various exemplary embodiments, a service provider initiates an add request to communities having an aggregation policy that matches a profile of the user when the user modifies the profile. In various exemplary embodiments, a service provider initiates a delete request to users in the list of the user's online communities when a profile of the user is deleted. In various exemplary embodiments, a service provider initiates a delete request to users in the other communities when a profile of the user is deleted.	BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to policy enabled aggregation of user communities. 2. Description of Related Art Communication service providers enable communication between pluralities of users in many different ways. An example of communications enabled between the plurality of users by a service provider is instant messaging (IM). Often, the users of communication services desire to be aggregated into communities. The desire of users to be aggregated in communities exists for many reasons. Thus, there is a need for a social networking service with a robust approach to the formation of user communities. The foregoing objects and advantages of the invention are illustrative of those that can be achieved by the various exemplary embodiments and are not intended to be exhaustive or limiting of the possible advantages which can be realized. Thus, these and other objects and advantages of the various exemplary embodiments will be apparent from the description herein or can be learned from practicing the various exemplary embodiments, both as embodied herein or as modified in view of any variation which may be apparent to those skilled in the art. Accordingly, the present invention resides in the novel methods, arrangements, combinations and improvements herein shown and described in various exemplary embodiments. SUMMARY OF THE INVENTION In light of the present need for policy enabled aggregation of user communities, a brief summary of various exemplary embodiments is presented. Some simplifications and omission may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit its scope. Detailed descriptions of a preferred exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the invention concepts will follow in later sections. Various exemplary embodiments are a method of automatically aggregating an online user community, including one or more of the following: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the service provider applying the aggregation policy to an other user; determining whether the other user fits the aggregation policy; adding the other user to the online user community; the user defining an anti-aggregation policy; the service provider retrieving the anti-aggregation policy; determining whether the other user fits the anti-aggregation policy; and removing the other user from the online user community when the other user fits the anti-aggregation policy. Various exemplary embodiments include one or more of the following: the user triggering aggregation for the online user community; the service provider sending an add request to the other user; the other user accepting the add request; determining that an additional other user exists and repeating the service provider applying the aggregation policy to the additional other user; defining the aggregation policy includes defining a criteria selected from the list consisting of one or more interests of the user, a physical location of the user, a gender of the user, and an age of the user; the user creating a plurality of online communities, wherein the user has a unified view of all of the plurality of online communities; the user creating a plurality of online communities, and the service provider providing the user and automated view of the plurality of online communities; a membership of the online community is determined transparently from a peer perspective; private information about the user is not available to the other user and private information about the other user is not available to the user; communicating through a communication network, such as, for example, the Internet, including, for example, an instant messaging network; an identity of the user and an identity of the other user correspond to an e-mail address of the user and an e-mail address of the other user; and determining whether a pre-determined maximum capacity of the online community has been reached. Various exemplary embodiments are a graphical user interface for an online user community, including a list of a user's online user communities, wherein each of the user's online user communities lists other users that are members of each of the user's online user communities, and a list of an other user's other communities consisting of the user's online user communities. In various exemplary embodiments, a service provider initiates a delete request to users in the other communities whose aggregation policy no longer matches a profile of the user when the user modifies the profile. In various exemplary embodiments, a service provider initiates an add request to communities having an aggregation policy that matches a profile of the user when the user modifies the profile. In various exemplary embodiments, a service provider initiates a delete request to users in the list of the user's online communities when a profile of the user is deleted. In various exemplary embodiments, a service provider initiates a delete request to users in the other communities when a profile of the user is deleted. BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand various exemplary embodiments, reference is made to the accompanying drawings, wherein: FIG. 1 is a schematic diagram of an exemplary system for policy enabled aggregation of user communities; FIG. 2 is a flowchart of an exemplary embodiment of a method for policy enabled aggregation of user communities; FIG. 3 is a schematic diagram of a first exemplary embodiment of a graphical user interface for policy enabled aggregation of user communities; and FIG. 4 is a schematic diagram of a second exemplary embodiment of a graphical user interface for policy enabled aggregation of user communities. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION On a networking website, a user may expand a social network by adding to his “buddies list” other subscribed users with whom the particular user has one or more common interests. When a user successfully adds another user into his buddies list, his social network expands to the buddies list of the added user. In a reciprocal fashion, the buddies list of the added user also expands to include buddies on the list of the initial user. However, in order to have access to communities, such as the communities described above, specific to a web service, a user often must create an account. Likewise, each time a user wants to have access, often the user must login via a web browser to an established account. Often, this requires abiding by the specifics of applicable web portal rules. Further, in various exemplary embodiments, a user manually searches based on the users own criteria, and manually adds new users to his buddies list matching the user's interest. According to the embodiments described above, subscribing and subsequentially accessing a plethora of social networks is cumbersome for a user. This is particularly true if the user desires to have access on a regularly basis to the plurality of communities. A problem with such embodiments is that the compartmentalization into various web portals fails to permit a user to have a unified view of all of his communities. Some instant messaging tools provide a means to build contact lists by selecting a user that is already known from the user's address book or by answering directly a user's IM handle through the IM graphical user interface (GUI). Unfortunately, in such embodiments, it is not possible for users to have an automated access to other users based on shared common interests or more generally based upon a specific user-defined user attribute. In other embodiments directed to provide an automated means for users to be matched with one another for a general network application, the existing base of user profiles and the ubiquity of client applications are not taken advantage of to provide an automated and unified view of user-defined communities. Other embodiments are related to providing a trust mechanism for peer-to-peer entities. Thus, in various exemplary embodiments, trust is determined based on a peers group interest. In this manner, social interaction of a network of peers is tied to trust. In other words, various exemplary embodiments pertain to determining peer interest for building community of users into IM application space, for building a network of trust, or both. Various exemplary embodiments pertain to a method, in a peer-to-peer environment, to associate peer entities with groups, providing peer group creation binding and discovery capabilities. Such embodiments include a process to determine whether a peer entity is qualified to be a member of a peer group. However, it is believed to be advantageous for groups to be owned by peer entities and for membership to be determined automatically and transparently from a peer perspective. Thus, various exemplary embodiments incorporate this capability. Various exemplary embodiments make use of a social website where a user browses among a set of users based on specific attributes. Some embodiments subsequentially enable a seamless integration of matched users into the buddies list of the user making a search. Unfortunately, such embodiments fail to overcome a requirement that a user manually search and an additional and unrelated requirement that limit the list of users from which to select to the users known to a specific social networking website. Thus, there is a need for embodiments that overcome these disadvantages. Various exemplary embodiments enable an IM user to determine an affinity level associated with another user part of users already known from his contact list. However, such embodiments fail to permit an automatic federation of otherwise unknown IM users into a particular user's contact list on a per-interest or aggregation policy basis for the given user. Thus, various exemplary embodiments provide the foregoing advantages. In view of the foregoing, a need exist for online users to share access to communities of users in a unified and automated manner. Likewise, a need exist for a simple and consistent interface that enables users to build their own user communities of interest without giving away a level of privacy required for the user. Accordingly, various exemplary embodiments enable a unified and automated access and management of online communities of users through IM systems. Referring now to the drawings, in which like numerals refer to like components or steps, there are disclosed broad aspects of various exemplary embodiments. FIG. 1 is a schematic diagram of an exemplary system 100 for policy enabled aggregation of user communities. The system 100 includes the service provider 102, a communications network 104, a user 106 and other users 108, 109, 110, 111. In various exemplary embodiments, the service provider 102 is an IM service provider that enables IM communications between the user 106 and the other users 108, 109, 110, 111 through the communications network 104. Various exemplary embodiments provide a means for automatically selecting a set of IM users and aggregating the set of IM users into a community of users that share one or more common characteristics. In various exemplary embodiments, the shared common characteristics are defined by a policy that can be customized such as an aggregation policy specified by the user 106. This will be discussed in greater detail below. Various exemplary embodiments are intended to satisfy a need of the users 106, 108, 109, 110, 111 to more easily share and access online communities of users. The popularity of social networking sites indicates that a growing number of users 106, 108, 109, 110, 111 desire to access diversified groups or communities of online users 106, 108, 109, 110, 111. Thus, in various exemplary embodiments, the communication network 104 is the Internet. Accordingly, various exemplary embodiments leverage an established based of IM infrastructures to enable a unified way for a user to build, and subsequentially seamlessly access, one or more online communities of users. Various exemplary embodiments may be implemented in connection with any existing, or later known, IM or other service provider 102. In various exemplary embodiments, the subject matter described herein is implemented in a unified IM service gateway. Accordingly, in various exemplary embodiments, the subject matter described herein is available to any IM subscriber federated by a unified IM service gateway. In various exemplary embodiments, communities of users 106, 108, 109, 110, 111 are built and automatically updated based on specific characteristics defined by each user. In various exemplary embodiments, the privacy associated with a user is administered according to a user-defined policy. Thus, in various exemplary embodiments, a user's access is restricted to only users matching specific characteristics defined by the user. In various exemplary embodiments, a profile is associated with each user 106, 108, 109, 110, 111. In various exemplary embodiments, the profile associated with each user records information such as the user's interests, physical location and demographic information such as gender, age and so on. In various exemplary embodiments, when a user desires to create a new community of users, the user specifies an aggregation policy that defines one or more characteristics of other users to be added to the group of users being created. Examples of characteristics used to define an aggregation policy include, but are not limited to, physical location of the user, interests of the user, basic profile information of the user, and so on. Similarly, in various exemplary embodiments, an aggregation policy is defined using one or more sets of characteristics previously defined by the user, or one or more sets of characteristics provided to the user 106 by the service provider 102. In various exemplary embodiments, policy checking is performed through a regular expression pattern matching that is applied to corresponding fields into a respective user profile. Thus, in various exemplary embodiments, a threshold value specifies a maximum number of users to be added to a community. Such embodiments define a limit on the number of users that can be aggregated in a community. In other exemplary embodiments profiles are evaluated in different ways. Accordingly, various exemplary embodiments assign “point” values for one or more criteria and matching/inclusion is based on cumulative point counts and thresholds and/or ranges. In various exemplary embodiments, the subject matter described herein is implemented by the service provider 102 as a global policy mechanism restricting a number of aggregated entities for a given group. Thus, various exemplary embodiments prevent an excessive workload for a server of the service provider 102. This prevents the service provider 102 from being required to handle more attempts by users 106, 108, 109, 110, 111 to create or add to a community at a particular time. In various exemplary embodiments, a policy allows the user 106 to specify whether the user 106 needs to explicitly approve each request by one or more of the other users 108, 109, 110, 111 to add the user 106 to one or more communities of the other users 108, 109, 110, 111. In various exemplary embodiments, the user 106 has the option to disable subject matter described herein according to other exemplary embodiments. Thus, in various exemplary embodiments, the user 106 is able to preserve his privacy fully and completely such that the user 106 is not impacted by mechanisms enabling aggregation of communities of users according to other exemplary embodiments described herein. Still further, various exemplary embodiments enable the user 106 to define specific anti-aggregation policies that enable the user 106 to specify which other users 108, 109, 110, 111 are permitted, or are not permitted, to aggregate the user 106 into their respective community groups. Likewise, various exemplary embodiments enable the user 106 to specify whether the user 106 needs to explicitly approve add requests in order to be added into a community of one or more of the other users 108, 109, 110, 111. In various exemplary embodiments, an anti-aggregation policy of the user 106 is specified in the same manner as the user 106 specifies an aggregation policy. In various exemplary embodiments, policy checking is performed by way of a pattern matching expression that is applied to one or more specific fields associated with a profile of the user 106 when the user 106 initiates a request to add an aggregation of other users 108, 109, 110, 111. The following is an example of a policy aggregation associated with a user-defined community according to one exemplary embodiment. The user 106 specifies an aggregation of other users 108, 109, 110, 111 that are located in Ottawa or Paris, are interested in soccer, and work for Alcatel. Such an aggregation request gathers other users 108, 109, 110, 111 who share an employer in common with the user 106, an interest in common with the user 106, and one of two geographical locations. FIG. 2 is a flowchart of an exemplary embodiment of a method 200 for policy enabled aggregation of user communities. The method 200 begins in step 202 and then continues to step 204. In step 204, the user 106 creates a community. Next, in step 206, the user 106 defines an aggregation policy for the community. In step 207, the user 106 defines an anti-aggregation policy. This is discussed in greater detail both above and below. Various exemplary embodiments do not include step 207. In various exemplary embodiments, step 208 is included wherein the user 106 triggers aggregation for the community. In other exemplary embodiments, aggregation for the community is automatically triggered by the service provider 102. In step 210, the service provider 102 retrieves the aggregation policy defined by the user 106 in step 206. Then, in step 212, the service provider 102 applies the aggregation policy to one of the other users 108, 109, 110, 111. The method 200 then proceeds to step 214 where a determination is made whether one of the other users 108, 109, 110, 111 fits the aggregation policy applied by the service provider 102 in step 212. If a determination is made in step 214 that one of the other users 108, 109, 110, 111 does fit the aggregation policy applied by the service provider 102 in step 212, then the method 200 proceeds to step 216. In step 216, an add request is sent to one of the other users 108, 109, 110, 111 by the service provider 102. The method 200 then proceeds to step 218 where a determination is made whether the one of the other users 108, 109, 110, 111 accepts the add request sent in step 216. When a determination is made in step 218 that the one of the other users 108, 109, 110, 111 accepts the add request, then the method 200 proceeds to step 220 where the one of the other users 108, 109, 110, 111 is added to the community created by the user 106 in step 204. In various exemplary embodiments, the other users 108, 109, 110, 111 define that they will accept all add requests automatically. Similarly, in various exemplary embodiments, the service provider 102 structures the method 200 such that the other users 108, 109, 110, 111 are automatically added to the community in step 220 after a determination is made in step 214 that the other user fits the aggregation policy defined by the user 106 in step 206. In other words, various exemplary embodiments omit both step 216 and step 218. Following step 220, the method 200 proceeds to step 222. In step 222, an anti-aggregation policy of the user 106, if any, is retrieved. Obviously, if the user 106 has not defined an anti-aggregation policy, then the method 200 does not include step 222. After retrieving an anti-aggregation policy in step 222, the method 200 proceeds to step 224. In step 224, a determination is made whether the other user 108, 109, 110, 111 added to the community in step 222 fits the anti-aggregation policy of the user 106. If a determination is made in step 224 that the other user 108, 109, 110, 111 does fit an anti-aggregation policy of the user 106, then the method 200 proceeds to step 226 where the other users 108, 109, 110, 111 is removed from the community of the user 106. The method 200 then proceeds to step 228 where a determination is made whether any additional ones of the other users 108, 109, 110, 111 exists for which steps 212 through 226 have not yet been applied. Likewise, if a determination is made in step 224 that the other user 108, 109, 110, 111 does not fit an anti-aggregation policy defined by the user 106, then the method 200 proceeds to step 228. Similarly, if a determination is made in step 218 that the other user 108, 109, 110, 111 does not accept an add request, then the method 200 proceeds to step 228. Also, when a determination is made in step 214 that the other user 108, 109, 110, 111 does not fit the aggregation policy applied by the service provider 102 in step 212, then the method 200 proceeds to step 228. If a determination is made in step 228 that additional ones of the other users 108, 109, 110, 111 exist for which steps 212 through 226 have not been performed, then the method 200 returns to step 212. Alternatively, when a determination is made in step 228 that all other users 108, 109, 110, 111 have been evaluated by steps 212 through 226, then the method 200 proceeds to step 230 where the method 200 ends. According to the foregoing, various exemplary embodiments eliminate a requirement that the user 106 manually create a community of users, such as by subscribing to one or more networking websites, selecting users from a user base of a networking website, and adding the selected users to the new community. The subject matter described above in connection with FIG. 2 is associated with the aggregation of a community of users from the perspective of the service provider 102. In various exemplary embodiments, the service provider 102 notifies the user 106 of a progression of the creation of a specific community of users requested by the user 106. Accordingly, various exemplary embodiments indicate a current number of users that have not yet replied to add requests sent in step 216. In various exemplary embodiments, the service provider 102 maintains a record of associations between the user 106 and communities defined by the user 106. Thus, in various exemplary embodiments, when processing add requests between two users already known to each other, the service provider 102 silently adds the users into the new community without including steps 216 or 218 in the method 200. FIG. 3 is a schematic diagram of a first exemplary embodiment of a graphical user interface (GUI) 300 for policy enabled aggregation of user communities. FIG. 4 is a schematic diagram of a second exemplary embodiment of a graphical user interface (GUI) 400 for policy enabled aggregation of user communities. The GUI 300 corresponds to a community list for the user 106. The GUI 400 corresponds to a community lists for one of the other users 108, 109, 110, 111. Thus, GUI 300 and GUI 400 collectively show an example of contact lists that result from an association between user 106 and one of the other users 108, 109, 110 and 111 based on an application of the method 200. As depicted, upon successfully adding the other user 308 into Community A 304 the user 106 creates another Community B 306 associating an aggregation policy matching the profile of the other user 308. As depicted, Community A 304 also includes User C 310 and User D 312. Likewise, as depicted, Community B 306 also includes User E 316. As depicted, the bundle named My Communities 302 is a list grouping all of the communities belonging to the user 106. Similarly, the bundle named Other Communities 402 groups all of the users owning a community of which the particular user 106 is a part of. Thus, the Other Communities 402 includes Community A 304 and Community B 306. In various exemplary embodiments, upon a change of a subscriber base for the service provider 102, including a modification, creation or deletion of a user profile, the service provider 102 notifies users impacted by the change of potential changes in their communities. Accordingly, in various exemplary embodiments, changes to a user community are performed in a silent mode with no user intervention based on the user's settings. Alternatively, in various exemplary embodiments, changes to a user community are performed by prompting the user if the user wants to accept the change or let the community remain untouched. Again, in various exemplary embodiments this is determined based on settings defined by the user. There are a variety of combinations where a user creates a profile, modifies an existing profile or deletes an existing profile. Each of these three possibilities has a different impact on My Communities 302, Other Communities 402, and even external communities. External communities refer to existing communities in the system 100 that the user 106 is not associated with. Each of these possibilities will be discussed in turn. In various exemplary embodiments, when the user 106 modifies his profile, the impact on My Communities 302 is as follows. The service provider 102 initiates a delete request to each user 308, 310, 312, 316 in My Communities 302 whose anti-aggregation policy matches the new profile of the user 106. In various exemplary embodiments, when the user 106 modifies his profile, the impact on Other Communities 402 is as follows. The service provider 102 initiates a delete request to users in Other Communities 402 whose aggregation policy no longer matches the new profile of the user 106. In various exemplary embodiments, when the user 106 modifies his profile, the impact on external communities is as follows. The service provider 102 initiates add request to communities whose aggregation policy now matches the new profile of the user 106. When a new profile of a user 106 is created, the impact on My Communities 302 and Other Communities 402 is not applicable because My Communities 302 and Other Communities 402 have not yet been created for the newly created user. However, in various exemplary embodiments, when a new user profile is created, the service provider 102 initiates add requests to communities whose aggregation policy matches the new user profile. When a user profile is deleted, the impact on external communities is not applicable. However, in various exemplary embodiments, the impact on My Communities 302 when a user profile is deleted is as follows. The service provider 102 initiates a delete request to users 308, 310, 312, 316 in My Communities 302. In various exemplary embodiments, when a user profile is deleted, the impact on Other Communities 402 is as follows. The service provider 102 initiates a delete request to users in Other Communities 402. In various exemplary embodiments, the user 106 is enabled to delete a community such as Community A 304 or Community B 306. Correspondingly, in various exemplary embodiments, when the user 106 deletes Community A 304 or Community B 306 the user 106 is removed from the Other Communities 402 list of users belonging to Community A 304 or Community B 306. According to the foregoing, various exemplary embodiments overcome current limitations on IM tools. Likewise, various exemplary embodiments solve problems associated with the federation of communities of online users. Various exemplary embodiments enable providers of IM technology to seamlessly provide a policy-based social networking service. Various exemplary embodiments enable users of social networking services to have easy and time-effective access to a wide range of user communities according to customized criteria. In addition to embodiments implemented in IM systems, other exemplary embodiments are implemented using e-mail addresses. Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other different embodiments, and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be affected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only, and do not in any way limit the invention, which is defined only by the claims.	G	60G06	161G06F	21	00
11871979	US20080034285A1-20080207	INFORMATION ARCHITECTURE FOR THE INTERACTIVE ENVIRONMENT	ACCEPTED	20080123	20080207	[]	G06F1724	["G06F1724"]	7992079	20071013	20110802	715	200000	79085.0	HUYNH	THU	[{"inventor_name_last": "Bimson", "inventor_name_first": "Andrea", "inventor_city": "Scottsdale", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Chyung", "inventor_name_first": "Jin", "inventor_city": "Hamburg", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Gopakumar", "inventor_name_first": "Meena", "inventor_city": "Glendale", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Miranda", "inventor_name_first": "Lorraine", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Sarkar", "inventor_name_first": "Biswajit", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Rao", "inventor_name_first": "Shashikant", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Kunte", "inventor_name_first": "Kaustubh", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}]	A system and method for providing management such as creation, manipulation, storage, control, and retrieval of digital content for a company on a global basis. Digital content is created and stored in, for example, the extensible Markup Language (XML) format using the relationship between component mapping information and content information comprising webpage components. The XML data is developed by defining page components, mapping the components on a page and indexing the page for future retrieval of the page. The data is then stored in a single database, as segments related to the page, for call-up by a user.	1. A computer-implemented method for managing digital content for a company website on a global basis, including the steps of: receiving, from a computer of a user, a request to view an updated content page; retrieving a category tag click count for a component corresponding to said user; analyzing said category tag click count to determine a level of interest for establishing user preferences; retrieving said component according to said user preferences, wherein said component includes a category tag corresponding to said user preferences; and, positioning said retrieved component on said updated content page according to content mapping data which includes instructions for mapping said component to said updated content page. 2. The method of claim 1, wherein said markup language file is in at least one of: an extensible Markup Language (XML) format and an HTML format. 3. The method of claim 1, further comprising translating said markup language file to an HTML format for presentation on said company website. 4. The method of claim 1, wherein storing said components as said markup language file includes storing said markup language file in an extensible database that is platform and software independent. 5. The method of claim 1, wherein storing said components as said markup language file includes storing said markup language file in at least one of: a database and a file system. 6. The method of claim 1, wherein storing said components as said markup language file includes storing said markup language file, wherein said markup language file is an XML file, in an extensible database that is platform and software independent. 7. The method of claim 1, further including creating said updated content page. 8. The method of claim 1, further including: receiving, at a content management application, a request to create updated content for a content page within said company website, wherein said updated content comprises components; creating said components according to said request; storing each of said components within a markup language file globally accessible by a reviewer, wherein said components are decoupled from said content page; and, creating an updated content page when each of said components has been authorized, wherein said updated content page does not include said components and comprises said content mapping data. 9. The method of claim 8, further including routing said components to said reviewer, wherein each of said components is individually routed. 10. A computer-implemented method for viewing an updated content page on a company website on a global basis, including the steps of: sending, from a computer of a user to a content management application, a request to view said updated content page, wherein said request causes said content management application to: retrieve a category tag click count for a component corresponding to said user; analyze said category tag click count to determine a level of interest for establishing user preferences; retrieve said component according to said user preferences, wherein said component includes a category tag corresponding to said user preferences; and, position said retrieved component on said updated content page according to content mapping data which includes instructions for mapping said component to said updated content page; and, receiving said updated content webpage for viewing by said user. 11. A computer-readable storage medium containing a set of instructions for a general-purpose computer comprising: receiving, from a computer of a user, a request to view an updated content page; retrieving a category tag click count for a component corresponding to said user; analyzing said category tag click count to determine a level of interest for establishing user preferences; retrieving said component according to said user preferences, wherein said component includes a category tag corresponding to said user preferences; and, positioning said retrieved component on said updated content page according to content mapping data which includes instructions for mapping said component to said updated content page.	<SOH> BACKGROUND OF INVENTION <EOH>As more and more companies begin to provide a presence on the internet, they are confronted with the issues of presentation of information and conformity within the preparation of the presentations. Various schemes have been presented to assist the companies in preparing the presentation screens that would appear on the internet website, along with placing the presentation of the page in a location or locations that are linked, requiring a user to traverse various web pages to obtain the presentation desired. Such approaches have included delegated authority systems, have used content aggregation, have provided graphical interfaces and dynamically generated web documents. Other general website management has included editing and generating information, data access/processing systems, automatic publishing systems and group ware systems. These approaches generally demand a knowledge of the HTML operating language, a capability generally only found in the website programmers and not among general employees. The prior art generally fails to disclose a process for implementing changes to an internet website, such that employees in a corporation may define and enforce a common style of page layout to provide an application that can be accessed by multiple users at the same time by an internet browser, where the application allows corporate employees to manage content, create new web pages, process content through workflow, and define new content and style which can then be provided to a user without an undue amount of searching to find the desired information. Accordingly, once the presentation page is completed, data elements relating to the significance of the content are utilized to store information relating to the content in various locations or sites, with the various sites interconnected through the use of links. Thus, to obtain the information desired, a user may, of necessity, be forced to traverse several links to obtain the desired page with the required information.	<SOH> SUMMARY OF THE INVENTION <EOH>The previously described deficiencies in the prior art are addressed in the present invention which, in conjunction with a content management application, provides an intranet application to provide a system for implementing changes to both an intranet or an internet website and, permitting a company to manage content for its website from a global perspective. The content, created and stored once, can then be shared and managed across a global organization. The information architecture system is the basic underlying infrastructure that allows a company to efficiently manage its content while taking advantage of various efficiencies. The data can thus be viewed from a holistic perspective utilizing a structure of website contents that results from the relationship between objects on the physical pages, i.e., appearance only, instead of the prior art reliance on the significance of the data elements displayed on the page, thereby providing a look and feel driven structure. The system function supports a workflow model for the launching of content and is extensible so the information architecture does not need to be expanded in order to support new data. Further, the system is platform and software independent whereby the content stored in the infrastructure can be delivered on any platform with the system providing granularity of content management. In one exemplary embodiment, the system makes use of the extensible Markup Language (XML) to store relevant content. The use of XML provides extensible data schema, content reuse, also known as repurposing, and flexible look and feel. Since the information architecture is XML based, it can be implemented either using a database, XML repository or a flat file based system.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 09/769,887 entitled “INFORMATION ARCHITECTURE FOR THE INTERACTIVE ENVIRONMENT” filed on Jan. 25, 2001, which application claims priority to and the benefit of U.S. Provisional Application No. 60/178,456 filed on Jan. 27, 2000, both of which are contained herein by reference. FIELD OF THE INVENTION The invention relates generally to methods and apparatus for managing content of a company-wide intranet or internet website, and more particularly, to systems for organizing data related in a single database so the content can be managed from a global perspective. BACKGROUND OF INVENTION As more and more companies begin to provide a presence on the internet, they are confronted with the issues of presentation of information and conformity within the preparation of the presentations. Various schemes have been presented to assist the companies in preparing the presentation screens that would appear on the internet website, along with placing the presentation of the page in a location or locations that are linked, requiring a user to traverse various web pages to obtain the presentation desired. Such approaches have included delegated authority systems, have used content aggregation, have provided graphical interfaces and dynamically generated web documents. Other general website management has included editing and generating information, data access/processing systems, automatic publishing systems and group ware systems. These approaches generally demand a knowledge of the HTML operating language, a capability generally only found in the website programmers and not among general employees. The prior art generally fails to disclose a process for implementing changes to an internet website, such that employees in a corporation may define and enforce a common style of page layout to provide an application that can be accessed by multiple users at the same time by an internet browser, where the application allows corporate employees to manage content, create new web pages, process content through workflow, and define new content and style which can then be provided to a user without an undue amount of searching to find the desired information. Accordingly, once the presentation page is completed, data elements relating to the significance of the content are utilized to store information relating to the content in various locations or sites, with the various sites interconnected through the use of links. Thus, to obtain the information desired, a user may, of necessity, be forced to traverse several links to obtain the desired page with the required information. SUMMARY OF THE INVENTION The previously described deficiencies in the prior art are addressed in the present invention which, in conjunction with a content management application, provides an intranet application to provide a system for implementing changes to both an intranet or an internet website and, permitting a company to manage content for its website from a global perspective. The content, created and stored once, can then be shared and managed across a global organization. The information architecture system is the basic underlying infrastructure that allows a company to efficiently manage its content while taking advantage of various efficiencies. The data can thus be viewed from a holistic perspective utilizing a structure of website contents that results from the relationship between objects on the physical pages, i.e., appearance only, instead of the prior art reliance on the significance of the data elements displayed on the page, thereby providing a look and feel driven structure. The system function supports a workflow model for the launching of content and is extensible so the information architecture does not need to be expanded in order to support new data. Further, the system is platform and software independent whereby the content stored in the infrastructure can be delivered on any platform with the system providing granularity of content management. In one exemplary embodiment, the system makes use of the extensible Markup Language (XML) to store relevant content. The use of XML provides extensible data schema, content reuse, also known as repurposing, and flexible look and feel. Since the information architecture is XML based, it can be implemented either using a database, XML repository or a flat file based system. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention are hereinafter described in the following detailed description of exemplary embodiments to be read in conjunction with the accompanying drawing figures, wherein like reference numerals are used to identify the same or similar parts or steps in the similar views, and: FIG. 1 is an exemplary representation of the workflow and page storage aspect of the present invention; FIG. 2 is an exemplary block diagram depicting an embodiment of the Information Architecture System using Content Management of the present invention; FIG. 3 is an exemplary block diagram depicting a user accessing the global database of the Information Architecture System; FIGS. 4a-4c are exemplary screen presentations provided by a user of the Information Architecture System; and FIG. 5 is an exemplary workflow diagram depicting a logical data model of the information architecture. DETAILED DESCRIPTION The present invention may be described herein in terms of functional block components and various processing steps. It should be appreciated that such functional blocks may be realized by any number of hardware and/or software components configured to perform the specified functions. For example, the software elements of the present invention may be implemented with any programming or scripting language such as C, C++, Java, PERL, or the like, with the various algorithms being implemented with any combination of data structures, objects, processes, routines or other programming elements. Further it should be noted that the present invention may employ any number of conventional techniques for data transmission, signaling, data processing, network control, and the like. Still further, the invention could be used to detect or prevent security issues with a scripting language, such as JavaScript, VBScript or the like. It should be appreciated that the particular implementations shown and described herein are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the present invention in any way. Indeed, for the sake of brevity, conventional data networking, application development and other functional aspects of the systems (and components of the individual operating components of the systems) may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in a practical electronic transaction system. As hereinafter described, the present invention is directed to a system and method for providing management such as creation, manipulation, storage, control, and retrieval of digital content for use in such as a company website on a global basis and includes support for new page layouts and component layouts (i.e., support for new presentation styles whether in Hypertext Markup Language (HTML), Wireless Markup Language (WML), PDF, or any other authoring language in which the presentation may be written). Further, the present invention permits content repurposing, i.e., the reuse of existing content for other forms of media once the content has been produced and stored in a database. Accordingly, repurposing permits use of the content in such forms as mail, print, or other websites or any application in which the printed or electronic word is used and which may take advantage of the content stored in the database. The information architecture of the present invention provides for a separation of data from the presentation itself. Thus, the information architecture data content, not being tied to the presentation, may, for example, enable the database to support various foreign languages, formats and medias. Referring now to FIG. 1, there is shown at 100 an exemplary representation of the flow diagram of the information architecture system of the present invention. The site administrator 102, initiates a project to develop a new web page by assigning an author 106 to create the page and its XML representation is stored in the database using a content management application system 108. This starts the workflow 104 whereby the author creates the page, then the author submits it for approval through various levels. Once the approvals are obtained, the site administrator 102 approves a content launch 110. While various scripting languages may be used in creating content and/or a page, by way of example only and not by way of limitation, the content/page is written in the extensible Markup Language (XML) and is stored in database 120 as an XML file. An external web user 130 wishing to access the information contained in the page would request the page through a Content Delivery Application (CDA) translator 140. The CDA translator 140 would query the database 120, retrieve the page and translate the XML file into an HTML page or any other presentation format suitable for user's device for presentation to the user 130. Referring now to FIG. 2, an exemplary embodiment of the present invention is shown at 200. This embodiment uses a workflow group, such as shown in FIG. 1, under control of the local site administrator 202. The workflow group includes a content author 206 and content approvers 208. Once the site administrator 202 initiates a project and verbally communicates the user ID and password to each new user designated in the workflow, designated content author 206 creates and edits items using content management applications. Designated content approvers 208 review the content items produced by content author 206 and pass them through an approval process. Content approvers 208 mark the items as approved or rejected and, when the new content has been approved by all concerned users in the workflow, local site administrator 202 launches the content to the global database 220. Users, using web browsers 230a, 230b, 230c, interface through the worldwide web 232 to review the launched content. In some instances, the request must be processed through a firewall 234 providing security to the global database 220. Again, the XML file from the global database containing the requested information is processed through a CDA translator into HTML, or a representation suitable for the user's device, passed through the firewall 234 and presented in an HTML or suitable representative language format on the worldwide web 232 for access by the web user requesting the information. Referring now to FIG. 3, there is shown an exemplary block diagram at 300 of a user accessing the global database of the network architecture system of the present invention. A user 330 connects to the internet or worldwide web 332, logging on through a firewall 334, if such is present, to a CDA translator to request information from database 320. The database, comprising various XML files relating to the various pages stored therein in XML, as Segment 1, 350, Segment 2, 352 through Segment X, 354. Once the proper segment containing the requested page is located, it is transmitted from the database 320 to the CDA translator, which translates the XML file to, for example, an HTML page for presentation through the firewall 334 to the internet 332 for presentation to user 330. Referring also to FIGS. 4a-4c, exemplary screen presentations accessible by user of the network architecture system are shown. The presentations 4a, 4b, 4c correspond to the various segments 350, 352, 354 depicted in FIG. 3 comprising the information relating to the content contained within the page. Referring now to FIG. 5, each exemplary information segment shown in FIG. 3 may be seen to include a top level index to the information contained within the page/segment at 502. The page index defines the location of page level information at 504. Page level information 504 defines segment component mapping at 506. Information contained within page component mapping 506 relates to component content information 508. Component content information 508 contains information relating to the various parts of a page, such as the navigation components, the cross-sell components, copyright components, and the like. Additionally, the component content information 508 includes page key word relationships, along with the component type information 510. Component type information 510 further defines the component item information used in generating various items within a page. Base element information 514 provides information used in developing the component item information 512. Accordingly, corresponding structures, acts, and equivalents of all elements in the claims below are intended to include any structural material or acts for performing the functions in combination with other elements as specifically claimed. The scope of the invention should be determined by the allowed claims and their legal equivalents, rather than by the examples given above.	G	60G06	161G06F	17	24
11741650	US20080270976A1-20081030	MANAGEMENT OF GRAPHICAL INFORMATION NOTES	ACCEPTED	20081016	20081030	[]	G06F944	["G06F944"]	8584091	20070427	20131112	717	105000	97774.0	VU	TUAN	[{"inventor_name_last": "Champion", "inventor_name_first": "David Frederick", "inventor_city": "Durham", "inventor_state": "NC", "inventor_country": "US"}, {"inventor_name_last": "Nyeste", "inventor_name_first": "Patrick Gabor", "inventor_city": "Raleigh", "inventor_state": "NC", "inventor_country": "US"}, {"inventor_name_last": "Smith", "inventor_name_first": "Jeffrey John", "inventor_city": "Raleigh", "inventor_state": "NC", "inventor_country": "US"}, {"inventor_name_last": "Windell", "inventor_name_first": "David Thomas", "inventor_city": "Raleigh", "inventor_state": "NC", "inventor_country": "US"}]	Provided are a method, system, and article of manufacture, wherein information is associated with a program element that is capable of being processed in a software environment generated by an operating system. A graphical information note application is executed in response to a processing of the program element in the software environment. A graphical information note that includes the associated information is displayed, in response to the execution of the graphical information note application.	1. An article of manufacture including code, wherein the code when executed by a computer performs operations, the operations comprising: associating information with a program element that is capable of being processed in a software environment generated by an operating system; executing a graphical information note application in response to a processing of the program element in the software environment; and displaying a graphical information note that includes the associated information, in response to the execution of the graphical information note application. 2. The article of manufacture of claim 1, wherein the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. 3. The article of manufacture of claim 1, wherein the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment, and wherein the graphical information note is transferred from one device to another over a wired or a wireless network. 4. The article of manufacture of claim 1, wherein the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. 5. The article of manufacture of claim 1, wherein the executing and displaying further comprises: analyzing one or more words included in the information associated with the program element; and triggering the graphical information note application to display the graphical information note based on the analyzing of the one or more words included in the information associated with the program element. 6. A method, comprising: associating information with a program element that is capable of being processed in a software environment generated by an operating system; executing a graphical information note application in response to a processing of the program element in the software environment; and displaying a graphical information note that includes the associated information, in response to the execution of the graphical information note application. 7. The method of claim 6, wherein the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. 8. The method of claim 6, wherein the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment, and wherein the graphical information note is transferred from one device to another over a wired or a wireless network. 9. The method of claim 6, wherein the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. 10. The method of claim 6, wherein the executing and displaying further comprises: analyzing one or more words included in the information associated with the program element; and triggering the graphical information note application to display the graphical information note based on the analyzing of the one or more words included in the information associated with the program element. 11. A system, comprising: memory; and processor coupled to the memory, wherein the processor performs operations, the operations comprising: associating information with a program element that is capable of being processed in a software environment generated by an operating system; executing a graphical information note application in response to a processing of the program element in the software environment; and displaying a graphical information note that includes the associated information, in response to the execution of the graphical information note application. 12. The system of claim 11, wherein the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. 13. The system of claim 11, wherein the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment, and wherein the graphical information note is transferred from one device to another over a wired or a wireless network. 14. The system of claim 11, wherein the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. 15. The system of claim 11, wherein the executing and displaying further comprises: analyzing one or more words included in the information associated with the program element; and triggering the graphical information note application to display the graphical information note based on the analyzing of the one or more words included in the information associated with the program element. 16. A method for deploying computing infrastructure, comprising integrating computer-readable code into a computer, wherein the code in combination with the computer is capable of performing: associating information with a program element that is capable of being processed in a software environment generated by an operating system; executing a graphical information note application in response to a processing of the program element in the software environment; and displaying a graphical information note that includes the associated information, in response to the execution of the graphical information note application. 17. The method for deploying computing infrastructure of claim 16, wherein the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. 18. The method for deploying computing infrastructure of claim 16, wherein the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment, and wherein the graphical information note is transferred from one device to another over a wired or a wireless network. 19. The method for deploying computing infrastructure of claim 16, wherein the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. 20. The method for deploying computing infrastructure of claim 16, wherein the executing and displaying further comprises: analyzing one or more words included in the information associated with the program element; and triggering the graphical information note application to display the graphical information note based on the analyzing of the one or more words included in the information associated with the program element.	<SOH> BACKGROUND <EOH>1. Field The disclosure relates to a method, system, and article of manufacture for the management of graphical information notes. 2. Background Physical “sticky notes” are widely used in office environments. Such physical sticky notes are relatively small physical pieces of paper on which an adhesive has been applied on one side to facilitate the attachment of the physical sticky note to a physical surface. Users may write reminders on such physical sticky notes and use these physical sticky notes as reminder aids. Certain software systems allow electronic versions of such physical sticky notes to be used. Such electronic versions of the physical sticky notes may be referred to as graphical information notes. Such graphical information notes may be displayed on the desktop and may allow users to make quick, temporary notes. Graphical information notes that pop up at predetermined times may be found in certain software systems. However, graphical information notes may have many of the same problems as physical sticky notes. Clutter and improper arrangements of graphical information notes may reduce the effectiveness of this memory aid and important tasks may be forgotten by users.	<SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>Provided are a method, system, and article of manufacture, wherein information is associated with a program element that is capable of being processed in a software environment generated by an operating system. A graphical information note application is executed in response to a processing of the program element in the software environment. A graphical information note that includes the associated information is displayed, in response to the execution of the graphical information note application. In additional embodiments, the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. In further embodiments, the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment. In still further embodiments, the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. In yet further embodiments, the executing and displaying further comprises analyzing one or more words included in the information associated with the program element, and triggering the graphical information note application to display the graphical information note is based on the analyzing of the one or more words included in the information associated with the program element.	BACKGROUND 1. Field The disclosure relates to a method, system, and article of manufacture for the management of graphical information notes. 2. Background Physical “sticky notes” are widely used in office environments. Such physical sticky notes are relatively small physical pieces of paper on which an adhesive has been applied on one side to facilitate the attachment of the physical sticky note to a physical surface. Users may write reminders on such physical sticky notes and use these physical sticky notes as reminder aids. Certain software systems allow electronic versions of such physical sticky notes to be used. Such electronic versions of the physical sticky notes may be referred to as graphical information notes. Such graphical information notes may be displayed on the desktop and may allow users to make quick, temporary notes. Graphical information notes that pop up at predetermined times may be found in certain software systems. However, graphical information notes may have many of the same problems as physical sticky notes. Clutter and improper arrangements of graphical information notes may reduce the effectiveness of this memory aid and important tasks may be forgotten by users. SUMMARY OF THE PREFERRED EMBODIMENTS Provided are a method, system, and article of manufacture, wherein information is associated with a program element that is capable of being processed in a software environment generated by an operating system. A graphical information note application is executed in response to a processing of the program element in the software environment. A graphical information note that includes the associated information is displayed, in response to the execution of the graphical information note application. In additional embodiments, the program element comprises one of an application, a file, an event, and an action, wherein the information can be associated with more than one program element, and wherein the graphical information note includes an indication of the program element with which the information is associated during the displaying of the graphical information note. In further embodiments, the execution of the graphical information note application to display the graphical information note occurs in response to a user action performed in the software environment. In still further embodiments, the execution of the graphical information note application to display the graphical information note is in response to a series of events occurring in a computational device that implements the software environment. In yet further embodiments, the executing and displaying further comprises analyzing one or more words included in the information associated with the program element, and triggering the graphical information note application to display the graphical information note is based on the analyzing of the one or more words included in the information associated with the program element. BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings in which like reference numbers represent corresponding parts throughout: FIG. 1 illustrates a block diagram of a computing environment, in accordance with certain embodiments; FIG. 2 illustrates a block diagram of a first graphical information note, in accordance with certain embodiments; FIG. 3 illustrates a block diagram of a magnified version of the first graphical information note, in accordance with certain embodiments; FIG. 4 illustrates a block diagram of a second graphical information note, in accordance with certain embodiments; FIG. 5 illustrates a block diagram of a magnified version of the second graphical information note, in accordance with certain embodiments; FIG. 6 illustrates a block diagram of a third graphical information note, in accordance with certain embodiments; FIG. 7 illustrates a block diagram of a magnified version of the third graphical information note, in accordance with certain embodiments; FIG. 8 illustrates a block diagram for organizing and consolidating graphical information notes, in accordance with certain embodiments; FIG. 9 illustrates a block diagram of a graphical information note that includes multiple cues for displaying priority level information, in accordance with certain embodiments; FIG. 10 illustrates operations for managing graphical information notes, in accordance with certain embodiments; and FIG. 11 illustrates a block diagram of a computer architecture in which certain described aspects of the embodiments are implemented. DETAILED DESCRIPTION In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made. Certain embodiments provide action, event, application and file-based reminders on graphical information notes. In certain embodiments, graphical information notes may be associated with particular documents, folders and applications and may be opened to remind the user of important tasks. Associated graphical information notes can pop up automatically on a display with the opening of a particular file, an attempt to perform a particular action, or the startup of an application. For example, a prompt to look at a particular website may open when an Internet browser window is opened, or a reminder to print out a particular document may pop up when other documents are printed. Application, action, and file-based reminders provide additional capabilities beyond time-based reminders. In certain other embodiments, graphical information notes may alert users about active notes automatically upon the startup of a computational device, and on attempts to shut down, hibernate, or restart a computational device. In certain embodiments graphical information notes may have a minimal footprint, moving to a designated area of the display and displaying only a title if desired, in order to keep the desktop from being cluttered. Graphical information notes may also automatically organize themselves by importance, topic, date, etc. within a folder for easy viewing, sorting, printing, emailing, and managing of the graphical information notes. Graphical information notes could then be reapplied to particular documents, moved to new drafts, organized, etc. Graphical information notes may provide additional capabilities beyond a permanent to-do list and simple temporally-based reminders provided by certain applications. Combining the automatic alert element with the ability to affiliate particular graphical information notes with applications, documents, etc., may eliminate certain problems related to the usage of graphical information notes. For example, clutter of graphical information notes on the display and the likelihood of forgotten reminders may be reduced. Exemplary Embodiments FIG. 1 illustrates block diagram of a computing environment 100 in which a computational device 102 is included. The computational device 102 may be any computational device known in the art, such as a personal computer, a workstation, a server, a mainframe, a hand held computer, a palm top computer, a telephony device, a network appliance, etc. The computational device 102 includes an operating system 104, a graphical information note application 104, and is capable of including, executing, generating, or allow the generating of program elements 106. A display 108 may be coupled to the computational device 102, where the display 108 may comprise any display device known in the art, such as a LCD (Liquid Crystal Display) device, etc. The graphical information note application 106 is an application implemented in software, hardware, firmware, or any combination thereof in the computational device 102. The program elements 106 may include many different types of applications 112 (e.g., electronic mail programs, word processing programs, etc.), data storage entities 114 (e.g., folders 116, files 118, etc.), dynamic features 120 (e.g., actions 122, action sequences 124, events 126, event sequences 128), etc. Actions 122 may include actions performed by a user, such as a mouse click to print a file. Events 124 may include any event occurring within the computational device 102, such as, a startup or shutdown of the computational device 102. In certain embodiments, graphical information notes may be transferred over a wired connection or over a wireless connection from one device to another. For example, a graphical information note may be transferred from a desktop computer to a mobile telephony device over a wireless network by utilizing mobile operating systems or other software programs. Transfers of graphical information notes may also be accomplished via electronic transmissions that include electronic mail, short message service (SMS), SMSVoice, Bluetoothwireless technology, universal serial bus (USB), or other mechanisms. Additionally, graphical information notes generated or edited within a mobile device may be transferred back to workstations, laptops or any computational device. In certain embodiments, software graphical information note management application programs could include actions associated with mobile devices such as call actions, alarms, etc, which can control the display or salience of the graphical information notes. Other embodiments may include additional program elements not shown in FIG. 1. A plurality of different types of information (denoted by reference numerals 108a, 108b, . . . 108n) may be associated with the program elements 106 via associations 110 created by the graphical information note application 106. For example, in certain embodiments information 108a may be a reminder that is associated with a file 118, and information 108b may be a reminder that is associated with a sequence of events 128 that could potentially occur in a software environment generated by the operating system 104. The information 108 . . . 108n may be associated with any of the many different types of program elements 112, 114, 116, 118, 120, 122, 124, 126, and 128 shown in FIG. 1. In certain embodiments illustrated in FIG. 1, the graphical information note application 106 associates information 108a . . . 108n with program elements 106 that are capable of being processed in a software environment generated by an operating system 104. The graphical information note application 106 is executed in response to a processing of a program element in the software environment. A graphical information note 130 that includes the associated information, is displayed in the display 108, in response to the execution of the graphical information note application 106. FIGS. 2-9 illustrate various types on graphical information notes 130 that appear on the display 108 in certain embodiments. Other embodiments may display other types of elements and graphical information notes on the display 108. FIG. 2 shows an exemplary graphical information note 200 displayed in an exemplary window 202 on the display 108. FIG. 3 shows a magnified view of the exemplary graphical information note 200. In FIGS. 2 and 3, a user has elected to surface, i.e., popup or display, a low-priority note (indicated redundantly by the relatively small area occupied by the bar 300) with an exemplary application 302 (Microsoft Word) or action 304 (printing). In this instance, the note surfaced when the user opened Microsoft Word 204. The graphical information note 200 can be hidden with a single mouse click on the “Hide” button 306 of the sticky note 200. In addition, all graphical information notes can be displayed and managed by pressing the “Show All” button 308. The opening of the graphical information note with Microsoft Word is shown via reference numeral 310 which shows the Microsoft Word application. FIG. 4 shows an exemplary graphical information note 400 displayed in an exemplary window 402 on the display 108. FIG. 5 shows a magnified view of the exemplary graphical information note 400. FIGS. 4 and 5 display the same graphical information note of FIGS. 2 and 3 surfaced when a user-selected printing action is initiated. Redundant indication (shown by reference numeral 500 that indicates print) is used to indicate the reason why the graphical information note 400 surfaced, in order to eliminate user confusion about why a particular reminder appeared. In order to achieve this redundancy, the graphical information note 400 is attached to the printing menu 404, Additionally, the graphical information note 400 indicates has a “print” 500 indicator. FIG. 6 shows an exemplary graphical information note 600 displayed in an exemplary desktop window 602 on the display 108. FIG. 7 shows a magnified view of the exemplary graphical information note 600. FIGS. 6 and 7 demonstrate the surfacing of the graphical information note 600 upon an attempted shutdown as shown by the shutdown window 604. This feature may be designed to prevent users from shutting down systems with important tasks remaining on their to-do lists. This graphical information note 600 may also have surfaced if Lotus Notes*602 (or any other user-specified application, file, or action) had been accessed or attempted. For example, surfacing of the graphical information note 600 may occur when a user attempts to lock a computational device. FIG. 8 shows certain embodiments for organizing and consolidating graphical information notes. Graphical information notes can be sorted by priority 800, timestamp 802, surface application/action/files 804, and graphical information note content 806 in the exemplary embodiment shown in FIG. 8. FIG. 8 shows that a graphical information note can be associated with any number of actions, applications, or files. FIG. 9 displays a graphical information note 900 that provides an exemplary display of priority level information. In FIG. 9, priority levels may be indicated redundantly by color or shading (reference numeral 902) and area (reference numeral 904) occupied by the bar. For example, light shading may indicate a lower priority and dark shading a higher priority, and a smaller area may indicate a lower priority than a larger area. In certain embodiments a user may be able to determine the priority by either observing the color/shading or by observing the area in the priority level indicator 906. FIG. 10 illustrates operations performed in certain embodiments. The operations may be implemented in the computational device 102. Control starts at block 1000, where information 108a . . . 108n to be displayed is associated with a plurality of program elements 106, such as applications 112, folders 116, files 118, actions 122, a sequence of actions 124, events 126, a sequence of events 128, wherein the associations are made via a graphical information note application 106. In certain embodiments the same information may be associated with one or more than one program elements. A program element with which information has been associated is processed (at block 1002). As a result, the graphical information note application 106 is triggered (at block 1004). A graphical information note 130 that includes the information associated with the program element is displayed (at block 1006) on the display 108. For example, in the embodiment shown in FIG. 4 the information “Print meeting notes from Tuesday” (shown within the exemplary graphical information note 400) is associated with the printing action 404. When the printing action is performed the graphical information note application 106 is triggered and the graphical information note 400 that includes the information “Print meeting notes from Tuesday” is displayed on the display 108. In certain embodiments, graphical information notes surface at a user-specified time, reminding the user of a task and its importance. Embodiments allow the ability to associate reminders with any application, file, and/or action (including startup and shutdown) for rapid surfacing of graphical information notes to users at times when reminders are necessary and intended actions should or can be completed. Certain embodiments allow the ability to attach reminders to single/multiple applications, actions, and files (e.g., Microsoft Word, shut down, printing). Users may benefit because these reminders are surfaced at a time when intended activities should be completed rather than merely being placed onto the desktop or surfacing at a specific time. In addition, reminders can be redundantly associated with multiple applications, actions, and/or files to increase the effectiveness of the reminders. For example, the task “print meeting notes” could be associated with Microsoft Word, printing, and locking the computer; the reminder would then surface when Microsoft Word was opened, when printing from any application occurred, and upon an attempt to lock the computer. In additional embodiments mechanisms for the removal of graphical information notes may be implemented. Removal of a graphical information note may be performed via a software button included within the graphical information note or via the graphical information note application. Additionally, a timed expiration mechanism or an automated removal mechanism may be used for the removal of a graphical information note. Other alternative embodiments may provide alternative implementations for the removal of graphical information notes. Additional Embodiment Details The described techniques may be implemented as a method, apparatus or article of manufacture involving software, firmware, micro-code, hardware and/or any combination thereof. The term “article of manufacture” as used herein refers to code or logic implemented in a medium, where such medium may comprise hardware logic [e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), Programmable System on Chip (PSoC). etc.] or a computer readable storage medium, such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, optical disks, etc.), volatile and non-volatile memory devices [e.g., Electrically Erasable Programmable Read Only Memory (EEPROM), Read Only Memory (ROM), Programmable Read Only Memory (PROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash, firmware, programmable logic, etc.], solid state storage devices (e.g., solid state serial ATA, i.e., solid state SATA, etc.). Code in the computer readable storage medium is accessed and executed by a processor. The medium in which the code or logic is encoded may also comprise transmission signals propagating through space or a transmission media, such as an optical fiber, copper wire, etc. The transmission signal in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signal in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices. Additionally, the “article of manufacture” may comprise a combination of hardware and software components in which the code is embodied, processed, and executed. Of course, those skilled in the art will recognize that many modifications may be made without departing from the scope of embodiments, and that the article of manufacture may comprise any information bearing medium. For example, the article of manufacture comprises a storage medium having stored therein instructions that when executed by a machine results in operations being performed. Certain embodiments can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, certain embodiments can take the form of a computer program product accessible from a computer usable or computer readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer usable or computer readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. The terms “certain embodiments”, “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean one or more (but not all) embodiments unless expressly specified otherwise. The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise. Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries. Additionally, a description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments. Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously, in parallel, or concurrently. When a single device or article is described herein, it will be apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be apparent that a single device/article may be used in place of the more than one device or article. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments need not include the device itself. FIG. 11 illustrates the architecture of computing system 1100, wherein in certain embodiments the computational device 102 of the computing environment 100 of FIG. 1 may be implemented in accordance with the architecture of the computing system 1100. The computing system 1100 may also be referred to as a system, and may include a circuitry 1102 that may in certain embodiments include a processor 1104. The system 1100 may also include a memory 1106 (e.g., a volatile memory device), and storage 1108. The storage 1108 may include a non-volatile memory device (e.g., EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, firmware, programmable logic, etc.), magnetic disk drive, optical disk drive, tape drive, etc. The storage 1108 may comprise an internal storage device, an attached storage device and/or a network accessible storage device. The system 1100 may include a program logic 1110 including code 1112 that may be loaded into the memory 1106 and executed by the processor 1104 or circuitry 1102. In certain embodiments, the program logic 1110 including code 1112 may be stored in the storage 1108. In certain other embodiments, the program logic 1110 may be implemented in the circuitry 1102. Therefore, while FIG. 11 shows the program logic 1110 separately from the other elements, the program logic 1110 may be implemented in the memory 1106 and/or the circuitry 1102. Certain embodiments may be directed to a method for deploying computing instruction by a person or automated processing integrating computer-readable code into a computing system, wherein the code in combination with the computing system is enabled to perform the operations of the described embodiments. At least certain of the operations illustrated in FIGS. 1-11 may be performed in parallel as well as sequentially. In alternative embodiments, certain of the operations may be performed in a different order, modified or removed. Furthermore, many of the software and hardware components have been described in separate modules for purposes of illustration. Such components may be integrated into a fewer number of components or divided into a larger number of components. Additionally, certain operations described as performed by a specific component may be performed by other components. The data structures and components shown or referred to in FIGS. 1-11 are described as having specific types of information. In alternative embodiments, the data structures and components may be structured differently and have fewer, more or different fields or different functions than those shown or referred to in the figures. Therefore, the foregoing description of the embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. Microsoft Word is a trademark or registered trademark of Microsoft Corporation. Lotus Notes is a trademark or registered trademark of IBM Corporation. Bluetooth is a trademark of Bluetooth SIG, Inc.	G	60G06	161G06F	9	44
11770725	US20080165136A1-20080710	System and Method for Managing Lists	ACCEPTED	20080625	20080710	[]	G06F3041	["G06F3041"]	8091045	20070628	20120103	715	863000	79338.0	AUGUSTINE	NICHOLAS	[{"inventor_name_last": "Christie", "inventor_name_first": "Greg", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Forstall", "inventor_name_first": "Scott", "inventor_city": "Mountain View", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Lemay", "inventor_name_first": "Stephen O.", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Ording", "inventor_name_first": "Bas", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Van Os", "inventor_name_first": "Marcel", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chaudhri", "inventor_name_first": "Imran", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}]	A computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items, detecting a finger contact on a moving-affordance icon, detecting movement of the finger contact on the touch screen display, and in response to detecting the movement of the finger contact, moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons.	1. A computer-implemented method, comprising: at a portable multifunction device with a touch screen display, displaying a list of items on the touch screen display; detecting a finger gesture on an edit initiation icon; in response to detecting the finger gesture on the edit initiation icon, displaying moving-affordance icons for corresponding items in the list; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; in response to detecting the movement of the finger contact while on the moving-affordance icon, moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact; detecting a break of the finger contact on the touch screen display at a break location on the touch screen display; in response to detecting the break, placing the corresponding item in the list at a position corresponding to the break location on the touch screen display; detecting a finger gesture on an edit completion icon; and in response to detecting the finger gesture on the edit completion icon, ceasing to display the moving-affordance icons. 2. A computer-implemented method, comprising: at a portable multifunction device with a touch screen display, displaying a list of items, wherein at least some of the items have corresponding moving-affordance icons; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; and in response to detecting the movement of the finger contact, moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. 3. The computer-implemented method of claim 2, wherein detecting the movement of the finger contact comprises detecting the movement of the finger contact while the finger contact is on the moving-affordance icon. 4. The computer-implemented method of claim 2, wherein the list of items is a playlist of songs, a list of phone numbers, a list of pictures, a list of files, a list of photo albums, a list of photographs, a list of videos, or a list of software applications. 5. The computer-implemented method of claim 2, including displaying moving-affordance icons in response to detection of a finger gesture on an edit initiation icon and ceasing to display moving-affordance icons in response to detection of a finger gesture on an edit completion icon. 6. The computer-implemented method of claim 5, wherein the finger gesture is a tap gesture. 7. The computer-implemented method of claim 2, including: detecting a break of the finger contact on the touch screen display at a break location on the touch screen display; and in response to detecting the break, placing the corresponding item in the list at a position corresponding to the break location on the touch screen display. 8. The computer-implemented method of claim 2, wherein the moving item comprises a user selected item, the method including, while the user selected item in the list is moving over a second item, simultaneously moving the second item in the list in a direction opposite movement of the user selected item. 9. A graphical user interface on a portable multifunction device with a touch screen display, comprising: a list of items on the touch screen display; and moving-affordance icons for corresponding items in the list; wherein: in response to detecting a finger contact on a moving-affordance icon and detecting movement of the finger contact, the moving-affordance icon and the corresponding item in the list are moved in accordance with the movement of the finger contact. 10. A portable multifunction device, comprising: a touch screen display; one or more processors; memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including: instructions for displaying a list of items, wherein at least some of the items have corresponding moving-affordance icons; instructions for detecting a finger contact on a moving-affordance icon; instructions for detecting movement of the finger contact on the touch screen display; and instructions for moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. 11. A computer-program product, comprising: a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to: display a list of items, wherein at least some of the items have corresponding moving-affordance icons; detect a finger contact on a moving-affordance icon; detect movement of the finger contact on the touch screen display; and in response to detecting the movement of the finger contact, move the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. 12. A portable multifunction device with a touch screen display, comprising: means for displaying a list of items, wherein at least some of the items have corresponding moving-affordance icons; means for detecting a finger contact on a moving-affordance icon; means for detecting movement of the finger contact on the touch screen display; and means for moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. 13. A computer-implemented method, comprising: at a portable multifunction device with a touch screen display, displaying a list of items on the touch screen display; detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; detecting movement of the finger contact on the touch screen display after the predetermined time; in response to detecting the movement of the finger contact, moving the item in the list in accordance with the movement of the finger contact; detecting a break of the finger contact on the touch screen display at a break location on the touch screen display; and in response to detecting the break, placing the item in the list at a position corresponding to the break location on the touch screen display. 14. A computer-implemented method, comprising: at a portable multifunction device with a touch screen display, displaying a list of items on the touch screen display; detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; detecting movement of the finger contact on the touch screen display after the predetermined time; and in response to detecting the movement of the finger contact, moving the item in the list in accordance with the movement of the finger contact. 15. The computer-implemented method of claim 14, wherein the list of items is a playlist of songs, a list of phone numbers, a list of pictures, a list of files, a list of photo albums, a list of photographs, a list of videos, or a list of software applications. 16. The computer-implemented method of claim 14, including: detecting a break of the finger contact on the touch screen display at a break location on the touch screen display; and in response to detecting the break, placing the item in the list at a position corresponding to the break location on the touch screen display. 17. The computer-implemented method of claim 14, including, while the finger-contacted item in the list is moving over a second item, simultaneously moving the second item in the list in a direction opposite movement of the finger-contacted item. 18. A graphical user interface on a portable multifunction device with a touch screen display, comprising: a list of items on the touch screen display, wherein: in response to detecting a finger contact on an item, wherein the finger contact is stationary for more than a predetermined time, and detecting movement of the finger contact after the predetermined time, the item is moved in accordance with the movement of the finger contact. 19. A portable multifunction device, comprising: a touch screen display; one or more processors; memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including: instructions for displaying a list of items on the touch screen display; instructions for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; instructions for detecting movement of the finger contact on the touch screen display after the predetermined time; and instructions for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. 20. A computer-program product, comprising: a computer readable storage medium and a computer program mechanism embedded therein, the computer program mechanism comprising instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to: display a list of items on the touch screen display; detect a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; detect movement of the finger contact on the touch screen display after the predetermined time; and in response to detecting the movement of the finger contact, move the item in the list in accordance with the movement of the finger contact. 21. A portable multifunction device with a touch screen display, comprising: means for displaying a list of items on the touch screen display; means for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; means for detecting movement of the finger contact on the touch screen display after the predetermined time; and means for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact.	<SOH> BACKGROUND <EOH>As portable electronic devices become more compact, and the number of functions performed by a given device increases, it has become a significant challenge to design a user interface that allows users to easily interact with a multifunction device. This challenge is particularly significant for handheld portable devices, which have much smaller screens than desktop or laptop computers. This situation is unfortunate because the user interface is the gateway through which users receive not only content but also responses to user actions or behaviors, including user attempts to access a device's features, tools, and functions. Some portable communication devices (e.g., mobile telephones, sometimes called mobile phones, cell phones, cellular telephones, and the like) have resorted to adding more pushbuttons, increasing the density of push buttons, overloading the functions of pushbuttons, or using complex menu systems to allow a user to access, store and manipulate data. These conventional user interfaces often result in complicated key sequences and menu hierarchies that must be memorized by the user. Many conventional user interfaces, such as those that include physical pushbuttons, are also inflexible. This is unfortunate because it may prevent a user interface from being configured and/or adapted by either an application running on the portable device or by users. When coupled with the time consuming requirement to memorize multiple key sequences and menu hierarchies, and the difficulty in activating a desired pushbutton, such inflexibility is frustrating to most users. Furthermore, portable communication devices with touch screens typically include a stylus for manipulating and selecting items on the touch screen itself. The styluses are typically separate from the device and are usually stored in the device within a compartment built to hold the stylus. Because such devices are designed to read the precise pinpoint contact of the stylus (when a user makes a selection on the touch screen with the stylus), making selections on the touch screen of the device without a stylus, for example, with a user's finger, can prove to be somewhat difficult. Accordingly, there is a need for portable multifunction devices with more transparent and intuitive user interfaces for digital (finger) selection and manipulation of selected items on a touch screen display that are easy to use, configure, and/or adapt.	<SOH> SUMMARY <EOH>The above deficiencies and other problems associated with user interfaces for portable devices are reduced or eliminated by the disclosed portable multifunction device. In some embodiments, the device has a touch-sensitive display (also known as a “touch screen”) with a graphical user interface (GUI), one or more processors, memory and one or more modules, programs or sets of instructions stored in the memory for performing multiple functions. In some embodiments, the user interacts with the GUI primarily through finger contacts and gestures on the touch-sensitive display. In some embodiments, the functions may include telephoning, video conferencing, e-mailing, instant messaging, blogging, digital photographing, digital videoing, web browsing, digital music playing, and/or digital video playing. Instructions for performing these functions may be included in a computer program product configured for execution by one or more processors. In accordance with some embodiments, a computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items, detecting a finger contact on a moving-affordance icon, detecting movement of the finger contact on the touch screen display, and in response to detecting the movement of the finger contact, moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with other embodiments, a graphical user interface on a portable multifunction device with a touch screen display includes a list of items on the touch screen display and moving-affordance icons for corresponding items in the list. In response to detecting a finger contact on a moving-affordance icon and detecting movement of the finger contact, the moving-affordance icon and the corresponding item in the list are moved in accordance with the movement of the finger contact. In accordance with other embodiments, a portable multifunction device includes a touch screen display, one or more processors, memory, and one or more programs stored in the memory and configured to be executed by the one or more processors. The one or more programs include instructions for the following: displaying a list of items; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; and moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with yet other embodiments, a computer-program product includes a computer readable storage medium and a computer program mechanism embedded therein. The computer program mechanism includes instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to perform the following steps: display a list of items; detect a finger contact on a moving-affordance icon; detect movement of the finger contact on the touch screen display; and in response to detecting the movement of the finger contact, move the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with other embodiments, a portable multifunction device with a touch screen display includes means for the following: displaying a list of items, wherein at least some of the items have corresponding moving-affordance icons; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; and moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. In accordance with yet other embodiments, a computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items on the touch screen display, detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time, detecting movement of the finger contact on the touch screen display after the predetermined time, and in response to detecting the movement of the finger contact, moving the item in the list in accordance with the movement of the finger contact. In some embodiments, the method may include detecting a break of the finger contact on the touch screen display at a break location on the touch screen display, and in response to detecting the break, placing the item in the list at a position corresponding to the break location on the touch screen display. A graphical user interface on a portable multifunction device with a touch screen display comprises a list of items on the touch screen display. In response to detecting a finger contact on an item, wherein the finger contact is stationary for more than a predetermined time, and detecting movement of the finger contact after the predetermined time, the item is moved in accordance with the movement of the finger contact. A portable multifunction device comprises a touch screen display, one or more processors, memory, and one or more programs. The one or more programs are stored in the memory and configured to be executed by the one or more processors. The one or more programs include instructions for displaying a list of items on the touch screen display; instructions for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; instructions for detecting movement of the finger contact on the touch screen display after the predetermined time; and instructions for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. A computer-program product comprises a computer readable storage medium and a computer program mechanism embedded therein. The computer program mechanism comprises instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to display a list of items on the touch screen display; to detect a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; to detect movement of the finger contact on the touch screen display after the predetermined time; and to move the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. A portable multifunction device with a touch screen display comprises means for displaying a list of items on the touch screen display; means for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; means for detecting movement of the finger contact on the touch screen display after the predetermined time; and means for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. Thus, the invention provides an intuitive, easy-to-use interface for displaying and managing lists on a portable electronic device with a touch screen display. In accordance with the embodiments of the present inventions, various lists may be easily re-arranged or re-ordered with simple finger gestures without the need for other tools or instruments.	RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application Nos. 60/883,808, “System and Method for Managing Lists,” filed Jan. 7, 2007; 60/879,469, “Portable Multifunction Device,” filed Jan. 8, 2007; and 60/879,253, “Portable Multifunction Device,” filed Jan. 7, 2007. All of these applications are incorporated by referenced herein in their entirety. This application is related to the following applications: (1) U.S. patent application Ser. No. 10/188,182, “Touch Pad For Handheld Device,” filed on Jul. 1, 2002; (2) U.S. patent application Ser. No. 10/722,948, “Touch Pad For Handheld Device,” filed on Nov. 25, 2003; (3) U.S. patent application Ser. No. 10/643,256, “Movable Touch Pad With Added Functionality,” filed on Aug. 18, 2003; (4) U.S. patent application Ser. No. 10/654,108, “Ambidextrous Mouse,” filed on Sep. 2, 2003; (5) U.S. patent application Ser. No. 10/840,862, “Multipoint Touchscreen,” filed on May 6, 2004; (6) U.S. patent application Ser. No. 10/903,964, “Gestures For Touch Sensitive Input Devices,” filed on Jul. 30, 2004; (7) U.S. patent application Ser. No. 11/038,590, “Mode-Based Graphical User Interfaces For Touch Sensitive Input Devices” filed on Jan. 18, 2005; (8) U.S. patent application Ser. No. 11/057,050, “Display Actuator,” filed on Feb. 11, 2005; (9) U.S. Provisional Patent Application No. 60/658,777, “Multi-Functional Hand-Held Device,” filed Mar. 4, 2005; and (10) U.S. patent application Ser. No. 11/367,749, “Multi-Functional Hand-Held Device,” filed Mar. 3, 2006; and (11) U.S. Provisional Patent Application No. 60/824,769, “Portable Multifunction Device,” filed Sep. 6, 2006. All of these applications are incorporated by reference herein. TECHNICAL FIELD The disclosed embodiments relate generally to portable electronic devices, and more particularly, to portable devices with digital (finger) selection and manipulation of selected items on a touch screen display. BACKGROUND As portable electronic devices become more compact, and the number of functions performed by a given device increases, it has become a significant challenge to design a user interface that allows users to easily interact with a multifunction device. This challenge is particularly significant for handheld portable devices, which have much smaller screens than desktop or laptop computers. This situation is unfortunate because the user interface is the gateway through which users receive not only content but also responses to user actions or behaviors, including user attempts to access a device's features, tools, and functions. Some portable communication devices (e.g., mobile telephones, sometimes called mobile phones, cell phones, cellular telephones, and the like) have resorted to adding more pushbuttons, increasing the density of push buttons, overloading the functions of pushbuttons, or using complex menu systems to allow a user to access, store and manipulate data. These conventional user interfaces often result in complicated key sequences and menu hierarchies that must be memorized by the user. Many conventional user interfaces, such as those that include physical pushbuttons, are also inflexible. This is unfortunate because it may prevent a user interface from being configured and/or adapted by either an application running on the portable device or by users. When coupled with the time consuming requirement to memorize multiple key sequences and menu hierarchies, and the difficulty in activating a desired pushbutton, such inflexibility is frustrating to most users. Furthermore, portable communication devices with touch screens typically include a stylus for manipulating and selecting items on the touch screen itself. The styluses are typically separate from the device and are usually stored in the device within a compartment built to hold the stylus. Because such devices are designed to read the precise pinpoint contact of the stylus (when a user makes a selection on the touch screen with the stylus), making selections on the touch screen of the device without a stylus, for example, with a user's finger, can prove to be somewhat difficult. Accordingly, there is a need for portable multifunction devices with more transparent and intuitive user interfaces for digital (finger) selection and manipulation of selected items on a touch screen display that are easy to use, configure, and/or adapt. SUMMARY The above deficiencies and other problems associated with user interfaces for portable devices are reduced or eliminated by the disclosed portable multifunction device. In some embodiments, the device has a touch-sensitive display (also known as a “touch screen”) with a graphical user interface (GUI), one or more processors, memory and one or more modules, programs or sets of instructions stored in the memory for performing multiple functions. In some embodiments, the user interacts with the GUI primarily through finger contacts and gestures on the touch-sensitive display. In some embodiments, the functions may include telephoning, video conferencing, e-mailing, instant messaging, blogging, digital photographing, digital videoing, web browsing, digital music playing, and/or digital video playing. Instructions for performing these functions may be included in a computer program product configured for execution by one or more processors. In accordance with some embodiments, a computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items, detecting a finger contact on a moving-affordance icon, detecting movement of the finger contact on the touch screen display, and in response to detecting the movement of the finger contact, moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with other embodiments, a graphical user interface on a portable multifunction device with a touch screen display includes a list of items on the touch screen display and moving-affordance icons for corresponding items in the list. In response to detecting a finger contact on a moving-affordance icon and detecting movement of the finger contact, the moving-affordance icon and the corresponding item in the list are moved in accordance with the movement of the finger contact. In accordance with other embodiments, a portable multifunction device includes a touch screen display, one or more processors, memory, and one or more programs stored in the memory and configured to be executed by the one or more processors. The one or more programs include instructions for the following: displaying a list of items; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; and moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with yet other embodiments, a computer-program product includes a computer readable storage medium and a computer program mechanism embedded therein. The computer program mechanism includes instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to perform the following steps: display a list of items; detect a finger contact on a moving-affordance icon; detect movement of the finger contact on the touch screen display; and in response to detecting the movement of the finger contact, move the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact. In some embodiments, at least some of the items have corresponding moving-affordance icons. In accordance with other embodiments, a portable multifunction device with a touch screen display includes means for the following: displaying a list of items, wherein at least some of the items have corresponding moving-affordance icons; detecting a finger contact on a moving-affordance icon; detecting movement of the finger contact on the touch screen display; and moving the moving-affordance icon and the corresponding item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. In accordance with yet other embodiments, a computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items on the touch screen display, detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time, detecting movement of the finger contact on the touch screen display after the predetermined time, and in response to detecting the movement of the finger contact, moving the item in the list in accordance with the movement of the finger contact. In some embodiments, the method may include detecting a break of the finger contact on the touch screen display at a break location on the touch screen display, and in response to detecting the break, placing the item in the list at a position corresponding to the break location on the touch screen display. A graphical user interface on a portable multifunction device with a touch screen display comprises a list of items on the touch screen display. In response to detecting a finger contact on an item, wherein the finger contact is stationary for more than a predetermined time, and detecting movement of the finger contact after the predetermined time, the item is moved in accordance with the movement of the finger contact. A portable multifunction device comprises a touch screen display, one or more processors, memory, and one or more programs. The one or more programs are stored in the memory and configured to be executed by the one or more processors. The one or more programs include instructions for displaying a list of items on the touch screen display; instructions for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; instructions for detecting movement of the finger contact on the touch screen display after the predetermined time; and instructions for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. A computer-program product comprises a computer readable storage medium and a computer program mechanism embedded therein. The computer program mechanism comprises instructions, which when executed by a portable multifunction device with a touch screen display, cause the device to display a list of items on the touch screen display; to detect a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; to detect movement of the finger contact on the touch screen display after the predetermined time; and to move the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. A portable multifunction device with a touch screen display comprises means for displaying a list of items on the touch screen display; means for detecting a finger contact on an item in the list, wherein the finger contact is stationary for more than a predetermined time; means for detecting movement of the finger contact on the touch screen display after the predetermined time; and means for moving the item in the list in accordance with the movement of the finger contact in response to detecting the movement of the finger contact. Thus, the invention provides an intuitive, easy-to-use interface for displaying and managing lists on a portable electronic device with a touch screen display. In accordance with the embodiments of the present inventions, various lists may be easily re-arranged or re-ordered with simple finger gestures without the need for other tools or instruments. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the aforementioned embodiments of the invention as well as additional embodiments thereof, reference should be made to the Description of Embodiments below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the figures. FIG. 1 is a block diagram illustrating a portable multifunction device with a touch-sensitive display in accordance with some embodiments. FIG. 2 illustrates a portable multifunction device having a touch screen in accordance with some embodiments. FIG. 3 illustrates an exemplary user interface for unlocking a portable electronic device in accordance with some embodiments. FIG. 4 illustrates an exemplary user interface for a menu of applications on a portable multifunction device in accordance with some embodiments. FIGS. 5A-5F illustrate an exemplary user interface for displaying and managing favorite contacts in accordance with some embodiments. FIG. 6A-6C illustrate flow diagrams of processes for displaying and managing lists in accordance with some embodiments DESCRIPTION OF EMBODIMENTS Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments. Embodiments of a portable multifunction device, user interfaces for such devices, and associated processes for using such devices are described. In some embodiments, the device is a portable communications device such as a mobile telephone that also contains other functions, such as PDA and/or music player functions. The user interface may include a physical click wheel in addition to a touch screen or a virtual click wheel displayed on the touch screen. A click wheel is a user-interface device that may provide navigation commands based on an angular displacement of the wheel or a point of contact with the wheel by a user of the device. A click wheel may also be used to provide a user command corresponding to selection of one or more items, for example, when the user of the device presses down on at least a portion of the wheel or the center of the wheel. Alternatively, breaking contact with a click wheel image on a touch screen surface may indicate a user command corresponding to selection. For simplicity, in the discussion that follows, a portable multifunction device that includes a touch screen is used as an exemplary embodiment. It should be understood, however, that some of the user interfaces and associated processes may be applied to other devices, such as personal computers and laptop computers, that may include one or more other physical user-interface devices, such as a physical click wheel, a physical keyboard, a mouse and/or a joystick. The device supports a variety of applications, such as a telephone application, a video conferencing application, an e-mail application, an instant messaging application, a blogging application, a digital camera application, a digital video camera application, a web browsing application, a digital music player application, and/or a digital video player application. The various applications that may be executed on the device may use at least one common physical user-interface device, such as the touch screen. One or more functions of the touch screen as well as corresponding information displayed on the device may be adjusted and/or varied from one application to the next and/or within a respective application. In this way, a common physical architecture (such as the touch screen) of the device may support the variety of applications with user interfaces that are intuitive and transparent. The user interfaces may include one or more soft keyboard embodiments. The soft keyboard embodiments may include standard (QWERTY) and/or non-standard configurations of symbols on the displayed icons of the keyboard, such as those described in U.S. patent application Ser. Nos. 11/459,606, “Keyboards For Portable Electronic Devices,” filed Jul. 24, 2006, and 11/459,615, “Touch Screen Keyboards For Portable Electronic Devices,” filed Jul. 24, 2006, the contents of which are hereby incorporated by reference. The keyboard embodiments may include a reduced number of icons (or soft keys) relative to the number of keys in existing physical keyboards, such as that for a typewriter. This may make it easier for users to select one or more icons in the keyboard, and thus, one or more corresponding symbols. The keyboard embodiments may be adaptive. For example, displayed icons may be modified in accordance with user actions, such as selecting one or more icons and/or one or more corresponding symbols. One or more applications on the portable device may utilize common and/or different keyboard embodiments. Thus, the keyboard embodiment used may be tailored to at least some of the applications. In some embodiments, one or more keyboard embodiments may be tailored to a respective user. For example, based on a word usage history (lexicography, slang, individual usage) of the respective user. Some of the keyboard embodiments may be adjusted to reduce a probability of a user error when selecting one or more icons, and thus one or more symbols, when using the soft keyboard embodiments. Attention is now directed towards embodiments of the device. FIG. 1 is a block diagram illustrating a portable multifunction device 100 with a touch-sensitive display 112 in accordance with some embodiments. The touch-sensitive display 112 is sometimes called a “touch screen” for convenience. The device 100 may include a memory 102 (which may include one or more computer readable storage mediums), a memory controller 122, one or more processing units (CPU's) 120, a peripherals interface 118, RF circuitry 108, audio circuitry 110, a speaker 111, a microphone 113, an input/output (I/O) subsystem 106, other input or control devices 116, and an external port 124. The device 100 may include one or more optical sensors 164. These components may communicate over one or more communication buses or signal lines 103. It should be appreciated that the device 100 is only one example of a portable multifunction device 100, and that the device 100 may have more or fewer components than shown, may combine two or more components, or a may have a different configuration or arrangement of the components. The various components shown in FIG. 1 may be implemented in hardware, software or a combination of both hardware and software, including one or more signal processing and/or application specific integrated circuits. Memory 102 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic disk storage devices, flash memory devices, or other non-volatile solid-state memory devices. Access to memory 102 by other components of the device 100, such as the CPU 120 and the peripherals interface 118, may be controlled by the memory controller 122. The peripherals interface 118 couples the input and output peripherals of the device to the CPU 120 and memory 102. The one or more processors 120 run or execute various software programs and/or sets of instructions stored in memory 102 to perform various functions for the device 100 and to process data. In some embodiments, the peripherals interface 118, the CPU 120, and the memory controller 122 may be implemented on a single chip, such as a chip 104. In some other embodiments, they may be implemented on separate chips. The RF (radio frequency) circuitry 108 receives and sends RF signals, also called electromagnetic signals. The RF circuitry 108 converts electrical signals to/from electromagnetic signals and communicates with communications networks and other communications devices via the electromagnetic signals. The RF circuitry 108 may include well-known circuitry for performing these functions, including but not limited to an antenna system, an RF transceiver, one or more amplifiers, a tuner, one or more oscillators, a digital signal processor, a CODEC chipset, a subscriber identity module (SIM) card, memory, and so forth. The RF circuitry 108 may communicate with networks, such as the Internet, also referred to as the World Wide Web (WWW), an intranet and/or a wireless network, such as a cellular telephone network, a wireless local area network (LAN) and/or a metropolitan area network (MAN), and other devices by wireless communication. The wireless communication may use any of a plurality of communications standards, protocols and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), wideband code division multiple access (W-CDMA), code division multiple access (CDMA), time division multiple access (TDMA), Bluetooth, Wireless Fidelity (Wi-Fi) (e.g., IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and/or IEEE 802.11n), voice over Internet Protocol (VoIP), Wi-MAX, a protocol for email, instant messaging, and/or Short Message Service (SMS)), or any other suitable communication protocol, including communication protocols not yet developed as of the filing date of this document. The audio circuitry 110, the speaker 111, and the microphone 113 provide an audio interface between a user and the device 100. The audio circuitry 110 receives audio data from the peripherals interface 118, converts the audio data to an electrical signal, and transmits the electrical signal to the speaker 111. The speaker 111 converts the electrical signal to human-audible sound waves. The audio circuitry 110 also receives electrical signals converted by the microphone 113 from sound waves. The audio circuitry 110 converts the electrical signal to audio data and transmits the audio data to the peripherals interface 118 for processing. Audio data may be retrieved from and/or transmitted to memory 102 and/or the RF circuitry 108 by the peripherals interface 118. In some embodiments, the audio circuitry 110 also includes a headset jack (not shown). The headset jack provides an interface between the audio circuitry 110 and removable audio input/output peripherals, such as output-only headphones or a headset with both output (e.g., a headphone for one or both ears) and input (e.g., a microphone). The I/O subsystem 106 couples input/output peripherals on the device 100, such as the touch screen 112 and other input/control devices 116, to the peripherals interface 118. The I/O subsystem 106 may include a display controller 156 and one or more input controllers 160 for other input or control devices. The one or more input controllers 160 receive/send electrical signals from/to other input or control devices 116. The other input/control devices 116 may include physical buttons (e.g., push buttons, rocker buttons, etc.), dials, slider switches, joysticks, click wheels, and so forth. In some alternate embodiments, input controller(s) 160 may be coupled to any (or none) of the following: a keyboard, infrared port, USB port, and a pointer device such as a mouse. The one or more buttons (e.g., 208, FIG. 2) may include an up/down button for volume control of the speaker 111 and/or the microphone 113. The one or more buttons may include a push button (e.g., 206, FIG. 2). A quick press of the push button may disengage a lock of the touch screen 112 or begin a process that uses gestures on the touch screen to unlock the device, as described in U.S. patent application Ser. No. 11/322,549, “Unlocking a Device by Performing Gestures on an Unlock Image,” filed Dec. 23, 2005, which is hereby incorporated by reference. A longer press of the push button (e.g., 206) may turn power to the device 100 on or off. The user may be able to customize a functionality of one or more of the buttons. The touch screen 112 is used to implement virtual or soft buttons and one or more soft keyboards. The touch-sensitive touch screen 112 provides an input interface and an output interface between the device and a user. The display controller 156 receives and/or sends electrical signals from/to the touch screen 112. The touch screen 112 displays visual output to the user. The visual output may include graphics, text, icons, video, and any combination thereof (collectively termed “graphics”). In some embodiments, some or all of the visual output may correspond to user-interface objects, further details of which are described below. A touch screen 112 has a touch-sensitive surface, sensor or set of sensors that accepts input from the user based on haptic and/or tactile contact. The touch screen 112 and the display controller 156 (along with any associated modules and/or sets of instructions in memory 102) detect contact (and any movement or breaking of the contact) on the touch screen 112 and converts the detected contact into interaction with user-interface objects (e.g., one or more soft keys, icons, web pages or images) that are displayed on the touch screen. In an exemplary embodiment, a point of contact between a touch screen 112 and the user corresponds to a finger of the user. The touch screen 112 may use LCD (liquid crystal display) technology, or LPD (light emitting polymer display) technology, although other display technologies may be used in other embodiments. The touch screen 112 and the display controller 156 may detect contact and any movement or breaking thereof using any of a plurality of touch sensing technologies now known or later developed, including but not limited to capacitive, resistive, infrared, and surface acoustic wave technologies, as well as other proximity sensor arrays or other elements for determining one or more points of contact with a touch screen 112. A touch-sensitive display in some embodiments of the touch screen 112 may be analogous to the multi-touch sensitive tablets described in the following U.S. patents: U.S. Pat. No. 6,323,846 (Westerman et al.), U.S. Pat. No. 6,570,557 (Westerman et al.), and/or U.S. Pat. No. 6,677,932 (Westerman), and/or U.S. Patent Publication 2002/0015024A1, each of which is hereby incorporated by reference. However, a touch screen 112 displays visual output from the portable device 100, whereas touch sensitive tablets do not provide visual output. The touch screen 112 may have a resolution in excess of 100 dpi. In an exemplary embodiment, the touch screen in the display system has a resolution of approximately 168 dpi. The user may make contact with the touch screen 112 using any suitable object or appendage, such as a stylus, a finger, and so forth. In some embodiments, the user interface is designed to work primarily with finger-based contacts and gestures, which are much less precise than stylus-based input due to the larger area of contact of a finger on the touch screen. In some embodiments, the device translates the rough finger-based input into a precise pointer/cursor position or command for performing the actions desired by the user. A touch-sensitive display in some embodiments of the touch screen 112 may be as described in the following applications: (1) U.S. patent application Ser. No. 11/381,313, “Multipoint Touch Surface Controller,” filed on May 2, 2006; (2) U.S. patent application Ser. No. 10/840,862, “Multipoint Touchscreen,” filed on May 6, 2004; (3) U.S. patent application Ser. No. 10/903,964, “Gestures For Touch Sensitive Input Devices,” filed on Jul. 30, 2004; (4) U.S. patent application Ser. No. 11/048,264, “Gestures For Touch Sensitive Input Devices,” filed on Jan. 31, 2005; (5) U.S. patent application Ser. No. 11/038,590, “Mode-Based Graphical User Interfaces For Touch Sensitive Input Devices,” filed on Jan. 18, 2005; (6) U.S. patent application Ser. No. 11/228,758, “Virtual Input Device Placement On A Touch Screen User Interface,” filed on Sep. 16, 2005; (7) U.S. patent application Ser. No. 11/228,700, “Operation Of A Computer With A Touch Screen Interface,” filed on Sep. 16, 2005; (8) U.S. patent application Ser. No. 11/228,737, “Activating Virtual Keys Of A Touch-Screen Virtual Keyboard,” filed on Sep. 16, 2005; and (9) U.S. patent application Ser. No. 11/367,749, “Multi-Functional Hand-Held Device,” filed on Mar. 3, 2006. All of these applications are incorporated by reference herein. In some embodiments, in addition to the touch screen, the device 100 may include a touchpad (not shown) for activating or deactivating particular functions. In some embodiments, the touchpad is a touch-sensitive area of the device that, unlike the touch screen, does not display visual output. The touchpad may be a touch-sensitive surface that is separate from the touch screen 112 or an extension of the touch-sensitive surface formed by the touch screen. In some embodiments, the device 100 may include a physical or virtual click wheel as an input control device 116. A user may navigate among and interact with one or more graphical objects (henceforth referred to as icons) displayed in the touch screen 112 by rotating the click wheel or by moving a point of contact with the click wheel (e.g., where the amount of movement of the point of contact is measured by its angular displacement with respect to a center point of the click wheel). The click wheel may also be used to select one or more of the displayed icons. For example, the user may press down on at least a portion of the click wheel or an associated button. User commands and navigation commands provided by the user via the click wheel may be processed by an input controller 160 as well as one or more of the modules and/or sets of instructions in memory 102. For a virtual click wheel, the click wheel and click wheel controller may be part of the touch screen 112 and the display controller 156, respectively. For a virtual click wheel, the click wheel may be either an opaque or semitransparent object that appears and disappears on the touch screen display in response to user interaction with the device. In some embodiments, a virtual click wheel is displayed on the touch screen of a portable multifunction device and operated by user contact with the touch screen. The device 100 also includes a power system 162 for powering the various components. The power system 162 may include a power management system, one or more power sources (e.g., battery, alternating current (AC)), a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator (e.g., a light-emitting diode (LED)) and any other components associated with the generation, management and distribution of power in portable devices. The device 100 may also include one or more optical sensors 164. FIG. 1 shows an optical sensor coupled to an optical sensor controller 158 in I/O subsystem 106. The optical sensor 164 may include charge-coupled device (CCD) or complementary metal-oxide semiconductor (CMOS) phototransistors. The optical sensor 164 receives light from the environment, projected through one or more lens, and converts the light to data representing an image. In conjunction with an imaging module 143 (also called a camera module), the optical sensor 164 may capture still images or video. In some embodiments, an optical sensor is located on the back of the device 100, opposite the touch screen display 112 on the front of the device, so that the touch screen display may be used as a viewfinder for either still and/or video image acquisition. In some embodiments, an optical sensor is located on the front of the device so that the user's image may be obtained for videoconferencing while the user views the other video conference participants on the touch screen display. In some embodiments, the position of the optical sensor 164 can be changed by the user (e.g., by rotating the lens and the sensor in the device housing) so that a single optical sensor 164 may be used along with the touch screen display for both video conferencing and still and/or video image acquisition. The device 100 may also include one or more proximity sensors 166. FIG. 1 shows a proximity sensor 166 coupled to the peripherals interface 118. Alternately, the proximity sensor 166 may be coupled to an input controller 160 in the I/O subsystem 106. The proximity sensor 166 may perform as described in U.S. patent application Ser. Nos. 11/241,839, “Proximity Detector In Handheld Device,” filed Sep. 30, 2005, and 11/240,788, “Proximity Detector In Handheld Device,” filed Sep. 30, 2005, which are hereby incorporated by reference. In some embodiments, the proximity sensor turns off and disables the touch screen 112 when the multifunction device is placed near the user's ear (e.g., when the user is making a phone call). In some embodiments, the proximity sensor keeps the screen off when the device is in the user's pocket, purse, or other dark area to prevent unnecessary battery drainage when the device is a locked state. In some embodiments, the software components stored in memory 102 may include an operating system 126, a communication module (or set of instructions) 128, a contact/motion module (or set of instructions) 130, a graphics module (or set of instructions) 132, a text input module (or set of instructions) 134, a Global Positioning System (GPS) module (or set of instructions) 135, and applications (or set of instructions) 136. The operating system 126 (e.g., Darwin, RTXC, LINUX, UNIX, OS X, WINDOWS, or an embedded operating system such as VxWorks) includes various software components and/or drivers for controlling and managing general system tasks (e.g., memory management, storage device control, power management, etc.) and facilitates communication between various hardware and software components. The communication module 128 facilitates communication with other devices over one or more external ports 124 and also includes various software components for handling data received by the RF circuitry 108 and/or the external port 124. The external port 124 (e.g., Universal Serial Bus (USB), FIREWIRE, etc.) is adapted for coupling directly to other devices or indirectly over a network (e.g., the Internet, wireless LAN, etc.). In some embodiments, the external port is a multi-pin (e.g., 30-pin) connector that is the same as, or similar to and/or compatible with the 30-pin connector used on iPod (trademark of Apple Computer, Inc.) devices. The contact/motion module 130 may detect contact with the touch screen 112 (in conjunction with the display controller 156) and other touch sensitive devices (e.g., a touchpad or physical click wheel). The contact/motion module 130 includes various software components for performing various operations related to detection of contact, such as determining if contact has occurred, determining if there is movement of the contact and tracking the movement across the touch screen 112, and determining if the contact has been broken (i.e., if the contact has ceased). Determining movement of the point of contact may include determining speed (magnitude), velocity (magnitude and direction), and/or an acceleration (a change in magnitude and/or direction) of the point of contact. These operations may be applied to single contacts (e.g., one finger contacts) or to multiple simultaneous contacts (e.g., “multitouch”/multiple finger contacts). In some embodiments, the contact/motion module 130 and the display controller 156 also detects contact on a touchpad. In some embodiments, the contact/motion module 130 and the controller 160 detects contact on a click wheel 116. The graphics module 132 includes various known software components for rendering and displaying graphics on the touch screen 112, including components for changing the intensity of graphics that are displayed. As used herein, the term “graphics” includes any object that can be displayed to a user, including without limitation text, web pages, icons (such as user-interface objects including soft keys), digital images, videos, animations and the like. The text input module 134, which may be a component of graphics module 132, provides soft keyboards for entering text in various applications (e.g., contacts 137, e-mail 140, IM 141, blogging 142, browser 147, and any other application that needs text input). The GPS module 135 determines the location of the device and provides this information for use in various applications (e.g., to telephone module 138 for use in location-based dialing, to camera module 143 and/or blogging module 142 as picture/video metadata, and to applications that provide location-based services such as weather widgets, local yellow page widgets, and map/navigation widgets). The applications 136 may include the following modules (or sets of instructions), or a subset or superset thereof: a contacts module 137 (which manages an address book 172 or contact list, as well as a list of favorite contacts 174); a telephone module 138; a video conferencing module 139; an e-mail client module 140; an instant messaging (IM) module 141; a blogging module 142; a camera module 143 for still and/or video images; an image management module 144; a video player module 145; a music player module 146; a browser module 147; a calendar module 148; widget modules 149, which may include weather widget 149-1, stocks widget 149-2, calculator widget 149-3, alarm clock widget 149-4, dictionary widget 149-5, and other widgets obtained by the user, as well as user-created widgets 149-6; widget creator module 150 for making user-created widgets 149-6; and/or search module 151. Examples of other applications 136 that may be stored in memory 102 include memo pad and other word processing applications, JAVA-enabled applications, encryption, digital rights management, voice recognition, and voice replication. In conjunction with touch screen 112, display controller 156, contact module 130, graphics module 132, and text input module 134, the contacts module 137 may be used to manage an address book 172 or contact list, including: adding name(s) to the address book 172; deleting name(s) from the address book 172; associating telephone number(s), e-mail address(es), physical address(es) or other information with a name; associating an image with a name; categorizing and sorting names; providing telephone numbers or e-mail addresses to initiate and/or facilitate communications by telephone 138, video conference 139, e-mail 140, or IM 141; and so forth. Embodiments of user interfaces and associated processes using contacts module 137 are described further below. In conjunction with RF circuitry 108, audio circuitry 110, speaker 111, microphone 113, touch screen 112, display controller 156, contact module 130, graphics module 132, and text input module 134, the telephone module 138 may be used to enter a sequence of characters corresponding to a telephone number, access one or more telephone numbers in the address book 172, modify a telephone number that has been entered, dial a respective telephone number, conduct a conversation and disconnect or hang up when the conversation is completed. As noted above, the wireless communication may use any of a plurality of communications standards, protocols and technologies. In conjunction with RF circuitry 108, audio circuitry 110, speaker 111, microphone 113, touch screen 112, display controller 156, optical sensor 164, optical sensor controller 158, contact module 130, graphics module 132, text input module 134, contact list 137, and telephone module 138, the videoconferencing module 139 may be used to initiate, conduct, and terminate a video conference between a user and one or more other participants. In conjunction with RF circuitry 108, touch screen 112, display controller 156, contact module 130, graphics module 132, and text input module 134, the e-mail client module 140 may be used to create, send, receive, and manage e-mail. In conjunction with image management module 144, the e-mail module 140 makes it very easy to create and send e-mails with still or video images taken with camera module 143. In conjunction with RF circuitry 108, touch screen 112, display controller 156, contact module 130, graphics module 132, and text input module 134, the instant messaging module 141 may be used to enter a sequence of characters corresponding to an instant message, to modify previously entered characters, to transmit a respective instant message (for example, using a Short Message Service (SMS) or Multimedia Message Service (MMS) protocol), to receive instant messages and to view received instant messages. In some embodiments, transmitted and/or received instant messages may include graphics, photos, audio files, video files and/or other attachments as are supported in a MMS and/or an Enhanced Messaging Service (EMS). In conjunction with RF circuitry 108, touch screen 112, display controller 156, contact module 130, graphics module 132, text input module 134, image management module 144, and browsing module 147, the blogging module 142 may be used to send text, still images, video, and/or other graphics to a blog (e.g., the user's blog). In conjunction with touch screen 112, display controller 156, optical sensor(s) 164, optical sensor controller 158, contact module 130, graphics module 132, and image management module 144, the camera module 143 may be used to capture still images or video (including a video stream) and store them into memory 102, modify characteristics of a still image or video, or delete a still image or video from memory 102. In conjunction with touch screen 112, display controller 156, contact module 130, graphics module 132, text input module 134, and camera module 143, the image management module 144 may be used to arrange, modify or otherwise manipulate, label, delete, present (e.g., in a digital slide show or album), and store still and/or video images. In conjunction with touch screen 112, display controller 156, contact module 130, graphics module 132, audio circuitry 110, and speaker 111, the video player module 145 may be used to display, present or otherwise play back videos (e.g., on the touch screen or on an external, connected display via external port 124). In conjunction with touch screen 112, display system controller 156, contact module 130, graphics module 132, audio circuitry 110, speaker 111, RF circuitry 108, and browser module 147, the music player module 146 allows the user to download and play back recorded music and other sound files stored in one or more file formats, such as MP3 or AAC files. In some embodiments, the device 100 may include the functionality of an MP3 player, such as an iPod (trademark of Apple Computer, Inc.). In conjunction with RF circuitry 108, touch screen 112, display system controller 156, contact module 130, graphics module 132, and text input module 134, the browser module 147 may be used to browse the Internet, including searching, linking to, receiving, and displaying web pages or portions thereof, as well as attachments and other files linked to web pages. In conjunction with RF circuitry 108, touch screen 112, display system controller 156, contact module 130, graphics module 132, text input module 134, e-mail module 140, and browser module 147, the calendar module 148 may be used to create, display, modify, and store calendars and data associated with calendars (e.g., calendar entries, to do lists, etc.). In conjunction with RF circuitry 108, touch screen 112, display system controller 156, contact module 130, graphics module 132, text input module 134, and browser module 147, the widget modules 149 are mini-applications that may be downloaded and used by a user (e.g., weather widget 149-1, stocks widget 149-2, calculator widget 149-3, alarm clock widget 149-4, and dictionary widget 149-5) or created by the user (e.g., user-created widget 149-6). In some embodiments, a widget includes an HTML (Hypertext Markup Language) file, a CSS (Cascading Style Sheets) file, and a JavaScript file. In some embodiments, a widget includes an XML (Extensible Markup Language) file and a JavaScript file (e.g., Yahoo! Widgets). In conjunction with RF circuitry 108, touch screen 112, display system controller 156, contact module 130, graphics module 132, text input module 134, and browser module 147, the widget creator module 150 may be used by a user to create widgets (e.g., turning a user-specified portion of a web page into a widget). In conjunction with touch screen 112, display system controller 156, contact module 130, graphics module 132, and text input module 134, the search module 151 may be used to search for text, music, sound, image, video, and/or other files in memory 102 that match one or more search criteria (e.g., one or more user-specified search terms). Each of the above identified modules and applications correspond to a set of instructions for performing one or more functions described above. These modules (i.e., sets of instructions) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise re-arranged in various embodiments. In some embodiments, memory 102 may store a subset of the modules and data structures identified above. Furthermore, memory 102 may store additional modules and data structures not described above. In some embodiments, the device 100 is a device where operation of a predefined set of functions on the device is performed exclusively through a touch screen 112 and/or a touchpad. By using a touch screen and/or a touchpad as the primary input/control device for operation of the device 100, the number of physical input/control devices (such as push buttons, dials, and the like) on the device 100 may be reduced. The predefined set of functions that may be performed exclusively through a touch screen and/or a touchpad include navigation between user interfaces. In some embodiments, the touchpad, when touched by the user, navigates the device 100 to a main, home, or root menu from any user interface that may be displayed on the device 100. In such embodiments, the touchpad may be referred to as a “menu button.” In some other embodiments, the menu button may be a physical push button or other physical input/control device instead of a touchpad. FIG. 2 illustrates a portable multifunction device 100 having a touch screen 112 in accordance with some embodiments. The touch screen may display one or more graphics. In this embodiment, as well as others described below, a user may select one or more of the graphics by making contact or touching the graphics, for example, with one or more fingers 202 (not drawn to scale in the figure). In some embodiments, selection of one or more graphics occurs when the user breaks contact with the one or more graphics. In some embodiments, the contact may include a gesture, such as one or more taps, one or more swipes (from left to right, right to left, upward and/or downward) and/or a rolling of a finger (from right to left, left to right, upward and/or downward) that has made contact with the device 100. In some embodiments, inadvertent contact with a graphic may not select the graphic. For example, a swipe gesture that sweeps over an application icon may not select the corresponding application when the gesture corresponding to selection is a tap. The device 100 may also include one or more physical buttons, such as “home” or menu button 204. As described previously, the menu button 204 may be used to navigate to any application 136 in a set of applications that may be executed on the device 100. Alternatively, in some embodiments, the menu button is implemented as a soft key in a GUI in touch screen 112. In one embodiment, the device 100 includes a touch screen 112, a menu button 204, a push button 206 for powering the device on/off and locking the device, and volume adjustment button(s) 208. The push button 206 may be used to turn the power on/off on the device by depressing the button and holding the button in the depressed state for a predefined time interval; to lock the device by depressing the button and releasing the button before the predefined time interval has elapsed; and/or to unlock the device or initiate an unlock process. In an alternative embodiment, the device 100 also may accept verbal input for activation or deactivation of some functions through the microphone 113. Attention is now directed towards embodiments of user interfaces (“UT”) and associated processes that may be implemented on a portable multifunction device 100. FIG. 3 illustrates an exemplary user interface for unlocking a portable electronic device in accordance with some embodiments. In some embodiments, user interface 300 includes the following elements, or a subset or superset thereof: Unlock image 302 that is moved with a finger gesture to unlock the device; Arrow 304 that provides a visual cue to the unlock gesture; Channel 306 that provides additional cues to the unlock gesture; Time 308; Day 310; Date 312; and Wallpaper image 314. In some embodiments, the device detects contact with the touch-sensitive display (e.g., a user's finger making contact on or near the unlock image 302) while the device is in a user-interface lock state. The device moves the unlock image 302 in accordance with the contact. The device transitions to a user-interface unlock state if the detected contact corresponds to a predefined gesture, such as moving the unlock image across channel 306. Conversely, the device maintains the user-interface lock state if the detected contact does not correspond to the predefined gesture. As noted above, processes that use gestures on the touch screen to unlock the device are described in U.S. patent application Ser. No. 11/322,549, “Unlocking a Device by Performing Gestures on an Unlock Image,” filed Dec. 23, 2005, which is hereby incorporated by reference. FIG. 4 illustrates an exemplary user interface for a menu of applications on a portable multifunction device in accordance with some embodiments. In some embodiments, user interface 400 includes the following elements, or a subset or superset thereof: Signal strength indicator 402 for wireless communication; Time 404; Battery status indicator 406; Tray 408 with icons for frequently used applications, such as: Phone 138; E-mail client 140, which may include an indicator 410 of the number of unread e-mails; Browser 147; and Music player 146; and Icons for other applications, such as: IM 141; Image management 144; Camera 143; Video player 145; Weather 149-1; Stocks 149-2; Blog 142; Calendar 148; Calculator 149-3; Alarm clock 149-4; Dictionary 149-5; and User-created widget 149-6. In some embodiments, UI 400 displays all of the available applications 136 on one screen so that there is no need to scroll through a list of applications (e.g., via a scroll bar). In some embodiments, as the number of applications increase, the icons corresponding to the applications may decrease in size so that all applications may be displayed on a single screen without scrolling. In some embodiments, having all applications on one screen and a menu button enables a user to access any desired application with at most two inputs, such as activating the menu button 204 and then activating the desired application (e.g., by a tap or other finger gesture on the icon corresponding to the application). In some embodiments, UI 400 provides integrated access to both widget-based applications and non-widget-based applications. In some embodiments, all of the widgets, whether user-created or not, are displayed in UI 400. In other embodiments, activating the icon for user-created widget 149-6 may lead to another UT (not shown) that contains the user-created widgets or icons corresponding to the user-created widgets. In some embodiments, a user may rearrange the icons in UI 400, e.g., using processes described in U.S. patent application Ser. No. 11/459,602, “Portable Electronic Device With Interface Reconfiguration Mode,” filed Jul. 24, 2006, which is hereby incorporated by reference. For example, a user may move application icons in and out of tray 408 using finger gestures. In some embodiments, UI 400 includes a gauge (not shown) that displays an updated account usage metric for an account associated with usage of the device (e.g., a cellular phone account), as described in U.S. patent application Ser. No. 11/322,552, “Account Information Display For Portable Communication Device,” filed Dec. 23, 2005, which is hereby incorporated by reference. FIGS. 5A-5F illustrate an exemplary user interface for displaying and managing favorite contacts on portable multifunction device 100 in accordance with some embodiments. UI 2700A displays an exemplary list of favorites, corresponding to favorites list 174. It is noted that the terms “favorite” and “favorites” are sometimes used as a short hand for “favorite contact” and “favorite contacts.” In some embodiments, each row 2720 in the list that corresponds to a favorite includes the name 2702 of the favorite, the type of phone number 2704 for the favorite that will be called, an additional information icon 2706, and an edit initiation icon 2710. In some embodiments, in response to the user activating icon 2706 for a particular favorite (e.g., by a finger tap on the icon), the touch screen displays the corresponding contact list entry for that favorite. In some embodiments, in response to a user tap or other predefined gesture elsewhere (i.e., a tap or gesture other than on icon 2702) in the row corresponding to a particular favorite, the phone module dials the corresponding phone number 2704 for that particular favorite. When a user makes a finger gesture on the edit initiation icon 2710, a moving-affordance icon 2722 is displayed on the touch screen display as seen in FIGS. 5B-5F. In some embodiments, in response to the user activating add favorite icon 2708 (e.g., by a finger tap on the icon), the device displays the user's contact list, from which the user selects the contact list entry for a new favorite and a phone number in the entry for the new favorite. In response to the user activating the edit initiation icon 2710 (e.g., by a finger tap on the icon), the touch screen displays a delete icon 2712 next to the favorites (e.g., UI 2700B, FIG. 5B). If a user activates a delete icon (e.g., by tapping it with a finger), the icon may rotate 90 degrees (e.g., 2714, FIG. 5C) or otherwise change its appearance and/or a second icon may appear (e.g., remove icon 2716, FIG. 5C). If the user activates the second icon, the corresponding favorite is deleted. A deletion process that requires multiple gestures by the user on different parts of the touch screen (e.g., delete icon 2714 and remove icon 2716 are on opposite sides of the touch screen in UI 2700C) greatly reduces the chance that a user will accidentally delete a favorite or other similar item. The user activates the done icon (also called the edit completion icon) 2718 (e.g., by tapping on it with a finger) when the user has finished deleting favorites and the device returns to UI 2700A. In some embodiments, as mentioned above, when a user performs a finger gesture on the edit initiation icon 2710, the touch screen display displays a moving-affordance icon 2722 as shown in FIGS. 5B-5F. After the moving-affordance icon 2722 is displayed on the touch screen display, the user may then execute a finger contact 2724 on the moving-affordance icon 2722. As the user's finger remains on the moving-affordance icon 2722, the user may move the corresponding row 2721 vertically within the list. As shown in FIG. 5D-5F, the user may use his finger to move the corresponding row 2721 anywhere within the list and re-arrange the order of items of that list. Upon detection of the initial finger contact 2724 and movement through the list, the corresponding row separates from the list as shown in FIG. 5D. As the user keeps his finger on the moving-affordance icon 2722 and moves the corresponding row 2721 through the list, the other items in the list may also move to accommodate the row 2721 that is being moved (as shown in FIG. 5E). In some embodiments, as shown in FIG. 5F, as the row 2721 that is being moved reaches a break location 2726, the corresponding item is placed in the list at a position corresponding to the break location 2726 on the touch screen display. In some embodiments, a user may perform a finger gesture on an edit completion icon 2718. Upon detection of the finger gesture on the edit completion icon 2718, the moving-affordance icon 2722 ceases to be displayed on the touch screen display. In some embodiments, a user may move the item within the list by performing a finger contact anywhere within a row 2720 for at least a predetermined time. For example, if a user performs a finger contact that is detected anywhere within the row 2720 of the corresponding item that they want to move for at least a predetermined time, that item becomes movable within the list. In some embodiments, the predetermined time may be several seconds long and may range from one second to five seconds. Allowing movement of an item in the list upon detection of a finger contact for at least a predetermined time permits the list to be rearranged without use of an edit initiation icon and a moving-affordance icon. The above figures show an exemplary list that may be re-ordered. In some other embodiments, other lists that may be re-ordered as described above may include a playlist of songs, a list of phone numbers, a list of pictures, a list of files, a list of photo albums, a list of photographs, a list of videos, a list of software applications, or any other type of list not having a predetermined order. FIG. 6A illustrates a flow diagram of process 600 for managing lists in accordance with some embodiments. In some embodiments, process 600 may be performed on a portable multifunction device (e.g., device 100) with a touch screen display (e.g., display 112). The portable multifunction device displays a list of items on its touch screen display (602). In some embodiments, the list is a playlist of songs, a list of phone numbers, a list of pictures, a list of files, a list of photo albums, a list of photographs, a list of videos, or a list of software applications. A finger gesture (e.g., a tap gesture) is detected on an edit initiation icon (e.g., icon 2710) on the touch screen display (604), and the device responds by displaying moving-affordance icons (e.g., icons 2722) for corresponding items in the list (606). If a finger contact (e.g., finger contact 2724) on a respective moving-affordance icon is detected (608) and movement of the finger contact on the touch screen display is also detected (610), the device responds by moving the moving-affordance icon and the corresponding item (i.e., the user-selected item) in the list in accordance with the movement of the finger contact (612). In some embodiments, while the user-selected item is moving over a second item, the second item simultaneously moves in the list in a direction opposite movement of the user selected item. When a break of the finger contact on the touch screen display at a break location (e.g., break location 2726) on the touch screen display is detected (614), the corresponding item in the list is placed at a position corresponding to the break location on the touch screen display in response to detecting the break (616). In some embodiments, if a finger gesture on an edit completion icon (e.g., done icon 2718) is detected (618), the device responds by ceasing display of the moving-affordance icon (620). FIG. 6B illustrates a flow diagram of process 630 for managing lists in accordance with some embodiments. In some embodiments, process 630 may be performed on a portable multifunction device (e.g., device 100) with a touch screen display (e.g., display 112). The portable multifunction device displays a list of items on its touch screen display (632). In some embodiments, at least some of the items on the list have corresponding moving-affordance icons (e.g., icons 2722). When a finger contact (e.g., 2724) on a respective moving-affordance icon is detected (634) and movement of the finger contact on the touch screen display is also detected (636), the device responds by moving the corresponding item in the list in accordance with the movement of the finger contact (638). In some embodiments, where at least some of the items on the list have corresponding moving-affordance icons, the device responds by moving the moving-affordance icon and the corresponding item in the list. FIG. 6C illustrates a flow diagram of process 640 for managing lists in accordance with some embodiments. In some embodiments, process 640 may be performed on a portable multifunction device (e.g., device 100) with a touch screen display (e.g., device 112). The portable multifunction device displays a list of items on its touch screen display (642). In some embodiments, the list of items is a playlist of songs, a list of phone numbers, a list of pictures, a list of files, a list of photo albums, a list of photographs, a list of videos, or a list of software applications. When a finger contact on an item in the list (e.g., a finger contact anywhere within a row 2720) is stationary for more than a predetermined time (644) and movement of the finger contact after the predetermined time is detected (646), the device responds by moving the item in the list in accordance with the movement of the finger contact (648). In some embodiments, the predetermined time may last up to several seconds and may range from one second, in some embodiments, to five seconds in other embodiments. In some embodiments, while the finger-contacted item in the list is moving over a second item, the second item simultaneously moves in the list in a direction opposite movement of the finger-contacted item. In some embodiments, a break of the finger contact on the touch screen display at a break location may be detected (650), and the item is placed in the list at a position corresponding to the break location on the touch screen display (652). The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.	G	60G06	161G06F	30	41
11671429	US20070192423A1-20070816	DOCUMENT REMINDER SYSTEM	ACCEPTED	20070801	20070816	[]	G06F1516	["G06F1516", "G06F1700", "G06F3048"]	8365080	20070205	20130129	715	739000	61650.0	NGUYEN	CAO	[{"inventor_name_last": "Karlson", "inventor_name_first": "Bruce", "inventor_city": "Mission", "inventor_state": "KS", "inventor_country": "US"}]	A document reminder system is provided. The system provides a user-friendly interface to a user's existing document management, email, calendar and other systems in order to ensure that an appropriate user is notified when action should be taken on a specific document, and also provides notation to the user indicating the appropriate course of action to be taken. The system provides a calendaring feature where a supervisor or manager can determine the workload of a group of workers for an upcoming time period. The system provides an easily accessible and traceable database of information pertaining to a document, a client name, a client matter number, a document type, or other customizable fields in order for a user to search and sort the information for their own use.	1. A document reminder system comprising: a connection with a document management system; a connection with a messaging system; and a database for storing reminder information including information relating to said document management system and said messaging system. 2. The system as claimed in claim 1 wherein said reminder information comprises at least one reminder message that will be transmitted through said messaging system. 3. The system as claimed in claim 1 wherein said reminder information comprises an action to be taken at a certain time regarding a document stored in said document management system. 4. The system as claimed in claim 3 wherein a copy of said document is attached to a reminder message. 5. The system as claimed in claim 3 wherein a reference link to said document is attached to a reminder message. 6. The system as claimed in claim 2 wherein said reminder information includes a selectable time and date for sending said reminder message. 7. The system as claimed in claim 2 wherein said reminder information includes a plurality of options to include information with said reminder message. 8. The system as claimed in claim 7 wherein one said option includes the ability to attach a checklist to said reminder message. 9. The system as claimed in claim 7 wherein one said option includes the ability to attach at least one form document to said reminder message. 10. The system as claimed in claim 3 further comprising a calendar displaying said reminder information. 11. The system as claimed in claim 10 wherein said calendar includes said reminder information for multiple users simultaneously for a specified time. 12. The system as claimed in claim 11 wherein said calendar includes an active link to view a reminder message in its entirety. 13. The system as claimed in claim 1 further including a report generator, wherein reminder information is sortable by a plurality of fields. 14. A document reminder system comprising: a document management system; a messaging system; and a database for storing reminder information including information relating to said document management system and said messaging system; wherein said reminder information further includes an action to be taken at a certain time regarding a document stored in said document management system. 15. The system as claimed in claim 14 wherein said action comprises sending a reminder message via said messaging system. 16. A method of managing documents comprising the steps of: storing a document in a document management system; storing information regarding said document in a document reminder system, wherein said information includes reminder information for an action to be taken at a certain time relating to the document; generating a reminder message at the time the action is to be taken, wherein the reminder message includes information regarding the document. 17. The method as claimed in claim 16 wherein said information regarding the document comprises a link to the document in the document management system. 18. The method as claimed in claim 16 wherein said information regarding the document comprises a copy of the document from the document management system.	<SOH> BACKGROUND OF THE INVENTION <EOH>In a modern business environment, proper management of documents and relevant dates is essential to success. A key problem in the management of documents and dates is the tracking of documents through time, whether because of a need to follow up on a document at a given time, generate periodic reports, or perform periodic document review such as that required by Sarbanes Oxley. Numerous document management systems are known in the art. These systems generally allow a user to identify a document using a variety of fields that are then saved in a database that can be searched when a user wishes to retrieve documents pertaining to a particular client, a particular matter, or even a general subject matter. Documents can also be searched by author, date of creation, or any other database field utilized by these systems. The problem with each of these systems, however, is that they require external functionality in order to indicate to a user when a certain document should be reviewed, or when a response to a document is expected, document management systems themselves treating documents as inert and having no significance other than as historical records. Contracts, demand letters, licenses, leases, and other business documents are not inert. They are the engines of business and govern numerous business events such as renewals, responses, elections, options, reviews, and cancellations. For example, in business, it would be useful to have a system that could notify a user that a key date is approaching, so that the user may then search for relevant documents in the document management system and act accordingly. Using conventional technology, this, of course, requires that the pertinent information be entered into a docketing or calendaring system so that the user will be notified of a need at a later date. The step of entering the needed information into a docketing or calendaring system takes time and requires significant labor on the part of workers in an organization. Moreover tedious data entry is redundant and is subject to human error. It is well known that only a fraction of dates are logged because of this time and resource utilization factor and because of the disconnection between and complexity of multiple systems, e.g., calendaring (tickler), document management, and messaging or notification. Therefore, it would be beneficial to attach a reminder to a document while the document is being read in a manner that only takes a few seconds and that automatically captures data already stored about the document, thus maximizing the possibility the date is captured. Moreover, even if the relevant data is entered, either enormous quantities of information must be entered, or the information will be without meaningful context such that the user still has to look up, retrieve, and review the documents relevant to the event in question. Therefore, it would be beneficial to provide a document reminder system that seamlessly interfaces with a user's existing document management system, email or messaging system, calendar (tickler) system and other software, to provide a simple and effective means of generating reminders, prompting users, tracking responses to the reminders (if any), and furnishing meaningful information about the event, the document, and the parties, all within a matter of seconds. Further, it would be beneficial to provide a system that furnishes quick access to the document itself, without a need to search the document management system. It would be further desirable to have a system that not only automatically identifies the relevant document, but also furnishes relevant information to refresh the user's recollection or points to the specific section within the document that has triggered the reminder. Having the reminder directly connected to the document permits the user quickly and easily to take the appropriate action without the need for separate entry of data. For example, a contract may specify that notice of renewal must be sent within a prescribed period of time prior to the expiration of the term of that contract. Knowing that is helpful, but to whom is the notice to be sent? What is the proper address for notice? Must the notice be sent by Certified Mail or other prescribed means? How are specific terms used in this example notice provision defined? Years may pass before the date comes due. In addition, if the date is in a personal calendar, there is always the chance when the person goes looking for the document that the person uses the wrong document or version of the document. By being linked into the document itself, each of these questions can be answered in seconds, all without the need for extensive data entry in a separate database system and without fear that the wrong document or wrong version will be retrieved. When users are responsible for an action item for a document, for example a renewal date, they will often put that renewal date in the user's personal calendar system, either an electronic or paper calendar. When the users are looking at their calendars, they are able to determine what their workload for an upcoming time period is and what action items need to be taken; however, usually, no other person in the group or even a supervisor has the ability to look at that person's calendar to determine what the upcoming action items are. Even if a supervisor can look at a person's individual calendar the supervisor will also see (and have to filter out) that person's personal events, such as social engagements, birthdays, and medical appointments. Additionally, in order to have an understanding for what an entire group is responsible for, a supervisor would have to integrate many personal calendars. Even if this could be done, which could be problematic, especially for those who insist upon using paper calendars, the integrated or merged calendar would be littered with personal information, and wading through this irrelevant information can be both time consuming and overwhelming to the supervisor. It would therefore be beneficial to provide a document reminder system that allows a supervisor to access a calendar which outlines all action items for each individual in the group and/or the group as a whole, without extraneous personal items. It would also be beneficial to provide a document reminder system where a supervisor accesses one master calendar that has all action items for a particular group of individuals or a particular project and that can be easily sorted by various fields such as dates, clients, matters, and so on. Another problem of relying, as most businesses do today, on personal calendars is that when the person leaves the organization, the reminders, in many instances, leave too. Even if calendar dates are somehow preserved, the cryptic personal notes the departed employee left behind in his/her calendar may be impossible to interpret. As a consequence, the calendared event may pass without a response or the necessary action being taken. Therefore, it would be beneficial to provide a document reminder system where the responsibility for action items can be centrally reviewed and be easily transferred from one user to another.	<SOH> SUMMARY OF THE INVENTION <EOH>An object of the instant invention is to provide a document reminder system. Another object of the instant invention is to provide a document reminder system that is easy to use. Another object of the instant invention is to provide a document reminder system that is easy to use and which provides increased usability over conventional systems. Another object of the instant invention is to provide a user-friendly interface to a user's existing document management, email or messaging, calendar, and/or other systems in order to ensure that an appropriate user is notified when action or actions should be taken with respect to a specific document, is furnished with contextual notation to the user indicating the appropriate course of action to be taken, is linked directly to the relevant document, is (after electing to enter the document) taken to the relevant section of the document, is furnished with an automatic verification of task completion, and is furnished with a project task list with respect to the document or the specific action item. Another object of the invention is to provide an easy and fast way for a supervisor or manager to determine the workload of a group of workers for an upcoming time period. Still another object of the invention is to provide an easily accessible and traceable database of information pertaining to a document, a client, or other fields in order for a user to search and sort the information for their own use and in order for management, and others, to verify that tasks have been completed. The document reminder system of the instant invention may be a stand alone program that includes email/messaging functionality and document management functionality, or, alternatively, the document reminder system of the instant invention may be a “middleware” (or ad-on) program that operates in conjunction with already existing programs, such as a document management system and an email/messaging system. In a preferred embodiment, the document reminder system accesses the databases of the other systems in order to create links and associations between the data stored in those databases, such as, for example, a document or an email address list, and stores the associations as a reminder in a separate database. A computer program associated with the document reminder system database includes a time schedule feature, such that the database is triggered at the time an action relating to a document is to be taken and the database automatically generates the reminder via the messaging system along with the associated data from the other databases. In a preferred embodiment, the instant invention is a middleware program adapted for use with any email or messaging and document management system. Popular document management systems, for example, are distributed by Hummingbird™, Interwoven , SharePoint™, Documentum™, FileNet™, IBM™, Worldox™, and Open Text™. While the examples provided herewith are directed to one aspect of the present invention, namely that aspect being adapted to function with the above listed document management systems, it is contemplated that any document management system may be used in conjunction with the instant invention, all document management systems having equivalent data structures and functionality. In one embodiment, the reminder information corresponding to a particular document is provided by a user at the time of document creation. That is, when the user creates a document, the user simply utilizes the document reminder system, such as, for example, by selecting an appropriate action from an onscreen drop-down menu, or clicking on an appropriate button or other control, to open a window into which the user may enter the appropriate tickler information, such as the reminder date. A reminder and a tickler are used as interchangeable terms in the industry and throughout this disclosure. Because the reminder of the present invention is opened within the on-screen document or in the document management profile or similar screen, other information for the reminder is captured automatically from the database record in the document management system associated with the document. Automatically collected information includes (without limitation): the pointer to the document itself, the date of creation, the author, the client and matter identifiers, the document type, the author's group, and the document management system's document description. All necessary information, such as, for example, the client name and matter number are included and if that information has not been entered yet, for the case where it is a new document that has not been saved to the document management system yet, the present invention will prompt the user to provide the necessary information or, in the alternative, to save the document in the document management system before creating a reminder for the subject document. In another embodiment, while the user is reading the document in an application, such as, for example, Microsoft Word™, Excel™ or Acrobat Adobe™, an icon in the user's toolbar is clicked, rather than utilizing a drop down menu, to bring up the tickler to be attached to the document. In another embodiment, the user selects a document that has already been created from the document management system, opens that document, and then creates a reminder for that document. In another embodiment, the present system is adapted to scan the document, upon accessing the present system, in order to search for important date information that may be included in the reminder. When appropriate events are identified within the document, the data window is again entered where both user-input and automatically captured data will be stored. Once the window for creating a reminder is opened, the user may enter the recipient of the reminder, information pertaining to the document and select certain features of the document reminder system. To select a recipient of the reminder, the system of a preferred embodiment allows users to utilize the address list of their current messaging system, thus choosing from existing staff members, a list of outside contacts, vendors, clients, customers, and so on. This prevents the need for creating and maintaining a separate user list for the document reminder system. In the window, the user may provide notation in the form of instructions to be provided at the time a reminder is sent. In this way, the user's recollection will later be easily refreshed and the user will know what action to take with respect to a particular document without spending an inordinate amount of time reviewing the document itself, a corresponding file, or other materials. Likewise, the user may indicate the date on which a later reminder is to be sent, and may request that a copy of the document itself be sent along with the reminder, or that a reference linked to the user's document management system be provided. In addition to entering reminder text, the user may pinpoint the precise section to which the reminder relates such that, when the document is accessed from the reminder message, the document will be opened to the precise clause in the document that is of importance to the date. Additionally, the reminder message may contain a link to a form that is to be used. Companies often have form letters or documents that are used by the entire company. Throughout the years those documents change but are usually saved as later versions of the original document. In a preferred embodiment, the reminder sent includes a link to the document such that when the document is accessed through the reminder the user will be taken to the most current version of the document. In addition to the above, in the window for creating reminders, the user may opt to provide additional attachments relevant to the document with respect to which the reminder is being generated. This ensures that, for example, additional forms needed to complete the action that must be taken with respect to a document are readily available and that a user does not have to search the document management system for the correct forms and the proper versions that the company wants used at the time the reminder is sent. Further, the user may also provide a checklist to be included with the reminder. In one embodiment, the action to be taken on a document has multiple steps, each requiring discrete actions, the checklist helping to ensure that the user completes each and every action required and does not inadvertently neglect one or more actions. The check list also allows a manager to monitor the progress of a particular project, being able to identify those tasks that have been completed and those tasks that remain. The checklist also permits knowledge transfer in that the checklist, created by experienced users, furnishes a roadmap for novice or less experienced users. Once a reminder is in place for a particular document, the users need no longer concern themselves with tracking that document, and need only take action when the document reminder system informs the user that action is needed, while the document reminder system continues to monitor the document response needs of the user, for all documents, over time. In the preferred embodiment, the document reminder system monitors and/or tracks the documents in the following way, the document reminder system may, for example, be scheduled to check, one or more times per day, a document reminder database created by the document reminder system. When a document reminder is identified as needing attention, the document reminder system retrieves the appropriate reminder message and also retrieves the appropriate document or reference, and additional documents, if any, identified by the user as pertinent to the task at hand. The user is reminded by email, instant message, telephone, pager, facsimile or other means, as chosen by the recipient. Where the reminder is electronic, the message will both contain the reminder information and a link to the pertinent document or documents. The system in question also retrieves procedural checklists, if any, provided by the user, as well as additional notation or instructions on the handling of the document or the event or events that are the subject of the reminder. The document reminder system then sends the reminder message, including all of its various components, and the appropriate document to the user's email server (or messaging system) for delivery to one or more users designated to receive the reminder. The user is then able to act on the document. It is preferred that once the necessary action has been taken with respect to a document, the user can then indicate to the document reminder system that the action (or appropriate step in a multiple-step project) has been completed. In one embodiment, once the user has completed the action or step, the user simply sends a reply message (using the user's email or other messaging system) with the word “complete.” The document reminder system then shows the task as completed without the user having to do anything more. In one embodiment, when the user completes the action or step, on a multiple-step project, the user indicates that he/she has completed the item but it is then sent to a supervisor for approval rather than just showing as complete by the system. The supervisor may review the work and set follow-up reminders for non-complete items. It will be appreciated that the document reminder system can monitor the documents in a variety of different ways now known or that will become known in the future in the art. In another embodiment, the user sets a reminder without the reminder being attached to a document. The reminder may have all of the same features and functions described above, including attaching given pre-set forms (or a link to those forms), setting multiple reminders, setting a reoccurring reminder, attaching checklists and other pertinent information to the reminder. In another embodiment, the document reminder system automatically creates the reminder based on information inputted by the user in the document management system profile or based on information from the document itself. The document reminder system extracts information from the profile to automatically create the reminder, for example, if a contract expiration date is entered in the profile by the user then an automatic reminder is set for sixty days prior to that expiration date. Alternatively, the document reminder system may scan the document itself and extract important date information and automatically create the reminder based on that information. As in the previously described manually created reminders, the reminder captures the profiled information of the document, such as, for example, the client matter name. If desired the user can later edit the reminder and add any of the functionally described herein, such as a link to forms or other documents, multiple notification dates, task checklists, etc. In addition to providing the reminder, the document reminder system provides reports and calendaring to further aid in the efficient handling of documents and/or events that need attention over time. In one embodiment, the calendaring component of the document reminder invention is adapted to provide a user with information related only to documents for which an action is scheduled on a given day, week, month, or other time period defined by the user. When the user accesses the calendar, the only items shown on the calendar are documents being tracked or monitored by the document reminder system or action items that have been set-up in the document reminder system, along with their status, if desired, and other information the user may select. In this way, the user is able to access a calendar that does not contain personal information or information not related to the documents for which reminders have been set, thus providing greater ease of use of the document reminder system than would be available by including the information in a user's preexisting calendaring software. Again, the user can access the pertinent document directly from the calendar view of the document reminder system, and a supervisor, administrator, or other user with appropriate access privileges can review, in calendar form, the documents that need to be, or have been, acted upon by one or more users. The user can view those documents for which action is pending, or can view documents for which actions have been completed. In one embodiment, the calendar view provides the user with information concerning who is responsible for the document, the action needed, and the date upon which the action must be taken. The calendar view also preferably allows the user to go directly to a document (and/or to a particular clause within a document) rather than having to search for the document in the user's document management system or having to scroll through the document once retrieved. In one embodiment, the calendar is searchable by various and customizable fields, for example, by client name, client matter number, document number or document type, in order to give a report to the client for all upcoming actions. The reporting feature of the document reminder system allows, for example, a user in a supervisory position to review all of the documents needing attention from one or more subordinates. In one embodiment, the reporting feature also allows the supervisor to view the status of the actions needed with respect to the documents, thereby determining whether the actions have been completed or are pending. In this manner, a supervisor is able to monitor all steps in a multiple-step project and has the ability to set up follow-up reminders or have the user that completed the item redo the item if it is not satisfactory to the supervisor. The reporting feature of the document reminder system provides information to the supervisor concerning which subordinate is responsible for a document, the date on which an action must be taken, the nature of the action to be taken, and additional comments, notation or the subordinates vacation schedules. Further, the reporting feature preferably allows the supervisor easily to review the appropriate document by selecting it from within the report itself, rather than having to go to the document management system to search for it, thus reducing the chance that the supervisor will access the wrong document or wrong version and reducing exposure to liability. The administrating feature of the document reminder system allows, for example, a user in a supervisory role to change the individual responsible for a calendared event, in order to even out workloads, move all responsibilities in the case where an individual leaves a company, or the individual is on vacation. In one embodiment, the administrating feature allows for a user with the correct authorization to configure user rights, edit user authorization, reassign the owner of a reminders for a specific period of time or permanently, create user groups, create and view vacation schedules, create custom tags, configure the system for customization, and viewing a log for a particular user so that the viewing of documents and reminders is monitored. The above provides an exemplary description of the document reminder system. This description is further supplemented by the documents appended hereto. It is contemplated that a user of the document reminder system may customize the system once in place, allowing the system to provide data fields, selections, or other information pertinent to the user's business. The present disclosure should be viewed broadly, and the primary objective of the invention should be seen, broadly, as providing an integrated document reminder system that interfaces with a user's existing document management, calendar and email systems. It should be understood that the various descriptions and illustrations of the present system set forth herein are exemplary and are not intended to limit the scope of the present invention. Upon reading this disclosure, many variations and modifications will be apparent to those of skill in the art, and it is contemplated that these variations and modifications are within the spirit and scope of the present invention.	This application claims priority to U.S. Provisional Patent Application Ser. No. 60/764,845 filed Feb. 4, 2006, the entire disclosure of which is incorporated herein by reference in it entirety. FIELD OF THE INVENTION The present invention relates generally to a document reminder system. More specifically, the present invention is concerned with a document reminder system that coordinates with a document management system, a messaging system and/or other various systems such that an appropriate user is notified when action items for a document, a client or a project are needed. BACKGROUND OF THE INVENTION In a modern business environment, proper management of documents and relevant dates is essential to success. A key problem in the management of documents and dates is the tracking of documents through time, whether because of a need to follow up on a document at a given time, generate periodic reports, or perform periodic document review such as that required by Sarbanes Oxley. Numerous document management systems are known in the art. These systems generally allow a user to identify a document using a variety of fields that are then saved in a database that can be searched when a user wishes to retrieve documents pertaining to a particular client, a particular matter, or even a general subject matter. Documents can also be searched by author, date of creation, or any other database field utilized by these systems. The problem with each of these systems, however, is that they require external functionality in order to indicate to a user when a certain document should be reviewed, or when a response to a document is expected, document management systems themselves treating documents as inert and having no significance other than as historical records. Contracts, demand letters, licenses, leases, and other business documents are not inert. They are the engines of business and govern numerous business events such as renewals, responses, elections, options, reviews, and cancellations. For example, in business, it would be useful to have a system that could notify a user that a key date is approaching, so that the user may then search for relevant documents in the document management system and act accordingly. Using conventional technology, this, of course, requires that the pertinent information be entered into a docketing or calendaring system so that the user will be notified of a need at a later date. The step of entering the needed information into a docketing or calendaring system takes time and requires significant labor on the part of workers in an organization. Moreover tedious data entry is redundant and is subject to human error. It is well known that only a fraction of dates are logged because of this time and resource utilization factor and because of the disconnection between and complexity of multiple systems, e.g., calendaring (tickler), document management, and messaging or notification. Therefore, it would be beneficial to attach a reminder to a document while the document is being read in a manner that only takes a few seconds and that automatically captures data already stored about the document, thus maximizing the possibility the date is captured. Moreover, even if the relevant data is entered, either enormous quantities of information must be entered, or the information will be without meaningful context such that the user still has to look up, retrieve, and review the documents relevant to the event in question. Therefore, it would be beneficial to provide a document reminder system that seamlessly interfaces with a user's existing document management system, email or messaging system, calendar (tickler) system and other software, to provide a simple and effective means of generating reminders, prompting users, tracking responses to the reminders (if any), and furnishing meaningful information about the event, the document, and the parties, all within a matter of seconds. Further, it would be beneficial to provide a system that furnishes quick access to the document itself, without a need to search the document management system. It would be further desirable to have a system that not only automatically identifies the relevant document, but also furnishes relevant information to refresh the user's recollection or points to the specific section within the document that has triggered the reminder. Having the reminder directly connected to the document permits the user quickly and easily to take the appropriate action without the need for separate entry of data. For example, a contract may specify that notice of renewal must be sent within a prescribed period of time prior to the expiration of the term of that contract. Knowing that is helpful, but to whom is the notice to be sent? What is the proper address for notice? Must the notice be sent by Certified Mail or other prescribed means? How are specific terms used in this example notice provision defined? Years may pass before the date comes due. In addition, if the date is in a personal calendar, there is always the chance when the person goes looking for the document that the person uses the wrong document or version of the document. By being linked into the document itself, each of these questions can be answered in seconds, all without the need for extensive data entry in a separate database system and without fear that the wrong document or wrong version will be retrieved. When users are responsible for an action item for a document, for example a renewal date, they will often put that renewal date in the user's personal calendar system, either an electronic or paper calendar. When the users are looking at their calendars, they are able to determine what their workload for an upcoming time period is and what action items need to be taken; however, usually, no other person in the group or even a supervisor has the ability to look at that person's calendar to determine what the upcoming action items are. Even if a supervisor can look at a person's individual calendar the supervisor will also see (and have to filter out) that person's personal events, such as social engagements, birthdays, and medical appointments. Additionally, in order to have an understanding for what an entire group is responsible for, a supervisor would have to integrate many personal calendars. Even if this could be done, which could be problematic, especially for those who insist upon using paper calendars, the integrated or merged calendar would be littered with personal information, and wading through this irrelevant information can be both time consuming and overwhelming to the supervisor. It would therefore be beneficial to provide a document reminder system that allows a supervisor to access a calendar which outlines all action items for each individual in the group and/or the group as a whole, without extraneous personal items. It would also be beneficial to provide a document reminder system where a supervisor accesses one master calendar that has all action items for a particular group of individuals or a particular project and that can be easily sorted by various fields such as dates, clients, matters, and so on. Another problem of relying, as most businesses do today, on personal calendars is that when the person leaves the organization, the reminders, in many instances, leave too. Even if calendar dates are somehow preserved, the cryptic personal notes the departed employee left behind in his/her calendar may be impossible to interpret. As a consequence, the calendared event may pass without a response or the necessary action being taken. Therefore, it would be beneficial to provide a document reminder system where the responsibility for action items can be centrally reviewed and be easily transferred from one user to another. SUMMARY OF THE INVENTION An object of the instant invention is to provide a document reminder system. Another object of the instant invention is to provide a document reminder system that is easy to use. Another object of the instant invention is to provide a document reminder system that is easy to use and which provides increased usability over conventional systems. Another object of the instant invention is to provide a user-friendly interface to a user's existing document management, email or messaging, calendar, and/or other systems in order to ensure that an appropriate user is notified when action or actions should be taken with respect to a specific document, is furnished with contextual notation to the user indicating the appropriate course of action to be taken, is linked directly to the relevant document, is (after electing to enter the document) taken to the relevant section of the document, is furnished with an automatic verification of task completion, and is furnished with a project task list with respect to the document or the specific action item. Another object of the invention is to provide an easy and fast way for a supervisor or manager to determine the workload of a group of workers for an upcoming time period. Still another object of the invention is to provide an easily accessible and traceable database of information pertaining to a document, a client, or other fields in order for a user to search and sort the information for their own use and in order for management, and others, to verify that tasks have been completed. The document reminder system of the instant invention may be a stand alone program that includes email/messaging functionality and document management functionality, or, alternatively, the document reminder system of the instant invention may be a “middleware” (or ad-on) program that operates in conjunction with already existing programs, such as a document management system and an email/messaging system. In a preferred embodiment, the document reminder system accesses the databases of the other systems in order to create links and associations between the data stored in those databases, such as, for example, a document or an email address list, and stores the associations as a reminder in a separate database. A computer program associated with the document reminder system database includes a time schedule feature, such that the database is triggered at the time an action relating to a document is to be taken and the database automatically generates the reminder via the messaging system along with the associated data from the other databases. In a preferred embodiment, the instant invention is a middleware program adapted for use with any email or messaging and document management system. Popular document management systems, for example, are distributed by Hummingbird™, Interwoven , SharePoint™, Documentum™, FileNet™, IBM™, Worldox™, and Open Text™. While the examples provided herewith are directed to one aspect of the present invention, namely that aspect being adapted to function with the above listed document management systems, it is contemplated that any document management system may be used in conjunction with the instant invention, all document management systems having equivalent data structures and functionality. In one embodiment, the reminder information corresponding to a particular document is provided by a user at the time of document creation. That is, when the user creates a document, the user simply utilizes the document reminder system, such as, for example, by selecting an appropriate action from an onscreen drop-down menu, or clicking on an appropriate button or other control, to open a window into which the user may enter the appropriate tickler information, such as the reminder date. A reminder and a tickler are used as interchangeable terms in the industry and throughout this disclosure. Because the reminder of the present invention is opened within the on-screen document or in the document management profile or similar screen, other information for the reminder is captured automatically from the database record in the document management system associated with the document. Automatically collected information includes (without limitation): the pointer to the document itself, the date of creation, the author, the client and matter identifiers, the document type, the author's group, and the document management system's document description. All necessary information, such as, for example, the client name and matter number are included and if that information has not been entered yet, for the case where it is a new document that has not been saved to the document management system yet, the present invention will prompt the user to provide the necessary information or, in the alternative, to save the document in the document management system before creating a reminder for the subject document. In another embodiment, while the user is reading the document in an application, such as, for example, Microsoft Word™, Excel™ or Acrobat Adobe™, an icon in the user's toolbar is clicked, rather than utilizing a drop down menu, to bring up the tickler to be attached to the document. In another embodiment, the user selects a document that has already been created from the document management system, opens that document, and then creates a reminder for that document. In another embodiment, the present system is adapted to scan the document, upon accessing the present system, in order to search for important date information that may be included in the reminder. When appropriate events are identified within the document, the data window is again entered where both user-input and automatically captured data will be stored. Once the window for creating a reminder is opened, the user may enter the recipient of the reminder, information pertaining to the document and select certain features of the document reminder system. To select a recipient of the reminder, the system of a preferred embodiment allows users to utilize the address list of their current messaging system, thus choosing from existing staff members, a list of outside contacts, vendors, clients, customers, and so on. This prevents the need for creating and maintaining a separate user list for the document reminder system. In the window, the user may provide notation in the form of instructions to be provided at the time a reminder is sent. In this way, the user's recollection will later be easily refreshed and the user will know what action to take with respect to a particular document without spending an inordinate amount of time reviewing the document itself, a corresponding file, or other materials. Likewise, the user may indicate the date on which a later reminder is to be sent, and may request that a copy of the document itself be sent along with the reminder, or that a reference linked to the user's document management system be provided. In addition to entering reminder text, the user may pinpoint the precise section to which the reminder relates such that, when the document is accessed from the reminder message, the document will be opened to the precise clause in the document that is of importance to the date. Additionally, the reminder message may contain a link to a form that is to be used. Companies often have form letters or documents that are used by the entire company. Throughout the years those documents change but are usually saved as later versions of the original document. In a preferred embodiment, the reminder sent includes a link to the document such that when the document is accessed through the reminder the user will be taken to the most current version of the document. In addition to the above, in the window for creating reminders, the user may opt to provide additional attachments relevant to the document with respect to which the reminder is being generated. This ensures that, for example, additional forms needed to complete the action that must be taken with respect to a document are readily available and that a user does not have to search the document management system for the correct forms and the proper versions that the company wants used at the time the reminder is sent. Further, the user may also provide a checklist to be included with the reminder. In one embodiment, the action to be taken on a document has multiple steps, each requiring discrete actions, the checklist helping to ensure that the user completes each and every action required and does not inadvertently neglect one or more actions. The check list also allows a manager to monitor the progress of a particular project, being able to identify those tasks that have been completed and those tasks that remain. The checklist also permits knowledge transfer in that the checklist, created by experienced users, furnishes a roadmap for novice or less experienced users. Once a reminder is in place for a particular document, the users need no longer concern themselves with tracking that document, and need only take action when the document reminder system informs the user that action is needed, while the document reminder system continues to monitor the document response needs of the user, for all documents, over time. In the preferred embodiment, the document reminder system monitors and/or tracks the documents in the following way, the document reminder system may, for example, be scheduled to check, one or more times per day, a document reminder database created by the document reminder system. When a document reminder is identified as needing attention, the document reminder system retrieves the appropriate reminder message and also retrieves the appropriate document or reference, and additional documents, if any, identified by the user as pertinent to the task at hand. The user is reminded by email, instant message, telephone, pager, facsimile or other means, as chosen by the recipient. Where the reminder is electronic, the message will both contain the reminder information and a link to the pertinent document or documents. The system in question also retrieves procedural checklists, if any, provided by the user, as well as additional notation or instructions on the handling of the document or the event or events that are the subject of the reminder. The document reminder system then sends the reminder message, including all of its various components, and the appropriate document to the user's email server (or messaging system) for delivery to one or more users designated to receive the reminder. The user is then able to act on the document. It is preferred that once the necessary action has been taken with respect to a document, the user can then indicate to the document reminder system that the action (or appropriate step in a multiple-step project) has been completed. In one embodiment, once the user has completed the action or step, the user simply sends a reply message (using the user's email or other messaging system) with the word “complete.” The document reminder system then shows the task as completed without the user having to do anything more. In one embodiment, when the user completes the action or step, on a multiple-step project, the user indicates that he/she has completed the item but it is then sent to a supervisor for approval rather than just showing as complete by the system. The supervisor may review the work and set follow-up reminders for non-complete items. It will be appreciated that the document reminder system can monitor the documents in a variety of different ways now known or that will become known in the future in the art. In another embodiment, the user sets a reminder without the reminder being attached to a document. The reminder may have all of the same features and functions described above, including attaching given pre-set forms (or a link to those forms), setting multiple reminders, setting a reoccurring reminder, attaching checklists and other pertinent information to the reminder. In another embodiment, the document reminder system automatically creates the reminder based on information inputted by the user in the document management system profile or based on information from the document itself. The document reminder system extracts information from the profile to automatically create the reminder, for example, if a contract expiration date is entered in the profile by the user then an automatic reminder is set for sixty days prior to that expiration date. Alternatively, the document reminder system may scan the document itself and extract important date information and automatically create the reminder based on that information. As in the previously described manually created reminders, the reminder captures the profiled information of the document, such as, for example, the client matter name. If desired the user can later edit the reminder and add any of the functionally described herein, such as a link to forms or other documents, multiple notification dates, task checklists, etc. In addition to providing the reminder, the document reminder system provides reports and calendaring to further aid in the efficient handling of documents and/or events that need attention over time. In one embodiment, the calendaring component of the document reminder invention is adapted to provide a user with information related only to documents for which an action is scheduled on a given day, week, month, or other time period defined by the user. When the user accesses the calendar, the only items shown on the calendar are documents being tracked or monitored by the document reminder system or action items that have been set-up in the document reminder system, along with their status, if desired, and other information the user may select. In this way, the user is able to access a calendar that does not contain personal information or information not related to the documents for which reminders have been set, thus providing greater ease of use of the document reminder system than would be available by including the information in a user's preexisting calendaring software. Again, the user can access the pertinent document directly from the calendar view of the document reminder system, and a supervisor, administrator, or other user with appropriate access privileges can review, in calendar form, the documents that need to be, or have been, acted upon by one or more users. The user can view those documents for which action is pending, or can view documents for which actions have been completed. In one embodiment, the calendar view provides the user with information concerning who is responsible for the document, the action needed, and the date upon which the action must be taken. The calendar view also preferably allows the user to go directly to a document (and/or to a particular clause within a document) rather than having to search for the document in the user's document management system or having to scroll through the document once retrieved. In one embodiment, the calendar is searchable by various and customizable fields, for example, by client name, client matter number, document number or document type, in order to give a report to the client for all upcoming actions. The reporting feature of the document reminder system allows, for example, a user in a supervisory position to review all of the documents needing attention from one or more subordinates. In one embodiment, the reporting feature also allows the supervisor to view the status of the actions needed with respect to the documents, thereby determining whether the actions have been completed or are pending. In this manner, a supervisor is able to monitor all steps in a multiple-step project and has the ability to set up follow-up reminders or have the user that completed the item redo the item if it is not satisfactory to the supervisor. The reporting feature of the document reminder system provides information to the supervisor concerning which subordinate is responsible for a document, the date on which an action must be taken, the nature of the action to be taken, and additional comments, notation or the subordinates vacation schedules. Further, the reporting feature preferably allows the supervisor easily to review the appropriate document by selecting it from within the report itself, rather than having to go to the document management system to search for it, thus reducing the chance that the supervisor will access the wrong document or wrong version and reducing exposure to liability. The administrating feature of the document reminder system allows, for example, a user in a supervisory role to change the individual responsible for a calendared event, in order to even out workloads, move all responsibilities in the case where an individual leaves a company, or the individual is on vacation. In one embodiment, the administrating feature allows for a user with the correct authorization to configure user rights, edit user authorization, reassign the owner of a reminders for a specific period of time or permanently, create user groups, create and view vacation schedules, create custom tags, configure the system for customization, and viewing a log for a particular user so that the viewing of documents and reminders is monitored. The above provides an exemplary description of the document reminder system. This description is further supplemented by the documents appended hereto. It is contemplated that a user of the document reminder system may customize the system once in place, allowing the system to provide data fields, selections, or other information pertinent to the user's business. The present disclosure should be viewed broadly, and the primary objective of the invention should be seen, broadly, as providing an integrated document reminder system that interfaces with a user's existing document management, calendar and email systems. It should be understood that the various descriptions and illustrations of the present system set forth herein are exemplary and are not intended to limit the scope of the present invention. Upon reading this disclosure, many variations and modifications will be apparent to those of skill in the art, and it is contemplated that these variations and modifications are within the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the invention, illustrative of the best mode in which the applicant has contemplated applying the principles, is set forth in the following description and is shown in the drawings and is particularly and distinctly pointed out and set forth in the appended claims. FIG. 1 is a sample screen shot of an exemplary embodiment of the document reminder system in connection with setting up a reminder within the present invention. FIG. 1a is a sample screen shot of the system of FIG. 1 showing an address list utilizing the user's current email messaging system. FIG. 2 is several sample screen shots of the system of FIG. 1 showing setting a notification date for the document reminder, with an option for the notification date to be recurring. FIG. 3 is several sample screen shots of a preferred embodiment showing a review of the action items for a document by selecting that document from a document management system and then showing the reminder that has been previously set up for that document. FIG. 4 is several sample screen shots of the reminder of a preferred embodiment showing various pop-up features, such as an attached forms window, a task checklist window, and a delivery history of the reminder, also showing an example of how the reminder will look as an email when opened by a user. FIG. 4a is a sample screen shot of a preferred embodiment showing the reminder sent by the document reminder system including an attached document. FIG. 5 is several sample screen shots of a preferred embodiment of the document reminder system showing a calendaring and a reporting feature with the ability to filter the calendar view, for example, by individual, group, or client, open the reminder and view the correct document. FIG. 6 is a sample screen shot of the reporting feature of a preferred embodiment of the present system showing a list of upcoming reminders and ability to sort and print reports. FIG. 7 is a sample screen shot of an administrating feature of a preferred embodiment of the present system showing a user rights configuration and assignment feature. FIG. 8 is a sample screen shot of the reporting feature of a preferred embodiment of the present system showing, in list form, a history of activity on a specific reminder. FIG. 9 is a sample screen shot of the administrating feature of FIG. 7 showing an editing feature that allows individuals to delegate/share reminders with other users. FIG. 10 is a sample screen shot of the administrating feature of FIG. 7 showing the ability to re-assign future reminders and calendar entries to other users (used for example, when someone leaves the company). FIG. 11 is a sample screen shot of the administrating feature of FIG. 7 showing the creation of user groups. FIG. 12 is a sample screen shot of the administrating feature of FIG. 7 showing a vacation feature that allows for a user to track his/her scheduled vacation. FIG. 13 is a sample screen shot of the administrating feature of FIG. 7 showing a custom tag feature allowing the user to customize the document reminder system of a preferred embodiment, such as by employing an alternative client/ matter filing system. FIG. 14 is a sample screen shot of the administrating feature of FIG. 7 showing a system configuration feature. FIG. 15 is a sample screen shot of the administrating feature of FIG. 7 showing a system log. FIG. 16 is a sample screen shot of a preferred embodiment of the present invention showing a reminder being set without being attached to a document but that has all other functionality of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS As required, detailed embodiments of the present inventions are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the principles of the inventions, which may be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art variously to employ the present invention in virtually any appropriately detailed structure. Preferred embodiments of the present invention are described in the context of a user interface system that uses an already existing document management system, an email system and other various systems in order seamlessly to link the multiple systems together. The document reminder system has endless applications including, but not limited to: contract management; contract milestones or evergreen clauses; regulatory compliance, such as Sarbanes Oxley; project document monitoring; certification and license renewals; maintenance and warranty agreements; real estate transactions, lease agreements, insurance contracts, human resources documents, such as employee reviews and benefits reminders; ongoing client correspondence; training manual updates; trademark and patent docketing; and other basic docketing. In one embodiment, referring to FIG. 1, a document reminder system 20 is utilized to set-up a reminder by selecting a document 22 from a document management system by right clicking the user's mouse on document 22 and having a reminder window 40 open on the user's screen. That reminder is now automatically linked to document 22 and that reminder is stored in a database of the document reminder system. At this time the user selects the appropriate person(s) to be responsible for document 22 from the user's existing email contacts. Referring to FIG. la, the user selects a To button 24 in reminder window 40 and a Recipients window 26 opens. Recipients window 26 utilizes the contact information from the user's email messaging system, thus allowing users to select themselves, a different user at the company, an entire group, or even an individual outside of the company, such as a client, vendor, customer, opposing counsel, local counsel or other individuals. This feature prevents the need for creating and maintaining a separate contact list for the document reminder system. In one embodiment, the user may carbon copy or blind copy recipients. It will be appreciated that there are other known ways to select the document so that a window to enter information will open, including but not limited to, selecting an appropriate command from an onscreen drop-down menu, or clicking on an appropriate button or other control, either from within the document management system or from within the profiled document such as a Microsoft Word document. Any function may be utilized that will allow for the reminder window to open into which the user can then enter the appropriate information. Because the reminder window is opened within the on-screen document (or document management system), other information for the reminder is captured automatically from the database record (called a profile) in the document management system associated with the document. Information automatically collected may include: the pointer to the document itself, the date of creation, the author, the client name, the client matter number and identifiers, the document type, the author's group, and the document management system's document description, to name some of the most likely data elements. The user has the option to attach document 22 to the reminder as a direct link to document 22 in the document management system or as a copy of document 22. In one embodiment, the user has the ability to open the document, for example, if the user wants to copy and paste a paragraph that needs attention, such as a termination clause, in the notation of reminder window 40. In one embodiment, the present system is adapted to scan the document, upon accessing the present system, in order to search for important date information that may be included automatically in the reminder. In another embodiment, the user may pinpoint the precise section to which the reminder relates, such that, when the document is accessed from the reminder, the document will be opened to the precise clause in the document that is of importance and which describes or mandates the action needed. In another embodiment, a user can set-up the reminder while within a document application, such as, for example, Microsoft Word™, Excel™ or Acrobat Adobe™, by simply clicking on an icon located in the user's toolbar or similar location the reminder window will open and automatically attach the document the user has open to the reminder along with any automatically collected information (as discussed above). Once the window for creating the reminder is opened, the user enters information pertaining to document 22 and selects certain features of document reminder system 20. For example, the user may provide notation in the form of instructions to be provided at the time the reminder is sent. Referring to FIG. 2, the users selects a Notify Date button 41 and a Notification Date window 42 opens. The user indicates the date on which the reminder is to be sent. This date can correspond to any important date, such as, for example, a contract renewal notice, a patent due date, client follow-up note or other key dates relating to the document. Multiple notification dates may be selected by the user, for example, the user may want the reminder to be sent 1 month, 2 weeks, 1 week, 3 days, and on the due date of the important date. If multiple notifications are set and the user completes the action item and sends a completion email by replying to the reminder, then future reminders will not be sent. In one embodiment, the user can set notifications to be sent after the due date, until the item is completed, for example, every day after the action item is due until the user completes the item. In one embodiment, the user may create the reminder for a date in the future beyond the due date of the action item, for example, if the user wants a reminder to send the completed document to the client for review. The user is therefore not limited to picking one notification date, but rather may select as many dates as are necessary and therefore setting up as many reminders to that particular document as the user wants. The user may also create a recurring date by selecting a Recurrence button 43 so a Notification Recurrence window 44 opens. The user can set a reoccurring reminder to coincide with an important document date, such as, for example, if a 15-year vendor contract has a clause that the vendor must carry insurance, the reoccurring reminder can be sent to the user to remind the user to check and make sure that the vendor has a current insurance policy. In one embodiment, the personal electronic calendar of the user, for example, Microsoft Outlook™, Lotus Notes or Novell GroupWise, synchronizes with the calendaring feature of the document reminder system such that the user's personal calendar is updated automatically when any reminder is set-up for that user, no matter what user has set the reminder, and such that if the user makes a change to the reminder in the user's personal calendar then the calendar of the document reminder system is automatically updated. In one embodiment, a contract's expiration date may be set-up as the reminder to the user. The user can then confirm that the contract has indeed expired and view a document retention table within the document reminder system and then set a new reminder that coincides with the proper retention dates. When the future reminder is then sent the user can determine if the document should continue to be retained or if it should be destroyed. The time necessary to retain documents depends on the law at the time the contract expires, therefore, current data retention tables may be accessed when the document expires in order to set the correct retention schedule for that document. In addition to the above, the user may opt to provide additional attachments relevant to the document with respect to which the reminder is being generated. Referring to FIGS. 3 and 4, reminder window 40 has various options available to the user so that the user may attach additional information to the reminder. The user may attach additional pre-set forms or templates to the reminder by selecting a Forms Library button 45 that opens an Attached Forms window 46. This ensures that additional forms needed to complete the action that must be taken with respect to the document are readily available and that a user does not have to search the document management system for such forms and their correct version. Once Attached Forms window 46 is open, the user can select which form(s) that he/she wants to attach to the reminder, such as, for example, a form to be used as an example of how the document should be drafted or another correlating agreement that is pertinent to the document or form. Most companies have set form letters that are to be sent to clients, vendors or other such correspondents and by having a form linked to the reminder, whenever that reminder is opened the most current version of the form will be accessed. The user may provide a checklist to be included with the reminder by selecting a Checklists button 49 which opens a Document Checklists window 48. In an instance wherein the action to be taken on a document has multiple steps, each requiring discrete actions, the checklist helps ensure that the user completes each and every action required and does not inadvertently neglect one or more actions. In one embodiment, the various tasks in the checklist may be handled by different users and each item on the checklist item can be assigned to a different user so that all users working on the project know who is responsible for what documents or action items and when they are due. This feature allows for the quick delegation of assignments within a project to a group of users and allows for quicker and more informed work flow. In one embodiment, completed items can be approved by the supervisor and follow up reminders can be assigned for uncompleted items or items not done to the satisfaction of the supervisor. In another embodiment, the user may create the reminder at a later time than when the user first created or reviewed the document. The process is similar to that described above, the user selects a document in the user's document management system and then accessing the document reminder system, such as by right clicking on the particular document in the document management system to select and launch the document reminder system. Similarly, a user may edit a reminder at anytime and the entire document reminder system and corresponding reminders on personal calendars are automatically updated. In another embodiment, the document reminder system automatically creates the reminder based on information inputted by the user in the document management system profile or based on information from the document itself. The document reminder system extracts information from the profile to automatically create the reminder, for example, if a contract expiration date is entered in the profile by the user then an automatic reminder is set for sixty days prior to that expiration date. Alternatively, the document reminder system may scan the document itself and extract important date information and automatically create the reminder based on that information. As in the previous manually created reminders, the reminder will capture the profiled information of the document, such as, for example, the client matter name. If desired the user can later edit the reminder and add any of the functionally described herein, such as a link to forms or other documents, multiple notification dates, task checklists, etc. In another embodiment, referring to FIGS. 4 and 8, after the reminder is created, the user may select a Delivery History button 51 and a history report 52 that summarizes the email delivery history of all the reminders for that document. This feature allows for a detailed and uneditable audit trail of all users and outside individuals that have received the reminder regarding the document. In yet another embodiment, the user has the ability to access a history report that displays when a reminder had been viewed by the receiver of the reminder. Once a reminder is in place for a particular document, users need no longer concern themselves with tracking that document, and need only take action when the document reminder system informs the user, for example, by a reminder message 50 that is generated by the document reminder system of the instant invention, that action is needed, while the document reminder system continues to monitor the document response needs, for all documents, over time. Referring to FIG. 4a, illustrating an example of reminder message 50 with an attached document. This is what the user receives when an action item is needed. Reminder message 50 includes information related to the various functionality and options described herein. In the reminder message examples, illustrated by FIGS. 4 and 4a, reminder message 50 is in the form of an email; however, it is contemplated that the reminder message could be an instant message, a text message, a pager message, a facsimile or other type of communication, as chosen by the recipient. The way in which the document reminder system monitors and/or tracks documents is now described briefly. It should be understood that the following is exemplary of the mode of operation of the document reminder system, and is not to be construed as limiting. Much of the functionality of the document reminder invention may be provided in other ways that will be obvious to one of ordinary skill in the art upon reading this disclosure. The document reminder system may, for example, be scheduled to check, one or more times per day, a document reminder database created by the document reminder system. When a document reminder is identified as needing attention, the document reminder system retrieves the appropriate reminder message and also retrieves the appropriate document or reference copy and additional documents, if any, identified by the user as pertinent to the task at hand. The system also retrieves procedural checklists, if any, provided by the user, as well as additional notation or instructions on the handling of the document. Referring to FIG. 4, the document reminder system then sends a reminder message 50, including all of its various components, and the appropriate document to the user's email server for delivery to one or more users designated to receive the reminder. The user is then able to act on the document. In a preferred embodiment, once the necessary action has been taken with respect to a document, the user can then indicate to the document reminder system that the action has been completed. The user simply replies to reminder message 50 and types “complete” as a message and then hits the “send” or similar functioning button. In one embodiment, a completion email is sent by an individual outside of the company, regardless of the messaging system that individual is using (for use when the reminder is sent to a vendor or client). The document reminder system will then update the status of the reminder as completed upon receipt of the email. In one embodiment, the reminder will be sent to a supervisor to approve the action that was completed. At that time, the supervisor may not approve the reminder and send it back to the user if more work is needed. The supervisor may assign follow up reminders for uncompleted items or additional items. In addition to sending reminder message 50, the document reminder system provides reports and calendaring to further aid in the efficient handling of documents that need attention over time. Referring to FIG. 5, illustrating the calendaring component, a calendar 100, of the document reminder system is adapted to provide a user with information related only to documents for which an action is scheduled on a given day, week, month, or other time period defined by the user. When the user accesses calendar 100, the only items shown on the calendar are documents being tracked or monitored by the document reminder system, along with their status, if desired, and other information the user selects. In this way, the user is able to access a calendar that does not contain personal information or information not related to the documents for which reminders have been set. The user, for example a supervisor, viewing calendar 100 that has, for example, all the items that the supervisor's staff needs to complete in an upcoming month, the supervisor can reassign upcoming work to balance the work load of the staff. In one embodiment, illustrated in FIG. 5, the different reminders are click buttons (or active links) with the reminder name showing. When a reminder entry 108 is accessed reminder window 40 opens for the user to review. Again, the user can access a document 56 directly from the calendar view of the document reminder system by selecting the Open Document button 47. A supervisor, administrator, or other user with appropriate access privileges can review, in calendar form, the documents that need to be, or have been, acted upon by one or more users. Calendar 100 provides the user with information concerning who is responsible for the document, the action needed, and the date upon which the action must be taken. The user can view only those documents for which action is pending, or can view documents for which actions have been completed by selecting the Completed Reminders button 102. A completed reports window 106 allows the reviewer to view what reminders were completed and when they were completed. This is also a quick and efficient way for the reviewer to ensure that any reminders that were set up by the reviewer for other users have been completed. In another embodiment, completed reminders can be sorted and printed for use as an audit report. Calendar 100 also allows the user to go directly to a document rather than having to search for the document in the user's document management system. In one embodiment, the calendar is searchable by various and customizable fields by selecting a Filter Users button 104 that can, for example, allow the user to filter calendar 100 by individual, group, client, document type, etc. In yet another embodiment, referring to FIG. 16, the user may create a reminder that is not related to a document. This reminder will appear as an entry to the calendar. The user need only type a subject in the subject line that the reminder pertains to, thus giving the reminder a title that will appear on the calendar. The reminder has the same abilities to, for example, access the email contacts address list, attach forms, include checklists, reference data tables, set several notification dates, and set reoccurring dates. The user also has the ability to access tables in the document management system or other systems to find the proper filing information, such as, for example, the client name or client matter number. The reporting feature of the document reminder system allows, for example, a user in a supervisory position to review all of the reminder events and/or documents needing attention from one or more subordinates. Referring to FIG. 6, upcoming reminders can be produced and sorted. The user accesses a Report window 60 and may select different variables in order to create the wanted report, such as, for example, the reporting feature can create a report to give to the client for all upcoming events. In one embodiment, the reporting feature allows the supervisor to view the status of the actions needed with respect to the documents, thereby determining whether the actions have been completed or are pending. When an item is marked as completed by the user, a supervisor may approve the item and/or assign follow-up items when necessary. The reporting feature of the document reminder system may provide information to the supervisor concerning which subordinate is responsible for a document, the date on which an action must be taken, the nature of the action to be taken, and additional comments or notation. Therefore, the supervisor can easily look into the future through the calendar and reassign upcoming work to balance the work load of their subordinates. In another embodiment, the reporting feature allows the supervisor to easily review the appropriate document by selecting it from within the report itself, rather than having to go to the document management system to search for it. Referring to FIGS. 7, 9-15, the administrating feature of the document reminder system allows for a user in an administrative role, such as, for example, an office manager, a project manager, or a billing attorney to make administrative changes to the document reminder system. In one embodiment, referring to FIG. 7, the administrating feature is accessed through the document reminder system and utilized using an administration window 120. By using administrative window 120 the administrator has various options for customizing the document reminder system. Referring to FIG. 9, the user in a supervisory role may change the individual responsible for a calendared event by selecting an Edit Authorization tab 122. Edit Authorization tab 122 allows for the administrator to delegate/share reminders to other users. This feature may be used to even out workloads by moving a few assignments from one user to another or may be used when an individual is on vacation so that the reminders to that person are redirected temporarily. Referring to FIG. 10, the user in an administrative role may reassign all future email reminders and calendar entries to another user when an individual leaves the company or moves to a different department. In one embodiment, referring to FIG. 11, administrative window 120 provides the ability to create user groups. This feature allows the administrator to put individuals in to a group, such as, sales, litigation, real estate, everyone, administration or tech. These groups can then be used by any user of the system to set a reminder (as opposed to using an individual own contacts list from the email/messaging system). In one embodiment, referring to FIG. 12, the administrator, by selecting a Vacation tab 128, can enter vacation schedules for any user. The vacation schedules are then coordinated with the calendaring feature. In another embodiment, referring to FIG. 13, the user, by selecting a Custom Tags tab 130, can create custom tags that will allow for sortable fields such as client/matter for the reminders. In yet another embodiment, referring to FIG. 14, the user, by selecting a System Config tab 126, the administrating feature allows the user to configure the document reminder system in conjunction with the server, to enable defaults for attachments and reminder window format. In one embodiment, referring to FIG. 15, the user, by selecting a System log tab 138, can view a system log that shows the reminders that have been created, edited and completed. Although the foregoing detailed description of the present invention has been described by reference to an exemplary embodiment, and the best mode contemplated for carrying out the present invention has been shown and described, it will be understood that certain changes, modification or variations may be made in embodying the above invention, and in the construction thereof, other than those specifically set forth herein, may be achieved by those skilled in the art without departing from the spirit and scope of the invention, and that such changes, modification or variations are to be considered as being within the overall scope of the present invention. Therefore, it is contemplated to cover the present invention and any and all changes, modifications, variations, or equivalents that fall with in the true spirit and scope of the underlying principles disclosed and claimed herein. Consequently, the scope of the present invention is intended to be limited only by the attached claims, all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. Having now described the features, discoveries and principles of the invention, the manner in which the invention is constructed and used, the characteristics of the construction, and advantageous, new and useful results obtained; the new and useful structures, devices, elements, arrangements, parts and combinations, are set forth in the appended claims. It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.	G	60G06	161G06F	15	16
11623893	US20080169848A1-20080717	High-Speed Leaf Clock Frequency-Divider/Splitter	ACCEPTED	20080701	20080717	[]	G06F110	["G06F110", "H03K2100", "H03K515"]	7915929	20070117	20110329	375	354000	94225.0	LE	DINH	[{"inventor_name_last": "Douskey", "inventor_name_first": "Steven Michael", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Ellavsky", "inventor_name_first": "Matthew Roger", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}]	A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.	1. A clock splitter comprising: an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that has a lower frequency than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. 2. The clock splitter of claim 1, wherein the clock frequency-divider further selectively suppresses pulses in the B clock to generate a slower B clock signal. 3. The clock splitter of claim 2, wherein the slower B and C clock signals have a same frequency. 4. The clock splitter of claim 3, wherein the clock splitter is located at a terminal leaf of a clock tree. 5. A high speed clock frequency-divider/splitter comprising: a first AND Inverted (AI) gate having an input that is coupled to an inverted BC clock order control signal (BC signal), wherein the BC signal determines a time-phase order between a B clock and a C clock that are output from the high speed clock leaf clock frequency-divider/splitter; a second AI gate having inputs that are coupled to the BC signal and a chopped oscillator signal; a third AI gate having inputs from an output of the first AI gate and an output of the second AI gate, wherein the third AI gate outputs the C clock; a fourth AI gate having inputs from the chopped oscillator signal and a B clock gate; and a fifth AI gate having inputs from an output of the fourth AI gate and a Level-Sensitive Scan Design (LSSD) C clock control signal (LSSDC), wherein the fifth AI outputs the B clock. 6. The high speed clock leaf clock frequency-divider/splitter of claim 5, further comprising: a sixth AI gate having an input that is coupled to a C clock suppression signal (CSUP), wherein the CSUP selectively suppresses C clock pulses to generate a clock signal having a lower frequency than the chopped oscillator signal. 7. The high speed clock leaf clock frequency-divider/splitter of claim 6, further comprising: a seventh and an eighth AI gate that have inputs that are coupled to a B clock suppression signal (BSUP), wherein the BSUP selectively suppresses B clock pulses to generate a clock signal having a lower frequency than the chopped oscillator signal. 8. The high speed clock frequency-divider/splitter of claim 5, wherein the high speed clock frequency-divider/splitter is located at a terminal leaf of a clock tree. 9. A high speed clock leaf clock frequency-divider/splitter comprising: a first inverter having inputs that are coupled to a BC (B/C clock order) signal, an output of a first Shift Register Latch (SRL), and an output of a chopper, wherein the first SRL has inputs from a speed control signal that is part of a scan data input (D); a second AI having inputs that are coupled to the output of the chopper, an output of a third AI, the BC signal, and an output from a second SRL that is coupled to the first SRL, wherein the third AI has inputs that are coupled to a C clock suppression signal (CSUP) and the output of the first SRL; a fourth AI having inputs that are coupled to an output of the first AI, an output of the second AI, and a clock gate not (CGTN) inverse logic signal that controls a release of a C clock signal at a C clock pin that is coupled to an output of the fourth AI; a second inverter having an input that is coupled to an Oscillator (OSC) clock; a fifth AI having inputs coupled to a Level-Sensitive Scan Design (LSSD) C clock control signal (LSSDC) and an output of the second inverter, wherein an output of the first AI is coupled to an input to the chopper, an input to a sixth AI and an input to a seventh AI, wherein the seventh AI has additional inputs that are coupled to a B clock gate not (BGTN) inverse logic signal that controls a release of a B clock at a C clock pin that is coupled to an output of a third inverter, wherein the third inverter has an input that is coupled to the seventh AI; an eighth AI having a first input coupled to a fixed value gate not (FVGTN) inverse logic signal that is capable of overriding the scan data input (D) signal, wherein the eighth AI has a second input coupled to the output of the chopper, and wherein the FVGTN inverse logic signal is also coupled to an input to the sixth AI; a fourth inverter coupling an output of the eighth AI to an input to an L1 latch in the first SRL; and a fifth inverter coupling an output of the sixth AI to an L2 latch in the first SRL, wherein an output of the L2 latch in the first SRL is coupled to an input of the first L1 latch in the second SRL, and wherein the output of the first L1 latch in the second SRL is coupled to an input of a ninth AI via a sixth inverter, and wherein the ninth AI has an input coupled to a B gate not (BGTN) inverse logic signal that controls a release of a B clock at a ZB pin, and wherein an output of the ninth AI is coupled to an input of the seventh AI, and wherein a level-sensitive scan design B clock controller (LSSDB) is input to the seventh AI, wherein the high speed clock leaf clock frequency-divider/splitter controls a speed and phase of output B and C clocks through a use of the BC, CGTN, CSUP, D, FVGTN, LSSDC, OSC, BGTN and LSSDB signals. 10. The high speed clock leaf clock frequency-divider/splitter of claim 9, wherein the clock splitter is located at a terminal leaf of a clock tree. 11. A system comprising: a processor; a data bus coupled to the processor; a memory coupled to the data bus; and a high speed clock frequency-divider/splitter that is a component of the processor, wherein the high speed clock frequency-divider/splitter comprises: first and second AND Inverted (AI) gates that are coupled to a third AI gate; a fourth AI gate coupled to an input of a chopper, wherein the chopper has an output that is coupled to a fifth AI gate and the first and second AI gates; a sixth AI gate that is coupled to an output of the fourth AI gate, wherein an output of the AI gate is coupled to an input of a first inverter; a second inverter having an input that is coupled to an output of the fifth AI gate, wherein outputs of the first and second inverters are coupled to a first Shift Register Latch (SRL), and wherein the output of the first inverter is also coupled to an input of second SRL, and wherein the output of the second inverter is also coupled to an input of a third inverter; a seventh AI gate having an input that is coupled to an output of the third inverter; an eighth AI gate having an input that is coupled to an output of the seventh AI gate; and a fourth inverter having an input that is coupled to an output of the eighth AI gate, wherein an output of the fourth inverter produces a B clock signal and an output of the third AI gate produces a C clock signal that is frequency and phase controlled by the high speed clock frequency-divider/splitter.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field The present disclosure relates in general to the field of electronics, and in particular to timing clocks in electronic circuits. Still more particularly, the present disclosure relates to a clock splitter having an integrated clock frequency-divider. 2. Description of the Related Art Timing of clock signals in an electronic circuit, including an Integrated Circuit (IC), is essential to proper operations of the circuit. Timing problems arise, however, when components of the IC are physically spaced far apart. In such scenarios, a clock signal from one component will be time-delayed before it reaches another component. If the two components have a synchronous relationship, then problems will ensue. For example, consider the circuit shown in FIG. 1 . An oscillator 100 generates a 1.0 GHz clock signal. While this clock signal frequency is useful in many components of a circuit, other components may need a lower frequency clock signal. To obtain a lower frequency, a clock frequency-divider 102 is utilized. In the example shown, clock frequency-divider 102 suppresses every other clock waveform, thus created a clock signal that has a frequency of 0.5 GHz (500 MHz). The two (different frequency) clock signals are then sent to clock splitters 104 a - b, which output two clock signals (ZC and ZB), which have the same frequency as the respective input clock signal, but are time shifted. This allows the slave latch B and the master latch C in the Shift Register Latch (SRL) 106 a - e to launch and capture data stored in these elements. For example, the clock signal ZB from clock splitter 104 a causes data in latch B from SRL 106 a to be launched to latch C in SRL 106 b. Clock signal ZC from clock splitter 104 a causes latch C in SRL 106 b to capture the data that was just launched from latch B in SRL 106 a. Similarly, clock signals ZC and ZB from clock splitter 104 a cause data to be launched and captured from latch 106 b to latch 106 c. Similarly, the clock signals ZC and ZB in clock splitter 104 b cause data to be launched and captured from latch B in SRL 106 d to latch C in SRL 106 e. Assume that data captured in latches 106 c and 106 e are synchronously dependent. That is, assume that data must be captured (or launched) from these two latches at exactly the same time. Alternatively, latches 106 c and 106 e may be directly or indirectly coupled. If so, then the timing between these two latches must be perfectly synchronized. However, because of the distance (and distance differences) between oscillator 100 and latches 106 c and 106 e, such signal synchronization is difficult, if not impossible, to achieve.	<SOH> SUMMARY OF THE INVENTION <EOH>To address the problem described above, presented herein is a novel clock splitter that has a local internal clock frequency-divider. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that has a lower frequency than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider can also selectively suppress pulses in the B clock to generate a correspondingly slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree. The above, as well as additional, purposes, features, and advantages of the present invention will become apparent in the following detailed written description.	BACKGROUND OF THE INVENTION 1. Technical Field The present disclosure relates in general to the field of electronics, and in particular to timing clocks in electronic circuits. Still more particularly, the present disclosure relates to a clock splitter having an integrated clock frequency-divider. 2. Description of the Related Art Timing of clock signals in an electronic circuit, including an Integrated Circuit (IC), is essential to proper operations of the circuit. Timing problems arise, however, when components of the IC are physically spaced far apart. In such scenarios, a clock signal from one component will be time-delayed before it reaches another component. If the two components have a synchronous relationship, then problems will ensue. For example, consider the circuit shown in FIG. 1. An oscillator 100 generates a 1.0 GHz clock signal. While this clock signal frequency is useful in many components of a circuit, other components may need a lower frequency clock signal. To obtain a lower frequency, a clock frequency-divider 102 is utilized. In the example shown, clock frequency-divider 102 suppresses every other clock waveform, thus created a clock signal that has a frequency of 0.5 GHz (500 MHz). The two (different frequency) clock signals are then sent to clock splitters 104a-b, which output two clock signals (ZC and ZB), which have the same frequency as the respective input clock signal, but are time shifted. This allows the slave latch B and the master latch C in the Shift Register Latch (SRL) 106a-e to launch and capture data stored in these elements. For example, the clock signal ZB from clock splitter 104a causes data in latch B from SRL 106a to be launched to latch C in SRL 106b. Clock signal ZC from clock splitter 104a causes latch C in SRL 106b to capture the data that was just launched from latch B in SRL 106a. Similarly, clock signals ZC and ZB from clock splitter 104a cause data to be launched and captured from latch 106b to latch 106c. Similarly, the clock signals ZC and ZB in clock splitter 104b cause data to be launched and captured from latch B in SRL 106d to latch C in SRL 106e. Assume that data captured in latches 106c and 106e are synchronously dependent. That is, assume that data must be captured (or launched) from these two latches at exactly the same time. Alternatively, latches 106c and 106e may be directly or indirectly coupled. If so, then the timing between these two latches must be perfectly synchronized. However, because of the distance (and distance differences) between oscillator 100 and latches 106c and 106e, such signal synchronization is difficult, if not impossible, to achieve. SUMMARY OF THE INVENTION To address the problem described above, presented herein is a novel clock splitter that has a local internal clock frequency-divider. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that has a lower frequency than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider can also selectively suppress pulses in the B clock to generate a correspondingly slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree. The above, as well as additional, purposes, features, and advantages of the present invention will become apparent in the following detailed written description. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further purposes and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, where: FIG. 1 depicts a prior art circuit having a clock frequency-divider that is distant from a clock splitter; FIG. 2 illustrates a high level conceptual figure describing a novel clock splitter (“splitter”) having an internal clock frequency-divider; FIG. 3 depicts circuitry for an exemplary high speed clock splitter (“splitter”) with an internal clock frequency-divider; FIGS. 4-5 are timing charts for the high speed clock splitter shown in FIG. 3; FIG. 6 illustrates circuitry for an alternative embodiment of a high speed clock splitter (“splitter”) that allows suppression of timing-selected B clock signals being output, as shown in FIG. 7; FIG. 8 depicts circuitry for an alternative embodiment of a high speed clock splitter that includes additional C clock signal chopping capability; FIG. 9 illustrates circuitry for a high speed clock splitter that utilizes pulsing a DATA input to allow functional clock division; FIG. 10 depicts the circuitry shown in FIG. 9 with additional circuitry for suppressing the C clock; FIG. 11 illustrates the circuitry shown in FIG. 10 with additional circuitry for suppressing the B clock; and FIG. 12 depicts an exemplary computer in which the clock splitter described herein may be incorporated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 2, a high-level overview of an inventive splitter 200 is presented. In a preferred embodiment, splitter 200 is at a leaf (termination point) of a clock tree. That is, in a preferred embodiment, splitter 200 provides clocking signals that are only used locally, and are not promulgated to other branches in a clock tree. A clock signal is generated by an oscillator 100. For exemplary purposes, the frequency of the clock signal is shown as 1.0 GHz, but oscillator (OSC) 100 is understood as being capable of generating any fixed frequency clock signal. The oscillator clock signal is split into a B clock signal and a C clock signal by an OSC clock splitter 210. From the OSC clock splitter 210, the B and C clock signals are sent to a clock frequency-divider 204, which is under the control of a frequency control signal 202. The B and C clock signals are preferably chopped such that they have a same frequency, although, alternatively, the B and C clock signals can be chopped independently such that the B and C clock signals have different frequencies. Clock frequency-divider 204 preferably “chops” (removes/suppresses) intermediary clock waveforms to reduce (divide) the frequency of the 1.0 GHz clock signal (e.g., down to 0.5 GHz or 0.33 GHz). Note, however, that the frequency control signal 202 may simply tell clock frequency-divider 204 to allow the 1.0 GHz clock signal to pass through clock frequency-divider 204 unaltered (still at 1.0 GHz). In either case, the B and C clock signals (altered or unaltered) are then sent to a B/C clock order logic 206, which is under the control of a B/C order control signal 208. B/C order control signal 208 directs B/C clock order logic 206 to time-shift the B and C clock signals such that the B clock signal is time/phase shifted before or after the C clock signal. The scenario shown in FIG. 2 permits the B and C clock signals to have the same or different frequencies. Alternatively, the clock frequency-divider 204 can be placed before the OSC clock splitter 210, such that the B and C clock signals are always at the same frequencies. FIG. 3 depicts additional detail of an exemplary splitter 300, whose function substantially comports with that described at a high-level for splitter 200 shown in FIG. 2. Splitter 300 inputs and outputs various signals, which are named and defined as follows: ZC—“C clock,” which is a split output clock, and may be used to clock “capture” data into the master latch of a SRL ZB—“B clock,” which is a split output clock, and may be used to clock “launch” data out of the slave latch of a SRL BC—control signal that determines whether ZC leads or lags ZB (in time or phase) CGTN—C clock gate not—inverse logic signal that controls the release of the C clock at ZC CSUP—signal for controlling the suppression intermediate, starting, or ending waveforms of the “C clock” D—scan data input, which also functions as a speed controller, which controls whether output clocks (at ZC and ZB) have a frequency that is at full speed, half speed, third speed, etc. FVGTN—fixed value gate not—inverse logic signal that allows the D speed controller to be overridden, such that clocks in the rest of the design are allowed to run at full speed LSSDC—level-sensitive scan design (LSSD) C clock controller, which affords control of Shift Register Latches (SRLs), found in the splitter 300, and fed through the ZC pin in accordance with LSSD protocol OSC—oscillator, fixed speed clock generator BGTN—B clock gate not—inverse logic signal that controls the release of the B clock at ZB, disabling the internal splitter latch control LSSDB—level-sensitive scan design (LSSD) B clock controller, which affords control of Shift Register Latches (SRLs), found in the splitter 300, and fed through the ZB pin in accordance with LSSD protocol SDO—scan data out—output of scan data that is passing through splitter 300 BSUP—signal for controlling the suppression intermediate, starting, or ending waveforms of the “B clock” (shown in FIG. 6) Referring again FIG. 3, BC is input into an inverter 331, which outputs to an AND Inverted (AI) gate 302. (Note that an AI gate is logically equivalent to a NAND gate.) Based on the value of BC, an output from AI gate 302 to AI gate 304 causes the C clock at ZC output pin 310 to pulse before the B clock at ZB output pin 312. That is, due to the configuration of different AI gates and other logic shown, BC as a low signal will cause a different delay to ZC compared to BC being a high signal. AI gate 302 also receives input signals from Shift Register Latch (SRL) 314, as well as from small chopper 328, which provides clock separation between the rising ZC edge and the falling ZB edge to ensure the master and slave clocks are not simultaneously active. AI 306 causes the C clock at ZC output pin 310 to pulse after the B clock at ZB output pin 312. Inputs to AI 306, which cause the C clock pulse to follow the B clock, include the output of small chopper 328, an output of AI 322 (whose inputs are discussed below), BC, and the output of SRL 316 (which can also be the Scan Data Out—SDO). CGTN is input to AI 304, thus permitting the C clock to be pulsed from ZC output pin 310 under the direction of AI 302 or AI 306. CSUP is input into AI 322, which causes C clock pulses to be suppressed in a controlled manner when combined with the output of SRL 314. Inputs to SRL 314 include input D, as well as inverted outputs of AI 324 and AI 326. Inputs to AI 324 include FVGTN and the output of small chopper 328. Input to the small chopper 328 is the output of AI 330, which has inputs of LSSDC and an inverted OSC clock signal. AI 330 thus provides a controlled input of raw signals which are cleaned up by small chopper 328. Note that the output of AI 330 also goes to the input of AI 326 and AI 318. Also input to AI 320 is BGTN and an inverted signal from the L1 latch in SRL 316, while AI 318 also receives LSSDB as an input. Output from AI 318 is a clock signal that, after being inverted by inverter 329, is put on ZB output pin 312. Note that in a conventional LSSD system, separate system and scan clocks are used to distinguish between normal operations and test mode. During normal operations, latches are used in pairs, wherein each has a normal data input, data output and clock. During test operations, however, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks (usually denoted as A and B), which are held low during system operations but cause the scan data to be latched when pulsed high during scan. In splitter 300, however, AI 318 allows scan gating via BGTN and functional gating from SRL 316. Thus, the LSSDB test clock signal is allowed to be shared for both normal functional test operations as well as scan operations (test mode), thus eliminating the need for a separate test clock input. Utilizing the inputs described above, SRLs 314 and 316 are used for clock gating. That is, SRLs 314 and 316 provide a tight timing path that closely synchronizes the relative temporal positions of the B and C clock outputs from respective ZB output pin 312 and ZC output pin 310. Note the existence of inverters 321, 323, 325, 327, 329, and 331, which may or may not have been described above, but which are utilized to provide appropriate inversion of inputs to components depicted. Referring now to FIG. 4, a timing chart 400 is presented showing the resulting C and B clocks at respective ZC output pin 310 and ZB output pin 312. At full speed (when D stays high and CSUP low), the B and C pulses are 180 degrees out of phase. However, when the D input is as shown, then one (for half speed) or two (for third speed) intermediate pulses for the C clock are suppressed. Note that intermediate pulses for the B clock are similarly suppressed so that the B follows the C clock pulses, allowing more cycle time from B to following C. Note also that, since splitter 300 serves as a suppression clock frequency-divider, pulse width is the same at all speeds, but duty cycle is reduced as a percentage of cycle time. Note also that all of the clock signals (full, half, third) are full cycle timed paths, while the half cycle clock gating paths are contained within the splitter from the SRLs 314 and 316. FIG. 5 shows timing chart 500, which depicts the timing of pulses when splitter 300 is used in at-speed testing (e.g., as part of an LBIST system). The ZC leading ZB clock timing (ZC→ZB) is rarely used. However, ZB leading ZC is often used, as in launching and capturing data from latches in SRLs. Note the extra ZB pulses for the divided clocks. The first B controls the data release from an SRL slave latch, with each subsequent ZB not changing the data. The timed path is therefore from the first ZB pulse to the only ZC pulse. This design, however, must time the final ZB versus the ZC to ensure that there is no pulse overlap. To avoid this problem, additional AIs 602 and 604 are added, as shown in the splitter 600 shown in FIG. 6. AI 602 has inputs from the inverted output of the L1 latch in SRL 316, the non-inverted output of the L1 latch in SRL 314, and BSUP, while AI 604 has inputs from the non-inverted output of the L1 latch of SRL 316 and the inverted BSUP signal. The output of AI 604 feeds into AI 320, which outputs to AI 318 in a manner described above for splitter 300. AIs 602 and 604 allow suppression of trailing ZB pulses during the ZB→ZC test, as shown in the timing chart 700 shown in FIG. 7. With reference now to FIG. 8, a splitter 800 is depicted. Splitter 800 has similar splitter/clock frequency-divider functionality as described above for splitter 300, but with an additional ZC chopping feature that is often useful in feeding Low Power Register Array (LPRA) clocks. Specifically, a chopper 802 includes a chop value 806 and two AIs 804 and 808. Test signals 1 and 2 are fed into respective AIs 804 and 808, thus providing exclusive paths for testability. FIGS. 9, 10, and 11 show another way to accomplish the functionality of splitter 800, but with a larger design. Referring now to FIG. 9, a splitter 900 is presented. A BC signal, via an inverter 901, is fed into an AI 902, which also has inputs from C Clock Gate 1 (CCLKGT1) and the outputs of AI 908, AI 918 and SRL 914. AI 906 has inputs from the BC signal, C Clock Gate 1 (CCLKGT1), Scan Data Out (SDO), and the outputs of AI 908 and AI 918. AI 904 has inputs from the ZC gate (GATEZC) and the outputs of AI 902 and AI 906. The output of AI 904 is the C clock found at ZC pin 910. A test control (TST2) signal is input to AI 908. A test control (TST1) is input into AI 918, along with an output of a chopper 928. The chopper 928 has a single input from the Oscillator (OSC) via an inverter 932. The output of inverter 932 also feeds an input to a delay 930, which feeds the input of an AI 924 as well as an AI 920. Using the SDO, output of delay 930, and a B clock gate (BCLKGT), AI 920, along with AI 922 (which includes an LSSD B Clock input (LSSDBCLK_NI) generates a B clock signal found at ZB pin 912. Note further that an output of AI 918 is input to AI 934, which outputs to inverter 903, which outputs to SRL 916. Note also that AI 924 outputs to an input of AI 926. AI gates 902, 906 and 904 allow the moving (time/phase shifting) of the ZC pulse (at ZC pin 910) to be before or after the ZB pulse (at ZB pin 912), thus generating a timing pattern such as that shown above in FIG. 4. However, suppression of the C clock pulses, as described above with splitter 300, is not possible using just the circuitry shown in FIG. 9. The splitter 1000, shown in FIG. 10, however, adds the C clock pulse suppression feature through the addition of an AI 1002, which accepts an input from a C suppression (CSUP) signal, which suppresses C clock pulses by suppressing C clock pulses at ZC pin 910. That is, the CSUP signal causes AI 1002 to block AI 906, which blocks 904 from pulsing unwanted C clock pulses. To provide suppression of B clock pulses, splitter 1100, shown in FIG. 11, includes additional AIs 1102 and 1104. As depicted, inputs to AI 1102 include a B clock suppression signal (BSUP) and the inverted output of the L1 latch in the SRL 914. The inputs to AI 1104 include the output of AI 1102, the inverted (BSUP) signal, and the L1 latch of SRL 916. AI 1102 and AI 1104 thus provide for suppression of B clock pulses (per the control of the BSUP signal), such as shown above in timing table 700 in FIG. 7. With reference now to FIG. 12, there is depicted a block diagram of a computer 1202, in which the present invention may be utilized. Computer 1202 includes a processor unit 1204 that is coupled to a system bus 1206. Within the circuitry of processor unit 1204 are one or more clock frequency-dividers/splitters, as described above in FIGS. 3, 6, 8-12, such that the logic shown in FIG. 12 is used to adjust the timing of clock signals used within processor 1204. Alternatively, the logic and software depicted for computer 1202 is used to control clock dividers (such as those depicted in FIGS. 3, 6, 8-12) in other (not shown) circuits. A video adapter 1208, which drives/supports a display 1210, is also coupled to system bus 1206. System bus 1206 is coupled via a bus bridge 1212 to an Input/Output (I/O) bus 1214. An I/O interface 1216 is coupled to I/O bus 1214. I/O interface 1216 affords communication with various I/O devices, including a keyboard 1218, a mouse 1220, a Compact Disk—Read Only Memory (CD-ROM) drive 1222, a floppy disk drive 1224, and a flash drive memory 1226. The format of the ports connected to I/O interface 1216 may be any known to those skilled in the art of computer architecture, including but not limited to Universal Serial Bus (USB) ports. Computer 1202 is able to communicate with a software deploying server 1250 via a network 1228 using a network interface 1230, which is coupled to system bus 1206. Network 1228 may be an external network such as the Internet, or an internal network such as an Ethernet or a Virtual Private Network (VPN). A hard drive interface 1232 is also coupled to system bus 1206. Hard drive interface 1232 interfaces with a hard drive 1234. In a preferred embodiment, hard drive 1234 populates a system memory 1236, which is also coupled to system bus 1206. System memory is defined as a lowest level of volatile memory in computer 1202. This volatile memory includes additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers. Data that populates system memory 1236 includes computer 1202's operating system (OS) 1238 and application programs 1244. OS 1238 includes a shell 1240, for providing transparent user access to resources such as application programs 1244. Generally, shell 1240 is a program that provides an interpreter and an interface between the user and the operating system. More specifically, shell 1240 executes commands that are entered into a command line user interface or from a file. Thus, shell 1240 (as it is called in UNIX®), also called a command processor in Windows®, is generally the highest level of the operating system software hierarchy and serves as a command interpreter. The shell provides a system prompt, interprets commands entered by keyboard, mouse, or other user input media, and sends the interpreted command(s) to the appropriate lower levels of the operating system (e.g., a kernel 1242) for processing. Note that while shell 1240 is a text-based, line-oriented user interface, the present invention will equally well support other user interface modes, such as graphical, voice, gestural, etc. As depicted, OS 1238 also includes kernel 1242, which includes lower levels of functionality for OS 1238, including providing essential services required by other parts of OS 1238 and application programs 1244, including memory management, process and task management, disk management, and mouse and keyboard management. Application programs 1244 include a browser 1246. Browser 1246 includes program modules and instructions enabling a World Wide Web (WWW) client (i.e., software deploying server 1250) to send and receive network messages to the Internet using HyperText Transfer Protocol (HTTP) messaging, thus enabling communication with computer 1202. In one embodiment of the present invention, software deploying server 1250 may utilize a same or substantially similar architecture as shown and described for computer 1202. Also stored with system memory 1236 is a Timing Pattern Program (TPP) 1248, which includes some or all software code needed to control the clock frequency-divider/splitters described above, including some or all of the signal inputs described above. TPP 1248 may be deployed from software deploying server 1250 to client computer 1202 in any automatic or requested manner, including being deployed to client computer 1202 in an on-demand basis. Similarly, TPP 1248 may be deployed to software deploying server 1250 from another software deploying server (not shown). The hardware elements depicted in computer 1202 are not intended to be exhaustive, but rather are representative to highlight essential components required by the present invention. For instance, computer 1202 may include alternate memory storage devices such as magnetic cassettes, Digital Versatile Disks (DVDs), Bernoulli cartridges, and the like. These and other variations are intended to be within the spirit and scope of the present invention. It should be understood that at least some aspects of the present invention may alternatively be implemented in a program product. Programs defining functions of the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., a floppy diskette, hard disk drive, read/write CD ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore in such signal-bearing media when carrying or encoding computer readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent. The presently presented splitter thus provides for a suppression style clock frequency-divider function that is built into the splitter. This allows for the use of a common oscillator clock signal to use different speed domains, easing timing on designs by enabling more opportunity for Common Path Pessimism Removal (CPPR), while still supporting LSSD at speed clock gating for LBIST through C and B clock suppression and relative phase adjustment (ZC→ZB or ZB→ZC). Specifically, one embodiment of the presently described clock splitter (as shown in an exemplary embodiment in FIG. 2 as splitter 200) comprises an oscillator clock splitter (210), wherein the oscillator clock splitter (210) splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider (204), wherein the clock frequency-divider (204) selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic (206), wherein the B/C clock order logic (206) phase shifts the C clock relative to a B clock. The clock frequency-divider (204) may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter (200) is located at a terminal leaf of a clock tree. In one embodiment, the novel clock frequency-divider/splitter is incorporated into a computer system. As described in an exemplary embodiment in FIG. 3 and FIG. 12, the novel clock frequency-divider/splitter is incorporated into a processor (1204) in a computer system (1202) that comprises a data bus (1206) coupled to the processor (1204); and a memory (1236) coupled to the data bus (1206). In exemplary form, the high speed clock frequency-divider/splitter (see FIG. 3) comprises: first (302) and second (306) AND Inverted (AI) gates that are coupled to a third AI gate (304); a fourth AI gate (330) coupled to an input of a chopper (328), wherein the chopper (328) has an output that is coupled to a fifth AI gate (324) and the first (302) and second (306) AI gates; a sixth AI gate (326) that is coupled to an output of the fourth AI gate (330), wherein an output of the AI gate (326) is coupled to an input of a first inverter (325); a second inverter (323) having an input that is coupled to an output of the fifth AI gate (324), wherein outputs of the first (325) and second (323) inverters are coupled to a first Shift Register Latch (SRL) (314), and wherein the output of the first inverter (325) is also coupled to an input of second SRL (316), and wherein the output of the second inverter (323) is also coupled to an input of a third inverter (327); a seventh AI gate (320) having an input that is coupled to an output of the third inverter (327); an eighth AI gate (318) having an input that is coupled to an output of the seventh AI gate (320); a fourth inverter (329) having an input that is coupled to an output of the eighth AI gate (318), wherein an output of the fourth inverter (329) produces a B clock signal and an output of the third AI gate (304) produces a C clock signal that are frequency and phase controlled by the high speed clock frequency-divider/splitter. In one embodiment, control of and signals to the novel clock frequency-divider/splitter is provided by a computer readable medium on which computer program instructions are stored. As depicted in FIG. 3, in one embodiment, a high speed clock frequency-divider/splitter comprises: a first AND Inverted (AI) gate having an input that is coupled to an inverted BC clock order control signal (BC signal), wherein the BC signal determines a time-phase order between a B clock and a C clock that are output from the high speed clock leaf clock frequency-divider/splitter; a second AI gate having inputs that are coupled to the BC signal and a chopped oscillator signal; a third AI gate having inputs from an output of the first AI gate and an output of the second AI gate, wherein the third AI gate outputs the C clock; a fourth AI gate having inputs from the chopped oscillator signal and a B clock gate; and a fifth AI gate having inputs from an output of the fourth AI gate and a Level-Sensitive Scan Design (LSSD) C clock control signal (LSSDC), wherein the fifth AI outputs the B clock. The high speed clock leaf clock frequency-divider/splitter may further comprise: a sixth AI gate having an input that is coupled to a C clock suppression signal (CSUP), wherein the CSUP selectively suppresses C clock pulses to generate a clock signal having a lower frequency than the chopped oscillator signal; and a seventh AI gate having an input that is coupled to a B clock suppression signal (BSUP), wherein the BSUP selectively suppresses B clock pulses to generate a clock signal having a lower frequency than the chopped oscillator signal. In one embodiment, this high speed clock frequency-divider/splitter is located at a terminal leaf of a clock tree. As depicted in exemplary form in FIGS. 8-11, in another embodiment a high speed clock leaf clock frequency-divider/splitter comprises: a first inverter having inputs that are coupled to a BC (B/C clock order) signal, an output of a first Shift Register Latch (SRL), and an output of a chopper, wherein the first SRL has inputs from a speed control signal that is part of a scan data input (D); a second AI having inputs that are coupled to the output of the chopper, an output of a third AI, the BC signal, and a Scan Data Out (SDO) from a second SRL that is coupled to the first SRL, wherein the third AI has inputs that are coupled to a C clock suppression signal (CSUP) and the output of the first SRL; a fourth AI having inputs that are coupled to an output of the first AI, an output of the second AI, and a clock gate not (CGTN) inverse logic signal that controls a release of a C clock signal at a C clock pin that is coupled to an output of the fourth AI; a second inverter having an input that is coupled to an Oscillator (OSC) clock; a fifth AI having inputs coupled to a Level-Sensitive Scan Design (LSSD) C clock control signal (LSSDC) and an output of the second inverter, wherein an output of the first AI is coupled to an input to the chopper, an input to a sixth AI and an input to a seventh AI, wherein the seventh AI has additional inputs that are coupled to a B clock gate not (BGTN) inverse logic signal that controls a release of a B clock at a C clock pin that is coupled to an output of a third inverter, wherein the third inverter has an input that is coupled to the seventh AI; an eighth AI having a first input coupled to a fixed value gate not (FVGTN) inverse logic signal that is capable of overriding the data input (D) signal, wherein the eighth AI has a second input coupled to the output of the chopper, and wherein the FVGTN inverse logic signal is also coupled to an input to the sixth AI; a fourth inverter coupling an output of the eighth AI to an input to an L1 latch in the first SRL; and a fifth inverter coupling an output of the sixth AI to an L2 latch in the first SRL, wherein an output of the L2 latch in the first SRL is coupled to an input of the first L1 latch in the second SRL, and wherein the output of the first L1 latch in the second SRL is coupled to an input of a ninth AI via a sixth inverter, and wherein the ninth AI has an input coupled to a B gate not (BGTN) inverse logic signal that controls a release of a B clock at a ZB pin, and wherein an output of the ninth AI is coupled to an input of the seventh AI, and wherein a level-sensitive scan design B clock controller (LSSDB) is input to the seventh AI, wherein the high speed clock leaf clock frequency-divider/splitter controls a speed and phase of output B and C clocks through a use of the BC, CGTN, CSUP, D, FVGTN, LSSDC, OSC, BGTN and LSSDB signals. In this embodiment, the clock splitter may be located at a terminal leaf of a clock tree. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.	G	60G06	161G06F	1	10
11867726	US20090094357A1-20090409	ROGUE ROUTER HUNTER	ACCEPTED	20090325	20090409	[]	G06F1516	["G06F1516"]	7991877	20071005	20110802	709	224000	57270.0	KHAJURIA	SHRIPAL	[{"inventor_name_last": "Keohane", "inventor_name_first": "Susann Marie", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "McBrearty", "inventor_name_first": "Gerald Francis", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Mullen", "inventor_name_first": "Shawn Patrick", "inventor_city": "Buda", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Murillo", "inventor_name_first": "Jessica Carol", "inventor_city": "Round Rock", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Shieh", "inventor_name_first": "Johnny Meng-Han", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}]	A computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. The process in the illustrative embodiments first obtains a physical address of a suspected router or destination device. A data packet is created which comprises at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit. The data packet is sent to the destination device using the physical address in the destination media access control field. If a time exceeded message is received from the destination device, the destination device is determined to be enabled for routing.	1. A computer implemented method for detecting unauthorized routers in a distributed network, the computer implemented method comprising: obtaining a physical address of a destination device; creating a data packet comprising at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit; sending the data packet to the destination device using the physical address in the destination media access control field; and responsive to receiving a time exceeded message from the destination device, determining that the destination device is enabled for routing. 2. The computer implemented method of claim 1, further comprising: responsive to a failure to receive a time exceeded message from the destination device, determining that the destination device is not enabled for routing. 3. The computer implemented method of claim 1, wherein the physical address of the destination device is the media access control address of a network interface card in the destination device. 4. The computer implemented method of claim 1, wherein the data packet further comprises a source media access control field comprising a physical address of a source device and a source internet protocol field comprising an internet protocol address of the source device. 5. The computer implemented method of claim 1, wherein the destination device examines the destination internet protocol address in the data packet, determines if the destination internet protocol address in the data packet matches the internet protocol address of the destination device, examines the value in the time-to-live field in the data packet if routing is enabled on the destination device, and sends the time exceeded message to the internet protocol address in the source internet protocol address field if the value indicates the data packet has exceeded a time limit. 6. The computer implemented method of claim 5, wherein the destination device discards the data packet if routing is not enabled on the destination device. 7. The computer implemented method of claim 1, wherein the determination that the destination device is enabled for routing is performed when the internet protocol address for the destination device is unknown. 8. The computer implemented method of claim 1, wherein the determination that the destination device is enabled for routing is performed when the internet protocol addresses for devices on a subnet of the destination device are unknown. 9. The computer implemented method of claim 8, wherein the devices are offline or powered off. 10. The computer implemented method of claim 1, wherein the physical address of the destination device is obtained using one of a ping utility or an Address Resolution Protocol. 11. A data processing system for detecting unauthorized routers in a distributed network, the data processing system comprising: a bus; a storage device connected to the bus, wherein the storage device contains computer usable code; at least one managed device connected to the bus; a communications unit connected to the bus; and a processing unit connected to the bus, wherein the processing unit executes the computer usable code to obtain a physical address of a destination device; create a data packet comprising at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit; send the data packet to the destination device using the physical address in the destination media access control field; and determine that the destination device is enabled for routing in response to receiving a time exceeded message from the destination device. 12. A computer program product for detecting unauthorized routers in a distributed network, the computer program product comprising: a computer usable medium having computer usable program code tangibly embodied thereon, the computer usable program code comprising: computer usable program code for obtaining a physical address of a destination device; computer usable program code for creating a data packet comprising at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit; computer usable program code for sending the data packet to the destination device using the physical address in the destination media access control field; and computer usable program code for determining that the destination device is enabled for routing in response to receiving a time exceeded message from the destination device. 13. The computer program product of claim 12, further comprising: computer usable program code for determining that the destination device is not enabled for routing in response to a failure to receive a time exceeded message from the destination device. 14. The computer program product of claim 12, wherein the physical address of the destination device is the media access control address of a network interface card in the destination device. 15. The computer program product of claim 12, wherein the data packet further comprises a source media access control field comprising a physical address of a source device and a source internet protocol field comprising an internet protocol address of the source device. 16. The computer program product of claim 12, wherein the destination device examines the destination internet protocol address in the data packet, determines if the destination internet protocol address in the data packet matches the internet protocol address of the destination device, examines the value in the time-to-live field in the data packet if routing is enabled on the destination device, and sends the time exceeded message to the internet protocol address in the source internet protocol address field if the value indicates the data packet has exceeded a time limit. 17. The computer program product of claim 16, wherein the destination device discards the data packet if routing is not enabled on the destination device. 18. The computer program product of claim 12, wherein the determination that the destination device is enabled for routing is performed when the internet protocol address for the destination device is unknown or when the internet protocol addresses for devices on a subnet of the destination device are unknown. 19. The computer program product of claim 18, wherein the devices are offline or powered off. 20. The computer program product of claim 12, wherein the physical address of the destination device is obtained using one of a ping utility or an Address Resolution Protocol.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates generally to an improved data processing system, and in particular to a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. 2. Description of the Related Art Distributed network data processing systems are becoming more and more prevalent in businesses and in homes. Typically, a network data processing system contains a network with a medium used to provide communications links between various devices and computers connected within that network. This medium includes wires providing communications links with other devices, such as a router providing routing of data between the different devices on the network. One protocol used to transmit data within a network is the transmission control protocol/internet protocol (TCP/IP). This protocol is used on the Internet and also may be implemented in other networks, such as an intranet, a local area network (LAN), or a wide area network (WAN). TCP provides transport functions to ensure that the total amount of bytes sent is received correctly at the other end. IP is used to accept packets from TCP and adds a header to deliver the packet to a data link layer protocol. An IP address is used by every client and server in the network to send data between the different systems. A router is a device that determines the proper path for data to travel between different networks (i.e., separate logical subnets). The router forwards data packets to the next device along this path. A router may create or maintain a table of the available routes and their conditions and use this information to determine the best route for a given packet. In the world of security, an unauthorized router in an organization's network is known as a rogue router. These unauthorized routers are not monitored, nor are the machines on the router's subnets. Organizations do not want unauthorized routers running on their networks since there are a number of security concerns associated with these routers. A client device in the network may become a rogue router even if the user does not have malicious intent. For example, if the user connects a laptop computer to the client device and uses a modem to access e-mail via the Internet, the modem becomes an unauthorized router. The user's laptop can even serve as a router if the operating system on the laptop includes a router function, and the function is enabled. This scenario creates security problems since the user's laptop comprises a weaker firewall than an authorized router. Consequently, it is desirable for a network security administrator to be able to detect unauthorized routers and cease their operation. When a packet is sent from one computer to another, it traverses zero or more routers. The sequence of routers that a packet traverses is termed its route, or path. The traversal of one router is called a hop. In the current art, the traceroute utility may be used to detect routers in the network by recording the route through the distributed network between a source machine and a specified destination machine. If the destination machine is active and a monitoring tool in the source machine is in a position to ping the destination machine's IP address, it is possible to detect the router(s) between the source machine and the destination machine. The traceroute command operates by sending a series of packets (using the Internet Control Message Protocol or ICMP) to the target destination machine. A first packet is constructed with a limited Time-To-Live (TTL) value that is designed to be exceeded by the first router that receives the packet for the first hop. For instance, the TTL value in the first packet has a value of 1. When the first router encounters the packet with the TTL value of 1, the first router is obligated to send an ICMP Time Exceeded message (type 11) back to the sending source machine. The sending source machine also sends other packets comprising a Time-To-Live (TTL) value of 2 for the second hop, then a Time-To-Live (TTL) value of 3 for the third hop, etc. Consequently, each router in the path will respond with a type 11 packet between the sending source machine and the destination machine. When the final destination machine responds to a packet, the process stops. While the traceroute utility may be used for detecting routers in the network, a problem with the traceroute utility is that a network administrator is unable to discover whether a machine is routing if the routed subnet is not known or if the machines on the router's subnet are silent or down. Thus, utilities in the current art such as traceroute only allow for discovering if a machine is a router if the source machine knows the IP addresses of the subnet or the IP addresses of the machines in the subnet.	<SOH> SUMMARY OF THE INVENTION <EOH>The illustrative embodiments provide a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. The process in the illustrative embodiments first obtains a physical address of a suspected router or destination device. A data packet is created which comprises at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit. The data packet is sent to the destination device using the physical address in the destination media access control field. If a time exceeded message is received from the destination device, the destination device is determined to be enabled for routing.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to an improved data processing system, and in particular to a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. 2. Description of the Related Art Distributed network data processing systems are becoming more and more prevalent in businesses and in homes. Typically, a network data processing system contains a network with a medium used to provide communications links between various devices and computers connected within that network. This medium includes wires providing communications links with other devices, such as a router providing routing of data between the different devices on the network. One protocol used to transmit data within a network is the transmission control protocol/internet protocol (TCP/IP). This protocol is used on the Internet and also may be implemented in other networks, such as an intranet, a local area network (LAN), or a wide area network (WAN). TCP provides transport functions to ensure that the total amount of bytes sent is received correctly at the other end. IP is used to accept packets from TCP and adds a header to deliver the packet to a data link layer protocol. An IP address is used by every client and server in the network to send data between the different systems. A router is a device that determines the proper path for data to travel between different networks (i.e., separate logical subnets). The router forwards data packets to the next device along this path. A router may create or maintain a table of the available routes and their conditions and use this information to determine the best route for a given packet. In the world of security, an unauthorized router in an organization's network is known as a rogue router. These unauthorized routers are not monitored, nor are the machines on the router's subnets. Organizations do not want unauthorized routers running on their networks since there are a number of security concerns associated with these routers. A client device in the network may become a rogue router even if the user does not have malicious intent. For example, if the user connects a laptop computer to the client device and uses a modem to access e-mail via the Internet, the modem becomes an unauthorized router. The user's laptop can even serve as a router if the operating system on the laptop includes a router function, and the function is enabled. This scenario creates security problems since the user's laptop comprises a weaker firewall than an authorized router. Consequently, it is desirable for a network security administrator to be able to detect unauthorized routers and cease their operation. When a packet is sent from one computer to another, it traverses zero or more routers. The sequence of routers that a packet traverses is termed its route, or path. The traversal of one router is called a hop. In the current art, the traceroute utility may be used to detect routers in the network by recording the route through the distributed network between a source machine and a specified destination machine. If the destination machine is active and a monitoring tool in the source machine is in a position to ping the destination machine's IP address, it is possible to detect the router(s) between the source machine and the destination machine. The traceroute command operates by sending a series of packets (using the Internet Control Message Protocol or ICMP) to the target destination machine. A first packet is constructed with a limited Time-To-Live (TTL) value that is designed to be exceeded by the first router that receives the packet for the first hop. For instance, the TTL value in the first packet has a value of 1. When the first router encounters the packet with the TTL value of 1, the first router is obligated to send an ICMP Time Exceeded message (type 11) back to the sending source machine. The sending source machine also sends other packets comprising a Time-To-Live (TTL) value of 2 for the second hop, then a Time-To-Live (TTL) value of 3 for the third hop, etc. Consequently, each router in the path will respond with a type 11 packet between the sending source machine and the destination machine. When the final destination machine responds to a packet, the process stops. While the traceroute utility may be used for detecting routers in the network, a problem with the traceroute utility is that a network administrator is unable to discover whether a machine is routing if the routed subnet is not known or if the machines on the router's subnet are silent or down. Thus, utilities in the current art such as traceroute only allow for discovering if a machine is a router if the source machine knows the IP addresses of the subnet or the IP addresses of the machines in the subnet. SUMMARY OF THE INVENTION The illustrative embodiments provide a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. The process in the illustrative embodiments first obtains a physical address of a suspected router or destination device. A data packet is created which comprises at least a destination media access control field, a destination internet protocol field, and a time-to-live field, wherein the destination media access control field comprises the physical address of the destination device, wherein the destination internet protocol field comprises a bogus internet protocol address, and wherein the time-to-live field comprises a value indicating the data packet has exceeded a time limit. The data packet is sent to the destination device using the physical address in the destination media access control field. If a time exceeded message is received from the destination device, the destination device is determined to be enabled for routing. BRIEF DESCRIPTION OF THE DRAWINGS The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: FIG. 1 depicts a pictorial representation of a distributed data processing system in which the illustrative embodiments may be implemented; FIG. 2 is a block diagram of a data processing system in which the illustrative embodiments may be implemented; FIG. 3 is a typical software architecture for a data processing system depicted in accordance with a preferred embodiment of the present invention; FIG. 4 is a diagram of a Transmission Control Protocol/Internet Protocol (TCP/IP) and similar protocols depicted in accordance with a preferred embodiment of the present invention; FIG. 5 is a block diagram of a rogue router hunter system for discovering unauthorized routers in accordance with the illustrative embodiments; FIG. 6 illustrates a packet created by the rogue router hunter in accordance with the illustrative embodiments; and FIG. 7 is a flowchart of a process for discovering unauthorized routers in accordance with the illustrative embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT With reference now to the figures and in particular with reference to FIGS. 1-2, exemplary diagrams of data processing environments are provided in which illustrative embodiments may be implemented. It should be appreciated that FIGS. 1-2 are only exemplary and are not intended to assert or imply any limitation with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environments may be made. FIG. 1 depicts a pictorial representation of a network of data processing systems in which illustrative embodiments may be implemented. Network data processing system 100 is a network of computers in which the illustrative embodiments may be implemented. Network data processing system 100 contains network 102, which is the medium used to provide communications links between various devices and computers connected together within network data processing system 100. Network 102 may include connections, such as wire, wireless communication links, or fiber optic cables. In the depicted example, server 104 and server 106 connect to network 102 along with storage unit 108. In addition, clients 110, 112, and 114 connect to network 102. Clients 110, 112, and 114 may be, for example, personal computers or network computers. In the depicted example, server 104 provides data, such as boot files, operating system images, and applications to clients 110, 112, and 114. Clients 110, 112, and 114 are clients to server 104 in this example. Network data processing system 100 may include additional servers, clients, and other devices not shown. In the depicted example, network data processing system 100 is the Internet with network 102 representing a worldwide collection of networks and gateways that use the Transmission Control Protocol/Internet Protocol (TCP/IP) suite of protocols to communicate with one another. At the heart of the Internet is a backbone of high-speed data communication lines between major nodes or host computers, consisting of thousands of commercial, governmental, educational and other computer systems that route data and messages. Of course, network data processing system 100 also may be implemented as a number of different types of networks, such as for example, an intranet, a local area network (LAN), or a wide area network (WAN). FIG. 1 is intended as an example, and not as an architectural limitation for the different illustrative embodiments. With reference now to FIG. 2, a block diagram of a data processing system is shown in which illustrative embodiments may be implemented. Data processing system 200 is an example of a computer, such as server 104 or client 110 in FIG. 1, in which computer usable program code or instructions implementing the processes may be located for the illustrative embodiments. In this illustrative example, data processing system 200 includes communications fabric 202, which provides communications between processor unit 204, memory 206, persistent storage 208, communications unit 210, input/output (I/O) unit 212, and display 214. Processor unit 204 serves to execute instructions for software that may be loaded into memory 206. Processor unit 204 may be a set of one or more processors or may be a multi-processor core, depending on the particular implementation. Further, processor unit 204 may be implemented using one or more heterogeneous processor systems in which a main processor is present with secondary processors on a single chip. As another illustrative example, processor unit 204 may be a symmetric multi-processor system containing multiple processors of the same type. Memory 206, in these examples, may be, for example, a random access memory. Persistent storage 208 may take various forms depending on the particular implementation. For example, persistent storage 208 may contain one or more components or devices. For example, persistent storage 208 may be a hard drive, a flash memory, a rewritable optical disk, a rewritable magnetic tape, or some combination of the above. The media used by persistent storage 208 also may be removable. For example, a removable hard drive may be used for persistent storage 208. Communications unit 210, in these examples, provides for communications with other data processing systems or devices. In these examples, communications unit 210 is a network interface card. Communications unit 210 may provide communications through the use of either or both physical and wireless communications links. Input/output unit 212 allows for input and output of data with other devices that may be connected to data processing system 200. For example, input/output unit 212 may provide a connection for user input through a keyboard and mouse. Further, input/output unit 212 may send output to a printer. Display 214 provides a mechanism to display information to a user. Instructions for the operating system and applications or programs are located on persistent storage 208. These instructions may be loaded into memory 206 for execution by processor unit 204. The processes of the different embodiments may be performed by processor unit 204 using computer implemented instructions, which may be located in a memory, such as memory 206. These instructions are referred to as, program code, computer usable program code, or computer readable program code that may be read and executed by a processor in processor unit 204. The program code in the different embodiments may be embodied on different physical or tangible computer readable media, such as memory 206 or persistent storage 208. Program code 216 is located in a functional form on computer readable media 218 and may be loaded onto or transferred to data processing system 200 for execution by processor unit 204. Program code 216 and computer readable media 218 form computer program product 220 in these examples. In one example, computer readable media 218 may be in a tangible form, such as, for example, an optical or magnetic disc that is inserted or placed into a drive or other device that is part of persistent storage 208 for transfer onto a storage device, such as a hard drive that is part of persistent storage 208. In a tangible form, computer readable media 218 also may take the form of a persistent storage, such as a hard drive or a flash memory that is connected to data processing system 200. Alternatively, program code 216 may be transferred to data processing system 200 from computer readable media 218 through a communications link to communications unit 210 and/or through a connection to input/output unit 212. The communications link and/or the connection may be physical or wireless in the illustrative examples. The computer readable media also may take the form of non-tangible media, such as communications links or wireless transmissions containing the program code. The different components illustrated for data processing system 200 are not meant to provide architectural limitations to the manner in which different embodiments may be implemented. The different illustrative embodiments may be implemented in a data processing system including components in addition to or in place of those illustrated for data processing system 200. Other components shown in FIG. 2 can be varied from the illustrative examples shown. For example, a bus system may be used to implement communications fabric 202 and may be comprised of one or more buses, such as a system bus or an input/output bus. Of course, the bus system may be implemented using any suitable type of architecture that provides for a transfer of data between different components or devices attached to the bus system. Additionally, a communications unit may include one or more devices used to transmit and receive data, such as a modem or a network adapter. Further, a memory may be, for example, memory 206 or a cache such as found in an interface and memory controller hub that may be present in communications fabric 202. Turning to FIG. 3, typical software architecture for a data processing system is depicted in accordance with the illustrative embodiments. This architecture may be implemented in a data processing system, such as data processing system 200 in FIG. 2. At the lowest level in software architecture 300, operating system 302 is utilized to provide high-level functionality to the user and to other software. Such an operating system typically includes a basic input output system (BIOS). Communication software 304 provides communications through an external port to a network such as the Internet via a physical communications link by either directly invoking operating system functionality or indirectly bypassing the operating system to access the hardware for communications over the network. Application programming interface (API) 306 allows the user of the system, an individual, or a software routine, to invoke system capabilities using a standard consistent interface without concern for how the particular functionality is implemented. Network access software 308 represents any software available for allowing the system to access a network. This access may be to a network, such as a local area network (LAN), wide area network (WAN), or the Internet. With the Internet, this software may include programs, such as Web browsers. Application software 310 represents any number of software applications designed to react to data through the communications port to provide the desired functionality the user seeks. The mechanism of the illustrative embodiments may be implemented within communication software 304 in these examples. FIG. 4 is a diagram of a Transmission Control Protocol/Internet Protocol (TCP/IP) and similar protocols depicted in accordance with the illustrative embodiments. TCP/IP and similar protocols are utilized by communications architecture 400. In this example, communications architecture 400 is a 4-layer system. This architecture includes application layer 402, transport layer 404, network layer 406, and link layer 408. Each layer is responsible for handling various communications tasks. Link layer 408 also is referred to as the data-link layer or the network interface layer and normally includes the device driver in the operating system and the corresponding network interface card in the computer. This layer handles all the hardware details of physically interfacing with the network media being used, such as optical cables or Ethernet cables. Network layer 406 also is referred to as the Internet layer and handles the movement of packets of data around the network. For example, network layer 406 handles the routing of various packets of data that are transferred over the network. Network layer 406 in the TCP/IP suite is comprised of several protocols, including Internet Protocol (IP), Internet control message protocol (ICMP), and Internet group management protocol (IGMP). Next, transport layer 404 provides an interface between network layer 406 and application layer 402 that facilitates the transfer of data between two host computers. Transport layer 404 is concerned with things, such as, for example, dividing the data passed to it from the application into appropriately sized chunks for the network layer below, acknowledging received packets, and setting timeouts to make certain the other end acknowledges packets that are sent. In the TCP/IP protocol suite, two distinctly different transport protocols are present, TCP and user datagram protocol (UDP). TCP provides reliability services to ensure that data is properly transmitted between two hosts, including dropout detection and retransmission services. Conversely, UDP provides a much simpler service to the application layer by merely sending packets of data called datagrams from one host to the other, without providing any mechanism for guaranteeing that the data is properly transferred. When using UDP, the application layer must perform the reliability functionality. Application layer 402 handles the details of the particular application. Many common TCP/IP applications are present for almost every implementation, including a Telnet for remote login, a file transfer protocol (FTP), a simple mail transfer protocol (SMTP) for electronic mail, and a simple network management protocol (SNMP). The mechanism of the illustrative embodiments may be implemented as a process within network layer 406. The illustrative embodiments provide a rogue router hunter system which detects potential security problems by discovering unauthorized routers in the network. An unauthorized router is a machine in which a routing function on the machine is intentionally or unintentionally enabled without being authorized by the network security administrator. In contrast with existing router detection methods such as the traceroute utility, the rogue router hunter system in the illustrative embodiments allows a network security administrator to determine if a machine is an unauthorized router when the IP addresses of the subnet the machine is routing are unknown and when the IP addresses of the machines on the subnet are unknown. This determination may be made even if the machines on the subnet are not powered on or online at the time of the determination. FIG. 5 is a block diagram of a rogue router hunter system for discovering unauthorized routers in accordance with the illustrative embodiments. In this example, the unauthorized routing device takes the form of suspected subnet router 502. Suspected subnet router 502 may be a machine having a routing function that is intentionally or unintentionally enabled. Suspected subnet router (SR) 502 contains a network interface card (NIC) in order to access an Ethernet. The network interface card in suspected subnet router 502 accesses the Ethernet using a media access control (MAC) address. A MAC address is a hardware address that uniquely identifies each node of a network. For example, each network interface card has a different MAC address. The MAC address for suspected subnet router 502 is allocated to the network interface card in a manufacturing stage. Network 504 is an example of a distributed network which provides communications links between various devices and computers, such as network 102 in FIG. 1. Suspected subnet router 502 is implemented to route traffic in network 504. Suspected subnet router 502 may forward data packets on network 504 to subnet 506. In this example, subnet 506 comprises a plurality of machines, such as S1 508 to S11 510. While conventional systems employ the traceroute utility to determine if a router is down or has failed by sending a packet to the router based on the known IP address of the router, rogue router hunter (RRH) host 512 comprises a program that uses the traceroute utility in a unique way determines whether a device such as suspected subnet router 502 is configured as a router. This determination may be made even though the rogue router hunter program does not know the IP addresses of the subnet of the suspected router or the IP addresses of the machines on the subnet. Rogue router hunter host 512 contains a network interface card having a MAC address to access network 504. Rogue router hunter host 512 may communicate with suspected subnet router 502 via network 504, since rogue router hunter host 512 knows the Ethernet address (MAC address) of suspected subnet router 502. Rogue router hunter 512 may obtain the MAC address of suspected subnet router 502 by using a ping utility which identifies whether a target device is on the network, or using an Address Resolution Protocol to determine a target's hardware address when only the target's IP address is known. Rogue router hunter 512 needs to obtain the MAC address of suspected subnet router 502 because a subnet router will not listen to or process a packet unless the packet contains the subnet router's MAC address in the packet's destination address. The ping utility operates by sending an ICMP request packet to a target device and listens for the reply. The reply packet may comprise the source MAC address, the destination or target MAC address, the source IP address, and the destination IP address. Thus, the program in rogue router hunter host 512 creates a data packet that includes a source MAC address comprising the MAC address for rogue router hunter host 512, and a destination MAC address comprising the MAC address for suspected subnet router 502. This data packet also includes a bogus IP address for suspected subnet router 502 in the destination IP address field of the packet. The rogue router hunter will also set the time-to-live (TTL) value of the packet to 1. Rogue router hunter host 512 then sends the data packet to suspected subnet router 502, and suspected subnet router 502 receives the packet because the destination MAC address in the packet matches the MAC address of the network interface card in suspected subnet router 502. Suspected subnet router 502 examines the packet header and determines if the destination IP packet is addressed to suspected subnet router 502. If the destination IP packet in the packet does not match the IP address of suspected subnet router 502, suspected subnet router 502 will discard the packet. Thus, if the subnet router is not configured to route, the subnet router checks the destination IP address, determines that the destination IP address is not the subnet router's IP address, and drops the packet. However, if suspected subnet router 502 has its router function enabled, suspected subnet router 502 will not discard the packet. In this router-enabled situation, suspected subnet router 502 eventually will compare the destination IP address in the packet with IP addresses in a routing table to determine the best route for the packet. The subnet router determines that although the destination IP address is not the subnet router's IP address, but since the subnet router is configured to route, the subnet router must send the packet onwards. However, before suspected subnet router 502 performs the comparison, suspected subnet router 502 examines the time-to-live (TTL) field. The TTL field is a hop limit used to indicate a limit on the number of iterations that a packet can experience before the packet should be discarded. If the TTL field is less than or equal to 1, suspected subnet router 502 returns a time exceeded (type 11) packet according to ICMP protocol to the source IP address in the packet, or rogue router hunter host 512. Thus, the subnet router determines it cannot route the packet because TTL value is too low, and the subnet router informs the packet sender of this problem. If rogue router hunter host 512 receives such an ICMP time exceeded message, the rogue router hunter knows that suspected subnet router 502 has its routing function enabled. Rogue router hunter host 512 may alert the network security administrator of the unauthorized router. In a particular example, suspected subnet router 502 employing the Advanced Interactive eXecutive (AIX™) operating system receives and examines a packet from rogue router hunter host 512. If the destination IP address in the packet does not match the IP address of suspected subnet router 502, and routing is enabled suspected subnet router 502, the packet is passed to an ip_mforward( ) function prior to being passed to the routing table. This ip_mforward( ) function will return a 0 if the TTL in the packet has expired (i.e., TTL ≦1), causing suspected subnet router 502 to respond with an ICMP time exceeded (type 11) message. If rogue router hunter host 512 receives such an ICMP time exceeded message from suspected subnet router 502, then rogue router hunter host 512 knows suspected subnet router 502 is enabled for routing. FIG. 6 illustrates a packet created by the rogue router hunter in accordance with the illustrative embodiments. Packet 600 may be sent from rogue router hunter 512 to determine if a machine such as suspected subnet router 502 in FIG. 5 is routing. Packet 600 comprises various fields, including source MAC address 602, destination MAC address 604, source IP address 606, destination IP address 608, and TTL field 610. Source MAC address 602 is the MAC address of the device sending the packet, or rogue router hunter host 512 in FIG. 5. Destination MAC address 604 is the MAC address of the device to receive the packet, or suspected subnet router 502 in FIG. 5. As previously mentioned, in situations where the IP addresses of the suspected routing machine or the machines on the subnet are unknown, a conventional packet comprising a source IP address and a destination IP address cannot be used to determine if the suspected machine is routing. The rogue router hunter addresses this issue by creating packet 600 which allows the rogue router hunter to send the packet to a particular suspected router using the suspected router's MAC address, an address which is known to the rogue router hunter. Thus, when the rogue router hunter sends packet 600 to the suspected router, the suspected router receives the packet because the destination MAC address in the packet matches the MAC address of the suspected router's network interface card. Source IP address 606 is the IP address of the device sending the packet, or the rogue router hunter. Source IP address 606 is used by the suspected router to return an ICMP time exceeded message to the rogue router hunter if the suspected router is routing. Destination IP address 608 is a bogus IP address. A correct destination IP address is not used in packet 600 because the rogue router hunter does not know any of the IP addresses of the suspected router or subnet machines. A bogus IP address is placed in destination IP address 608 to allow the suspected router to process packet 600 in a normal manner, and to allow the rogue router hunter to discover if the suspected router is routing, since the bogus IP address in destination IP address 608 will not match the IP address of the suspected router, and thus the suspected router will try, if routing is enabled, to route the packet. TTL field 610 is a value which specifies the time-to-live value assigned to packet 600. When the rogue router hunter creates packet 600, the rogue router hunter assigns a value of “1” to TTL field 610, since only one hop is required between the rogue router hunter and the suspected router. A value of 1 in the TTL field 610 causes a suspected router to send an ICMP time exceeded message back to the rogue router hunter when the suspected router receives packet 600. FIG. 7 is a flowchart of a process for discovering unauthorized routers in accordance with the illustrative embodiments. The process begins when a rogue router hunter program creates a data packet according to packet 600 in FIG. 6 which comprises a source MAC address of the rogue router hunter, a destination MAC address of the suspected router, a source IP address of the rogue router hunter, a bogus destination IP address and a TTL field with a value of 1 (step 702). The rogue router hunter sends the packet to the suspected router (step 704). The suspected router receives the packet (step 706), since the destination MAC address in the packet matches the MAC address of the suspected router's network interface card. The suspected router then examines the destination IP address (bogus IP address) in the packet to determine whether the packet is intended for the suspected router (step 708). Since the destination IP address in the packet is a bogus address, the destination IP address in the packet will not match the suspected router's IP address. The suspected router will thus determine that the packet is not intended for the suspected router (step 710). At this point, if there is no routing function enabled on the suspected router, the suspected router discards the packet (step 712), with the process termination thereafter. Since the rogue router hunter never receives an ICMP time exceeded message from the suspected router, the rogue router hunter determines that the suspected router is not routing. However, if a routing function is enabled on the suspected router, the suspected router examines the TTL field in the packet (step 714). Since the TTL field in the packet created by the rogue router hunter has a value of 1, the suspected router returns an ICMP time exceeded message back to the rogue router hunter (packet sender) based on the source IP address in the packet (step 716). Since the source IP address in the packet is the IP address of the rogue router hunter, the rogue router hunter receives the ICMP time exceeded message (step 718). When a time exceeded message from the suspected router is received by the rogue router hunter, the rogue router hunter will know that the suspected router is routing (step 720). The rogue router hunter may then alert a network security administrator that the suspected router is an unauthorized router on the network (step 722), with the process terminating thereafter. The invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. In a preferred embodiment, the invention is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc. Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any tangible apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. Further, a computer storage medium may contain or store a computer readable program code such that when the computer readable program code is executed on a computer, the execution of this computer readable program code causes the computer to transmit another computer readable program code over a communications link. This communications link may use a medium that is, for example without limitation, physical or wireless. A data processing system suitable for storing and/or executing program code will include at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters. The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.	G	60G06	161G06F	15	16
11891492	US20090043939A1-20090212	Bus node	ACCEPTED	20090128	20090212	[]	G06F1314	["G06F1314"]	7624219	20070809	20091124	710	305000	96460.0	DANG	KHANH	[{"inventor_name_last": "Fuessl", "inventor_name_first": "Bernd", "inventor_city": "Eriskirch", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Riehm", "inventor_name_first": "Thomas", "inventor_city": "Konstanz", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Schoepe", "inventor_name_first": "Peter", "inventor_city": "Weingarten", "inventor_state": "", "inventor_country": "DE"}]	The present invention relates to an apparatus for connection to a communication bus, in particular an apparatus for encoding the status of several emergency devices for communication across an AS-interface. A data code indicative of a collective state of one or more subsets of the emergency devices is communicated during cyclic communication from the slave to the master whereas information indicative of the individual states of the emergency devices is communicated during acyclic communication from the slave to the master.	1. A bus node circuit comprising: a coding circuit that receives a plurality of substantially binary input signals and outputs a first output signal and a plurality of other output signals; and a bus interface circuit having a first data input terminal and a plurality of parameter input terminals, wherein said first output signal has a first binary state if each of a first predetermined subset greater than one of said plurality of substantially binary input signals exhibits a respectively predetermined binary state, each of said plurality of other output signals has a binary state indicative of a binary state of a respective one of said substantially binary input signals, said first data input terminal is connected to said coding circuit to receive said first output signal, and each of said plurality of parameter input terminals is connected to said coding circuit to receive a respective one of said plurality of other output signals. 2. The bus node circuit of claim 1, wherein said coding circuit receives a first input signal, and said first output signal is equal to said first input signal if any of said first predetermined subset of said plurality of substantially binary input signals exhibits a binary state that differs from said respectively predetermined binary state. 3. The bus node circuit of claim 1, wherein said bus interface circuit has a plurality of bus connection terminals that are each connectable to a respective signal line of a bus, said bus interface circuit outputs, via said plurality of bus connection terminals, a data code representative of said first input signal and a parameter code representative of said plurality of other output signals. 4. The bus node circuit of claim 3, wherein said bus interface circuit outputs said data code in response to a cyclic request from a master node of said bus and outputs said parameter code in response to an acyclic request from said master node. 5. The bus node circuit of claim 1, wherein said coding circuit outputs a second output signal, said bus interface circuit has a second data input terminal, said second output signal has a second binary state if each of said first predetermined subset of said plurality of substantially binary input signals exhibits a respectively predetermined binary state, and said second data input terminal is connected to said coding circuit to receive said second output signal. 6. The bus node circuit of claim 5, wherein said coding circuit comprises a first coding sub-circuit that generates said first output signal and a second coding sub-circuit, independent from said first coding sub-circuit, that generates said second output signal. 7. The bus node circuit of claim 5, wherein said coding circuit receives a second input signal, and said second output signal is equal to said second input signal if any of said first predetermined subset of said plurality of substantially binary input signals exhibits a binary state that differs from said respectively predetermined binary state. 8. The bus node circuit of claim 5, wherein said bus interface circuit has a plurality of bus connection terminals that are each connectable to a respective signal line of a bus, said bus interface circuit outputs, via said plurality of bus connection terminals, a data code representative of said first and second input signals and a parameter code representative of said plurality of other output signals. 9. The bus node circuit of claim 8, wherein said bus interface circuit outputs said data code in response to a cyclic request from a master node of said bus and outputs said parameter code in response to an acyclic request from said master node. 10. The bus node circuit of claim 6, wherein said coding circuit outputs a third and a fourth output signal, said bus interface circuit has a third and a fourth data input terminal, said third output signal has a third binary state if each of a second predetermined subset greater than one of said plurality of substantially binary input signals that differs from said first predetermined subset of said plurality of substantially binary input signals exhibits a respectively predetermined binary state, said fourth output signal has a fourth binary state if each of said second predetermined subset of said plurality of substantially binary input signals exhibits a respectively predetermined binary state, said third data input terminal is connected to said coding circuit to receive said third output signal, said fourth data input terminal is connected to said coding circuit to receive said fourth output signal, and said coding circuit comprises a third coding sub-circuit that generates said third output signal and a fourth coding sub-circuit, independent from said third coding sub-circuit, that generates said fourth output signal. 11. The bus node circuit of claim 1, wherein said bus interface circuit complies with European standard EN 50295 or IEC Standard 62026-2. 12. A bus node for connection to a bus, comprising: a coding and interface circuit that receives a plurality of substantially binary input signals and outputs a plurality of bus signals including a data code signal and a parameter code signal, wherein said data code signal is representative of a collective state of two or more of said substantially binary input signals, and said parameter code signal is representative of an individual state of each of said substantially binary input signals. 13. The bus node of claim 12, wherein said coding and interface circuit comprises a series circuit that processes said two or more of said substantially binary input signals to generate an output signal that is representative of said collective state. 14. The bus node of claim 13, wherein said series circuit comprises two or more serially connected switching devices, each of which switching devices has an input and an output that is electrically isolated from said input. 15. The bus node of claim 14, wherein said switching devices are selected from the group consisting of optocouplers, digital magnetic isolators and relays. 16. The bus node of claim 13, wherein said coding and interface circuit comprises a bus interface circuit that receives said output signal and generates said data code signal therefrom. 17. The bus node of claim 12, wherein said coding and interface circuit comprises a bus interface circuit and a plurality of switching devices, each of which switching devices has an input and an output that is electrically isolated from said input, said bus interface circuit receives a plurality of input signals that are respectively representative of said plurality of substantially binary input signals, said bus interface circuit receives each of said plurality of input signals via a respective one of said plurality of switching devices, and said bus interface circuit generates said parameter code signal from said plurality of input signals. 18. The bus node of claim 17, wherein each of said plurality of switching devices is selected from the group consisting of optocouplers, digital magnetic isolators and relays. 19. The bus node of claim 12, wherein said bus signals comply with European standard EN 50295 or IEC Standard 62026-2. 20. The bus node of claim 12, wherein said coding and interface circuit outputs said data code signal in response to a cyclic request from a master node of said bus and outputs said parameter code signal in response to an acyclic request from said master node. 21. The bus node of claim 12, wherein said data code signal comprises a first bit representative of said collective state and a second bit representative of said collective state, and said coding and interface circuit comprises a first circuit for generating said first bit and a second circuit, independent of said first circuit, for generating said second bit.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an apparatus for connection to a communication bus. More specifically, it relates to an apparatus for encoding the status of several emergency switches for communication across a so-called AS-interface. 2. Description of the Related Art The Aktuator-Sensor-Interface, typically referred to as an AS-interface or AS-i, is a two-wire master-slave bus system as described in “AS-Interface, The Automation Solution” published 2002 by the AS-International Association, Zum Taubengarten 52, 63571 Gelnhausen, Germany, the full content of which is hereby incorporated by reference. The AS-interface has been standardized in European standard EN 50295, the full content of which is hereby incorporated by reference. An alternative version of the AS-interface has been standardized in IEC Standard 62026-2, the full content of which is hereby incorporated by reference. Bus systems compliant with any of the aforementioned references may be termed an AS-interface. The two wires of an AS-interface are used for data communication and power supply. An AS-interface has a single master node (hereinafter also just “master”) and a plurality of slave nodes node (hereinafter also just “slave”). The master queries each of the slaves individually. In other words, only the queried slave responds. The master queries each of the slaves sequentially. In other words, the master queries each of the slaves, one after the other, in accordance with a predetermined sequence. Such a sequential querying of all slaves is designated as a cycle. Once all slaves have been sequentially queried by the master, the cycle is repeated. Between any two cycles, the master may exchange data with any one of the slaves. The master queries the slaves in accordance with a predetermined timing. In the context of an AS-interface, the exchange of data between the master and a slave during a cycle is termed cyclic communication, and the exchange of data between the master and a slave between any two cycles is termed acyclic communication. Hereinafter, data communicated in an AS-interface by cyclic communication are referred to as data codes, and data communicated in an AS-interface by acyclic communication are referred to as parameters or parameter codes. The AS-interface specification includes so-called “Safety at Work” provisions that allow both safety information and normal data to be communicated across the same AS-i cable. For example, the emergency wiring of a machine can be integrated into the control wiring of that machine without significant additional overhead, yet while complying with the requirements of Safety Integrity Level 3 (SIL3) of IEC standard 61508 and Category 4 of European standard EN 954-1. To ensure secure querying of safety-relevant slaves that are connected to safety components such as emergency buttons and that supply corresponding safety signals, the (querying/request) data packets that are sent from the master to safety-relevant slaves as well as the (response) data packets that are sent from a safety-relevant slave to the master during cyclic communication include special bit patterns that are several bits in length. Specifically, a secure slave, i.e. a slave compliant with the AS-i “Safety at Work” provisions, codes safety relevant information, e.g. the information “emergency button not activated,” into a 32-bit long codeword, four respective bits of which are communicated per cycle over a consecutive sequence of eight cycles. The use of 32-bit codewords theoretically allows for over four billion, namely 2 32 , different codewords. However, the AS-i specification includes rules that restrict the available codewords to roughly 950,000 possibilities. The available codewords are centrally administered and individually issued to ensure that each secure AS-i slave is globally uniquely identifiable based on the “fingerprint” of its codeword(s). In accordance with the AS-i “Safety at Work” provisions, a safety monitor monitors the data communicated between the master and any secure slaves during cyclic communication. If the safety monitor detects a codeword from a secure slave that, instead of the expected codeword, contains a zeroed bit pair at the beginning and/or the end of the four bits communicated in a respective cycle, the safety monitor activates the safety state associated with the respective secure slave. In the case of a secure slave that transmits information indicative of the state of an emergency button on a machine, for example, divergence from the expected codeword indicating that the emergency button has not been activated could trigger the safety monitor to cut off all power to that machine and to perhaps activate an emergency braking mechanism for that machine. In practice, it is often desired to install safety-relevant devices, e.g. emergency buttons, door contact switches, etc., at various positions in an installation. Conventionally, networking these safety-relevant devices via an AS-interface requires a corresponding number of secure slaves, which is impractical. Alternatively, the safety-relevant devices can be connected in series. In latter case, however, when one of the serially connected, safety-relevant devices is activated, the safety monitor receives no information specifying which of the serially connected, safety-relevant devices has been activated. While this lack of specific information may be irrelevant for many safety aspects of an installation, e.g. for ensuring that the appropriate machine or that the overall installation is shut down, it is generally desirable to obtain such information e.g. for guiding firefighting or rescue crews or for allowing the “fault” to be pinpointed and remedied by maintenance personnel. Similar problems can arise when networking numerous devices via other, i.e. non-AS-i, bus systems or when networking numerous non-safety-critical devices via an AS-interface. It is an object of the present invention to overcome these deficiencies of the prior art.	<SOH> BRIEF SUMMARY OF THE INVENTION <EOH>In a broad aspect, the invention can be seen in an apparatus for coding a plurality of substantially binary input signals and for outputting the coded signals as bus signals for communication on a bus, i.e. as a bus node circuit. Similarly, the invention can be seen in method comprising the steps of coding a plurality of substantially binary input signals and outputting the coded signals as bus signals for communication on a bus. In an embodiment of the invention, a first bus signal is output that is representative of a collective state of two or more of the plurality of substantially binary input signals and a second bus signal is output that is representative of an individual state of each of said substantially binary input signals. For example, if each of the plurality of substantially binary input signals is indicative of whether a respective emergency switch has been activated, the first bus signal can be representative of whether any of the emergency switches has been activated, and the second bus signal can be representative of the individual activation states of the emergency switches. In an AS-interface, the first bus signal can be communicated during cyclic communication between the master and a secure slave, i.e. as a data code (signal) in the form of the predefined codeword associated with the secure slave or an appropriately zeroed (as described above) variant thereof, and the second bus signal can be communicated during acyclic communication between the master and a secure slave, i.e. as a parameter code (signal) that is independent of the predefined codeword associated with the secure slave. In an embodiment of the invention, at least two bits of the data code (signal) are representative of a collective state of two or more of the plurality of substantially binary input signals. To improve upon the reliability of the data codes, the state of the at least two bits can be determined by independent means, e.g. by identical, yet redundant means. In this fashion, the requirements of European standard EN 954 can be fulfilled. In an embodiment of the invention, a series circuit is employed to process the two or more substantially binary input signals to generate a signal that is representative of the collective state of the two or more substantially binary input signals. Such a series circuit is simple to manufacture, low in cost, yet reliable. The series circuit can be simply and cost-effectively implemented by a chain of serially connected switching devices. In an embodiment of the invention, the inputs of the apparatus that receive the plurality of substantially binary input signals are electrically insulated from the outputs of the apparatus that output the bus signals. This ensures that the bus is not disturbed by extraneous signals. This electrical insulation can be achieved by optocouplers, digital magnetic isolators, relays or other electrically insulating signal transmission devices/electrically insulating switching devices situated e.g. between the inputs and the bus interface circuitry of the apparatus. If employed in the aforementioned series circuit, electrically insulating switching devices can simultaneously fulfill two functions within the apparatus. In an embodiment of the invention as a slave node circuit for encoding the status of several emergency devices for communication across an AS-interface, a data code indicative of a collective state of one or more subsets of the emergency devices is communicated during cyclic communication from the slave to the master whereas information indicative of the individual states of the emergency devices is communicated during acyclic communication from the slave to the master. While the present description may, for the sake of brevity, limit itself to a description of the invention as an apparatus, the teachings of this specification are to be understood as applying equally to a method capable of effecting the functionality of the described apparatus, i.e. a method comprising steps that effect the results of the apparatus.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a non-provisional application claiming no benefit of an earlier filed application. STATEMENT OF GOVERNMENT INTEREST The subject matter of this application was not carried out under contract with the government of the United States. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for connection to a communication bus. More specifically, it relates to an apparatus for encoding the status of several emergency switches for communication across a so-called AS-interface. 2. Description of the Related Art The Aktuator-Sensor-Interface, typically referred to as an AS-interface or AS-i, is a two-wire master-slave bus system as described in “AS-Interface, The Automation Solution” published 2002 by the AS-International Association, Zum Taubengarten 52, 63571 Gelnhausen, Germany, the full content of which is hereby incorporated by reference. The AS-interface has been standardized in European standard EN 50295, the full content of which is hereby incorporated by reference. An alternative version of the AS-interface has been standardized in IEC Standard 62026-2, the full content of which is hereby incorporated by reference. Bus systems compliant with any of the aforementioned references may be termed an AS-interface. The two wires of an AS-interface are used for data communication and power supply. An AS-interface has a single master node (hereinafter also just “master”) and a plurality of slave nodes node (hereinafter also just “slave”). The master queries each of the slaves individually. In other words, only the queried slave responds. The master queries each of the slaves sequentially. In other words, the master queries each of the slaves, one after the other, in accordance with a predetermined sequence. Such a sequential querying of all slaves is designated as a cycle. Once all slaves have been sequentially queried by the master, the cycle is repeated. Between any two cycles, the master may exchange data with any one of the slaves. The master queries the slaves in accordance with a predetermined timing. In the context of an AS-interface, the exchange of data between the master and a slave during a cycle is termed cyclic communication, and the exchange of data between the master and a slave between any two cycles is termed acyclic communication. Hereinafter, data communicated in an AS-interface by cyclic communication are referred to as data codes, and data communicated in an AS-interface by acyclic communication are referred to as parameters or parameter codes. The AS-interface specification includes so-called “Safety at Work” provisions that allow both safety information and normal data to be communicated across the same AS-i cable. For example, the emergency wiring of a machine can be integrated into the control wiring of that machine without significant additional overhead, yet while complying with the requirements of Safety Integrity Level 3 (SIL3) of IEC standard 61508 and Category 4 of European standard EN 954-1. To ensure secure querying of safety-relevant slaves that are connected to safety components such as emergency buttons and that supply corresponding safety signals, the (querying/request) data packets that are sent from the master to safety-relevant slaves as well as the (response) data packets that are sent from a safety-relevant slave to the master during cyclic communication include special bit patterns that are several bits in length. Specifically, a secure slave, i.e. a slave compliant with the AS-i “Safety at Work” provisions, codes safety relevant information, e.g. the information “emergency button not activated,” into a 32-bit long codeword, four respective bits of which are communicated per cycle over a consecutive sequence of eight cycles. The use of 32-bit codewords theoretically allows for over four billion, namely 232, different codewords. However, the AS-i specification includes rules that restrict the available codewords to roughly 950,000 possibilities. The available codewords are centrally administered and individually issued to ensure that each secure AS-i slave is globally uniquely identifiable based on the “fingerprint” of its codeword(s). In accordance with the AS-i “Safety at Work” provisions, a safety monitor monitors the data communicated between the master and any secure slaves during cyclic communication. If the safety monitor detects a codeword from a secure slave that, instead of the expected codeword, contains a zeroed bit pair at the beginning and/or the end of the four bits communicated in a respective cycle, the safety monitor activates the safety state associated with the respective secure slave. In the case of a secure slave that transmits information indicative of the state of an emergency button on a machine, for example, divergence from the expected codeword indicating that the emergency button has not been activated could trigger the safety monitor to cut off all power to that machine and to perhaps activate an emergency braking mechanism for that machine. In practice, it is often desired to install safety-relevant devices, e.g. emergency buttons, door contact switches, etc., at various positions in an installation. Conventionally, networking these safety-relevant devices via an AS-interface requires a corresponding number of secure slaves, which is impractical. Alternatively, the safety-relevant devices can be connected in series. In latter case, however, when one of the serially connected, safety-relevant devices is activated, the safety monitor receives no information specifying which of the serially connected, safety-relevant devices has been activated. While this lack of specific information may be irrelevant for many safety aspects of an installation, e.g. for ensuring that the appropriate machine or that the overall installation is shut down, it is generally desirable to obtain such information e.g. for guiding firefighting or rescue crews or for allowing the “fault” to be pinpointed and remedied by maintenance personnel. Similar problems can arise when networking numerous devices via other, i.e. non-AS-i, bus systems or when networking numerous non-safety-critical devices via an AS-interface. It is an object of the present invention to overcome these deficiencies of the prior art. BRIEF SUMMARY OF THE INVENTION In a broad aspect, the invention can be seen in an apparatus for coding a plurality of substantially binary input signals and for outputting the coded signals as bus signals for communication on a bus, i.e. as a bus node circuit. Similarly, the invention can be seen in method comprising the steps of coding a plurality of substantially binary input signals and outputting the coded signals as bus signals for communication on a bus. In an embodiment of the invention, a first bus signal is output that is representative of a collective state of two or more of the plurality of substantially binary input signals and a second bus signal is output that is representative of an individual state of each of said substantially binary input signals. For example, if each of the plurality of substantially binary input signals is indicative of whether a respective emergency switch has been activated, the first bus signal can be representative of whether any of the emergency switches has been activated, and the second bus signal can be representative of the individual activation states of the emergency switches. In an AS-interface, the first bus signal can be communicated during cyclic communication between the master and a secure slave, i.e. as a data code (signal) in the form of the predefined codeword associated with the secure slave or an appropriately zeroed (as described above) variant thereof, and the second bus signal can be communicated during acyclic communication between the master and a secure slave, i.e. as a parameter code (signal) that is independent of the predefined codeword associated with the secure slave. In an embodiment of the invention, at least two bits of the data code (signal) are representative of a collective state of two or more of the plurality of substantially binary input signals. To improve upon the reliability of the data codes, the state of the at least two bits can be determined by independent means, e.g. by identical, yet redundant means. In this fashion, the requirements of European standard EN 954 can be fulfilled. In an embodiment of the invention, a series circuit is employed to process the two or more substantially binary input signals to generate a signal that is representative of the collective state of the two or more substantially binary input signals. Such a series circuit is simple to manufacture, low in cost, yet reliable. The series circuit can be simply and cost-effectively implemented by a chain of serially connected switching devices. In an embodiment of the invention, the inputs of the apparatus that receive the plurality of substantially binary input signals are electrically insulated from the outputs of the apparatus that output the bus signals. This ensures that the bus is not disturbed by extraneous signals. This electrical insulation can be achieved by optocouplers, digital magnetic isolators, relays or other electrically insulating signal transmission devices/electrically insulating switching devices situated e.g. between the inputs and the bus interface circuitry of the apparatus. If employed in the aforementioned series circuit, electrically insulating switching devices can simultaneously fulfill two functions within the apparatus. In an embodiment of the invention as a slave node circuit for encoding the status of several emergency devices for communication across an AS-interface, a data code indicative of a collective state of one or more subsets of the emergency devices is communicated during cyclic communication from the slave to the master whereas information indicative of the individual states of the emergency devices is communicated during acyclic communication from the slave to the master. While the present description may, for the sake of brevity, limit itself to a description of the invention as an apparatus, the teachings of this specification are to be understood as applying equally to a method capable of effecting the functionality of the described apparatus, i.e. a method comprising steps that effect the results of the apparatus. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of the invention, as well as the invention itself, both as to its structure and its operation will be best understood from the accompanying FIGURE, taken in conjunction with the accompanying description. The FIGURE shows: FIG. 1 a bus node circuit in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 schematically illustrates a bus node circuit 100 in accordance with an embodiment of the invention. The illustrated bus node circuit 100 constitutes a secure server node of an AS-interface. Bus node circuit 100 includes an AS-i interface IC 10, a code generator 20, optocouplers 30A to 30H, optocouplers 40A to 40D. The bus node circuit 100 is connected to emergency switches 50A to 50D. Code generator 20 serves to generate the 32-bit codeword associated with the bus node circuit four bits at a time (codebit 0 to codebit 3) as described supra. The illustrated strobe signal of AS-i interface IC 10 serves to trigger generation and output of the next four-bit sub-code of the 32-bit codeword from code generator 20. Various implementations for codeword generator 20 are well known in the art. For example, code generator 20 can be implemented by a microprocessor as described in paragraph [0004] of German laid-open application DE 10 20 009 A1. The teaching thereof can be paraphrased as teaching that, to generate and provide the bit pattern, the slave comprises, in addition to the interface, a further, external circuit, typically in the form of a microprocessor, that includes memory means (e.g. solid state memory) for providing the multi-bit information constituting the (sub-)codeword(s), a counter that points at a location in memory, a timing device synched to the timing of communication on the AS-i bus, a plurality of output channels corresponding in number to the number of bits of the information (e.g. sub-codeword) to be provided, as well as an input impulse detector for triggering the timing device during valid AS-i communication, wherein a program for controlling operation is provided in a storage area of the microprocessor. The bus node circuit 100 is configured such that an input terminal of optocoupler 40A is connected to a power supply Vcc via emergency switch 50A and that the other input terminal of optocoupler 40A is connected to ground via the light emitting diodes (LED's) of optocouplers 30A and 30B. Accordingly, the respective LED's of optocouplers 40A, 30A and 30B emit light when emergency switch 50A is closed (inactivated) and emit no light when emergency switch 50A is open (activated). Optocouplers 40B, 30C and 30D are similarly connected to emergency switch 50B. Optocouplers 40C, 30E and 30F are similarly connected to emergency switch 50C. Optocouplers 40D, 30G and 30H are similarly connected to emergency switch 50D. The bus node circuit 100 is configured such that the collector of the phototransistor that constitutes an output terminal of optocoupler 40A is connected to a power supply Vcc. The emitter of the phototransistor that constitutes an output terminal of optocoupler 40A is connected to parameter input terminal P0 of AS-i interface IC 10. Accordingly, when emergency switch 50A is closed, the phototransistor of optocoupler 40A receives light from the input LED of optocoupler 40A, and parameter input terminal P0 of AS-i interface IC 10 is connected to power supply Vcc, i.e. is held at a binary “1” level. When emergency switch 50A is activated, the phototransistor of optocoupler 40A receives no light, and parameter input terminal P0 of AS-i interface IC 10 is disconnected from power supply Vcc, i.e. falls to a binary zero level. Parameter input terminals P1, P2 and P3 respectively interact with optocouplers 40B, 40C and 40D and emergency switches 50B, 50C and 50D in a similar fashion. The bus node circuit 100 is configured such that the collector of the phototransistor that constitutes an output terminal of optocoupler 30A is connected to a “codebit 0” output terminal of code generator 20. The emitter of the phototransistor that constitutes an output terminal of optocoupler 30A is connected to the collector of the phototransistor that constitutes an output terminal of optocoupler 30C, and the emitter of the phototransistor that constitutes an output terminal of optocoupler 30C is connected to data input terminal “DIN 0” of AS-i interface IC 10. Optocouplers 30A and 30C thus constitute a series circuit, the output of which depends, by virtue of the connection of optocouplers 30A and 30C to emergency switches 50A and 50B, respectively, on the state of optocouplers 30A and 30C. Specifically, when both emergency switch 50A and emergency switch 50B are closed, the phototransistor of optocoupler 30A receives light from the input LED of optocoupler 30A due to the closure of emergency switch 50A, the phototransistor of optocoupler 30C receives light from the input LED of optocoupler 30C due to the closure of emergency switch 50B, and, as a result, data input terminal “DIN 0” of AS-i interface IC 10 is connected to the “codebit 0” output terminal of code generator 20. When either (or both) of emergency switches 50A or 50B is/are activated, the phototransistor of optocoupler 30A/30C, as the case may be, receives no light, and data input terminal “DIN o” of AS-i interface IC 10 is disconnected from the “codebit 0” output terminal of code generator 20, i.e. falls to a binary zero level. The output of optocouplers 30B and 30D to data input terminal “DIN 1” of AS-i interface IC 10 similarly depends on the state of emergency switches 50A and 50B as well as codebit 1 of code generator 20. The output of optocouplers 30E and 30G to data input terminal “DIN 2” of AS-i interface IC 10 similarly depends on the state of emergency switches 50C and 50D as well as codebit 2 of code generator 20. The output of optocouplers 30F and 30H to data input terminal “DIN 3” of AS-i interface IC 10 similarly depends on the state of emergency switches 50C and 50D as well as codebit 3 of code generator 20. Although the inputs of optocouplers 30A, 30C, 30E and 30 G are shown as being respectively connected in series with optocouplers 40A to 40D to emergency switches 50A to 50D, the inputs of optocouplers 30A, 30C, 30E and 30 G could be directly connected to emergency switches 50A to 50D, e.g. could be connected in parallel with the inputs of optocouplers 40A to 40D to emergency switches 50A to 50D. AS-i interface IC 10 interfaces the signals received via data inputs “DIN 0” to “DIN 3” and parameter inputs P0 to P3 in an AS-i-compliant manner to an AS-interface, i.e. to the two signal lines of an AS-i-compliant bus, via the two bus signal outputs AS-i− and AS-i+. Specifically, the signals, i.e. binary signal levels, received via data inputs “DIN 0” to “DIN 3” are interfaced to be communicated as the four bits communicated from the secure slave to the master per cycle. Similarly, the signals, i.e. binary signal levels, received via parameter inputs P0 to P3 are interfaced to be acyclically communicated from the secure slave to the master as binary parameter codes between cycles. As is apparent from the above description of the bus node circuit and its function, activation of any of emergency switches 50A to 50D will result in communication of a codeword from the secure slave that, instead of the correct codeword generated by the code generator 20, contains a zeroed bit pair at the beginning and/or the end, as the case may be, of the four bits communicated in a respective cycle. This “fault” or “emergency” condition will be recognized by the safety monitor that will then activate the appropriate safety state, i.e. the safety state associated with the secure slave whose codeword contained the zeroed bits. Later, in one or more rounds of acyclic communication, the safety monitor and/or the master will receive parameter codes based on the input signals received at parameter input terminals P0 to P3 that specify the emergency switch or similar safety device whose activation triggered to the “fault” or “emergency” condition. In this respect, it is important to note that recognition of a “fault” or “emergency” condition by the safety monitor does not ordinarily lead to termination of communication over the AS-interface. As stated above, the illustrated strobe signal of AS-i interface IC 10 serves to trigger generation and output of the next four-bit sub-code of the 32-bit codeword from code generator 20. Any circuit that interfaces data input signals and parameter input signals to a bus network, e.g. provides the interface functionality described in this specification, can be used as AS-i interface IC 10. For example, the integrated circuit commercially available under the designation “ASI4UC-G1-ST” from ZMD America Inc., 201 Old Country Road, Ste 204, Melville, N.Y. 11747 can be employed as AS-i interface IC 10. In the illustrated embodiment, the outputs of two safety devices are processed in series via respective pairs of optocouplers 30A to 30H. This principle can be extended to a larger number of safety devices. In other words, the outputs of three or more safety devices can be processed in series to influence the signal provided to any of data input terminals “DIN 0” to “DIN 3.” In general, the signal output to any of data input terminals “DIN 0” to “DIN 3” is indicative of a collective state of a subset of the safety devices connected to the bus node circuitry. For example, the signal output to any of data input terminals “DIN 0” to “DIN 3” can be indicative of a deviation of the state any of the subset of the safety devices connected to the bus node circuitry from an expected state of the respective safety device. To specify the specific safety device that triggered the “fault” or “emergency” condition, the interface circuitry can include a larger number of parameter input terminals that receive a signal from a respective one of the safety devices, and/or alternative circuitry can be used that uniquely codes the identity of the specific safety device that triggered the “fault” or emergency condition to a number of bits that is smaller than the number of safety devices connected to the bus node circuitry. Such circuitry for uniquely coding the identity of a single signal having a value that differs from a plurality of other signals is known in the art. In the illustrated embodiment, optocouplers are used as switching elements and for electrical insulation of the inputs of the bus node circuitry from the outputs of the bus node circuitry. However, digital magnetic isolators, relays or other electrically insulating signal transmission devices/electrically insulating switching devices can be likewise used in the present invention, e.g. in lieu of the optocouplers or at appropriate locations as known to the person skilled in the art in alternative circuit configurations of the present invention. Similarly, conventional switching devices can be combined with electrically insulating signal transmission devices/electrically insulating switching devices to provide the optional electrical insulation in addition to the desired coding and interface functionality of the present invention. The use of independent circuitry, based on the outputs of the same subset of safety devices connected to the bus node circuitry, to zero a bit pair at the beginning and/or the end, as the case may be, of the four bits communicated in a respective cycle increases the reliability of signals communicated by the bus node as compared to a zeroing of a single bit of the four bits or the use of non-independent circuitry. Nonetheless, this circuitry need not zero bit pairs and need not be independently implemented. Any circuitry that outputs one or more signals indicative of a “fault” or “emergency” condition in one or more predetermined subsets of the safety devices connected to the bus node circuitry can be used in place of illustrated circuit configuration of optocouplers 30A to 30H. Although a secure slave node for an AS-interface is illustrated and described, the present invention is equally applicable to any type of bus node circuitry for any type of bus system. In the present specification, data communicated in an AS-interface by cyclic communication are referred to as data codes, and data communicated in an AS-interface by acyclic communication are referred to as parameters or parameter codes. However, since the present invention is applicable to bus systems other than AS-interfaces, the terms data code, parameter and parameter code as used in the present specification are not to be interpreted per se as limiting to within the aforementioned contextual definition of these terms. Instead, the term data code is to be understood in the general sense of information that is consistently communicated at a time, in a manner and/or in a form that is distinct from the time, manner or form at/in which other information, which other information is designated by the term parameter or parameter code, is communicated in the bus environment for which the respective bus node circuitry has been conceived. Of the two distinct times, manners and/or forms of communication, data codes designate information that is communicated at a time, in a manner and/or in a form that is more reliable and/or faster and/or at briefer intervals than the information designated as parameters or parameter codes in the relevant bus environment. Further information with regard to the terminology used in this specification as well as techniques and hardware employable for implementing the known features of the invention can be found in the aforementioned documents incorporated into the present specification by reference. While various embodiments of the present invention have been disclosed and described in detail herein, it will be apparent to those skilled in the art that various changes may be made to the configuration, operation and form of the invention without departing from the spirit and scope thereof. In particular, it is noted that the respective features of the invention, even those disclosed solely in combination with other features of the invention, may be combined in any configuration excepting those readily apparent to the person skilled in the art as nonsensical. Likewise, use of the singular and plural is solely for the sake of illustration and is not to be interpreted as limiting. Except where the contrary is explicitly noted, the plural may be replaced by the singular and vice-versa.	G	60G06	161G06F	13	14
11867244	US20090093900A1-20090409	Production Moving Line System and Method	ACCEPTED	20090325	20090409	[]	G06F1900	["G06F1900"]	7599756	20071004	20091006	700	113000	93224.0	PATEL	RAMESH	[{"inventor_name_last": "Reeves", "inventor_name_first": "Brad J.", "inventor_city": "Everett", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Bradley", "inventor_name_first": "James S.", "inventor_city": "Arlington", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Irvine", "inventor_name_first": "Richard S.", "inventor_city": "Mukilteo", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "McInelly", "inventor_name_first": "Chris G.", "inventor_city": "Stanwood", "inventor_state": "WA", "inventor_country": "US"}]	A production moving line system. An illustrative embodiment of the production moving line system includes at least one metallic guide strip and at least one tow vehicle which may be adapted to follow the guide strip. The tow vehicle may include control circuitry and a power source and a wireless transceiver connected to the control circuitry. An assembly fixture cart may be coupled to the tow vehicle. A wireless communication link may be provided between a central control computer and the wireless transceiver of the tow vehicle. A production moving line method is also disclosed.	1. A production moving line system, comprising: at least one metallic guide strip; at least one tow vehicle adapted to follow said guide strip; said at least one tow vehicle comprises control circuitry and a power source and a wireless transceiver connected to said control circuitry; an assembly fixture cart coupled to said tow vehicle; a central control computer; and a wireless communication link between said central control computer and said wireless transceiver of said tow vehicle. 2. The system of claim 1 further comprising a user interface pendant connected to said control circuitry. 3. The system of claim 1 wherein said power source comprises at least one battery. 4. The system of claim 3 further comprising a battery recharging system connected to said battery. 5. The system of claim 1 further comprising a data input/output device connected to said circuitry. 6. The system of claim 1 wherein said assembly fixture cart comprises a cart base having a plurality of cart wheels, a cart frame carried by said cart base and a cart platform carried by said cart frame. 7. The system of claim 6 wherein said tow vehicle is coupled to said cart base of said assembly fixture cart. 8. The system of claim 1 wherein said tow vehicle comprises a vehicle housing. 9. A production moving line system, comprising: a plurality of production work stations; at least one metallic guide strip extending generally adjacent to said production work stations; at least one tow vehicle adapted to follow said guide strip; said at least one tow vehicle comprises control circuitry having memory, at least one battery connected to said control circuitry, a wireless transceiver connected to said control circuitry, a position sensing mechanism connected to said control circuitry and adapted to sense said guide strip, a drive motor connected to said control circuitry, at least one wheel drivingly engaged by said drive motor and a steering mechanism connected to said control circuitry and coupled to said at least one wheel; an assembly fixture cart coupled to said tow vehicle; a central control computer; and a wireless communication link between said central control computer and said wireless transceiver of said tow vehicle. 10. The system of claim 9 further comprising a user interface pendant connected to said control circuitry. 11. The system of claim 9 further comprising a battery recharging system connected to said battery. 12. The system of claim 9 further comprising a data input/output device connected to said circuitry. 13. The system of claim 9 wherein said assembly fixture cart comprises a cart base having a plurality of cart wheels, a cart frame carried by said cart base and a cart platform carried by said cart frame. 14. The system of claim 13 wherein said tow vehicle is coupled to said cart base of said assembly fixture cart. 15. The system of claim 9 wherein said tow vehicle comprises a vehicle housing. 16. The system of claim 9 wherein said at least one tow vehicle comprises a plurality of tow vehicles and further comprising a wireless communication link between said tow vehicles. 17. A production moving line method, comprising the steps of: providing at least one metallic guide strip; providing at least one tow vehicle having a wireless transceiver in guided contact with said guide strip; coupling an assembly fixture cart to said at least one tow vehicle; providing at least one part on said assembly fixture cart; providing a central control computer; providing a wireless communication link between said central control computer and said wireless transceiver of said tow vehicle; and moving said tow vehicle along said guide strip. 18. The method of claim 17 further comprising connecting a user interface pendant to said tow vehicle and controlling said tow vehicle by operation of said user interface pendant. 19. The method of claim 17 further comprising providing at least one battery, powering said tow vehicle using said at least one battery and recharging said at least one battery during operation of said tow vehicle. 20. The method of claim 17 wherein said at least one tow vehicle comprises a plurality of tow vehicles and further comprising providing a wireless communication link between said plurality of tow vehicles.	<SOH> BACKGROUND <EOH>Part moving lines may be used in assembly facilities to shuttle parts among multiple work stations. A conventional part moving line may utilize an automated guided vehicle (AGV) on which the part is placed and transported among and between the work stations. However, conventional part moving lines may suffer from any of multiple drawbacks. These may include, for example, breakdown of the entire part moving line in the event that one part of the line breaks down; duplication of tools/fixtures since the tools/fixtures may be empty as they move from an “unload position” (end of the line) to the “load position” (beginning of the line); requirement for a substantial support structure for the lines; difficulty in reconfiguration of the lines; imposition of work space by support rails for the lines; requirement for longer and more expensive curing ovens; lack of ergonomic height adjustments; and a requirement that the lines be designed and built for a maximum production rate. This requirement increases the cost of the line as well as the floor space which is required for the line. Various types of automated guided vehicles (AGVs) exist on the market today. However, AGVs may not be “system linked” and therefore, may act as individual units that do not communicate with each other. Moreover, AGVs may be large and expensive and may not be suitable or capable of precision low speeds which may be required for part-moving lines.	<SOH> SUMMARY <EOH>The disclosure is generally directed to a production moving line system. An illustrative embodiment of the production moving line system includes at least one metallic guide strip and at least one tow vehicle which may be adapted to follow the guide strip. The tow vehicle may include control circuitry and a power source and a wireless transceiver connected to the control circuitry. An assembly fixture cart may be coupled to the tow vehicle. A wireless communication link may be provided between a central control computer and the wireless transceiver of the tow vehicle. The disclosure is further generally directed to a production moving line method. An illustrative embodiment of the production moving line method may include the steps of providing at least one metallic guide strip, providing at least one tow vehicle having a wireless transceiver in guided contact with the guide strip, coupling an assembly fixture cart to the at least one tow vehicle, providing at least one part on the assembly fixture cart, providing a central control computer, providing a wireless communication link between the central control computer and the wireless transceiver of the tow vehicle and moving the tow vehicle along the guide strip.	TECHNICAL FIELD The disclosure relates to production moving line systems and methods. More particularly, the disclosure relates to a production moving line system and method in which multiple line-following tow vehicles are controlled wirelessly by a central computer. BACKGROUND Part moving lines may be used in assembly facilities to shuttle parts among multiple work stations. A conventional part moving line may utilize an automated guided vehicle (AGV) on which the part is placed and transported among and between the work stations. However, conventional part moving lines may suffer from any of multiple drawbacks. These may include, for example, breakdown of the entire part moving line in the event that one part of the line breaks down; duplication of tools/fixtures since the tools/fixtures may be empty as they move from an “unload position” (end of the line) to the “load position” (beginning of the line); requirement for a substantial support structure for the lines; difficulty in reconfiguration of the lines; imposition of work space by support rails for the lines; requirement for longer and more expensive curing ovens; lack of ergonomic height adjustments; and a requirement that the lines be designed and built for a maximum production rate. This requirement increases the cost of the line as well as the floor space which is required for the line. Various types of automated guided vehicles (AGVs) exist on the market today. However, AGVs may not be “system linked” and therefore, may act as individual units that do not communicate with each other. Moreover, AGVs may be large and expensive and may not be suitable or capable of precision low speeds which may be required for part-moving lines. SUMMARY The disclosure is generally directed to a production moving line system. An illustrative embodiment of the production moving line system includes at least one metallic guide strip and at least one tow vehicle which may be adapted to follow the guide strip. The tow vehicle may include control circuitry and a power source and a wireless transceiver connected to the control circuitry. An assembly fixture cart may be coupled to the tow vehicle. A wireless communication link may be provided between a central control computer and the wireless transceiver of the tow vehicle. The disclosure is further generally directed to a production moving line method. An illustrative embodiment of the production moving line method may include the steps of providing at least one metallic guide strip, providing at least one tow vehicle having a wireless transceiver in guided contact with the guide strip, coupling an assembly fixture cart to the at least one tow vehicle, providing at least one part on the assembly fixture cart, providing a central control computer, providing a wireless communication link between the central control computer and the wireless transceiver of the tow vehicle and moving the tow vehicle along the guide strip. BRIEF DESCRIPTION OF THE ILLUSTRATIONS FIG. 1 is a schematic block diagram of an exemplary tow vehicle. FIG. 2 is a partially schematic side view of a tow vehicle towing an assembly fixture cart on which is supported a part. FIG. 3 is a schematic diagram of a production moving line system in an illustrative implementation of the tow vehicles. FIG. 4 is a flow diagram illustrating an exemplary production moving line method. FIG. 5 is a flow diagram of an aircraft production and service methodology. FIG. 6 is a block diagram of an aircraft. DETAILED DESCRIPTION Referring initially to FIGS. 1-3, the present disclosure is generally directed to a production moving line system 40 (FIG. 3) in which multiple line-following tow vehicles 1 may be controlled wirelessly by a central computer 44. As will be hereinafter described, each tow vehicle 1 may be adapted to tow an assembly fixture cart 30 (shown in FIG. 2 and in phantom in FIG. 3) which carries a part or parts 36 (FIG. 2) among multiple production work stations 42 in the production moving line system 40. The part or parts 36 may be modified or assembled as part of a production or assembly process. Any number of tow vehicles 1 may be provided in a single production moving line 41 and may be system linked such that the tow vehicles 1 communicate with the central control computer 44. The tow vehicles 1 may also be adapted to communicate with each other. The tow vehicles 1 may move independently of each other and at various speeds depending on the transport requirements of the production moving line system 40. In the event that one tow vehicle 1 breaks down, the remaining tow vehicles 1 may continue transport without interruption in the production moving line 41. As shown in FIG. 1, an exemplary tow vehicle 1 which may be suitable for implementation of the production moving line system 40 is indicated in schematic block diagram form. The tow vehicle 1 may include a vehicle housing 24 (shown in phantom) which may completely or partially enclose the functional components of the tow vehicle 1. The vehicle housing 24 may have a compact design. The tow vehicle 1 may include control circuitry 2 which controls and coordinates the various functions of the tow vehicle 1. The various functional components of the tow vehicle 1 may be electrically connected to the control circuitry 2 such as through electrical connections 8 which may be wiring or direct electrical contacts, for example and without limitation. The control circuitry 2 may have a memory 12 which is adapted to store data. A data input/output device 18 may be connected to the control circuitry 2 to facilitate input of data into and retrieval of data from the memory 12. At least one battery 10 or other power source may be connected to the control circuitry 2 to supply electrical power to the control circuitry 2 and other functional components of the tow vehicle 1. The at least one battery 10 may have sufficient electrical storage capacity to power additional tools and accessories (not shown) connected to the at least one battery 10. A battery recharging system 11 may be connected to the at least one battery 10. The battery recharging system 11 may be adapted to facilitate on-the-fly electrical recharging of the at least one battery 10 during operation of the tow vehicle 1, which will be hereinafter described. A wireless transceiver 16 may be connected to the control circuitry 2. The wireless transceiver 16 may be adapted to facilitate wireless communication (receive and transmit data) between the tow vehicle 1 and the central control computer 44 (FIG. 3) in the production moving line system 40. The wireless transceiver 16 may also be adapted to facilitate wireless communication between the tow vehicle 1 and other tow vehicles 1 in the production moving line 41. A drive motor 3 may be connected to the control circuitry 2. A vehicle wheel or wheels 5 may be drivingly engaged by the drive motor 3 through a mechanical coupling 6 which is suitable for the purpose. The drive motor 3 may be a variable-speed electric drive motor, for example and without limitation, and may have the capability of towing an assembly fixture cart 30 weighing at least 500 pounds at precise speeds of from 1 inch per minute to up to 3,000 inches per minute, for example and without limitation. A steering mechanism 4 may be connected to the control circuitry 2 and coupled to the vehicle wheels 5 through a mechanical coupling 7 which enables the steering mechanism 4 to steer the vehicle wheels 5. A track sensing mechanism 14 may be connected to the control circuitry 2. The track sensing mechanism 14 may be adapted to follow a metallic floor-mounted guide strip 46 (FIG. 3) and provide data input to the control circuitry 3 which enables the steering mechanism 4 to steer the vehicle wheels 5 along the guide strip 46 of the production moving line system 41. The track sensing mechanism 14 may also be adapted to provide data input to the control circuitry 3 which enables the control circuitry 3 to terminate operation of the drive motor 3 and thus, rotation of the wheel or wheels 5 in the event that the tow vehicle 1 inadvertently leaves the guide strip 46. The control circuitry 2 may be adapted to monitor the position of the tow vehicle 1 with respect to other tow vehicles 1 moving in the production moving line 41, such as through input from the wireless transceiver 16, for example. A user interface pendant 20 may be hard-wired to the control circuitry 2 such as through a pendant cord 21, for example. The user interface pendant 20 may be adapted to manually override commands which are transmitted from the central control computer 44 to the control circuitry 2 through the wireless transceiver 16. The guide strip 46 of the production moving line system 40 may be a metallic passive element guide strip (not connected to a power source), in which case the track sensing mechanism 14 of each tow vehicle 1 may be adapted to sense the metallic properties of the guide strip 46. As shown in FIG. 3, the guide strip 46 may be attached to a floor 38 in a production or assembly facility. The guide strip 46 may be a strip of sheet metal, for example, and may be attached to the floor 38 using adhesive such as tape and/or glue and/or may be attached to the floor 38 using fasteners. In the example of the production moving line system 40 shown in FIG. 3, the guide strip 46 is configured to form a loop which extends generally among and adjacent to a first production work station 42a, a second production work station 42b, a third production work station 42c and a fourth production work station 42d. The guide strip 46 may be readily reshaped, lengthened, shortened or moved, as shown by the alternative pathways 46a, 46b (shown in phantom) of the guide strip 46. The central control computer 44 may communicate with the wireless transceiver 16 (FIG. 1) of each tow vehicle 1 through a wireless communication link 48. The central control computer 44 may be programmed to control and adjust the speed of each tow vehicle 1 in order to keep the production moving line system 40 synchronized in relation to all tow vehicles 1 in the production moving line 41. The wireless transceivers 16 of the tow vehicles 1 may communicate with each other through a wireless communication link 50. Therefore, the speed of each tow vehicle 1 may be additionally adjusted depending on the proximity of each tow vehicle 1 to the next tow vehicle 1 on the production moving line 41, responsive to operation of the position sensing mechanism 99 (FIG. 1) of the tow vehicle 1. In implementation of the production moving line system 40, each tow vehicle 1 may be adapted to tow an assembly fixture cart 30 (shown in phantom in FIG. 3) on which may be supported a part 36 or parts 36 (FIG. 2). An exemplary assembly fixture cart 30 is shown in FIG. 2 and may include a cart base 31 having multiple cart wheels 32. The cart wheels 32 may be castor-type wheels, for example and without limitation. A cart frame 33 may extend from the cart base 31. A cart platform 34 may be provided on the cart frame 33. The part 36 which is to be transported may be supported by the cart platform 34. The tow vehicle 1 may be situated between cart base 31 of the assembly fixture cart 30 and the floor 38 of the production or assembly facility. The vehicle housing 24 of the tow vehicle 1 may be coupled to the cart base 31 using a suitable coupling mechanism 26 such as clamps, for example and without limitation. The guide strip 46 may be attached to the floor 38 of the production or assembly facility and configured in any desired configuration. The guide strip 46 may extend among or adjacent to the production work stations 42 according to the order in which the production work stations 42 sequentially implement the production or assembly process, such as by modifying and/or assembling the part or parts 36 on each assembly fixture cart 30, for example and without limitation. Multiple tow vehicles 1, each of which may be coupled to an assembly fixture cart 30, may be placed on the guide strip 46. The cart wheels 32 (FIG. 2) of each assembly fixture cart 30 and the vehicle wheels 5 (FIG. 2) of each tow vehicle 1 may rest on the floor 38 on opposite sides of the guide strip 46. At least one part 36 (FIG. 2) may be placed on each assembly fixture cart 30. Throughout sequential transport of the parts 36 among the production work stations 42, the tow vehicles 1 may be operated to follow the guide strip 46 of the production moving line 41 in the direction indicated by the arrows in FIG. 3. Therefore, each assembly fixture cart 30, towed by a tow vehicle 1, may sequentially transport each part 36 to the first production work station 42a, the second production work station 42b, the third production work station 42c and the fourth production work station 42d, respectively. When the tow vehicle 1 which tows an assembly fixture cart 30 having a particular part or parts 36 arrives at each production work station 42, the tow vehicle 1, responsive to commands from the central control computer 44, may stop to facilitate retrieval of the part 36 from the assembly fixture cart 30. At the production work stations 42, the part 36 may be progressively modified and/or assembled throughout the production or assembly process. After modification and/or assembly at each production work station 42, the part 36 may be replaced on the assembly fixture cart 30. The tow vehicle 1 may then tow the assembly fixture cart 30 and the part 36 which is carried thereon to the next production work station 42 in the production or assembly sequence. As each tow vehicle 1 travels along the guide strip 46, the battery recharging system 11 (FIG. 1) may continually recharge the at least one battery 10. The central control computer 44 may transmit wireless commands to each of the tow vehicles 1 via the wireless communication link 48. These wireless commands may relate to starting and stopping of the tow vehicles 1 at each production work station 42 or between the production work stations 42, as well as the speed of the tow vehicles 1. The commands may include commands for one or more of the tow vehicles 1 to switch guide strips 46, for example and without limitation. The wireless commands which are transmitted from the central control computer 44 to each of the tow vehicles 1 may enable the production moving line system 40 to stay synchronized and maintain a controlled production or assembly rate. The position sensing mechanism 99 (FIG. 1) may continually sense the position of each tow vehicle 1 along the guide strip 46 and relay this position of the tow vehicle 1 to the control circuitry 2. Via the wireless transceiver 16 and wireless communication link 48, the control circuitry 2 may in turn transmit position-indicating data to the central control computer 44. In turn, based on the positions of the tow vehicles 1 along the guide strip 46, the central control computer 44 may determine the distance between consecutive tow vehicles 1 and may control or adjust this distance by controlling the operational speed of the drive motor 3 (FIG. 1) of each tow vehicle 1 via the wireless communication link 48. Additionally or alternatively, the control circuitry 2 of each tow vehicle 1 may determine the distance between that tow vehicle 1 and the adjacent front or rear tow vehicle 1 via the wireless communication link 50. The control circuitry 2 of the tow vehicle 1 may then relay this data via the wireless communication link 48 to the central control computer 44, which may adjust the speed of the tow vehicles 1 accordingly in order to achieve the desired distance between the consecutive tow vehicles 1. In the event that a tow vehicle 1 inadvertently leaves the guide strip 46, the track sensing mechanism 14 may notify the control circuitry 2, which may then terminate operation of the drive motor 3 of the tow vehicle 1. In addition to control of each tow vehicle 1 by operation of the central control computer 44 via the wireless communication link 48, the tow vehicles 1 may also be manually controlled using the handheld user interface pendant 20 (FIGS. 1 and 3). This may facilitate driving of a tow vehicle 1 off the guide strip 46 in order to make changes to the production moving line 41 such as, for example and without limitation, adding or removing assembly fixture carts 30 to or from, respectively, the production moving line 41; reconfiguring the production moving line 41 for production rates; and moving the production moving line 41 to a different location. Referring next to FIG. 4, a flow diagram 400 which illustrates an exemplary production moving line method is shown. In block 402, at least one metallic guide strip is provided. In block 404, at least one tow vehicle having a wireless transceiver is provided in guided contact with the guide strip. In block 406, an assembly fixture cart is coupled to the tow vehicle. In block 408, at least one part is provided on the assembly fixture cart. In block 410, a central control computer is provided. In block 412, a wireless communication link is provided between the central control computer and the wireless transceiver of the tow vehicle. In block 414, the tow vehicle is moved along the guide strip. Referring next to FIGS. 5 and 6, embodiments of the disclosure may be used in the context of an aircraft manufacturing and service method 78 as shown in FIG. 5 and an aircraft 94 as shown in FIG. 6. During pre-production, exemplary method 78 may include specification and design 80 of the aircraft 94 and material procurement 82. During production, component and subassembly manufacturing 84 and system integration 86 of the aircraft 94 takes place. Thereafter, the aircraft 94 may go through certification and delivery 88 in order to be placed in service 90. While in service by a customer, the aircraft 94 is scheduled for routine maintenance and service 92 (which may also include modification, reconfiguration, refurbishment, and so on). Each of the processes of method 78 may be performed or carried out by a system integrator, a third party, and/or an operator (e.g., a customer). For the purposes of this description, a system integrator may include without limitation any number of aircraft manufacturers and major-system subcontractors; a third party may include without limitation any number of vendors, subcontractors, and suppliers; and an operator may be an airline, leasing company, military entity, service organization, and so on. As shown in FIG. 6, the aircraft 94 produced by exemplary method 78 may include an airframe 98 with a plurality of systems 96 and an interior 100. Examples of high-level systems 96 include one or more of a propulsion system 102, an electrical system 104, a hydraulic system 106, and an environmental system 108. Any number of other systems may be included. Although an aerospace example is shown, the principles of the invention may be applied to other industries, such as the automotive industry. The apparatus embodied herein may be employed during any one or more of the stages of the production and service method 78. For example, components or subassemblies corresponding to production process 84 may be fabricated or manufactured in a manner similar to components or subassemblies produced while the aircraft 94 is in service. Also, one or more apparatus embodiments may be utilized during the production stages 84 and 86, for example, by substantially expediting assembly of or reducing the cost of an aircraft 94. Similarly, one or more apparatus embodiments may be utilized while the aircraft 94 is in service, for example and without limitation, to maintenance and service 92. Although the embodiments of this disclosure have been described with respect to certain exemplary embodiments, it is to be understood that the specific embodiments are for purposes of illustration and not limitation, as other variations will occur to those of skill in the art.	G	60G06	161G06F	19	00
11840169	US20090049251A1-20090219	SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE	ACCEPTED	20090205	20090219	[]	G06F1200	["G06F1200"]	8131957	20070816	20120306	711	162000	67970.0	KROFCHECK	MICHAEL	[{"inventor_name_last": "Bartfai", "inventor_name_first": "Robert Francis", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Boyd", "inventor_name_first": "Kenneth Wayne", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "James Chien-Chiung", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Day, III", "inventor_name_first": "Kenneth Fairclough", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Fienblit", "inventor_name_first": "Shachar", "inventor_city": "Ein Ayala", "inventor_state": "", "inventor_country": "IL"}, {"inventor_name_last": "McBride", "inventor_name_first": "Gregory Edward", "inventor_city": "Vail", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Messina", "inventor_name_first": "David W.", "inventor_city": "Malden on Hudson", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Nicholson", "inventor_name_first": "Robert Bruce", "inventor_city": "Southsea", "inventor_state": "", "inventor_country": "GB"}, {"inventor_name_last": "Spear", "inventor_name_first": "Gail Andrea", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}]	Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume.	1. A method to replicate data performed by a splitter executing in a storage controller managing access to primary volumes, comprising: receiving an initialization command to communicate with a replication engine; receiving a replication command for one primary volume; indicating the primary volume as subject to replication; receiving a write request to write data to a target primary volume of the primary volumes that is indicated as subject to the replication; writing the data in the write request to the target primary volume; and sending the data in the write request to the replication engine, wherein the replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. 2. The method of claim 1, wherein the replication engine and splitter communicate by packaging commands and data in a standard storage communication protocol package for transmission. 3. The method of claim 2, wherein there are a plurality of replication engines each implementing heterogeneous copy functions from different vendors, wherein the splitter is capable of using a same set of commands and the standard storage communication protocol to communicate with the different replication engines to invoke the heterogeneous copy functions. 4. The method of claim 1, further comprising: returning complete to the write request in response to receiving acknowledgment that the write completed at both the primary volume and at the replication engine volume. 5. The method of claim 1, further comprising: detecting a failure in communicating with the replication engine; recording indications in a record change data structure of writes to the primary volume that occur following the detected failure; receiving a request from the replication engine for the record change data structure; sending information on changed data in the record change data structure to the replication engine; and clearing the record change data structure in response to sending the record change data structure to the replication engine. 6. The method of claim 5, further comprising: receiving a request from the replication engine for updated data in the primary volume indicated in the record change data structure; and sending the requested updated data indicated in the record change data structure to the replication engine. 7. The method of claim 1, further comprising: receiving indication of a region to copy from the replication engine to the primary volume; requesting from the replication engine data indicated in the region; receiving data from replication engine indicated in the region; writing the received data indicated in the region to the primary volume; indicating that the data in the region was written to the primary in response to writing the data received from the replication engine to the primary volume. 8. The method of claim 7, further comprising: receiving a read request to data in the primary volume after receiving the list of regions; determining whether the read requested data is indicated in the list; redirecting the read request to the replication engine in response to determining that the read requested data is indicated in the list; and returning the read requested data from the primary volume in response to determining that the read requested data is not indicated in the list. 9. The method of claim 7, further comprising: receiving a write request to write data to the primary volume after receiving the region; determining whether the data to write is indicated in the region; and indicating that the data from the write request in the region was written to the primary volume in response to writing the data to the primary volume. 10. The method of claim 1, further comprising: receiving indication of a region to copy from the primary volume to the replication engine; sending data from the indicated region to the replication engine; and indicating that the data in the region was sent to the replication engine in response to sending the data indicated in the region to the replication engine. 11. The method of claim 1, further comprising: receiving a command to create a virtual primary volume associated with a replication engine volume; creating a virtual primary volume accessible to a host; receiving an Input/Output (I/O) request directed to the virtual primary volume; directing the I/O request directed to the virtual primary volume to the replication engine. 12. The method of claim 1, wherein the replication engine executes an additional function associated with the target primary volume. 13. A system managing access to primary volumes and in communication with a replication engine, comprising: a computer readable medium having primary volume metadata; and a splitter enabled to cause operations, the operations comprising: receiving an initialization command to communicate with the replication engine; receiving a replication command for one primary volume; indicating in the primary volume metadata that the primary volume is subject to replication; receiving a write request to write data to a target primary volume of the primary volumes that is indicated as subject to the replication; writing the data in the write request to the target primary volume; and sending the data in the write request to the replication engine, wherein the replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. 14. The system of claim 13, wherein there are a plurality of replication engines each implementing heterogeneous copy functions from different vendors, wherein the splitter is capable of using a same set of commands and the standard storage communication protocol to communicate with the different replication engines to invoke the heterogeneous copy functions. 15. The system of claim 13, wherein the splitter further causes operations comprising: detecting a failure in communicating with the replication engine; recording indications in a record change data structure of writes to the primary volume that occur following the detected failure; receiving a request from the replication engine for the record change data structure; sending information on changed data in the record change data structure to the replication engine; and clearing the record change data structure in response to sending the record change data structure to the replication engine. 16. The system of claim 13, wherein the splitter further causes operations comprising: receiving indication of a region to copy from the replication engine to the primary volume; requesting from the replication engine data indicated in the region; receiving data from replication engine indicated in the region; writing the received data indicated in the region to the primary volume; indicating that the data in the region was written to the primary in response to writing the data received from the replication engine to the primary volume. 17. The system of claim 16, wherein the splitter further causes operations comprising: receiving a read request to data in the primary volume after receiving the list of regions; determining whether the read requested data is indicated in the list; redirecting the read request to the replication engine in response to determining that the read requested data is indicated in the list; and returning the read requested data from the primary volume in response to determining that the read requested data is not indicated in the list. 18. The system of claim 13, wherein the splitter further causes operations comprising: receiving a command to create a virtual primary volume associated with a replication engine volume; creating a virtual primary volume accessible to a host; receiving an Input/Output (I/O) request directed to the virtual primary volume; directing the I/O request directed to the virtual primary volume to the replication engine. 19. An article of manufacture including code to communicate with a replication engine, manage access to primary volumes, and cause operations to be performed, the operations comprising: receiving an initialization command to communicate with the replication engine; receiving a replication command for one primary volume; indicating the primary volume as subject to replication; receiving a write request to write data to a target primary volume of the primary volumes that is indicated as subject to the replication; writing the data in the write request to the target primary volume; and sending the data in the write request to the replication engine, wherein the replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. 20. The article of manufacture of claim 19, wherein the replication engine and splitter communicate by packaging commands and data in a standard storage communication protocol package for transmission. 21. The article of manufacture of claim 20, wherein there are a plurality of replication engines each implementing heterogeneous copy functions from different vendors, wherein the splitter is capable of using a same set of commands and the standard storage communication protocol to communicate with the different replication engines to invoke the heterogeneous copy functions. 22. The article of manufacture of claim 19, wherein the operations further comprise: returning complete to the write request in response to receiving acknowledgment that the write completed at both the primary volume and at the replication engine volume. 23. The article of manufacture of claim 19, wherein the operations further comprise: detecting a failure in communicating with the replication engine; recording indications in a record change data structure of writes to the primary volume that occur following the detected failure; receiving a request from the replication engine for the record change data structure; sending information on changed data in the record change data structure to the replication engine; and clearing the record change data structure in response to sending the record change data structure to the replication engine. 24. The article of manufacture of claim 23, wherein the operations further comprise: receiving a request from the replication engine for updated data in the primary volume indicated in the record change data structure; and sending the requested updated data indicated in the record change data structure to the replication engine. 25. The article of manufacture of claim 19, wherein the operations further comprise: receiving indication of a region to copy from the replication engine to the primary volume; requesting from the replication engine data indicated in the region; receiving data from replication engine indicated in the region; writing the received data indicated in the region to the primary volume; indicating that the data in the region was written to the primary in response to writing the data received from the replication engine to the primary volume. 26. The article of manufacture of claim 25, wherein the operations further comprise: receiving a read request to data in the primary volume after receiving the list of regions; determining whether the read requested data is indicated in the list; redirecting the read request to the replication engine in response to determining that the read requested data is indicated in the list; and returning the read requested data from the primary volume in response to determining that the read requested data is not indicated in the list. 27. The article of manufacture of claim 25, wherein the operations further comprise: receiving a write request to write data to the primary volume after receiving the region; determining whether the data to write is indicated in the region; and indicating that the data from the write request in the region was written to the primary volume in response to writing the data to the primary volume. 28. The article of manufacture of claim 19, wherein the operations further comprise: receiving indication of a region to copy from the primary volume to the replication engine; sending data from the indicated region to the replication engine; and indicating that the data in the region was sent to the replication engine in response to sending the data indicated in the region to the replication engine. 29. The article of manufacture of claim 19, wherein the operations further comprise: receiving a command to create a virtual primary volume associated with a replication engine volume; creating a virtual primary volume accessible to a host; receiving an Input/Output (I/O) request directed to the virtual primary volume; directing the I/O request directed to the virtual primary volume to the replication engine. 30. The article of manufacture of claim 19, wherein the replication engine executes an additional function associated with the target primary volume.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. 2. Description of the Related Art In current network storage systems, a splitter can be implemented in a host or a switch to split writes directed to a volume managed by a storage controller to another storage device. The splitter sends a copy of the data to the storage controller and another copy to a replication engine that implements copy services to copy the data to a storage. The replication engine may comprise a separate network device or appliance. In one implementation, a splitter is implemented in the host software stack, such as the device driver or logical volume manager. In another implementation, the splitter may be implemented in the fabric, such as in a switch. In a yet further implementation, the splitter and the replication function are implemented within the storage controller, such as the case with Peer-to-Peer-Copy (“PPRC”), where a primary storage controller continuously mirrors or replicates data to a remote secondary site.	<SOH> SUMMARY <EOH>Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. In a further embodiment, the replication engine and splitter communicate by packaging commands and data in a standard storage communication protocol package for transmission. In a further embodiment, there are a plurality of replication engines each implementing heterogeneous copy functions from different vendors. The splitter is capable of using a same set of commands and the standard storage communication protocol to communicate with the different replication engines to invoke the heterogeneous copy functions. In a further embodiment, complete is returned to the write request in response to receiving acknowledgment that the write completed at both the primary volume and at the replication engine volume. In a further embodiment, a failure in communicating with the replication engine is detected. Indications of writes to the primary volume that occur following the detected failure are recorded in a record change data structure. A request is received from the replication engine for the record change data structure. Information on changed data in the record change data structure is sent to the replication engine. The record change data structure is cleared in response to sending the record change data structure to the replication engine. In a further embodiment, a request is received from the replication engine for updated data in the primary volume indicated in the record change data structure. The requested updated data indicated in the record change data structure is sent to the replication engine. In a further embodiment, indication is received of a region to copy from the replication engine to the primary volume. A request is made from the replication engine for data indicated in the region. Data from the replication engine indicated in the region is received and the received data indicated in the region is written to the primary volume. Indication is made that the data in the region was written to the primary in response to writing the data received from the replication engine to the primary volume. In a further embodiment, a read request to data in the primary volume is received after receiving the list of regions. A determination is made as to whether the read requested data is indicated in the list. The read request is redirected to the replication engine in response to determining that the read requested data is indicated in the list. The read requested data is returned from the primary volume in response to determining that the read requested data is not indicated in the list. In a further embodiment, a write request to write data to the primary volume is received after receiving the region. A determination is made as to whether the data to write is indicated in the region. Indication is made that the data from the write request in the region was written to the primary volume in response to writing the data to the primary volume. In a further embodiment, indication is received of a region to copy from the primary volume to the replication engine. Data is sent from the indicated region to the replication engine and indication is made that the data in the region was sent to the replication engine in response to sending the data indicated in the region to the replication engine. In a further embodiment, a command is received to create a virtual primary volume associated with a replication engine volume. A virtual primary volume accessible to a host is created. An Input/Output (I/O) request directed to the virtual primary volume is received and the I/O request is redirected to the replication engine. In a further embodiment, the replication engine executes an additional function associated with the target primary volume.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. 2. Description of the Related Art In current network storage systems, a splitter can be implemented in a host or a switch to split writes directed to a volume managed by a storage controller to another storage device. The splitter sends a copy of the data to the storage controller and another copy to a replication engine that implements copy services to copy the data to a storage. The replication engine may comprise a separate network device or appliance. In one implementation, a splitter is implemented in the host software stack, such as the device driver or logical volume manager. In another implementation, the splitter may be implemented in the fabric, such as in a switch. In a yet further implementation, the splitter and the replication function are implemented within the storage controller, such as the case with Peer-to-Peer-Copy (“PPRC”), where a primary storage controller continuously mirrors or replicates data to a remote secondary site. SUMMARY Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume. In a further embodiment, the replication engine and splitter communicate by packaging commands and data in a standard storage communication protocol package for transmission. In a further embodiment, there are a plurality of replication engines each implementing heterogeneous copy functions from different vendors. The splitter is capable of using a same set of commands and the standard storage communication protocol to communicate with the different replication engines to invoke the heterogeneous copy functions. In a further embodiment, complete is returned to the write request in response to receiving acknowledgment that the write completed at both the primary volume and at the replication engine volume. In a further embodiment, a failure in communicating with the replication engine is detected. Indications of writes to the primary volume that occur following the detected failure are recorded in a record change data structure. A request is received from the replication engine for the record change data structure. Information on changed data in the record change data structure is sent to the replication engine. The record change data structure is cleared in response to sending the record change data structure to the replication engine. In a further embodiment, a request is received from the replication engine for updated data in the primary volume indicated in the record change data structure. The requested updated data indicated in the record change data structure is sent to the replication engine. In a further embodiment, indication is received of a region to copy from the replication engine to the primary volume. A request is made from the replication engine for data indicated in the region. Data from the replication engine indicated in the region is received and the received data indicated in the region is written to the primary volume. Indication is made that the data in the region was written to the primary in response to writing the data received from the replication engine to the primary volume. In a further embodiment, a read request to data in the primary volume is received after receiving the list of regions. A determination is made as to whether the read requested data is indicated in the list. The read request is redirected to the replication engine in response to determining that the read requested data is indicated in the list. The read requested data is returned from the primary volume in response to determining that the read requested data is not indicated in the list. In a further embodiment, a write request to write data to the primary volume is received after receiving the region. A determination is made as to whether the data to write is indicated in the region. Indication is made that the data from the write request in the region was written to the primary volume in response to writing the data to the primary volume. In a further embodiment, indication is received of a region to copy from the primary volume to the replication engine. Data is sent from the indicated region to the replication engine and indication is made that the data in the region was sent to the replication engine in response to sending the data indicated in the region to the replication engine. In a further embodiment, a command is received to create a virtual primary volume associated with a replication engine volume. A virtual primary volume accessible to a host is created. An Input/Output (I/O) request directed to the virtual primary volume is received and the I/O request is redirected to the replication engine. In a further embodiment, the replication engine executes an additional function associated with the target primary volume. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of a network computing environment. FIG. 2 illustrates an embodiment of primary volume metadata maintained by a splitter. FIG. 3 illustrates an embodiment of primary volume metadata maintained by a replication engine. FIG. 4 illustrates an embodiment of how replication commands are packaged in communication protocols. FIG. 5 illustrates an embodiment of operations to initiate communication between the splitter and the replication engine. FIG. 6 illustrates an embodiment of operations to configure the splitter to split writes to the replication engine. FIG. 7 illustrates an embodiment of operations to process a write request to a primary volume to split to the replication engine. FIG. 8 illustrates an embodiment of operations to handle a communication failure between the splitter and the replication engine. FIG. 9 illustrates an embodiment of operations to copy data from the replication engine volume to the primary volume. FIG. 10 illustrates an embodiment of operations to process a read request to a region of the primary volume to be updated with data from the replication engine volume. FIG. 11 illustrates an embodiment of operations to process a write request to a region of the primary volume to be updated with data from the replication engine volume FIG. 12 illustrates an embodiment of operations to create a virtual primary volume associated with a replication engine volume. FIG. 13 illustrates a block diagram of a computer architecture in which certain described aspects of the embodiments are implemented DETAILED DESCRIPTION FIG. 1 illustrates an embodiment of a network computing environment. One or more hosts 2 send read/write requests for primary volumes 4 in one or more primary storages 6. One or more storage controllers 8 manage Input/Output (I/O) access from the hosts 2 to the primary volumes 4. The storage controllers 8 may include a splitter program 10 to copy write data to the primary volumes 4 to one or more replication engines 12 implemented in replication devices 14. Each replication engine 12 may invoke a copy service 16 to copy data received from the splitter 10 to replication engine volumes 18 maintained by the replication engine 12 in a storage 20. In further embodiments, the replication engine 12 may implement the copy services function in a manner that does not involve copying, such as by creating a log and logging write data to the log. The hosts 2, storage controllers 8, and replication devices 14 may communicate over a network 22. The network 22 may comprise a Storage Area Network (SAN), Local Area Network (LAN), Intranet, the Internet, Wide Area Network (WAN), peer-to-peer network, wireless network, arbitrated loop network, etc. The storages 6 and 20 may comprise a single storage device, such as a hard disk drive, Flash Memory, etc or an array of storage devices, such as a Just a Bunch of Disks (JBOD), Network Attached Storage (NAS), hard disk drive, Direct Access Storage Device (DASD), Redundant Array of Independent Disks (RAID) array, virtualization device, tape storage, flash memory, etc. In the embodiment of FIG. 1, the replication engine 12 is shown as implemented in separate device from the storage controller 8. In an alternative embodiment, the replication engine 12 may be implemented within the same system as the storage controller 8. For instance, the replication device 14 and storage controller 8 may comprise separate Logical Parturitions (LPARs) in a same box or system. Alternatively, the replication engine 14 and storage controller 8 may comprise expansion cards inserted into different slots of a same motherboard. In such implementations, the replication device 14 and storage controller 18 may communicate using standard protocols other than a network protocol, such as a bus communication protocol, e.g., the Peripheral Component Interconnect (PCI) protocol and architecture. FIG. 2 illustrates an embodiment of the primary volume metadata 26 the storage controller 8 maintains for one primary volume. The primary volume metadata 26 may include information indicating a primary volume 52; a replication flag 54 indicating whether the primary volume 52 is to be replicated to an identified replication engine 56; a change record data structure 58 used to record changes to a primary volume being replicated while communication between the storage controller 8 and replication device 14 is disabled; a revert data structure 60 identifying regions in a the primary volume 52 to be updated with data from the replication engine 12; and virtual mode information 62 indicating whether the primary volume 52 is a virtual volume in the primary storage 6 whose data is maintained in an associated replication engine volume 18. A virtual primary volume is created to expose a replication engine volume 18 to the hosts 2 as a primary volume managed by the storage controller 8. FIG. 3 illustrates an embodiment of the primary volume metadata 28 the replication engine 12 maintains for one primary volume 4. The primary volume metadata 28 includes primary volume 72 information identifying one primary volume 4; a replication engine volume 74 used to store data for the corresponding primary volume 72; a copy service 76 that the replication engine 12 invokes to store data for the primary volume 72 in the replication engine volume 74; and virtual mode 78 information indicating whether the primary volume 72 is a virtual volume in the primary storage 6. FIG. 4 illustrates an embodiment of how commands are communicated between the storage controllers 8 to one replication engine 12. The splitter 10 and replication engine 12 may cause the construction of a standard network communication package 90 having a network protocol header 92 according to a standard network communication protocol such as Fibre Channel, Ethernet, Serial Attached SCSI (SAS), etc. A standard storage communication package 94 may be encapsulated in the network communication package 90 with a storage protocol header 96 using a standard storage communication protocol, such as a Small Computer System Interface (SCSI). A replication command/message 98 may be included in the standard storage communication package 94 to implement the replication related operations, messages, and communications and, optionally, data 100. In one embodiment, splitters 10 and replication engines 12 from different vendors comprising heterogeneous and, perhaps, incompatible programs, may implement the same set of replication commands to enable communication and replication operations between heterogeneous splitters and replication engines from different vendors. In this way, a splitter or replication engine vendor may incorporate the replication command set into their products to allow communication with heterogeneous splitters and replication engines from different vendors that also implement the command set. Further, different replication engines 12 may implement different copy services 16 from different vendors to enable heterogeneous splitters 12 to invoke heterogeneous copy services 16 from different vendors through the replication engines 12 that support the copy services 16. FIG. 5 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to initialize communication. The splitter 10 receives (at block 120) a command 98, which may be included in the package 90 and 94 (FIG. 4), to initiate communication with the replication engine 12. The splitter 10 may receive this command via a user interface or command line of the storage controller 8. In response, the splitter 10 generates (at block 122) and sends a standard storage communication package 94, which may be encapsulated within a network communication package 90, with replication commands 98 and messages to initiate communicate with the replication engine 12. Upon receiving (at block 124) the replication communications to initiate communication with a splitter 10, the replication engine 12 performs operations (at block 126) to establish communication with the splitter 10, by sending further messages 98 to the splitter 10. FIG. 6 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to place a primary volume 4 in a replication relationship. In one embodiment, a user at a user interface of the replication device 14 invokes the replication engine 12 to generate and send (at block 150) a replication command 98 to the splitter 10 to replicate a specified primary volume 4. Upon receiving (at block 152) the replication command 98, the splitter 10 sets (at block 154) the replication flag 54 for the specified primary volume 52 to indicate to split data for the primary volume 52 to the identified replication engine 56, which may comprise the replication engine 12 that sent the replication command or another specified replication engine. FIG. 7 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to process a write request to a primary volume 4. Upon receiving (at block 170) a write request from a host 2 to a primary volume 4, the splitter 10 determines (at block 172) whether the replication flag 54 (FIG. 2) for the target primary volume 52 indicates replication. If replication is set, then the splitter 10 generates and sends (at block 174) a storage communication protocol package 94, which may be further included in a standard network communication package 90, including a copy replication command 98 and the write data 100 to the replication engine 12, which may comprise the replication engine 56 identified for the target primary volume. From the no branch of block 172 or from block 174, the splitter 10 writes (at block 176) the data to the primary volume 4. Upon the replication engine 12 receiving (at block 178) from the splitter 10 the copy replication command 98 with the data to replicate 100, the replication engine 12 determines (at block 180) a copy service 16 function to use to copy the received data. In one embodiment, the copy service 16 may be determined from the primary volume metadata 28 the replication engine 12 maintains for the primary volume or may be indicated in the replication command sent from the splitter 10. The replication engine 12 may execute (at block 182) the determined copy service 16 function to transfer the received data to the corresponding replication engine volume 18, which may be indicated in the field 74 of the primary volume metadata 28 (FIG. 3) maintained by the replication engine 12. Upon completing the copying, the replication engine 12 sends (at block 184) a message, comprising one replication command 98, to the splitter 10 that the write of the data completed. Upon receiving (at block 186) complete from the replication engine 12 for the transferred data, the splitter 10 sends (at block 188) a message to the host 2 initiating the write request that write of the data completed. FIG. 8 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to handle a failure in communication between the splitter 10 and the replication engine 12, such as a network 22 failure. Upon detecting (at block 200) a failure in the ability to communicate with the replication engine 12, the splitter 10 generates (at block 202) a change record data structure 58 for each primary volume in a replication relationship, as indicated by the replication flag 54 being set, to record changes to the primary volume 4 subject to replication following the detected failure. In a further embodiment, the splitter 10 may maintain a global data structure for a set of volumes. Upon reestablishing (at block 204) communication with the splitter 10 following a failure in the communication, the replication engine 12 generates and sends (at block 206) a replication command 98 in the standard storage communication protocol package 94 to the splitter 10 requesting information from the record change data structure 58 (which may comprise a copy of the record change data structure 58 or information extracted from the data structure 58). In response to receiving (at block 208) the replication command request for the record change data structure 58, the splitter 10 sends (at block 210) information from the record change data structure 58 to the requesting replication engine 12 using the standard storage communication protocol 94. The sent information may indicate those regions of the primary volumes subject to replication that were updating during the communication failure. Upon sending the replication engine 12 information on the record change data structure 58, the splitter 10 may further clear (at block 212) the record change data structure 58. Upon the replication engine 12 receiving (at block 216) the information from the record change data structure 58, the replication engine 12 sends (at block 218) one or more packages 94 of a command to the splitter 10 requesting the data updated in the primary volume 4 during the communication failure. In response to receiving (at block 220) the replication command 98 from the replication engine 12 requesting data in the primary volume 4 whose data was identified in the record change data structure 58, the splitter 10 transfers (at block 222) the requested data to the replication engine 12 in one or more messages in a standard storage communication protocol package 94. Upon receiving (at block 224) the requested data from the splitter 10, the replication engine 12 invokes (at block 226) the copy service 76 function for the splitter 10 to transfer the received data to the corresponding replication engine volume 18. The replication engine volume 18 corresponding to a primary volume 4 may be determined from the fields 72 and 74 in the primary volume metadata 28 maintained by the replication engine 12. In a further embodiment, when a resynchronization of the other regions is performed, the replication engine 12 may run the specific function that is required for the recovery procedure. FIG. 9 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to copy regions from the replication engine volume 18 to a primary volume 4. The replication engine 12 sends (at block 250) a command in standard storage protocol package 94 with list of regions at the replication engine volume 18 to copy to a primary volume 4. In response to receiving (at block 252) the copy command with the list of regions, the splitter 10 generates (at block 254) a revert data structure 60 (FIG. 2) for the target primary volume 4 indicating a list of regions in the primary volume to update with data from the replication engine 12. The splitter 10 sends (at block 256) a replication command 98 in a storage communication protocol package 94 and network package 90 to the replication engine 12 requesting data in the list of regions indicated in the revert data structure 60. Upon receiving (at block 258) the replication command from the splitter 10 requesting the list of regions, the replication engine 12 generates and sends (at block 260) to the splitter 10 one or more messages using the standard storage communication protocol package 94, and network package 90. The splitter 10, upon receiving (at block 262) the data, writes (at block 264) the data to the target primary volume 4. The splitter 10 indicates (at block 266) in the revert data structure 60 the primary volume locations updated with the data from the replication engine volume 18. If (at block 268) the revert data structure 60 indicates that all the indicated data was copied over, i.e., all the list of regions were copied from the replication engine volume 18 to the primary volume 4, then the splitter 10 sends (at block 270) an end status to the replication engine 12 indicating that the list of regions were copied from the replication engine volume 18 to the target primary volume 4. Otherwise, if (at block 268) the revert data structure 60 indicates that there are further regions to copy over, control ends. FIG. 10 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to handle read requests to a primary volume 4 having regions indicated in the revert data structure 60 to be updated with data from a replication engine volume 18. Upon the splitter 10 receiving (at block 300) a read request from a host 2 to a primary volume 4 location indicated in revert data structure 60 indicated as not updated, or waiting to be updated, the splitter 10 sends (at block 302) a replication command 98 to the replication engine 12 for the read requested data. Upon receiving (at block 304) the request for the read requested data, the replication engine 12 generates and sends (at block 306) the requesting splitter 10 one or more messages including the requested data, such as in the data field 100 of the standard storage communication package 94 within a network package 90. Upon receiving (at block 308) the requested data, the splitter 10 returns (at block 310) the received data to the host 2 initiating the read request and updates (at block 312) the primary volume 4 with the received data. The splitter 10 further indicates (at block 314) in the revert data structure 60 that the region in the primary volume 4 was updated. FIG. 11 illustrates an embodiment of operations performed by the splitter 10 to handle a write request from a host 2 to a region indicated in a revert data structure 60 as waiting for data from a replication engine volume 18. Upon the splitter 10 receiving (at block 330) a write request to a primary volume location indicated in the revert data structure 60 as not updated, the splitter 10 performs (at block 332) the operations at blocks 264-270 in FIG. 9 to update the data with the new write data. The splitter 10 further sends a replication message to the replication engine 12 with the updated data if the data is indicated to copy to the replication engine 12. FIG. 12 illustrates an embodiment of operations performed by the splitter 10 and replication engine 12 to manage a virtual primary volume 4 exposing a replication engine volume 18 to the hosts 2. The replication engine 12 (or some other component) may generate and send (at block 350) a replication command 98 to the splitter 10 requesting that splitter 10 create a virtual primary volume for a replication engine volume 18. The replication engine primary volume metadata 28 may indicate the virtual primary volume 72, corresponding replication engine volume 74 exposed through the virtual primary volume 72, and a virtual mode 78. Upon receiving (at block 352) the command to create the virtual primary volume, the splitter 10 creates (at block 354) a virtual primary volume by creating primary volume metadata 26 indicating the new virtual primary volume 52 with the virtual mode 62 set to indicate that the primary volume 52 is virtual. The splitter 10 returns (at block 356) a replication message 98 indicating that the requested virtual primary volume was created. Upon the splitter 10 receiving (at block 358) a read/write request directed to a primary volume indicated in virtual mode 62, the splitter 10 generates and sends (at block 360) a command 98 with the read/write request for the virtual primary volume to the replication engine 12. The replication engine 12 receives (at block 362) the command and executes (at block 364) the read/write request against the corresponding replication engine volume 18, indicated in the metadata 28 as associated with the primary volume 72. The replication engine 12 generates and sends (at block 366) a command 98 to the splitter 10 including return data and/or complete in response to executing the read/write request against the replication engine volume 18. The splitter 10 forwards (at block 368) the returned data or complete to the requesting host 2. Described embodiments provide techniques to enable data transfer operations between a splitter in a storage controller managing access to primary volumes and a replication engine managing access to replication engine volumes. The described embodiments provide techniques for the splitter to communicate with different replication engines implementing the replication command set. The replication engine 10 may invoke a copy service for the splitter in the storage controller splitting writes to the primary volume to a replication engine volume. Additional Embodiment Details The described operations may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The described operations may be implemented as code maintained in a “computer readable medium”, where a processor may read and execute the code from the computer readable medium. A computer readable medium may comprise media such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, DVDs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, Flash Memory, firmware, programmable logic, etc.), etc. The code implementing the described operations may further be implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.). Still further, the code implementing the described operations may be implemented in “transmission signals”, where transmission signals may propagate through space or through a transmission media, such as an optical fiber, copper wire, etc. The transmission signals in which the code or logic is encoded may further comprise a wireless signal, satellite transmission, radio waves, infrared signals, Bluetooth, etc. The transmission signals in which the code or logic is encoded is capable of being transmitted by a transmitting station and received by a receiving station, where the code or logic encoded in the transmission signal may be decoded and stored in hardware or a computer readable medium at the receiving and transmitting stations or devices. An “article of manufacture” comprises computer readable medium, hardware logic, and/or transmission signals in which code may be implemented. A device in which the code implementing the described embodiments of operations is encoded may comprise a computer readable medium or hardware logic. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the present invention, and that the article of manufacture may comprise suitable information bearing medium known in the art. The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise. The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise. The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise. Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries. A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention. Further, although process steps, method steps, algorithms or the like may be described in a sequential order, such processes, methods and algorithms may be configured to work in alternate orders. In other words, any sequence or order of steps that may be described does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order practical. Further, some steps may be performed simultaneously. When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself. The illustrated operations of FIGS. 5-12 show certain events occurring in a certain order. In alternative embodiments, certain operations may be performed in a different order, modified or removed. Moreover, steps may be added to the above described logic and still conform to the described embodiments. Further, operations described herein may occur sequentially or certain operations may be processed in parallel. Yet further, operations may be performed by a single processing unit or by distributed processing units. FIG. 13 illustrates an embodiment of computing system architecture 400 that may be implemented, in whole or in part, in the devices 2, 8, and 14 (FIG. 1). The architecture 400 may include one or more processors 402 (e.g., a microprocessor), a memory 404 (e.g., a volatile memory device), and storage 406 (e.g., a non-volatile storage, such as magnetic disk drives, optical disk drives, a tape drive, etc.). The storage 406 may comprise an internal storage device or an attached or network accessible storage. Programs in the storage 406 are loaded into the memory 404 and executed by the processor(s) 402 in a manner known in the art. The architecture further includes one or more adaptors 408 to enable communication over a network. An input device 410 may be used to provide user input to the processor 402, and may include a keyboard, mouse, pen-stylus, microphone, touch sensitive display screen, or any other activation or input mechanism known in the art. An output device 412 is capable of rendering information transmitted from the processor 402, or other component, such as a display monitor, printer, storage, etc. The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.	G	60G06	161G06F	12	00
11801670	US20080282189A1-20081113	System and method for simultaneous display of multiple tables	ACCEPTED	20081030	20081113	[]	G06F3048	["G06F3048"]	7925989	20070509	20110412	715	793000	78326.0	ALVESTEFFER	STEPHEN	[{"inventor_name_last": "Hofmann", "inventor_name_first": "Helmut", "inventor_city": "Sandhausen", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Koenigstein", "inventor_name_first": "Markus", "inventor_city": "Bad Schonborn", "inventor_state": "", "inventor_country": "DE"}]	In a system and method for displaying hierarchically related data, a processor may display in a single display window of a display device respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship, where each of at least two of the representations includes a respective table including a plurality of data columns, and where the display of some of the columns of the tables is in accordance with display settings set based on a determination that columns of different tables correspond to each other for alignment.	1. A method for displaying hierarchically related data, comprising: simultaneously displaying in a display window respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship; wherein: each of at least two of the representations includes a respective table, the respective table including a plurality of data columns; the at least two representations' represented data records depend from a common ancestor data record; and the respective tables are displayed nested in another table representing the ancestor data record. 2. The method of claim 1, wherein the respective tables differ from each other with respect to at least one of a number of included columns, data categories represented by respective columns, data types included in respective columns, and an order in which respective columns are arranged. 3. The method of claim 1, wherein a displayed representation includes a plurality of tables, each table including data records of a hierarchical level that is one lower than that of the data record represented by the displayed representation. 4. The method of claim 1, further comprising: displaying, for each of at least one of the hierarchically related data records, a control to toggle between an expanded and collapsed view of the respective one of the respective data records; wherein: when the expanded view is active, a table including child data records of the respective data record is displayed; and when the collapsed view is active, the table is not displayed. 5. The method of claim 1, further comprising: setting a display attribute of a first column of a first one of the respective tables based on a display attribute of a first column of a second one of the respective tables so that at least a portion of the first column of the first one of the respective tables and a portion of the first column of the second one of the respective tables are aligned when displayed in the displaying step. 6. The method of claim 5, wherein the display attribute of the first column includes at least one of a size and a display position. 7. The method of claim 5, further comprising: setting a width of a second column of the first one of the respective tables which is set for display to an immediate left of the first column of the first one of the respective tables as variable in accordance with a stored rule instructing to set as variable a column that is positioned to an immediate left of another column which is a table's left most column for which a display setting is set for column alignment with a column of another table; wherein, in accordance with the width's setting as variable, the width depends on a remaining display area of the first one of the respective tables after setting a position of the second column of the first one of the respective tables. 8. The method of claim 5, further comprising: setting a width of a second column of the first one of the respective tables which is set for display to an immediate left of the first column of the first one of the respective tables as variable in accordance with a stored rule instructing to set as variable a column that is positioned to an immediate left of another column for which a display setting is set for column alignment with a column of another table; wherein, in accordance with the width's setting as variable, the width depends on a remaining display area of the first one of the respective tables after setting a position of the second column of the first one of the respective tables. 9. The method of claim 8, wherein the rule instructs the setting as variable only those columns for which display settings are not set for column alignment with a column of another table. 10. The method of claim 5, further comprising: determining that the first column of the first one of the respective tables corresponds for alignment to the first column of the second table; wherein: the correspondence is determined based on one of: (a) a similarity of a data type between content of the first column of the first one of the respective tables and the first column of the second one of the respective tables, (b) a link between the first column of the first one of the respective tables and the first column of the second one of the respective tables set in accordance with a user input instruction, and (c) a shared column ID between the first column of the first one of the respective tables and the first column of the second one of the respective tables; and the setting of the display attribute of the first column of the first one of the respective tables based on the display attribute of the first column of the second one of the respective tables is performed conditional upon the determining that the first column of the first one of the respective tables corresponds for alignment to the first column of the second table. 11. A computer-readable medium having stored thereon instructions adapted to be executed by a processor, the instructions which, when executed, cause the processor to perform a method for displaying hierarchically related data, the method comprising: simultaneously displaying in a display window respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship; wherein: each of at least two of the representations includes a respective table, the respective table including a plurality of data columns; the at least two representations' represented data records depend from a common ancestor data record; and the respective tables are displayed nested in another table representing the ancestor data record. 12. A system for displaying hierarchically related data, comprising: a display device; and a processor configured to: display in a display window of the display device respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship; wherein: each of at least two of the representations includes a respective table, the respective table including a plurality of data columns; the at least two representations' represented data records depend from a common ancestor data record; and the respective tables are displayed nested in another table representing the ancestor data record. 13. The system of claim 12, wherein the respective tables differ from each other with respect to at least one of a number of included columns, data categories represented by respective columns, data types included in respective columns, and an order in which respective columns are arranged. 14. The system of claim 12, wherein a displayed representation includes a plurality of tables, each table including data records of a hierarchical level that is one lower than that of the data record represented by the displayed representation. 15. The method of claim 12, wherein: the processor is configured to display, for each of at least one of the hierarchically related data records, a control to toggle between an expanded and collapsed view of the respective one of the respective data records; when the expanded view is active, a table including child data records of the respective data record is displayed; and when the collapsed view is active, the table is not displayed. 16. The system of claim 12, wherein the processor is configured to set a display attribute of a first column of a first one of the respective tables based on a display attribute of a first column of a second one of the respective tables so that at least a portion of the first column of the first one of the respective tables and a portion of the first column of the second one of the respective tables are aligned when displayed in the display window. 17. The system of claim 16, wherein the display attribute of the first column includes at least one of a size and a display position. 18. The system of claim 16, further comprising: a memory storing a rule set, the rule set indicating an instruction to set as variable a column that is positioned to an immediate left of another column which is a table's left most column for which a display setting is set for column alignment with a column of another table; wherein: the processor is configured to set a width of a second column of the first one of the respective tables which is set for display to an immediate left of the first column of the first one of the respective tables as variable in accordance with the instruction; and in accordance with the width's setting as variable, the width depends on a remaining display area of the first one of the respective tables after setting a position of the second column of the first one of the respective tables. 19. The system of claim 16, further comprising: a memory storing a rule set, the rule set indicating an instruction to set as variable a column that is positioned to an immediate left of another column for which a display setting is set for column alignment with a column of another table; wherein: the processor is configured to set a width of a second column of the first one of the respective tables which is set for display to an immediate left of the first column of the first one of the respective tables as variable in accordance with the instruction; and in accordance with the width's setting as variable, the width depends on a remaining display area of the first one of the respective tables after setting a position of the second column of the first one of the respective tables. 20. The system of claim 16, wherein: the processor is configured to determine that the first column of the first one of the respective tables corresponds for alignment to the first column of the second table; the correspondence is determined based on one of: (a) a similarity of a data type between content of the first column of the first one of the respective tables and the first column of the second one of the respective tables, (b) a link between the first column of the first one of the respective tables and the first column of the second one of the respective tables set in accordance with a user input instruction, and (c) a shared column ID between the first column of the first one of the respective tables and the first column of the second one of the respective tables; and the setting of the display attribute of the first column of the first one of the respective tables based on the display attribute of the first column of the second one of the respective tables is performed conditional upon the processor determining that the first column of the first one of the respective tables corresponds for alignment to the first column of the second table. 21. A method comprising: providing data for transmission, the data including instructions adapted to be executed by a processor, the instructions which, when executed, cause the processor to perform a method for displaying hierarchically related data, the method comprising: simultaneously displaying in a display window respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship; wherein: each of at least two of the representations includes a respective table, the respective table including a plurality of data columns; the at least two representations' represented data records depend from a common ancestor data record; and the respective tables are displayed nested in another table representing the ancestor data record.	<SOH> BACKGROUND <EOH>Data can be arranged in an hierarchical fashion by a logical assignment of various data elements to classes and sub-classes of data. To allow a user to easily search for a particular data element, a tree structure is often displayed which can be traversed until the sought data element is found. For example, files arranged in directories and sub-directories are often represented visually in such a tree structure. A data element presented in an hierarchical tree structure is often selectable for viewing of particular properties and attributes of the data element. For example, in response to selection of a file in the tree structure, the file may be opened in a new display window to reveal its contents. The contents may include tables of interrelated data. For example, a transaction record represented in the tree structure may include, among other tables, a table of personal data of a customer with whom the transaction was conducted. Further, it is often the case that data of one cell of a table represents another sub-table. For example, a customer may be associated with multiple transactions. A cell indicating that the customer is associated with transactions may be selected to display a table including transactions data. For example, each row of the transactions data table may include data of a respective transaction record. To navigate all of the data, a user can traverse the tree structure to find a data element and select it to separately view its contents, e.g., a table of data. Contents of different data elements presented in an hierarchical tree structure can include similar tables or table components. However, at most, conventional computer systems provide for simultaneous display of two first hierarchical level tables that are not hierarchically related to each other. Further, the extent to which conventional systems provide for a hierarchical display of records that can be expanded to display corresponding tables is limited by the constraint that the tables of a same hierarchical level are of the same structure, i.e., they include the same column types in the same order. Conventional systems do not provide for presentation of hierarchically related tables in a manner via which relationships of different tables and table components of low hierarchical level tables can be visually discerned. In particular, conventional systems do not provide for presentation of differently structured tables in a manner via which relationships of the differently structured tables can be visually discerned.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a block diagram that illustrates components of a system according to an example embodiment of the present invention. FIG. 2 is a screenshot of a display including nested tables arranged according to an example embodiment of the present invention. FIG. 3 is flowchart that illustrates a method that may be performed to display a plurality of hierarchically related tables with collapse/expand indicators. FIG. 4 is a screenshot of a display that identifies alignment of corresponding columns of different tables, according to an example embodiment of the present invention. FIG. 5 is a flowchart that illustrates a method that may be performed to determine whether columns of a table are associated with columns of other tables for column alignment, according to an example embodiment of the present invention. FIG. 6 illustrates columns set as fixed or variable for alignment of corresponding columns of different tables, according to an example embodiment of the present invention. FIG. 7 is a flowchart that illustrates a method that may be performed to arrange columns in a display, according to an example embodiment of the present invention. FIG. 8 illustrates selective alignment of some of a plurality of columns arranged in different orders in different tables, according to an example embodiment of the present invention. FIG. 9 illustrates alignment of pairs of corresponding columns having a different number of intermediary columns, according to an example embodiment of the present invention. FIG. 10 illustrates alignment of pairs of corresponding columns having a different number of intermediary columns, according to an alternative example embodiment of the present invention. FIG. 11 illustrates partial alignment of pairs of corresponding columns having a different number of intermediary columns without alignment of column edges, according to an example embodiment of the present invention. FIG. 12 illustrates full alignment of pairs of corresponding columns having a different number of intermediary columns, according to an example embodiment of the present invention. FIG. 13 illustrates a width of a first column set based on maximum allowed white space and based on consideration of correspondence of another column of the same table as that of the first column with a column of another table, according to an example embodiment of the present invention. detailed-description description="Detailed Description" end="lead"?	BACKGROUND Data can be arranged in an hierarchical fashion by a logical assignment of various data elements to classes and sub-classes of data. To allow a user to easily search for a particular data element, a tree structure is often displayed which can be traversed until the sought data element is found. For example, files arranged in directories and sub-directories are often represented visually in such a tree structure. A data element presented in an hierarchical tree structure is often selectable for viewing of particular properties and attributes of the data element. For example, in response to selection of a file in the tree structure, the file may be opened in a new display window to reveal its contents. The contents may include tables of interrelated data. For example, a transaction record represented in the tree structure may include, among other tables, a table of personal data of a customer with whom the transaction was conducted. Further, it is often the case that data of one cell of a table represents another sub-table. For example, a customer may be associated with multiple transactions. A cell indicating that the customer is associated with transactions may be selected to display a table including transactions data. For example, each row of the transactions data table may include data of a respective transaction record. To navigate all of the data, a user can traverse the tree structure to find a data element and select it to separately view its contents, e.g., a table of data. Contents of different data elements presented in an hierarchical tree structure can include similar tables or table components. However, at most, conventional computer systems provide for simultaneous display of two first hierarchical level tables that are not hierarchically related to each other. Further, the extent to which conventional systems provide for a hierarchical display of records that can be expanded to display corresponding tables is limited by the constraint that the tables of a same hierarchical level are of the same structure, i.e., they include the same column types in the same order. Conventional systems do not provide for presentation of hierarchically related tables in a manner via which relationships of different tables and table components of low hierarchical level tables can be visually discerned. In particular, conventional systems do not provide for presentation of differently structured tables in a manner via which relationships of the differently structured tables can be visually discerned. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram that illustrates components of a system according to an example embodiment of the present invention. FIG. 2 is a screenshot of a display including nested tables arranged according to an example embodiment of the present invention. FIG. 3 is flowchart that illustrates a method that may be performed to display a plurality of hierarchically related tables with collapse/expand indicators. FIG. 4 is a screenshot of a display that identifies alignment of corresponding columns of different tables, according to an example embodiment of the present invention. FIG. 5 is a flowchart that illustrates a method that may be performed to determine whether columns of a table are associated with columns of other tables for column alignment, according to an example embodiment of the present invention. FIG. 6 illustrates columns set as fixed or variable for alignment of corresponding columns of different tables, according to an example embodiment of the present invention. FIG. 7 is a flowchart that illustrates a method that may be performed to arrange columns in a display, according to an example embodiment of the present invention. FIG. 8 illustrates selective alignment of some of a plurality of columns arranged in different orders in different tables, according to an example embodiment of the present invention. FIG. 9 illustrates alignment of pairs of corresponding columns having a different number of intermediary columns, according to an example embodiment of the present invention. FIG. 10 illustrates alignment of pairs of corresponding columns having a different number of intermediary columns, according to an alternative example embodiment of the present invention. FIG. 11 illustrates partial alignment of pairs of corresponding columns having a different number of intermediary columns without alignment of column edges, according to an example embodiment of the present invention. FIG. 12 illustrates full alignment of pairs of corresponding columns having a different number of intermediary columns, according to an example embodiment of the present invention. FIG. 13 illustrates a width of a first column set based on maximum allowed white space and based on consideration of correspondence of another column of the same table as that of the first column with a column of another table, according to an example embodiment of the present invention. DETAILED DESCRIPTION Embodiments of the present invention relate to a computer system and method for improving visualization of hierarchically structured data elements by providing an expanded tree structure with a visualization of the relationship of the different data elements in the tables regardless of hierarchical level. In particular, embodiments of the present invention provide for a display of hierarchically arranged nested tables. More particularly, embodiments of the present invention provide for the display of the nested tables in a manner that accentuates the relationships of different tables and/or table components of different tables of the same or different hierarchical levels of the hierarchical structure. In an example embodiment of the present invention, for such accentuation, columns of different ones of the tables that include the same type of data may be aligned. The computer system may include one or more computer programs written in any conventional computer language. Example computer languages that may be used to implement the computer system and method of the present invention may be Java, Extensible Markup Language (XML), C++, Structured Query Language (SQL) or other database query language, or a combination thereof. The computer program(s) may include, e.g., a plurality of routines for performance of different tasks. FIG. 1 is a block diagram that illustrates example components of a system on which embodiments of the present invention may be implemented. The system may include a memory 100, which may include any combination of conventional memory circuits, including electrical, magnetic, and/or optical systems. The memory 100 may include, for example, read only memory (ROM), random access memory (RAM), and/or bulk memory. The memory 100 may include a computer program 101 and a relational database 102. Information may be stored, e.g., relationally, in the database 102. For example, the information may be stored as a plurality of data elements. The data elements may include records associated with a plurality of further data elements that can be grouped in multiple ways. The further data elements with which the records are associated may be further records that are associated with other data elements, etc. A record's sub-records may include different record types. For example, an “expense” record may be associated with multiple transaction records, each transaction contributing to the expense record, and may be associated with multiple company records, each company contributing to the expense. The relationships between various data elements may include different kinds of cardinality. For example, cardinalities may include one to one, one to many, and/or many to many. The relational database 102 may store the records as nodes in a data structure definition. The data structure definition may include node definitions 120, where each node is represents a record. A node definition of a particular node for which one or more tables of data may be presented may include a node ID 121, a dependency pointer 122 pointing to an immediate parent of the particular node, child pointers 123, one or more table definitions 125, and table data 124 to be presented in the columns of the table defined by the table definition 125. A record may be stored as a separate node in the node definition 120, e.g., if the record is to be presented as its own separate table. Otherwise, the record may be provided as table data of a parent node. A child pointer 123 of the particular node may be included in the particular node's node definition to another node that is a child node of the particular node having its own defined node structure, if the particular node has such a child node. The table definition(s) 125 may include a plurality of column IDs 126, column constraints 127 such as a stipulation of a data type that may be included in the column (if there are any such constraints), and column headers 128. The computer program 101 may include a Graphical User Interface (GUI) generator component 116. A processor 105 may execute the computer program 101 for obtaining the information or parts thereof from the database 102 and displaying, via execution of the GUI generator component 116, tables including the obtained information according to the relationships between the data elements as defined by the node definitions 120, e.g., in accordance with prescribed criteria, for example, input by a user via an input device 111, e.g., at a terminal 110. For example, the GUI generator component 116 may generate different tables according to different hierarchical data structures 130, depending on which columns defined in the node definitions 120 the user indicates should be included in the provided tables. The processor 105 may output data for causing display of the generated tables on a GUI 112 provided in a monitor screen of the terminal 110. The memory 100 may be a memory of the terminal 110 or may be, e.g., a server memory that services a plurality of terminals. For example, the information of the database 102 may include information input by multiple users via distributed devices of a network, e.g., the Internet. The processor 105 may be any one or combination of suitably appropriate processing systems, such as, for example, a microprocessor, a digital signal processor, and a field programmable logic array. The processing system may be embodied as any suitably appropriate computing device, e.g., a computer, personal digital assistant (PDA), laptop computer, notebook computer, a hard-drive based device, or any device that can receive, send, and store data. FIG. 2 is a screenshot of a display the processor 105 may display on the GUI 112 via execution of the GUI generator component 116 of the computer program 101, according to an example embodiment of the present invention. The processor 105 may generate and display on the GUI 112 a plurality of tables that includes tables nested according to the hierarchy in which the data elements are stored in the database 102 and/or according to hierarchies specified for the present display, e.g., depending on user input indicating the particular constraints regarding which data to include in the display. Parts of the display may be selectable, e.g., via point and click of a mouse. For example, levels of nested tables may be expandable and collapsible via selection of records within the tables. The processor 105, via execution of the GUI generator component 130, may provide for expandable/collapsible selection of those displayed records for which a separate node definition 120 is provided. This may be determined based on the child pointers 123. For example, in an embodiment of the present invention, the processor 105 may display a collapse/expand indicator 202, such as an arrow that indicates that the record alongside which the arrow is displayed is expandable. The processor 105 may initially display a single parent table 205 representing a highest hierarchical level that includes a plurality of records, one or more of which are expandable. In response to a selection of an expandable record, e.g., via point and click of the record or of its associated indicator 202, via keyboard entries, and/or via other input types depending on the particular input device used, the processor 105 may update the display to include another table 206, e.g., in place of or below the selected record and within the table 206's parent table(s). The newly displayed table 206 may be of a lower hierarchical level than that of the parent table 205. (Depending on the cardinality structure, the hierarchy may take on various forms, such that the roles of parent and child in one hierarchy of the database 102 may be reversed in another hierarchy of the database 102. For example, the database may include a plurality of dependency and child pointer versions, where each version is associated with a different view or context. Depending on the view selected by the user or context in which the user inputs an instruction for display of the tables, the GUI generator 116 may generate a particular hierarchical structure in accordance with the corresponding pointer version. However, further discussion regarding the nature and structures of the hierarchies is not important for an understanding of the present invention). FIG. 3 is a flowchart that illustrates a method that may be performed during execution of the GUI generator component 116 for generating the parent table 205 representing the highest hierarchical level. At 300, the GUI generator component 116 may receive a table generation request. In response, the GUI generator component 116 may access the database 102 and search the node definitions 120 for a node having a record ID that matches one associated with the table of the highest hierarchical level. Starting at a first address of the node definitions 120, the GUI generator component 116 may determine, at 302, whether there is a record ID match. If there is not a match, the GUI generator component 116 may, at 304, increment the node definition address by 1, and return to 302 to check the record identifier of next node definition. When a match is found, the GUI generator component 116 may, at 306, display the table defined in the node's respective table definition 125 including the respective table data 124. For displaying the table at 306, the GUI generator component 116 may, at 308, determine, for each included record of the table(s) of the node definition 120 of the matched record ID, whether there is a child pointer 123 of the node definition 120 of the matched record ID that is associated with the particular included record. If there is such a child pointer 123, the GUI generator component 116 may, at 309, include an indicator 202 for the record. The GUI generator component 116 may then, at 310, move on to the next record if any. Otherwise, the GUI generator component may proceed to 310 without including an indicator 202. Steps 304-310 may be performed until each record of the table has been checked. The procedure of FIG. 3 may also be performed in response to each selection of an indicator 202, i.e., the selection may be interpreted as a table generation request. In one example embodiment of the present invention, in response to the input indicating an instruction to expand a record, the system and method of the present invention may display a table of a hierarchical level that is one level lower than that of the table to which the record selected for expansion belongs, e.g., so that the user can easily follow the progression through the data hierarchy. The newly displayed table may include further expandable records initially displayed in a collapsed state. In an alternative embodiment, in response to expansion of a record of a table of a highest hierarchical level, records of all lower hierarchical levels may be displayed initially in an expanded state so that the user is provided with all information of the data hierarchy associated in a single hierarchical branch with the record selected by the user. In one example embodiment of the present invention, the processor 105 may display the arrow indicators 202 pointing in different directions, depending one whether the associated records have been expanded. For example, the processor 105 may display an arrow pointing towards the right side of the GUI 112 to indicate that the associated record is in a collapsed state and an arrow pointing downwards to indicate that the associated record is in expanded state. In response to an instruction to expand a record, the processor 105 may insert within the table to which the record belongs a child table associated with the record and may change the direction of the arrow. The number of nesting levels of tables that originate from a root table and that are displayed by the processor 105 may depend on the particular hierarchical structure of the database 102 followed by the processor 105. For example, FIG. 2 illustrates tables nested down to a fourth hierarchical level. However, further levels are possible depending on the given hierarchy. In one example embodiment of the present invention, the number of different levels of tables simultaneously displayed on the GUI 112 may be limited only by the size of the GUI 112. In an example embodiment of the present invention, the user may select any displayed record's indicator 202. In response to the selection, the system and method may display the record's associated table, while maintaining the previous collapsed/expanded state of all other records displayed prior to the user selection. Thus, particular expandable records of a particular table may be displayed in an expanded state while other records of the particular table are simultaneously displayed in a collapsed state. For example, with respect to table 205, record 205.B is shown displayed in an expanded state, while records 205.A and 205.C are shown displayed in a collapsed state. The expanded record including a table with one or more records may be displayed between other records, including expanded and collapsed records, of the table to which the expanded record belongs. More than one record may be displayed simultaneously in an expanded state. For example, after performing the procedure described with respect to FIG. 3 for a first record of a low hierarchical level, the GUI generator component 116 may receive another table generation request with respect to a second record of a low hierarchical level, e.g., on a different hierarchy branch than that of the first record. In response to the new request, the GUI generator component 116 may update a previously generated display to include a new table corresponding to the second record for nested display in a parent table without removing the previously provided table of the first record from the display. The present invention accommodates nested tables that have different structures. For example, a non-exhaustive list of differences may include differences with respect to a number of included columns, data categories to which the columns correspond, data types included in the columns, and/or the order in which the tables' respective columns appear. For example, the respective structures of tables 205 and 206 are shown to be different at least with respect to the number of included columns and the particular data categories for which corresponding columns are provided. The tables having different structures may be of different hierarchical levels and/or of the same hierarchical level. With respect to records of the same hierarchical level having different table structures, the records may be of the same or different tables. For example, records 207.C and 207.D, which are of the same hierarchical level and which belong to the same table, i.e., table 207, are shown as being expanded to tables having different structures. Moreover, a single record may be expanded to display a plurality of differently structured tables. A record may include sub-records expandable to differently structured tables or may be expanded to display differently structured tables, for example, where, respectively, the sub-records of the record include different record types, or where the tables include records of different types. For example, an “expense” record may be associated with multiple transaction records, each transaction contributing to the expense record, and may also be associated with multiple company records, each company contributing to the expense. The tables having different structures, whether of the same or different hierarchical levels and whether of the same or different immediately preceding parent tables, may be simultaneously displayed. In an example embodiment of the present invention, different records of a same hierarchical level may be expanded to a different number of sub-hierarchical levels. For example, a first record of a particular hierarchical level may be fully expanded to a number of sub-hierarchical levels that correspond to a first number, i.e., first with respect to hierarchical sequence, of sub-hierarchical levels of a second record of the particular hierarchical level, so that the last of all of the sub-hierarchical levels of the first record may correspond to the last one of the first number of sub-hierarchical levels of the second record, although the second record may be further expanded to a second number of sub-hierarchical levels of lower hierarchical level than that of the last one of the first number of sub-hierarchical levels. A first record expandable to fewer hierarchical levels than a second record, e.g., of the same table as that of the first record, may be missing tables corresponding to tables of intermediate ones of the hierarchical levels of the second record, but may include tables corresponding to tables of hierarchical levels of the second record that are higher and lower than the intermediate hierarchical levels. For example, a first record may represent a company headquarters in charge of facilities throughout a country. A first sub-hierarchical level of the first record may include records representing managers of facilities in various regions of the country, each region including a number of states. A second sub-hierarchical level, which is a sub-hierarchical level of the records of the first sub-hierarchical level, may include records representing managers of facilities in particular ones of the states of the regions represented by their respective parent records. By contrast, a second record may represent another company headquarters in charge of facilities throughout the country. A first sub-hierarchical level of the second record may include records representing managers of facilities in particular states of the country. A hierarchical level including records representing managers of facilities in regions of the country may be omitted with respect to the second record. Thus, although tables may be of different hierarchical levels, they may be associated with each other. Their simultaneous display may aid the user in discerning the tables' associations with each other. Even where different tables that are logically associated with each other are simultaneously displayed, it can nevertheless be difficult for the user to visually comprehend the logical data associations, in particular where the tables are not separated from each by other records or where the tables are of different hierarchical levels. In an example embodiment of the present invention, a plurality of tables may be displayed simultaneously in a manner that accentuates relationships between data of the plurality of tables. For such accentuation, columns of different ones of the tables that include data determined to be associated with each other may be aligned. For example, FIG. 4 is a screenshot of a display similar to the screenshot of FIG. 2, but further indicates where columns of tables 208 and 209 have been aligned according to an example embodiment of the present invention. Whether columns of different tables are determined to be associated with each other by the GUI generator component 116 may depend, for example, on the different column IDs 126, column headers 128, and/or column constraints 127, as provided in a rule set 136, as explained below. According to an example embodiment of the present invention, columns of a plurality of tables of a single record determined to be associated with each other may be aligned. According to a further embodiment of the present invention, even columns that are of a plurality of simultaneously displayed tables of different corresponding records of an immediate parent record's table, and that are determined to be associated with each other may be aligned. According to a further embodiment of the present invention, even columns that are of a plurality of simultaneously displayed tables of different corresponding records of tables of different immediate parent records and that are determined to be associated with each other may be aligned. According to a further embodiment of the present invention, even columns that are of a plurality of simultaneously displayed tables of different hierarchical levels of a data tree and that are determined to be associated with each other may be aligned. In one example embodiment of the present invention, columns of different tables may be determined to be associated with each other if the columns are assigned the same column header 128. For example, a rule set 135 used by the computer program 101 for storing data in the database 102 may provide that for a particular table, each column must be assigned an ID unique with respect to other columns of the same table, but that the columns of different tables may be assigned the same column header 128. In an alternative example embodiment of the present invention, columns of different tables may be determined to be associated with each other if the columns are assigned the same column ID 126. For example, the rule set 135 used by the computer program 101 for storing data in the database 102 may provide that for a particular table, each column must be assigned an ID unique with respect to other columns of the same table, but that columns of different tables may be assigned the same ID. Unlike a column header, the column ID may be metadata that is not displayed by the GUI generator component 116 in response to a table generation request. Initially when entering the table data to be eventually included in the table display, or when updating the data, the user may assign the column IDs based on the user's determination that there is a relationship between different tables' columns. Use of column IDs instead of column headers may be advantageous because columns having categorically different data nevertheless may have a relationship to each other. Thus, the column IDs may be used for associating the columns to each other for purposes of alignment. The association for purposes of alignment may be performed so that a relationship between the columns' respective data may be visually discerned. For example, a table of a first hierarchical level may include a “net worth” column in the cells of which are included data indicating a respective record's associated company's net worth. Tables of lower hierarchical levels, which may be displayed by expanding the records of the first hierarchical level, may include a table having a column that includes cells, data of which indicate a particular asset value, and a table having a column that includes cells, data of which indicate a particular debt. The assets and debts may bear a relationship to the overall net worth represented in a record of the parent table. Accordingly, although the data represented in each of the tables may be categorically different, they may nevertheless bear a relationship for which a visual indication may be beneficial and may be provided based on shared column IDs according to an example embodiment of the present invention. In an alternative example embodiment of the present invention, other factors in addition to or instead of column ID may be taken into account for determining an association between columns of different tables. For example, the rule set 136 may provide that the GUI generator component 116 is to examine definitions of a data type of columns within different tables to identify a relationship between the columns. For example, data defining a number format (e.g., representing dollar amounts) may cause the columns to be considered related even if the column headings and/or IDs do not indicate a relationship. The columns determined to be related may be aligned, which may contribute to a display that is more easily reviewed by the user. In one example embodiment, the system and method of the present invention may provide for alignment of only those columns that include data in a number format. In particular, the system and method may provide for alignment of only those columns that include data in a particular number format type, e.g., a dollar amount format. More particularly, the system and method may provide for alignment of only those columns dedicated to inclusion of, e.g., only, data that is in the number format. Whether a column satisfies these conditions may be discerned by checking the table data 124 of the column and/or the column constraints 127 of the column. Alternatively or additionally, the system and method of the present invention may provide for manual association by a user between columns of different tables, regardless of an assignment of identical IDs or the inclusion of similar data types. For example, the GUI generator component 116 may generate a set-up page with a set of drop-down boxes presented in an hierarchy based on the dependency and child pointers 123 of the node definitions 120. The drop-down boxes may each correspond to a respective table and may include a list of column names of the respective table. The user may select a column header name and, e.g., drag and drop it on another drop-down box from which the user may select a column header name of the column with which the user desires an association to the dragged column header name. In response to the drag-and-drop, the GUI generator component 116 may access the database 102 to update the table definition 125 of the node corresponding to the dragged table and the node corresponding to the table at which it was dropped to include a pointer associated with each of the selected columns to the other selected column. Alternatively, for a displayed column, the user may otherwise input instructions identifying a particular table and column with which to associate the displayed column. Any other suitably appropriate method of inputting instructions may be used for manual association between columns. The particular conditions that must be satisfied for columns of different tables to be considered as being associated with each other for alignment may be stored in the rule set 136. For each column to be displayed, the GUI generator 116 may determine whether the column satisfies each condition of the rule set 136. FIG. 5 is a flowchart that illustrates a method that may be performed by the GUI generator component 116 to set a column to be displayed as being one that corresponds for alignment with a column of another table. At 500, the GUI generator component 116 may compare the column's ID with a column ID of another table to be included in the display to determine if there is a match. (Which other tables are to be included in the display may depend on which records were selected for expansion by the user.) If there is a match, the GUI generator component 116 may, at 502, store an indication that notes the association of the column with the column of the other table. After noting the association, the GUI generator component 116 may, at 504, determine if the table in which the corresponding column was found is the last of the tables to be included. If there are other tables, the GUI generator component 116 may, at 506, move on to the first column of the next table to be displayed, and repeat the steps starting at 500 with respect to the first column of the next table. If it is determined at 500 that there is no match, the GUI generator component 116 may, at 508, determine whether the previously checked column is the least of the columns of the table. If it is not the last column, the GUI generator component 116 may, at 508, move on to the next column of the table and repeat the steps starting at 500 with respect to the next column. If it is determined at 508 that the checked column is the last column, the GUI generator component 116 may perform 504. Steps 500 to 504 may be performed until it is determined at 504 that the previously checked table is the last of the tables to be displayed. As indicated above, whether columns of different tables correspond for alignment may depend on satisfaction of additional or different conditions than matching column ID. For each condition, the GUI generator component 116 may determine whether a column satisfies the condition and store a flag indicating whether the condition has been satisfied. If all flags are set indicating that the column satisfies the condition. If all flags are set indicating satisfaction of all of the conditions, the GUI generator component 116 may generate the tables so that the columns satisfying the condition are aligned with the columns indicated to be ones to which the column corresponds for alignment. In an example embodiment of the present invention, for arrangement of columns to provide for alignment between tables, the system and method may set a column width as either fixed or variable. A fixed column width is one that is based on the respective column's data, associations for alignment with columns of other tables, and/or rules of the rule set 136 regarding permissible column widths for a column. A variable column width is one that is based at least on a remaining space available to neighboring columns or to the respective column's table's edge after setting a position and width of the neighboring columns and/or after setting edges of the respective column based on correspondence for alignment of the respective column with a column of another table. A column's width may be set as variable if at least one of three conditions of the rule set 136, hereinafter referred to as condition 1, condition 2, and condition 3, is met. With respect to condition 1, a width of a first column of a first table may be set as variable if the first column corresponds for alignment with a first column of a second table and is positioned to an immediate left of a second column of the first table that is designated for alignment with a second column of the second table, and the first column of the second table is separated from the second column of the second table by an intermediate column. With respect to condition 2, a width of a first column of a first table may be set as variable if the first column does not correspond for alignment with any column of any other table and is positioned to an immediate left of a second column of the first table that is aligned with a column of another table. With respect to condition 3, a width of a first column of a first table may be set as variable if the first column corresponds for alignment with a first column of any other table and is a right-most of all aligned columns of the first table, and the first column of any of the other tables to which the first column of the first table corresponds is positioned to the left of more columns than is the first column of the first table. For a column that does not meet any of the three conditions, the column may be assigned a fixed width. The three conditions are exemplary. In alternative embodiments of the present invention, columns may be set as variable upon satisfying additional or alternative conditions. For example, condition 1 may be expanded to include setting as variable a width of a first column of a first table if the first column of the first table corresponds for alignment to a first column of a second table and is separated from a second column of the first table that is the first one of the columns to the right of the first column of the first table that correspond for alignment to any column of the second table by fewer columns than are the first column of the second table and the column of the second table to which the second column of the first table corresponds for alignment. For example, with respect to FIG. 12 (which does not illustrate implementation of this variant condition 1 for assigning a variant width), column 1203 satisfies this variant condition 1. In one alternative example embodiment of the present invention, only a column to the immediate left of a left most one of the columns of the table that corresponds for alignment with a column of another table is set as a variable width column. FIG. 6 shows assignments of either variable or fixed widths to columns of a plurality of tables, where the assignments are determined based on whether any of the three conditions is met. The width of column 623 is set as variable since column 623 satisfies condition 1. In this regard, column 623 corresponds for alignment with column 614 and is positioned to the immediate left of column 624 which corresponds for alignment with column 616 which is separated from column 614 by intermediate column 615. The widths of columns 621, 631, 632, 641, 642, and 653 are similarly set as variable since these columns satisfy condition 1. The width of column 652 is set as variable since column 652 satisfies condition 2. In this regard, column 652 does not correspond for alignment with columns of any of the other tables 600-660 and is positioned to the immediate left of column 653 which corresponds for alignment with columns 604, 614, 623, 642, and 665. The width of column 663 is similarly set as variable since this column satisfies condition 2. The width of column 616 is set as variable since column 616 satisfies condition 3. In this regard, column 616 corresponds for alignment with columns 606, 624, 643, 654, and 667. Column 616 is a right-most of all aligned columns of table 610, and columns 606 and 667 are each positioned to the left of more columns than is column 616. The widths of columns 624, 633, 643, and 654 are similarly set as variable since these columns satisfy condition 3. The widths of the remaining columns 601-607, 611-615, 622, 651, 661-662, and 664-668 are set as fixed since these columns do not satisfy any of the three conditions. FIG. 7 illustrates a method for arranging a display of columns in which corresponding columns may be aligned, according to an example embodiment of the present invention. The system and method may initially, at 700, determine whether the column corresponds for alignment with a column of another table. For example, the method described with respect to FIG. 5 may be performed at this point. However, additional conditions besides for matching column ID may also be considered, such as data type of the column. Furthermore, as discussed in detail below, table display constraints, in particular in view of association for alignment between other columns may impact whether the GUI generator component 116 sets a column as corresponding for alignment with other columns. Accordingly, after setting a tentative indication that columns correspond for alignment with columns of other tables, the system may determine for a first column having a tentative indication that it corresponds for alignment with another column whether the indication should be finalized based on the tentative indications of other columns. After determining, for each of the columns to be displayed, whether the column corresponds for alignment with a column of another table, the system may, at 702, determine for each column whether the column's width should be set as variable or fixed, e.g., by determining whether the column satisfies any of the three conditions. For example 702 may include 703-707. At 703, the system may determine whether a column satisfies condition 1. If it satisfies condition 1, the system may, at 706, set the column's width as variable. If it does not satisfy condition 1, the system may, at 704, determine whether the column satisfies condition 2. If it satisfies condition 2, the system may proceed to 706. Otherwise, the system may, at 705, determine whether the column satisfies condition 3. If it satisfies condition 3, the system may proceed to 706. Otherwise, the system may, at 707, set the column width as fixed. After the determination whether to set the column width as fixed or variable is made for each column, the system and method may, at 708, set, for each fixed width column, the column's width to the lesser of (a) the maximum allowed column width and (b) the width required for display of all of the data of the cell(s) of the column (and all corresponding columns of other tables if any) that includes the greatest amount (with respect to required display space) of data. In an alternative example embodiment, 708 may be performed during 702 after each determination that a column should be fixed. After the widths of the fixed width columns are set, the system and method may set the positions for each column. For setting the columns' positions, the system and method may, at 709, set positions for the fixed width columns of all of the tables and may then, at 710, set positions for the variable width columns of all of the tables. To set the positions of the fixed width columns of a table, the system and method may begin with the right-most fixed width column of the table and move onwards towards the left of the table. To set the position of a fixed width column, if the column is a right-most column of the table, its right edge may be set at the right edge of the table. Its left edge may be set at a position that is at a distance from the column's right edge that corresponds to the column's set column width. If the fixed width column is not the right-most column of the table and the position of the left edge of the column to its immediate right has been set, its right edge may be set at the left edge of the column to its immediate right. Its left edge may be set at a position that is at a distance from the column's right edge that corresponds to the column's set column width. If the fixed width column is not the right-most column of the table and the position of the left edge of the column to its immediate right has not been set, its left edge may be set at the first column position for fixed width columns of the table if it is the left-most fixed width column of the table. The first column position may be tentatively set in accordance with a display area determined by the equation [ ( max * var_width  _col  _no ) + ( max * var_width  _cond1  _no ) + ( max * ∑ n = 0 x   no_right  _cor  _col  _cond3  ( n ) ) + ∑ n = 0 m  width   of   fixed_width  _col  ( n ) ] , where max is the maximum width of all of the tables' fixed columns' widths, var_width_col_no is the number of columns of the table that are variable, var_width_cond1_no is the number of columns of the table that satisfy condition 1, no_right_cor_col_cond3(n) is the number of columns to the right of a column that corresponds to the variable column ‘n’ of the table satisfying condition 3 and that is of a table having the most number of columns to the right of any table's column corresponding to the column ‘n,’ x is the number of columns of the table satisfying condition 3, and m is the number of fixed width columns of the table. Once the tentative display area is determined, the left edge of the fixed column may be positioned at a distance from the first column position of the table that equals ([max]*[number of columns to the fixed width column's left]). Its right edge may be set at a position that is at a distance from the column's left edge that corresponds to the column's set column width. The calculated display area may be larger than actually necessary. In one example embodiment of the present invention, subsequent to positioning of all of the columns, the system and method may adjust the positioning to provide a smaller display area. In an alternative embodiment, the larger display area may be maintained. In another alternative embodiment, instead of applying ‘max’ as the width for all of the variable width columns of the table, the calculation of the display area and the portion of the display area required to the left of the fixed column to be positioned may be fine tuned to the particular fixed column widths of the fixed columns on which are based the widths of the variable width columns of the table. If the fixed width column is not the right-most column of the table, the position of the left edge of the column to its immediate right has not been set, the fixed width column is not the left-most fixed width column of the table, and the column corresponds for alignment with a column of another table the position of the left edge of which has already been set, its left edge may be set at the horizontal location of the display corresponding to the horizontal location of the set left edge of the column to which the fixed width column corresponds for alignment. Its right edge may be set at a position that is at distance from the column's left edge that corresponds to the column's set column width. If the fixed width column is not the right-most column of the table, the position of the left edge of the column to its immediate right has not been set, the column is not the left-most fixed width column of the table, and the column does not correspond for alignment to a column of another table the position of the left edge of which has already been set, the system and method may seek a next column to the left of the fixed width column which is itself fixed and which corresponds for alignment with a column of another table the position of the left edge of which has been set or which is the left most fixed width column of the table. If such a next column is found, the system and method may set the position of the found column. The system and method may then set, based on assigned widths, all fixed width columns that consecutively follow the found column to the right of the found column without interruption by variable width columns. If there are only variable columns to the left of the fixed width column or if there is a variable width column between the found column and the fixed width column, the system and method may interrupt setting a position for the fixed width column, and move on in the table to the left of the found column to the next fixed width column for which positions have not yet been set, if any. If positions of any of the fixed width columns to the left of the found column can be set as described above, the system and method may do so. Once all of the fixed width columns of the table, the positions of which can be set as described above, have been set, the system and method may interrupt setting the positions of the fixed width columns of the table and move on to setting fixed width columns of following tables. After performing these steps for all of the tables, the system and method may return to the tables including fixed width columns for which positions were not determined in the previous loop through the method and attempt to set the positions of the fixed width columns for which positions were not previously set. The loop may be repeated until the positions of all of the fixed width columns have been set. After all of the positions are set for all columns having fixed column widths, the system and method may set the positions of the columns having variable column widths. The system and method may begin at the right most column of a table and continue towards the left. If a variable width column is a right most column of a table, the system and method may set its right edge at the right edge of the table. If the variable width column is not a right most column of the table, the system and method may set its right edge at a left edge of the column to its immediate right. With respect to the left edge of the variable width column, if the column to the immediate left of the variable width column is a fixed width column, the system and method may set the left edge of the variable width column at the right edge of the fixed width column to the immediate left of the variable width column. If the column to the immediate left of the variable width column is itself a second variable width column, then the first variable width column is variable for the reason that it satisfies either condition 1 or condition 3, i.e., the first variable width column corresponds for alignment with a column of at least one other table. (The first variable width column does not satisfy condition 2, since, if it did, the column to its immediate left would have been fixed.) Accordingly, the system and method may search other tables for a column to which the first variable width column corresponds for alignment and the left edge of which had been previously set. For example, the column of the other table may be a fixed width column, the position of which had been set prior to setting of the variable width columns, or may be another variable width column the left edge of which has been set, e.g., based on the right edge of a fixed width column to its immediate left or based on another previously set column to which the other variable width column corresponds. In one example embodiment of the present invention, if the variable width column is a left most column of the table and does not correspond for alignment with a column of any other table, the system and method may postpone setting the position of the left edge of the variable width column until after positions of left edges of all of the columns of all of the tables, but for left most variable width columns, have been set. At this point, a first column position of each table may be determined. In an alternative example embodiment of the present invention, the system and method may postpone setting the position of the left edge of the variable width column until after positions of the left edges of all of the columns of all of the tables of the same hierarchical level as that of the table to which the variable width column belongs, but for the left most variable width columns, have been set. According to this alternative, tables of different hierarchical may have different column starting positions, at least if first columns of tables of different hierarchical levels do not correspond for alignment. In an alternative example embodiment of the present invention, each table may have its own defined first column starting position. According to this alternative, if a first column of a table is a variable width column that does not correspond for alignment with any other column, the system and method may set a width for the column as the lesser of (a) the predetermined maximum allowed column width and (b) the width required for simultaneous display of all of the data of the cell(s) containing the greatest amount (with respect to required display space) of data of all of the cells of the column. The left edge of the variable width column may be set in accordance with the determined width. In an alternative example embodiment of the present invention, condition 2 may be limited to only those columns that are not left most columns of their respective tables, in which case the column's position would be set as described above with respect to fixed width columns. An example implementation of some of the features of the method described above may be described with respect to FIG. 6. With respect to FIG. 6, after determining for each column whether the column is a variable or fixed width column and setting the widths of the fixed width columns, the system and method may begin to set positions of the columns of table 600. Since all of the columns of table 600 are fixed width columns, their positions may be set during an initial pass through the method. The system and method may then proceed to column 615 of table 610, since it is the right most fixed width column of table 610. To set the column's position, the system and method may set the left edge of column 615 to the same horizontal position of the left edge of column 605. The right edge of column 615 may be set to the position at a distance from the column's left edge that corresponds to the column's set fixed distance. The rest of the columns of table 610 to the left of column 615, which are all fixed width columns, may be set based on the position of each column's neighboring column to the right. The system and method may then set the position of column 622 of table 620 in accordance with the position of the left edge of column 613 of table 610. The position of column 651 of table 650 may be set in accordance with the position of the left edge of either of columns 601 and 611. The system and method may then set the positions of columns 668-664 since they are all fixed width columns and are the right most columns of table 660. The system and method may then set the position of column 661 based on the position of the left edge of any of columns 601, 611, and 651. After setting the position of column 661, the system and method may set the position of column 662 so that its left edge is at the right edge of column 661. The positions of all of the fixed width columns having been set, the system and method may begin setting positions of the variable width columns. The right edge of column 616 may be set at the right edge of table 610. The left edge of column 616 may be set at the right edge of column 615. The right edge of column 624 may be set at the right edge of table 620. The left edge of column 624 may be set at the same horizontal position as that of either of columns 606 and 616. The right edge of column 623 may be set at the left edge of column 624. The left edge of column 623 may be set at the right edge of column 622. The right edge of column 621 may be set at the left edge of column 622. The left edge of column 621 may be set at the same horizontal position as that of the left edge of either of column 601 and column 611. With respect to table 630, the positions of columns 633-631 may be similarly set based on, e.g., the positions of columns 615, 613, and 611, respectively. With respect to table 640, the positions of columns 643-641 may be similarly set based on, e.g., the positions of columns 616, 614, and 611, respectively. With respect to table 650, the positions of columns 654 and 653 may be similarly set based on, e.g., the positions of columns 616 and 614, respectively. The position of column 652 may be set based on the positions of columns 653 and 651. With respect to table 660, the position of column 663 may be set based on the positions of columns 664 and 662. In an alternative example embodiment of the present invention, the system and method may initially set positions of columns of each table without consideration of positions of corresponding columns of other tables. During the initial positioning, a temporary column width, e.g., a predetermined minimum column width, may be assigned to variable width columns of the table. After positioning of all of the columns of all tables, column positions may be adjusted based on inter-table column correspondence. In an alternative example embodiment of the present invention, the widths of all tables that correspond for alignment with columns of other tables may be set as fixed. For example, setting of a variable column width may be limited to those columns satisfying condition 2. According to this embodiment, if a first column of a first table satisfies condition 1, i.e., (a) it corresponds for alignment with a first column of at least one second table and is positioned to the left of a second column that corresponds for alignment with a second column of the at least one second table, and (b) the at least one second table includes more intermediate columns between its respective first and second columns than does the first table, the width of the first column of the first table may be set as fixed. To determine its width, the system and method of the present invention may determine which of the at least one second table includes the most intermediate columns. The width may then be set based on a width required for display of the contents of each of the first columns of the first table and any other tables' corresponding first columns plus the widths of each of the intermediate columns of the table determined to include the most intermediate columns. For example, referring to FIG. 6, the width of column 621 may be set as fixed. Its width may be set to be wide enough to simultaneously display all of its contents and all of the contents of each of columns 601, 611, 631, 641, 651, and 661, plus the width of column 602 or 612 which are each an intermediate column separating, respectively, columns 601 and 603, and columns 611 and 613, where columns 603 and 613 correspond for alignment with column 622. According to this embodiment, if a first column of a first table satisfies condition 3, i.e., it corresponds for alignment with a first column of at least one second table, is a right-most of the first table's aligned columns, and one or more of the at least one second table includes additional aligned columns to the right of its respective first column, the width of the first column of the first table may be set as fixed. To determine its width, the system and method of the present invention may determine which of the at least one second table includes the most aligned columns to the right of its respective first column. The width of the first column of the first table may then be set based on its contents and the contents of the corresponding columns of the other tables plus the widths of all of the aligned columns to the right of the first column of the one of the at least one second table including the most aligned columns to the right of its respective first column. For example, referring to FIG. 6, the width of column 633 may be set as fixed. Its width may be set based on the size of its contents and all other columns ‘E’ plus the widths of either columns 605-607 or 666-668. In one example embodiment of the present invention, alignment of columns of different tables may be limited to different tables having the same or similar structure, e.g., having the same number of columns, same data categories to which the columns correspond or same column IDs, and/or same order in which the tables' respective columns appear. For example, tables 208 and 209 of FIG. 4, the columns of which are aligned, include the same number of columns, having the same column headers, ordered in the same way. According to this embodiment, columns of different tables that are aligned with each other may be set to a same column size. For example, the column width of all columns of a set that are aligned with each other may be set based on a largest data string included in the cells of all of the set of columns combined. In an alternative example embodiment of the present invention, columns of tables having different column structures may also be aligned. However, the extent of implementable column alignment between non-similarly structured tables may be limited as detailed below. According to this embodiment, it may occur that two tables include more than one pair of columns associated with each other for alignment and that the tables' respective columns belonging to the column pairs occur in different orders. For example, referring to FIG. 8, column 802 of table 800 and column 803 of table 801 are assigned a same column ID (or column header) ‘A’ and column 804 of table 800 and column 805 of table 801 are assigned a same column ID ‘B’. However, the column A and B of the different tables 800 and 801 appear in reverse order. In this instance, according to an example embodiment of the present invention, one of the pairs of the associated columns may be aligned, while the other pair may remain unaligned as shown in FIG. 4. The rule set 136 according to which the system and method of the present invention align columns of different tables may provide for maximizing the number of columns that are aligned with corresponding columns of another table. For example, columns of different tables that are associated with each other with respect to alignment, e.g., where they share IDs, may be arranged in different sequences by the node definitions 120. The out-of-sequence column pairs may include sets of in-sequence column pairs. Further, the different in-sequence column pair sets may include different numbers of column pairs. In this instance, the rule set 136 may provide that the set having the larger number of in-sequence column pairs is to be aligned and the set having the smaller number of in-sequence column pairs are not to be aligned. For example, in FIG. 8, the tables 800 and 801 include two sets of columns associated for alignment, i.e., set 810 including column pairs B-B (804-805) and C-C (806-807) and set 811 including column pair A-A (802-803). Since set 810 includes more pairs of columns associated for alignment than does set 811, the rule set 136 may provide for alignment of the columns of set 810, while leaving the columns of set 811 unaligned. However, the rule set 136 may identify a plurality of conditions other than the number of in-sequence column pairs, to be considered for determining which sets of column pairs are to be aligned. For example, the rule set 136 may attach particular significance to columns designated for or that are determined to include data having a number format. Numbers may be significant with respect to column alignment since numbers are often compared, e.g., to determine or discern the particular transaction amounts of a plurality of tables that are summed to a total amount shown in yet another table. To attach more significance to satisfaction of one condition than to satisfaction of another feature, the rule set 136 may assign different weights for each satisfied condition. For each alignment option, an overall score may be calculated by adding the different weights associated with the alignment option. According to this embodiment, the rule set 136 may provide that the columns of set 811 should be aligned at the expense of the non-alignment of the pairs of columns of set 810 if the columns 802 and 803 include data in a number format and none of the columns of the set 810 include data in the number format (or if none of the pairs of the set 810 includes two columns that each includes data in the number format). The rule set 136 may provide for alignment of the set of column pairs that includes the most columns including data in a number format. This is just one example of a condition that the rule set 136 may provide for determining which set of column pairs to align. Even of those sets of inter-table column pairs that appear in a same sequence in each of the tables, it may occur that each table includes a different number of columns that are not associated for alignment with the other table and interspersed amongst the columns that are associated for alignment, than the set of the other table. For example, FIG. 9 shows a table 900 that includes columns 902 and 904 that are associated for alignment with columns 903 and 905, respectively, of table 901. However, while columns 902 and 904 are positioned next to each other without interruption, columns 903 and 905 are separated by column 906 which is not associated for alignment with any column of table 900. In one example embodiment of the present invention, where two consecutive columns of a first table are associated for alignment with two non-consecutive columns of a second table that appear in the same order as that of the two consecutive columns of the first table, the system and method may provide for aligning either the first or the second of the two consecutive columns of the first table with the corresponding column of the second table, without aligning the other corresponding columns. The two aligned columns may be assigned the same column width. According to an alternative example embodiment of the present invention, the system and method may provide for aligning both of the associated columns with each other, by aligning at least a portion of the corresponding columns to each other. For example, as shown in FIG. 9, the outer edges of each of the pairs of corresponding columns may be aligned. FIG. 10 shows alignment of the outer edges of such corresponding pairs of columns according to an alternative example embodiment of the present invention. In FIG. 10, a left one of the consecutive pair of columns, i.e., column 1002 of table 1000, is assigned a width so that it is fully aligned with corresponding column 1003 of table 1001, while the right one of the consecutive pair of columns, i.e., column 1004 of table 1000, is assigned a width such that its right edge is aligned with the right edge of corresponding column 1005 of table 1001 but its left edge is aligned with the left edge of the intermediary column 1006 of table 1001. In a variant of this embodiment, the right column of the column pair that does not include any intermediary columns may be fully aligned with its corresponding column and the left column of the column pair that does not include any intermediary columns may be aligned at its left edge with its corresponding column and at its right edge with the right edge of the intermediary of the table including the corresponding pair of columns. An exemplary implementation of this variant is described in detail above with respect to FIG. 6. In one variant of this embodiment, the system and method may provide that at least one of the column pairs should not be aligned in certain instances. For example, the rule set 136 may provide that columns are to be assigned at least a minimum column width. The minimum may be absolute or may be relative to the space occupied by the data of the columns. The rule set 136 may further provide that a column width should not exceed a certain maximum width. The maximum may be absolute or may be relative to the space occupied by the data of the columns. For example, the rule set 136 may set a maximum for an amount of white space that may appear after a longest string of a column. According to this embodiment, the rule set 136 may provide for an alignment different than that shown in FIG. 9 if the alignment of FIG. 9 requires an assignment to either of columns 902 and 904 of a column width greater than the maximum allowed column width. In one variant, the maximums and minimums may be modified according to manual manipulation of the column sizes. For example, if a user manually stretches a column's width so that it exceeds its maximum width, the rule set 136 may provide for setting a new maximum width as some predetermined amount past the point to which the user manually extended the column's width. Accordingly, if the width required for the column to have a side aligned with a corresponding column of another table is within the predetermined amount past the manually extended edge of the column, the rule set 136 may provide for automatically further extending the column so that one of its edges is aligned with an edge of the corresponding column. Similarly, if the user manually minimizes a column width past its minimum, a new minimum may be set in order to align the corresponding columns. Even according to this embodiment, however, the rule set 136 may set overall absolute maximums and minimums that may trump the predetermined additional extending or narrowing of the columns. In one variant of this embodiment, while the rule set 136 may provide for generally setting a column's width so that all of the data of most or all of the column's cells are displayed without scrolling within the cells, the rule set 136 may provide otherwise to minimize the widths of the non-consecutive columns towards their respective minimums so that the consecutive columns, e.g., extended towards their respective maximums, can be aligned at least at their outer edges with the non-consecutive columns. It may occur that, even with the minimizing of the column widths of the non-consecutive columns to their respective minimums and the maximizing of the column widths of the consecutive columns to their respective maximums, none of the column edges of the corresponding columns of the different tables become aligned. Nevertheless, the rule set 136 may provide for the minimizing of the column widths of the non-consecutive columns to their respective minimums and the maximizing of the column widths of the consecutive columns to their respective maximums so that the corresponding columns may be aligned at least to the extent that portions of the corresponding columns overlap, e.g., as much as possible, as shown in FIG. 11. In FIG. 11, of corresponding columns A 1102 and 1103 of tables 1100 and 110.1, only portions 1102.1 and 1103.1 overlap and none of the column edges of columns 1102 and 1103 are aligned. Similarly, of corresponding columns B 1104 and 1105 of tables 1100 and 1101, only portions 1104.1 and 1105.1 overlap and none of the column edges of columns 1104 and 1105 are aligned. In an example embodiment of the present invention, if: (a) a first pair of columns of a first table correspond for alignment to a second pair of columns of a second table; (b) the corresponding columns of the first pair and the second pair are in the same sequence; and (c) the first and second pairs of columns include a different number (of at least one each) of intervening columns that are not aligned between the first and second tables, the system and method of the present invention may provide for fully aligning each of the columns of one pair with the respective corresponding columns of the other pair, i.e., the outer edges of each of the columns of one pair align with the outer edges of each of the respective corresponding columns of the other pair. FIG. 12 shows an example of pairs of corresponding columns of different tables having different numbers of intervening columns. In FIG. 12, column A 1202 of table 1200 corresponds to column A 1203 of table 1201, and column B 1204 of table 1200 corresponds to column B 1205 of table 1201. However, between columns 1202 and 1204 of table 1200 are two intervening columns 1206 and 1208 that do not correspond for alignment purposes with any columns of table 1201, and between columns 1203 and 1205 of table 1201 is only a single intervening column 1207 that does not correspond for alignment purposes with any column of table 1200. Thus, the number of intervening columns between columns 1202 and 1204 and between 1203 and 1205, respectively, differs. In this instance, columns A 1202-1203 and columns B 1204-1205, respectively, are shown to be fully aligned. For the full alignment, the widths of columns 1206 and 1208 may be minimized towards their respective minimums. In one example embodiment of the present invention, the full alignment may be provided only so long as rules regarding the minimum and maximum column widths are adhered to with respect to the intervening columns. Furthermore, whether the full alignment is provided may be impacted by the extent to which the intervening columns correspond for alignment with columns of other tables besides for the first and second table. Tables including corresponding columns may be structured such that, should all of the corresponding columns of the tables be fully aligned, a first column, e.g., following a column identifying the individual records with which the respective rows are associated, of one of the tables would begin after much white space measured from a left edge of the table. For example, the full alignment may require that the beginning of the first column appear in the display screen only after scrolling the display screen even where the left edge of the table is displayed near the left edge of the display area of GUI 112. This may occur, for example, where a first table includes a number of columns that do not correspond for alignment to any columns of a second table, the non-corresponding columns precede columns that do correspond for alignment to columns of the second table, and the first column of the second table corresponds for alignment to a column of the first table. For the alignment of the first column of the second table with the corresponding column of the first table, it may be required to position the first column of the second table so that it begins after white space corresponding to the space of the first table in which the number of non-corresponding columns are displayed. In one example embodiment of the present invention, the rule set 136 may specify a maximum amount of white space that may precede a beginning of a first (in sequence) displayed column of a first table, e.g., a column displayed first after a column identifying the table records. For determining the amount of required white space, the first white space beginning from a left edge of the first table or beginning from a right edge of a column of the first table in which record identifiers are displayed may be considered the beginning of the white space. Accordingly, should alignment of a first column of a first table with a column of a second table require displaying a first edge, e.g., a left edge, of the first column after more than the specified maximum of white space, the rule set 136 may provide for displaying the first column without aligning it with the column of the second table. However, even if the left edge of the first column is not aligned with a left edge of the column of the second table, the rule set 136 may provide for extending the width of the first column so that at least the right edge of the first column aligns with a right edge of the column of the second table or so that at least a portion of the first column aligns with a portion of the column of the second table. However, if the rule set 136 specifies a maximum width for the first column and the first column does not at all align with the column of the second table even if extended to the maximum allowed width, the rule set 136 may provide for displaying the first column without extending it for alignment purposes. In one variant, however, the first column may be extended towards or to the maximum allowed width if such extension allows another column of the first table to be aligned, e.g., fully, with a corresponding column of the second or another table. For example, in FIG. 13, column A 1303 of table 1301 may correspond for alignment to column A 1302 of table 1300. However, alignment of columns A 1302-1303, even to the extent that only portions of the corresponding columns overlap without alignment of any edges, may require displaying a left edge of column A 1303 after a significant amount of white space that exceeds a specified maximum since column A 1303 is a first column of table 1301 and column A 1302 is displayed after columns C 1306 and D 1308 of table 1300. Accordingly, the rule set 136 may provide that the columns 1303 and 1302 should not be aligned. Portion 1303.1 of column 1303 represents a width that would be assigned to column 1303 if only contents of column 1303 are considered. Nevertheless, the rule set 136 may provide that column 1303 should be extended, towards or to its maximum allowed width to include portion 1303.2 so that columns B 1304-1305 may be fully aligned. In an example embodiment of the present invention, a display area required for display of all of the columns of all of the tables may be larger than that which can be simultaneously displayed in the display area of the GUI 112. For example, the required display area may depend on font size, set column widths, and a number of columns to be provided in a table. Accordingly, after all of the column positions are determined, a required scrolling extension to the display area may be determined. In one example embodiment of the present invention, where a scrolling area is provided, the system and method may set all columns of a table, but for a first column identifying records, to scroll. The first column identifying records may remain stationary so that it is always displayed even when scrolling to view columns to the right. For example, the columns scrolling left when scrolling to view columns to the right may appear to be scrolling into a position underneath the first column. In an example embodiment of the present invention, subsequent to an arrangement of two (or more) columns of different tables according to a stored setting of an association between the two columns, where the columns are fully aligned, the system and method may provide that, if a user manually shifts an edge of a column of a first one of the tables, then the corresponding edge of a corresponding column of a second one of the tables is automatically shifted in a corresponding manner. In one variant, the corresponding shift of the column of the second table may be performed conditional upon maintaining other realized alignments between the columns of the second and the first table and/or the columns of the second and other tables, where the other realized alignments are in accordance with stored associations between the aligned columns. Whether the other alignments can be maintained may depend, for example, on the rules regarding maximum and minimum widths, maximum white space, and/or other rules of the rule set 136. In one variant, as long as at least partial alignment between the other columns can be maintained, the system and method may automatically shift the edge of the column of the second table in accordance with the manual shift of the edge of the column of the first table. In one variant, the system and method may shift one or more edges of the column of the second table in accordance with the manual shift of the column of the first table only to an extent required to maintain at least partial alignment between the two columns. In particular, this variant may be implemented in a case where the shift of the column of the second table to maintain full alignment between the two columns causes a loss of full or at least partial alignment between other columns. In one example embodiment of the present invention, the system and method may perform the method described with respect to FIG. 7 each time an instruction to modify the display of the tables is received. For example, the method may be performed each time an indicator 202 is selected indicating to either expand or collapse a record, or each time input for manual manipulation of column edges is received. In an alternative example embodiment of the present invention, after a first display of tables according to the method described with respect to FIG. 7, the system and method may adjust the previous table display according to the newly received instructions. Those skilled in the art can appreciate from the foregoing description that the present invention can be implemented in a variety of forms. Therefore, while the embodiments of this invention have been described in connection with particular examples thereof, the true scope of the embodiments of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.	G	60G06	161G06F	30	48
11833208	US20080034364A1-20080207	Sharing Live Appliances	ACCEPTED	20080123	20080207	[]	G06F9455	["G06F9455"]	8266576	20070802	20120911	717	100000	59811.0	RAMPURIA	SATISH	[{"inventor_name_last": "Lam", "inventor_name_first": "Monica", "inventor_city": "Menlo Park", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Berkheimer", "inventor_name_first": "Andrew", "inventor_city": "Boston", "inventor_state": "MA", "inventor_country": "US"}, {"inventor_name_last": "Sapuntzakis", "inventor_name_first": "Constantine", "inventor_city": "Mountain View", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Whaley", "inventor_name_first": "John", "inventor_city": "San Mateo", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chandra", "inventor_name_first": "Ramesh", "inventor_city": "Belmont", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "Michael", "inventor_city": "Palo Alto", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chun", "inventor_name_first": "Won-Suk", "inventor_city": "Belmont", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Yue", "inventor_name_first": "Kelvin", "inventor_city": "Sunnyvale", "inventor_state": "CA", "inventor_country": "US"}]	Methods, systems, and apparatus, including computer program apparatus, implementing techniques for publishing, subscribing to, or playing live appliances. A live appliance includes a current virtual machine image. In publishing, a proxy file of a live appliance file type is provided to the publisher. The type is mapped to a live appliance player; so that when a proxy file is opened, the current virtual machine image is run. The player automatically binds a writeable file system external to the virtual machine image to the image to provide file storage that is accessible from within the virtual machine image and from a host operating system. The player also creates a subscription to the live appliance on the host computer if one does not exist when the proxy file is run. With the subscription, the player runs the then-current virtual machine image whenever the live appliance is run.	1. A computer-implemented method comprising: receiving in a computer a request to run a live appliance, the live appliance providing a computing environment that a user can run on the computer, the live appliance being defined by a data source that includes a version description for a current version of a virtual machine image; determining whether the computer has subscribed to the live appliance, and if not, subscribing to the live appliance on the computer, reading the data source for the live appliance, and using the current version description to initiate downloading of the current version of the virtual machine image to the computer; when the computer has subscribed to the live appliance, detecting whether a change has occurred in the data source that changes the version description designated as the current version description, and if a change has occurred, reading updated data from the data source, the updated data designating a second version description as the current version description, the second version description describing a different second version of the virtual machine image as the current version of the virtual machine image; obtaining the current version of the virtual machine image as described by the second version description; and running the current version of the virtual machine image. 2. The method of claim 1, wherein: the data source includes a respective version description for each of multiple versions of the virtual machine image, the data source further including data designating one of the versions of the virtual machine image as the current version. 3. The method of claim 1, wherein: receiving the request to run the live appliance comprises receiving in the computer a request to open a proxy for the live appliance, the proxy including a source identifier that can be resolved to a location of the data source. 4. The method of claim 3, wherein: the request to open the proxy is a user input received through a graphical user interface. 5. The method of claim 3, further comprising: running a helper program in response to receiving in the computer the request to run the live appliance, the helper program either starting a player to open the proxy or notifying a running player of the request to open the proxy. 6. The method of claim 3, further comprising: running a player to open the proxy, the player being an application program on the computer, the player performing the actions of creating the subscription and obtaining the current version of the virtual machine image as described by the second version description. 7. The method of claim 6, wherein the player further performs the actions of detecting whether a change has occurred in the data source. 8. The method of claim 6, wherein a background process performs the actions of detecting whether a change has occurred in the data source. 9. The method of claim 6, wherein: the player performs polling of the data source to detect whether a change has occurred in the data source. 10. The method of claim 6, wherein: the player receives an indication pushed over the Internet that a change has occurred in the data source. 11. The method of claim 6, wherein: the player includes a virtual machine monitor to run the current version of the virtual machine image. 12. The method of claim 6, wherein: the player invokes a virtual machine monitor to run the current version of the virtual machine image. 13. The method of claim 6, wherein: the player comprises a virtual appliance transceiver. 14. The method of claim 6, wherein: the player provides a user file system to provide writeable data storage for the running virtual machine image, the user file system storing file data and metadata on a local data store coupled to the computer. 15. The method of claim 14, wherein: the user file system is a networked file system protocol implemented in the player that maps file system operations to the local data store. 16. The method of claim 15, wherein: data files stored on the local data store are stored in a FAT (File Allocation Table) or an NTFS (New Technology File System) file system. 17. The method of claim 15, wherein the networked file system protocol is an NFS (Network File System), SMB (Server Message Block), CIFS (Common Internet File System) or AFS (Andrew File System) protocol. 18. The method of claim 14, wherein: the local data store is an internal disk drive in the computer, an external disk drive, an attachable disk drive, or an attachable solid state memory device, or an audio or video media player device. 19. The method of claim 14, wherein the file data and metadata in local store is visible to programs running under a host operating system of the computer. 20. The method of claim 6, wherein: the player uses persistent storage on the computer for user profile and registry information to allow user configuration of the current virtual machine image to be persistent across updates to the current virtual machine image and across rebooting of the computer. 21. The method of claim 20, wherein: the persistent storage is provided by an attachable personal storage device. 22. The method of claim 3, further comprising: obtaining the proxy as an attachment to an e-mail message, as an attachment to an instant message, through a link on a web page, or as a pre-installed file on a read-only or a writable memory device. 23. The method of claim 3, wherein: the data source is an XML (Extensible Markup Language) file; the proxy is an XML file that includes a unique identifier identifying the live appliance and a source identifier URL (Uniform Resource Locator) for the data source; each version description is an XML file that identifies a respective virtual machine configuration by a link to the virtual machine configuration; and each virtual machine configuration is an XML file that includes respective virtual machine configuration data, disk configuration and location information for one or more virtual disks, the one or more virtual disks including a respective virtual machine image. 24. The method of claim 23, wherein: the virtual machine configuration data for a version includes a title for the version, a description of the version, and a change history for the version. 25. The method of claim 1, wherein: obtaining the current version of the virtual machine image includes reading parts of the virtual machine image on demand. 26. The method of claim 1, wherein: the first version of the virtual machine image is in a first format and the second version of the virtual machine image is in a different second format. 27. The method of claim 26, wherein: the first format is a VMware format and the second format is a Virtual PC format. 28. The method of claim 1, further comprising: obtaining the proxy from a subscription service; obtaining the data source from the subscription service; and obtaining the virtual machine configuration for the current version and the one or more virtual disks from a distribution service. 29. The method of claim 28, wherein: each virtual disk is organized as a series of one or more copy on write data storage resources. 30. A method comprising: uploading a virtual machine image to a distribution service; and posting a live appliance to a subscription service by providing data source information to the subscription service, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration. 31. The method of claim 30, further comprising: receiving from the subscription service a proxy file generated by the subscription service, the proxy file including a source identifier that can be resolved to a location of the data source, the proxy file having a distinguished file type identifying the proxy file as a live appliance proxy. 32. The method of claim 30, further comprising: receiving from the subscription service a proxy file that includes a source identifier that can be resolved to a location of the data source, the proxy file having a distinguished file type identifying the proxy file as a live appliance proxy. 33. The method of claim 30, wherein: the data source including multiple versions of the virtual machine image, each version having a virtual machine version configuration, the data source identifying a current version, the current version being one of the one or more versions of the virtual machine image. 34. The method of claim 30, further comprising: creating the virtual machine image from a previously-existing virtual machine image in a previously-existing live appliance. 35. The method of claim 30, further comprising: creating the virtual machine image as a new virtual machine image, including installing on the virtual machine image an operating system and software to run on the operating system. 36. The method of claim 30, wherein: providing data source information comprises posting a data source to the subscription service. 37. The method of claim 30, wherein: providing data source information comprises filling in a form provided by the subscription service. 38. The method of claim 30, further comprising: uploading a new virtual machine image to extend the live appliance. 39. The method of claim 30, wherein: the distribution service is a peer-to-peer service on the Internet through which subscribers can provide virtual machine images to other subscribers. 40. The method of claim 30, wherein: the distribution service is implemented on one or more distribution servers serving virtual machine images to remote clients over the Internet. 41. The method of claim 30, wherein: the subscription service is implemented on a subscription server. 42. A system comprising: one or more computers coupled in data communication with each other and to a data communication network to interact with users; and a post interface, an upload interface, and a system database implemented on the one or more computers; the post interface being operable to receive post input over the network from a publisher user posting a live appliance to the system, the post input including data source information, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration, in response to which the system registers the live appliance, creates a corresponding data source including the data source information, and stores the corresponding data source in the system database; the upload interface being operable to receive upload input over the network from the publisher user, the upload input comprising the version of the virtual machine image, and to store the virtual machine image in the system database; the system being operable to provide a proxy for the live appliance to the publisher user in response to the publisher posting the live appliance. 43. The system of claim 42, further comprising: an update interface implemented on the one or more computers, the update interface being operable to receive update input over the network from the publisher user updating the corresponding data sources for the live appliance. 44. The system of claim 42, wherein: the system implements a subscription service and a distribution service, the subscription service being implemented on one or more subscription subsystem and the distribution service being implemented on one or more distribution computers; the post interface and a subscription database being implemented on the one or more subscription computers, the subscription database being a part of the system database storing the data source; and the upload interface and an upload database being implemented on the one or more distribution computers, the upload database being a part of the system database storing the virtual machine image. 45. The system of claim 44, further comprising: an update interface implemented on the one or more subscription computers, the update interface being operable to receive update input over the network from the publisher user updating the corresponding data sources for the live appliance. 46. The system of claim 45, further comprising: distribution software operable to distribute virtual machine image to a requesting user. 47. The system of claim 46, wherein the distribution software comprises a centralized web server. 48. The system of claim 46, wherein the distribution software comprises distributed peer-to-peer file sharing software. 49. The system of claim 42, further comprising: distribution software operable to distribute virtual machine image to a requesting user. 50. The system of claim 49, wherein the distribution software comprises a centralized web server. 51. The system of claim 49, wherein the distribution software comprises distributed peer-to-peer file sharing software. 52. A computer-implemented method comprising: in response to a user action opening a proxy file on a computer, automatically invoking a player application on the computer, the player application performing player actions comprising: using the proxy file to locate the current version of the virtual machine image; and causing the current version of the virtual machine image to be run by a virtual machine monitor. 53. The method of claim 52, wherein using the proxy file to locate the current version of the virtual machine image comprises: obtaining feed data from a data source identified in the proxy file; using the feed data to identify a current version of a virtual machine image; and using the feed data to locate the current version of the virtual machine image. 54. The method of claim 52, wherein the proxy file comprises a hyperlink to a virtual machine and using the proxy file to locate the current version of the virtual machine image comprises using the hyperlink to obtain the virtual machine image. 55. The method of claim 52, further comprising: binding data files for the virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer. 56. The method of claim 52, further comprising: installing a guest operating system dependent helper in the virtual machine image to implement a user file system protocol to read and write the data files on a local data store; and the player performs player actions further comprising: configuring a network file system server on the computer to provide the guest operating system with the user file system for reading and writing the data files. 57. The method of claim 52, wherein the data source includes an RSS (Rich Site Summary) feed and the feed data includes data obtained from the RSS feed. 58. The method of claim 52, wherein: the data source is identified in the proxy by a link to the data source; and the player uses the link to access the data source. 59. The method of claim 58, wherein the link is a Uniform Resource Identifier (URI) 60. The method of claim 58, wherein the virtual machine image includes an operating system and application software installed on the virtual machine. 61. The method of claim 58, wherein the virtual machine monitor is a VMWare Player, a Microsoft Virtual Server, a Xen virtual machine monitor, a Parallels virtual machine monitor, or a Virtuozzo virtual machine monitor. 62. The method of claim 58, wherein the virtual machine monitor provides machine-level virtualization or operating system level virtualization. 63. A memory for storing data for access by an application program being executed on a data processing system, comprising: a data structure stored in the memory, the data structure comprising: a proxy for a live appliance; a data source; and one or more virtual machine version configurations, each version configuration including one or more links to a corresponding virtual machine image; wherein: the proxy includes a source identifier that can be resolved to a location of the data source; the data source includes data designating one of the versions of the virtual machine image as the current version, the current version being described by a current version description; and each version configuration contains configuration data describing the corresponding virtual machine image. 64. The memory of claim 63, wherein: the proxy further includes a live appliance identifier. 65. The memory of claim 63, wherein: the data source includes an identifier unique to the data source. 66. The memory of claim 63, wherein: each version description includes a link to a respective version configuration. 67. The memory of claim 63, wherein: each version description is included as part of the data source. 68. The memory of claim 63, wherein: the proxy is a file; the data source is an XML file; and each version configuration is an XML file. 69. The memory of claim 63, wherein: the memory is distributed across multiple servers, the data source being stored on a subscription server, each virtual machine image being stored on one of one or more distribution servers. 70. The memory of claim 69, wherein: each version configuration is stored on one of one or more distribution servers. 71. The memory of claim 63, wherein: the memory is all within a single server. 72. The memory of claim 63, wherein: the source identifier is a Uniform Resource Identifier (URI); and the data source includes a maintainer name and e-mail address. 73. A computer-implemented method comprising: receiving in a user interface of a computer an uninterrupted user action opening a proxy document and, in response to the user action and without further user intervention, performing actions comprising: identifying, based on information in the proxy document, a live appliance; determining whether the computer has subscribed to the live appliance and, if not, subscribing to the live appliance; and running a current version of a virtual machine image from the live appliance, the live appliance including one or more versions of the virtual machine image. 74. The method of claim 73, wherein subscribing to the live appliance comprises: registration of a live appliance download process on the computer, the process being operable to download virtual machine images from the live appliance, the live appliance download process being installed to persist across, and to be run after, a reboot of the computer. 75. The method of claim 73, wherein: the live appliance includes a temporal sequence of virtual machine images that are updated over time 76. The method of claim 73, wherein: the user action opening the proxy document is a single-click action on an icon representing the proxy document. 77. The method of claim 73, wherein: the user action opening the proxy document is a single-click action on a hyperlink that is linked to the proxy document. 78. The method of claim 73, wherein: the user action opening the proxy document is a double-click action on an icon representing the proxy document. 79. The method of claim 73, wherein: the user interface is a user interface of an e-mail client or an instant messaging client. 80. A computer program product, tangibly stored on a machine-readable medium, the product comprising instructions operable when executed by a computer to perform operations comprising: receiving in a user interface of the computer an uninterrupted user action opening a proxy document and, in response to the user action and without further user intervention, performing actions comprising: identifying, based on information in the proxy document, a live appliance; determining whether the computer has subscribed to the live appliance and, if not, subscribing to the live appliance; and running a current version of a virtual machine image from the live appliance, the live appliance including one or more versions of the virtual machine image. 81. The method of claim 80, wherein subscribing to the live appliance comprises: registration of a live appliance download process on the computer, the process being operable to download virtual machine images from the live appliance, the live appliance download process being installed to persist across, and to be run after, a reboot of the computer. 82. The method of claim 80, wherein: the live appliance includes a temporal sequence of virtual machine images that are updated over time 83. The method of claim 80, wherein: the user action opening the proxy document is a single-click action or a double-click action on an icon representing the proxy document. 84. The method of claim 80, wherein: the user action opening the proxy document is a single-click action on a hyperlink that is linked to the proxy document. 85. The method of claim 80, wherein: the user interface is a user interface of an e-mail client or an instant messaging client. 86. A computer-implemented method, comprising: registering a live appliance file type on a computer to associate the file type with a player application on the computer, wherein: running the player application in response to a user action or a programmatic action opening a first document of the file type on the computer, the player application performing actions comprising: acting on the first document by reading feed data from a first live appliance data feed source, the data feed source being the first document or being identified by a source locator in the first document; reading a first virtual machine image, the virtual machine image being in the feed source or being identified by an image locator in the feed source; and causing the first virtual machine to be run by a virtual machine monitor. 87. The method of claim 86, wherein the player application further performs actions comprising: selecting the first virtual machine image from among multiple virtual machine images found in or identified by the feed source. 88. The method of claim 86, wherein: the player includes the virtual machine monitor. 89. A computer program product, tangibly stored on a machine-readable medium, the product comprising instructions operable when executed by a computer to perform operations comprising: registering a live appliance file type on the computer to associate the file type with a player application on the computer, wherein: running the player application in response to a user action or a programmatic action opening a first document of the file type on the computer, the player application performing actions comprising: acting on the first document by reading feed data from a first live appliance data feed source, the data feed source being the first document or being identified by a source locator in the first document; reading a first virtual machine image, the virtual machine image being in the feed source or being identified by an image locator in the feed source; and causing the first virtual machine to be run by a virtual machine monitor. 90. The method of claim 89, wherein the player application further performs actions comprising: selecting the first virtual machine image from among multiple virtual machine images found in or identified by the feed source. 91. The method of claim 89, wherein: the player includes the virtual machine monitor. 92. A computer-implemented method comprising: receiving in a user interface of a computer an uninterrupted user action opening a proxy document having a live appliance file type and, in response to the user action and without further user intervention, automatically invoking a player application on the computer, the player application performing actions comprising: identifying a remote source identifying a current version of a virtual machine image based on information in the proxy document; determining whether a copy of the current version of the virtual machine image has been downloaded to the computer and if not, beginning to download the virtual machine image to the computer; and running the virtual machine image on a virtual machine monitor on the computer. 93. The method of claim 92, wherein the proxy document identifies a live appliance and the actions further comprise: determining whether a subscription to the live appliance exists on the computer and if not, initiating a persistent process on the computer to maintain a subscription to the live appliance on the computer. 94. The method of claim 92, wherein the uninterrupted user action is a single-click action or a double-click action. 95. A computer program product, tangibly stored on a machine-readable medium, the product comprising instructions operable when executed by a computer to perform operations comprising: receiving in a user interface of the computer an uninterrupted user action opening a proxy document having a live appliance file type and, in response to the user action and without further user intervention, automatically invoking a player application on the computer, the player application performing actions comprising: identifying a remote source identifying a current version of a virtual machine image based on information in the proxy document; determining whether a copy of the current version of the virtual machine image has been downloaded to the computer and if not, beginning to download the virtual machine image to the computer; and running the virtual machine image on a virtual machine monitor on the computer. 96. The method of claim 95, wherein the proxy document identifies a live appliance and the actions further comprise: determining whether a subscription to the live appliance exists on the computer and if not, initiating a persistent process on the computer to maintain a subscription to the live appliance on the computer. 97. The method of claim 95, wherein the uninterrupted user action is a single-click action or a double-click action. 98. A system comprising: a computer comprising memory, the memory storing instructions operable when executed by the computer to perform operations comprising: receiving in a user interface of a computer an uninterrupted user action opening a proxy document and, in response to the user action and without further user intervention, performing actions comprising: identifying, based on information in the proxy document, a live appliance; determining whether the computer has subscribed to the live appliance and, if not, subscribing to the live appliance; and running a current version of a virtual machine image from the live appliance, the live appliance including one or more versions of the virtual machine image. 99. A system comprising: a computer with a player application installed on the computer, a live appliance file type being registered on the computer to associate the file type with the player application on the computer; a computer comprising memory, the memory storing instructions operable when executed by the computer to perform operations comprising: running the player application in response to a user action or a programmatic action opening a first document of the file type on the computer, the player application performing actions comprising: acting on the first document by reading feed data from a first live appliance data feed source, the data feed source being the first document or being identified by a source locator in the first document; reading a first virtual machine image, the virtual machine image being in the feed source or being identified by an image locator in the feed source; and causing the first virtual machine to be run by a virtual machine monitor. 100. A system comprising: a computer with a player application installed on the computer; the computer comprising memory, the memory storing instructions operable when executed by the computer to perform operations comprising: receiving in a user interface of a computer an uninterrupted user action opening a proxy document having a live appliance file type and, in response to the user action and without further user intervention, automatically invoking the player application on the computer, the player application performing actions comprising: identifying a remote source identifying a current version of a virtual machine image based on information in the proxy document; determining whether a copy of the current version of the virtual machine image has been downloaded to the computer and if not, beginning to download the virtual machine image to the computer; and running the virtual machine image on a virtual machine monitor on the computer. 101. A computer program product, tangibly embodied in a computer-readable medium, comprising instructions operable to cause a computer to perform operations comprising: receiving in a computer a request to run a live appliance, the live appliance providing a computing environment that a user can run on the computer, the live appliance being defined by a data source that includes a version description for a current version of a virtual machine image; determining whether the computer has subscribed to the live appliance, and if not, subscribing to the live appliance on the computer, reading the data source for the live appliance, and using the current version description to initiate downloading of the current version of the virtual machine image to the computer; when the computer has subscribed to the live appliance, detecting whether a change has occurred in the data source that changes the version description designated as the current version description, and if a change has occurred, reading updated data from the data source, the updated data designating a second version description as the current version description, the second version description describing a different second version of the virtual machine image as the current version of the virtual machine image; obtaining the current version of the virtual machine image as described by the second version description; and running the current version of the virtual machine image. 102. The product of claim 101, wherein: the data source includes a respective version description for each of multiple versions of the virtual machine image, the data source further including data designating one of the versions of the virtual machine image as the current version. 103. The product of claim 101, wherein: receiving the request to run the live appliance comprises receiving in the computer a request to open a proxy for the live appliance, the proxy including a source identifier that can be resolved to a location of the data source. 104. The product of claim 103, wherein: the request to open the proxy is a user input received through a graphical user interface. 105. The product of claim 103, the instructions being operable to cause a computer to perform further operations comprising: running a helper program in response to receiving in the computer the request to run the live appliance, the helper program either starting a player to open the proxy or notifying a running player of the request to open the proxy. 106. The product of claim 103, the instructions being operable to cause a computer to perform further operations comprising: running a player to open the proxy, the player being an application program on the computer, the player performing the actions of creating the subscription and obtaining the current version of the virtual machine image as described by the second version description. 107. The product of claim 106, wherein the player further performs the actions of detecting whether a change has occurred in the data source. 108. The product of claim 106, wherein a background process performs the actions of detecting whether a change has occurred in the data source. 109. The product of claim 106, wherein the player performs polling of the data source to detect whether a change has occurred in the data source. 110. The product of claim 106, wherein the player receives an indication pushed over the Internet that a change has occurred in the data source. 111. The product of claim 106, wherein the player includes a virtual machine monitor to run the current version of the virtual machine image. 112. The product of claim 106, wherein the player invokes a virtual machine monitor to run the current version of the virtual machine image. 113. The product of claim 106, wherein the player comprises a virtual appliance transceiver. 114. The product of claim 106, wherein the player provides a user file system to provide writeable data storage for the running virtual machine image, the user file system storing file data and metadata on a local data store coupled to the computer. 115. The product of claim 114, wherein the user file system is a networked file system protocol implemented in the player that maps file system operations to the local data store. 116. The product of claim 115, wherein data files stored on the local data store are stored in a FAT (File Allocation Table) or an NTFS (New Technology File System) file system. 117. The product of claim 115, wherein the networked file system protocol is an NFS (Network File System), SMB (Server Message Block), CIFS (Common Internet File System) or AFS (Andrew File System) protocol. 118. The product of claim 114, wherein the local data store is an internal disk drive in the computer, an external disk drive, an attachable disk drive, or an attachable solid state memory device, or an audio or video media player device. 119. The product of claim 114, wherein the file data and metadata in local store is visible to programs running under a host operating system of the computer. 120. The product of claim 106, wherein the player uses persistent storage on the computer for user profile and registry information to allow user configuration of the current virtual machine image to be persistent across updates to the current virtual machine image and across rebooting of the computer. 121. The product of claim 120, wherein the persistent storage is provided by an attachable personal storage device. 122. The product of claim 103, the instructions being operable to cause a computer to perform further operations comprising: obtaining the proxy as an attachment to an e-mail message, as an attachment to an instant message, through a link on a web page, or as a pre-installed file on a read-only or a writable memory device. 123. The product of claim 103, wherein: the data source is an XML (Extensible Markup Language) file; the proxy is an XML file that includes a unique identifier identifying the live appliance and a source identifier URL (Uniform Resource Locator) for the data source; each version description is an XML file that identifies a respective virtual machine configuration by a link to the virtual machine configuration; and each virtual machine configuration is an XML file that includes respective virtual machine configuration data, disk configuration and location information for one or more virtual disks, the one or more virtual disks including a respective virtual machine image. 124. The product of claim 123, wherein the virtual machine configuration data for a version includes a title for the version, a description of the version, and a change history for the version. 125. The product of claim 101, wherein obtaining the current version of the virtual machine image includes reading parts of the virtual machine image on demand. 126. The product of claim 101, wherein the first version of the virtual machine image is in a first format and the second version of the virtual machine image is in a different second format. 127. The product of claim 126, wherein the first format is a VMware format and the second format is a Virtual PC format. 128. The product of claim 101, the instructions being operable to cause a computer to perform further operations comprising: obtaining the proxy from a subscription service; obtaining the data source from the subscription service; and obtaining the virtual machine configuration for the current version and the one or more virtual disks from a distribution service. 129. The product of claim 128, wherein each virtual disk is organized as a series of one or more copy on write data storage resources. 130. A method comprising: binding data files for a virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image. 131. The method of claim 130, further comprising: installing a guest operating system dependent helper in the virtual machine image to implement a user file system protocol to read and write the data files on a local data store; and the player performs player actions further comprising: configuring a network file system server on the computer to provide the guest operating system with the user file system for reading and writing the data files. 132. The method of claim 130, wherein: the user file system is a networked file system protocol implemented in the player that maps file system operations to the local data store. 133. The method of claim 132, wherein: the data files stored on the local data store are stored in a FAT (File Allocation Table) or an NTFS (New Technology File System) file system. 134. The method of claim 132, wherein the networked file system protocol is an NFS (Network File System), SMB (Server Message Block), CIFS (Common Internet File System) or AFS (Andrew File System) protocol. 135. The method of claim 130, wherein: the local data store is an internal disk drive in the computer, an external disk drive, an attachable disk drive, or an attachable solid state memory device, or an audio or video media player device. 136. The method of claim 130, wherein: the file system comprises an NFS (Network File System) volume. 137. The method of claim 130, wherein the player performs player actions further comprising: binding an attachable data storage device to the virtual machine image. 138. The method of claim 137, wherein: when a file system write operation is directed from the virtual machine of the virtual machine image to the attachable data storage device, network extension code is invoked, the network extension code being operable to: cause data to be written to the attachable data storage device based upon the file system write function call, generate a transmit determination indicative of whether to transmit the data to a network repository, and transmit the data to the network repository based upon the transmit determination. 139. The method of claim 130, wherein: the player runs a first version of the virtual machine image and is operable to discard changes to one or more virtual disks in the virtual machine image and return the one or more virtual disks to an original state found in the first version of the virtual machine image; the player makes a virtual volume of data storage visible to the running virtual machine image; the running virtual machine image mounts the virtual volume; and the running virtual machine uses the virtual volume to store user data files. 140. The method of claim 139, wherein: the virtual volume is available as a mountable volume on the computer. 141. The method of claim 139, further comprising: creating a fake user at startup of the computer having no general access rights to file storage on the computer other than storage mounted on the running virtual machine image by the player; and running the virtual machine monitor as a program run by the fake user to protect file storage on the computer. 142. A computer program product, tangibly embodied in a computer-readable medium, comprising: a dependent helper in a virtual machine image to implement a user file system protocol to read and write the data files on a local data store, the dependent helper being operable to perform actions comprising: binding data files for the virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image; and a player operable to perform actions comprising: configuring a host computer to provide a guest operating system with the user file system for reading and writing the data files. 143. The product of claim 142, wherein configuring the host computer comprising configuring a network file system server on the host computer to provide the guest operating system with the user file system for reading and writing the data files. 144. The product of claim 142, wherein configuring the host computer comprising configuring a virtual machine monitor running the virtual machine image on the host computer to provide the guest operating system with the user file system for reading and writing the data files.	<SOH> BACKGROUND <EOH>This specification relates to creating, publishing, subscribing to, and using virtual machines. A virtual machine is software construct that appears to be hardware on which a guest operating system and applications can be installed. In an emulator implementation, the virtual machine is an emulator, simulating all of the hardware used by the guest operating system and applications. In para-virtualization, the virtual machine allows the guest operating system and applications to run on the host hardware, but requires that the guest operating system be modified to use a special API (application programming interface) to run on the virtual machine monitor. In machine-level or full virtualization, the virtual machine allows a guest operating system that is implemented for the underlying host processor to be run without modification. In a para-virtualization or a machine-level virtualization implementation, a virtual machine monitor is used to bind the virtual machine to the underlying host hardware. In some architectures, the virtual machine monitor runs directly on the host hardware, in a hypervisor configuration. In others, it runs as an application on the host operating system. In some architectures, a lightweight hypervisor is run between the host operating system and the host hardware that provides a calling interface for both the host operating system and the virtual machine monitors. In some architectures, a hypervisor uses the services of a host operating system for device and other support.	<SOH> SUMMARY <EOH>This specification describes technologies for publishing, distributing, and subscribing to one or more live appliances. A live appliance includes a virtual machine image, and generally a sequence of virtual machine images. In general, one aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a computer a request to run a live appliance, the live appliance providing a computing environment that a user can run on the computer, the live appliance being defined by a data source that includes a version description for a current version of a virtual machine image; determining whether the computer has subscribed to the live appliance, and if not, subscribing to the live appliance on the computer, reading the data source for the live appliance, and using the current version description to initiate-downloading of the current version of the virtual machine image to the computer; when the computer has subscribed to the live appliance, detecting whether a change has occurred in the data source that changes the version description designated as the current version description, and if a change has occurred, reading updated data from the data source, the updated data designating a second version description as the current version description, the second version description describing a different second version of the virtual machine image as the current version of the virtual machine image; obtaining the current version of the virtual machine image as described by the second version description; and running the current version of the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of uploading a virtual machine image to a distribution service; and posting a live appliance to a subscription service by providing data source information to the subscription service, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in systems that include one or more computers coupled in data communication with each other and to a data communication network to interact with users; and a post interface, an upload interface, and a system database implemented on the one or more computers; the post interface being operable to receive post input over the network from a publisher user posting a live appliance to the system, the post input including data source information, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration, in response to which the system registers the live appliance, creates a corresponding data source including the data source information, and stores the corresponding data source in the system database; the upload interface being operable to receive upload input over the network from the publisher user, the upload input including the version of the virtual machine image, and to store the virtual machine image in the system database; where the system being operable to provide a proxy for the live appliance to the publisher user in response to the publisher posting the live appliance. Other embodiments of this aspect include corresponding methods, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of opening a proxy file in response to a user action on a computer, automatically invoking a player application on the computer, the player application performing player actions that include using the proxy file to locate the current version of the virtual machine image; and causing the current version of the virtual machine image to be run by a virtual machine monitor. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in memory devices for storing data for access by an application program being executed on a data processing system, whether the memory devices include a data structure stored in the memory, the data structure including a proxy for a live appliance; a data source; and one or more virtual machine version configurations, each version configuration including one or more links to a corresponding virtual machine image; wherein the proxy includes a source identifier that can be resolved to a location of the data source; the data source includes data designating one of the versions of the virtual machine image as the current version, the current version being described by a current version description; and each version configuration contains configuration data describing the corresponding virtual machine image. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a user interface of a computer an uninterrupted user action opening a proxy document and, in response to the user action and without further user intervention, performing actions that include identifying, based on information in the proxy document, a live appliance; determining whether the computer has subscribed to the live appliance and, if not, subscribing to the live appliance; and running a current version of a virtual machine image from the live appliance, the live appliance including one or more versions of the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of registering a live appliance file type on a computer to associate the file type with a player application on the computer, wherein running the player application in response to a user action or a programmatic action opening a first document of the file type on the computer, the player application performing actions that include acting on the first document by reading feed data from a first live appliance data feed source, the data feed source being the first document or being identified by a source locator in the first document; reading a first virtual machine image, the virtual machine image being in the feed source or being identified by an image locator in the feed source; and causing the first virtual machine to be run by a virtual machine monitor. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a user interface of a computer an uninterrupted user action opening a proxy document having a live appliance file type and, in response to the user action and without further user intervention, automatically invoking a player application on the computer, the player application performing actions that include identifying a remote source identifying a current version of a virtual machine image based on information in the proxy document; determining whether a copy of the current version of the virtual machine image has been downloaded to the computer and if not, beginning to download the virtual machine image to the computer; and running the virtual machine image on a virtual machine monitor on the computer. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of binding data files for a virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in computer program products tangibly embodied in a computer-readable medium that include a dependent helper in a virtual machine image to implement a user file system protocol to read and write the data files on a local data store, the dependent helper being operable to perform actions including binding data files for the virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image; and a player operable to perform actions including configuring a host computer to provide a guest operating system with the user file system for reading and writing the data files. Other embodiments of this aspect include corresponding systems, apparatus, and methods. The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.	CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Patent Application No. 60/835,258, titled “Sharing Live Appliances,” filed Aug. 2, 2006, which is incorporated herein by reference. BACKGROUND This specification relates to creating, publishing, subscribing to, and using virtual machines. A virtual machine is software construct that appears to be hardware on which a guest operating system and applications can be installed. In an emulator implementation, the virtual machine is an emulator, simulating all of the hardware used by the guest operating system and applications. In para-virtualization, the virtual machine allows the guest operating system and applications to run on the host hardware, but requires that the guest operating system be modified to use a special API (application programming interface) to run on the virtual machine monitor. In machine-level or full virtualization, the virtual machine allows a guest operating system that is implemented for the underlying host processor to be run without modification. In a para-virtualization or a machine-level virtualization implementation, a virtual machine monitor is used to bind the virtual machine to the underlying host hardware. In some architectures, the virtual machine monitor runs directly on the host hardware, in a hypervisor configuration. In others, it runs as an application on the host operating system. In some architectures, a lightweight hypervisor is run between the host operating system and the host hardware that provides a calling interface for both the host operating system and the virtual machine monitors. In some architectures, a hypervisor uses the services of a host operating system for device and other support. SUMMARY This specification describes technologies for publishing, distributing, and subscribing to one or more live appliances. A live appliance includes a virtual machine image, and generally a sequence of virtual machine images. In general, one aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a computer a request to run a live appliance, the live appliance providing a computing environment that a user can run on the computer, the live appliance being defined by a data source that includes a version description for a current version of a virtual machine image; determining whether the computer has subscribed to the live appliance, and if not, subscribing to the live appliance on the computer, reading the data source for the live appliance, and using the current version description to initiate-downloading of the current version of the virtual machine image to the computer; when the computer has subscribed to the live appliance, detecting whether a change has occurred in the data source that changes the version description designated as the current version description, and if a change has occurred, reading updated data from the data source, the updated data designating a second version description as the current version description, the second version description describing a different second version of the virtual machine image as the current version of the virtual machine image; obtaining the current version of the virtual machine image as described by the second version description; and running the current version of the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of uploading a virtual machine image to a distribution service; and posting a live appliance to a subscription service by providing data source information to the subscription service, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in systems that include one or more computers coupled in data communication with each other and to a data communication network to interact with users; and a post interface, an upload interface, and a system database implemented on the one or more computers; the post interface being operable to receive post input over the network from a publisher user posting a live appliance to the system, the post input including data source information, the data source information including version information describing a version of a virtual machine image, the version having a virtual machine version configuration, in response to which the system registers the live appliance, creates a corresponding data source including the data source information, and stores the corresponding data source in the system database; the upload interface being operable to receive upload input over the network from the publisher user, the upload input including the version of the virtual machine image, and to store the virtual machine image in the system database; where the system being operable to provide a proxy for the live appliance to the publisher user in response to the publisher posting the live appliance. Other embodiments of this aspect include corresponding methods, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of opening a proxy file in response to a user action on a computer, automatically invoking a player application on the computer, the player application performing player actions that include using the proxy file to locate the current version of the virtual machine image; and causing the current version of the virtual machine image to be run by a virtual machine monitor. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in memory devices for storing data for access by an application program being executed on a data processing system, whether the memory devices include a data structure stored in the memory, the data structure including a proxy for a live appliance; a data source; and one or more virtual machine version configurations, each version configuration including one or more links to a corresponding virtual machine image; wherein the proxy includes a source identifier that can be resolved to a location of the data source; the data source includes data designating one of the versions of the virtual machine image as the current version, the current version being described by a current version description; and each version configuration contains configuration data describing the corresponding virtual machine image. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a user interface of a computer an uninterrupted user action opening a proxy document and, in response to the user action and without further user intervention, performing actions that include identifying, based on information in the proxy document, a live appliance; determining whether the computer has subscribed to the live appliance and, if not, subscribing to the live appliance; and running a current version of a virtual machine image from the live appliance, the live appliance including one or more versions of the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of registering a live appliance file type on a computer to associate the file type with a player application on the computer, wherein running the player application in response to a user action or a programmatic action opening a first document of the file type on the computer, the player application performing actions that include acting on the first document by reading feed data from a first live appliance data feed source, the data feed source being the first document or being identified by a source locator in the first document; reading a first virtual machine image, the virtual machine image being in the feed source or being identified by an image locator in the feed source; and causing the first virtual machine to be run by a virtual machine monitor. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving in a user interface of a computer an uninterrupted user action opening a proxy document having a live appliance file type and, in response to the user action and without further user intervention, automatically invoking a player application on the computer, the player application performing actions that include identifying a remote source identifying a current version of a virtual machine image based on information in the proxy document; determining whether a copy of the current version of the virtual machine image has been downloaded to the computer and if not, beginning to download the virtual machine image to the computer; and running the virtual machine image on a virtual machine monitor on the computer. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in methods that include the actions of binding data files for a virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. In general, another aspect of the subject matter described in this specification can be embodied in computer program products tangibly embodied in a computer-readable medium that include a dependent helper in a virtual machine image to implement a user file system protocol to read and write the data files on a local data store, the dependent helper being operable to perform actions including binding data files for the virtual machine image to the virtual machine image automatically from outside the virtual machine image, the data files being also visible as local files on the computer, the data files being bound by being mounted as a directory hierarchy within or as a home directory or a user profile in the virtual machine image; and a player operable to perform actions including configuring a host computer to provide a guest operating system with the user file system for reading and writing the data files. Other embodiments of this aspect include corresponding systems, apparatus, and methods. The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A, 1B, and 1C are schematic diagrams illustrating alternative architectures using one or live appliances in accordance with the invention. FIG. 2 is a schematic diagram illustrating an architecture for publishing, distributing, and subscribing to one or more live appliances. FIG. 3 is a schematic diagram illustrating an alternate view of an architecture for publishing, distributing, and subscribing to one or move live appliances. FIG. 4 is a flow chart illustrating a method for applying updates to a live appliance FIG. 5 is a flow chart illustrating a method for publishing a live appliance FIG. 6 is a flow chart illustrating a method for subscribing to a live appliance FIG. 7 is a flow chart illustration a method for creating a live appliance Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION This specification describes technologies for publishing, distributing, and subscribing to one or more live appliances. A live appliance includes a sequence of virtual machine images. FIGS. 1A, 1B, and 1C show illustrative host system architectures for using a virtual machine from a live appliance. In the architecture shown in FIG. 1A, a host computer includes host hardware 130 and a host operating system 132. The host computer provides a host file system, generally as part of the host operating system 132, which can be stored on a variety of storage mediums, e.g., hard disks and flash disks, local to or remote from the host computer. The host computer generally also includes one or more host devices, e.g., keyboard, mouse, or Ethernet card. The host computer will also be referred to as the subscriber or subscriber computer, because live appliance player software 120 running on the computer causes it to subscribe to a live appliance. The live appliance is located on a remote service (e.g., a subscription service). The subscription service is described in more detail in reference to FIG. 2. The live appliance is described in more detail in reference to FIG. 3. A live appliance includes or defines a sequence of one or more virtual machine images, one of which is identified as the current virtual machine image by live appliance metadata. A virtual machine image is a specific instance of a virtual machine. There are many varieties of virtual machines, for example, full or machine-level virtualization and para-virtualization virtual machines. A full virtualization virtual machine can run more than one kind of an unmodified guest operating system. Para-virtualization virtual machines can only run guest operating systems that have been modified to run on a special architecture that is specified by the virtual machine implementation. A virtual machine image generally encapsulates a complete computer configuration. A virtual machine image can include the contents of local storage (e.g., hard disks), RAM, and device configurations. The contents of the local storage can include a variety of software systems, generally including a guest operating system and one or more applications, which can be applications of any kind, including word processors, financial applications, web browsers, or other software applications. When a virtual machine image is run by a virtual machine monitor, it allows the user of the virtual machine image to run the applications on the guest operating system. FIG. 1A illustrates a running virtual machine image 112 that has two applications, Application A 116a and Application B 116b, installed to run on the guest operating system 114. The applications 116a, 116b and the guest operating system 114 were installed on the virtual machine of the virtual machine image before the virtual machine image 112 was downloaded by the live appliance player 120. Additional applications can be installed after the virtual machine 112 has been downloaded. The virtual machine image 112 is being run by a virtual machine monitor 124 that is part of, or alternatively invoked by, a live appliance player 120. In the implementation illustrated, the virtual machine monitor 124 is part of a virtual appliance transceiver (VAT) 140, which also includes management software 128 to perform management functions, e.g., receiving virtual machine data blocks, exporting data for backup, and publishing virtual machine images. The virtual appliance transceiver 140 also includes storage 126, memory and data storage, which can be implemented in the form a file or a directory of files on a native host file system, for use in caching blocks of the virtual machine image and other purposes. In some implementations, the VAT or live appliance player does not include, but instead invokes, an appropriate virtual machine monitor 124. A description of a suitable virtual appliance transceiver can be found in U.S. patent application Ser. No. 11/007,911, entitled “Cache-Based System Management Architecture With Virtual Appliances, Network Repositories, And Virtual Appliance Transceivers”, filed Dec. 8, 2004, and U.S. Patent Application No. 60/528,220, filed Dec. 8, 2003. The entire content of both applications is incorporated in this application by reference. A description of a suitable virtual appliance transceiver can also be found in R. Chandra, N. Zeldovich, C. Sapuntzakis, and M. S. Lam, “The Collective: A Cache-Based System Management Architecture,” Proceedings of the 2nd Symposium on Networked Systems Design and Implementation (NSDI 2005), May 2005. The virtual appliance transceiver transmits and receives virtual machine images in a distributed environment such as the Internet or a private network. The live appliance player 120 can cause the most current virtual machine image, as received by the VAT to be executed by a virtual machine monitor 124. Example virtual machine monitors include VMware Player®, available from VMware, Inc. of Palo Alto, Calif., and Microsoft® Virtual Server, available from Microsoft Corporation of Redmond, Wash. The live appliance player 120 performs a subscription process 125. The subscription process 125 ensures that live appliance player 120 has the current virtual machine image for the live appliance. The subscription process 125 can run as a background process and receive periodic updates on the status of, and changes to, the virtual machine images of a live appliance to which the player has subscribed. The subscription process 125 can poll a service to determine if new updates are available, or it can receive updates pushed by a service. New updates are downloaded by the process 125 as necessary. If updates are available the live appliance player can install the updates without user intervention, though the update may not be available until the user restarts the virtual machine. FIG. 1B illustrates an alternative arrangement of the elements of the architecture. In this arrangement, a hypervisor 150 is running on the hardware 130, and the host operating system 132 is running on the hypervisor. An arrangement of this kind is implemented in a Xen™ hypervisor, available from XenSource, Inc. of Palo Alto, Calif. Normal virtual machine images 112a and 112b run on the hypervisor 150. Some guest operating systems in the guest virtual machines are modified to run on the hypervisor. Because the virtual machine monitor is substantially implemented in the hypervisor 150, the live appliance player 121 running on the host operating system 132 does not include the virtual machine monitor, but still includes the other functionality of the live appliance player 120 described in reference to FIG. 1A, namely a subscription process 145 corresponding to subscription process 125, a virtual appliance transceiver 141, which corresponds to virtual appliance transceiver 140 minus the virtual machine monitor 124, but including storage 146 and management functions 148 corresponding to storage 126 and management functions 128, respectively. FIG. 1C illustrates a further alternative arrangement of the elements of the architecture. In this arrangement, the live appliance player 160 is constructed to run directly in a virtual machine on a guest operating system on the hypervisor 150, as are the subscription process 168, the virtual appliance transceiver 162, the storage 164 and the management functions 166, which correspond to the modules previously described of the same name. As in the arrangement of FIG. 1B, any number of guest virtual machine images 112c can be run on the hypervisor 150. To provide writeable user file storage for applications running on a virtual machine, the live appliance player can provide a networked file system to be mounted in the virtual machine. The mounting can be done manually by a user of the virtual machine or, more conveniently, it can be done automatically by a helper program installed on the virtual machine by the publisher. This writeable storage may be referred to as a user file system, to distinguish it from the file system embodied in the virtual machine image disks. The user file system can be also be visible to and mounted by programs running on the host operating system 132 of the host computer. The storage for the user file system can be provided by any memory device attached to, or in communication with, the host computer, including an internal disk drive, an external disk drive, a file server, an attachable disk drive, or an attachable solid state memory device (e.g., USB flash drive or an audio or video player). A live appliance player can create a user file system by configuring a directory in the host file system that will store the user files for a virtual machine image. The live appliance player then configures the host operating system to export the directory using a network file system. For example, in the Microsoft® Windows operating system, the user file system is conveniently a Common Internet File System (CIFS). For the Linux operating system, the user file system can conveniently be either a CIFS or NFS file system. Network path(s) describing how to mount the user files (e.g., \\192.168.74.1\NTWSHR$ for CIFS) are passed to the running virtual machine image, to help the virtual machine find and mount the exported directory. When a virtual machine image is started, the virtual machine reads the network paths and sets up the user home directory (e.g., in the Linux operating system) or profile (e.g., in the Windows operating system), or a directory under the home directory or part of the profile (e.g. My Documents), to point to the user file system. In some implementations, it is possible to run a custom (e.g., non-NFS and non-CIFS) user file system (e.g., VMware® Workstation Shared Folders or Microsoft™ Virtual PC Shared Folders) over a non-network interface between a guest operating system and the host operating system with the goal of improving performance and reliability. Such implementations integrate the file system server into the virtual machine monitor to improve performance. The implementation includes user file system clients for Windows or Linux guests or both. The implementation has interfaces by which the guest operating system can call into the host operating system requesting service and by which the host operating system can return status and data to the guest operating system. The custom user file system, as described, removes the overhead of the generality of the network protocols used with a networked file system. FIG. 2 shows an illustrative architecture 200 of a system for publishing, distributing, and subscribing to one or more live appliances. The architecture 200 is used to facilitate the sharing of one or more live appliances over a network by publishers 216 of live appliances. The architecture 200 includes a subscription service 210 and a distribution service 220. The subscription service 210 and the distribution service 220 can exist on the same network server or on different network servers. The subscription service 210 and the distribution service 220 can also exist under the same administrative domain or they can exist under different administrative domains. Each service communicates with a database to obtain data to fulfill requests generated by users. A database can be any organized collection of data, whether or not managed by some kind of database management system, and whether or not stored in a single location. Requests are fulfilled using a live appliance player that can subscribe to or invoke a live appliance. The subscription service 210 includes a post interface 211, an update interface 212, and a database 213. The interfaces are used in conjunction with the database to provide users with a mechanism to create and update live appliances through the generation or modification of data sources 214 and the generation of proxy files 215. The post interface 211 accepts connections from a publisher 216. The publisher 216, using the post interface 211, can post a live appliance, which registers the live appliance and creates a corresponding data source 214 so that the live appliance can be accessed by other users. Publishing live appliances is described in more detail in reference to FIG. 5. The update interface 212 also accepts connections from a publisher 216. The update interface allows the publisher 216 to update data sources files that already exist in the database 213. The update interface also ensures that the publisher 216 originally posted the data source that is being updated or is otherwise authorized to do so. Using the update interface is described in more detail in reference to FIG. 4. A data source 214 contains data that describes a corresponding live appliance. When a live appliance is posted or updated, the corresponding data source is created or updated, respectively. A data source contains a unique identifier for the live appliance and version information for the one or more virtual machine images that the live appliance includes. A data source 214 for a live appliance can be distributed to users once the live appliance has been registered through the post interface. The live appliance player can poll a data source to determine if the data source has changed. Data sources are described in more detail in reference to FIG. 3. A proxy file 115 is a metadata file used to point to a corresponding data source 114. Proxy files 115 can be distributed once a live appliance has been registered through the post interface 111. Proxy files 115 can be opened by a user through a graphical user interface (GUI) of a shell. Proxy files are described in more detail in reference to FIG. 3. The distribution service 220 is used to distribute live appliances. The distribution service can be centralized (e.g., a hosted HTTP server) or distributed (e.g., a peer-to-peer file sharing network). The distribution service 220 includes an upload interface 222 and a database 224. The upload interface 222 allows a user to upload a virtual machine image 225 that is later accessed by a live appliance. The upload interface 222 can communicate through a web based interface or a graphical user interface attached to an application, e.g., an FTP application. Virtual machine images 225 are accessed by other users after the live appliance has been published through the post interface 211. Uploading the virtual machine images can be accomplished during the publishing processes, or can be accomplished at a later time. Publishing is described in more detail in reference to FIG. 5. The distribution service serves or distributes, from the database 224, upon request, the virtual machine images 225 and the version configuration files 226 (e.g., virtual machine configuration files). The distribution service data database 224 can include one or more virtual appliance images 225 and one or more version configuration files 226. Version configuration files 226 provide configuration information for corresponding virtual machine images. Version configuration files 226 can exist in a variety of formats, e.g., a flat or an Extensible Markup Language (XML) file. In one embodiment, an XML formatted file is used. Version configuration files 226 are described in more detail in reference to FIG. 3. FIG. 3 is a schematic diagram illustrating another view of the architecture for publishing, distributing, and subscribing to one or more live appliances. As described previously, a publisher receives a proxy file 215 after registering the live appliance with a subscription service. The publisher can distribute the proxy file 215 to subscribers. Subscribers open the proxy file 215, and, because the proxy file has a file type mapped to a live appliance player or a helper program, opening the proxy file results in starting the player or the helper. The file type can be mapped to the player or helper program by having been registered with an operating system on the subscriber's computer or with an application, e.g., a web browser, running on the subscriber's computer. This registration can be built into the operating system or application, or the subscriber can register the file type. If the file type is mapped to the helper, the helper informs the live appliance player of the user's opening of the proxy file. The proxy file includes an optional live appliance identifier 302 and a data source identifier 304. The data source identifier 304 can be used to access the data source 214. The identifier 304 can be, for example, a URI (Uniform Resource Identifier) pointing to an Rich Site Summary (RSS) feed that includes live appliance metadata and points to configuration data for a current version of the virtual machine image of the live appliance. A data source 214 includes a unique identifier 306, and can include optional maintainer information 308, and information identifying an active environment 310, which can be a URI pointing to a configuration file for a current virtual machine image. The unique identifier 306 is represented as a string. The data source 214 is stored in the subscription server. The data source 214 can be implemented as an RSS feed or as a document pointed to by such a feed. The data source 214 for a live appliance to which a player has subscribed is regularly polled by the player, which downloads updates as the data source 214 changes. In alternative implementations, the player learns of updates from update notifications pushed to live appliance subscribers. The maintainer information 308 specifies the name and e-mail address of the one or more individuals responsible for the live appliance. Maintenance responsibilities include but are not limited to updating new live appliances on the subscription servers, including uploading new virtual machine images for a live appliance to the distributions servers. A version description 309 can be implemented as a separate file or it can be included as part of the data source 214. The active environment 310 information can be a URI pointing to a version description file 309. The active environment can optionally be implicit, if only one version description exists. A version description can include a number of optional items of information: a title 312, a description 314, a logo 316, and a change history 318. The version description includes configuration identifier 320. If the data source 214 includes additional version descriptions 309a, 309b or immediately prior versions of the virtual machine image, portions of those version descriptions can be the same, e.g., the title 312, while others will generally be different e.g., the change history 318. The title 312 is a short string that defines a name for the live appliance. For example, “Hikarunix” or “Elive 0.4.2.” The description 314 is a string of generally greater length than the title 312 and is used to specify the characteristics of the live appliance. Example characteristics include the operating system or applications that the live appliance has installed. The logo 316 is used to graphically represent the live appliance as an icon. Logos can be specified as a URI to an image file. The configuration identifier 320 is a network reference, e.g., a URI, that can be used to identify a configuration file 322, e.g., a virtual machine configuration file, that specifies configuration information for a corresponding virtual machine image. Configuration files 322 322a, 322b are stored in distribution servers. The current configuration file 322 includes virtual machine configuration information 324 and disk properties and location information 326. The configuration file 322 can exist in a variety of formats, e.g., flat-file or XML. Virtual machine configuration information 324 is a reference to a virtual machine description file, for example, a VMware.vvmx file. A VMware.vmx file can specify, for example, the memory settings of the virtual machine image, the type of disk controller, the number of network interfaces, and the address of each network interface, among other things. The disk properties and location information 326 specifies, for example, the size of the disk and whether the contents of the disk persist across restarts of the virtual machine image. The number of disks is specified when the virtual machine image is created and can vary. For example, the number of disks in a first version of a virtual machine image can differ from the number of disks in a second version of a virtual machine image. Each disk specified by the disk properties and location information 326 can be stored in and access through one or more distribution services 220 as a disk image 328 of a virtual machine image 330. In one implementation, the disk images are copy-on-write (COW) disks. FIG. 4 is a flow chart illustrating a method for applying updates to a live appliance. As previously described, a publisher can publish (step 410) a live appliance through the use of the post interface. As part of the posting process, the publisher receives a proxy, e.g., an XML proxy file or a URL that includes the necessary metadata. Publishing is described in more detail in reference to FIG. 5. The publisher can distribute the proxy to others, allowing users with the proxy to subscribe (step 420) to the live appliance automatically by opening the proxy. In one implementation, opening a proxy file in a GUI shell, e.g., by clicking on an icon representing the file, invokes a live player, which will run and subscribe to the corresponding live appliance, if necessary, and begin running it. Subscription is described in more detail in reference to FIG. 6. The publisher can also choose (step 430) to update (step 440) the live appliance. As previously described, to update the live appliance, the publisher uses the update interface. The update interface allows the publisher to enter the parameters for a new version in the live appliance data source. The update interface generates an updated data source that defines the newest version of a live appliance, specifying the most current version of the virtual machine image. After an update has occurred, when a subscriber attempts to invoke the live appliance through the live appliance player or by opening the corresponding proxy file, for example, the subscriber automatically receives (step 450) the most current version of the virtual machine image, unless the subscriber update was delayed, for example, due to disconnection or because the background update process had not yet picked up the update. FIG. 5 is a flow chart illustrating a method for publishing a live appliance. The publisher initially creates (step 510) a live appliance. The live appliance can be created from scratch, created from an existing live appliance, by importing a Live CD, or by importing a virtual machine, for example, a VMware virtual machine. Importing a Live CD can be done by create a VMware virtual machine with a CD-ROM device pointing to the ISO image of the Live CD. Importing a VMware VM can be as simple as creating a live appliance version configuration for the VM. A live appliance can be created from scratch by specifying certain properties, e.g., the operating system, certain computing system requirements (e.g., memory usage), and the virtual devices present. The import module of the live appliance player uses these properties to create a virtual machine image and associate the virtual machine image with the live appliance. A live appliance that is created from an existing live appliance inherits a copy of its basic properties from the original, but the publisher can, for example, add additional applications to the live appliance. If a live appliance is created from an existing live appliance, the live appliance player can share disk storage for blocks that have not changed between the two versions; this sharing can also be used to avoid transferring such blocks multiple times over a network connection. Creating a live appliance is described in more detail in reference to FIG. 7. Once the live appliance has been created (step 510) by the publisher, the publisher can upload (step 520) the virtual machine image that is used by the live appliance to network storage (e.g., the distribution services). As previously described, the publisher uses the upload interface on the distribution servers to upload the virtual machine image. The publisher also posts (step 530) the previously created live appliance on the subscription server. As previously described, posting is accomplished through a post interface. After a successful posting operation, the subscription service creates a proxy file stored on the subscription service that can be downloaded by the publisher or linked to by the publisher. The publisher is then able to send (step 540) the proxy to other subscribers. For example, subscribers can receive a proxy file as an e-mail attachment, as a link on a website, as a file on a USB drive, a CD, or through any other process of transferring files between computer systems. After the subscriber has received the proxy, the subscriber can invoke the live appliance by activating the proxy, e.g., by opening the proxy file. The subscriber is then taken through a subscription process, e.g., one of the kind described in reference to FIG. 6. FIG. 6 is a flow chart illustrating a method for subscribing to a live appliance using a proxy file. As previously described, the subscriber obtains (step 610) a proxy file for a live appliance from a publisher or by way of a process specified by the publisher (e.g., clicking on a link on a website). The subscriber can open (step 620) the proxy file at any time. The subscriber does not need to open the proxy file immediately. The proxy file does not need to be opened before the live appliance is updated. Once the proxy file is opened, the live appliance player determines (step 630) if the live appliance has previously been subscribed to based on the live appliance identifier in the proxy file. If the live appliance has not been subscribed to, the live appliance player selects (step 640) the version of the live appliance identified as the current live appliance in the live appliance data source file. The live appliance player then downloads (step 650) the live appliance data source and version configuration to the subscriber's computer. The live appliance player also downloads (step 650) the most current version of the virtual machine image to the subscriber's computer. The live player can download portions of the virtual machine image on demand as they are needed, or while the subscriber's computer is idle. The live appliance player initiates (step 660) a maintenance process on the subscriber's computer to obtain live appliance data. The process can poll the subscription service to determine if a live appliance has been updated. In some implementations, the subscription service pushes information to subscribed live appliance players, in addition to accepting polling requests. Once a live appliance player has determined, or been informed of, the existence of an update, the player can download the new virtual machine image. Downloading can occur immediately, or at some later point in time. Once the live appliance has been subscribed to and the necessary portions of the download have completed, the live appliance starts (step 670). While the live appliance is executing, the live appliance player can complete (step 680) downloading the current virtual machine. As described previously, downloading can occur on demand, or when the subscriber's computer is idle. FIG. 7 is a flow chart illustration a method for creating a live appliance. As previously described, a live appliance can be created from scratch, from an existing live appliance, or from an existing virtual machine. The live appliance player determines (step 710) if the live appliance to be created is based on an exiting live appliance. If the desired live appliance is based of an existing live appliance, the live appliance player invokes (step 720) the existing live appliance. Otherwise, the live appliance player determines (step 730) if live appliance to be created is based on an existing virtual machine. If the desired live appliance is based on an existing virtual machine, the live appliance player imports (step 740) the virtual machine as a live appliance. If the desired live appliance is not based on an existing live appliance or a virtual machine, the live appliance player creates and configures (step 750) a new live appliance. For example, the newly created live appliance can be configured with a virtual machine name, operating system, various drives (e.g., floppy, IDE, or SCSI), and virtual devices. The live appliance player creates the VMware virtual machine, including the disks and configuration file, and the live appliance version configuration. All files are placed in the same subdirectory and relative URLs are used to link between them. The live appliance data source and live appliance proxy are not created at this time. After a live appliance has been created and configured the publisher installs (step 760) the selected operating system. The operating system is installed from an operating system installer that the publisher has in their possession. Example installers include, install CDs or CD images and installer executables stored locally or remotely. The operating system is installed from the installer onto a virtual machine image of the live appliance. Once the live appliance player invokes an existing live appliance, the live appliance player has imported an existing virtual machine, or a live appliance has been created, the publisher can install (step 770) applications or customize (step 770) the live appliance. The process of installing applications is similar to installing the operating system; the publisher must have access to the installer for the applications they wish to install. The publisher can customize the live appliance by changing the parameters that were defined during the creation of the original live appliance, e.g., memory usage or virtual devices. After the publisher has installed their desired applications, they create (step 780) a serialization of the live appliance using the live appliance player. The live appliance player compresses the virtual machine image using traditional compression techniques. Once compressed, the publisher can upload the virtual machine image to a distribution server through the previously described upload interface. Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer-readable medium for execution by, or to control the operation of, data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. A propagated signal is an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus. A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network. The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, to name just a few. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry. To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described is this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), e.g., the Internet. The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. While this specification contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Particular embodiments of the subject matter described in this specification have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results.	G	60G06	161G06F	94	55
11699996	US20070132775A1-20070614	Buffer management in vector graphics hardware	ACCEPTED	20070531	20070614	[]	G06F1210	["G06F1210"]	8390634	20070131	20130305	345	537000	74558.0	MCDOWELL, JR	MAURICE	[{"inventor_name_last": "Tuomi", "inventor_name_first": "Mika", "inventor_city": "", "inventor_state": "", "inventor_country": "US"}]	A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.	1. A processor unit for processing vector graphics primitives, the processor unit comprising: counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel; a first internal buffer configured to store at least one indicator bit value for each pixel; and determination logic configured to determine whether to retrieve and to retrieve the counter value from a memory based on the indicator bit values. 2. The processor unit of claim 1, wherein the processor unit is further configured to clear said memory by resetting said indicator bit values from said first internal buffer. 3. The processor unit of claim 1, the processor unit further comprising a bus, wherein said processor is configured to receive instructions and data from said bus 4. The processor unit of claim 3, wherein in said bus is a unidirectional bus. 5. The processor unit of claim 1, further comprising: a second internal buffer configured to store limited values for each counter, wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer. 6. The processor unit of claim 5, wherein the processor unit is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer. 7. The processor unit of claim 5, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed. 8. The processor unit of claim 5, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory. 9. The processor unit of claim 5, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved. 10. The processor unit of claim 1, wherein the memory is an external memory configured to store counter values for each pixel to be processed. 11. The processor unit of claim 1, wherein the memory is an internal memory configured to store counter values for each pixel to be processed. 12. The processor unit of claim 1, wherein a memory is configured to store complete counter values for each sub-pixel having a counter. 13. The processor unit of claim 1, wherein the processor unit further comprises: an internal memory arranged to store a portion of the complete counter values. 14. The processor unit of claim 13, wherein the portion is a scan line. 15. The processor unit of claim 13, wherein the portion is a tile. 16. A processor unit for processing vector graphics primitives, the processor unit comprising: an internal memory configured to store a portion of vector graphics primitives; and wherein said portion of vector graphics primitives is a tile corresponding to a portion of the memory wherein said vector graphics primitives are stored. 17. The processor unit of claim 16, wherein the processor unit further comprising: counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel. 18. A handheld device, comprising: a display; a processing unit for processing vector graphics primitives, and including: counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel, a first internal buffer configured to store at least one indicator bit value for each pixel, a memory for storing data, and determination logic configured to determine whether to retrieve and to retrieve the counter value from a memory based on the indicator bit values. 19. The handheld device of claim 18, wherein the handheld device is further configured to clear said memory by resetting said indicator bit values from said first internal buffer. 20. The handheld device of claim 18, the handheld device further comprising a bus, wherein said processing unit is configured to receive instructions and data from said bus 21. The handheld device of claim 18, wherein in said bus is a unidirectional bus. 22. The handheld device of claim 18, wherein the processing unit further comprises: a second internal buffer configured to store limited values for each counter, wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer. 23. The handheld device of claim 22, wherein the handheld device is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer. 24. The handheld device of claim 22, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed. 25. The handheld device of claim 22, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory. 26. The handheld device of claim 22, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved. 27. The handheld device of claim 18, wherein the memory is an external memory configured to store counter values for each pixel to be processed. 28. The handheld device of claim 18, wherein the memory is an internal memory configured to store counter values for each pixel to be processed. 29. The handheld device of claim 18, wherein a memory is configured to store complete counter values for each sub-pixel having a counter. 30. The handheld device of claim 18, wherein the processor unit further comprises: an internal memory arranged to store a portion of the complete counter values. 31. The handheld device of claim 30, wherein the portion is a scan line. 32. The handheld device of claim 30, wherein the portion is a tile. 33. The handheld device of claim 18, wherein the device comprises a handheld device. 34. An apparatus for processing vector graphics primitives, the apparatus comprising: counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel; a first internal buffer configured to store at least one indicator bit value for each pixel; and determination logic configured to determine whether to retrieve the counter value from a memory based on the indicator bit values, wherein the apparatus is further configured to clear said memory by resetting said indicator bit values from said first internal buffer. 35. The apparatus of claim 34, wherein the apparatus further comprising a second internal buffer configured to store limited values for each counter, wherein the determination logic is further configured to determine whether to retrieve the limited counter values from the second buffer and wherein the apparatus is further configured to clear said memory and said second internal buffer by resetting said indicator bit values from said first internal buffer. 36. The apparatus of claim 34, where in the apparatus is further comprising a unidirectional bus for receiving instructions.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention generally relates to buffer management, and more particularly to buffer management in vector graphics hardware. 2. Discussion of the Background In recent years, vector graphics systems and algorithms have been developed for achieving robust and exact visualization, and have been employed in demanding software applications, such as in computer aided design, graphics applications, and the like. The benefit of the employing vector graphics, include scalability without the loss of graphics quality. The vector in a drawing or a plan typically includes a starting point, a direction, and a length or an ending point. Thus, a line can be represented using vector graphics with reduced information, as compared to having to indicate each pixel of the line, as with other methods. Furthermore, the vector need not be a direct line, as curves, and the like, also can be employed, and including additional information, for example, for defining a curve. The corresponding format employed during the execution of a corresponding graphical application, the file format for storing the corresponding graphical information, the fundamentals of vector graphics and the corresponding software applications employed, and the like, are well known and will not be described in detail herein. In addition, certain graphics standards have been developed, such the OpenVG 1.0 standard by Khronos group of Jul. 28, 2005, incorporated by reference herein, and which includes an application programming interface (API) for hardware accelerated two-dimensional vector and raster graphics applications. The standard provides a device independent and vendor-neutral interface for sophisticated two-dimensional graphical applications, while allowing device manufacturers to provide hardware acceleration on devices ranging from wrist watches, to full microprocessor-based desktop systems, to server machines, and the like. The standard provides an interface for a set of functions that can be implemented by hardware and/or software drivers for rasterization, filling of polygons, and the like. In the standard, two different fill rules, a non-zero and an odd/even rule, are implemented, and are described at page 72 of the standard. The basic principle of such filling technique employs the fact that each edge of a polygon has a direction, such that when the filling procedure arrives at the edge from the left, the filling procedure detects if the edge is going up or down. If the edge is going upwards, a counter is increased, and if the edge is going downwards, the counter is decreased. The value of the counter is stored in a buffer for each pixel on the screen. However, the pixels are further divided into sub-pixels, wherein the counter values must be stored for each line of each sub-pixel, requiring even larger buffers. The above technique presents a problem for compact hardware implementations, and the like, and which may limit the buffer size, for example, due to manufacturing considerations, cost considerations, and the like. For example, if a mobile device has a display resolution of 176×208 pixels, and each pixel is divided into 16×16 sub-pixels, and an 8-bit counter is employed for each line, a buffer of 585728 bytes is needed. However, a buffer of such size may not be practical for integration on a graphics hardware accelerator of such a mobile device. Furthermore, merely adding more memory to the graphics hardware accelerator may not be practical, for example, due to the common evolvement in manufacturing processes, a need for bigger graphics resolutions, and the like. One solution is to use the main memory of the device for implementing the above-noted buffer. However, such a solution results in increased traffic on limited bandwidth buses between the graphics accelerator and the main memory.	<SOH> SUMMARY OF THE INVENTION <EOH>Therefore, there is a need for decreasing traffic on buses between a main memory, and a graphics accelerator, as described above. The above and other problems are addressed by the exemplary embodiments of the present invention, which provide an exemplary hardware implemented vector graphics solution. The exemplary embodiments can be employed with various graphical applications, including computer graphics applications, and the like, and in particular handheld device applications, low computing capacity device applications, memory limited device applications, and the like. Accordingly, in exemplary embodiments of the present invention there are provided a graphics processor, a graphics processing unit, a functional block for a graphics processor, a graphics device, and the like, for processing vector graphics primitives, and the like. The exemplary embodiments can include counters for storing a value indicating a current state of a fill rule for each of a sub-pixel sampling point. The counter values are stored in a memory that can be an internal memory of the graphics processor or an external memory, for example, a conventional memory of a device. The exemplary embodiments further can include a bus for receiving instructions and primitives. If the memory is an internal memory, the bus is unidirectional, and if the memory is external, the bus is bidirectional for transmitting requests to the memory. Accordingly, the memory is used for storing the values of each of the counters. The exemplary embodiments further can include a first internal buffer arranged to store at least one indicator bit value for each pixel. Typically, the internal buffer has values having a length of one or two bits. However, different bit lengths can be employed, as needed. The exemplary embodiments further can include determination logic arranged to determine whether or not to retrieve a counter value from the memory based on the indicator bit values. The indicator bits of the first buffer include a value for indicating that a value of a counter has not changed. Furthermore, the indicator bits of the first buffer include a value for indicating that a value of a counter has to be retrieved from the memory, which can be internal or external, depending on a given implementation, as described above. The exemplary embodiments can include a second internal buffer arranged to store limited values for each counter, and the determination logic can be further arranged to determine whether or not to retrieve the counter value from the second buffer. The indicator bits of the first buffer further can include values for indicating a range of the second buffer from which the limited value of each counter can be retrieved. In an exemplary embodiment, polygons can be processed in tiles, wherein, advantageously, the internal memories employed need not be allocated for the whole screen, but rather a portion thereof. The tile size can be, for example, 32×32 pixels. In further exemplary embodiments such a size can be chosen depending on a given implementation, and various other hardware architectures can be employed for the internal memory, the internal buffers, and the like, as will be appreciated by those skilled in the hardware art(s). Advantageously, the exemplary embodiments can be employed to reduce traffic in a bus between a graphics accelerator and an external main memory, by employing the internal memory in the graphics processor, and which is faster than the external main memory that is addressed over the bus. As the exemplary embodiments include the counter information in the first or the second buffers internal to the graphics processor, advantageously, the main memory need not be addressed for every pixel, resulting in a solution that is beneficial and faster than conventional approaches to solving the above-noted problem. Furthermore, with the exemplary embodiments, the first buffer and the second buffer can be reduced in size, advantageously, allowing integration thereof in a graphics processor, and resulting in minimizing of manufacturing costs. Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, by illustrating a number of exemplary embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive.	CROSS REFERENCE TO RELATED DOCUMENTS The present invention is a continuation of U.S. patent application Ser. No. 11/272,867 of TUOMI, entitled “BUFFER MANAGEMENT IN VECTOR GRAPHICS HARDWARE,” filed Nov. 15, 2005, and is related to U.S. patent application Ser. No. 11/272,866 of TUOMI, entitled “VECTOR GRAPHICS ANTI-ALIASING,” filed Nov. 15, 2005, the entire disclosures of all of which are hereby incorporated by reference herein. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to buffer management, and more particularly to buffer management in vector graphics hardware. 2. Discussion of the Background In recent years, vector graphics systems and algorithms have been developed for achieving robust and exact visualization, and have been employed in demanding software applications, such as in computer aided design, graphics applications, and the like. The benefit of the employing vector graphics, include scalability without the loss of graphics quality. The vector in a drawing or a plan typically includes a starting point, a direction, and a length or an ending point. Thus, a line can be represented using vector graphics with reduced information, as compared to having to indicate each pixel of the line, as with other methods. Furthermore, the vector need not be a direct line, as curves, and the like, also can be employed, and including additional information, for example, for defining a curve. The corresponding format employed during the execution of a corresponding graphical application, the file format for storing the corresponding graphical information, the fundamentals of vector graphics and the corresponding software applications employed, and the like, are well known and will not be described in detail herein. In addition, certain graphics standards have been developed, such the OpenVG 1.0 standard by Khronos group of Jul. 28, 2005, incorporated by reference herein, and which includes an application programming interface (API) for hardware accelerated two-dimensional vector and raster graphics applications. The standard provides a device independent and vendor-neutral interface for sophisticated two-dimensional graphical applications, while allowing device manufacturers to provide hardware acceleration on devices ranging from wrist watches, to full microprocessor-based desktop systems, to server machines, and the like. The standard provides an interface for a set of functions that can be implemented by hardware and/or software drivers for rasterization, filling of polygons, and the like. In the standard, two different fill rules, a non-zero and an odd/even rule, are implemented, and are described at page 72 of the standard. The basic principle of such filling technique employs the fact that each edge of a polygon has a direction, such that when the filling procedure arrives at the edge from the left, the filling procedure detects if the edge is going up or down. If the edge is going upwards, a counter is increased, and if the edge is going downwards, the counter is decreased. The value of the counter is stored in a buffer for each pixel on the screen. However, the pixels are further divided into sub-pixels, wherein the counter values must be stored for each line of each sub-pixel, requiring even larger buffers. The above technique presents a problem for compact hardware implementations, and the like, and which may limit the buffer size, for example, due to manufacturing considerations, cost considerations, and the like. For example, if a mobile device has a display resolution of 176×208 pixels, and each pixel is divided into 16×16 sub-pixels, and an 8-bit counter is employed for each line, a buffer of 585728 bytes is needed. However, a buffer of such size may not be practical for integration on a graphics hardware accelerator of such a mobile device. Furthermore, merely adding more memory to the graphics hardware accelerator may not be practical, for example, due to the common evolvement in manufacturing processes, a need for bigger graphics resolutions, and the like. One solution is to use the main memory of the device for implementing the above-noted buffer. However, such a solution results in increased traffic on limited bandwidth buses between the graphics accelerator and the main memory. SUMMARY OF THE INVENTION Therefore, there is a need for decreasing traffic on buses between a main memory, and a graphics accelerator, as described above. The above and other problems are addressed by the exemplary embodiments of the present invention, which provide an exemplary hardware implemented vector graphics solution. The exemplary embodiments can be employed with various graphical applications, including computer graphics applications, and the like, and in particular handheld device applications, low computing capacity device applications, memory limited device applications, and the like. Accordingly, in exemplary embodiments of the present invention there are provided a graphics processor, a graphics processing unit, a functional block for a graphics processor, a graphics device, and the like, for processing vector graphics primitives, and the like. The exemplary embodiments can include counters for storing a value indicating a current state of a fill rule for each of a sub-pixel sampling point. The counter values are stored in a memory that can be an internal memory of the graphics processor or an external memory, for example, a conventional memory of a device. The exemplary embodiments further can include a bus for receiving instructions and primitives. If the memory is an internal memory, the bus is unidirectional, and if the memory is external, the bus is bidirectional for transmitting requests to the memory. Accordingly, the memory is used for storing the values of each of the counters. The exemplary embodiments further can include a first internal buffer arranged to store at least one indicator bit value for each pixel. Typically, the internal buffer has values having a length of one or two bits. However, different bit lengths can be employed, as needed. The exemplary embodiments further can include determination logic arranged to determine whether or not to retrieve a counter value from the memory based on the indicator bit values. The indicator bits of the first buffer include a value for indicating that a value of a counter has not changed. Furthermore, the indicator bits of the first buffer include a value for indicating that a value of a counter has to be retrieved from the memory, which can be internal or external, depending on a given implementation, as described above. The exemplary embodiments can include a second internal buffer arranged to store limited values for each counter, and the determination logic can be further arranged to determine whether or not to retrieve the counter value from the second buffer. The indicator bits of the first buffer further can include values for indicating a range of the second buffer from which the limited value of each counter can be retrieved. In an exemplary embodiment, polygons can be processed in tiles, wherein, advantageously, the internal memories employed need not be allocated for the whole screen, but rather a portion thereof. The tile size can be, for example, 32×32 pixels. In further exemplary embodiments such a size can be chosen depending on a given implementation, and various other hardware architectures can be employed for the internal memory, the internal buffers, and the like, as will be appreciated by those skilled in the hardware art(s). Advantageously, the exemplary embodiments can be employed to reduce traffic in a bus between a graphics accelerator and an external main memory, by employing the internal memory in the graphics processor, and which is faster than the external main memory that is addressed over the bus. As the exemplary embodiments include the counter information in the first or the second buffers internal to the graphics processor, advantageously, the main memory need not be addressed for every pixel, resulting in a solution that is beneficial and faster than conventional approaches to solving the above-noted problem. Furthermore, with the exemplary embodiments, the first buffer and the second buffer can be reduced in size, advantageously, allowing integration thereof in a graphics processor, and resulting in minimizing of manufacturing costs. Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, by illustrating a number of exemplary embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: FIG. 1 illustrates an exemplary graphical device, according to the present invention; and FIG. 2 illustrates a further exemplary graphical device, according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to FIGS. 1 and 2 thereof, there are illustrated exemplary graphical devices, according to exemplary embodiments. As will be appreciated by those skilled in the hardware art(s), the bit values and data type lengths employed in the exemplary embodiments are for exemplary purposes, and in further exemplary embodiments can be selected, for example, depending on the overall design of the corresponding graphics module, and the like. In an exemplary embodiment, the exemplary graphics module can be part of a graphics processor unit, which can be a part of a graphics card, and the like. In further exemplary embodiments, for example, such in embedded system applications, and the like, the graphics processor unit can include further functionality for producing graphics, and the like. Thus, a graphics processor unit according to further exemplary embodiments can include further functionality in addition to the functionality of the exemplary embodiments. In FIG. 1, the exemplary graphical device 10 can include, for example, a mobile telephone, a video graphics card, and the like, and, thus, can include further components that need not be described with respect to the exemplary embodiments, but which can be employed for a given application. The exemplary embodiments, for example, can be implemented in a graphics processor unit 11, and the like, and which can include other functionality 15 that need not be described with respect to the exemplary embodiments, but which can be configured for a given application. The exemplary embodiments can be implemented via logic 12 (e.g., configured to determine whether or not to retrieve and to retrieve counter value from a memory based on indicator bit values), and internal buffers 13 and 14. Furthermore, an external memory 16 connected via a bus 17 can be employed, as shown in FIG. 1. However, the external memory 16 need not be employed, for example, if the exemplary embodiments are implemented in an internal memory of a graphics processor. If the external memory 16 is employed, a bi-directional bus 17 can be provided, as shown in FIG. 1. Otherwise, a unidirectional bus can be employed. In addition, other components in the graphics processing unit 11 may employ a bi-directional bus or unidirectional bus, as needed. The exemplary embodiments are based on an exemplary architecture, which can include three different memory areas that are employed for storing the information for producing a graphical image. The first memory area, which is referred to as an edge buffer 25, can include the complete information for the previously described filling operation. Each pixel includes sub-pixels that typically have a sampling point on each sub-pixel line. Thus, the allocated memory depends on the chosen resolution for each corresponding parameter. For example, for an actual screen resolution of 176×208 pixels, as is common for current mobile phone applications, and the like, each pixel is divided into 16×16 sub-pixels, with each sub-pixel line employing a corresponding 8-bit counter, resulting in a memory allocation of 585,728 bytes for the corresponding counters. The counters are used in the above-noted filling technique, and are employed because the complete information may not be available. The corresponding 585,728 bytes of memory can be configured as an internal or an external memory. However, it may not possible to manufacture such a memory as an internal memory, for example, because of manufacturing costs, and the like, and in which case an external memory can be employed and accessed with a bi-directional bus for requesting a value for each counter value when necessary, as shown in FIG. 1. The two other memories according to the exemplary embodiments include internal buffers 13 and 14, wherein the first internal buffer 13 can be configured as a type buffer 23, and the second internal buffer 14 can be configured as a limited edge buffer 24, for example, when there are no changes in filling rules for each pixel or sub-pixel. Thus, with the exemplary embodiments, advantageously, requests to the external memory can be avoided, minimized, and the like. In an exemplary embodiment, the first internal buffer 13 can be configured to have a resolution of two bits for each pixel. Thus, the corresponding memory allocation employed is 176×208/4 bytes, which equals 9,152 bytes, and which is considerably less than that needed for implementing a complete edge buffer 25. The exemplary values for the type buffer 23 can include and indicate, for example: 00=No information 01=Limited edge buffer, range −1 . . 2 10=Limited edge buffer, range −2 . . 1 11=edge buffer in the external memory The exemplary values indicate from where the filling information for each pixel can be retrieved. For example, a value of 00 can indicate that there is no information available for the current pixels, which means that the state of the filling rule does not change on a current pixel. Thus, no further processing need be performed, as all of the counters have the same values as in the previous pixel. Values 01 and 10 can be used to indicate that information is stored in the second internal buffer 14, which can be a limited edge buffer 24. The significance of the corresponding ranges is further described below with respect to the second internal buffer 14. The value 11 indicates that the counter value cannot be stored in the limited edge buffer 24, but rather can be retrieved from the complete edge buffer 25. According to the exemplary embodiments, the first internal buffer 13 is processed first. Thus, to clear the buffers, each value in the first internal buffer 13 can be set to 00. While computing the edge information, the first internal buffer 13 can be modified, for example, only when information is to be stored to the other buffers. Thus, outdated information stored into other buffers is not accessed, when the value of the type buffer 23 is set to 00. As the counters are assigned for each line of sub-pixels, the second internal buffer 14 includes more information, because there are 16 counters for each pixel. In an exemplary embodiment, the information in the second internal buffer 14 also has a length of two bits, but it is assigned for each sub-pixel sampling point. Thus, each pixel has 32-bits of information, for an implementation employing a 16×16 resolution. Advantageously, a 32-bit length can be covered with a single double word. However, in further exemplary embodiments, any suitable length, for example, depending on a given application can be employed, as will be appreciated by those skilled in the hardware art(s). In the current example, the second internal buffer 14 employs 146,432 bytes, and which is considerably less than that needed for the complete information. With the exemplary embodiments, as two bits of information can be employed for the values 01 and 10, four different numbers can be represented. In addition, as the information can be signed, the possibilities for the values 01 and 10 can include − . . +2, and −2 . . +1, respectively. The selection of such a range can be indicated in the type buffer 23, wherein in most cases, such a range is sufficient for covering the changes within one pixel, advantageously, reducing accesses to the complete edge buffer 25. In an exemplary embodiment, the range can be different for different pixels, but within one pixel a single range can be applied. Thus, if either of the ranges is not acceptable, the type buffer 23 can be set to a value indicating that the counter value can be retrieved from the complete edge buffer 25. According to the exemplary embodiments, data lengths can vary depending on a given application. However, if the type buffer 23, which is the first internal buffer 13, has a data length of one bit, such implementation need not employ the second internal buffer 14. In this case, the type buffer 23 need only indicate if the counter value has to be retrieved from an edge buffer that is stored in the external memory 16. Such implementation is possible, but is not as efficient as the implementation of the example described above. However, such implementation may be employed and may be desirable, for example, if it is not possible to provide sufficient internal memory. In addition, the memory demand for the one-bit type buffer 23 implementation is one half that of the two-bit implementation. In FIG. 2, the exemplary graphics device 20 can include a graphics processing unit 21. In an exemplary embodiment, the screen can be processed in tiles, wherein, advantageously, the corresponding memory and internal buffers need not be allocated for the whole screen resolution. If the memory is an external memory, it can be allocated for the whole screen. Advantageously, with the tiled implementation, the corresponding memory can be an internal memory, due to a reduced need for memory size. Such an internal memory can be used for storing the complete edge buffer 25 for the whole tile. For example, if a 32×32 pixel tile is used, there can be employed 16,384 bytes for the complete edge buffer 25. If the type buffer 23, which is the first internal buffer 13, has 2-bit values, there can be employed 256 bytes for the type buffer 23. If the limited edge buffer 24, which is the second internal buffer 14, is employed and has 2-bit values for each sub-pixel line, there can be employed 4,096 bytes for the limited edge buffer 24. If the limited edge buffer 24 is not employed and the type buffer 23 has 1-bit values, the type buffer 23 need only employ 128 bytes. Advantageously, the memory employed can be adjusted by choosing the tile size without losing the resolution of the values in the buffers. When the type buffer 23, the edge buffer 25, and possibly the limited edge buffer 24 are stored internal to the graphics processing unit 21, the bus 27 can be configured as a unidirectional bus. The bus 27 can configured for receiving instructions and data from other components 28, such as CPU, main memory, and the like. The logic 22 and the other functionality 26 can function as in the exemplary embodiments of FIG. 1. In addition to tiles, in further exemplary embodiments, the screen can be divided into parts or in other ways, can by processed by scan lines, and the like, as will be appreciated by those skilled in the hardware art(s). Although the exemplary embodiments are described in terms of implementation as part of a graphics processor unit, the exemplary embodiments can be implemented as a graphics block included in any suitable processor unit, and the like, as will be appreciated by those skilled in the hardware art(s). The novel aspects of the exemplary embodiments include the logic 22, the type buffer 23, and the edge buffer 25, but may further include the limited edge buffer 24, and the like. The remaining components, for example, such as the bus 27, and the like, can depend on the needs of a given host processor. Advantageously, the exemplary embodiments need not employ a bi-directional bus, even though busses typically are bidirectional in general-purpose processors, graphics processors, and the like. In the tiled exemplary embodiment, the processor unit or graphics block 21 can be configured to process the screen tile by tile. Once a tile is processed, it need not be further employed and can be discarded. Advantageously, the respective tile memory can be re-used by clearing the type buffer 23. As only the data related to the currently processed tile is known, in an exemplary embodiment, appropriate rules can be employed, for example, for controlling the information related to adjacent tiles, and the like. For example, in a typical drawing process, operating from left to right, a currently processed tile can employ information from the left neighbor tile, and may pass information to the right neighbor tile. In an exemplary embodiment, the processing of the complete image can be started from the left. Thus, the first case to be handled is a situation wherein a polygon is not completely in view, but rather is partially out on the left side. In this situation, the portion of the edge exceeding the left border is forced to the left border. If the whole edge is outside the leftmost tile, the complete edge can be forced to the left border of the tile. When the edge is forced to the left border, each of the counters can be changed to produce an image rendered correctly in the visible part of the polygon. Without such forcing, some of the counters would not be changed and this would cause a situation, wherein a part of the pixel would be interpreted as being within the polygon, while another part of the pixel would be interpreted as being outside the polygon. Since the fill rule works cumulatively, all of the counter values in the same horizontal line before the currently processed counter value may need to be known. Thus, the values outside the image can be computed in the left border. The leftmost border can be computed in a similar manner, even if the tiled embodiment is not employed. When the first tile has been processed, the data affecting the second tile can be transferred to the second tile, in various different ways, as will be appreciated by those skilled in the hardware art(s). For example, counters can be employed for passing the values of the sub-pixel counters to the next tile. However, if an edge crosses a sub-pixel so that it is not considered to be within the pixel, the result will not be correct in the next pixel, if this is not taken into account. Thus, when the tile is not the leftmost tile, the edges also can be computed one pixel to the left from the tile currently being processed. In this case, the edges are not forced on the left border, as with the leftmost tile. Similarly, the corresponding information is transferred to the next tile, until the rightmost tile is reached. In the rightmost tile, the information needs to be received from the previous tile, as previously described. However, such information need not be transferred further, as the rest of the edges are out of view. When the rightmost tile has been processed, the rendering moves to the next tile line, and starts from the leftmost tile, as described above. This process can be repeated until the rightmost tile of the last tile line has been processed. At this stage, the current polygon is considered processed, and the above processing can be repeated with the next polygon, until all of the polygons have been processed. The exemplary embodiments can receive the edges from an edge feeder component, configured to send all of the edges that hit on the screen or tile, as will be appreciated by those skilled in the hardware art(s). In addition, in the case of the leftmost tile or complete screen implementation, the edges to the left of the present tile also can be sent, as will be appreciated by those skilled in the hardware art(s). The exemplary embodiments can be included within any suitable device, for example, including any suitable servers, workstations, PCs, laptop computers, PDAs, Internet appliances, handheld devices, cellular telephones, wireless devices, other devices, and the like, capable of performing the processes of the exemplary embodiments, and which can communicate via one or more interface mechanisms, including, for example, Internet access, telecommunications in any suitable form (e.g., voice, modem, and the like), wireless communications media, one or more wireless communications networks, cellular communications networks, G3 communications networks, Public Switched Telephone Network (PSTNs), Packet Data Networks (PDNs), the Internet, intranets, a combination thereof, and the like. It is to be understood that the exemplary embodiments are for exemplary purposes, as many variations of the specific hardware used to implement the exemplary embodiments are possible, as will be appreciated by those skilled in the hardware art(s). For example, the functionality of one or more of the components of the exemplary embodiments can be implemented via one or more hardware devices. The exemplary embodiments can store information relating to various processes described herein. This information can be stored in one or more memories, such as a hard disk, optical disk, magneto-optical disk, RAM, and the like. One or more databases can store the information used to implement the exemplary embodiments of the present inventions. The databases can be organized using data structures (e.g., records, tables, arrays, fields, graphs, trees, lists, and the like) included in one or more memories or storage devices listed herein. The processes described with respect to the exemplary embodiments can include appropriate data structures for storing data collected and/or generated by the processes of the devices and subsystems of the exemplary embodiments in one or more databases. All or a portion of the exemplary embodiments can be implemented by the preparation of application-specific integrated circuits or by interconnecting an appropriate network of conventional component circuits, as will be appreciated by those skilled in the electrical art(s). As stated above, the components of the exemplary embodiments can include computer readable medium or memories according to the teachings of the present inventions and for holding data structures, tables, records, and/or other data described herein. Computer readable medium can include any suitable medium that participates in providing instructions to a processor for execution. Such a medium can take many forms, including but not limited to, non-volatile media, volatile media, transmission media, and the like. Non-volatile media can include, for example, optical or magnetic disks, magneto-optical disks, and the like. Volatile media can include dynamic memories, and the like. Transmission media can include coaxial cables, copper wire, fiber optics, and the like. Transmission media also can take the form of acoustic, optical, electromagnetic waves, and the like, such as those generated during radio frequency (RF) communications, infrared (IR) data communications, and the like. Common forms of computer-readable media can include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other suitable magnetic medium, a CD-ROM, CDRW, DVD, any other suitable optical medium, punch cards, paper tape, optical mark sheets, any other suitable physical medium with patterns of holes or other optically recognizable indicia, a RAM, a PROM, an EPROM, a FLASH-EPROM, any other suitable memory chip or cartridge, a carrier wave or any other suitable medium from which a computer can read. While the present inventions have been described in connection with a number of exemplary embodiments, and implementations, the present inventions are not so limited, but rather cover various modifications, and equivalent arrangements, which fall within the purview of prospective claims.	G	60G06	161G06F	12	10
11958072	US20090089750A1-20090402	METHOD AND SYSTEM OF PERFORMING JAVA LANGUAGE CLASS EXTENSIONS	ACCEPTED	20090318	20090402	[]	G06F944	["G06F944"]	8381177	20071217	20130219	717	108000	97593.0	MAMO	ELIAS	[{"inventor_name_last": "Cabillic", "inventor_name_first": "Gilbert", "inventor_city": "Brece", "inventor_state": "", "inventor_country": "FR"}, {"inventor_name_last": "Lesot", "inventor_name_first": "Jean-Philippe", "inventor_city": "Argentre du Plessis", "inventor_state": "", "inventor_country": "FR"}]	A method and system of performing Java language class extensions. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to identify a first class having a first name, and create a second class based on the first class (the second class is an abstract view of the first class, and the second class has a second name equal to a third name of a third class).	1. A computer-readable medium storing a program that, when executed by a processor of a host system, causes the processor to: identify a first class having a first name; and create a second class based on the first class, wherein the second class is an abstract view of the first class, and wherein the second class has a second name equal to a third name of a third class. 2. The computer-readable medium according to claim 1 wherein the program further causes the processor to filter the first class, wherein the filtering is based on a set of annotations. 3. The computer-readable medium according to claim 1 wherein the program further causes the processor to filter the first class, wherein the filtering is based on at least one selected from the group consisting of: extensible markup language files; or a dedicated application programming interface. 4. The computer-readable medium according to claim 1 wherein the program further causes the processor to create the second class, wherein the second class is comprised within a filtered view. 5. The computer-readable medium according to claim 4 wherein the program further causes the processor to create the second class, wherein the second class is accessible to software applications based on being comprised within the filtered view. 6. The computer-readable medium according to claim 1 wherein the program further causes the processor to create the second class, wherein the second class has a different name than the first name of the first class. 7. The computer-readable medium according to claim 1 wherein the program further causes the processor to create the second class, wherein the second class is a global class, wherein the first class is a local class, and wherein the third class is a local class. 8. The computer-readable medium according to claim 1 wherein the program further causes the processor to filter one or more from the group consisting of: the first class; a field; and a method, and wherein the filtering changes one or more from the group consisting of: a name; and a visibility. 9. A computer system comprising: a processor that executes bytecodes; and a memory coupled to the processor; wherein the processor identifies a first class having a first name; and wherein the processor creates a second class based on the first class, wherein the second class is an abstract view of the first class, and wherein the second class has a second name equal to a third name of a third class. 10. The computer system according to claim 9 further comprising wherein the processor executes a class loader, wherein the class loader identifies the first class. 11. The computer system according to claim 9 further comprising wherein the processor executes a class loader, wherein the class loader filters the first class. 12. The computer system according to claim 9 further comprising wherein the processor executes a class loader, wherein the class loader creates the second class. 13. The computer system according to claim 9 further comprising wherein the processor executes a class loader, wherein the class loader provides classes to an application at runtime by way of the second class. 14. The computer system according to claim 9 further comprising wherein the processor creates the second class, wherein the processor creates the second class based on a set of annotations. 15. The computer system according to claim 9 further comprising wherein the processor creates the second class, wherein the processor creates the second class based on at least one selected from the group consisting of: extensible markup language files; or a dedicated application programming interface. 16. The computer system according to claim 9 further comprising wherein the processor creates the second class, wherein the second class is comprised within a filtered view. 17. The computer system according to claim 16 further comprising wherein the processor creates the second class, wherein the second class is accessible to software applications based on being comprised within the filtered view. 18. The computer system according to claim 9 further comprising wherein the processor creates the second class, wherein the second class is a global class, wherein the first class is a local class, and wherein the third class is a local class. 19. The computer system according to claim 9 wherein the processor filters the first class. 20. The computer system according to claim 9 further comprising wherein the processor filters one or more from the group consisting of: the first class; a field; and a method, and wherein the filtering changes one or more from the group consisting of: a name; and a visibility.	<SOH> BACKGROUND <EOH>Java™ is a programming language that, at the source code level, is similar to object oriented programming languages such as C++. Java language source code is compiled into an intermediate representation based on a plurality of “bytecodes” that define specific actions. In some implementations, the bytecodes are further compiled to machine language for a particular processor. In order to speed the execution of Java language programs, some processors are specifically designed to execute some of the Java bytecodes directly. Many times, a processor that directly executes Java bytecodes is paired with a general purpose processor to accelerate Java program execution. To aid in the programming of Java, groups of related classes are bundled into class libraries, which are also referred to as a packages. Among other uses, packages enable efficient code reusability. A Java Application Programming Interface (API) comprises a plurality of such packages. One exemplary package, the Java language package (java.lang), comprises Java classes such as the object class (java.lang.object) that correspond to a set of classes that enable the execution of Java bytecodes. The Java language classes are provided by the Java API and are unique within any given Java platform. Stated otherwise, each Java API is targeted to only one configuration of a Java Virtual Machine (JVM). It would be desirable to define a methodology that would allow at least some JVM compatibility to any API configuration.	<SOH> SUMMARY <EOH>The problems noted above are solved in large part by a method and system of performing Java language class extensions. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to identify a first class having a first name, and create a second class based on the first class (the second class is an abstract view of the first class, and the second class has a second name equal to a third name of a third class). Other illustrative embodiments are computer systems comprising a processor that executes bytecodes and a memory coupled to the processor. The processor identifies a first class having a first name. The processor creates a second class based on the first class (the second class is an abstract view of the first class, and the second class has a second name equal to a third name of a third class).	CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to EP Application No. 07291168.8, filed on Sep. 28, 2007, hereby incorporated herein by reference. BACKGROUND Java™ is a programming language that, at the source code level, is similar to object oriented programming languages such as C++. Java language source code is compiled into an intermediate representation based on a plurality of “bytecodes” that define specific actions. In some implementations, the bytecodes are further compiled to machine language for a particular processor. In order to speed the execution of Java language programs, some processors are specifically designed to execute some of the Java bytecodes directly. Many times, a processor that directly executes Java bytecodes is paired with a general purpose processor to accelerate Java program execution. To aid in the programming of Java, groups of related classes are bundled into class libraries, which are also referred to as a packages. Among other uses, packages enable efficient code reusability. A Java Application Programming Interface (API) comprises a plurality of such packages. One exemplary package, the Java language package (java.lang), comprises Java classes such as the object class (java.lang.object) that correspond to a set of classes that enable the execution of Java bytecodes. The Java language classes are provided by the Java API and are unique within any given Java platform. Stated otherwise, each Java API is targeted to only one configuration of a Java Virtual Machine (JVM). It would be desirable to define a methodology that would allow at least some JVM compatibility to any API configuration. SUMMARY The problems noted above are solved in large part by a method and system of performing Java language class extensions. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to identify a first class having a first name, and create a second class based on the first class (the second class is an abstract view of the first class, and the second class has a second name equal to a third name of a third class). Other illustrative embodiments are computer systems comprising a processor that executes bytecodes and a memory coupled to the processor. The processor identifies a first class having a first name. The processor creates a second class based on the first class (the second class is an abstract view of the first class, and the second class has a second name equal to a third name of a third class). BRIEF DESCRIPTION OF THE DRAWINGS For a more detailed description of the various embodiments, reference will now be made to the accompanying drawings, wherein: FIG. 1 illustrates a diagram of a system in accordance with embodiments comprising a Java Stack Machine (JSM); FIG. 2 illustrates a first system in accordance with some embodiments of the invention; FIG. 3 illustrates a method of filtering a class in accordance with embodiments of the invention; FIG. 4 illustrates a second system in accordance with embodiments of the invention; FIG. 5 illustrates a method in accordance with embodiments of the invention; and FIG. 6 illustrates a system in accordance with at least some embodiments of the invention. NOTATION AND NOMENCLATURE Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. DETAILED DESCRIPTION The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment. FIG. 1 illustrates a system 100 in accordance with at least some embodiments. In particular, the system 100 comprises at least one processor 102. Processor 102 is referred to for purposes of this disclosure as a Java Stack Machine (“JSM”) 102. The JSM 102 comprises an interface to one or more input/output (“I/O”) devices such as a keypad to permit a user to control various aspects of the system 100. In addition, data streams may be received from the I/O space into the JSM 102 to be processed by the JSM 102. Optional processor 104 may be referred to as a Micro-Processor Unit (“MPU”). System 100 may also comprise memory 106 coupled to both the JSM 102 and MPU 104 and thus accessible by both processors. A portion of the memory 106 may be shared by both processors, and if desired, other portions of the memory 106 may be designated as private to one processor or the other. The memory 106 may be further coupled to a display 114. System 100 also comprises a Java virtual machine (JVM) 124. The JVM 124 may comprise an Application Programming Interface implementation (API) 108 and a Java Virtual Processor (JVP) 118 (discussed more below). The API implementation 108 comprises a resource manager 120 and a configuration 122. The resource manager 120 manages resource sharing between multiple threads and/or applications running on the system 100. The configuration 122 provides applications with an API, which API is used to access base functionalities of the system. The JVP 118 may comprise a combination of software and hardware. The software may comprise a compiler 110 and a JSM Execution Kernel (JEK) 116. The JEK 116 comprises software that is executable within the JSM 102, such as a class loader, bytecode verifier, garbage collector, and firmware to interpret the bytecodes that are not directly executed on the JSM processor 102. Thus, the hardware of the JVP 118 may comprise the JSM 102. The JVP 118 provides a layer of abstraction between the API 108 and a physical hardware platform (e.g., JSM 102) that executes Java bytecodes. Other components may be present as well. Java language source code is converted or compiled to a series of bytecodes 112, with each individual one of the bytecodes referred to as an “opcode.” Bytecodes 112 may be provided to the JEK 116, possibly compiled by compiler 110, and provided to the JSM 102. When appropriate, the JVP 118 may direct some method execution to the MPU 104. The MPU 104 also may execute non-Java instructions. For example, the MPU 104 may host an operating system (O/S) which performs various functions such as system memory management, system task management and most or all other native tasks running on the system, management of the display 114, and receiving input from input devices. Java code, executed on the JVP 118, may be used to perform any one of a variety of applications such as multimedia, games or web based applications in the system 100, while non-Java code, which may comprise the O/S and other native applications, may run on the MPU 104. As discussed above, the JVP 118 provides a layer of abstraction. In particular, the JVP 118 is a virtual hardware platform that is compatible with any Java API, any real hardware/software platform that may comprise a JSM processor, or any JVM implementation. In some exemplary embodiments, the JVP 118 comprises a JEK core that has an execution engine, a memory management component, and a compiler. The execution engine may comprise a Bytecode engine, a class loader, a notification manager, and an external method interface. The memory management component may comprise a memory allocator, an object mapper for physically constrained objects, a garbage collector, a memory defragmentor, and a swapper. The compiler may comprise a dynamic compiler and provide code buffer management. The JEK core may also comprise firmware to facilitate the execution of Java Bytecodes on the JSM processor. The JVP 118 also provides the API 108 with methods to create software class loaders. A class loader loads classes used by an application at runtime. Other hardware components of the hardware platform or software components are virtualized within the JEK 116 as Java Virtual Devices (JVD) that communicate with the JEK core. Each JVD comprises some combination of fields, methods, and notifications. The fields may comprise standard Java fields or may be mapped to a predefined or constrained physical memory space, wherein the constraint may be due to hardware or software. The fields may also comprise a map to indirect memories. The methods may comprise standard bytecodes or may comprises JSM native code, hardware instructions, or may use any kind of native interface such as a Java Native Interface (JNI) or a KVM Native Interface (KNI). The notifications may be initiated by an event, for example, a hardware interrupt, or from software. Additionally, the JEK core manages native interface links and the notification mechanism provides a way to implement flexible monitoring. To aid in the programming of Java, groups of related classes are bundled into class libraries, which are also referred to as a packages. Among other uses, packages enable efficient code reusability. The Java API comprises a plurality of such packages. One exemplary package, the Java language package (java.lang), comprises Java classes such as the object class (java.lang.object) that correspond to a set of classes that enable the execution of Java bytecodes. Classes may define attributes and behaviors. Behaviors are referred to as methods, and classes may comprise one or more methods that define all the behaviors available within a given class. For example, methods may request performing of an action such as setting a value, returning a value, or writing to a file. The object class (java.lang.object) is at the top of the class hierarchy, and every other class inherits (either directly or indirectly) attributes and methods from the object class. In other words, the object class is a superclass for all other classes in a given Java system. FIG. 2 illustrates a system 200 that comprises a Java API 212 and a JVP 214. The API 212 comprises at least one class loader that loads classes used at runtime by Java applications 210. One exemplary class loaded by one of the class loaders of the API 212 is the object class 216 of the Java language package. As discussed above, the JVP 214 comprises the JSM and the JEK. The JVP 214 also comprises at least one class loader that may be used to load classes at runtime. In embodiments of the present invention, the JEK realizes its own limited Java API configuration (that can be used to execute itself). Thus, one of the JVP 214 class loaders has the capability to load its own object class 218 by way of the JEK. However, the object class 218 to be loaded by the JVP 214 is not necessarily the same object class 216 that the API 212 class loader provides to the applications 210 during program execution. In effect, there could be two different “local” versions (that may have the same name) of the object class (or any other class such as those classes of the Java language package). This raises a potential conflict since language classes are unique within any given Java system. To avoid this potential conflict, a class loader may filter classes (as discussed below) belonging to the Java language package such as the object class (java.lang.object). In some embodiments, the class loader may filter classes belonging to other distinct Java packages. The result of the filtering is that a new class (such as a new object class) is created (which is an abstract view of an already existing class), and conflicts can be avoided while the JVP 214 maintains compatibility with any Java API 212. Through the process of filtering, a class loader may abstract the “view” of an existing class, where the view is defined as the manner in which a Java application sees (or handles) a particular Java class. FIG. 3 illustrates a method of filtering a class by way of a class loader. In particular, the class loader may define a new filtered class as a “filtered view” of another already defined class. In some exemplary embodiments, the class loader performing the filtering is implemented by the JVP. As shown in FIG. 3A, a class loader 308 retrieves a class 304 and passes it through a filter 306, resulting in a filtered class 310. The area indicated by arrows 312 may be referred to as the “view”, and the area indicated by arrows 314 may be referred to as the “filtered view”. Thus, the filtering of a class 304 creates a filtered class 310 which is a filtered view of the unfiltered class 304. In some embodiments the filtering may be accomplished by a set of Java annotations (i.e., a set of modifiers), where the annotations may be applied to a class, a class member, or a method parameter in order to modify its top level view. An example of an annotation is a “name” annotation, which allows for the renaming of a class, field, or a method. Thus, a filtered class may be a renamed version of an unfiltered class, where the filtered class has a “filtered name”. Classes, fields, or methods that do not have a name annotation keep their original name. Another example of an annotation is a “visibility” annotation, which allows changing the visibility of a class, field, or a method. For example, in embodiments of the present invention, only classes that have an appropriate visibility annotation will be available to Java applications during runtime. Classes, fields, or methods that do not have a visibility annotation are by default considered to be invisible with respect to the Java applications and to the filtered classes. In other words, only classes within the filtered view 314 are accessible (i.e., visible) to the Java applications and to other filtered classes. The filtering process in not restricted to renaming or changing the visibility of an individual or group of classes, fields, or methods. In some embodiments, other distinct modifiers can be applied to any individual or group of classes, fields, or methods. In addition, the filtering process is not restricted to Java annotations. For instance, in alternative embodiments, filtering may be accomplished by way of extensible markup language (XML) files or a dedicated JVP API. FIG. 3B illustrates a method similar to that of FIG. 3A, where the class loader 308 retrieves and filters the class 304 resulting in a filtered class 310. However, in FIG. 3B, the filter 306 is comprised within the class loader 308. FIG. 4 illustrates a system 400 which implements a view abstraction method based on class filtering of the various embodiments. The system 400 comprises a Java API 412, and a JVP 414 which comprises the JSM and the JEK. The API 412 comprises at least one class loader that loads classes used at runtime by Java applications 410. The JVP 414 also comprises at least one class loader that may be used to load classes at runtime. Consider again the object class (java.lang.object), where the Java applications 410 and the JVP 414 each use their own “local” versions of the object class. In particular, the JVP 414 defines object class 418 that is used by both the API 412 and the JVP 414. The API 412 also uses object class 416 to define a filtered object class 420 (discussed below) that is used by the Java applications 410. In other embodiments, the Java applications 410 or the JVP 414 may use any other class such as those classes of the Java language package. In any case, having two different versions of the same class with the same name (e.g., two versions of the object class java.lang.object) poses a potential conflict since language classes are unique within any given Java system. The view abstraction method carried out by the system 400 of FIG. 4 may be implemented according to various embodiments. In some exemplary embodiments, the object class 416 is programmed with a name such as myconf.lang.object prior to runtime. As described with reference to FIG. 3, the class loader of the JVP 414 retrieves and filters the class myconf.lang.object (i.e., the object class 416) such that a new filtered class 420 is created, where the filtered class 420 is a filtered view (i.e., an abstract view) of myconf.lang.object (i.e., the object class 416) of the API 412. The filtering process may also perform a renaming such that the filtered class 420 has a different name than the object class 416 from which it was derived. In the present example, the filtered class 420 is named “java.lang.object” while the unfiltered object class 416 retains its original name of “myconf.lang.object”. Moreover, the filtering process may change the visibility of a class. For example, the applications 410 may access (i.e., view) the renamed, filtered class 420 (java.lang.object) based on appropriate visibility annotations that have been applied during the filtering process. Java.lang.object (object class 418) remains as the only “real” language class; however, the object class 418 remains invisible to the Java applications 410 since classes that do not have a visibility annotation are by default considered to be invisible with respect to the Java applications 410 as well as to the filtered class 420 (as discussed above). In addition, the object class 416 remains invisible to the Java applications 410 since it remains within the unfiltered view (i.e., view 312 of FIG. 3). Thus, by this filtering method, the object class 416 (myconf.lang.object) that the API 412 intended to provide to the applications 410 is still provided by way of the filtered class 420. Additionally, potential conflicts with the object class 418 (java.lang.object) are avoided. In some exemplary embodiments, following a similar view abstraction method as described with respect to FIG. 4, the object class 418 of the JVP 414 may be provided to the applications 410 by way of the filtered class 420. For purposes of this disclosure, the filtered class 420 may be referred to as a “global” class. The term global here does not mean that the filtered class 420 may be accessed across an entire Java system such as system 400 (in fact, the filtered class 420 is only visible to the applications 410). Rather, the term global is used to describe the fact that the abstract filtered class 420 can be used to provide (to the applications 410) any of a plurality of classes from the API 412 or from the JVP 414 while avoiding potential conflicts (e.g., with the object class 418). The filtered class 420 is not a new class. Rather, the filtered class 420 is an abstract view of the object class 416, as discussed above. Consequently, an instance of the object class 416 is “compatible” with an instance of the filtered class 420, where compatible is defined as having the same structure in memory (e.g., the same fields at the same offset). For example, in FIG. 4, an instance of the object class 416 is viewed in the API 412 as an instance of the object class 416, and the same instance of the object class 416 is viewed in the Java applications 410 as an instance of the filtered class 420. Thus, an instance of the object class 416 created in API 412 could be passed to the Java applications 410 or an instance of the filtered class 420 created in the Java applications 410 could be passed to the API 412. There is no overhead at runtime to access fields or invoke methods of an instance of the object class 416 in the API 412 nor in the Java applications 410. The filtered class 420 remains a pure abstract view of the object class 416, which describes the instance and remains as a real class. FIG. 5 illustrates a method (e.g., software) in accordance with some embodiments. In particular, the process starts (block 510) and proceeds to identify a first Java class having a first name (block 512). The first Java class may be an object class or any other class such as those classes of the Java language package. The first Java class is then filtered (block 514). The filtering is based on a set of annotations, extensible markup language (XML) files, or a dedicated application programming interface. The process then proceeds to create a second Java class based on the filtered first Java class (block 516). The second Java class is an abstract view of the first Java class, and has a second name equal to a third name of a third Java class. In some exemplary embodiments, the second name may be different than the third name. The second name is also different than the first name of the first Java class. The second Java class is also accessible (i.e., viewable) to Java applications based on the second Java class being comprised within a filtered view (area indicated by arrows 314 of FIG. 3). Furthermore, the second Java class is a “global” class (as described above), and the first Java class and the third Java class are both local classes. Also, since the first Java class and the third Java class are not comprised within the filtered view, they are not directly accessible to the Java applications. The process then ends (block 518). System 100 (FIG. 1) may be implemented as a mobile cell phone such as that shown in FIG. 6. As shown, the mobile communication device has an outer enclosure 615 and includes an integrated keypad 612 and display 614. The JSM processor 102 and MPU processor 104 and other components may be included in electronics package 610 connected to the keypad 612, display 614, and radio frequency (RF) circuitry 616. The RF circuitry 616 may be connected to an antenna 618. From the description provided herein, those skilled in the art are readily able to combine software created as described with appropriate general purpose or a special purpose computer hardware to create a computer system and/or computer subcomponents embodying aspects of the invention, to create a computer system and/or computer subcomponents for carrying out the method embodiments of the invention, and/or to create a computer-readable medium storing a software program to implement method aspects of the various embodiments. Moreover, the embodiments of the illustrative methods could be implemented together in a single program (with various subroutines), or split up into two or more programs executed on the processor. While various embodiments of the invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are illustrative only, and are not intended to be limiting. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.	G	60G06	161G06F	9	44
11785880	US20070187825A1-20070816	Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument	ACCEPTED	20070801	20070816	[]	H01L2348	["H01L2348"]	7307351	20070420	20071211	257	784000	79459.0	MANDALA	VICTOR	[{"inventor_name_last": "Hashimoto", "inventor_name_first": "Nobuaki", "inventor_city": "Suwa-shi", "inventor_state": "", "inventor_country": "JP"}]	The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provided on the semiconductor chip (12), and a stress transmission portion (22) for transmitting stress from the solder ball (20) to the stress relieving layer (16) in a peripheral position of an electrical connection portion (24a) of the solder ball (20) and wiring (18).	1. An electronic component, comprising: a semiconductor chip; an electrode disposed on the semiconductor chip; a wiring electrically connected to the electrode, the wiring disposed on the semiconductor chip; a first resin layer formed over the semiconductor chip and the wiring, the first resin layer having an opening on a first portion of the wiring; and an external terminal provided above the first portion of the wiring, the external terminal electrically connected to the wiring via the opening, wherein a second portion of the wiring between the electrode and the external terminal extends in a direction that changes in a horizontal plane on the semiconductor chip, wherein the wiring extends from the first portion of the wiring in a direction perpendicular to a direction of stress generated by differences in a coefficient of thermal expansion between a mounting board and the electronic component when the electronic component is bonded to the mounting board.	<SOH> BACKGROUND ART <EOH>To pursue high density mounting in semiconductor devices, bare chip mounting is the ideal. However, quality control and handling of bare chips are difficult. For this reason, CSP (chip size/scale package) technology, in which the package size is close to the chip size, has been developed. In such a CSP semiconductor device, an important problem is to relieve the thermal stress due to the differences in coefficient of thermal expansion between the semiconductor chip and the mounting board. In particular, as the number of pins continues to increase, it is essential that no wiring breaks are caused by thermal stress, since wiring is required to connect from the electrodes to the solder balls. The present invention addresses the above described problems, and has as its object the provision of an electronic component, a semiconductor device, methods of manufacturing these, a circuit board on which these are mounted, and an electronic instrument having this circuit board.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 shows a first embodiment of the semiconductor device. FIG. 2 shows a second embodiment of the semiconductor device. FIG. 3 shows a third embodiment of the semiconductor device. FIGS. 4A and 4B shows a fourth embodiment of the semiconductor device. FIG. 5 shows a fifth embodiment of the semiconductor device. FIG. 6 shows a sixth embodiment of the semiconductor device. FIG. 7 shows a seventh embodiment of the semiconductor device. FIG. 8 shows an eighth embodiment of the semiconductor device. FIG. 9 shows a ninth embodiment of the semiconductor device. FIG. 10 shows a tenth embodiment of the semiconductor device. FIGS. 11A and 11B show an eleventh embodiment of the semiconductor device. FIGS. 12A and 12B show a twelfth embodiment of the semiconductor device. FIG. 13 shows a thirteenth embodiment of the semiconductor device. FIG. 14 shows a fourteenth embodiment of the semiconductor device. FIG. 15 shows a fifteenth embodiment of the semiconductor device. FIG. 16 shows a sixteenth embodiment of the semiconductor device. FIGS. 17A to 17 E show a process of fabricating the semiconductor device of the present invention. FIGS. 18A to 18 C show a process of fabricating the semiconductor device of the present invention. FIG. 19 shows a CSP semiconductor device. FIG. 20 shows a circuit board mounted with a semiconductor device fabricated by application of the method of the present invention. FIG. 21 snows an electronic instrument equipped with a circuit board mounted with a semiconductor device fabricated by application of the method of the present invention. detailed-description description="Detailed Description" end="lead"?	This is a Continuation of application Ser. No. 10/331,510 filed Dec. 31, 2002, which is a Continuation of application Ser. No. 09/953,858 filed Sep. 18, 2001, which is a Continuation of application Ser. No. 09/142,856 filed Mar. 26, 1999 which is a National Stage of PCT/JP98/00130 filed Jan. 16, 1998. TECHNICAL FIELD The present invention relates to a compact electronic component and a semiconductor device whose final formed package size is close to the size of the chip (semiconductor element), to methods of manufacturing these, to a circuit board on which these are mounted, and to an electronic instrument having this circuit board. BACKGROUND ART To pursue high density mounting in semiconductor devices, bare chip mounting is the ideal. However, quality control and handling of bare chips are difficult. For this reason, CSP (chip size/scale package) technology, in which the package size is close to the chip size, has been developed. In such a CSP semiconductor device, an important problem is to relieve the thermal stress due to the differences in coefficient of thermal expansion between the semiconductor chip and the mounting board. In particular, as the number of pins continues to increase, it is essential that no wiring breaks are caused by thermal stress, since wiring is required to connect from the electrodes to the solder balls. The present invention addresses the above described problems, and has as its object the provision of an electronic component, a semiconductor device, methods of manufacturing these, a circuit board on which these are mounted, and an electronic instrument having this circuit board. DISCLOSURE OF THE INVENTION The semiconductor device of the present invention comprises a semiconductor element, an external electrode provided within the region of the semiconductor element for external connection, wiring connected through a connection portion to the external electrode and electrically connecting the semiconductor element and the external electrode, a stress relieving portion provided on the semiconductor element, and a stress transmission portion transmitting stress from the external electrode to the stress relieving portion. Since the semiconductor element and external electrode of the present invention are connected by the wiring, the pitch of external electrode can be converted as required. The stress transmission portion transmits stress from the external electrode to the stress relieving portion, and stress can be thus relieved. The wiring is connected to the external electrode through a connection portion. The connection portion is not restricted to the case of existing as a separate member between the wiring and the external electrode, but includes the case of being a part of at least one of the wiring and external electrode. The connection portion is not restricted to directly contacting at least one of the wiring and external electrode, but includes the case of not directly contacting either. That is to say, the connection portion of the present invention indicates at least a part of the member electrically connecting the wiring and external electrode. More specifically, the wiring may be provided on the stress relieving portion, and the stress transmission portion may be provided in the connection portion. By this means, since the wiring is provided on the stress relieving portion, the connection portion and stress transmission portion are provided on the stress relieving portion, and the stress from the external electrode is transmitted to the stress relieving portion. Alternatively, the wiring may be provided under the stress relieving portion, the connection portion may be provided to pass through the stress relieving portion, and the stress transmission portion may be formed on the stress relieving portion integrally with the connection portion. By this means, since the connection portion passes through the stress relieving portion, the connection portion does not transmit stress vertically to the stress relieving portion. In place of this, the stress transmission portion provided on the stress relieving portion transmits stress to the stress relieving portion. The stress relieving portion may be formed with a thickness to reach the stress transmission portion from the wiring. The stress relieving portion may have a groove formed outside of the stress transmission portion. By forming a groove, the stress relieving portion is more easily deformed, and stress from the stress transmission portion can be absorbed more easily. The stress relieving portion may have a space formed between a contact position on the wiring and a contact position under the stress transmission portion. By this means, the stress relieving portion is more easily able to, deform, and stress from the stress transmission portion can be absorbed more easily. A stress relieving portion having such a space may be formed with a thickness to reach the stress transmission portion from the wiring, and then may be etched from the outside of the stress transmission portion to underneath thereof. The present invention may further comprise a supplementary transmission portion provided at least between a root periphery of the external electrode and the stress relieving portion, and transmitting stress from the external electrode to the stress relieving portion. By means of the supplementary transmission portion, stress from the external electrode is transmitted to the stress relieving portion, and a concentration of stress between the external electrode and the stress transmission portion can be prevented. The supplementary transmission portion may be formed of a material capable of being used for the stress relieving portion. The stress relieving portion may include a first stress relieving layer and a second stress relieving layer formed on the first stress relieving layer; the wiring may be provided between the first and second stress relieving layers; the connection portion may be provided to penetrate the second stress relieving layer; and the stress transmission portion may be formed on the second stress relieving layer integrally with the connection portion. By this means, the connection Portion transmits stress in the vertical direction to the first stress relieving layer. Meanwhile, the stress transmission portion transmits stress to the second stress relieving layer. In this way, stress is relieved at two locations. The stress relieving portion may include a first stress relieving layer and a second stress relieving layer formed on the first stress relieving layer; the wiring may be provided between the first and second stress relieving layers; the connection portion may be provided to penetrate the second stress relieving layer; and the stress transmission portion may include a first transmission portion formed between the first and second stress relieving layers integrally with the connection portion, and a second transmission portion formed on the second stress relieving layer integrally with the connection portion. The connection portion transmits stress in the vertical direction to the first stress relieving layer. Stress is also transmitted to the first stress relieving layer from the first transmission portion of the stress transmission portion. Furthermore, the stress transmission portion has a second stress transmission portion, and this second stress transmission portion transmits stress to the second stress relieving layer. In this way, stress is relieved at three locations. It is preferable that the second transmission Portion has a larger area than the first transmission portion, and transmits the stress to the second stress relieving layer. Since the second transmission portion transmits a large amount of stress, the stress transmitted by the first transmission portion is comparatively small. The first transmission portion is close to the direct contact portion of the connection portion and wiring. Therefore, by reducing the stress transmitted from the first transmission portion, the effect on this contact portion can be reduced. It is preferable that the stress transmission portion is provided without contacting the connection portion. By this means, the stress transmission portion does not transfer stress to the direct contact portion of the connection portion and wiring. The stress relieving portion may have an isolation portion for inhibiting transmission of the stress between a support region supporting the stress transmission portion and a connection region in which the connection portion is formed. Because the isolation portion is provided, stress transmitted from the stress transmission portion to the support region of the stress relieving portion is not transmitted to the connection region. Therefore, transfer of stress from the stress transmission portion through the stress relieving portion to the connection portion also does not occur. Here, the isolation portion may for example be a groove. The wiring preferably has a bent portion forming an empty portion with the semiconductor element. By this means, since the wiring can freely deform in the bent portion, maximum stress absorption is possible. A gel material may be injected in the empty portion to protect the bent portion. The stress relieving portion may include a first stress relieving layer and a second stress relieving layer formed on the first stress relieving layer; the wiring may include a first wiring portion formed below the first stress relieving layer and a second wiring portion formed between the first and second stress relieving layers; the connection portion may include a first wiring connection portion penetrating the first stress relieving is layer and connecting the first and second wiring portions and a second wiring connection portion penetrating the second stress relieving layer and connecting the external electrode and the second wiring portion; the first and second wiring connection portions may be disposed on different planes; and the stress transmission portion may include a first transmission portion formed between the first and second stress relieving layers integrally with the first wiring connection portion, and a second transmission portion formed on the second stress relieving layer integrally with the second wiring connection portion. Since the first and second wiring connection portions of the present invention are provided with first and second transmission portions respectively, in each of the wiring connection portions, stress can be transmitted to the stress relieving layer. The contact position of the first wiring connection portion with respect to the first and second wiring portions, and the contact position of the second wiring connection portion with respect to the external electrode and second wiring portion are disposed on different planes. Therefore, stress applied to one of the contact positions is not directly easily transferred to the other contact position. Since stress transferred from the external electrode is relieved before reaching the semiconductor element, the effect on this semiconductor element can be reduced. The wiring may be brought out from the external electrode substantially at right angles to a direction of generation of the stress. By this means, the generating direction of the stress and the extending direction of the wiring are substantially orthogonal. Thus the application of tension to the wiring in the direction of its extension and consequent wiring breaks can be prevented. The stress transmission portion may be formed at a position outside of the connection portion. Since the stress transmission portion is transmitting stress at a peripheral position of the connection portion of the external electrode and wiring, stress can be transmitted over a large area. The electronic component of the present invention comprises an electronic element; an external electrode for external connection; wiring electrically connecting the electronic element and the external electrode; a stress reliving portion provided on the electronic element; and a stress transmission portion transmitting stress from the external electrode to the stress relieving portion, at a peripheral Position of an electrical connection portion of the external electrode and the wiring. The method of manufacturing an electronic component of the present invention comprises: a step of integrally forming in substrate form a plurality of electronic element; a step of forming an electrode on the electronic element in substrate form; a step of providing a stress relieving portion on the electronic element in substrate form, avoiding the electrode; a step of forming wiring from the electrode; a step of providing a stress transmission portion transmitting stress from the external electrode to the stress relieving portion, in a peripheral position of the electrical connection portion of the wiring and external electrode; and a step of separating the electronic element in substrate form into individual elements. The method of manufacturing a semiconductor device of the present invention comprises; a step of forming an electrode on a wafer; a step of providing a stress relieving portion on the wafer avoiding the electrode; a stop of forming wiring from the electrode; a step of providing a stress transmission portion transmitting stress from the external electrode to the stress relieving portion, in a peripheral position of the electrical connection portion of the wiring and external electrode; and a step of separating the wafer into individual elements. With an aspect of the present invention, after a stress relieving layer, wiring, and external electrode are formed on the wafer, the wafer is cut up to obtain individual semiconductor devices. Therefore, since the formation of stress relieving layer, wiring, and external electrode can be carried out simultaneously for a large number of semiconductor devices, the fabrication process can be simplified. The step of forming a stress relieving portion may be carried out after the step of forming wiring; and a step of forming a groove by etching in the stress relieving portion outside of the stress transmission portion may be performed before the step of separating the wafer. By forming the groove, the stress relieving portion is more easily deformed, and stress from the stress transmission portion can be absorbed more easily. The step of forming the stress relieving portion may be carried out after the step of forming wiring; and a step of etching the stress relieving portion to under the stress transmission portion may be performed before the step of separating the wafer. By this means, the stress relieving portion has a space formed between a contact position over the wiring and a contact position under the stress transmission portion. Thus, the stress relieving portion is more easily deformed, and stress from the stress transmission portion can be absorbed more easily. A step of providing a material capable of being used for the stress receiving portion from over the stress relieving portion to at least a root periphery of the external electrode, to form a Supplementary transmission portion, may be performed before the step of separating the wafer. In this way, when the supplementary transmission portion is formed, stress from the external electrode is transmitted to the stress relieving portion by means of the supplementary transmission portion, and a concentration of stress between the external electrode and the stress transmission portion can be prevented. The circuit board of present invention has the above described semiconductor device and a substrate on which a desired wiring pattern is formed; and external electrodes of the semiconductor device are connected to the wiring pattern. The electronic instrument of the present invention has this circuit board. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a first embodiment of the semiconductor device. FIG. 2 shows a second embodiment of the semiconductor device. FIG. 3 shows a third embodiment of the semiconductor device. FIGS. 4A and 4B shows a fourth embodiment of the semiconductor device. FIG. 5 shows a fifth embodiment of the semiconductor device. FIG. 6 shows a sixth embodiment of the semiconductor device. FIG. 7 shows a seventh embodiment of the semiconductor device. FIG. 8 shows an eighth embodiment of the semiconductor device. FIG. 9 shows a ninth embodiment of the semiconductor device. FIG. 10 shows a tenth embodiment of the semiconductor device. FIGS. 11A and 11B show an eleventh embodiment of the semiconductor device. FIGS. 12A and 12B show a twelfth embodiment of the semiconductor device. FIG. 13 shows a thirteenth embodiment of the semiconductor device. FIG. 14 shows a fourteenth embodiment of the semiconductor device. FIG. 15 shows a fifteenth embodiment of the semiconductor device. FIG. 16 shows a sixteenth embodiment of the semiconductor device. FIGS. 17A to 17E show a process of fabricating the semiconductor device of the present invention. FIGS. 18A to 18C show a process of fabricating the semiconductor device of the present invention. FIG. 19 shows a CSP semiconductor device. FIG. 20 shows a circuit board mounted with a semiconductor device fabricated by application of the method of the present invention. FIG. 21 snows an electronic instrument equipped with a circuit board mounted with a semiconductor device fabricated by application of the method of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention is now described with reference to the drawings. The present invention can be applied to a compact electronic component, in particular the examples described are of application to a semiconductor device. Some of the drawings are enlarged for clarity. In particular the following explanation is in terms of a final separated individual semiconductor device, and therefore the terminology used, forms, and so forth, may be slightly different from in actual practice. Where a semiconductor chip is referred to, this may refer not only to a single separated device (that is, a chip) but also to devices in the form of a wafer. In other words, the term “semiconductor chip” used here refers to a certain circuit formed on a base substrate (for example of silicon) and capable of being used once separated, and is not restricted in respect of whether separated or whether still integral. Furthermore, references are restricted to typical locations where explanation is required such as wiring, and therefore in the figures where other locations are similar, or other constructions, are omitted. First Embodiment FIG. 1 is a sectional view showing a first embodiment of the semiconductor device. A semiconductor device 10 shown in this figure comprises a stress relieving layer 16 and wiring 18 formed thereon In more detail, on a semiconductor chip 12, a stress relieving layer 16 is formed to avoid an electrode 14, and wiring 18 is formed from the electrode 14 over the stress relieving layer 16. The stress relieving layer 16 is formed from a photosensitive polyimide resin, and when the semiconductor device 10 is mounted on a substrate (not shown in the drawings), relieves the stress created by the difference in the coefficient of thermal expansion between the semiconductor chip 12 and the substrate. The polyimide resin is insulating with respect to the wiring 18, is able to protect the surface a and has heat resistance when a solder ball. 20 is melted. A polyimide resin with a low Young's modulus (such as an olefin polyimide resin or BCB manufactured by the Dow Chemical Corporation) is preferably used, and in particular it is preferable that the Young's modulus be not more than about 20 kg/mm2. The stress relieving layer 16 has a larger stress relieving effect the thicker it is, but a thickness approximately in the range 1 to 100 μm is preferable. However, when a polyimide resin with a Young's modulus of approximately 10 kg/mm2 is used, a thickness of approximately 10 μm will be sufficient. Alternatively, a material which has a low Young's modulus and is effective for stress relieving such as, silicone denatured polyimide resin, epoxy resin, or silicone denatured epoxy resin may be used as the stress relieving layer 16. When a nonphotosensitive resin is used, in combination with another resist, a required pattern may be formed by a photo-etching process. The wiring 18 is formed of chromium (Cr). Here, chromium (Cr) is selected because of its good adhesion properties to the polyimide resin forming the stress relieving layer 16. Alternatively, when resistance to cracks is considered, ductile metal such as aluminum, aluminum alloys such as aluminum-silicon and aluminum-copper, copper alloys, copper, or gold may be used. Besides, when titanium or titanium-tungsten, having excellent resistance to moisture is selected, wiring breaks due to corrosion can be prevented. Titanium is also preferable as it has favorable adhesion properties with respect to polyimide. When titanium is used for the wiring 18, a multi-layer construction of titanium and another of the above metals may be used. The wiring 18 is formed in a film by sputtering, plating, a combination thereof, or another method, and is patterned by photoetching. It should be noted that the above described examples of materials for the stress relieving layer and wiring may equally be applied in a suitable way to all of the second and subsequent embodiments in the same way as to the first embodiment. On the wiring 18, a solder ball (external electrode) 20 is provided. In more detail, a stress transmission portion 22 is provided on the wiring 18, a base 24 is provided on this stress transmission portion 22, and a solder ball 20 is provided on the seat 24. The stress transmission portion 22 and base 24 are formed by copper plating, and the solder ball is formed of solder of at least a hemispherical ball shape. It should be noted that the stress transmission portion 22 and base 24 are preferably formed from the same metal as that Used for the material of the wiring 18. A characteristic of the present embodiment is that as shown in FIG. 1, the width d of the base portion 24a of the base 24 on the stress transmission portion 22 and the width D of the stress transmission portion 22 satisfy the relation d<D. In other words, the base portion 24a of the base 24 forms a part (connection portion) of the element electrically connecting the solder ball (external electrode) 20 and the wiring 18, and the stress transmission portion 22 extends integrally to the peripheral position thereof. By forming such a stress transmission portion 22, the solder ball 20 is supported on the stress relieving layer 16 with a is comparatively wide width D. Such the wide stress transmission portion 22 is effective for transmitting stress. That is to say, for example, when heat is applied to the substrate and the semiconductor device mounted on the substrate because of the difference in the coefficient of thermal expansion between the mounting board and the semiconductor chip 12, a stress of bending the semiconductor chip 12 is created. This stress is a force bending over, with the center of the solder ball 20 as-axis. According to the present embodiment, by means of the stress transmission portion 22 with the comparatively wide width D, the solder ball 20 is supported with respect to the stress relieving layer 16. Therefore, the stress tending to bend over the solder ball 20 is transmitted over a wide area to the stress relieving layer 16, and the stress can be largely absorbed by the stress relieving layer 16. Besides, with regard to the stress transmission effect, the second and subsequent embodiments are also similar to that shown in the first embodiment. It should be noted that while omitted from the drawings, to prevent corrosion and the like of the wiring a wiring protection layer such as solder resist is preferably provided as the outermost layer. Second Embodiment FIG. 2 is a sectional view showing a second embodiment of the semiconductor device. The semiconductor device 30 shown in this figure has wiring 38 formed beneath a stress relieving layer 36. In more-detail, on a semiconductor chip 32, with an oxide layer (not shown in the drawings) acting as an insulating layer interposed, wiring 38 is formed from an electrode 34. A stress relieving layer 36 is formed over this. It should be noted that the wiring 38 is formed of chromium (Cr). In the stress relieving layer 36, a hole 36a is formed by photolithography, so that in the region of this hole 36a the wiring 38 is not covered by the stress relieving layer 36. In other words, the hole 36a is formed so that the wiring 38 is positioned directly under the hole 36a. Then a chromium (Cr) layer 42 and a copper (Cu) layer 44 are formed by sputtering applied to the wiring 38 and the inner circumferential surface and opening rim surface forming the hole 36a. In other words, the chromium (Cr) layer 42 and copper (Cu) layer 44 are formed to pass through the stress relieving layer 36. Moreover, in the opening rim portion, the chromium (Cr) layer 42 and copper (Cu) layer 44 are arranged to extend with a comparatively wide width. On the copper (Cu) layer 44, a base 46 is formed of copper (Cu), and on this base 46, a solder ball 40 is formed. The solder ball 40 is electrically connected to the electrode 34 through the drawn out wiring 38, the copper (Cu) layer 44, the chromium (Cr) layer 42 and the base 46. According to the present embodiment, at the opening rim portion of the hole 36a, stress from the solder ball 40 is transmitted from a stress transmission portion 48 formed from at least a part of the chromium (Cr) layer 42, copper (Cu) layer 44 and base 46 to the stress relieving layer 36. This stress transmission portion 48 is positioned outside a connection portion 38a. The connection portion 38a is a part of the chromium (Cr) layer 42, and is a part of the member electrically connecting the solder ball (external electrode) 40 and wiring 38. In this example, the stress transmission portion 48 is provided to include a flange portion 48a, in other words, a projecting portion. Therefore, the stress acting to bend over with the center of the solder ball 40 as axis can be transmitted over a wide area to the stress relieving layer 36 by the stress transmission portion 48. The larger the area of the stress transmission portion 48, the more effective it is. Besides, according to the present embodiment, since the stress transmission portion 48 Is disposed at a different height from the connection portion 38a with respect to the wiring 38, and the connection portion 38a and wiring 38 are disposed on a hard oxide layer, the stress generated is absorbed by the stress relieving layer 36. Therefore, stress is less likely to be transmitted to the connection portion 38a, and to the wiring 38, and as a result cracks can be prevented. Third Embodiment FIG. 3 is a sectional view showing a third embodiment of the semiconductor device. The semiconductor device 31 shown in this figure has a supplementary transmission layer 33 formed on the stress relieving layer 36 of the semiconductor device 30 shown in FIG. 2. In the present embodiment also, the connection portion 38a is a part of the chromium (Cr) layer 42, and is a part of the member electrically connecting the solder ball (external electrode) 40 and wiring 38. The supplementary transmission layer 33 is formed in contact with, at least, the root periphery of the solder ball 40. Therefore, through the supplementary transmission layer 33, stress is transmitted from the solder ball 40 to the stress relieving layer 36. By this means, the stress is dispersed, and between the solder ball 40 and the stress transmission portion 48, in particular at the connecting portion of the base 46 with the copper (Cu) layer 44, a concentration of stress is avoided. It should be noted that here, the stress transmission portion 48 is formed from at least a part of the chromium (Cr) layer 42, copper (Cu) layer 44 and base 46. The supplementary transmission layer 33 is constructed of a resin capable of being used for the stress relieving layer 36, and its thickness is determined by the flexibility (Young's modulus) of the resin itself, and the magnitude of the stress which it is required to be transmitted. More specifically, when a soft resin is used, a large stress transmission is possible by forming the supplementary transmission layer 33 with greater thickness. Besides, when a comparatively hard resin is used, by forming the supplementary transmission layer 33 to be thin, excessive stress transmission can be avoided. The supplementary transmission layer 33 can be formed by spin coating after formation of the solder ball 40. Alternatively, after formation of the stress transmission portion 48 (including the base 46), and before forming the solder ball 40, a resin layer may be formed on the stress relieving layer 36, an opening formed in the resin layer on the stress transmission portion 48, and the solder ball 40 provided. In this case, the opening can be formed by the application of a photolithography technique, or an etching technique (dry or wet). These methods are suitable when the supplementary transmission layer 33 is formed before cutting the semiconductor device into individual pieces. Fourth Embodiment FIGS. 4A and 4B are sectional views showing a fourth embodiment of the semiconductor device. It should be noted that FIG. 4A is a section along the line IV-IV in FIG. 4B. The semiconductor device 37 shown in these figures has grooves 35 formed in the stress relieving layer 36 of the semiconductor device 30 shown in FIG. 2. However, FIGS. 2 and 4A differ in the section position. In the present embodiment again, the connection portion 38a is a part of the member electrically connecting the solder ball (external electrode) 40 and wiring 38 (see FIG. 2). As shown in FIGS. 4A and 4B, the grooves 35 are formed positioned on the outside of the stress transmission portion 48 in the stress relieving layer 36. By this means, when stress is transmitted from the stress transmission portion 48 to the stress relieving layer 36, the stress relieving layer 36 can more easily deform at a portion closer to the stress transmission portion 48 than the grooves 35. By means of this, the stress relieving layer 36 can more easily absorb stress. In particular, by forming the grooves 35 when the material forming the stress absorption layer 36 has a low degree of flexibility (high Young's modulus), a stress relieving ability equal to that of the case of a material of a high degree of flexibility (low Young's modulus) can be obtained. If a material of a high degree of flexibility is used, and then the above described forming is carried out, stress relief can be even more so achieved. The same effect can be expected in the fifth and sixth embodiments described below. Besides, the grooves 35 are formed on the sides in the direction (shown by an arrow in FIG. 4B) in which stress is applied from the stress transmission portion 48 to the stress relieving layer 36. Therefore, in the direction in which the stress is applied, the stress relieving ability is increased. It should be noted that the position of formation of the grooves 35 is not restricted to the positions shown in FIGS. 4A and 4B. For example, the grooves 35 may be formed on sides in a direction other than the direction (shown by an arrow in FIG. 4B) in which stress is applied from the stress transmission portion 48 to the stress relieving layer 36, or may be formed to surround the stress transmission portion 48. Fifth Embodiment FIG. 5 is a sectional view showing a fifth embodiment of the semiconductor device. The semiconductor device 39 shown in this figure is one in which the stress relieving layer 36 of the semiconductor device 30 shown in FIG. 2 is etched. That is to say, the stress relieving layer 41 of the semiconductor device 39 is formed to be thinner than the stress relieving layer 36 shown in FIG. 2. A space 43 is formed between the contact position below the flange 48a of the stress transmission portion 48 and the contact position on the wiring 38. In other words, below the flange portion 48a of the stress transmission portion 48, the stress relieving layer 41 forms a neck. This neck portion may have a circular cross-section, or may equally be formed with a taper. In the present embodiment too, the connection portion 38a is part of the member electrically connecting the solder ball (external electrode) 40 and wiring 38. In this way, by forming the space 43 below the flange portion 481 of the stress transmission portion 48, the stress relieving layer 41 is more easily able to deform. By means of this, the stress relieving layer 41 is more easily able to absorb stress. The space 43, can be formed by carrying out isotropic dry etching on the stress relieving layer 36 shown in FIG. 2. More specifically, by isotropic dry etching, the etch rate is approximately equal in the horizontal direction and the depth direction. As a result, as shown in FIG. 5, it is possible to etch into a necked shape below the flange portion 48a of the stress transmission portion 48. By means of this, the space 43 can be formed. Sixth Embodiment FIG. 6 is a sectional view showing a sixth embodiment of the semiconductor device. The semiconductor device 45 shown in this figure has a supplementary transmission portion 47 added to the semiconductor device 39 shown in FIG. 5. That is to say, in FIG. 6, a supplementary transmission portion 47 is formed continuous with the stress relieving layer 41 on the periphery of the solder ball 40. The supplementary transmission portion 47 is interposed at least between the root periphery of the solder ball 40 and the stress relieving layer 41. By this means, stress applied to the solder ball 40 can be transmitted through the supplementary transmission portion 47 to the stress relieving layer 41. Moreover, the stress is dispersed, and concentration of the stress at the connecting area of the solder ball 40 and stress transmission portion 48 is avoided. The semiconductor device 45 having a supplementary transmission portion 47 of this type can be fabricated by, forming the stress relieving layer 36 and supplementary transmission layer 33, as shown in FIG. 3, and then carrying out etching in the same way as in the fifth embodiment. In the present embodiment too, the connection portion 38a is part of the member electrically connecting the solder ball (external electrode) 40 and wiring 38. Seventh Embodiment FIG. 7 is a sectional view showing a seventh embodiment of the semiconductor device. This seventh embodiment has the characteristics of both the first and second embodiments. In this figure, a semiconductor device 50 has wiring 58 formed between first and second stress relieving layers 56 and 57. In more detail, on a semiconductor chip 52, a first stress relieving layer 56 is formed to avoid an electrode 54, and wiring 58 is formed from the electrode 54 over the stress relieving layer 56. This structure is the same as in the first embodiment. Over the wiring 58, a second stress relieving layer 57 is formed. The second stress relieving layer 57 may also be provided with a thickness in a range similar to that of the above described first stress relieving layer 56. In this stress relieving layer 57, a hole 57a is formed. A chromium (Cr) layer 62 and a copper (Cu) layer 64 are formed to pass through the stress relieving layer 57. Alternatively, in place of these, the wiring 18 described in the first embodiment may be used. At opening rim portion of the hole 57a, and the chromium (Cr) layer 62 and copper (Cu) layer 64 are arranged to broaden with comparatively wide range. On the copper (Cu) layer 64 a base 66 is formed, and a solder ball 60 is formed on this base 66. In the opening rim Portion of the hole 57a, stress from the solder ball 60 is transmitted from a stress transmission portion 68 formed by the chromium (Cr) layer 62, copper (Cu) layer 64, and a part of base 66, to the second stress relieving layer 57. The stress transmission portion 68 is provided outside the connection portion 58a. Here, the connection portion 58a is part of the chromium (Cr) layer 62, and is part of the member electrically connecting the solder ball (external electrode) 60 and wiring 58. The structure above the wiring 58 is the same as in the second embodiment, and detailed description is omitted. According to the present embodiment, stress in the vertical direction from the solder ball 60 is transmitted through the connection portion 58a to the first stress relieving layer 56 and absorbed, while being transmitted through the stress transmission portion 68 to the second stress relieving layer 57 and absorbed. In this way, a two-stage absorbing structure is provided, whereby the stress absorption is even more effective. It should be noted that in the present embodiment, the second stress relieving layer 57 also serves as a protecting layer for the wiring 58 and semiconductor chip 52. It should be noted that the second stress relieving layer 57 of the present embodiment may also have the grooves 35, the necked form of the stress relieving layer 41, or the supplementary transmission portion 47 of the fourth to sixth embodiments. Eighth Embodiment FIG. 8 is a sectional view showing an eighth embodiment of the semiconductor device. The semiconductor device 51 shown in this figure has a supplementary transmission layer 53 formed on the first stress relieving layer 57 of the semiconductor device 50 shown in FIG. 7. In the present embodiment too, the connection portion 58a is part of the member electrically connecting the solder ball (external electrode) 60 and the wiring 58. The supplementary transmission layer 53 is formed at least contacting the root periphery of the solder ball 60. Therefore, through the supplementary transmission layer 53, stress is transmitted from the solder ball 60 to the stress relieving layer 57. By this means, stress is dispersed, and a concentration of stress at the connecting portion of the solder ball 60 and the stress transmission portion 68 is avoided. It should be noted that the material and method of formation of the supplementary transmission layer 53 is the same as in the third embodiment, and description is omitted. Ninth Embodiment FIG. 9 is a sectional view showing a ninth embodiment of the semiconductor device. The ninth embodiment is a modification of the seventh embodiment. In this figure, a semiconductor device 70 has wiring 78 formed between first and second stress relieving layers 76 and 77. In more detail, a first stress relieving layer 76 is formed on the semiconductor chip 72, avoiding an electrode 74. Wiring 78 is formed from the electrode 74 over the stress relieving layer 76. On the wiring 78, a second stress relieving layer 77 is formed. To pass through this stress relieving layer 77, a copper (Cu) layer 82 is formed by sputtering, a copper (Cu) layer 84 is formed by plating, a copper (Cu) layer 86 is formed by sputtering, and a base 88 is formed by plating. A solder ball 80 is formed an this base 88. Here, the copper (Cu) layer 82 and copper (Cu) layer 84 have a larger area than the base 88 and base portion 88a of the copper (Cu) layer 86. In the copper (Cu) layer 82 and copper (Cu) layer 84, a stress transmission portion 89 corresponding to the position of the periphery of the base portion 88a transmits stress from the solder ball 80 to the first stress relieving layer 76. It should be noted that a portion of the stress transmission portion 89 (the portion contacting the base portion 88a) forms a part (connection portion) of the member electrically connecting the solder ball (external electrode) 80 and wiring 78. According to the present embodiment, since the stress transmission portion 89 is formed positioned on the periphery of the base portion 88a electrically connecting the solder ball 80 and wiring 78, stress can be transmitted to the first stress relieving layer 76 over a large area. It should be noted that in the present embodiment, even if the first stress relieving layer 76 is omitted, the stress can be absorbed by the second stress relieving layer 77. In the present embodiment too, a stress transmission portion 87 similar to the stress transmission portion 68 of the seventh embodiment (see FIG. 7) may be further formed, and a similar effect will be obtained. Tenth Embodiment FIG. 10 is a sectional view showing a tenth embodiment of the semiconductor device. This tenth embodiment is a modification of the ninth embodiment. Here, to describe only difference from the ninth embodiment. A copper (Cu) layer 92 and copper (Cu) layer 93 formed on wiring 91 are smaller than a stress transmission portion 94. Therefore, stress tending to bend over a solder ball 95 is transmitted from the stress transmission portion 94, but hard to be transmitted from the copper (Cu) layer 92 and copper (Cu) layer 93. Moreover, the copper (Cu) layer 92 and copper (Cu) layer 93 do not function as a stress transmission portion, and therefore stress tends not to be transmitted to wiring 91. By this means, breaks of the wiring 91 can be prevented. In the present embodiment, a part of the stress transmission portion 94 forms a part (connection portion) of the member electrically connecting the solder ball (external electrode) 9S and wiring 91. It should be noted that the effect in the ninth embodiment that even if the first stress relieving layer 76 is omitted, the stress can be absorbed by the second stress relieving layer 77 is the same in the tenth embodiment. Eleventh Embodiment FIGS. 11A and 11B show an eleventh embodiment of the semiconductor device. It should be noted that FIG. 11B is a plan view seen along line XI-XI in FIG. 11A. AS shown in these figures, with a semiconductor device 100, a solder ball 114 is supported by a stress transmission portion 112 in a position not contacting an electrical connection portion 110. In more detail, on an oxide layer 104 formed on a semiconductor chip 102, wiring 106 is formed. The wiring 106 electrically connects a pad 106a positioned in the center of the solder ball with to an electrode 108. Moreover, the wiring 106 extends from the pad 106a in a direction perpendicular to the direction (shown by an arrow in FIG. 11B) of stress generated by differences in the coefficient of thermal expansion between the mounting board and the semiconductor device 100. Therefore, even if stress is applied to the wiring 106, since force is not applied in the direction of extension in the vicinity of the pad 106a, wiring breaks are less likely to occur. On the wiring 106 a stress relieving layer 118 is formed. However, on the pad 106a a hole is formed in the stress relieving layer 118, and the connection portion 110 is formed to electrically connect the pad 106a and solder ball 114. The connection portion 110 forms a part of the member electrically connecting the solder ball (external electrode) 114 and wiring 106. Besides, in a peripheral position of the connection portion 110 and in a noncontact position, between an oxide layer 104 and solder ball 114 a plurality of stress transmission portions 112 are provided. For this reason, in the stress relieving layer 118 a plurality of holes are formed. It should be noted that the connection portion 110 and stress transmission portion 112 are form,ed continuously as projections projecting downward from a base 116 which supports the solder ball 114. The present embodiment has the above described structure, and its effect is now described. In the present embodiment, the solder ball 114 is electrically connected to the wiring 106 by the connection portion 110 in a central position thereof. Then a stress transmission portion 112 is provided in a peripheral position of the connection portion 110 and in a noncontact position. Therefore, since it is in the noncontact state, the influence of the stress transmitted by the stress transmission portion 112 tends not to be transmitted to the connection portion 110. Thus, stress is not transmitted to the wiring 106 and wiring breaks can be prevented. The base 116 partially contacts above the stress relieving layer 118. In particular, a contact portion 116a positioned on the periphery of the stress transmission-portion 110 is such as to transmit stress to the stress relieving layer 118 and absorb the same. Twelfth Embodiment FIGS. 12A and 12B show a twelfth embodiment of the semiconductor device. It should be noted that FIG. 12B is a plan view seen along line XII-XII in FIG. 12A. This twelfth embodiment is a modification of the above described eleventh embodiment. Here the differences from the eleventh embodiment are described. In FIGS. 12A and 12B, a semiconductor device 120 has first and second stress relieving layers 122 and 124. Then wiring 126 is formed on the first stress relieving layer 122, and a stress transmission portion 128 is formed on the first stress relieving layer 124. Therefore, stress from a solder ball 130 is transmitted from the stress transmission portion 128 to the first stress relieving layer 122, and absorbed. It should be noted that with regard to a connection portion 132 formed on a pad 126a, the structure is the same as the connection portion 110 shown in FIG. 11A, and therefore description is omitted. That is to say, the connection portion 132 forms a part of the element electrically connecting the solder ball (external electrode) 130 and wiring 126. According to the present embodiment, stress is relieved through the stress transmission portion 128 by the first stress relieving layer 122. Therefore, the base 134 has a flange formed in a peripheral position of the stress transmission portion 128. The contact portion with the second stress relieving layer 124 is omitted. However, a contact portion may be provided in the same way as in the eleventh embodiment. Thirteenth Embodiment FIG. 13 shows a thirteenth embodiment of the semiconductor device. This thirteenth embodiment is a modification of the above described eleventh and twelfth embodiments. In other words, in place of the plurality of pillar-shaped stress transmission portions 112 shown In FIGS. 11A and 11B, the semiconductor device 140 shown in FIG. 13 has a cylindrical stress transmission portion 142. This stress transmission portion 142 has a part cut away to allow wiring 144 to be led to the inside, and is arranged not to contact the wiring 144. Even with a stress transmission portion 142 of this type, the same effect as in the eleventh embodiment can be achieved. The connection portion electrically connecting the solder ball (external electrode) and wiring is the same as in the twelfth embodiment. Fourteenth Embodiment FIG. 14 shows a fourteenth embodiment of the semiconductor device. The semiconductor device 150 shown in this figure also has a first stress relieving layer 154 formed on a semiconductor chip 152. However, in this stress relieving layer 154 a substantially circular groove 156 is formed. Thus an island portion 158 delineated by the groove 156 is formed. Besides, wiring 159 is formed to reach the island portion 158. In more detail, in order to form the wiring 159, the groove 156 is formed in a C-shape. On the first stress relieving layer 154, a second stress relieving layer 160 is formed. In the second stress relieving layer 160, a hole 160a is formed to extend further outside than the groove 156. Then on the inner surface and opening rim portion of the hole 160a, on the surface 154a of the first stress relieving layer 154 exposed by the hole 160a, and on the wiring 159 formed on the island portion 158, a base 162 is provided with a thin metal film interposed by sputtering. A solder ball 164 is provided on the base 162. According to the present embodiment, island portion 158 is isolated from the region receiving stress from the solder ball 164, by means of the groove 156. Therefore, stress tends not to be transmitted to the wiring 159, and the occurrence of wiring breaks can be prevented. It should be noted that the connection portion being one part of the member electrically connecting the solder ball (external electrode) and wiring is the same as in the twelfth embodiment. Fifteenth Embodiment FIG. 15 shows a fifteenth embodiment of the semiconductor device. The semiconductor device 170 shown in this figure has a bump 174 provided on a stress relieving layer 172 to absorb stress. It is the same as the above embodiments from the point of view of stress absorption. The characteristic of the present embodiment is that wiring 176 has a bent portion 180 forming an empty portion between the wiring 176 and the semiconductor chip 178, and the empty portion is injected with a gel material 182. It should be noted that since the gel material 182 is inserted for the purpose of reinforcement, it may be omitted. Besides, the wiring 176 is preferably formed of metal from the viewpoint of ductility. In this way, when the bent portion 180 is formed, even if stress is applied to the wiring 176, it is absorbed by the bent portion 180. Therefore, stress transmitted from the bump 174 is not transmitted to the electrode 184. In this way wiring breaks can be prevented. To form the bent portion 180 a resist is deposited to outline the bent portion 180, and the wiring 176 is formed thereon, then the resist is removed by dry etching or wet etching. It should be noted that a material other than resist can be used as long as it can be etched. While omitted from the drawings, a wiring protection layer being a solder resist or the like is preferably provided as the outermost layer to prevent corrosion and the like of the wiring. The present embodiment can be applied to other embodiments, and in this case the connection portion being one part of the member electrically connecting the solder ball (external electrode) and wiring is the same as in the twelfth embodiment. Sixteenth Embodiment FIG. 16 shows a sixteenth embodiment of the semiconductor device. The semiconductor device 190 shown in this figure has first wiring 194 formed on a semiconductor chip 192, a first stress relieving layer 196 formed on this wiring 194, and second wiring 198 formed on this stress relieving layer 196. In more detail, on the first wiring 194, a hole is formed in the first stress relieving layer 196, and the second wiring 198 is formed from the first wiring 194 over the first stress relieving layer 196. On the second wiring 198, a copper (Cu) layer 200 is formed by plating, and on this copper (Cu) layer 200, a second stress relieving layer 202 is formed. In the second stress relieving layer 202, a hole 202a is formed over the copper (Cu) layer 200. A bump 204 is provided on the copper (Cu) layer 200. Part of the bump 204 contacts the second stress relieving layer 202, and is arranged to transmit stress. According to the present embodiment, the connection portion 206 of the first and second wiring 194 and 198 and the connection portion 208 of the second wiring 198 and the bump 204 are disposed on the different planes. Here, the connection portion 206 indicates the portion of contact between the first and second wiring 194 and 198, and the connection portion 208 indicates the portion of contact between the second wiring 198 and the bump 204. The connection portions 206 and 208 form a part of the member electrically connecting the wiring 194 and bump (external electrode) 204. Therefore, even if stress is transmitted from the bump 204 through the connection portion 208 to the second wiring 198, this stress tends not to be transmitted to the other connection portion 206. In this way, since stress is made less likely to be transmitted to the first wiring 194, wiring breaks in this wiring 194 are prevented. (Fabrication Process) FIGS. 17A to ISC show a manufacturing method of a semiconductor device of the present embodiment. First, using well-known technology, normally, an electrode 302 and other elements are formed up to the state before carrying out dicing on a wafer 300 (see FIG. 17A). In the present embodiment, the electrode 302 is formed of aluminum, but equally an aluminum alloy material (for example, aluminum silicon, aluminum silicon copper, and so on) or a copper material may be used. On the surface of the wafer 300, a passivation film (not shown in the drawings) such as an oxide layer is formed to prevent chemical change. The passivation film is formed to avoid not only the electrode 302, but also a scribing line used to carry out dicing. By not forming the passivation film on the scribing line, during dicing the creation of debris from the passivation film can be avoided, and furthermore, the generation of cracks in the passivation film can be prevented. Next, sputtering is carried out with the wafer 300 as the target, and the foreign objects are removed from the surface of the wafer 300 (in other words, reverse sputtering). Then, as shown in FIG. 17A, by means of sputtering a titanium tungsten (TiW) layer 304 and copper (Cu) layer 306 are superimposed on the surface of the wafer 300. It should be noted that in this fabrication process, the example described has titanium tungsten (TiW) and copper (Cu) used for the wiring, but the present invention is not limited to this. Then, when the wiring resistance is lowered, in particular on the copper layer 306, a copper plating layer 308 is formed by electroplating. The layer thicknesses may be, for example, approximately the following values: Titanium tungsten layer: 1000 angstroms (10−10 m) Copper layer: 1000 angstroms (10−10 m) Copper plating layer: 0.5 to 5 μm Next, as shown in FIG. 17B, the titanium tungsten layer 304, copper layer 306, and copper plating layer 308 are dry etched, applying photolithography technology, to form wiring 310. In more detail, a photoresist (not shown in the drawings) is applied on the copper plating layer 308, and prebaking, exposure and development are carried out. Drying and postbaking are carried out after washing. Then dry etching is applied to the copper plating layer 308 and copper layer 306 for rinsing, and the titanium tungsten layer 304 is dry etched. Next, the photoresist is removed and washing carried out. In this way, as shown in FIG. 17B, the wiring 310 is formed. Next, the wiring 310 is subjected to ashing by an O2 plasma, then after water is removed from the wafer 300, as shown in FIG. 17C, a polyimide resin 312 is applied to the whole surface of the wafer 300. The polyimide resin 312 forms a stress relieving layer same as the stress relieving layer 36 and the like shown in FIG. 2. Here, by means of the ashing, the adhesion properties of the wiring 310 and wafer 300 with the polyimide resin 312 are improved. For the polyimide resin 312, it is preferable to use one with good adhesion properties with the passivation film of the wafer 300, a low Young's modulus and a low water absorption ratio, and for which a large film thickness is possible. The polyimide resin 312 is now subjected to prebaking, exposure, drying, development, washing, drying and curing processes. In this way, as shown in FIG. 17D, a hole 314 is formed in the polyimide resin 312. The polyimide resin 312, while adhered to the wiring 310 and wafer 300, is shrunk by the drying and curing processes, so that the inside of the hole 314 is shaped as a 60 to 70 degree taper. Therefore, it is preferable that the polyimide resin 312 is selected so that a taper is shaped inside the hole 314. Next, the surface of the polyimide resin 312 is subjected to ashing by an O2 plasma, and sputtering is carried out with this polyimide resin 312 as the target to remove foreign objects. By means of the ashing, the adhesion properties of the surface of the polyimide resin 312 with a metal film are improved. Then as shown in FIG. 17E, by sputtering applied to the whole surface of the polyimide resin 312, a titanium tungsten (TiW) layer 316 and copper (Cu) layer 318 are formed to be overlaid. Then, a copper plating layer 320 is formed on the copper layer 318 by electroplating. It should be noted that in place of the titanium tungsten layer 316, a titanium (Ti) layer may be formed. The layer thicknesses may be, for example, approximately the following values: Titanium tungsten layer: 1000 angstroms (10−10 m) Copper layer: 1000 angstroms (10−10 m) Copper plating layer: 0.5 to 100 μm Next, a photoresist is applied on the copper plating layer 320, then the copper plating layer 320 and copper layer 318 are etched after prebaking, exposure, development, washing, drying and postbaking are carried out. Then the titanium tungsten layer 316 is etched after washing, and the photoresist is removed, and washing is carried out. In this way, as shown in FIG. 18A, the stress transmission portion 322 is formed on the wiring 310. Then ashing is carried out to the stress transmission portion 322 by an O2 plasma. Then as shown in FIG. 18B, a solder paste 324 is disposed on the stress transmission portion 322. The solder paste 324 can be provided, for example, by screen printing. Besides, when the particle size of the solder paste 324 is of the range around 25 to 15 μm, the printing mask will be easily released. Alternatively, the solder paste 324 may be provided by a solder plating method. Next, through a reflow process, the solder paste 324 is melted to form a solder ball 326 by means of surface tension, as shown in FIG. 18C. Then the flux is subjected to washing. According to the above described manufacturing method of a semiconductor device, almost all steps are completed within the stage of wafer processing. In other words, the step in which the external terminals for connection to the mounting board are formed is carried out within the stage of wafer processing, and it is not necessary to carry out the conventional packaging process, that is to say, in which individual semiconductor chips are handled, and an inner lead bonding process and external terminal formation process are carried out for each individual semiconductor chip. Besides, when the stress relieving layer is formed, a substrate such as a patterned film is not required. For these reasons, a semiconductor device of low cost and high quality can be obtained. Other Embodiments The present invention can be applied to a CSP semiconductor device. In FIG. 19 is shown a typical CSP semiconductor device. In this figure, a semiconductor chip 1 has wiring 3 formed extending from electrodes 2 toward the center of an active surface 1a, and an external electrode 5 is provided on each wiring 3. All of the external electrodes 5 are provided on a stress relieving layer 7, so that the stresses can be relieved when mounted on a circuit board (not shown in the drawings). Besides, excluding the region of the external electrodes 5, a solder resist layer 8 is formed as a protective film. The stress relieving layer 7 is formed at least in the region surrounded by the electrodes 12. It should be noted that the electrodes 2 refer to the portions connected to the wiring 3. Besides, when the area required to form the external electrodes 5 is considered, although not shown in FIG. 19, the stress relieving layer 7 may be provided on the outside of the electrodes 2, and the wiring 3 brought around thereon, to provide the external electrodes 5 in the same way. The electrodes 2 are positioned around the periphery of the semiconductor chip 1, in an example of the so-called peripheral electrode type, however, equally an area array type of semiconductor chip in which the electrodes are formed in a region inside the periphery of the semiconductor chip may be used. In this case, the stress relieving layer 7 may be formed to avoid at least a portion of the electrodes 2. As shown in this drawing, the external electrodes 5 are provided not on the electrodes 2 of the semiconductor chip 1, but in the active region (the region in which the active elements are formed) of the semiconductor chip 1. By providing the stress relieving layer 7 in the active region, and further positioning (bringing In) the wiring 3 within the active region, the external electrodes 5 can be provided within the active region. That is to say, a pitch conversion can be carried out. As a result, when laying out the external electrodes 5, the interior of the active region, that is to say, a region of a particular plane can be provided. Thus the flexibility for positioning the external electrodes 5 is greatly increased. By bending the wiring 3 at the required position, the external electrodes 5 can be aligned in a lattice. It should be noted that this is not an essential construction of the present invention, and therefore the-external electrodes 5 do not necessarily have to be disposed in a lattice. In FIG. 19, at the junction of the electrodes 2 and wiring 3 the size of the electrodes 2 and the size of the wiring 3 are such that: wiring 3<electrodes 2 but it is preferable that: electrodes 2≦wiring 3 In particular, in the case that: electrodes 2<wiring 3 not only is the resistance of the wiring 3 reduced, but also, since the strength is increased, wiring breaks are prevented. In each of the above described embodiments, in cases where external stress applied to the solder ball is concentrated in the wiring, the wiring is designed to be curved (or bent) in the planar direction, and in addition to or separate from this, a bent (curved) structure as in the fifteenth embodiment is adopted to each embodiment, so that concentration of Stress on the wiring is dispersed. In such a semiconductor device, almost all steps can be completed within the stage of wafer processing. More specifically, a plurality of electrodes 2 are formed on the wafer, and a stress relieving layer 7 is disposed on the wafer avoiding the electrodes 2, and individual semiconductor devices are cut from the wafer after gone through the process of forming wiring 3 from the electrodes 2. Here, for the formation of the electrodes 2 and wiring 3, for example, sputtering, etching, or other thin metal film forming technology can be applied. For the formation of the external electrodes 5, a solder plating process can be applied. Furthermore, for the formation and processing of the stress relieving layer 7, a photolithography in which a photosensitive resin is exposed and developed can be applied. These steps can all be carried out during wafer processing. In this way, after carrying out almost all of the steps is in wafer processing, the individual semiconductor devices are cut. By doing this the stress relieving layer 7, wiring 3, and external electrodes 5 of a plurality of semiconductor devices can be formed simultaneously. As a result, the fabrication process can be simplified. In FIG. 20 is shown a circuit board 1000 on which is mounted a semiconductor device 1100 fabricated by the method of the above described embodiment. The circuit board generally uses an organic compound substrate such as glass epoxy. A wiring pattern of, for example, copper is formed on the circuit board to form a desired circuit. The electrical connection Is achieved by mechanical connection of the wiring pattern and the external terminals of the semiconductor device. In this case, since the above described semiconductor device has a construction for absorbing strain generated by differences in thermal expansion with the exterior provided by the stress relieving portion, when this semiconductor device is mounted on the circuit board and thereafter, the reliability can be improved. Besides, if appropriate attention is paid to the wiring of the semiconductor device., the reliability during connection and the reliability after connection can be improved. It should be noted that the mounting area can also be reduced to the area for mounting as a bare chip. Therefore, when this circuit board is used in an electronic instrument, the electronic instrument itself can be made more, compact. Besides, within the same area, greater effective mounting space can be made available, and it is possible to design for greater functionality. Next, as an electronic instrument provided with this circuit board 1000, FIG. 21 shows a notebook personal computer 1200. It should be noted that the above described embodiments apply the present invention to a semiconductor device, but the present invention can be applied to any surface-mounted electronic component, whether active or passive. Electronic components include, for example, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, variable resistors, and fuses. In addition, by using given electronic element in place of the semiconductor element in the above described embodiments, and by forming the same kind of stress transmission portion as in the above described embodiments, stress can be relieved by the stress relieving portion, and wiring breaks and the like can be prevented. Since the manufacturing method is the same as in the above described embodiment, description is omitted.	H	67H01	185H01L	23	48
11858437	US20090079038A1-20090326	Method Of Making An Integrated Circuit Including Singulating A Semiconductor Wafer	ACCEPTED	20090311	20090326	[]	H01L23544	["H01L23544", "H01L2178"]	7674689	20070920	20100309	438	462000	72874.0	HOANG	QUOC	[{"inventor_name_last": "Schneegans", "inventor_name_first": "Manfred", "inventor_city": "Vaterstetten", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Kroninger", "inventor_name_first": "Werner", "inventor_city": "Regensburg", "inventor_state": "", "inventor_country": "DE"}]	A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.	1. A method of making an integrated circuit, the method comprising: providing a semiconductor wafer comprising a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface; forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface; and sawing a second trench in the other of the first surface and the second surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer. 2. The method of claim 1, wherein providing a semiconductor wafer comprises: providing a semiconductor wafer including a front side having an active chip surface, the front side coupled to a first carrier; grinding a side of the semiconductor wafer opposite the front side to define a back side of the semiconductor wafer; and depositing a metallization layer onto the back side. 3. The method of claim 2, wherein forming a first trench comprises: attaching the metallization layer to an adhesive carrier; decoupling the front side from the first carrier; and sawing the front side of the semiconductor wafer through a portion of the semiconductor wafer toward the back side to define dicing marks on the front side. 4. The method of claim 3, wherein sawing a second trench comprises: coupling the sawn front side of the semiconductor wafer to an adhesive carrier; matching the dicing marks on the front side with a desired saw pattern on the back side; and singulating a chip by sawing the back side of the semiconductor wafer. 5. The method of claim 3, wherein sawing the front side of the semiconductor wafer comprises transferring a saw pattern to the back side of the semiconductor wafer that is configured to visually guide sawing a second trench in the back side of the semiconductor wafer. 6. The method of claim 3, wherein decoupling the front side from the first carrier comprises cutting along a sloped cut line such that a diameter of the front side of the semiconductor wafer is greater than a diameter of the back side. 7. The method of claim 2, wherein forming a first trench comprises: removing an edge portion of the metallization layer; visualizing a front side kerf pattern by viewing through the removed edge portion of the metallization layer; aligning the metallization layer and the back side with the front side kerf pattern; and forming a first trench through the metallization layer and the back side of the semiconductor wafer, the first trench extending part way toward the front side of the semiconductor wafer. 8. The method of claim 7, wherein sawing a second trench comprises: coupling the metallization layer to an adhesive carrier; removing the first carrier from the front side of the semiconductor wafer; and sawing through the front side along the front side kerf. 9. The method of claim 7, wherein visualizing a front side kerf pattern comprises infrared viewing through the removed edge portion of the metallization layer to determine the front side kerf pattern. 10. The method of claim 2, wherein providing a semiconductor wafer comprises providing a semiconductor wafer having a thickness of about 700 micrometers and forming a first trench comprises sawing a first trench through the metallization layer and the back side of the semiconductor wafer, the first trench extending between about 50-100 micrometers toward the front side of the semiconductor wafer. 11. The method of claim 10, wherein sawing a second trench comprises: coupling the metallization layer to an adhesive carrier; and sawing through the front side along the front side kerf. 12. The method of claim 1, wherein a width of the first trench is greater than a width of the second trench. 13. The method of claim 1, wherein a width of the first trench is about equal to a width of the second trench. 14. A method of making an integrated circuit including singulating a semiconductor substrate, the method comprising: providing a semiconductor wafer comprising an active surface and a metallized back side opposite the active surface; sawing the active surface of the semiconductor wafer through a portion of the thickness of the semiconductor wafer; and dicing the semiconductor wafer by sawing the metallized back side through a remaining portion of the thickness of the semiconductor wafer. 15. The method of claim 14, wherein sawing the active surface of the semiconductor wafer comprises attaching the metallized back side to a carrier and sawing streets along a visible kerf pattern that is oriented between chips disposed on the active surface. 16. The method of claim 15, wherein dicing the semiconductor wafer comprises: attaching the sawn active surface to a carrier; and aligning the semiconductor wafer in a dicing tool such that the metallized back side is aligned with the sawn streets. 17. The method of claim 16, wherein attaching the metallized back side to a carrier comprises laser separating the semiconductor wafer from a carrier wafer such that a diameter of the active surface is greater than a diameter of the back side, the narrower back side configured to enable visualization of the sawn streets. 18. A method of making an integrated circuit including singulating a semiconductor substrate, the method comprising: providing a semiconductor wafer comprising an active surface and a metallized back side opposite the active surface; visualizing through the metallized back side to discern a kerf pattern on the active surface; sawing streets in the metallized back side that are aligned with the kerf pattern and extend part way toward the active surface; and sawing the active surface of the semiconductor wafer through a remaining thickness of the semiconductor wafer. 19. The method of claim 18, wherein visualizing through the metallized back side to discern a kerf pattern on the active surface comprises removing an edge portion of the metallized back side. 20. The method of claim 19, further comprising: infrared scanning through the removed edge portion of the metallized back side to identify the kerf pattern. 21. A semiconductor wafer having an active surface and a metallized back side opposite the active surface, the semiconductor wafer comprising: partially sawn first streets extending through the active surface and a portion of the thickness of the semiconductor wafer; means for aligning the metallized back side with a dicing tool such that the metallized back side is aligned with the first streets formed in the active surface; and second streets sawn into the metallized back side such that the second streets communicate with the first streets. 22. The singulated semiconductor substrate of claim 21, wherein means for aligning the metallized back side with a dicing tool comprises means for transferring visual information related to the sawn first streets on the active surface to the metallized back side. 23. The singulated semiconductor substrate of claim 22, wherein means for transferring visual information related to the sawn first streets on the active surface to the metallized back side comprises cutting a beveled edge around the semiconductor wafer such that a diameter of the active surface side of the semiconductor wafer is greater than a diameter of the metallized back side. 24. The singulated semiconductor substrate of claim 21, wherein the partially sawn first streets comprise streets half-cut diced into the active surface of the semiconductor wafer.	<SOH> BACKGROUND <EOH>Market demand for smaller and more functional electronic devices has driven the development of semiconductor devices, packages, and highly functional chips. Multiples of these functional chips are formed on a surface of a semiconductor wafer and include specific, desired chip properties. The semiconductor wafer includes a semiconductor substrate having a metal layer on one side and an active surface opposite the metal layer. The metal layer is configured to provide electrical connection for each chip after the chip is separated from the wafer. The active surface is fabricated to include contact pads that provide electrical access to the chip. After fabrication, the chips are cut or singulated from the semiconductor substrate and suited for individual use in electronic devices. FIG. 1 is a cross-sectional view of a conventional semiconductor substrate 20 . The known semiconductor substrate 20 includes a silicon portion 22 defining an active surface 24 , a back side 26 opposite active surface 24 , and a metal layer 28 deposited on back side 26 . Semiconductor substrate 20 is fabricated to include a plurality of chips (not shown) deposed in the plane of active surface 24 . After fabrication of semiconductor substrate 20 , it is desired to separate, or singulate, the individual chips by sawing semiconductor substrate 20 from active surface 24 down to back side 26 and through metal layer 28 . It is known that sawing through metal layer 28 is likely to produce burrs 30 , and/or cracks 32 . Burrs 30 and cracks 32 are highly undesirable. Burrs 30 extend from metal layer 28 and deleteriously affect electrical performance/contact of the chip when coupled to another electronic device. Cracks 32 can potentially interrupt the electrical contact between the silicon layer 22 and metal layer 28 . In addition, cracks 32 in silicon portion 22 are known to propagate when the chip is thermally cycled, thus possibly interrupting electrical connection for the chip. Dicing or cutting semiconductor substrate 20 from metal layer 28 through silicon layer 22 is problematic because the chip pattern (or kerf) on active surface 24 is not visible from the metal layer 28 side. Thus, blindly sawing semiconductor substrate 20 from metal layer 28 toward active surface 24 has the potential of damaging the unseen chips on active surface 24 . For these and other reasons there is a need for the present invention.	<SOH> SUMMARY <EOH>One aspect provides a method of making an integrated circuit. The method includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the layers of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward another of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.	BACKGROUND Market demand for smaller and more functional electronic devices has driven the development of semiconductor devices, packages, and highly functional chips. Multiples of these functional chips are formed on a surface of a semiconductor wafer and include specific, desired chip properties. The semiconductor wafer includes a semiconductor substrate having a metal layer on one side and an active surface opposite the metal layer. The metal layer is configured to provide electrical connection for each chip after the chip is separated from the wafer. The active surface is fabricated to include contact pads that provide electrical access to the chip. After fabrication, the chips are cut or singulated from the semiconductor substrate and suited for individual use in electronic devices. FIG. 1 is a cross-sectional view of a conventional semiconductor substrate 20. The known semiconductor substrate 20 includes a silicon portion 22 defining an active surface 24, a back side 26 opposite active surface 24, and a metal layer 28 deposited on back side 26. Semiconductor substrate 20 is fabricated to include a plurality of chips (not shown) deposed in the plane of active surface 24. After fabrication of semiconductor substrate 20, it is desired to separate, or singulate, the individual chips by sawing semiconductor substrate 20 from active surface 24 down to back side 26 and through metal layer 28. It is known that sawing through metal layer 28 is likely to produce burrs 30, and/or cracks 32. Burrs 30 and cracks 32 are highly undesirable. Burrs 30 extend from metal layer 28 and deleteriously affect electrical performance/contact of the chip when coupled to another electronic device. Cracks 32 can potentially interrupt the electrical contact between the silicon layer 22 and metal layer 28. In addition, cracks 32 in silicon portion 22 are known to propagate when the chip is thermally cycled, thus possibly interrupting electrical connection for the chip. Dicing or cutting semiconductor substrate 20 from metal layer 28 through silicon layer 22 is problematic because the chip pattern (or kerf) on active surface 24 is not visible from the metal layer 28 side. Thus, blindly sawing semiconductor substrate 20 from metal layer 28 toward active surface 24 has the potential of damaging the unseen chips on active surface 24. For these and other reasons there is a need for the present invention. SUMMARY One aspect provides a method of making an integrated circuit. The method includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the layers of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward another of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. FIG. 1 is a cross-sectional view of a semiconductor substrate as known in the art. FIG. 2 is a side view of a carrier assembly including a product wafer coupled to a carrier wafer according to one embodiment. FIG. 3 is a side view of the carrier assembly shown in FIG. 2 after the product wafer has been ground and coated with a metallization layer to define a semiconductor substrate according to one embodiment. FIG. 4 is a side view of the semiconductor substrate shown in FIG. 3 coupled to an adhesive carrier according to one embodiment. FIG. 5 is a side view of the semiconductor substrate shown in FIG. 4 illustrating a diced active surface according to one embodiment. FIG. 6 is a back side view of exposed and un-diced metallization layer with the diced active surface of the semiconductor substrate mounted to another adhesive carrier according to one embodiment. FIG. 7A is a back side view after dicing of the metallization layer shown in FIG. 6. FIG. 7B is side view of singulated semiconductor chips coupled to a tape carrier according to one embodiment. FIG. 8A is a side view of a semiconductor substrate mounted on a carrier according to another embodiment. FIG. 8B is a side view of a dicing blade sawing a trench through a metalized back side of the semiconductor substrate shown in FIG. 8A. FIG. 8C is a side view of the sawn metalized back side illustrated in FIG. 8B mounted on a film of a clamp assembly. FIG. 8D is a side view showing removal of the carrier illustrated in FIG. 8A. FIG. 8E is a side view showing a dicing blade cutting a trench into an active surface of the semiconductor substrate shown in FIG. 8A according to one embodiment. FIG. 9A is a side view of a thick semiconductor substrate oriented metallization layer up according to one embodiment. FIG. 9B is a side view of a first trench cut through the metallization layer of the semiconductor substrate shown in FIG. 9A. FIG. 9C is a side view of a second trench cut into an active surface of the semiconductor substrate shown in FIG. 9A. DETAILED DESCRIPTION In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. As employed in this Specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the “coupled” or “electrically coupled” elements. Embodiments provide a method of sawing a semiconductor substrate including a silicon wafer portion and a metal layer portion that minimizes or eliminates the formation of burrs and/or cracks when sawing through the semiconductor substrate. Some embodiments provide for the partial dicing through a semiconductor substrate. Dicing part way through the substrate, for example through an active surface of the semiconductor substrate, provides an alignment feature that enables full-thickness dicing of the substrate through a metallized back side. In one embodiment, the partial dicing alignment feature aligns enables alignment of the metallized back side with kerf lines/dicing lines formed on the active surface of the semiconductor substrate. In this manner, final dicing streets that are cut through the metallization layer align with the partial/initial dicing streets sawn through the active surface of the semiconductor substrate. Other embodiments provide for the removal of a portion of a metallization layer deposited on a back side of a semiconductor substrate, where the removed portion of the metallization layer enables optical alignment of the metallized back side with kerf lines on an opposing active surface of the semiconductor substrate. To this end, the back side metallization layer is first sawn in alignment with the kerfs on the active surface, and a second subsequent sawing of the active surface singulates chips from the semiconductor substrate. In other embodiments, first trenches or streets are diced in a first surface of the semiconductor substrate, where the first streets imprint or otherwise transfer a cutting pattern to the opposite surface of the semiconductor substrate. Thereafter, the imprinted surface of the semiconductor substrate may be accurately sawn in alignment with the first streets. The various embodiments of partial dicing of streets in a semiconductor substrate solves the problem known in the art of forming metal burrs when the semiconductor substrate is diced from the kerf lines on the active surface down to the metallization layer. In addition, the partial dicing of streets in a semiconductor substrate as described herein minimizes or eliminates the undesirable formation of cracks in the silicon portion of the substrate. FIG. 2 is a side view of a carrier assembly 50 according to one embodiment. Carrier assembly 50 includes a semiconductor substrate 52 having an active surface 54, where semiconductor substrate 52 is coupled to a carrier wafer 56 by adhesive 58. Semiconductor substrate 52 includes silicon wafers having a diameter of about 100 to about 300 millimeters. In one embodiment, semiconductor substrate 52 is provided as a thick product wafer having semiconductor chips (not shown) formed on active surface 54. Active surface 54 of semiconductor substrate 52 is oriented toward carrier wafer 56. The chips are aligned in rows and columns across active surface 54, where the space between the rows and columns of chips define a kerf pattern (not shown). Subsequent to fabrication, the chips are singulated from semiconductor substrate 52 by sawing or dicing along the kerf to provide individual chips useful in electronic components. Carrier wafer 56 is coupled over active surface 54 by glue 58. In one embodiment, carrier wafer 56 is a thin silicon carrier wafer configured to protect active surface 54 during fabrication of semiconductor substrate 52. In one embodiment, an outer perimeter of semiconductor substrate 52 is coupled to an outer perimeter of carrier wafer 56 by adhesive material 58. Adhesive material 58 includes epoxies, glues, and other materials suited for adhesively coupling carrier wafer 56 to product wafer 52. FIG. 3 is a side view of carrier assembly 50 illustrating semiconductor substrate 52 after thinning according to one embodiment. In one embodiment, semiconductor substrate 52 is ground to reduce its thickness, which defines a back side 60 opposite active surface 54. In one embodiment, a metallization layer 62 is deposited onto back side 60 of semiconductor substrate 52, such that semiconductor substrate 52 includes active surface 54 and a metal layer 62 opposite active surface 54. In one embodiment, semiconductor substrate 52 is thinned by grinding to have a thickness T of between about 40-60 micrometers, although other thicknesses are also acceptable. In one embodiment, metallization layer 62 is deposited onto back side 60 to have a thickness of between about 1-8 micrometers. Metallization layer 62 is deposited in a suitable deposition process, including a vapor deposition process, a chemical vapor deposition process, a plasma vapor deposition process, sputtering, or other suitable deposition process employed to coat a thin layer of metal 62 onto back side 60 of semiconductor substrate 52. FIG. 4 is a side view of carrier assembly 50 coupled to a carrier tape 70 according to one embodiment. In one embodiment, metallization layer 62 is coupled to carrier tape 70 and active surface 54 is oriented toward carrier wafer 56. In one embodiment, carrier tape 70 is a single sided adhesive tape configured to carry semiconductor substrate 52 through fabrication processes. In another embodiment, carrier tape 70 is a saw foil 70, although other forms of tape are also acceptable. In one embodiment, a separation line 72 is provided that removes carrier wafer 56 from semiconductor substrate 52 by cutting within the perimeter of adhesive 58. In one embodiment, separation line 72 is provided by a laser or other energetic cutting procedure in which a cut is provided to remove carrier wafer 56 from carrier assembly 50. In one embodiment, separation line 72 is oriented at an angle A relative to vertical such that separation line 72 is a sloped cutting line and semiconductor substrate 52 includes beveled edges. In one embodiment, separation line 72 does not sever carrier tape 70, such that carrier tape 70 is available for subsequent fabrication of semiconductor substrate 52. FIG. 5 is a side view of semiconductor substrate 52 after the removal of carrier wafer 56 (FIG. 4) from carrier assembly 50. Angled separation line 72 (FIG. 4) severs semiconductor substrate 52 such that active surface 54 has a first diameter D1 and metallization layer 62 has a second diameter D2. In one embodiment, D1 is greater than D2 such that semiconductor substrate 52 is beveled in a manner that active surface 54 extends beyond metallization layer 62. In one embodiment, semiconductor substrate 52 is oriented on carrier tape 70 such that active surface 54 is oriented up (relative to FIG. 5) and configured for dicing or sawing by a dicing blade. As noted above, active surface 54 includes a plurality of semiconductor chips oriented in columns and rows, where the chips are separated by a kerf. The layout of the chips, and the kerf, is visible on active surface 54. Sawing along the kerf ensures accurate singulation of semiconductor substrate 52. However, sawing along the kerf from active surface 54 down to metallization layer 62 has the potential to form undesirable metal burrs and cracks in the silicon wafer. In one embodiment, a plurality of first trenches 80 are formed in active surface 54 that dice or extend partially into the thickness of semiconductor substrate 52. In one embodiment, first trenches 80 are half-cut diced into active surface 54 and extend part-way toward metallization layer 62. In this specification, half-cut dice means a cut street that extends between 10-90% of the thickness of semiconductor substrate 52. In some embodiments, a half-cut diced street extends about midway through semiconductor substrate 52, although first trenches 80 could extend more than 50% or less than 50% through semiconductor substrate 52 consistent with the definition of half-cut diced. In one embodiment, sawing front side active surface 54 of semiconductor wafer substrate 52 transfers a saw pattern to back side 60 of semiconductor wafer substrate 52 and/or metallization layer 62 that is configured to visually guide sawing second trenches in back side 60 of the semiconductor wafer substrate 52. As described below, half-cut dicing of the front/active surface 54 enables matching the dicing marks on the active surface 54 with a desired saw pattern on the back side or metallization layer 62. FIG. 6 is a back side view of metallization layer 62 showing active surface 54 of semiconductor substrate 52 coupled to another adhesive carrier 71. Metallization layer 62 is exposed (oriented up relative to FIG. 6) and prevents the optical, infrared or otherwise, visualization of first trenches 80. Active surface 54 including first trenches 80 has been coupled to adhesive carrier 71. Active surface 54 has a diameter D1 that is larger than diameter D2 of metallization layer 62. In this manner, first trenches 80 formed an active surface 54 are visible around a periphery 82 of metallization layer 62. In one embodiment, the visible first trenches 80 disposed around and extending beyond the periphery 82 of metallization layer 62 enables alignment of metallization layer 62 along a direction of first trenches 80. In this manner, a dicing tool is aligned with and enabled to cut/dice a second set of trenches that will align with first trenches 80. In one embodiment, beveled separation line 72 (FIG. 4) is configured such that diameter D1 is greater than diameter D2 and thus provides a transfer alignment mechanism that enables metallization layer 62 to be aligned with first trenches 80 prior to cutting of second trenches in metallization layer 62. For example, in one embodiment an X-Y axis 84 of semiconductor substrate 52 is spatially oriented such that metallization layer 62 is aligned with first trenches 80 and with a desired cutting direction for second trenches. FIG. 7A is a back side view of semiconductor substrate 52 including second trenches 90 cut into metallization layer 62 in alignment with first trenches 80. FIG. 7B is a side view of semiconductor substrate 52 including singulated chips 92 according to one embodiment. In one embodiment, active surface 54 is in contact with carrier tape 71 and metallization layer 62 is oriented up relative to the illustration of FIG. 7B. First trenches 80 and second trenches 90 align and intersect such that chips 92 are singulated from semiconductor substrate 52 and retained by transfer tape 71. Chips 92 are coupled to transfer tape 71 in a manner that enables transportation and subsequent mounting of chips 92 to other electronic devices. FIG. 8A is a side view of a semiconductor carrier assembly 100 according to another embodiment. Semiconductor carrier assembly 100 includes a semiconductor substrate 102 coupled to a carrier 104. In one embodiment, semiconductor substrate 102 is coupled to carrier 104 by an adhesive deposited about a periphery 106 of assembly 100, although other forms of coupling substrate 102 to carrier 104 are also acceptable. In one embodiment, semiconductor substrate 102 includes a wafer 108 having an active surface 110 opposite a back side 112 and a metallization layer 114 coupled to back side 112. It is desired to dice or singulate semiconductor substrate 102 by cutting through metallization layer 114. However, metallization layer 114 forms an optical barrier to visualizing the kerf pattern on active surface 110 of semiconductor substrate 102. In addition, the metal of metallization layer 114 prevents other forms of optical visualization of active surface 110, including infrared imaging through semiconductor 102. FIG. 8B is a side view of semiconductor carrier assembly 100 including a dicing blade 120 oriented along the kerf pattern on active surface 110 of semiconductor substrate 102. In one embodiment, an edge portion 122 of metallization layer 114 is removed from semiconductor substrate 102. Removal of edge portion 122 enables visualization of at least a portion of the kerf pattern on active surface 110, which enables alignment of dicing blade 120 between the chips formed on active surface 11 0. For example, in one embodiment infrared imaging is projected through the edge portion 122 and through silicon wafer 108 to provide a view of a portion of the front side kerf pattern formed on active surface 110. Thereafter, semiconductor substrate 102 is aligned such that dicing blade 120 is oriented along the visualized kerf pattern on the active surface 110. Dicing blade 120 dices or cuts a set of first trenches 124 through metallization layer 114 and through a portion of silicon wafer 108. First trenches 124 are half-cut diced through semiconductor substrate 102 such that metallization layer 114 is diced first, which has been found to minimize or eliminate the formation of metal burrs. FIG. 8C is a side view of semiconductor carrier assembly 100 coupled to a clamp assembly 130 according to one embodiment. In one embodiment, metallization layer 114 is adhesively coupled to a flexible film 132 of clamp assembly 130 such that carrier 104 is oriented upwards. FIG. 8D is a side view of carrier assembly 100 shown in FIG. 8C. In one embodiment, a cut line 134 is formed along the edge of semiconductor substrate 102 such that adhesive 106 at the periphery of assembly 100 is removed/separated. In one embodiment, a cut line 134 is formed by laser cutting, although other forms of providing cut line 134 are also acceptable. After cut line 134 is provided on assembly 100, carrier 104 is removed from semiconductor substrate 102 to expose active surface 110. FIG. 8E is a side view of semiconductor substrate 102 coupled to film 132 of clamp 130. Active surface 110 is oriented up and the chips and kerf on active surface are visible. First trenches 124 diced into metallization layer 114 are oriented down adjacent to film 132. In one embodiment, a wide dicing blade 140a dices a street along kerf of active surface 110 of semiconductor substrate 102 to form second trenches 144a that are aligned with first trenches 124. In one embodiment, wide dicing blade 140a has a width of between about 50-70 micrometers, preferably the width of wide dicing blade 140a is about 60 micrometers. In another embodiment, a thin dicing blade 140b dices a street along kerf of active surface 110 of semiconductor substrate 102 to form second trenches 144b that are aligned with first trenches 124. In one embodiment, thin dicing blade 140b has a width of between about 10-30 micrometers, and preferably thin dicing blade 140b has a width of about 20 micrometers. Although both dicing blades 140a, 140b are illustrated, it is to be understood that dicing of semiconductor substrate 102 is accomplished by employing one of the illustrated dicing blades. Embodiments provided above in FIGS. 8A-8E provide half-cut dicing part way into a metallized back side of a semiconductor substrate with a process that reduces or eliminates the formation of metal burrs. Cutting first trenches 124 into metallization layer 114 provides an efficient process for singulating chips from a semiconductor substrate that saves at least one processing step. FIG. 9A is a side view of a thick semiconductor substrate 150 according to another embodiment. Semiconductor substrate 150 includes a silicon wafer 152 including an active surface 154 opposite a back side 156 and a metallization layer 158 coupled to back side 156. In one embodiment, semiconductor substrate 150 has a thickness H of between about 600-800 micrometers, and typically semiconductor substrate 150 has a thickness H of about 725 micrometers. In one embodiment, semiconductor substrate 150 is half-cut diced through metallization layer 158 in a manner that minimizes or eliminates the formation of metal burrs and/or cracks in silicon wafer 152. FIG. 9B is a side view of semiconductor substrate 150 including an edge portion 162 of metallization layer 158 that has been removed to enable visualization of a front side kerf formed on active surface 154. In one embodiment, edge portion 162 of metallization layer 158 is removed down to back side 156 to enable infrared visualization of the front side kerf formed on active surface 154. In this manner, a dicing blade 170 is oriented relative to metallization layer 158 and in alignment with front side kerf on active surface 154, which enables alignment for cutting of a first set of trenches. In one embodiment, a dicing blade 170 half-cut dices a set of first trenches 172 through metallization layer 158 and into a portion of silicon wafer 152. In one embodiment, first trenches 172 are diced through metallization layer 158 to a thickness of H1. In one embodiment, thickness H1 of first trenches 172 has a depth of between about 50-100 micrometers leaving a solid thickness H2 of silicon wafer 152. In one embodiment, thickness H2 provides stable silicon having a thickness of about 600 micrometers. FIG. 9C is a side view of semiconductor substrate 150 coupled to a thin film 182 of clamp 180. In one embodiment, metallization layer 158 is coupled to thin film 182 and active surface 154 including the visible front side kerf is oriented up. In one embodiment, a relatively thick and stable portion of silicon wafer 152 remains and is presented for dicing and singulation. In one embodiment, silicon wafer 152 has a thickness H2 of silicon that is easily diced by dicing blades 190a, 190b in a manner that resists cracking. In one embodiment, H2 has a thickness of between about 550-650 micrometers. In one embodiment, a thick dicing blade 190a dices a street along kerf of active surface 154 of silicon wafer 152 to form a second set of trenches 192a that align and intersect with first streets/trenches 172. Thick dicing blade 190a follows the front side kerf that is visible on active surface 154 and cuts streets 192a down to at least a thickness H2 such that second trenches 192a align with and meet first trenches 172. In one embodiment, thick dicing blade 190a is similar to wide dicing blade 140a (FIG. 8E) and has a width of about 60 micrometers. In another embodiment, a thin dicing blade 190b dices a street along kerf of active surface 154 of silicon wafer 152 to form second trenches 192b through silicon wafer 152. In one embodiment, thin dicing blade 190b is similar to thin dicing blade 140b (FIG. 8E) and has a thickness of about between 10-30 micrometers and is employed to cut a set of second trenches 192b through at least the thickness H2. Second trenches 192b are aligned and cut through first trenches 172 to singulate chips from semiconductor substrate 150. Embodiments provide the singulation a semiconductor substrate by aligning the un-diced metallized back side accurately with streets half-cut diced in the active side of a semiconductor substrate. In some embodiments, streets cut onto one side of the semiconductor substrate are transferred and aligned with the other, opposite side of the semiconductor substrate. Other embodiments provide cutting a first set of trenches into a semiconductor substrate through the metallized back side in a manner that minimizes or eliminates the formation and propagation of cracks through the silicon and minimizes or eliminates the creation of metal burrs. In one embodiment, an active surface of a semiconductor substrate is half-cut diced with first trenches that imprint a pattern onto a metallized back side. The imprinted pattern on the back side is subsequently aligned and diced with streets to singulate chips from the semiconductor substrate. In other embodiments, a portion of the metallized back side is removed to enable visual alignment of the metallized back side with the front side kerf. A first set of trenches is formed in the metallized back side with a minimum formation of burrs. A second set of trenches is formed in the active surface of the semiconductor substrate, where the second streets/trenches align with the first trenches cut through the metallized back side. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments that provide a method of sawing a semiconductor substrate. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.	H	67H01	185H01L	235	44
11627924	US20070123013A1-20070531	CONTROLLED PROCESS AND RESULTING DEVICE	ACCEPTED	20070519	20070531	[]	H01L21425	["H01L21425"]	7759217	20070126	20100720	438	455000	77782.0	LEE	HSIEN MING	[{"inventor_name_last": "HENLEY", "inventor_name_first": "FRANCOIS", "inventor_city": "Aptos", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Cheung", "inventor_name_first": "Nathan", "inventor_city": "Albany", "inventor_state": "CA", "inventor_country": "US"}]	A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.	1-51. (canceled) 52. A process for forming a film of material from a semiconductor substrate using a chemical source, the process comprising steps of: introducing particles through a surface of a semiconductor substrate to a selected depth underneath the surface, the particles being at a concentration at the selected depth to define a material to be removed above the selected depth; applying a chemical source to increase stress at the selected depth; and providing additional energy to a selected region of the semiconductor substrate to initiate a controlled cleaving action at the selected depth in the semiconductor substrate using a propagating cleave front to free a portion of the semiconductor material to be removed from the semiconductor substrate. 53. The process of claim 52 wherein the particles are derived from a source selected from the group consisting of hydrogen gas, helium gas, water vapor, methane, hydrogen compounds, and other light atomic mass particles. 54. The process of claim 52 wherein the particles are selected from the group consisting of neutral molecules, neutral atoms, charged molecules, charged atoms, and electrons. 55. The process of claim 52 wherein the particles are energetic. 56. The process of claim 55 wherein the energetic particles have sufficient kinetic energy to penetrate through the surface to the selected depth underneath the surface. 57. The process of claim 52 wherein the providing energy sustains the controlled cleaving action to remove the semiconductor material from the substrate to provide a film of material. 58. The process of claim 52 wherein the providing energy increases a controlled stress in the semiconductor material and sustains the controlled cleaving action to remove the semiconductor material from the substrate to provide a film of material. 59. The process of claim 52 wherein the introducing forms damage selected from the group consisting of atomic bond damage, bond substitution, weakening, and breaking bonds of the semiconductor substrate at the selected depth. 60. The process of claim 59 wherein the damage creates stress in the semiconductor substrate material. 61. The process of claim 59 wherein the damage reduces an ability of the semiconductor substrate material to withstand stress without a possibility of a cleaving of the substrate material. 62. The process of claim 52 wherein the propagating cleave front comprises a plurality of cleave fronts. 63. The process of claim 52 wherein the introducing causes stress of the semiconductor material region at the selected depth by a presence of the particles at the selected depth. 64. The process of claim 52 wherein the chemical source is selected from particles, fluids, gases, or liquids. 65. The process of claim 64 wherein the chemical source causes a chemical reaction. 66. The process of claim 64 wherein the chemical source is selected from the group consisting of a flood source, a time-varying source, a spatially varying source, and a continuous source. 67. The process of claim 52 wherein the introducing is a step(s) of beam line ion implantation. 68. The process of claim 52 wherein the introducing is a step(s) of plasma immersion ion implantation. 69. The process of claim 52 further comprising a step of joining the surface of the substrate to a surface of a target substrate to form a stacked assembly. 70. The process of claim 69 wherein the joining step is provided by applying an electrostatic pressure between the substrate and the target substrate. 71. The process of claim 70 wherein the joining step is provided by using an adhesive substance between the target substrate and the substrate. 72. The process of claim 70 wherein the joining step is provided by an activated surface between the target substrate and the substrate. 73. The process of claim 70 where in the joining step is provided by an interatomic bond between the target substrate and the substrate. 74. The process of claim 70 wherein the joining step is provided by a spin-on-glass between the target substrate and the substrate. 75. The process of claim 71 wherein the joining step is provided by a polyimide between the target substrate and the substrate. 76. The process of claim 52 wherein the semiconductor substrate is made of a material selected from the group consisting of silicon, silicon carbide, group IIUV material, plastic, ceramic material, monocrystalline silicon, polycrystalline silicon, amorphous silicon, and multi-layered substrate. 77. The process of claim 52 wherein the semiconductor substrate is a silicon substrate comprising an overlying layer of dielectric material, the selected depth being underneath the dielectric material. 78. The process of claim 77 wherein the dielectric material is selected from the group consisting of an oxide material, a nitride material, or an oxide/nitride material. 79. The process of claim 52 wherein the semiconductor substrate includes an overlying layer of conductive material. 80. The process of claim 79 wherein the conductive material is selected from the group consisting of a metal, a plurality of metal layers, aluminum, tungsten, titanium, titanium nitride, polycide, polysilicon, copper, indium tin oxide, silicide, platinum, gold, silver, and amorphous silicon. 81. The process of claim 52 wherein the step of introducing provides a substantially uniform distribution of particles along a plane of the material region at the selected depth. 82. The process of claim 81 wherein the substantially uniform distribution is a uniformity of less than about 5%.	<SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and device for cleaving a substrate in the fabrication of a silicon-on-insulator substrate for semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like. Craftsmen or more properly crafts-people have been building useful articles, tools, or devices using less useful materials for numerous years. In some cases, articles are assembled by way of smaller elements or building blocks. Alternatively, less useful articles are separated into smaller pieces to improve their utility. A common example of these articles to be separated include substrate structures, such as a glass plate, a diamond, a semiconductor substrate, and others. These substrate structures are often cleaved or separated using a variety of techniques. In some cases, the substrates can be separated using a saw operation. The saw operation generally relies upon a rotating blade or tool, which cuts through the substrate material to separate the substrate material into two pieces. This technique, however, is often extremely “rough” and cannot generally be used for providing precision separations in the substrate for the manufacture of fine tools and assemblies. Additionally, the saw operation often has difficulty separating or cutting extremely hard and/or brittle materials, such as diamond or glass. Accordingly, techniques have been developed to separate these hard and/or brittle materials using cleaving approaches. In diamond cutting, for example, an intense directional thermal/mechanical impulse is directed preferentially along a crystallographic plane of a diamond material. This thermal/mechanical impulse generally causes a cleave front to propagate along major crystallographic planes, where cleaving occurs when an energy level from the thermal/mechanical impulse exceeds the fracture energy level along the chosen crystallographic plane. In glass cutting, a scribe line using a tool is often impressed in a preferred direction on the glass material, which is generally amorphous in character. The scribe line causes a higher stress area surrounding the amorphous glass material. Mechanical force is placed on each side of the scribe line, which increases stress along the scribe line until the glass material fractures, preferably along the scribe line. This fracture completes the cleaving process of the glass, which can be used in a variety of applications, including households. Although the techniques described above are satisfactory, for the most part, as applied to cutting diamonds or household glass, they have severe limitations in the fabrication of small complex structures or precision workpieces. For instance, the above techniques are often “rough” and cannot be used with great precision in fabrication of small and delicate machine tools, electronic devices, or the like. Additionally, the above techniques may be useful for separating one large plane of glass from another, but are often ineffective for splitting off, shaving, or stripping a thin film of material from a larger substrate. Furthermore, the above techniques may often cause more than one cleave front, which join along slightly different planes, which is highly undesirable for precision cutting applications. From the above, it is seen that a technique for separating a thin film of material from a substrate which is cost effective and efficient is desirable.	<SOH> SUMMARY OF THE INVENTION <EOH>According to the present invention, an improved technique for removing a thin film of material from a substrate using a controlled cleaving action is provided. This technique allows an initiation of a cleaving process on a substrate using a single or multiple cleave region(s) through the use of controlled energy (e.g., spatial distribution) and selected conditions to allow an initiation of a cleave front(s) and to allow it to propagate through the substrate to remove a thin film of material from the substrate. In a specific embodiment, the present invention provides a process for forming a film of material from a donor substrate using a controlled cleaving process. The process includes a step of introducing energetic particles (e.g., charged or neutral molecules, atoms, or electrons having sufficient kinetic energy) through a surface of a donor substrate to a selected depth underneath the surface, where the particles are at a relatively high concentration to define a thickness of donor substrate material (e.g., thin film of detachable material) above the selected depth. To cleave the donor substrate material, the method provides energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate, whereupon the cleaving action is made using a propagating cleave front(s) to free the donor material from a remaining portion of the donor substrate. In most of the embodiments, a cleave is initiated by subjecting the material with sufficient energy to fracture the material in one region, causing a cleave front, without uncontrolled shattering or cracking. The cleave front formation energy (E c ) must often be made lower than the bulk material fracture energy (E mat ) at each region to avoid shattering or cracking the material. The directional energy impulse vector in diamond cutting or the scribe line in glass cutting are, for example, the means in which the cleave energy is reduced to allow the controlled creation and propagation of a cleave front. The cleave front is in itself a higher stress region and once created, its propagation requires a lower energy to further cleave the material from this initial region of fracture. The energy required to propagate the cleave front is called the cleave front propagation energy (E p ). The relationship can be expressed as: in-line-formulae description="In-line Formulae" end="lead"? E c =E p +[cleave front stress energy] in-line-formulae description="In-line Formulae" end="tail"? A controlled cleaving process is realized by reducing E p along a favored direction(s) above all others and limiting the available energy to below the E p of other undesired directions. In any cleave process, a better cleave surface finish occurs when the cleave process occurs through only one expanding cleave front, although multiple cleave fronts do work. Numerous benefits are achieved over pre-existing techniques using the present invention. In particular, the present invention uses controlled energy and selected conditions to preferentially cleave a thin film of material from a donor substrate which includes multi-material sandwiched films. This cleaving process selectively removes the thin film of material from the substrate while preventing a possibility of damage to the film or a remaining portion of the substrate. Accordingly, the remaining substrate portion can be re-used repeatedly for other applications. Additionally, the present invention uses a relatively low temperature during the controlled cleaving process of the thin film to reduce temperature excursions of the separated film, donor substrate, or multi-material films according to other embodiments. This lower temperature approach allows for more material and process latitude such as, for example, cleaving and bonding of materials having substantially different thermal expansion coefficients. In other embodiments, the present invention limits energy or stress in the substrate to a value below a cleave initiation energy, which generally removes a possibility of creating random cleave initiation sites or fronts. This reduces cleave damage (e.g., pits, crystalline defects, breakage, cracks, steps, voids, excessive roughness) often caused in pre-existing techniques. Moreover, the present invention reduces damage caused by higher than necessary stress or pressure effects and nucleation sites caused by the energetic particles as compared to pre-existing techniques. The present invention achieves these benefits and others in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.	CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority from the provisional patent application entitled A CONTROLLED CLEAVAGE PROCESS AND RESULTING DEVICE, filed May 12, 1997 and assigned Application No. 60/046,276, the disclosure of which is hereby incorporated in its entirety for all purposes. BACKGROUND OF THE INVENTION The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and device for cleaving a substrate in the fabrication of a silicon-on-insulator substrate for semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, photonic devices, piezoelectronic devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, flat panel displays (e.g., LCD, AMLCD), biological and biomedical devices, and the like. Craftsmen or more properly crafts-people have been building useful articles, tools, or devices using less useful materials for numerous years. In some cases, articles are assembled by way of smaller elements or building blocks. Alternatively, less useful articles are separated into smaller pieces to improve their utility. A common example of these articles to be separated include substrate structures, such as a glass plate, a diamond, a semiconductor substrate, and others. These substrate structures are often cleaved or separated using a variety of techniques. In some cases, the substrates can be separated using a saw operation. The saw operation generally relies upon a rotating blade or tool, which cuts through the substrate material to separate the substrate material into two pieces. This technique, however, is often extremely “rough” and cannot generally be used for providing precision separations in the substrate for the manufacture of fine tools and assemblies. Additionally, the saw operation often has difficulty separating or cutting extremely hard and/or brittle materials, such as diamond or glass. Accordingly, techniques have been developed to separate these hard and/or brittle materials using cleaving approaches. In diamond cutting, for example, an intense directional thermal/mechanical impulse is directed preferentially along a crystallographic plane of a diamond material. This thermal/mechanical impulse generally causes a cleave front to propagate along major crystallographic planes, where cleaving occurs when an energy level from the thermal/mechanical impulse exceeds the fracture energy level along the chosen crystallographic plane. In glass cutting, a scribe line using a tool is often impressed in a preferred direction on the glass material, which is generally amorphous in character. The scribe line causes a higher stress area surrounding the amorphous glass material. Mechanical force is placed on each side of the scribe line, which increases stress along the scribe line until the glass material fractures, preferably along the scribe line. This fracture completes the cleaving process of the glass, which can be used in a variety of applications, including households. Although the techniques described above are satisfactory, for the most part, as applied to cutting diamonds or household glass, they have severe limitations in the fabrication of small complex structures or precision workpieces. For instance, the above techniques are often “rough” and cannot be used with great precision in fabrication of small and delicate machine tools, electronic devices, or the like. Additionally, the above techniques may be useful for separating one large plane of glass from another, but are often ineffective for splitting off, shaving, or stripping a thin film of material from a larger substrate. Furthermore, the above techniques may often cause more than one cleave front, which join along slightly different planes, which is highly undesirable for precision cutting applications. From the above, it is seen that a technique for separating a thin film of material from a substrate which is cost effective and efficient is desirable. SUMMARY OF THE INVENTION According to the present invention, an improved technique for removing a thin film of material from a substrate using a controlled cleaving action is provided. This technique allows an initiation of a cleaving process on a substrate using a single or multiple cleave region(s) through the use of controlled energy (e.g., spatial distribution) and selected conditions to allow an initiation of a cleave front(s) and to allow it to propagate through the substrate to remove a thin film of material from the substrate. In a specific embodiment, the present invention provides a process for forming a film of material from a donor substrate using a controlled cleaving process. The process includes a step of introducing energetic particles (e.g., charged or neutral molecules, atoms, or electrons having sufficient kinetic energy) through a surface of a donor substrate to a selected depth underneath the surface, where the particles are at a relatively high concentration to define a thickness of donor substrate material (e.g., thin film of detachable material) above the selected depth. To cleave the donor substrate material, the method provides energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate, whereupon the cleaving action is made using a propagating cleave front(s) to free the donor material from a remaining portion of the donor substrate. In most of the embodiments, a cleave is initiated by subjecting the material with sufficient energy to fracture the material in one region, causing a cleave front, without uncontrolled shattering or cracking. The cleave front formation energy (Ec) must often be made lower than the bulk material fracture energy (Emat) at each region to avoid shattering or cracking the material. The directional energy impulse vector in diamond cutting or the scribe line in glass cutting are, for example, the means in which the cleave energy is reduced to allow the controlled creation and propagation of a cleave front. The cleave front is in itself a higher stress region and once created, its propagation requires a lower energy to further cleave the material from this initial region of fracture. The energy required to propagate the cleave front is called the cleave front propagation energy (Ep). The relationship can be expressed as: Ec=Ep+[cleave front stress energy] A controlled cleaving process is realized by reducing Ep along a favored direction(s) above all others and limiting the available energy to below the Ep of other undesired directions. In any cleave process, a better cleave surface finish occurs when the cleave process occurs through only one expanding cleave front, although multiple cleave fronts do work. Numerous benefits are achieved over pre-existing techniques using the present invention. In particular, the present invention uses controlled energy and selected conditions to preferentially cleave a thin film of material from a donor substrate which includes multi-material sandwiched films. This cleaving process selectively removes the thin film of material from the substrate while preventing a possibility of damage to the film or a remaining portion of the substrate. Accordingly, the remaining substrate portion can be re-used repeatedly for other applications. Additionally, the present invention uses a relatively low temperature during the controlled cleaving process of the thin film to reduce temperature excursions of the separated film, donor substrate, or multi-material films according to other embodiments. This lower temperature approach allows for more material and process latitude such as, for example, cleaving and bonding of materials having substantially different thermal expansion coefficients. In other embodiments, the present invention limits energy or stress in the substrate to a value below a cleave initiation energy, which generally removes a possibility of creating random cleave initiation sites or fronts. This reduces cleave damage (e.g., pits, crystalline defects, breakage, cracks, steps, voids, excessive roughness) often caused in pre-existing techniques. Moreover, the present invention reduces damage caused by higher than necessary stress or pressure effects and nucleation sites caused by the energetic particles as compared to pre-existing techniques. The present invention achieves these benefits and others in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-11 are simplified diagrams illustrating a controlled cleaving technique according to embodiments of the present invention; FIG. 12A is a simplified diagram illustrating a controlled cleaving technique using dynamic pressure embodied as a high-pressure jet of fluid or gas to separate a thin film of material from a donor wafer according to another embodiment of the present invention; FIG. 12B is a simplified diagram illustrating a controlled cleaving technique using static pressure to separate a thin film of material from a donor wafer according to another embodiment of the present invention; FIG. 13 is a simplified diagram illustrating the use of static fluid pressure to separate a thin film of material from a donor wafer; and FIGS. 14-18 are simplified cross-sectional view diagrams illustrating a method of forming a silicon-on-insulator substrate according to the present invention. DESCRIPTION OF THE SPECIFIC EMBODIMENT The present invention provides a technique for removing a thin film of material from a substrate while preventing a possibility of damage to the thin material film and/or a remaining portion of the substrate. The thin film of material is attached to or can be attached to a target substrate to form, for example, a silicon-on-insulator wafer. The thin film of material can also be used for a variety of other applications. The invention will be better understood by reference to the Figs. and the descriptions below. 1. Controlled Cleaving Techniques FIG. 1 is a simplified cross-sectional view diagram of a substrate 10 according to the present invention. The diagram is merely an illustration and should not limit the scope of the claims herein. As merely an example, substrate 10 is a silicon wafer which includes a material region 12 to be removed, which is a thin relatively uniform film derived from the substrate material. The silicon wafer 10 includes a top surface 14, a bottom surface 16, and a thickness 18. Substrate 10 also has a first side (side 1) and a second side (side 2) (which are also referenced below in the Figs.). Material region 12 also includes a thickness 20, within the thickness 18 of the silicon wafer. The present invention provides a novel technique for removing the material region 12 using the following sequence of steps. Selected energetic particles implant 22 through the top surface 14 of the silicon wafer to a selected depth 24, which defines the thickness 20 of the material region 12, termed the “thin film” of material. A variety of techniques can be used to implant the energetic particles into the silicon wafer. These techniques include ion implantation using, for example, beam line ion implantation equipment manufactured from companies such as Applied Materials, Eaton Corporation, Varian, and others. Alternatively, implantation occurs using a plasma immersion ion implantation (“PIII”) technique. Examples of plasma immersion ion implantation techniques are described in “Recent Applications of Plasma Immersion Ion Implantation,” Paul K. Chu, Chung Chan, and Nathan W. Cheung, SEMICONDUCTOR INTERNATIONAL, pp. 165-172, June 1996, and “Plasma Immersion Ion Implantation—A Fledgling Technique for Semiconductor Processing,”, P. K. Chu, S. Qin, C. Chan, N. W. Cheung, and L. A. Larson, MATERIALS SCIENCE AND ENGINEERING REPORTS: A REVIEW JOURNAL, pp. 207-280, Vol. R17, Nos. 6-7, (Nov. 30, 1996), which are both hereby incorporated by reference for all purposes. Of course, techniques used depend upon the application. Depending upon the application, smaller mass particles are generally selected to reduce a possibility of damage to the material region 12. That is, smaller mass particles easily travel through the substrate material to the selected depth without substantially damaging the material region that the particles traverse through. For example, the smaller mass particles (or energetic particles) can be almost any charged (e.g., positive or negative) and/or neutral atoms or molecules, or electrons, or the like. In a specific embodiment, the particles can be neutral and/or charged particles including ions such as ions of hydrogen and its isotopes, rare gas ions such as helium and its isotopes, and neon. The particles can also be derived from compounds such as gases, e.g., hydrogen gas, water vapor, methane, and hydrogen compounds, and other light atomic mass particles. Alternatively, the particles can be any combination of the above particles, and/or ions and/or molecular species and/or atomic species. The particles generally have sufficient kinetic energy to penetrate through the surface to the selected depth underneath the surface. Using hydrogen as the implanted species into the silicon wafer as an example, the implantation process is performed using a specific set of conditions. Implantation dose ranges from about 1015 to about 1018 atoms/cm2, and preferably the dose is greater than about 1016 atoms/cm2. Implantation energy ranges from about 1 KeV to about 1 MeV, and is generally about 50 KeV. Implantation temperature ranges from about −200 to about 600° C., and is preferably less than about 400° C. to prevent a possibility of a substantial quantity of hydrogen ions from diffusing out of the implanted silicon wafer and annealing the implanted damage and stress. The hydrogen ions can be selectively introduced into the silicon wafer to the selected depth at an accuracy of about +/−0.03 to +/−0.05 microns. Of course, the type of ion used and process conditions depend upon the application. Effectively, the implanted particles add stress or reduce fracture energy along a plane parallel to the top surface of the substrate at the selected depth. The energies depend, in part, upon the implantation species and conditions. These particles reduce a fracture energy level of the substrate at the selected depth. This allows for a controlled cleave along the implanted plane at the selected depth. Implantation can occur under conditions such that the energy state of the substrate at all internal locations is insufficient to initiate a non-reversible fracture (i.e., separation or cleaving) in the substrate material. It should be noted, however, that implantation does generally cause a certain amount of defects (e.g., micro-detects) in the substrate that can typically at least partially be repaired by subsequent heat treatment, e.g., thermal annealing or rapid thermal annealing. FIG. 2 is a simplified energy diagram 200 along a cross-section of the implanted substrate 10 according to the present invention. The diagram is merely an illustration and should not limit the scope of the claims herein. The simplified diagram includes a vertical axis 201 that represents an energy level (E) (or additional energy) to cause a cleave in the substrate. A horizontal axis 203 represents a depth or distance from the bottom of the wafer to the top of the wafer. After implanting particles into the wafer, the substrate has an average cleave energy represented as E 205, which is the amount of energy needed to cleave the wafer along various cross-sectional regions along the wafer depth. The cleave energy (Ec) is equal to the bulk material fracture energy (Emat) in non-implanted regions. At the selected depth 20, energy (Ecz) 207 is lower since the implanted particles essentially break or weaken bonds in the crystalline structure (or increase stress caused by a presence of particles also contributing to lower energy (Ecz) 207 of the substrate) to lower the amount of energy needed to cleave the substrate at the selected depth. The present invention takes advantage of the lower energy (or increased stress) at the selected depth to cleave the thin film in a controlled manner. Substrates, however, are not generally free from defects or “weak” regions across the possible cleave front or selected depth zo after the implantation process. In these cases, the cleave generally cannot be controlled, since they are subject to random variations such as bulk material non-uniformities, built-in stresses, defects, and the like. FIG. 3 is a simplified energy diagram 300 across a cleave front for the implanted substrate 10 having these defects. The diagram 300 is merely an illustration and should not limit the scope of the claims herein. The diagram has a vertical axis 301 which represents additional energy (E) and a horizontal axis 303 which represents a distance from side 1 to side 2 of the substrate, that is, the horizontal axis represents regions along the cleave front of the substrate. As shown, the cleave front has two regions 305 and 307 represented as region 1 and region 2, respectively, which have cleave energies less than the average cleave energy (Ecz) 207 (possibly due to a higher concentration of defects or the like). Accordingly, it is highly likely that the cleave process begins at one or both of the above regions, since each region has a lower cleave energy than surrounding regions. An example of a cleave process for the substrate illustrated by the above Fig. is described as follows with reference to FIG. 4. FIG. 4 is a simplified top-view diagram 400 of multiple cleave fronts 401, 403 propagating through the implanted substrate. The cleave fronts originate at “weaker” regions in the cleave plane, which specifically includes regions 1 and 2. The cleave fronts originate and propagate randomly as shown by the arrows. A limitation with the use of random propagation among multiple cleave fronts is the possibility of having different cleave fronts join along slightly different planes or the possibility of forming cracks, which is described in more detail below. FIG. 5 is a simplified cross-sectional view 500 of a film cleaved from a wafer having multiple cleave fronts at, for example, regions 1 305 and 2 307. This diagram is merely an illustration and should not limit the scope of the claims herein. As shown, the cleave from region 1 joined with the cleave from region 2 at region 3 309, which is defined along slightly different planes, may initiate a secondary cleave or crack 311 along the film. Depending upon the magnitude of the difference 313, the film may not be of sufficient quality for use in manufacture of substrates for integrated circuits or other applications. A substrate having crack 311 generally cannot be used for processing. Accordingly, it is generally undesirable to cleave a wafer using multiple fronts in a random manner. An example of a technique which may form multiple cleave fronts in a random manner is described in U.S. Pat. No. 5,374,564, which is in the name of Michel Bruel (“Bruel”), and assigned to Commissariat A l'Energie Atomique in France. Bruel generally describes a technique for cleaving an implanted wafer by global thermal treatment (i.e., thermally treating the entire plane of the implant) using thermally activated diffusion. Global thermal treatment of the substrate generally causes an initiation of multiple cleave fronts which propagate independently. In general, Bruel discloses a technique for an “uncontrollable” cleaving action by way of initiating and maintaining a cleaving action by a global thermal source, which may produce undesirable results. These undesirable results include potential problems such as an imperfect joining of cleave fronts, an excessively rough surface finish on the surface of the cleaved material since the energy level for maintaining the cleave exceeds the amount required, and many others. The present invention overcomes the formation of random cleave fronts by a controlled distribution or selective positioning of energy on the implanted substrate. FIG. 6 is a simplified cross-sectional view of an implanted substrate 10 using selective positioning of cleave energy according to the present invention. This diagram is merely an illustration, and should not limit the scope of the claims herein. The implanted wafer undergoes a step of selective energy placement or positioning or targeting which provides a controlled cleaving action of the material region 12 at the selected depth. The impulse or impulses are provided using energy sources. Examples of sources include, among others, a chemical source, a mechanical source, an electrical source, and a thermal sink or source. The chemical source can include particles, fluids, gases, or liquids. These sources can also include a chemical reaction to increase stress in the material region. The chemical source is introduced as flood, time-varying, spatially varying, or continuous. In other embodiments, a mechanical source is derived from rotational, translational, compressional, expansional, or ultrasonic energies. The mechanical source can be introduced as flood, time-varying, spatially varying, or continuous. In further embodiments, the electrical source is selected from an applied voltage or an applied electro-magnetic field, which is introduced as flood, time-varying, spatially varying, or continuous. In still further embodiments, the thermal source or sink is selected from radiation, convection, or conduction. This thermal source can be selected from, among others, a photon beam, a fluid jet, a liquid jet, a gas jet, an electro/magnetic field, an electron beam, a thermoelectric heating, a furnace, and the like. The thermal sink can be selected from a fluid jet, a liquid jet, a gas jet, a cryogenic fluid, a super-cooled liquid, a thermoelectric cooling means, an electro/magnetic field, and others. Similar to the previous embodiments, the thermal source is applied as flood, time-varying, spatially varying, or continuous. Still further, any of the above embodiments can be combined or even separated, depending upon the application. Of course, the type of source used depends upon the application. In a specific embodiment, the present invention provides a controlled-propagating cleave. The controlled-propagating cleave uses multiple successive impulses to initiate and perhaps propagate a cleaving process 700, as illustrated by FIG. 7. This diagram is merely an illustration, and should not limit the scope of the claims herein. As shown, the impulse is directed at an edge of the substrate, which propagates a cleave front toward the center of the substrate to remove the material layer from the substrate. In this embodiment, a source applies multiple pulses (i.e., pulse 1, 2, and 3) successively to the substrate. Pulse 1 701 is directed to an edge 703 of the substrate to initiate the cleave action. Pulse 2 705 is also directed at the edge 707 on one side of pulse 1 to expand the cleave front. Pulse 3 709 is directed to an opposite edge 711 of pulse 1 along the expanding cleave front to further remove the material layer from the substrate. The combination of these impulses or pulses provides a controlled cleaving action 713 of the material layer from the substrate. FIG. 8 is a simplified illustration of selected energies 800 from the pulses in the preceding embodiment for the controlled-propagating cleave. This diagram is merely an illustration, and should not limit the scope of the claims herein. As shown, the pulse 1 has an energy level which exceeds average cleaving energy (E), which is the necessary energy for initiating the cleaving action. Pulses 2 and 3 are made using lower energy levels along the cleave front to maintain or sustain the cleaving action. In a specific embodiment, the pulse is a laser pulse where an impinging beam heats a selected region of the substrate through a pulse and a thermal pulse gradient causes supplemental stresses which together exceed cleave formation or propagation energies, which create a single cleave front. In preferred embodiments, the impinging beam heats and causes a thermal pulse gradient simultaneously, which exceeds cleave energy formation or propagation energies. More preferably, the impinging beam cools and causes a thermal pulse gradient simultaneously, which exceeds cleave energy formation or propagation energies. Optionally, a built-in energy state of the substrate or stress can be globally raised toward the energy level necessary to initiate the cleaving action, but not enough to initiate the cleaving action before directing the multiple successive impulses to the substrate according to the present invention. The global energy state of the substrate can be raised or lowered using a variety of sources such as chemical, mechanical, thermal (sink or source), or electrical, alone or in combination. The chemical source can include a variety such as particles, fluids, gases, or liquids. These sources can also include chemical reaction to increase stress in the material region. The chemical source is introduced as flood, time-varying, spatially varying, or continuous. In other embodiments, a mechanical source is derived from rotational, translational, compressional, expansional, or ultrasonic energies. The mechanical source can be introduced as flood, time-varying, spatially varying, or continuous. In further embodiments, the electrical source is selected from an applied voltage or an applied electro-magnetic field, which is introduced as flood, time-varying, spatially varying, or continuous. In still further embodiments, the thermal source or sink is selected from radiation, convection, or conduction. This thermal source can be selected from, among others, a photon beam, a fluid jet, a liquid jet, a gas jet, an electro/magnetic field, an electron beam, a thermoelectric heating, and a furnace. The thermal sink can be selected from a fluid jet, a liquid jet, a gas jet, a cryogenic fluid, a super-cooled liquid, a thermoelectric cooling means, an electro/magnetic field, and others. Similar to the previous embodiments, the thermal source is applied as flood, time-varying, spatially varying, or continuous. Still further, any of the above embodiments can be combined or even separated, depending upon the application. Of course, the type of source used also depends upon the application. As noted, the global source increases a level of energy or stress in the material region without initiating a cleaving action in the material region before providing energy to initiate the controlled cleaving action. In a specific embodiment, an energy source elevates an energy level of the substrate cleave plane above its cleave front propagation energy but is insufficient to cause self-initiation of a cleave front. In particular, a thermal energy source or sink in the form of heat or lack of heat (e.g., cooling source) can be applied globally to the substrate to increase the energy state or stress level of the substrate without initiating a cleave front. Alternatively, the energy source can be electrical, chemical, or mechanical. A directed energy source provides an application of energy to a selected region of the substrate material to initiate a cleave front which self-propagates through the implanted region of the substrate until the thin film of material is removed. A variety of techniques can be used to initiate the cleave action. These techniques are described by way of the Figs. below. FIG. 9 is a simplified illustration of an energy state 900 for a controlled cleaving action using a single controlled source according to an aspect of the present invention. This diagram is merely an illustration, and should not limit the scope of the claims herein. In this embodiment, the energy level or state of the substrate is raised using a global energy source above the cleave front propagation energy state, but is lower than the energy state necessary to initiate the cleave front. To initiate the cleave front, an energy source such as a laser directs a beam in the form of a pulse at an edge of the substrate to initiate the cleaving action. Alternatively, the energy source can be a cooling fluid (e.g., liquid, gas) that directs a cooling medium in the form of a pulse at an edge of the substrate to initiate the cleaving action. The global energy source maintains the cleaving action which generally requires a lower energy level than the initiation energy. An alternative aspect of the invention is illustrated by FIGS. 10 and 11. FIG. 10 is a simplified illustration of an implanted substrate 1000 undergoing rotational forces 1001, 1003. This diagram is merely an illustration, and should not limit the scope of the claims herein. As shown, the substrate includes a top surface 1005, a bottom surface 1007, and an implanted region 1009 at a selected depth. An energy source increases a global energy level of the substrate using a light beam or heat source to a level above the cleave front propagation energy state, but lower than the energy state necessary to initiate the cleave front. The substrate undergoes a rotational force turning clockwise 1001 on top surface and a rotational force turning counter-clockwise 1003 on the bottom surface which creates stress at the implanted region 1009 to initiate a cleave front. Alternatively, the top surface undergoes a counter-clockwise rotational force and the bottom surface undergoes a clockwise rotational force. Of course, the direction of the force generally does not matter in this embodiment. FIG. 11 is a simplified diagram of an energy state 1100 for the controlled cleaving action using the rotational force according to the present invention. This diagram is merely an illustration, and should not limit the scope of the claims herein. As previously noted, the energy level or state of the substrate is raised using a global energy source (e.g., thermal, beam) above the cleave front propagation energy state, but is lower than the energy state necessary to initiate the cleave front. To initiate the cleave front, a mechanical energy means such as rotational force applied to the implanted region initiates the cleave front. In particular, rotational force applied to the implanted region of the substrates creates zero stress at the center of the substrate and greatest at the periphery, essentially being proportional to the radius. In this example, the central initiating pulse causes a radially expanding cleave front to cleave the substrate. The removed material region provides a thin film of silicon material for processing. The silicon material possesses limited surface roughness and desired planarity characteristics for use in a silicon-on-insulator substrate. In certain embodiments, the surface roughness of the detached film has features that are less than about 60 nm, or less than about 40 nm, or less than about 20 nm. Accordingly, the present invention provides thin silicon films which can be smoother and more uniform than pre-existing techniques. In a specific embodiment, the energy source can be a fluid jet that is pressurized (e.g., compressional) according to an embodiment of the present invention. FIG. 12A shows a simplified cross-sectional view diagram of a fluid jet from a fluid nozzle 608 used to perform the controlled cleaving process according to an embodiment of the present invention. The fluid jet 607 (or liquid jet or gas jet) impinges on an edge region of substrate 10 to initiate the controlled cleaving process. The fluid jet from a compressed or pressurized fluid source is directed to a region at the selected depth 603 to cleave a thickness of material region 12 from substrate 10 using force, e.g., mechanical, chemical, thermal. As shown, the fluid jet separates substrate 10 into two regions, including region 609 and region 611 that separate from each other at selected depth 603. The fluid jet can also be adjusted to initiate and maintain the controlled cleaving process to separate material 12 from substrate 10. Depending upon the application, the fluid jet can be adjusted in direction, location, and magnitude to achieve the desired controlled cleaving process. The fluid jet can be a liquid jet or a gas jet or a combination of liquid and gas. The fluid jet can separate a thin film from the substrate at ambient (i.e. room) temperature, but the substrate and/or jet can also be heated or cooled to facilitate the separation process. In a preferred embodiment, the energy source can be a compressional source such as, for example, compressed fluid that is static. FIG. 12B shows a simplified cross-sectional view diagram of a compressed fluid source 607 according to an embodiment of the present invention. The compressed fluid source 607 (e.g., pressurized liquid, pressurized gas) is applied to a sealed chamber 621, which surrounds a periphery or edge of the substrate 10. As shown, the chamber is enclosed by device 623, which is sealed by, for example, O-rings 625 or the like, and which surrounds the outer edge of the substrate. The chamber has a pressure maintained at PC that is applied to the edge region of substrate 10 to initiate the controlled cleaving process at the selected depth of implanted material. The outer surface or face of the substrate is maintained at pressure PA which can be ambient pressure e.g., 1 atmosphere or less. A pressure differential exists between the pressure in the chamber, which is higher, and the ambient pressure. The pressure difference applies force to the implanted region at the selected depth 603. The implanted region at the selected depth is structurally weaker than surrounding regions, including any bonded regions. Force is applied via the pressure differential until the controlled cleaving process is initiated. The controlled cleaving process separates the thickness of material 609 from substrate material 611 to split the thickness of material from the substrate material at the selected depth. Additionally, pressure PC forces material region 12 to separate by a “prying action” from substrate material 611. During the cleaving process, the pressure in the chamber can also be adjusted to initiate and maintain the controlled cleaving process to separate material 12 from substrate 10. Depending upon the application, the pressure can be adjusted in magnitude to achieve the desired controlled cleaving process. The fluid pressure can be derived from a liquid or a gas or a combination of liquid and gas. Optionally, a mechanical force, as from a pin or blade, may be applied to the edge of the implanted region to initiate the cleaving process, which typically reduces the maximum pressure differential required between the chamber and the ambient. In a preferred embodiment, the present invention is practiced at temperatures that are lower than those used by pre-existing techniques. In particular, the present invention does not require increasing the entire substrate temperature to initiate and sustain the cleaving action as pre-existing techniques. In some embodiments for silicon wafers and hydrogen implants, substrate temperature does not exceed about 400° C. during the cleaving process. Alternatively, substrate temperature does not exceed about 350° C. during the cleaving process. Alternatively, substrate temperature is kept substantially below implanting temperatures via a thermal sink, e.g., cooling fluid, cryogenic fluid. Accordingly, the present invention reduces a possibility of unnecessary damage from an excessive release of energy from random cleave fronts, which generally improves surface quality of a detached film(s) and/or the substrate(s). Accordingly, the present invention provides resulting films on substrates at higher overall yields and quality. The above embodiments are described in terms of cleaving a thin film of material from a substrate. The substrate, however, can be disposed on a workpiece such as a stiffener or the like before the controlled cleaving process. The workpiece joins to a top surface or implanted surface of the substrate to provide structural support to the thin film of material during controlled cleaving processes. The workpiece can be joined to the substrate using a variety of bonding or joining techniques, e.g., electro-statics, adhesives, interatomic. Some of these bonding techniques are described herein. The workpiece can be made of a dielectric material (e.g., quartz, glass, sapphire, silicon nitride, silicon dioxide), a conductive material (silicon, silicon carbide, polysilicon, group III/V materials, metal), and plastics (e.g., polyimide-based materials). Of course, the type of workpiece used will depend upon the application. Alternatively, the substrate having the film to be detached can be temporarily disposed on a transfer substrate such as a stiffener or the like before the controlled cleaving process. The transfer substrate joins to a top surface or implanted surface of the substrate having the film to provide structural support to the thin film of material during controlled cleaving processes. The transfer substrate can be temporarily joined to the substrate having the film using a variety of bonding or joining techniques, e.g., electro-statics, adhesives, interatomic. Some of these bonding techniques are described herein. The transfer substrate can be made of a dielectric material (e.g., quartz, glass, sapphire, silicon nitride, silicon dioxide), a conductive material (silicon, silicon carbide, polysilicon, group III/V materials, metal), and plastics (e.g., polyimide-based materials). Of course, the type of transfer substrate used will depend upon the application. Additionally, the transfer substrate can be used to remove the thin film of material from the cleaved substrate after the controlled cleaving process. 2. Silicon-On-Insulator Process A process for fabricating a silicon-on-insulator substrate according to the present invention may be briefly outlined as follows: (1) Provide a donor silicon wafer (which may be coated with a dielectric material); (2) Introduce particles into the silicon wafer to a selected depth to define a thickness of silicon film; (3) Provide a target substrate material (which may be coated with a dielectric material); (4) Bond the donor silicon wafer to the target substrate material by joining the implanted face to the target substrate material; (5) Increase global stress (or energy) of implanted region at selected depth without initiating a cleaving action (optional); (6) Provide stress (or energy) to a selected region of the bonded substrates to initiate a controlled cleaving action at the selected depth; (7) Provide additional energy to the bonded substrates to sustain the controlled cleaving action to free the thickness of silicon film from the silicon wafer (optional); (8) Complete bonding of donor silicon wafer to the target substrate; and (9) Polish a surface of the thickness of silicon film. The above sequence of steps provides a step of initiating a controlled cleaving action using an energy applied to a selected region(s) of a multi-layered substrate structure to form a cleave front(s) according to the present invention. This initiation step begins a cleaving process in a controlled manner by limiting the amount of energy applied to the substrate. Further propagation of the cleaving action can occur by providing additional energy to selected regions of the substrate to sustain the cleaving action, or using the energy from the initiation step to provide for further propagation of the cleaving action. This sequence of steps is merely an example and should not limit the scope of the claims defined herein. Further details with regard to the above sequence of steps are described in below in references to the Figs. FIGS. 14-19 are simplified cross-sectional view diagrams of substrates undergoing a fabrication process for a silicon-on-insulator wafer according to the present invention. The process begins by providing a semiconductor substrate similar to the silicon wafer 2100, as shown by FIG. 14. Substrate or donor includes a material region 2101 to be removed, which is a thin relatively uniform film derived from the substrate material. The silicon wafer includes a top surface 2103, a bottom surface 2105, and a thickness 2107. Material region also includes a thickness (z0), within the thickness 2107 of the silicon wafer. Optionally, a dielectric layer 2102 (e.g., silicon nitride, silicon oxide, silicon oxynitride) overlies the top surface of the substrate. The present process provides a novel technique for removing the material region 2101 using the following sequence of steps for the fabrication of a silicon-on-insulator wafer. Selected energetic particles 2109 implant through the top surface of the silicon wafer to a selected depth, which defines the thickness of the material region, termed the thin film of material. As shown, the particles have a desired concentration 2111 at the selected depth (z0). A variety of techniques can be used to implant the energetic particles into the silicon wafer. These techniques include ion implantation using, for example, beam line ion implantation equipment manufactured from companies such as Applied Materials, Eaton Corporation, Varian, and others. Alternatively, implantation occurs using a plasma immersion ion implantation (“PIII”) technique. Of course, techniques used depend upon the application. Depending upon the application, smaller mass particles are generally selected to reduce a possibility of damage to the material region. That is, smaller mass particles easily travel through the substrate material to the selected depth without substantially damaging the material region that the particles traversed through. For example, the smaller mass particles (or energetic particles) can be almost any charged (e.g., positive or negative) and/or neutral atoms or molecules, or electrons, or the like. In a specific embodiment, the particles can be neutral and/or charged particles including ions of hydrogen and its isotopes, rare gas ions such as helium and its isotopes, and neon. The particles can also be derived from compounds such as gases, e.g., hydrogen gas, water vapor, methane, and other hydrogen compounds, and other light atomic mass particles. Alternatively, the particles can be any combination of the above particles, and/or ions and/or molecular species and/or atomic species. The process uses a step of joining the implanted silicon wafer to a workpiece 2200 or target wafer, as illustrated in FIG. 15. The workpiece may also be a variety of other types of substrates such as those made of a dielectric material (e.g., quartz, glass, silicon nitride, silicon dioxide), a conductive material (silicon, polysilicon, group III/V materials, metal), and plastics (e.g., polyimide-based materials). In the present example, however, the workpiece is a silicon wafer. In a specific embodiment, the silicon wafers are joined or fused together using a low temperature thermal step. The low temperature thermal process generally ensures that the implanted particles do not place excessive stress on the material region, which can produce an uncontrolled cleave action. In one aspect, the low temperature bonding process occurs by a self-bonding process. In particular, one wafer is stripped to remove oxidation therefrom (or one wafer is not oxidized). A cleaning solution treats the surface of the wafer to form O—H bonds on the wafer surface. An example of a solution used to clean the wafer is a mixture of H2O2—H2SO4. A dryer dries the wafer surfaces to remove any residual liquids or particles from the wafer surfaces. Self-bonding occurs by placing a face of the cleaned wafer against the face of an oxidized wafer. Alternatively, a self-bonding process occurs by activating one of the wafer surfaces to be bonded by plasma cleaning. In particular, plasma cleaning activates the wafer surface using a plasma derived from gases such as argon, ammonia, neon, water vapor, and oxygen. The activated wafer surface 2203 is placed against a face of the other wafer, which has a coat of oxidation 2205 thereon. The wafers are in a sandwiched structure having exposed wafer faces. A selected amount of pressure is placed on each exposed face of the wafers to self-bond one wafer to the other. Alternatively, an adhesive disposed on the wafer surfaces is used to bond one wafer onto the other. The adhesive includes an epoxy, polyimide-type materials, and the like. Spin-on-glass layers can be used to bond one wafer surface onto the face of another. These spin-on-glass (“SOG”) materials include, among others, siloxanes or silicates, which are often mixed with alcohol-based solvents or the like. SOG can be a desirable material because of the low temperatures (e.g., 150 to 250° C.) often needed to cure the SOG after it is applied to surfaces of the wafers. Alternatively, a variety of other low temperature techniques can be used to join the donor wafer to the target wafer. For instance, an electro-static bonding technique can be used to join the two wafers together. In particular, one or both wafer surface(s) is charged to attract to the other wafer surface. Additionally, the donor wafer can be fused to the target wafer using a variety of commonly known techniques. Of course, the technique used depends upon the application. After bonding the wafers into a sandwiched structure 2300, as shown in FIG. 16, the method includes a controlled cleaving action to remove the substrate material to provide a thin film of substrate material 2101 overlying an insulator 2305 the target silicon wafer 2201. The controlled-cleaving occurs by way of selective energy placement or positioning or targeting 2301, 2303 of energy sources onto the donor and/or target wafers. For instance, an energy impulse(s) can be used to initiate the cleaving action. The impulse (or impulses) is provided using an energy source which include, among others, a mechanical source, a chemical source, a thermal sink or source, and an electrical source. The controlled cleaving action is initiated by way of any of the previously noted techniques and others and is illustrated by way of FIG. 16. For instance, a process for initiating the controlled cleaving action uses a step of providing energy 2301, 2303 to a selected region of the substrate to initiate a controlled cleaving action at the selected depth (z0) in the substrate, whereupon the cleaving action is made using a propagating cleave front to free a portion of the substrate material to be removed from the substrate. In a specific embodiment, the method uses a single impulse to begin the cleaving action, as previously noted. Alternatively, the method uses an initiation impulse, which is followed by another impulse or successive impulses to selected regions of the substrate. Alternatively, the method provides an impulse to initiate a cleaving action which is sustained by a scanned energy along the substrate. Alternatively, energy can be scanned across selected regions of the substrate to initiate and/or sustain the controlled cleaving action. Optionally, an energy or stress of the substrate material is increased toward an energy level necessary to initiate the cleaving action, but not enough to initiate the cleaving action before directing an impulse or multiple successive impulses to the substrate according to the present invention. The global energy state of the substrate can be raised or lowered using a variety of sources such as chemical, mechanical, thermal (sink or source), or electrical, alone or in combination. The chemical source can include particles, fluids, gases, or liquids. These sources can also include chemical reaction to increase stress in the material region. The chemical source is introduced as flood, time-varying, spatially varying, or continuous. In other embodiments, a mechanical source is derived from rotational, translational, compressional, expansional, or ultrasonic energies. The mechanical source can be introduced as flood, time-varying, spatially varying, or continuous. In further embodiments, the electrical source is selected from an applied voltage or an applied electro-magnetic field, which is introduced as flood, time-varying, spatially varying, or continuous. In still further embodiments, the thermal source or sink is selected from radiation, convection, or conduction. This thermal source can be selected from, among others, a photon beam, a fluid jet, a liquid jet, a gas jet, an electro/magnetic field, an electron beam, a thermoelectric heating, and a furnace. The thermal sink can be selected from a fluid jet, a liquid jet, a gas jet, a cryogenic fluid, a super-cooled liquid, a thermoelectric cooling means, an electro/magnetic field, and others. Similar to the previous embodiments, the thermal source is applied as flood, time-varying, spatially varying, or continuous. Still further, any of the above embodiments can be combined or even separated, depending upon the application. Of course, the type of source used depends upon the application. As noted, the global source increases a level of energy or stress in the material region without initiating a cleaving action in the material region before providing energy to initiate the controlled cleaving action. In a preferred embodiment, the method maintains a temperature which is below a temperature of introducing the particles into the substrate. In some embodiments, the substrate temperature is maintained between −200 and 450° C. during the step of introducing energy to initiate propagation of the cleaving action. Substrate temperature can also be maintained at a temperature below 400° C. or below 350° C. In preferred embodiments, the method uses a thermal sink to initiate and maintain the cleaving action, which occurs at conditions significantly below room temperature. A final bonding step occurs between the target wafer and thin film of material region according to some embodiments, as illustrated by FIG. 17. In one embodiment, one silicon wafer has an overlying layer of silicon dioxide, which is thermally grown overlying the face before cleaning the thin film of material, as shown in FIG. 15. The silicon dioxide can also be formed using a variety of other techniques, e.g., chemical vapor deposition. The silicon dioxide between the wafer surfaces fuses together thermally in this process. In some embodiments, the oxidized silicon surface from either the target wafer or the thin film of material region (from the donor wafer) are further pressed together and are subjected to an oxidizing ambient 2401. The oxidizing ambient can be in a diffusion furnace for steam oxidation, hydrogen oxidation, or the like. A combination of the pressure and the oxidizing ambient fuses the thin film of silicon material 2101 to the target silicon wafer 2201 together at the oxide surface or interface 2305. These embodiments often require high temperatures (e.g., 700° C.). Alternatively, the two silicon surfaces are further pressed together and subjected to an applied voltage between the two wafers. The applied voltage raises temperature of the wafers to induce a bonding between the wafers. This technique limits the amount of crystal defects introduced into the silicon wafers during the bonding process, since substantially no significant mechanical force is needed to initiate the bonding action between the wafers. Of course, the technique used depends upon the application. After bonding the wafers, silicon-on-insulator has a target substrate with an overlying film of silicon material and a sandwiched oxide layer between the target substrate and the silicon film, as also illustrated in FIG. 15. The detached surface of the film of silicon material is often rough 2404 and needs finishing. Finishing occurs using a combination of grinding and/or polishing techniques. In some embodiments, the detached surface undergoes a step of grinding using, for examples, techniques such as rotating an abrasive material overlying the detached surface to remove any imperfections or surface roughness therefrom. A machine such as a “back grinder” made by a company called Disco may provide this technique. Alternatively, chemical mechanical polishing or planarization (“CMP”) techniques finish the detached surface of the film, as illustrated by FIG. 18. In CMP, a slurry mixture is applied directly to a polishing surface 2501 which is attached to a rotating platen 2503. This slurry mixture can be transferred to the polishing surface by way of an orifice, which is coupled to a slurry source. The slurry is often a solution containing an abrasive and an oxidizer, e.g., H2O2, KIO3, ferric nitrate. The abrasive is often a borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, aluminum trioxide, iron nitrate, cerium oxide, silicon dioxide (colloidal silica), silicon nitride, silicon carbide, graphite, diamond, and any mixtures thereof. This abrasive is mixed in a solution of deionized water and oxidizer or the like. Preferably, the solution is acidic. This acid solution generally interacts with the silicon material from the wafer during the polishing process. The polishing process preferably uses a poly-urethane polishing pad. An example of this polishing pad is one made by Rodel and sold under the trade name of IC-1000. The polishing pad is rotated at a selected speed. A carrier head which picks up the target wafer having the film applies a selected amount of pressure on the backside of the target wafer such that a selected force is applied to the film. The polishing process removes about a selected amount of film material, which provides a relatively smooth film surface 2601 for subsequent processing, as illustrated by FIG. 18. In certain embodiments, a thin film of oxide 2406 overlies the film of material overlying the target wafer, as illustrated in FIG. 17. The oxide layer forms during the thermal annealing step, which is described above for permanently bonding the film of material to the target wafer. In these embodiments, the finishing process is selectively adjusted to first remove oxide and the film is subsequently polished to complete the process. Of course, the sequence of steps depends upon the particular application. Although the above description is in terms of a silicon wafer, other substrates may also be used. For example, the substrate can be almost any monocrystalline, polycrystalline, or even amorphous type substrate. Additionally, the substrate can be made of III/V materials such as gallium arsenide, gallium nitride (GaN), and others. The multi-layered substrate can also be used according to the present invention. The multi-layered substrate includes a silicon-on-insulator substrate, a variety of sandwiched layers on a semiconductor substrate, and numerous other types of substrates. Additionally, the embodiments above were generally in terms of providing a pulse of energy to initiate a controlled cleaving action. The pulse can be replaced by energy that is scanned across a selected region of the substrate to initiate the controlled cleaving action. Energy can also be scanned across selected regions of the substrate to sustain or maintain the controlled cleaving action. One of ordinary skill in the art would easily recognize a variety of alternatives, modifications, and variations, which can be used according to the present invention. While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.	H	67H01	185H01L	214	25
11846874	US20090057849A1-20090305	INTERCONNECT IN A MULTI-ELEMENT PACKAGE	ACCEPTED	20090218	20090305	[]	H01L2348	["H01L2348", "H01L2156"]	7838420	20070829	20101123	438	672000	67894.0	DANG	PHUC	[{"inventor_name_last": "Tang", "inventor_name_first": "Jinbang", "inventor_city": "Chandler", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Frear", "inventor_name_first": "Darrel R.", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Lytle", "inventor_name_first": "William H.", "inventor_city": "Chandler", "inventor_state": "AZ", "inventor_country": "US"}]	A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.	1. A packaged semiconductor device comprising: an interconnect layer over a first side of a polymer layer; a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer; a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side; and a connector block within the polymer layer, having at least one electrical path extending from a first surface of the connector block to a second surface of the connector block, and electrically coupling the interconnect layer to the first conductive element through the at least one electrical path. 2. The packaged semiconductor device of claim 1, wherein the connector block comprises an insulating material surrounding the at least one electrical path. 3. The packaged semiconductor device of claim 1, wherein the connector block has at least two coaxial electrical paths. 4. The packaged semiconductor device of claim 1, wherein the at least one electrical path is a ground path and the first conductive element is a ground plane. 5. The packaged semiconductor device of claim 1, wherein the at least one electrical path is a signal path and the first conductive element is an antenna. 6. The packaged semiconductor device of claim 5, further comprising a second conductive element and a second electrical path, wherein the second electrical path is a ground path and the second conductive element is a ground plane. 7. The packaged semiconductor device of claim 6, further comprising a third electrical path, wherein the third electrical path is coupled to the antenna. 8. A method for forming a packaged semiconductor device, the method comprising: surrounding a semiconductor device on at least three sides by a polymer layer; forming an interconnect layer over a first side of the polymer layer and over the semiconductor device, wherein the semiconductor device is coupled to the interconnect layer; forming a conductive element over a second side of the polymer layer, wherein the second side is opposite the first side; and electrically coupling the interconnect layer to the conductive element through a connector block within the polymer layer, having at least one electrical path. 9. The method of claim 8, wherein forming the conductive element over a second side comprises plating a conductive material to form an antenna. 10. The method of claim 8, wherein: surrounding a semiconductor device on at least three sides by the polymer layer, comprises: attaching a semiconductor device to a temporary support structure; forming the polymer layer over the semiconductor device; and removing the temporary support structure after forming the polymer layer; and electrically coupling the interconnect layer, comprises: attaching the connector block to the temporary support structure before forming the polymer layer; removing a portion of the polymer layer to expose a surface of the connector block; and forming the interconnect layer over the surface of the connector block while forming the interconnect layer over the first side of the polymer layer. 11. The method of claim 10, further comprising: depositing a dielectric layer over the surface of the connector block; and forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the conductive element. 12. The method of claim 8, wherein the at least one electrical path is selected from the group consisting of a ground path and a signal path. 13. The method of claim 8, wherein the first conductive element is selected from a group consisting of a ground plane and an antenna. 14. The method of claim 8, wherein the at least one electrical path comprises at least two coaxial electrical paths. 15. A method for forming a packaged semiconductor device, the method comprising: attaching a semiconductor device to a temporary support structure; attaching a connector block to the temporary support structure, wherein the connector block has at least one electrical path; forming an encapsulant over the connector block and the semiconductor device; removing a portion of the encapsulant to expose a top surface of the connector block; forming an interconnect layer electrically coupled to the top surface of the connector block; removing the temporary support structure to expose a bottom surface of the connector block; and electrically coupling a tangible element to the bottom surface of the connector block. 16. The method of claim 15, wherein electrically coupling a tangible element to the bottom surface of the connector block, comprises plating a conductive material to form an antenna. 17. The method of claim 16, wherein electrically coupling a tangible element to the bottom surface of the connector block further comprises: depositing a dielectric layer over the bottom surface of the connector block; and forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the antenna. 18. The method of claim 15, wherein the removing a portion of the encapsulant to expose a top surface of the connector block comprises grinding the encapsulant. 19. The method of claim 15, wherein the temporary support structure is selected from a group consisting of a tape and a carrier. 20. The method of claim 15, wherein the connector block has at least two coaxial electrical paths.	<SOH> BACKGROUND <EOH>1. Field This disclosure relates generally to packages that have more than one element including at least one semiconductor device, and more specifically, to interconnect for such packages. 2. Related Art One technique for increasing density of functionality is to include multiple elements, such as integrated circuits into one package. This is an alternative to simply placing all of the functionality on a single integrated circuit because there are types of integrated circuits and semiconductor components that are difficult to make on the same integrated circuit or at least difficult to optimize on the same integrated circuit. Radio frequency (RF) circuits typically require a different process than logic. Also logic and analog may need to be optimized and use a different process. One of the techniques for placing multi-elements in the same package is redistributed chip package (RCP) which uses an organic fill around the elements and builds interconnect layers on a top side of the package where external contacts are also formed. This has been found to be a useful packaging technique which provides a very effective way of combining elements and connecting to them on a top side of the package. There is, however, further benefit for increased utility of RCP.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 is a cross section of a packaged semiconductor device at a stage in processing according to an embodiment; FIG. 2 is a cross section of the packaged semiconductor device of FIG. 1 at a subsequent stage in processing; FIG. 3 is a cross section of the packaged semiconductor device of FIG. 2 at a subsequent stage in processing; FIG. 4 is a cross section of the packaged semiconductor device of FIG. 3 at a subsequent stage in processing; FIG. 5 is a cross section of the packaged semiconductor device of FIG. 4 at a subsequent stage in processing; FIG. 6 is a cross section of the packaged semiconductor device of FIG. 5 at a subsequent stage in processing; FIG. 7 is a cross section of the packaged semiconductor device of FIG. 6 at a subsequent stage in processing; FIG. 8 is a cross section of the packaged semiconductor device of FIG. 7 at a subsequent stage in processing; FIG. 9 is a cross section of the packaged semiconductor device of FIG. 8 at a subsequent stage in processing; FIG. 10 is a top view of a portion of the packaged device of FIGS. 1-9 ; and FIG. 11 is a top view of an alternative for the portion of FIG. 10 . detailed-description description="Detailed Description" end="lead"?	BACKGROUND 1. Field This disclosure relates generally to packages that have more than one element including at least one semiconductor device, and more specifically, to interconnect for such packages. 2. Related Art One technique for increasing density of functionality is to include multiple elements, such as integrated circuits into one package. This is an alternative to simply placing all of the functionality on a single integrated circuit because there are types of integrated circuits and semiconductor components that are difficult to make on the same integrated circuit or at least difficult to optimize on the same integrated circuit. Radio frequency (RF) circuits typically require a different process than logic. Also logic and analog may need to be optimized and use a different process. One of the techniques for placing multi-elements in the same package is redistributed chip package (RCP) which uses an organic fill around the elements and builds interconnect layers on a top side of the package where external contacts are also formed. This has been found to be a useful packaging technique which provides a very effective way of combining elements and connecting to them on a top side of the package. There is, however, further benefit for increased utility of RCP. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 is a cross section of a packaged semiconductor device at a stage in processing according to an embodiment; FIG. 2 is a cross section of the packaged semiconductor device of FIG. 1 at a subsequent stage in processing; FIG. 3 is a cross section of the packaged semiconductor device of FIG. 2 at a subsequent stage in processing; FIG. 4 is a cross section of the packaged semiconductor device of FIG. 3 at a subsequent stage in processing; FIG. 5 is a cross section of the packaged semiconductor device of FIG. 4 at a subsequent stage in processing; FIG. 6 is a cross section of the packaged semiconductor device of FIG. 5 at a subsequent stage in processing; FIG. 7 is a cross section of the packaged semiconductor device of FIG. 6 at a subsequent stage in processing; FIG. 8 is a cross section of the packaged semiconductor device of FIG. 7 at a subsequent stage in processing; FIG. 9 is a cross section of the packaged semiconductor device of FIG. 8 at a subsequent stage in processing; FIG. 10 is a top view of a portion of the packaged device of FIGS. 1-9; and FIG. 11 is a top view of an alternative for the portion of FIG. 10. DETAILED DESCRIPTION An RCP is built having multiple elements that are interconnected with external connections available on a top side. One of the elements is a connection block which provides the capability of extending from the top side to a back side because the connection block is prefabricated. The connection block, which can also be called a connector block, has the organic fill formed around in the same manner as the other elements in the RCP. The connection block thus allows electrical connection to be made from the interconnect on the top side to the back side without having to etch via holes and then filling the via holes to form vias. The distance from the top side to the back side, for practical production, is too long for forming and filling vias. One application of connection block is to place an antenna on the back side. Another is place a ground plane on the back side. This is better understood by reference to the drawings and the following description. Shown in FIG. 1 is a package 10 comprising a carrier 12, a tape 14, an element 16, an element 18, and connection block 20. Carrier 12 is for providing mechanical support. Tape 14 is two-sided. Element 16 may be an integrated circuit, and element 18 may be an integrated circuit. On or the other could also be another type of element such as a passive device or a discrete semiconductor device. Connection block 20 has a conductor 22, a conductor 24, and a conductor 26 that run vertically the length connection block 20 and are surrounded by a dielectric 28. Dielectric 28 is preferably an organic material similar to or the same as that used as the fill in making an RCP, but dielectric 28 could also be another material such as ceramic. Copper is a preferred material for conductors 22, 24, and 26 because of its relatively high conductivity and relatively low cost. More conductive material such as platinum, gold, or silver may be used but at a higher cost. The length of connection block 20 is chosen to be a little thicker than the thickness of the organic layer that surround the elements of the finished RCP. A common thickness for the organic layer surrounding the elements is about 0.65 millimeter (mm) but this may vary. In such case of 0.65 mm, connection block 20 and thus conductors 22, 24, and 26 are about 0.70 mm in length. Connection block 20 is preferably one mm or more in diameter. A smaller diameter may present difficulties in adhering reliably to tape 14 but may nonetheless be advantageous for some applications. Shown in FIG. 2 is package 10 after deposition of an organic layer 30 which covers elements 16 and 18 and connection block 20. Organic layer 30 may be deposited to be about 0.80 mm for the example of connection block 20 being about 0.70 mm. Organic layer 30 may be considered a polymer layer. Shown in FIG. 3 is package 10 after grinding organic layer 30 and a small portion of connection block 20 to expose conductors 22, 24, and 26. Organic layer 30 is then reduced, in this example, to 0.65 mm. Shown in FIG. 4 is package 10 after removing carrier 12 and tape 14. FIG. 4 also has package 10 inverted from that of FIGS. 1-3. Elements 16 and 18 are exposed on the top side of package 10. The exposed surface of element 16 and the expose surface of element 18 are where contacts for elements 16 and 18 reside. Shown in FIG. 5 is package 10 after forming an interconnect 32 in contact with connection block 20, element 16, and element 18. Interconnect 32 may be made of multiple conductive layers connected to elements 16 and 18 and connection block 20 using vias. On interconnect 32 is a plurality of pads 34 of which one is pad 36. Pads 34 are for receiving solder balls and are on a top side of package 10. Connection block 20 is exposed on a back side of package 10. In a conventional RCP which would not have connection block 20, processing could be complete except for the solder balls. Solder balls could be added at this point or at a subsequent convenient time. Shown in FIG. 6 is package 10 after forming a dielectric layer 38 on the back side and forming vias 42, 44, and 46 through dielectric layer 38. Dielectric layer 38 is preferably the same material as organic layer 30 but could be another insulating material. Dielectric layer 38 may be 0.1 mm thick. Via 42 is in contact with conductor 22. Via 44 is contact with conductor 24. Via 46 is in contact with conductor 46. FIG. 6 also shows package 10 inverted from FIGS. 4 and 5. The side with pads 34 is still called the top side though and the side with dielectric layer 38 is still called the back side. Shown in FIG. 7 is package 10 after forming a patterned conductive layer over dielectric layer 38 comprising a ground plane 47 in contact with via 40, a trace 48 on in contact with via 42, and a trace 50 in contact with via 44. Ground plane 47 surrounds traces 48 and 50. Trace 48 extends laterally from via 42 and is present for stability. Similarly, trace 50 extends laterally from via 44 in a different direction from that of trace 48 so that the lateral extension is not visible in the cross section of FIG. 7. The patterned conductive layer may be made by a conventional plating process in which a thin seed layer is deposited followed by photoresist which is patterned. Plating then ensues so that the conductive material, preferably copper although other metals may also be effective, grows in the areas not covered by the photoresist. The photoresist is removed. An etch back is performed to remove the seed layer in the areas where the conductive layer was not grown. The thickness of ground plane 47 and traces 48 and 50 may be about 0.10 mm. Shown in FIG. 8 is package 10 after forming a dielectric layer 52 and vias 54 and 56 through dielectric layer 52. Dielectric layer 52 may be the same material as for dielectric layer 38. Via 54 is in contact with trace 48. Via 56 is contact with trace 50. Although via 56 is shown in the cross section of FIG. 8 in contact with trace 50, via 56 is preferably located over a wider portion of trace 50 than shown. Shown in FIG. 9 is package 10 after forming an antenna 58 in contact with vias 54 and 56. Antenna 58 may be formed and patterned using the same plating technique described for ground plane 47 and traces 48 and 50. Antenna 58 may be 0.200 mm thick. With antenna 58 in contact with vias 54 and 56, antenna is coupled to conductors 22 and 24, respectively. Due to the high frequencies that may be involved, vias 54 and 56 may not have to be in actual contact with antenna 58, if sufficiently close to antenna 58, for antenna 58 to be coupled to conductor 22. Package 10 of FIG. 9 is a completed RCP that will have solder balls added later at a time closer to being mounted on a circuit board. Shown in FIG. 10 is a top view of connection block 20 showing conductors 22, 24, and 26 in a line and dielectric 28 surrounding them in a circular shape. In this configuration, connection block 20 is a cylinder with three inline conductors. Conductors 22, 24, and 26 could be in a different configuration. Also the shape could be different than circular, such as square, rectangular, or triangular. Shown in FIG. 11 is an alternative connection block 60 comprising an outer insulating layer 68, a conductor ring 62, an inner conductor 64, and an insulating layer between conductor ring 62 and inner conductor 64. This forms a coaxial line which may be particularly beneficial when coupling to an antenna that is transmitting and receiving RF. Connection block 60 may replace connection block 20 with respect to the connection to antenna 58. If a ground plane were still desirable, the connection to the ground plane could be by another connection block or connection block 60 could be modified to have another conductor outside ring 62 for coupling to the ground plane. Construction of a connection block such as connection block 20 or connection block 60 may be achieved using wire bond machines. A wire bond is commonly 25 microns in diameter. Three of those wire bonds can be placed into a cylindrical mold that is many times longer than that of connection block 20. The mold is filled with the desired dielectric such as the material used for dielectric 30. The resulting structure is then cut into pieces of the desired length of about 0.070 mm. Instead of an organic material, the surrounding dielectric may be a material such as ceramic. The rigidity of ceramic may be beneficial in the manufacturing process. By now it should be appreciated that there has been provided a packaged semiconductor device having an interconnect layer, a semiconductor device, a first conductive element, and a connector block. The interconnect layer is over a first side of a polymer layer. The semiconductor device is surrounded on at least three sides by the polymer layer and is coupled to the interconnect layer. The first conductive element is over a second side of the polymer layer. The second side is opposite the first side. The connector block is within the polymer layer and has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block, and electrically couples the interconnect layer to the first conductive element through the at least one electrical path. The connector block may comprise an insulating material surrounding the at least one electrical path. The connector block may have at least two coaxial electrical paths. The at least one electrical path may be a ground path and the first conductive element may be a ground plane. The at least one electrical path may be a signal path and the first conductive element may be an antenna. The packaged semiconductor device may further comprise a second conductive element and a second electrical path, wherein the second electrical path is a ground path and the second conductive element is a ground plane. The packaged semiconductor device may further comprise a third electrical path, wherein the third electrical path is coupled to the antenna. Also provided is a method for forming a packaged semiconductor device. The method includes surrounding a semiconductor device on at least three sides by a polymer layer. The method further includes forming an interconnect layer over a first side of the polymer layer and over the semiconductor device, wherein the semiconductor device is coupled to the interconnect layer. The method further includes forming a conductive element over a second side of the polymer layer, wherein the second side is opposite the first side. The method further includes electrically coupling the interconnect layer to the conductive element through a connector block within the polymer layer, having at least one electrical path. The forming the conductive element over a second side may comprise plating a conductive material to form an antenna. The step of surrounding may comprise attaching a semiconductor device to a temporary support structure, forming the polymer layer over the semiconductor device, and removing the temporary support structure after forming the polymer layer. The step of electrically coupling may comprise attaching the connector block to the temporary support structure before forming the polymer layer, removing a portion of the polymer layer to expose a surface of the connector block, forming the interconnect layer over the surface of the connector block while forming the interconnect layer over the first side of the polymer layer. The method may further comprise depositing a dielectric layer over the surface of the connector block, and forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the conductive element. The at least one electrical path may be selected from the group consisting of a ground path and a signal path. The first conductive element may be selected from a group consisting of a ground plane and an antenna. The at least one electrical path may comprise at least two coaxial electrical paths. Further described is a method for forming a packaged semiconductor device. The method includes attaching a semiconductor device to a temporary support structure. The method further includes attaching a connector block to the temporary support structure, wherein the connector block has at least one electrical path. The method further includes forming an encapsulant over the connector block and the semiconductor device. The method further includes removing a portion of the encapsulant to expose a top surface of the connector block. The method further includes forming an interconnect layer electrically coupled to the top surface of the connector block. The method further includes removing the temporary support structure to expose a bottom surface of the connector block. The method further includes electrically coupling a tangible element to the bottom surface of the connector block. The step of electrically coupling a tangible element to the bottom surface of the connector block may comprise plating a conductive material to form an antenna. The step of electrically coupling a tangible element to the bottom surface of the connector block may further comprise depositing a dielectric layer over the bottom surface of the connector block, and forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the antenna. The step of removing a portion of the encapsulant to expose a top surface of the connector block may comprise grinding the encapsulant. The temporary support structure may be selected from a group consisting of a tape and a carrier. The connector block may have at least two coaxial electrical paths. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, dielectric layer 38 is shown as being formed after interconnect layer 32 whereas dielectric layer 38 may be deposited before interconnect layer 32 is formed. Also plating was described as the method for forming patterned metal layers, but other deposition techniques may be used. For example, the metal could be sputtered and then patterned with an etch. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.	H	67H01	185H01L	23	48
11915921	US20090309117A1-20091217	PROTECTION CIRCUIT, AND SEMICONDUCTOR DEVICE AND LIGHT EMITTING DEVICE USING SUCH PROTECTION CIRCUIT	ACCEPTED	20091202	20091217	[]	H01L3300	["H01L3300", "H01L2973", "H02H900"]	7889467	20071129	20110215	361	056000	95717.0	JACKSON	STEPHEN	[{"inventor_name_last": "Okazaki", "inventor_name_first": "Mitsuru", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Takahashi", "inventor_name_first": "Naoki", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Shimizu", "inventor_name_first": "Akira", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Nakata", "inventor_name_first": "Kenichi", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}]	In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.	1. A protection circuit connected via a line including a significant inductance component to a circuit to be protected, comprising: a first transistor arranged on a path to ground from a connection point of the protection circuit and the line; and a second transistor arranged on a path to ground from a connection point of the circuit to be protected and the line, the second transistor extracting, from the connection point, a current corresponding to a current flowing in the first transistor. 2. A protection circuit according to claim 1, wherein the first and the second transistors are bipolar transistors having a base and an emitter commonly connected. 3. A protection circuit according to claim 2, wherein the first and the second transistors are NPN bipolar transistors, a collector of the first transistor being connected to a connection point of the protection circuit and the wire, a collector of the second transistor being connected to a connection point of the circuit to be protected and the wire, and a commonly connected emitter being grounded, the protection circuit further comprising: a resistor arranged between a base and an emitter of the first transistor; and a diode with a cathode connected to the collector of the first transistor, and an anode connected to the base of the first transistor. 4. A protection circuit according to claim 1, wherein transistor sizes of the first and the second transistor are configured to be approximately the same. 5. A protection circuit according to claim 1, wherein the protection circuit is integrated on a same semiconductor substrate as the circuit to be protected, and the circuit to be protected and the protection circuit are each provided with bonding pads; and the respective bonding pads are connected by a bonding wire equivalent to the wire, via a terminal arranged on a base on which the semiconductor substrate is mounted. 6. A semiconductor device comprising: a driver circuit which is connected to a cathode of a light emitting diode and which controls emitted quantity of light of the light emitting diode; and the protection circuit according to claim 1, provided with the driver circuit as the circuit to be protected. 7. A light emitting apparatus comprising: a light emitting diode; and a semiconductor device according to claim 6, which drives the light emitting diode.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to circuit protection technology for protecting a circuit to be protected, from surge voltages and the like. 2. Description of the Related Art Many semiconductor integrated circuits are used in various electronic devices, starting from mobile telephones, PDAs (Personal Digital Assistants), and laptop personal computers, or electrical systems in automobiles. Since usage in all kinds of conditions is envisaged for such semiconductor integrated circuits, high reliability is required. In order to improve reliability, in general, a protection circuit is provided for each bonding pad of an input-output terminal connected to the outside of a circuit. Among such protection circuits, a voltage clamp circuit may be provided so that the reliability of an internal circuit that is to be protected (referred to as a protected circuit, below), does not deteriorate, even in cases in which a surge voltage or the like is precipitously applied. Circuit protection technology by this kind of voltage clamp circuit is described, for example, in Patent Document 1. Here, as an example, a protection circuit of a driver circuit 200 of an LED (Light Emitting Diode) shown in FIG. 1 is examined. The LED driver circuit 200 is, for example, a circuit for driving the LED 24 provided as illumination of a meter of an automobile. A battery voltage outputted from a battery 20 is applied via a resistor 22 to an anode of the LED 24 . Furthermore, for the cathode of the LED 24 , there is a connection to a drive transistor M 1 of the LED driver circuit 200 . A controller 26 controls gate voltage of the drive transistor M 1 , and, by regulating current flowing in the LED 24 , controls emitted light intensity of the LED 24 . Since voltage outputted from the battery 20 is unstable, for a semiconductor integrated circuit used for this type of application, reliability is required particularly against surge voltages and the like. At the same time, in the LED driver circuit 200 of FIG. 1 , breakdown voltage of the drive transistor M 1 becomes a problem. Accordingly, a protection circuit 100 , which clamps voltage applied to a drain of the drive transistor M 1 , is arranged in parallel to the drive transistor M 1 . Patent Document 1: Japanese Patent Application, Laid Open No. H6-140576 FIG. 2 is a plan view of the LED driver circuit 200 of FIG. 1 seen from above. The LED driver circuit 200 is integrated on a semiconductor substrate 30 , and the semiconductor substrate 30 is mounted on a base 32 for a package. A protected circuit 110 integrated on the semiconductor substrate 30 includes a drive transistor M 1 of FIG. 1 . With regard to the drive transistor M 1 , which is the protected circuit 110 , since it is necessary to inspect breakdown voltage in a state in which the protection circuit 100 is not used, that is, as a single unit, a dedicated bonding pad 34 is provided. The protection circuit 100 also is provided with another bonding pad 36 , and the protection circuit 100 and the protected circuit 110 are connected to one another by bonding wires W 1 and W 2 , via a bonding pad 38 arranged on the base 32 . The bonding pad 38 is connected to an external electrode of a package, and this external electrode is connected to a cathode of the LED 24 of FIG. 1 . In this way, the protection circuit 100 and the protected circuit 110 are connected via the bonding wires W 1 and W 2 , which are lines that include a significant inductance component. FIG. 3 is an equivalent circuit diagram of the LED driver circuit 200 of FIG. 1 . The protection circuit 100 is provided with a first transistor Q 1 , a diode D 1 , and a resistor R 3 . The first transistor Q 1 is an NPN bipolar transistor, and is arranged on a path to ground, from the bonding pad 34 , which is a connection point of the present protection circuit 100 and the bonding wire W 1 . The diode D 1 is connected between a base and a collector of the first transistor Q 1 , and the resistor R 3 is arranged between the base and an emitter of the first transistor Q 1 . In the figure, C 1 and C 2 represent parasitic capacitances in the LED driver circuit 200 ; the parasitic capacitance C 1 is mainly collector-emitter capacitance of the first transistor Q 1 of the protection circuit 100 , and the parasitic capacitance C 2 is drain-source capacitance of the drive transistor M 1 inside the protected circuit 110 . Furthermore, the bonding wires W 1 and W 2 respectively include resistance components R 1 and R 2 , and inductance components L 1 and L 2 . Included in the resistance components R 1 and R 2 are not only the bonding wires W 1 and W 2 , but also IC chip internal wiring resistance. When voltage of the bonding pad 38 rises due to occurrence of a surge voltage, voltage Va of the bonding pad 34 rises therewith. When the voltage Va of the bonding pad 34 exceeds a Zener voltage Vz of the diode D 1 , a reverse current directed from cathode to anode flows, the first transistor Q 1 is ON, and a current is extracted from the bonding pad 34 . As a result, voltages Va and Vb of the bonding pad 34 and the bonding pad 36 are clamped, and it is possible to prevent application of a high voltage to the protected circuit 110 . With the protection circuit 100 configured in this way, problems described below arise. FIG. 4 is a voltage waveform diagram of the LED driver circuit 200 of FIG. 3 , and shows a time waveform of the voltage Va of the bonding pad 34 and the voltage Vb of the bonding pad 36 of FIG. 3 . At time T 0 , when a surge voltage is inputted from the bonding pad 38 , both of the voltages Va and Vb of the bonding pad 34 and 36 rise. When the voltage Va of the bonding pad 34 rises and exceeds the Zener voltage Vz of the diode D 1 , a reverse current directed from cathode to anode of the diode D 1 flows, and the first transistor Q 1 is ON. If base-emitter voltage of the first transistor Q 1 is taken as Vbe, the voltage Va of the bonding pad 34 is clamped close to Vmax=Vz+Vbe, as shown in FIG. 4 . However, as shown in FIG. 3 , parasitic capacitances of different capacitance values exist for each of the bonding pad 34 and the bonding pad 36 . If C 1 >C 2 , charge stored in the parasitic capacitance C 2 of the protected circuit 110 is extracted by the protection circuit 100 . At this time, the charge stored in the parasitic capacitance C 2 is discharged by the protection circuit 100 via the bonding wires W 1 and W 2 , which include the inductance components L 1 and L 2 . By a current flowing in the inductance components L 1 and L 2 , LCR resonance is generated by the parasitic capacitances C 1 and C 2 , the resistors R 1 and R 2 , and the inductance components L 1 and L 2 included in the bonding wires W 1 and W 2 , and a reverse voltage is generated with respect to the inductance components L 1 and L 2 . As a result, the voltage Vb of the bonding pad 36 rises while oscillating, and the oscillation continues even after time T 1 at which the voltage Va of the bonding pad 34 is clamped at the voltage Vmax. As a result, for the protected circuit 110 , there have been cases in which voltage exceeding the voltage Vmax is applied, and there has been room for improvement in functionality of the protection circuit 100 .	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made in view of these problems, and a general purpose thereof is to provide a protection circuit which enables a voltage clamp that suppresses oscillation, and also a semiconductor device using the protection circuit. An embodiment of the present invention relates to a protection circuit connected, via a line including a significant inductance component, to a circuit to be protected. The protection circuit is provided with a first transistor arranged on a path to ground from a connection point of the protection circuit and the line, and a second transistor arranged on a path to ground from a connection point of the circuit to be protected and the line, the second transistor extracting, from the connection point, a current corresponding to a current flowing in the first transistor. The “significant inductance component” is an inductance component of a level forming an oscillation circuit and a parasitic capacitance within a circuit. According to the embodiment, when a surge voltage occurs, a current due to the second transistor in addition to the first transistor is extracted. As a result, since a current is extracted from both ends of a wire including the significant inductance component, LCR oscillation can be suppressed, and voltage oscillation can be suppressed. The first and the second transistors may be bipolar transistors whose base and emitter are commonly connected. In such cases, by adjusting size ratio of the first transistor and the second transistor, a constant current in accordance with the size ratio of the transistors can be extracted. The first and the second transistors are NPN bipolar transistors; a collector of the first transistor may be connected to a connection point of the protection circuit and the wire; a collector of the second transistor may be connected to a connection point of the circuit to be protected and the wire; and a commonly connected emitter may be grounded. The protection circuit may be further provided with a resistor arranged between a base and an emitter of the first transistor, and a diode, with a cathode connected to a collector of the first transistor, and an anode connected to the base of the first transistor. Transistor sizes of the first and the second transistor may be configured to be approximately the same. By the size of the first and the second transistors being approximately the same, electrical current amount extracted by each of the transistors can be made approximately equal, and it is possible to suppress oscillation. The protection circuit may be integrated on the same semiconductor substrate as the circuit to be protected; the circuit to be protected and the protection circuit may each be provided with bonding pads; and each of the bonding pads may be connected by a bonding wire equivalent to the wire, via a terminal arranged on a base on which the semiconductor substrate is mounted. Another embodiment of the present invention is a semiconductor device. The device is provided with a driver circuit, which is connected to a cathode of a light emitting diode, and which controls emitted quantity of light of the light emitting diode, and with the abovementioned protection circuit provided with the driver circuit as the circuit to be protected. According to this embodiment, the driver circuit can be protected from a surge voltage and the like, and it is possible to raise reliability of the semiconductor device. It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuit protection technology for protecting a circuit to be protected, from surge voltages and the like. 2. Description of the Related Art Many semiconductor integrated circuits are used in various electronic devices, starting from mobile telephones, PDAs (Personal Digital Assistants), and laptop personal computers, or electrical systems in automobiles. Since usage in all kinds of conditions is envisaged for such semiconductor integrated circuits, high reliability is required. In order to improve reliability, in general, a protection circuit is provided for each bonding pad of an input-output terminal connected to the outside of a circuit. Among such protection circuits, a voltage clamp circuit may be provided so that the reliability of an internal circuit that is to be protected (referred to as a protected circuit, below), does not deteriorate, even in cases in which a surge voltage or the like is precipitously applied. Circuit protection technology by this kind of voltage clamp circuit is described, for example, in Patent Document 1. Here, as an example, a protection circuit of a driver circuit 200 of an LED (Light Emitting Diode) shown in FIG. 1 is examined. The LED driver circuit 200 is, for example, a circuit for driving the LED 24 provided as illumination of a meter of an automobile. A battery voltage outputted from a battery 20 is applied via a resistor 22 to an anode of the LED 24. Furthermore, for the cathode of the LED 24, there is a connection to a drive transistor M1 of the LED driver circuit 200. A controller 26 controls gate voltage of the drive transistor M1, and, by regulating current flowing in the LED 24, controls emitted light intensity of the LED 24. Since voltage outputted from the battery 20 is unstable, for a semiconductor integrated circuit used for this type of application, reliability is required particularly against surge voltages and the like. At the same time, in the LED driver circuit 200 of FIG. 1, breakdown voltage of the drive transistor M1 becomes a problem. Accordingly, a protection circuit 100, which clamps voltage applied to a drain of the drive transistor M1, is arranged in parallel to the drive transistor M1. Patent Document 1: Japanese Patent Application, Laid Open No. H6-140576 FIG. 2 is a plan view of the LED driver circuit 200 of FIG. 1 seen from above. The LED driver circuit 200 is integrated on a semiconductor substrate 30, and the semiconductor substrate 30 is mounted on a base 32 for a package. A protected circuit 110 integrated on the semiconductor substrate 30 includes a drive transistor M1 of FIG. 1. With regard to the drive transistor M1, which is the protected circuit 110, since it is necessary to inspect breakdown voltage in a state in which the protection circuit 100 is not used, that is, as a single unit, a dedicated bonding pad 34 is provided. The protection circuit 100 also is provided with another bonding pad 36, and the protection circuit 100 and the protected circuit 110 are connected to one another by bonding wires W1 and W2, via a bonding pad 38 arranged on the base 32. The bonding pad 38 is connected to an external electrode of a package, and this external electrode is connected to a cathode of the LED 24 of FIG. 1. In this way, the protection circuit 100 and the protected circuit 110 are connected via the bonding wires W1 and W2, which are lines that include a significant inductance component. FIG. 3 is an equivalent circuit diagram of the LED driver circuit 200 of FIG. 1. The protection circuit 100 is provided with a first transistor Q1, a diode D1, and a resistor R3. The first transistor Q1 is an NPN bipolar transistor, and is arranged on a path to ground, from the bonding pad 34, which is a connection point of the present protection circuit 100 and the bonding wire W1. The diode D1 is connected between a base and a collector of the first transistor Q1, and the resistor R3 is arranged between the base and an emitter of the first transistor Q1. In the figure, C1 and C2 represent parasitic capacitances in the LED driver circuit 200; the parasitic capacitance C1 is mainly collector-emitter capacitance of the first transistor Q1 of the protection circuit 100, and the parasitic capacitance C2 is drain-source capacitance of the drive transistor M1 inside the protected circuit 110. Furthermore, the bonding wires W1 and W2 respectively include resistance components R1 and R2, and inductance components L1 and L2. Included in the resistance components R1 and R2 are not only the bonding wires W1 and W2, but also IC chip internal wiring resistance. When voltage of the bonding pad 38 rises due to occurrence of a surge voltage, voltage Va of the bonding pad 34 rises therewith. When the voltage Va of the bonding pad 34 exceeds a Zener voltage Vz of the diode D1, a reverse current directed from cathode to anode flows, the first transistor Q1 is ON, and a current is extracted from the bonding pad 34. As a result, voltages Va and Vb of the bonding pad 34 and the bonding pad 36 are clamped, and it is possible to prevent application of a high voltage to the protected circuit 110. With the protection circuit 100 configured in this way, problems described below arise. FIG. 4 is a voltage waveform diagram of the LED driver circuit 200 of FIG. 3, and shows a time waveform of the voltage Va of the bonding pad 34 and the voltage Vb of the bonding pad 36 of FIG. 3. At time T0, when a surge voltage is inputted from the bonding pad 38, both of the voltages Va and Vb of the bonding pad 34 and 36 rise. When the voltage Va of the bonding pad 34 rises and exceeds the Zener voltage Vz of the diode D1, a reverse current directed from cathode to anode of the diode D1 flows, and the first transistor Q1 is ON. If base-emitter voltage of the first transistor Q1 is taken as Vbe, the voltage Va of the bonding pad 34 is clamped close to Vmax=Vz+Vbe, as shown in FIG. 4. However, as shown in FIG. 3, parasitic capacitances of different capacitance values exist for each of the bonding pad 34 and the bonding pad 36. If C1>C2, charge stored in the parasitic capacitance C2 of the protected circuit 110 is extracted by the protection circuit 100. At this time, the charge stored in the parasitic capacitance C2 is discharged by the protection circuit 100 via the bonding wires W1 and W2, which include the inductance components L1 and L2. By a current flowing in the inductance components L1 and L2, LCR resonance is generated by the parasitic capacitances C1 and C2, the resistors R1 and R2, and the inductance components L1 and L2 included in the bonding wires W1 and W2, and a reverse voltage is generated with respect to the inductance components L1 and L2. As a result, the voltage Vb of the bonding pad 36 rises while oscillating, and the oscillation continues even after time T1 at which the voltage Va of the bonding pad 34 is clamped at the voltage Vmax. As a result, for the protected circuit 110, there have been cases in which voltage exceeding the voltage Vmax is applied, and there has been room for improvement in functionality of the protection circuit 100. SUMMARY OF THE INVENTION The present invention has been made in view of these problems, and a general purpose thereof is to provide a protection circuit which enables a voltage clamp that suppresses oscillation, and also a semiconductor device using the protection circuit. An embodiment of the present invention relates to a protection circuit connected, via a line including a significant inductance component, to a circuit to be protected. The protection circuit is provided with a first transistor arranged on a path to ground from a connection point of the protection circuit and the line, and a second transistor arranged on a path to ground from a connection point of the circuit to be protected and the line, the second transistor extracting, from the connection point, a current corresponding to a current flowing in the first transistor. The “significant inductance component” is an inductance component of a level forming an oscillation circuit and a parasitic capacitance within a circuit. According to the embodiment, when a surge voltage occurs, a current due to the second transistor in addition to the first transistor is extracted. As a result, since a current is extracted from both ends of a wire including the significant inductance component, LCR oscillation can be suppressed, and voltage oscillation can be suppressed. The first and the second transistors may be bipolar transistors whose base and emitter are commonly connected. In such cases, by adjusting size ratio of the first transistor and the second transistor, a constant current in accordance with the size ratio of the transistors can be extracted. The first and the second transistors are NPN bipolar transistors; a collector of the first transistor may be connected to a connection point of the protection circuit and the wire; a collector of the second transistor may be connected to a connection point of the circuit to be protected and the wire; and a commonly connected emitter may be grounded. The protection circuit may be further provided with a resistor arranged between a base and an emitter of the first transistor, and a diode, with a cathode connected to a collector of the first transistor, and an anode connected to the base of the first transistor. Transistor sizes of the first and the second transistor may be configured to be approximately the same. By the size of the first and the second transistors being approximately the same, electrical current amount extracted by each of the transistors can be made approximately equal, and it is possible to suppress oscillation. The protection circuit may be integrated on the same semiconductor substrate as the circuit to be protected; the circuit to be protected and the protection circuit may each be provided with bonding pads; and each of the bonding pads may be connected by a bonding wire equivalent to the wire, via a terminal arranged on a base on which the semiconductor substrate is mounted. Another embodiment of the present invention is a semiconductor device. The device is provided with a driver circuit, which is connected to a cathode of a light emitting diode, and which controls emitted quantity of light of the light emitting diode, and with the abovementioned protection circuit provided with the driver circuit as the circuit to be protected. According to this embodiment, the driver circuit can be protected from a surge voltage and the like, and it is possible to raise reliability of the semiconductor device. It is to be noted that any arbitrary combination or rearrangement of the above-described structural components and so forth is effective as and encompassed by the present embodiments. Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which: FIG. 1 is a circuit diagram of a driver circuit of a general LED provided with a protection circuit; FIG. 2 is a plan view seen from above, of the LED driver circuit of FIG. 1; FIG. 3 is an equivalent circuit diagram of the LED driver circuit of FIG. 1; FIG. 4 is a voltage waveform diagram of the LED driver circuit of FIG. 3; FIG. 5 is a circuit diagram showing a configuration of the LED driver circuit including the protection circuit according to an embodiment of the present invention; and FIG. 6 is an operation waveform diagram of the LED driver circuit of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention. A protection circuit 100 according to the present embodiment is used, for example, in an LED driver circuit 200 described in FIG. 1. As shown in FIG. 2, also in the present embodiment, the protection circuit 100 and a protected circuit 110, that is to be protected, are integrated on the same semiconductor substrate 30, and the protection circuit 100 and the protected circuit 110 are respectively provided with bonding pads 34 and 36. The bonding pads 34 and 36 are connected by bonding wires W1 and W2 that are lines including significant inductance components, via a bonding pad 38 arranged on a base 32, on which the semiconductor substrate 30 is mounted. FIG. 5 is a circuit diagram showing a configuration of the LED driver circuit 200 including the protection circuit 100 according to the present embodiment. The LED driver circuit 200 includes the protection circuit 100 and the protected circuit 110, and the protection circuit 100 and the protected circuit 110 are connected via the bonding wires W1 and W2 that include inductance components L1 and L2. The inductance components L1 and L2 included in the bonding wires W1 and W2 are dependant upon bonding wire length and thickness, but since the inductance components are normally less than or equal to 1 nH or of the order of 1 nH, an undesired LCR oscillation circuit is formed due to a combination of another capacitance component and resistance component. The protection circuit 100 is provided with a first transistor Q1, a second transistor Q2, a diode D1, and a resistor R3. The first transistor Q1 is an NPN bipolar transistor, and is arranged on a path to ground, from the bonding pad 34, which is a connection point of the protection circuit 100 and the bonding wire W1; an emitter thereof is grounded and a collector is connected to a bonding pad 34. The diode D1 is arranged between a base and the collector of the first transistor Q1; a cathode thereof is connected to the collector of the first transistor Q1, and an anode thereof is connected to the base of the first transistor Q1. Furthermore, the resistor R3 is arranged between the base and the emitter of the first transistor Q1. The second transistor Q2 is an NPN bipolar transistor similar to the first transistor Q1, and is arranged on a path to ground, from the bonding pad 36, which is a connection point of the protected circuit 110 and the bonding wire W2. An emitter of the second transistor Q2 is grounded, and a collector is connected to the bonding pad 36. The bases and the emitters of the first transistor Q1 and the second transistor Q2 are commonly connected. In the present embodiment, transistor sizes of the first transistor Q1 and the second transistor Q2 are configured to be approximately the same. As a result, the second transistor Q2 extracts a current of the same amount as a current flowing in the first transistor Q1, from the bonding pad 36. In the figure, C1 to C3 represent parasitic capacitances in the LED driver circuit 200. The parasitic capacitance C1 is mainly capacitance between the collector and the emitter of the first transistor Q1 of the protection circuit 100; the parasitic capacitance C2 is mainly capacitance between a drain and a source of a drive transistor M1 inside the protected circuit 110; and parasitic capacitance C3 is mainly capacitance between the collector and the emitter of the second transistor Q2 of the protection circuit 100. That is, the parasitic capacitance C1 exists between the bonding pad 34 and ground, and a parasitic capacitance (C2+C3) exists between the bonding pad 36 and ground. Here, in cases in which C2<C1 holds, since the sizes of the first transistor Q1 and the second transistor Q2 are configured to be the same, C1≈(C2+C3) holds. In this way, the capacitance between the bonding pad 34 and ground, and the capacitance between the bonding pad 36 and ground are approximately equal. An explanation will be given concerning operation of the LED driver circuit 200 configured as above. FIG. 6 is an operation waveform diagram of the LED driver circuit 200 of FIG. 5. At time T0, when a surge voltage is inputted from the bonding pad 38, voltage of the bonding pad 38 rises, and accompanying this, voltage Va of the bonding pad 34 and voltage Vb of the bonding pad 36 rise. When the voltage Va of the bonding pad 34 rises and exceeds a Zener voltage Vz of the diode D1, a reverse current directed from cathode to anode of the diode D1 flows, and the first transistor Q1 is ON. As described above, the transistor sizes of the first transistor Q1 and the second transistor Q2 are configured to be approximately the same, so that the parasitic capacitances of the bonding pad 34 and the bonding pad 36 are approximately equal. Parasitic capacitance values being equal means that charge amounts stored when electrical potential is the same are approximately equal, so that it is possible to reduce transfer of charge via the inductance components L1 and L2 between the parasitic capacitances. As a result, the LCR oscillation, which occurs when the voltage Vb of the bonding pad 36 rises with a rise in the voltage Va of the bonding pad 34, is suppressed, and the voltage Vb of the bonding pad 36 does not oscillate, but rises, following the voltage Va of the bonding pad 34. As described above, the transistor sizes of the first transistor Q1 and the second transistor Q2 are configured to be approximately the same, so that a current Iq1 flowing in the first transistor Q1 and a current Iq2 flowing in the second transistor Q2 are approximately equal. As a result, even after the voltages Va and Vb of the bonding pads 34 and 36 reach Vmax=Vz+Vbe at time T1 and are clamped, the same amount of current is extracted from the bonding pad 34 and the bonding pad 36. By continually extracting approximately the same amount of current from the bonding pad 34 and the bonding pad 36, even after time T1, it is possible to prevent the voltage Vb of the bonding pad 36 fluctuating due to the LCR oscillation. In this way, according to the protection circuit 100 according to the present embodiment, it is possible to suppress oscillation of the voltage Vb applied to the protected circuit 110, and to clamp the voltage at a predetermined voltage Vmax; it is possible to prevent voltage greater than or equal to the predetermined voltage Vmax from being applied to the protected circuit 110, and to provide more secure protection. This embodiment is an example; various modified examples of combinations of various component elements and various processes thereof are possible, and a person skilled in the art will understand that such modified examples are within the scope of the present invention. For example, in the protection circuit 100 of FIG. 5, the first transistor Q1 and the second transistor Q2 may be PNP bipolar transistors. In such cases, by connecting the resistor R3 between the base and the emitter, and the diode D1 between the base and the collector, it is possible to clamp the voltage of the bonding pads 34 and 36. Furthermore, in the protection circuit 100, the diode D1 may be connected in multiple stages between the base and the collector of the first transistor Q1. The clamp voltage can be according to the number of stages of the diode D1. Furthermore, a resistance element or a diode may be arranged on a current path form of the first transistor Q1 or the second transistor Q2. There are different variations of format of the protection circuit 100, and the circuit format thereof is not particularly limited to the circuit diagram shown in FIG. 5; the first transistor Q1 may be arranged on a path to ground from the bonding pad 34 and may be ON in an overvoltage state, and the second transistor Q2 may be arranged in parallel to the first transistor Q1, and may be provided on a path to ground from the bonding pad 36. In the embodiment, an explanation has been given concerning cases in which transistor sizes of the first transistor Q1 and the second transistor Q2 are configured to be approximately the same. Here, “approximately the same” means sizes at which inhibition of the LCR oscillation is possible; for example, if in a range of ½ to double, it is possible to adequately inhibit the LCR oscillation. Furthermore, even if the size ratio of the first transistor Q1 and the second transistor Q2 is outside this range, the voltage Vb of the bonding pad 36 may oscillate a little, but compared to cases in which the second transistor Q2 is not provided, it is possible to realize an effect in which the LCR oscillation is suppressed. Furthermore, in the embodiment, an explanation was given concerning cases in which the protection circuit 100 is arranged in the LED driver circuit, but there is no limitation thereto, and various circuits can be used in which the protection circuit and the protected circuit are connected via a line including a significant inductance component such as a bonding wire. In addition, in the embodiment an explanation has been given concerning cases in which the line that has the inductance component is a bonding wire, but there is no limitation thereto. For example, in cases of a wafer level CSP (Chip Size Package), the bonding pads 34 and 36 are connected by post and rewiring. In such cases, since the post and rewiring include the inductance component, by using the protection circuit 100 according to the present embodiment, it is possible to preferably suppress the LCR oscillation. While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.	H	67H01	185H01L	33	00
11776750	US20080102594A1-20080501	METHOD FOR FORMING SEMICONDUCTOR MEMORY CAPACITOR WITHOUT CELL-TO-CELL BRIDGES	ACCEPTED	20080422	20080501	[]	H01L21306	["H01L21306"]	7498267	20070712	20090303	438	706000	85142.0	NHU	DAVID	[{"inventor_name_last": "KIM", "inventor_name_first": "Gyu Hyun", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "CHOI", "inventor_name_first": "Yong Soo", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}]	A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.	1. A method for forming a capacitor comprising steps of: forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate; forming a storage node on the surface of each of the storage node holes in the mold insulating layer; and removing the mold insulating layer comprising steps of: loading the semiconductor substrate with the storage node in the chamber in which a cleaning process, rinse process, and drying process are performed in an in-situ manner; removing the mold insulating layer by introducing an etchant into the chamber; rinsing the semiconductor substrate with the mold insulating layer being removed by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of deionized water and an organic solvent; drying the finally rinsed semiconductor substrate by introducing an iso-propylene alcohol (IPA) vapor into the chamber while discharging the mixed solution of deionized water and organic solvent out of the chamber; and unloading the dried semiconductor substrate. 2. The method according to claim 1, wherein the storage node made of metal. 3. The method according to claim 1, wherein the etchant for removing the mold insulating layer is used with a BOE solution or a diluted HF solution. 4. The method according to claim 3, wherein the diluted HF solution has HF:H2O ratio of 49%:51% with a HF:H2O volume ratio of 1:1˜1:50. 5. The method according to claim 1, wherein the rinsing step of the semiconductor substrate comprises steps of: first rinsing with only the deionized water introduced into the chamber; and second rinsing with the deionized water and O3 by introducing O3 into the chamber. 6. The method according to claim 5, wherein the second rinsing step is performed with O3 maintained at a concentration of 5˜200 ppm. 7. The method according to claim 5, wherein the second rinsing step is performed for 1˜10 minutes. 8. The method according to claim 1, wherein the final rinsing step is performed using a mixed solution of deionized water and any one of IPA, methanol, and ethanol as the organic solvent. 9. The method according to claim 8, wherein the final rinsing step is performed using the mixed solution of the deionized water and the IPA. 10. The method according to claim 9, wherein the IPA is contained at a volume ratio of 1˜99%. 11. The method according to claim 9, wherein the final rinsing step is performed by controlling the temperature of the mixed solution of deionized water and the IPA at 23˜70° C. 12. The method according to claim 1, wherein the drying step of the semiconductor substrate is performed by introducing into the chamber a hot N2 gas as a carrier gas for the IPA vapor. 13. The method according to claim 12, wherein the hot N2 gas has a temperature of 50˜200° C. 14. The method according to claim 12, wherein the IPA has vapor contents of 20˜90% in the mixed gas of the IPA and hot N2 gas. 15. The method according to claim 1, wherein the chamber is used with a dHF & Rinsing Dryer (FRD) type dryer that is capable of performing the cleaning process, rinse process, and drying process in an in-situ manner. 16. The method according to claim 15, wherein the FRD type dryer comprises: a chamber in which all or any combination of the cleaning process, rinse process, and drying process are performed; a cover covering the chamber; a deionized water supply bath, an etchant supply bath, an O3 generator, and an organic solvent bath, all of which are connected to the chamber for providing the deionized water, etchant, O3 and organic solvent, respectively; and an IPA vapor generator connected to the chamber for providing the IPA vapor. 17. The method according to claim 16, wherein the IPA vapor generator is connected to an upper portion of the cover. 18. The method according to claim 16, wherein the FRD type dryer further comprises a hot N2 gas supplier connected to the IPA vapor generator for providing the hot N2 gas. 19. The method according to claim 16, wherein the FRD type dryer further comprises: a supply port connected to the lower side portion of the chamber for introducing the deionized water, etchant, O3 and organic solvent into the chamber; and a drain connected to the bottom portion of the chamber for discharging the solutions introduced into the chamber out of the chamber.	<SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to a method for forming a capacitor, and more particularly to a method for forming a capacitor capable of preventing the generation of cell-to-cell bridges upon the formation of cylindrical metal storage nodes. A capacitor has a structure in which a dielectric layer is interposed between a storage node and a plate node. The capacitance is proportional to the surface area of the node and the dielectric constant of the dielectric layer and inversely proportional to the distance between the nodes, i.e., the thickness of the dielectric layer. Therefore, in order to achieve high capacitance, it is necessary to use a dielectric layer having a high dielectric constant and/or enlarge the surface area of the node and/or reduce the distance between the nodes. A concave-type silicon-insulator-silicon (SIS) capacitor which employs poly-silicon as node materials has been conventionally used. However, such a concave-type SIS capacitor has difficulties in decreasing the surface area and increasing the height of the capacitor due to reduction in the cell size, which limits the SIS capacitor's ability to secure the capacitance. Further, although research concerning dielectric layer having a larger dielectric constant has been actively conducted in a variety of ways with regard to terms of structure and method, leakage current increases the difficulty of using a dielectric layer having a larger dielectric constant. Therefore, a capacitor has been recently developed which employs metals of higher work function as the node materials. Moreover, the capacitor structure is changed from concave to cylindrical, since the smaller size of the storage node limits the extent to which the height of the capacitor may be increased. On the other hand, when forming the cylindrical metal-insulator-metal (MIM) capacitor using the metal node, a mold insulating layer of oxide layer must be removed after forming the cylindrical metal storage node. For these purposes, a cleaning process using a Buffered Oxide Etchant (BOE) was conventionally implemented. Hereinafter, the conventional cleaning process which removes the mold insulating layer upon forming the cylindrical MIM capacitor will be briefly described. First, in order to remove the mold insulating layer, the cleaning process is performed by immersing a semiconductor substrate with the metal storage node in the BOE bath containing BOE solution layer. The resulting substrate with the mold insulating layer being removed is moved into a rinse bath, where it is rinsed with deionized water in order to remove BOE chemical residues. Subsequently, the rinsed resulting substrate is moved into another rinse bath, where it is finally rinsed with the deionized water in order to remove any particles. Then, the final rinsed substrate is moved into a dryer, where it is dried. The drying process is performed using an isopropyl alcohol (IPA) vapor dryer, a Marangoni dryer, or an IPA vapor spray dryer. In the prior art described above, however, the substrate is exposed to the atmosphere each time the substrate is moved to different bathes (i.e., chambers) for performing the cleaning process, rinse process, resulting rinse process, and drying process, and these exposures lead to certain portions of the substrate being dried out. As a result, watermarks are generated between neighboring cylindrical metal storage nodes. Such watermarks may be generated even when the water in the substrate is not completely substituted into the IPA during the drying process. FIG. 1 shows examples of such watermarks 120 generated upon the formation of the cylindrical metal storage node. It can be noted from FIG. 1 that the watermarks 120 are generated between the neighboring cylindrical metal storage nodes 110 . However, if watermarks are generated between the cylindrical metal storage nodes, the watermarks may apply surface tension to the side walls of the neighboring cylindrical metal storage nodes such that cell-to-cell leaning is caused, thereby creating cell-to-cell bridges as shown in FIG. 2 . It is impossible to repair such cell-to-cell bridges, which reduce the manufacturing yield of the semiconductor device.	<SOH> SUMMARY OF THE INVENTION <EOH>Embodiments of the present invention are directed to a method for forming a capacitor which can prevent the formation of watermarks between metal storage nodes upon the formation of cylindrical metal storage nodes. Further, embodiments of the present invention are directed to a method for forming a capacitor which can prevent the formation of cell-to-cell bridges by preventing formation of watermarks between the metal storage nodes. Also, embodiments of the present invention are directed to a method for forming a capacitor, which can prevent reduction in manufacturing yield by preventing the formation of cell-to-cell bridges. In one embodiment, a method for forming a capacitor comprises steps of forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate; forming a storage node on the surface of each of the plurality of storage node holes in the mold insulating layer; and removing the mold insulating layer, wherein the removal step comprises steps of loading the semiconductor substrate with the storage node in the chamber where a cleaning process, rinse process and drying process are performed in an in-situ manner; removing the mold insulating layer by introducing an etchant into the chamber; rinsing the semiconductor substrate with the mold insulating layer being removed by introducing a deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and an organic solvent; drying the finally rinsed semiconductor substrate by introducing an IPA vapor into the chamber while discharging the mixed solution of the deionized water and the organic solvent out of the chamber; and unloading the dried semiconductor substrate. The storage node made of metal. The etchant for removing the mold insulating layer is used with a BOE solution or a diluted HF solution and the diluted HF solution has a ratio of 49% HF:H 2 O and a volume ratio of 1:1˜1:50. The rinsing step of the semiconductor substrate comprises steps of first rinsing with only the deionized water introduced into the chamber; and second, rinsing with the deionized water and O 3 by introducing O 3 into the chamber. The second rinsing step is performed with O 3 maintained at a concentration of 5˜200 ppm for 1˜10 minutes. The final rinsing step is performed using a mixed solution of any one of an IPA, a methanol or an ethanol as the organic solvent and the deionized water. Preferably, the IPA is contained at a volume ratio of 1˜99%, and the final rinsing step is performed by controlling the temperature of the mixed solution of the deionized water and the IPA at 23˜70° C. The drying step of the semiconductor substrate is performed by introducing a hot N 2 gas as a carrier gas for the IPA vapor into the chamber, and the hot N 2 gas has a temperature of 50˜200° C. The IPA has vapor contents of 20˜90% in the mixed gas of the IPA and the hot N 2 gas. The chamber is used with a FRD (dHF & Rinsing Dryer) type dryer in which the cleaning process, rinse process and drying process are performed in an in-situ manner. The FRD type dryer comprises the chamber in which the cleaning process, rinse process and drying process are performed; a cover covering the chamber; a deionized water supply bath, an etchant supply bath, an O 3 generator and an organic solvent bath connected to the chamber for providing the deionized water, the etchant, the O 3 and the organic solvent, respectively; and an IPA vapor generator connected to the chamber for providing the IPA vapor. The IPA vapor generator is connected to an upper portion of the cover. The FRD type dryer further comprises a hot N 2 gas supplier connected to the IPA vapor generator for providing the hot N 2 gas. The FRD type dryer further comprises a supply port connected to the lower side portion of the chamber for introducing the deionized water, etchant, O 3 and organic solvent into the chamber; and a drain connected to the bottom portion of the chamber for discharging the solutions introduced into the chamber out of the chamber	CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to Korean patent application number 10-2006-0106909 filed on Oct. 31, 2006, which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION The present invention relates to a method for forming a capacitor, and more particularly to a method for forming a capacitor capable of preventing the generation of cell-to-cell bridges upon the formation of cylindrical metal storage nodes. A capacitor has a structure in which a dielectric layer is interposed between a storage node and a plate node. The capacitance is proportional to the surface area of the node and the dielectric constant of the dielectric layer and inversely proportional to the distance between the nodes, i.e., the thickness of the dielectric layer. Therefore, in order to achieve high capacitance, it is necessary to use a dielectric layer having a high dielectric constant and/or enlarge the surface area of the node and/or reduce the distance between the nodes. A concave-type silicon-insulator-silicon (SIS) capacitor which employs poly-silicon as node materials has been conventionally used. However, such a concave-type SIS capacitor has difficulties in decreasing the surface area and increasing the height of the capacitor due to reduction in the cell size, which limits the SIS capacitor's ability to secure the capacitance. Further, although research concerning dielectric layer having a larger dielectric constant has been actively conducted in a variety of ways with regard to terms of structure and method, leakage current increases the difficulty of using a dielectric layer having a larger dielectric constant. Therefore, a capacitor has been recently developed which employs metals of higher work function as the node materials. Moreover, the capacitor structure is changed from concave to cylindrical, since the smaller size of the storage node limits the extent to which the height of the capacitor may be increased. On the other hand, when forming the cylindrical metal-insulator-metal (MIM) capacitor using the metal node, a mold insulating layer of oxide layer must be removed after forming the cylindrical metal storage node. For these purposes, a cleaning process using a Buffered Oxide Etchant (BOE) was conventionally implemented. Hereinafter, the conventional cleaning process which removes the mold insulating layer upon forming the cylindrical MIM capacitor will be briefly described. First, in order to remove the mold insulating layer, the cleaning process is performed by immersing a semiconductor substrate with the metal storage node in the BOE bath containing BOE solution layer. The resulting substrate with the mold insulating layer being removed is moved into a rinse bath, where it is rinsed with deionized water in order to remove BOE chemical residues. Subsequently, the rinsed resulting substrate is moved into another rinse bath, where it is finally rinsed with the deionized water in order to remove any particles. Then, the final rinsed substrate is moved into a dryer, where it is dried. The drying process is performed using an isopropyl alcohol (IPA) vapor dryer, a Marangoni dryer, or an IPA vapor spray dryer. In the prior art described above, however, the substrate is exposed to the atmosphere each time the substrate is moved to different bathes (i.e., chambers) for performing the cleaning process, rinse process, resulting rinse process, and drying process, and these exposures lead to certain portions of the substrate being dried out. As a result, watermarks are generated between neighboring cylindrical metal storage nodes. Such watermarks may be generated even when the water in the substrate is not completely substituted into the IPA during the drying process. FIG. 1 shows examples of such watermarks 120 generated upon the formation of the cylindrical metal storage node. It can be noted from FIG. 1 that the watermarks 120 are generated between the neighboring cylindrical metal storage nodes 110. However, if watermarks are generated between the cylindrical metal storage nodes, the watermarks may apply surface tension to the side walls of the neighboring cylindrical metal storage nodes such that cell-to-cell leaning is caused, thereby creating cell-to-cell bridges as shown in FIG. 2. It is impossible to repair such cell-to-cell bridges, which reduce the manufacturing yield of the semiconductor device. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a method for forming a capacitor which can prevent the formation of watermarks between metal storage nodes upon the formation of cylindrical metal storage nodes. Further, embodiments of the present invention are directed to a method for forming a capacitor which can prevent the formation of cell-to-cell bridges by preventing formation of watermarks between the metal storage nodes. Also, embodiments of the present invention are directed to a method for forming a capacitor, which can prevent reduction in manufacturing yield by preventing the formation of cell-to-cell bridges. In one embodiment, a method for forming a capacitor comprises steps of forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate; forming a storage node on the surface of each of the plurality of storage node holes in the mold insulating layer; and removing the mold insulating layer, wherein the removal step comprises steps of loading the semiconductor substrate with the storage node in the chamber where a cleaning process, rinse process and drying process are performed in an in-situ manner; removing the mold insulating layer by introducing an etchant into the chamber; rinsing the semiconductor substrate with the mold insulating layer being removed by introducing a deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and an organic solvent; drying the finally rinsed semiconductor substrate by introducing an IPA vapor into the chamber while discharging the mixed solution of the deionized water and the organic solvent out of the chamber; and unloading the dried semiconductor substrate. The storage node made of metal. The etchant for removing the mold insulating layer is used with a BOE solution or a diluted HF solution and the diluted HF solution has a ratio of 49% HF:H2O and a volume ratio of 1:1˜1:50. The rinsing step of the semiconductor substrate comprises steps of first rinsing with only the deionized water introduced into the chamber; and second, rinsing with the deionized water and O3 by introducing O3 into the chamber. The second rinsing step is performed with O3 maintained at a concentration of 5˜200 ppm for 1˜10 minutes. The final rinsing step is performed using a mixed solution of any one of an IPA, a methanol or an ethanol as the organic solvent and the deionized water. Preferably, the IPA is contained at a volume ratio of 1˜99%, and the final rinsing step is performed by controlling the temperature of the mixed solution of the deionized water and the IPA at 23˜70° C. The drying step of the semiconductor substrate is performed by introducing a hot N2 gas as a carrier gas for the IPA vapor into the chamber, and the hot N2 gas has a temperature of 50˜200° C. The IPA has vapor contents of 20˜90% in the mixed gas of the IPA and the hot N2 gas. The chamber is used with a FRD (dHF & Rinsing Dryer) type dryer in which the cleaning process, rinse process and drying process are performed in an in-situ manner. The FRD type dryer comprises the chamber in which the cleaning process, rinse process and drying process are performed; a cover covering the chamber; a deionized water supply bath, an etchant supply bath, an O3 generator and an organic solvent bath connected to the chamber for providing the deionized water, the etchant, the O3 and the organic solvent, respectively; and an IPA vapor generator connected to the chamber for providing the IPA vapor. The IPA vapor generator is connected to an upper portion of the cover. The FRD type dryer further comprises a hot N2 gas supplier connected to the IPA vapor generator for providing the hot N2 gas. The FRD type dryer further comprises a supply port connected to the lower side portion of the chamber for introducing the deionized water, etchant, O3 and organic solvent into the chamber; and a drain connected to the bottom portion of the chamber for discharging the solutions introduced into the chamber out of the chamber BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows examples of watermarks generated upon the formation of cylindrical metal storage nodes. FIG. 2 shows examples of cell-to-cell leaning caused by the generation of watermarks upon the formation of prior cylindrical metal storage nodes. FIGS. 3A through 3F are cross-sectional views for showing the process steps of a method for forming a cylindrical MIM capacitor in accordance with another embodiment of the present invention. FIG. 4 is a cross-sectional view for showing a HF rinse dryer (FRD) type dryer. FIGS. 5A through 5G are diagrams illustrating the cleaning process, rinse process and drying process in the method for forming a capacitor in accordance with another embodiment of the present invention. DESCRIPTION OF SPECIFIC EMBODIMENTS A cleaning process, rinse process, and drying process for removing a mold insulating layer according to an embodiment of the present invention are performed in an in-situ manner within the same chamber and do not require the substrate to be moved. In this case, since the substrate is not exposed to the atmosphere at the time of the cleaning process, rinse process, and drying process, it is possible to prevent the residual water in the substrate from drying, thereby preventing watermarks from being formed and cell-to-cell bridges from being generated between the metal storage nodes. Further, in an embodiment of the present invention, the final rinse process preceded by the drying process is performed using a mixed solution of deionized water and an organic solvent rather than solely deionized water. In this case, since surface tension of the residual water in the substrate is reduced by the organic solvent, the subsequent drying process can be performed when the surface tension of the water is minimal. Therefore, all of the water on the substrate can be substituted into the isopropyl alcohol (IPA), whereby the generation of watermarks between the metal storage nodes is prevented and thus cell-to-cell bridges are not created. Therefore, according to an embodiment of the present invention, it is possible to prevent watermarks from being generated between the metal storage nodes by performing in-situ processes and using a mixed solution of the deionized water and organic solvent in the final rinse process. As a result, the present invention makes it possible to prevent cell-to-cell leaning and cell-to-cell bridges from being caused by watermarks, and thus prevents a reduction in the manufacturing yield of the semiconductor device. FIG. 3A through 3F are cross-sectional views illustrating the process steps of a method for manufacturing a cylindrical MIM capacitor according to an embodiment of the present invention. Referring to FIG. 3A, an interlayer insulating layer 302 is deposited over a semiconductor substrate 300, and then a contact hole is formed by etching the interlayer insulating layer 302. A storage node contact plug 304 is formed by filling the contact hole with poly-silicon layer. An etch-stop nitrate layer 306 having a thickness of approximately 800A is formed on the interlayer insulating layer 302 including the storage node contact plug 304. The etch-stop nitrate layer 306 is formed at a temperature of approximately 710° C. using N2 gas, NH3 gas, and DCS (Dichlorosilane; SiH2Cl2) gas as a source gas in a furnace. The etch-stop nitrate layer 306 serves to protect against etch attack by the lower structure of the storage node, i.e., the interlayer insulating layer 302 and the storage node contact plug 304 in a subsequent dip-out process for removing the mold insulating layer. Referring to FIG. 3B, the mold insulating layer 308 serving as a mold for the cylindrical storage node is formed on the etch-stop nitrate layer 306. The mold insulating layer 308 is formed as a laminated layer having a PE-TEOS layer, an O3-TEOS layer, an O3-USG layer, a PSG layer, and a PE-TEOS layer or a laminated layer having a BPSG layer and a PE-TEOS layer. Referring to FIG. 3C, a hard mask layer 310 and a mask pattern 312 defining the storage node formation area are sequentially formed on the mold insulating layer 308. The hard mask layer 310 is typically formed with poly-silicon in order to compensate for difficulties in pattern formation, such as collapses occurring at side surfaces of the pattern, since sufficient selectivity cannot be ensured by solely the mask pattern 312 in the subsequent etch process. Referring to FIG. 3D, exposed portions of the hard mask layer 310 are etched by HBr, Cl2, and O2 gases using the mask pattern 312 as an etch mask, and then the mask pattern is removed. The mold insulating layer 308 is etched using the etched hard mask layer 310 as etch mask and using etch selectivity between the oxide layer and the nitrate layer. The mold insulating layer 308 is etched using C4F6, O2 and CF4 gas. The hard mask layer 310 is removed via the etch process using C2F6 and O2 gas. The portions of the etch-stop nitrate layer 306 exposed by etching the mold insulating layer 308 are removed, whereby storage node holes H are formed to expose the storage node contact plug 304. Referring to FIG. 3E, a TiN layer having a thickness of approximately 300 Å is deposited as a storage node conductive layer on surfaces of the hole H and the mold insulating layer 308. The TiN layer is deposited at a temperature of 580° C. via Chemical Vapor Deposition (CVD) using TiCl4 gas. The TiN layer formed on the mold insulating layer 308 is selectively removed by a plasma-etching process using Cl2 and Ar gas as etching gas, whereby the cylindrical metal storage node 314 contacted with the exposed storage node contact plug 304 is formed on the surfaces of the hole H. The storage node 314 can be formed with a W layer or a Ru layer instead of the TiN layer. Referring to FIG. 3F, the mold insulating layer used as the mold for forming the cylindrical metal storage node 314 is removed using a FRD (HF rinse dryer) type dryer in which the cleaning process, the rinse process and the drying process are performed in an in-situ manner within the same equipment, to finish forming the cylindrical metal storage node 314. Although not shown, the dielectric layer and the metal plate node are sequentially formed on the cylindrical metal storage node 314, thereby forming the cylindrical MIM capacitor. FIG. 4 is a cross-sectional view illustrating the FRD type dryer used in the method for forming the capacitor according to an embodiment of the present invention. The FRD type dryer 400 according to an embodiment of the present invention can allow the cleaning process, the rinse process, and the drying process to be performed in an in-situ manner within the same equipment. As shown in FIG. 4, the FRD type dryer 400 includes a chamber 410 in which the cleaning process, rinse process and drying process are performed, a cover 420 covering the chamber 410, a deionized water supply bath 430 providing the deionized water, etchant, O3 and the organic solvent, respectively, an etchant supply bath 440, an O3 generator 450, and an organic solvent bath 460, and an iso-propylene alcohol (IPA) vapor generator 470 which is connected to the chamber 410 for providing the IPA vapor. The FRD type dryer 400 according to an embodiment of the present invention further includes a hot N2 gas supplier 480 which is connected to the IPA vapor generator 470 for providing a hot N2 gas. The lower side portion of the chamber 410 is connected to a supply port 490 through which deionized water, etchant, O3 and organic solvent are introduced into the chamber 410. The bottom of the chamber 410 is connected to a drain 492 through which the solutions and the gas introduced into the chamber 410 are discharged out of the chamber 410. The IPA vapor generator 470 is connected to an upper portion of the cover 420 by the IPA vapor supply port 494. In order to remove the mold insulating layer 308 using the FRD type dryer 400, the cleaning process for etching the insulating layer using a diluted HF solution within the chamber, the rinse process for rinsing the cleaned substrate, and the drying process for drying the rinsed substrate are all performed in an in-situ manner. Therefore, the substrate is not exposed to the atmosphere during the processes. More specifically, if the semiconductor substrate with the metal storage node is carried into the chamber 410, the etchant, deionized water, O3, organic solvent and IPA vapor containing the hot N2 gas are sequentially introduced into the chamber 410 via the supply port 490 connected to the bottom side portion of the chamber 410, whenever the cleaning process, rinse process and drying process are performed. At this time, the etchant, deionized water, O3, and organic solvent are introduced into the chamber 410 via the supply port 490 in accordance with the on/off status of the valve 496 connected to the supply port 490, and the IPA vapor is introduced into the chamber 410 via the IPA vapor supply port 494 above the chamber 410. Hot N2 gas at a temperature of 80˜200° C. is introduced into the chamber 410 as a carrier gas together with the IPA vapor. Further, whenever each process is finished, the solution used in the prior process is discharged out of the chamber 410 via the drain 492 located at the bottom of the chamber 410. Moreover, new solution necessary for the next process is introduced into the chamber 410 via the supply port 490. Therefore, since the present invention allows the cleaning process, rinse process and drying process for removing the mold insulating layer to be performed in an in-situ manner within the chamber without a need to move the semiconductor substrate, it is possible to prevent watermarks from being formed between the metal storage nodes, thereby preventing the generation of cell-to-cell leaning and cell-to-cell bridges, which are caused by watermarks. Hereinafter, referring to FIGS. 5A through 5G, the cleaning process, rinse process and drying process will be described specifically using the above-mentioned FRD type dryer. Referring to FIG. 5A, the semiconductor substrate 500 with the metal storage node is loaded into the chamber 410 of the FRD type dryer. Referring to FIG. 5B, the etchant 442 is introduced from the etchant supply bath 440 into the chamber 410 via the supply port 490 connected to a lower side portion of the chamber 410 such that the cleaning process for removing the mold insulating layer may be performed. It is preferable to employ the BOE solution or the diluted HF solution as the etchant and to use a diluted HF solution of 49% (HF):51% (H2O) with HF:H2O volume ratio of 1:1˜1:50. Referring to FIG. 5C, the etchant is discharged out of the chamber 410 via the drain 492 located at the bottom of the chamber 410, and deionized water 432 is subsequently introduced from the deionized water supply bath 430 into the chamber 410 via the supply port 490 such that the semiconductor substrate 500 with the mold insulating layer being removed from it is first rinsed. Referring to FIG. 5D, O3 is introduced into the chamber with the deionized water via the supply port 490 connected to the chamber 410 such that the first rinsed semiconductor substrate 500 may be rinsed a second time with the deionized water and O3 solution 452. The deionized water and O3 solution 452 maintains an O3 concentration of 5˜200 ppm. The second rinse process using the deionized water and O3 solution 452 is performed for 1˜10 minutes. Referring to FIG. 5E, the deionized water and O3 solution 452 is discharged out of the chamber 410 via the drain 492, and the deionized water and organic solvent are then introduced into the chamber 410 from the deionized water supply bath 430 and the organic solvent bath 460, respectively, via the supply port 490 such that the second rinsed semiconductor substrate 500 may be finally rinsed with a mixed solution 462 of deionized water and organic solvent. Any one of IPA, methanol, and ethanol can be used as the organic solvent, although IPA is preferred. When IPA is used, the IPA is maintained at a volume ratio of 1˜99% in the mixed solution 462 of deionized water and organic solvent. The mixed solution of deionized water and organic solvent is controlled at a temperature of 23˜70° C. Therefore, the final rinse process is performed using the mixed solution of deionized water and organic solvent, thereby reducing the surface tension of the residual water in the semiconductor substrate. Referring to FIG. 5F, the mixed solution of deionized water and organic solvent is discharged out of the chamber 410 via the drain 492. Referring to FIG. 5G, the IPA vapor is introduced into the chamber 410 from the IPA vapor generator 470 via the IPA vapor supply port 494 so that the final rinsed semiconductor substrate may be dried. At this time, the hot N2 gas at a temperature of 50˜200° C. is released into the IPA vapor generator 470 from the hot N2 gas supplier 480 and acts as a carrier gas for the IPA vapor, whereby the hot N2 gas is introduced into the chamber 410 together with the IPA vapor. At this time, the mixed gas of IPA vapor and hot N2 gas has IPA vapor contents of 20˜90%. Herein, the present invention can allow the residual water remaining in the substrate to be substituted into the IPA, since larger amounts of IPA vapor flow into the chamber 410 one time in a state such that the surface tension of the residual water in the substrate is minimized. Further, the present invention can prevent the watermarks forming between the metal storage nodes, and thus prevent cell-to-cell leaning and cell-to-cell bridges caused by the generation of watermarks, since the cleaning process and subsequent rinse and drying processes for removing the mold insulating layer may be performed in in-situ within the same chamber. As is apparent from the above description, the present invention can allow the cleaning process, rinse process, and drying process for removing the mold insulating layer to be performed in an in-situ manner upon forming the cylindrical storage node, as well as the final rinse process performed with the mixed solution of deionized water and organic solvent such that the subsequent drying process is performed in a state where the surface tension is minimized. Therefore, the present invention prevents the formation of watermarks between the metal storage nodes and thus prevents cell-to-cell leaning and cell-to-cell bridges caused by the generation of watermarks, which results in an improvement in the manufacturing yield of the semiconductor device. Although specific embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.	H	67H01	185H01L	213	06
11697779	US20070190694A1-20070816	INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR	ACCEPTED	20070801	20070816	[]	H01L2100	["H01L2100"]	7413933	20070409	20080819	438	123000	72874.0	HOANG	QUOC	[{"inventor_name_last": "Punzalan", "inventor_name_first": "Jeffrey", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}, {"inventor_name_last": "Ku", "inventor_name_first": "Jae Hun", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}, {"inventor_name_last": "Han", "inventor_name_first": "Byung Joon", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}]	A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.	1. A method of manufacturing a semiconductor comprising: providing a leadframe having a die attach paddle and a number of leads; forming a recess in the die attach paddle to provide a number of mold dams around the periphery of the die attach paddle; positioning an integrated circuit in the recess; forming electrical connections between the integrated circuit and the number of leads; and forming an encapsulant over the integrated circuit and around the number of mold dams. 2. The method of manufacturing a semiconductor as claimed in claim 1 wherein forming a recess in the die attach paddle forms a recess about fifty-five percent of the way through the die attach paddle. 3. The method of manufacturing a semiconductor as claimed in claim 1 wherein providing a number of mold dams around the periphery of the die attach paddle provides the number of mold dams in a position of at least one of at the corners of the die attach paddle, intermediate the corners of the die attach paddle, and combinations thereof. 4. The method of manufacturing a semiconductor as claimed in claim 1 wherein forming an encapsulant flows the encapsulant into the spaces between the mold dams and over the integrated circuit. 5. The method of manufacturing a semiconductor as claimed in claim 1 wherein forming the encapsulant forms at least one of plastic, epoxy, ceramic, and combinations thereof. 6. A method of manufacturing a semiconductor comprising: providing a leadframe having a die attach paddle and a number of leads; etching a recess at least half way into the die attach paddle to provide a number of mold dams around the periphery of the die attach paddle; bonding an integrated circuit in the recess; wire bonding electrical connections between the integrated circuit and the number of leads; and forming an encapsulant over the integrated circuit and around the number of mold dams. 7. The method of manufacturing a semiconductor as claimed in claim 6 wherein forming a recess into the die attach paddle forms a recess about fifty-five percent of the way through the die attach paddle. 8. The method of manufacturing a semiconductor as claimed in claim 6 wherein providing a number of mold dams around the periphery of the die attach paddle provides the number of mold dams in a position of at least one of at the corners of the die attach paddle, intermediate the comers of the die attach paddle, and combinations thereof. 9. The method of manufacturing a semiconductor as claimed in claim 6 wherein forming an encapsulant flows the encapsulant into the spaces between the mold dams and over the integrated circuit. 10. The method of manufacturing a semiconductor as claimed in claim 6 wherein forming the encapsulant forms an encapsulant of at least one of plastic, epoxy, ceramic, and combinations thereof. 11. A semiconductor comprising: a leadframe having a die attach paddle and a number of leads; the die attach paddle having a recess to provide a number of mold dams around the periphery of the die attach paddle; an integrated circuit in the recess; electrical connections between the integrated circuit and the number of leads; and an encapsulant over the integrated circuit and around the number of mold dams. 12. The semiconductor as claimed in claim 11 wherein the recess in the die attach paddle is about fifty-five percent of the way through the die attach paddle. 13. The semiconductor as claimed in claim 11 wherein the number of mold dams is positioned in at least one of at the corners of the die attach paddle, intermediate the corners of the die attach paddle, and combinations thereof. 14. The semiconductor as claimed in claim 11 wherein the encapsulant substantially fills the spaces between the number of mold dams. 15. The semiconductor as claimed in claim 11 wherein the encapsulant comprises at least one of plastic, epoxy, ceramic, and combinations thereof. 16. A semiconductor comprising: a leadframe having a die attach paddle and a number of leads; the die attach paddle having a recess at least half way into the die attach paddle to provide a number of mold dams around the periphery of the die attach paddle; an integrated circuit in the recess; electrical connections between the integrated circuit and the number of leads; and an encapsulant over the integrated circuit and around the number of mold dams. 17. The semiconductor as claimed in claim 16 wherein the recess into the die attach paddle is about fifty-five percent of the way through the die attach paddle. 18. The semiconductor as claimed in claim 16 wherein the number of mold dams around the periphery of the die attach paddle is positioned in at least one of at the corners of the die attach paddle, intermediate the comers of the die attach paddle, and combinations thereof. 19. The semiconductor as claimed in claim 16 wherein the encapsulant substantially fills the spaces between the mold dams. 20. The semiconductor as claimed in claim 16 wherein the encapsulant comprises an encapsulant of at least one of plastic, epoxy, ceramic, and combinations thereof.	<SOH> BACKGROUND ART <EOH>In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of a multiplicity of interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. Semiconductor devices are formed in the various layers of the integrated circuit chips using photolithographic techniques. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards. Packages including integrated circuit chips typically have numerous external pins that are mechanically attached by solder or a variety of other known techniques to conductor patterns on the printed wiring board. Typically, the packages on which these integrated semiconductor chips are mounted include a substrate or other chip mounting device. One example of such a substrate is a leadframe. High performance leadframes typically are multi-layer structures including power, ground, and signal planes. Leadframes also typically include at least an area on which an integrated circuit chip is mounted and a plurality of power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor chip are electronically attached. Semiconductor integrated chips may be attached to the leadframe using adhesive or any other techniques for attaching such chips to a leadframe which are commonly known to those skilled in the art, such as soldering. The power, ground and signal sites on the chip may then be electrically connected to selected power, ground and signal plane or individual leads of the leadframe. Leadframes have been used extensively in the integrated circuit (IC) packaging industry mainly because of their low manufacturing cost and high reliability. Leadframe packages remain a cost-effective solution for packaging integrated circuits despite the introduction of various leadless packages in recent years. Typical leadframe packages include a die attach paddle, or pad, surrounded by a number of leads. An integrated circuit chip, is attached to the die attach paddle using a conductive adhesive such as silver epoxy. The conductive adhesive is cured after die attach. After the die is attached to the die paddle, a wire-bonding process is used to make electrical interconnections between the integrated circuit and the leads of the leadframe. After wire bonding, the leadframe with the integrated circuit attached is encapsulated using a molding compound. Such enclosures may include encapsulation in a plastic or a multi-part housing made of plastic ceramic, or metal. The enclosure protects the leadframe and the attached chip from physical, electrical, and/or chemical damage. Finally, post mold curing and singulation steps are conducted to complete the packaging process. The leadframe and attached chip(s) may then be mounted on, for example, a circuit board, or card along with other leadframes or devices. The circuit board or card may then be incorporated into a wide variety of devices such as computers, automobiles, or appliances, among others. One problem that persists with leadframes is that the integrated circuits mounted on these leadframes are subject to failure due to moisture penetration of the integrated circuit package. If the molding compound is not securely attached to the leadframe, moisture or other contaminants can contact the integrated circuit thereby causing failures. Another problem is that the molding compound does not flow evenly over the entire leadframe resulting in areas where moisture or other contaminants may contact the integrated circuit thereby contributing to the failure of the integrated circuit. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a partial cross-sectional view of a leadframe in an intermediate stage of manufacture in accordance with the present invention; FIG. 2 is the structure of FIG. 1 after processing of a mask on the surface of the leadframe; FIG. 3 is the structure of FIG. 2 after an etch process to form a die paddle; FIG. 4 is the structure of FIG. 3 after an integrated circuit is attached to the die paddle of the leadframe; FIG. 5 is the structure of FIG. 4 after encapsulation of the integrated circuit; FIG. 6 is a plan view of the structure of FIG. 5 manufactured in accordance with the present invention without an encapsulant; FIG. 7 is a plan view of another embodiment of a leadframe having four mold dams manufactured in accordance with the present invention; and FIG. 8 is a flow chart of a method for manufacturing a leadframe in accordance with the present invention. detailed-description description="Detailed Description" end="lead"?	CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/478,433 filed Jun. 12, 2003, and the subject matter thereof is hereby incorporated herein by reference thereto. This application is a continuation of U.S. Non Provisional Patent Application Ser. No. 10/850,220 filed May 19, 2004. TECHNICAL FIELD The present invention relates generally to semiconductor technology, and more particularly to a method and apparatus for an integrated circuit leadframe package. BACKGROUND ART In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of a multiplicity of interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. Semiconductor devices are formed in the various layers of the integrated circuit chips using photolithographic techniques. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards. Packages including integrated circuit chips typically have numerous external pins that are mechanically attached by solder or a variety of other known techniques to conductor patterns on the printed wiring board. Typically, the packages on which these integrated semiconductor chips are mounted include a substrate or other chip mounting device. One example of such a substrate is a leadframe. High performance leadframes typically are multi-layer structures including power, ground, and signal planes. Leadframes also typically include at least an area on which an integrated circuit chip is mounted and a plurality of power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor chip are electronically attached. Semiconductor integrated chips may be attached to the leadframe using adhesive or any other techniques for attaching such chips to a leadframe which are commonly known to those skilled in the art, such as soldering. The power, ground and signal sites on the chip may then be electrically connected to selected power, ground and signal plane or individual leads of the leadframe. Leadframes have been used extensively in the integrated circuit (IC) packaging industry mainly because of their low manufacturing cost and high reliability. Leadframe packages remain a cost-effective solution for packaging integrated circuits despite the introduction of various leadless packages in recent years. Typical leadframe packages include a die attach paddle, or pad, surrounded by a number of leads. An integrated circuit chip, is attached to the die attach paddle using a conductive adhesive such as silver epoxy. The conductive adhesive is cured after die attach. After the die is attached to the die paddle, a wire-bonding process is used to make electrical interconnections between the integrated circuit and the leads of the leadframe. After wire bonding, the leadframe with the integrated circuit attached is encapsulated using a molding compound. Such enclosures may include encapsulation in a plastic or a multi-part housing made of plastic ceramic, or metal. The enclosure protects the leadframe and the attached chip from physical, electrical, and/or chemical damage. Finally, post mold curing and singulation steps are conducted to complete the packaging process. The leadframe and attached chip(s) may then be mounted on, for example, a circuit board, or card along with other leadframes or devices. The circuit board or card may then be incorporated into a wide variety of devices such as computers, automobiles, or appliances, among others. One problem that persists with leadframes is that the integrated circuits mounted on these leadframes are subject to failure due to moisture penetration of the integrated circuit package. If the molding compound is not securely attached to the leadframe, moisture or other contaminants can contact the integrated circuit thereby causing failures. Another problem is that the molding compound does not flow evenly over the entire leadframe resulting in areas where moisture or other contaminants may contact the integrated circuit thereby contributing to the failure of the integrated circuit. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art. DISCLOSURE OF THE INVENTION The present invention provides a semiconductor including a leadframe having a die attach paddle and a number of leads. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams. The present invention reduces failure of semiconductors due to moisture penetration of the integrated circuit package. The molding compound is attached more securely to the leadframe so moisture or other contaminants cannot contact the integrated circuit thereby causing failures. Also, the molding compound flows evenly reducing the areas where moisture or other contaminants may contact the integrated circuit thereby reducing the failure of the integrated circuit. Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view of a leadframe in an intermediate stage of manufacture in accordance with the present invention; FIG. 2 is the structure of FIG. 1 after processing of a mask on the surface of the leadframe; FIG. 3 is the structure of FIG. 2 after an etch process to form a die paddle; FIG. 4 is the structure of FIG. 3 after an integrated circuit is attached to the die paddle of the leadframe; FIG. 5 is the structure of FIG. 4 after encapsulation of the integrated circuit; FIG. 6 is a plan view of the structure of FIG. 5 manufactured in accordance with the present invention without an encapsulant; FIG. 7 is a plan view of another embodiment of a leadframe having four mold dams manufactured in accordance with the present invention; and FIG. 8 is a flow chart of a method for manufacturing a leadframe in accordance with the present invention. BEST MODE FOR CARRYING OUT THE INVENTION In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the present invention are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the FIGs. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the leadframe, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane. The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure. Referring now to FIG. 1, therein is shown a partial cross-sectional view of a semiconductor 100 in an intermediate stage of manufacture in accordance with the present invention. The semiconductor 100 includes a leadframe 102. The leadframe has an upper surface 104 and a lower surface 106. Referring now to FIG. 2, therein is shown the structure of FIG. 1 after processing to form a mask 200 on the upper surface 104 of the leadframe 102. The mask 200 is formed by depositing a layer of photoresist 202 on the upper surface 104 of the leadframe 102 and processing the layer of photoresist 202 to form the mask 200. Referring now to FIG. 3, therein is shown the structure of FIG. 2 after an etch process 300 has been performed on the upper surface 104 of the leadframe 102 using the mask 200. The leadframe 102 is etched using the mask 200 to form a die attach paddle 302 and a number of leads 304 surrounding the die attach paddle 302. A recess 308 is formed in the leadframe 102 by etching only partially through the leadframe 102 to form a number of mold dams 310 in the die attach paddle 302. The recess 308 is formed interior to the peripheral areas of the die attach paddle 302. It has been discovered that etching the die paddle 302 of the leadframe 102 to about fifty-five percent (55%) of the thickness of the die paddle 302 to form the recess 308 results in providing suitable thickness for the number of mold dams 310 while maintaining the stiffness of the die paddle 302. Referring now to FIG. 4, therein is shown the structure of FIG. 3 after an integrated circuit 400 is attached to the die paddle 302 of the leadframe 102. The mask 200 shown in FIG. 3 has been removed. A bonding compound 402, such as an epoxy, has been deposited in the recess 308 in the die attach paddle 302. The integrated circuit 400 is positioned on the die attach paddle 302 to be bonded by the bonding compound 402. When the recess 308 is sufficiently deep, the integrated circuit 400 will be positioned partially below the upper surface 104 of the die attach paddle 302 and surrounded by the number of mold dams 310. The integrated circuit 400 is therefore locked in position by the number of mold dams 310 to provide additional stability for the integrated circuit 400. Referring now to FIG. 5, therein is shown the structure of FIG. 4 after encapsulation of the integrated circuit 400. The integrated circuit 400 is electrically connected to the number of leads 304 using a number of bonding wires 500. An encapsulant 502, such as plastic, epoxy, ceramic, or other suitable material, is formed over the integrated circuit 400, the number of bonding wires 500, and a portion of the number of leads 304. The encapsulant 502 also fills the space between the number of leads 304 and the die attach paddle 302. During the encapsulation process, a mold (not shown) is used to direct the flow of the encapsulant 502 into any spaces between the mold dams 310 thereby providing a locking mechanism for the encapsulant 502. It is therefore more difficult for the encapsulant 502 to pull away from the die attach paddle 302 or the integrated circuit 400 thereby enhancing the integrity and stability of the semiconductor 100. Moisture or other contaminants cannot as easily penetrate the semiconductor 100. Referring now to FIG. 6, therein is shown a plan view of the structure of FIG. 5 without the encapsulant 502 having the number of mold dams 310 manufactured in accordance with the present invention. The leadframe 102 includes the die attach paddle 302 and the number of leads 304 surrounding the die attach paddle 302. The die attach paddle 302 has been processed to form the number of mold dams 310 around the periphery of the die attach paddle 302 and the recess in the die attach paddle 302. The bonding compound 402 shown in FIG. 5 is deposited on the die attach paddle 302. The integrated circuit 400 is positioned over the bonding compound 402 to attach the integrated circuit 400 to the die attach paddle 302. The encapsulant 502 fills the spaces between the mold dams 310 to provide the locking mechanism for locking the encapsulant 502 and the die attach paddle 302. An edge 600 is formed during a singulation process after the semiconductor is encapsulated. Referring now to FIG. 7 therein is shown a plan view of another embodiment of the semiconductor 100 having four mold dams 310 manufactured in accordance with the present invention. The number of mold dams 310 is formed at each corner of the die attach paddle 302 to form four mold dams. It will be apparent to those skilled in the art that a particular semiconductor may have any number of mold dams 310 depending upon the design requirements for a particular semiconductor. The encapsulant 502 fills the spaces between the mold dams 310 to provide the locking mechanism for locking the encapsulant 502 and the die attach paddle 302. An edge 700 is formed during a singulation process after the semiconductor is encapsulated. Referring now to FIG. 8 therein is shown a flow chart of a method 800 for manufacturing a semiconductor in accordance with the present invention. The method 800 includes providing a leadframe having a die attach paddle and a number of leads in a block 802; forming a recess in the die attach paddle to provide a number of mold dams around the periphery of the die attach paddle in a block 804; positioning an integrated circuit in the recess in a block 806; forming electrical connections between the integrated circuit and the number of leads in a block 808; and forming an encapsulant over the integrated circuit and around the number of mold dams in a block 810. Thus, it has been discovered that the method and apparatus of the present invention furnish important and heretofore unavailable solutions, capabilities, and functional advantages for the manufacture of semiconductors. The resulting process and configurations are straightforward, economical, uncomplicated, highly versatile, and effective, use conventional technologies, and are thus readily suited for manufacturing semiconductor devices and are fully compatible with conventional manufacturing processes and technologies. While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.	H	67H01	185H01L	21	00
11809719	US20110068350A1-20110324	Diamond semiconductor devices and associated methods	ACCEPTED	20110309	20110324	[]	H01L310312	["H01L310312", "H01L21223"]	8110846	20070531	20120207	257	079000	63495.0	TORNOW	MARK	[{"inventor_name_last": "Sung", "inventor_name_first": "Chien-Min", "inventor_city": "Tansui", "inventor_state": "", "inventor_country": "TW"}]	Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In one aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers.	1. A semiconductor device, comprising: a diamond substrate; a transparent diamond layer positioned parallel to the diamond substrate; a plurality of semiconductor layers coupled between the transparent diamond layer and the diamond substrate; and a SiC layer coupled directly to the transparent diamond layer and facing the plurality of semiconductor layers, such that the SiC layer is coupled directly to at least one of the plurality of semiconductor layers, and wherein light generated in the semiconductor layers is emitted through the transparent diamond layer. 2. The device of claim 1, wherein the semiconductor device is an LED device and the plurality of semiconductor layers is a plurality of LED nitride layers. 3. The device of claim 1, wherein the plurality of semiconductor layers is arranged in series between the diamond substrate and the transparent diamond layer. 4. (canceled) 5. The device of claim 1, wherein the SiC layer is a single crystal SiC layer. 6. The device of claim 5, wherein the SiC layer has a crystal lattice that is substantially epitaxially matched to the transparent diamond layer. 7. The device of claim 5, wherein the SiC layer has a crystal lattice that is substantially epitaxially matched to at least one of the semiconductor layers. 8. The device of claim 1, further comprising at least one of a p-type electrode or an n-type electrode electrically coupled to at least one of the semiconductor layers. 9. The device of claim 8, wherein the diamond substrate is p-type doped, and the p-type electrode is the p-type doped diamond substrate. 10. The device of claim 9, wherein the diamond substrate is doped with boron to form the p-type doped diamond substrate. 11. The device of claim 1, wherein the plurality of semiconductor layers includes at least one member selected from the group consisting of silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium antimonide, gallium indium arsenide phosphide, aluminum phosphide, aluminum arsenide, aluminum gallium arsenide, gallium nitride, boron nitride, aluminum nitride, indium arsenide, indium phosphide, indium antimonide, indium nitride, and combinations thereof. 12. The device of claim 11, wherein at least one of the semiconductor layers is gallium nitride. 13. The device of claim 11, wherein at least one of the semiconductor layers is aluminum nitride. 14. A method of making a semiconductor device, comprising: forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer; depositing epitaxially at least one of a plurality of semiconductor layers on the SiC layer opposite the transparent diamond layer; and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond substrate is oriented parallel to the transparent diamond layer, and the plurality of semiconductor layers are located between the transparent diamond layer and the diamond substrate. 15. The method of claim 14, further comprising electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. 16. The method of claim 14, wherein the plurality of semiconductor layers includes at least one member selected from the group consisting of silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium antimonide, gallium indium arsenide phosphide, aluminum phosphide, aluminum arsenide, aluminum gallium arsenide, gallium nitride, boron nitride, aluminum nitride, indium arsenide, indium phosphide, indium antimonide, indium nitride, and combinations thereof. 17. The method of claim 14, wherein the semiconductor layer is gallium nitride. 18. The method of claim 14, wherein the semiconductor layer is aluminum nitride.	<SOH> BACKGROUND OF THE INVENTION <EOH>In many developed countries, major portions of the populations consider electronic devices to be integral to their lives. Such increasing use and dependence has generated a demand for electronics devices that are smaller and faster. As electronic circuitry increases in speed and decreases in size, cooling of such devices becomes problematic. Electronic devices generally contain printed circuit boards having integrally connected electronic components that allow the overall functionality of the device. These electronic components, such as processors, transistors, resistors, capacitors, light-emitting diodes (LEDs), etc., generate significant amounts of heat. As it builds, heat can cause various thermal problems associated with such electronic components. Significant amounts of heat can affect the reliability of an electronic device, or even cause it to fail by, for example, causing burn out or shorting both within the electronic components themselves and across the surface of the printed circuit board. Thus, the buildup of heat can ultimately affect the functional life of the electronic device. This is particularly problematic for electronic components with high power and high current demands, as well as for the printed circuit boards that support them. Various cooling devices have been employed such as fans, heat sinks, Peltier and liquid cooling devices, etc., as means of reducing heat buildup in electronic devices. As increased speed and power consumption cause increasing heat buildup, such cooling devices generally must increase in size to be effective and may also require power to operate. For example, fans must be increased in size and speed to increase airflow, and heat sinks must be increased in size to increase heat capacity and surface area. The demand for smaller electronic devices, however, not only precludes increasing the size of such cooling devices, but may also require a significant size decrease. As a result, methods and associated devices are being sought to provide adequate cooling of electronic devices while minimizing size and power constraints placed on such devices due to cooling.	<SOH> SUMMARY OF THE INVENTION <EOH>Accordingly, the present invention provides diamond semiconductor devices having improved thermal properties and methods for making such devices. In one aspect, for example, a semiconductor device is provided having a diamond substrate, a transparent diamond layer positioned parallel to the diamond substrate, and a plurality of semiconductor layers coupled between the transparent diamond layer and the diamond substrate. In one specific aspect, the semiconductor device is an LED device and the plurality of semiconductor layers is a plurality of LED nitride layers. The plurality of semiconductor layers can be arranged in a variety of configuration, however in one aspect the plurality of semiconductor layers may be arranged in series between the diamond substrate and the transparent diamond layer. In various aspects of the present invention, semiconductor devices are provided having very low lattice mismatches between material layers. Such low lattice mismatches may be achieved through the use of a high quality SiC layer. In one aspect, for example, the device may further include a SiC layer coupled to the transparent diamond layer and facing the plurality of semiconductor layers, such that the SiC layer is coupled to at least one of the plurality of semiconductor layers. In another aspect the SiC layer is a single crystal SiC layer. In yet another aspect the SiC layer has a crystal lattice that is substantially epitaxially matched to the transparent diamond layer. In a further aspect, the SiC layer has a crystal lattice that is substantially epitaxially matched to at least one of the semiconductor layers. The devices according to aspects of the present invention also may include various electrodes. In one aspect, for example, the device may include at least one of a p-type electrode or an n-type electrode electrically coupled to at least one of the semiconductor layers. In another aspect, the diamond substrate may be p-type doped, and the p-type electrode is the p-type doped diamond substrate. In one specific aspect, the diamond substrate is doped with boron to form the p-type doped diamond substrate. A variety of semiconductor materials may be used in various aspects the present invention depending on the intended use of resulting devices. For example, and without limitation, the plurality of semiconductor layers may include at least one of silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium antimonide, gallium indium arsenide phosphide, aluminum phosphide, aluminum arsenide, aluminum gallium arsenide, gallium nitride, boron nitride, aluminum nitride, indium arsenide, indium phosphide, indium antimonide, indium nitride, and combinations thereof. In one specific aspect the semiconductor layers may include gallium nitride. In another specific aspect the semiconductor layers may include aluminum nitride. The present invention also provides methods for making semiconductor devices. In one aspect such a method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In another aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. There has thus been outlined, rather broadly, various features of the invention so that the detailed description thereof that follows may be better understood, and so that the present contribution to the art may be better appreciated. Other features of the present invention will become clearer from the following detailed description of the invention, taken with the accompanying claims, or may be learned by the practice of the invention.	FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and associated methods. Accordingly, the present invention involves the electrical and material science fields. BACKGROUND OF THE INVENTION In many developed countries, major portions of the populations consider electronic devices to be integral to their lives. Such increasing use and dependence has generated a demand for electronics devices that are smaller and faster. As electronic circuitry increases in speed and decreases in size, cooling of such devices becomes problematic. Electronic devices generally contain printed circuit boards having integrally connected electronic components that allow the overall functionality of the device. These electronic components, such as processors, transistors, resistors, capacitors, light-emitting diodes (LEDs), etc., generate significant amounts of heat. As it builds, heat can cause various thermal problems associated with such electronic components. Significant amounts of heat can affect the reliability of an electronic device, or even cause it to fail by, for example, causing burn out or shorting both within the electronic components themselves and across the surface of the printed circuit board. Thus, the buildup of heat can ultimately affect the functional life of the electronic device. This is particularly problematic for electronic components with high power and high current demands, as well as for the printed circuit boards that support them. Various cooling devices have been employed such as fans, heat sinks, Peltier and liquid cooling devices, etc., as means of reducing heat buildup in electronic devices. As increased speed and power consumption cause increasing heat buildup, such cooling devices generally must increase in size to be effective and may also require power to operate. For example, fans must be increased in size and speed to increase airflow, and heat sinks must be increased in size to increase heat capacity and surface area. The demand for smaller electronic devices, however, not only precludes increasing the size of such cooling devices, but may also require a significant size decrease. As a result, methods and associated devices are being sought to provide adequate cooling of electronic devices while minimizing size and power constraints placed on such devices due to cooling. SUMMARY OF THE INVENTION Accordingly, the present invention provides diamond semiconductor devices having improved thermal properties and methods for making such devices. In one aspect, for example, a semiconductor device is provided having a diamond substrate, a transparent diamond layer positioned parallel to the diamond substrate, and a plurality of semiconductor layers coupled between the transparent diamond layer and the diamond substrate. In one specific aspect, the semiconductor device is an LED device and the plurality of semiconductor layers is a plurality of LED nitride layers. The plurality of semiconductor layers can be arranged in a variety of configuration, however in one aspect the plurality of semiconductor layers may be arranged in series between the diamond substrate and the transparent diamond layer. In various aspects of the present invention, semiconductor devices are provided having very low lattice mismatches between material layers. Such low lattice mismatches may be achieved through the use of a high quality SiC layer. In one aspect, for example, the device may further include a SiC layer coupled to the transparent diamond layer and facing the plurality of semiconductor layers, such that the SiC layer is coupled to at least one of the plurality of semiconductor layers. In another aspect the SiC layer is a single crystal SiC layer. In yet another aspect the SiC layer has a crystal lattice that is substantially epitaxially matched to the transparent diamond layer. In a further aspect, the SiC layer has a crystal lattice that is substantially epitaxially matched to at least one of the semiconductor layers. The devices according to aspects of the present invention also may include various electrodes. In one aspect, for example, the device may include at least one of a p-type electrode or an n-type electrode electrically coupled to at least one of the semiconductor layers. In another aspect, the diamond substrate may be p-type doped, and the p-type electrode is the p-type doped diamond substrate. In one specific aspect, the diamond substrate is doped with boron to form the p-type doped diamond substrate. A variety of semiconductor materials may be used in various aspects the present invention depending on the intended use of resulting devices. For example, and without limitation, the plurality of semiconductor layers may include at least one of silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium antimonide, gallium indium arsenide phosphide, aluminum phosphide, aluminum arsenide, aluminum gallium arsenide, gallium nitride, boron nitride, aluminum nitride, indium arsenide, indium phosphide, indium antimonide, indium nitride, and combinations thereof. In one specific aspect the semiconductor layers may include gallium nitride. In another specific aspect the semiconductor layers may include aluminum nitride. The present invention also provides methods for making semiconductor devices. In one aspect such a method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer, and coupling a diamond substrate to at least one of the plurality of semiconductor layers such that the diamond support is oriented parallel to the transparent diamond layer. In another aspect such a method may further include electrically coupling at least one of a p-type electrode or an n-type electrode to at least one of the plurality of semiconductor layers. There has thus been outlined, rather broadly, various features of the invention so that the detailed description thereof that follows may be better understood, and so that the present contribution to the art may be better appreciated. Other features of the present invention will become clearer from the following detailed description of the invention, taken with the accompanying claims, or may be learned by the practice of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-section view of a semiconductor device in accordance with one embodiment of the present invention. FIG. 2 is a cross-section view of a semiconductor device in accordance with one embodiment of the present invention. FIG. 3 is a cross-section view of a semiconductor device being constructed in accordance with one embodiment of the present invention. FIG. 4 is a cross-section view of an LED device in accordance with one embodiment of the present invention. FIG. 5 is a cross-section view of an LED device in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Definitions In describing and claiming the present invention, the following terminology will be used in accordance with the definitions set forth below. The singular forms “a,” “an,” and, “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a heat source” includes reference to one or more of such sources, and reference to “the diamond layer” includes reference to one or more of such layers. The terms “heat transfer,” “heat movement,” and “heat transmission” can be used interchangeably, and refer to the movement of heat from an area of higher temperature to an area of cooler temperature. It is intended that the movement of heat include any mechanism of heat transmission known to one skilled in the art, such as, without limitation, conductive, convective, radiative, etc. As used herein, the term “emitting” refers to the process of moving heat or light from a solid material into the air. As used herein, “light-emitting surface” refers to a surface of a device or object from which light is intentionally emitted. Light may include visible light and light within the ultraviolet spectrum. An example of a light-emitting surface may include, without limitation, a nitride layer of an LED, or of semiconductor layers to be incorporated into an LED, from which light is emitted. As used herein, “vapor deposited” refers to materials which are formed using vapor deposition techniques. “Vapor deposition” refers to a process of forming or depositing materials on a substrate through the vapor phase. Vapor deposition processes can include any process such as, but not limited to, chemical vapor deposition (CVD) and physical vapor deposition (PVD). A wide variety of variations of each vapor deposition method can be performed by those skilled in the art. Examples of vapor deposition methods include hot filament CVD, rf-CVD, laser CVD (LCVD), laser ablation, conformal diamond coating processes, metal-organic CVD (MOCVD), sputtering, thermal evaporation PVD, ionized metal PVD (IMPVD), electron beam PVD (EBPVD), reactive PVD, and the like. As used herein, “chemical vapor deposition,” or “CVD” refers to any method of chemically forming or depositing diamond particles in a vapor form upon a surface. Various CVD techniques are well known in the art. As used herein, “physical vapor deposition,” or “PVD” refers to any method of physically forming or depositing diamond particles in a vapor form upon a surface. Various PVD techniques are well known in the art. As used herein, “diamond” refers to a crystalline structure of carbon atoms bonded to other carbon atoms in a lattice of tetrahedral coordination known as sp3 bonding. Specifically, each carbon atom is surrounded by and bonded to four other carbon atoms, each located on the tip of a regular tetrahedron. Further, the bond length between any two carbon atoms is 1.54 angstroms at ambient temperature conditions, and the angle between any two bonds is 109 degrees, 28 minutes, and 16 seconds although experimental results may vary slightly. The structure and nature of diamond, including its physical and electrical properties are well known in the art. As used herein, “distorted tetrahedral coordination” refers to a tetrahedral bonding configuration of carbon atoms that is irregular, or has deviated from the normal tetrahedron configuration of diamond as described above. Such distortion generally results in lengthening of some bonds and shortening of others, as well as the variation of the bond angles between the bonds. Additionally, the distortion of the tetrahedron alters the characteristics and properties of the carbon to effectively lie between the characteristics of carbon bonded in sp3 configuration (i.e. diamond) and carbon bonded in sp2 configuration (i.e. graphite). One example of material having carbon atoms bonded in distorted tetrahedral bonding is amorphous diamond. As used herein, “diamond-like carbon” refers to a carbonaceous material having carbon atoms as the majority element, with a substantial amount of such carbon atoms bonded in distorted tetrahedral coordination. Diamond-like carbon (DLC) can typically be formed by PVD processes, although CVD or other processes could be used such as vapor deposition processes. Notably, a variety of other elements can be included in the DLC material as either impurities, or as dopants, including without limitation, hydrogen, sulfur, phosphorous, boron, nitrogen, silicon, tungsten, etc. As used herein, “amorphous diamond” refers to a type of diamond-like carbon having carbon atoms as the majority element, with a substantial amount of such carbon atoms bonded in distorted tetrahedral coordination. In one aspect, the amount of carbon in the amorphous diamond can be at least about 90%, with at least about 20% of such carbon being bonded in distorted tetrahedral coordination. Amorphous diamond also has a higher atomic density than that of diamond (176 atoms/cm3). Further, amorphous diamond and diamond materials contract upon melting. As used herein, “adynamic” refers to a type of layer which is unable to independently retain its shape and/or strength. For example, in the absence of a mold or support layer, an adynamic diamond layer will tend to curl or otherwise deform when the mold or support surface is removed. While a number of reasons may contribute to the adynamic properties of a layer, in one aspect, the reason may be the extreme thinness of the layer. As used herein, “growth side,” and “grown surface” may be used interchangeably and refer to the surface of a film or layer which is grows during a CVD process. As used herein, “substrate” refers to a support surface to which various materials can be joined in forming a semiconductor or semiconductor-on-diamond device. The substrate may be any shape, thickness, or material, required in order to achieve a specific result, and includes but is not limited to metals, alloys, ceramics, and mixtures thereof. Further, in some aspects, the substrate may be an existing semiconductor device or wafer, or may be a material which is capable of being joined to a suitable device. As used herein, the term “substantially” refers to the complete or nearly complete extent or degree of an action, characteristic, property, state, structure, item, or result. For example, an object that is “substantially” enclosed would mean that the object is either completely enclosed or nearly completely enclosed. The exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, generally speaking the nearness of completion will be so as to have the same overall result as if absolute and total completion were obtained. The use of “substantially” is equally applicable when used in a negative connotation to refer to the complete or near complete lack of an action, characteristic, property, state, structure, item, or result. For example, a composition that is “substantially free of” particles would either completely lack particles, or so nearly completely lack particles that the effect would be the same as if it completely lacked particles. In other words, a composition that is “substantially free of” an ingredient or element may still actually contain such item as long as there is no measurable effect thereof. As used herein, the term “about” is used to provide flexibility to a numerical range endpoint by providing that a given value may be “a little above” or “a little below” the endpoint. As used herein, a plurality of items, structural elements, compositional elements, and/or materials may be presented in a common list for convenience. However, these lists should be construed as though each member of the list is individually identified as a separate and unique member. Thus, no individual member of such list should be construed as a de facto equivalent of any other member of the same list solely based on their presentation in a common group without indications to the contrary. Concentrations, amounts, and other numerical data may be expressed or presented herein in a range format. It is to be understood that such a range format is used merely for convenience and brevity and thus should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. As an illustration, a numerical range of “about 1 to about 5” should be interpreted to include not only the explicitly recited values of about 1 to about 5, but also include individual values and sub-ranges within the indicated range. Thus, included in this numerical range are individual values such as 2, 3, and 4 and sub-ranges such as from 1-3, from 2-4, and from 3-5, etc., as well as 1, 2, 3, 4, and 5, individually. This same principle applies to ranges reciting only one numerical value as a minimum or a maximum. Furthermore, such an interpretation should apply regardless of the breadth of the range or the characteristics being described. The Invention The present invention provides semiconductor devices having incorporated diamond layers and methods of making such devices. Semiconductor devices are often challenging to cool, particularly those that emit light. It should be noted that, even though much of the following description is devoted to light emitting devices such as LEDs, the scope of the claims of the present invention should not be limited thereby and that such teachings are equally applicable to other types of semiconductor devices. Much of the heat generated by semiconductor devices tends to build up within the semiconducting layers, thus affecting the efficiency of the device. For example, an LED may consist of a plurality of nitride layers arranged to emit light from a light-emitting surface. As they have become increasingly important in electronics and lighting devices, LEDs continue to be developed that have ever increasing power requirements. This trend of increasing power has created cooling problems for such devices. These cooling problems can be exacerbated by the typically small size of these devices, which may render heat sinks with traditional aluminum heat fins ineffective due to their bulky nature. Additionally, such traditional heat sinks block the emission of light if applied to the light-emitting surface of the LED. Because heat sinks cannot interfere with the function of the nitride layers or the light-emitting surface, they are often located at the junction between the LED and a supporting structure such as a circuit board. Such a heat sink location is relatively remote from the accumulation of much of the heat, namely, the light-emitting surface and the nitride layers. It has been discovered that forming a diamond layer within the LED package allows adequate cooling even at high power, while at the same time maintaining a small LED package size. Additionally, in one aspect the maximum operating wattage of an LED may be exceeded by drawing heat from the semiconductor layers of the LED with a diamond layer in order to operate the LED at an operating wattage that is higher than the maximum operating wattage for that LED. Additionally, in both semiconductor devices that emit light and those that don't, heat may be trapped within the semiconducting layers due to the relatively poor thermal conductivity of materials that often make up these layers. Additionally, crystal lattice mismatches between semiconductive layers slow the conduction of heat, thus facilitating further heat buildup. Semiconductor devices have now been developed incorporating layers of diamond that provide, among other things, improved cooling properties to the device. Such layers of diamond increase the flow of heat laterally through the semiconductor device to thus reduce the amount of heat trapped within the semiconductor layers. This lateral heat transmission may thus effectively improve the thermal properties of many semiconductor devices. Furthermore, devices according to aspects of the present invention have increased lattice matching, thus further improving their thermal cooling properties. Additionally, it should be noted that the beneficial properties provided by diamond layers may extend beyond cooling, and as such, the present scope should not be limited thereto. More effective cooling can be achieved within a semiconductor device if diamond layers can be incorporated close to the semiconducting layers. One barrier to integration concerns the high dielectric properties of diamond materials, particularly those that have substantially single crystal lattice configurations. Optimum cooling conditions may be achieved if the diamond layer is within the conductive pathway of the semiconductor device, however such configurations have been difficult to achieve due to the dielectric properties of diamond. It has now been discovered that a conductive diamond layer can function as an electrode and be coupled to semiconductor layers and thus be within the conductive pathway of the device. Additionally, by utilizing a conductive diamond layer as an electrode, LED devices can be constructed having a linear conductive pathway through the semiconductive layers between the electrodes. Many prior LED devices were constructed such that the conductive pathway from the n-type electrode was at a right angle to the conductive pathway from the p-type electrode. Such an “L” shaped conductive pathway caused electrons and holes to be oriented at right angles to one another, thus reducing the efficiency of the device. The linear conductive pathway according to aspects of the present invention causes electrons and holes to be oriented along the same linear pathway, thus improving the efficiency of the LED device. Furthermore, it has been discovered that locating heat-generating semiconductor layers between layers of diamond materials in a “sandwich-like” configuration greatly improves the thermal cooling of semiconductor devices, particularly high power LEDs. It may be beneficial to utilize at least one of the diamond layers as a conductive diamond layer in some aspects, and as such, a high level of epitaxial lattice matching between the conductive diamond layer and an associated semiconductor layer is preferred. Although there may be thermal cooling benefits to lattice matching all associated diamond layers, diamond layers that are nonconductive do not necessarily require such matching. Accordingly, in one aspect of the present invention, an LED device is provided. As is shown in FIG. 1, such a device may include a diamond substrate 12, a transparent diamond layer 14 positioned parallel to the diamond substrate 12, and a plurality of semiconductor layers 16 coupled between the transparent diamond layer 14 and the diamond substrate 12. Light generated by the semiconductor layers 16 is emitted 15 through the transparent diamond layer 14. A reflective layer 13 may be applied to the diamond substrate 12 to reflect light that is emitted toward the diamond substrate 12 back through the semiconductor layers 16 and the transparent diamond layer 14 to thus improve the efficiency of the LED device. Such a reflective layer may be formed from a variety of reflective materials that are known to those of ordinary skill in the art. One example of such a reflective material would be a layer of chromium metal or other reflective metal. In another aspect, as is shown in FIG. 2, a SiC layer 18 may be coupled to the transparent diamond layer 14 in order to improve the lattice matching between the transparent diamond layer 14 and the semiconductor layers 16. In some aspects the transparent diamond layer may also be conductive, thus functioning as an electrode for the semiconductor device. In such cases, an electrode of opposite polarity may be coupled to the semiconductor layers opposite the transparent conductive diamond layer (not shown). FIG. 3 shows selected steps of a method constructing a semiconductor substrate that may be used to form an LED device according to particular aspects of the present invention. A single crystal Si growth substrate 34 is provided upon which other materials are formed. Although it is not required that the Si growth substrate be single crystal, such a single crystal lattice configuration may facilitate deposition of additional materials with fewer lattice mismatches as compared to a non-single crystal substrate. It may be beneficial to thoroughly clean the Si growth substrate to remove any non-crystalline Si or non-Si particles from the wafer prior to deposition that may affect the lattice mismatch between the Si growth substrate and the layers formed thereon. Any method of cleaning the Si growth substrate would be considered to be within the present scope, however, in one aspect the substrate can be soaked in KOH and ultrasonically cleaned with distilled water. Following cleaning of the Si growth substrate 34, an epitaxial layer of single crystal SiC 32 and an epitaxial transparent diamond layer 36 may be formed thereon, such that the single crystal SiC layer 32 is located between the Si growth substrate 34 and the transparent diamond layer 36. The SiC layer may be formed separately from the diamond layer, or it may be formed as a result of, or in conjunction with, the deposition of the diamond layer. For example, the SiC layer may be formed as a result of a gradation process from Si to diamond, as is described below. Additionally, the SiC layer may be created in vivo by the deposition of an amorphous diamond layer onto the Si growth substrate, as is also described below. Subsequently, a Si layer 38 may be deposited on the transparent diamond layer 36. The Si layer 38 improves the bonding of the Si carrier substrate 42 to the transparent diamond layer 36. The Si carrier substrate 42 has a SiO2 layer for bonding to the Si layer 38. Following the wafer bonding of the Si carrier substrate 42 to the Si layer 38, the Si growth substrate 34 may be removed to expose the SiC layer 32. As has been described, the SiC layer 32 may be used as a growth surface for the deposition of semiconductor materials (not shown). In one aspect, following formation of the LED layers on the SiC layer 32, the Si carrier substrate 42 and the Si layer 38 may be removed to expose the transparent diamond layer 36. The diamond substrate may be coupled to the semiconductor layers as has been described (not shown). Diamond materials have excellent thermal conductivity properties that make them ideal for incorporation into semiconductor devices, such as LEDs. The transfer of heat that is present in the semiconductor device can thus be accelerated from the device through a diamond material. It should be noted that the present invention is not limited as to specific theories of heat transmission. As such, in one aspect the accelerated movement of heat from inside the device can be at least partially due to heat movement into and through a diamond layer. Due to the heat conductive properties of diamond, heat can rapidly spread laterally through the diamond layer and to the edges of a semiconductor device. Heat present around the edges will be more rapidly dissipated into the air or into surrounding structures, such as heat spreaders or device supports. Additionally, diamond layers having a major portion of surface area exposed to air will more rapidly dissipate heat from a device in which such a layer is incorporated. Because the thermal conductivity of diamond is greater than the thermal conductivity of a semiconductor layer or other structure to which it is thermally coupled, a heat sink is established by the diamond layer. As such, heat that builds up in the semiconductor layer is drawn into the diamond layer and spread laterally to be discharged from the device. Such accelerated heat transfer may result in semiconductor devices with much cooler operational temperatures. Additionally, the acceleration of heat transfer not only cools a semiconductor device, but may also reduce the heat load on many electronic components that are spatially located nearby the semiconductor device. In some aspects of the present invention, a portion of a diamond layer may be exposed to the air. Such exposure may be limited to the edges of the layer in some cases, or it may be a larger proportion of surface area, such as would be the case for a diamond layer having one side exposed. In such aspects, the accelerated movement of heat away from a semiconductor layer may be at least partially due to heat movement from the diamond layer to air. For example, a diamond material such as diamond-like carbon (DLC) has exceptional heat emissivity characteristics even at temperatures below 100° C., and as such, may effectively radiate heat directly to the air. Many semiconductor materials that comprise a device conduct heat much better than they emit heat. As such, heat can be conducted through a semiconductor material to a DLC layer, spread laterally through the DLC layer, and subsequently emitted to the air along the edges or other exposed surfaces. Due to the high heat conductive and radiative properties of DLC, heat movement from the DLC layer to air can be greater than heat movement from the semiconductor layer to air. Also, heat movement from the semiconductor device to the DLC layer can be greater than heat movement from the semiconductor device to the air. As such, the layer of DLC can serve to accelerate heat transfer away from the semiconductor layer more rapidly than heat can be transferred through the semiconductor device itself, or from the semiconductor device to the air. As has been suggested, various diamond materials may be utilized to provide accelerated heat transferring properties to a semiconductor device. Non-limiting examples of such diamond materials may include diamond, DLC, amorphous diamond, and combinations thereof. It should be noted, however, that any form of natural or synthetic diamond material that may be utilized to cool a semiconductor device is considered to be within the present scope. It should be understood that the following is a very general discussion of diamond deposition techniques that may or may not apply to a particular diamond layer or application, and that such techniques may vary widely between the various aspects of the present invention. Generally, diamond layers may be formed by any means known, including various vapor deposition techniques. Any number of known vapor deposition techniques may be used to form these diamond layers. The most common vapor deposition techniques include chemical vapor deposition (CVD) and physical vapor deposition (PVD), although any similar method can be used if similar properties and results are obtained. In one aspect, CVD techniques such as hot filament, microwave plasma, oxyacetylene flame, rf-CVD, laser CVD (LCVD), metal-organic CVD (MOCVD), laser ablation, conformal diamond coating processes, and direct current arc techniques may be utilized. Typical CVD techniques use gas reactants to deposit the diamond or diamond-like material in a layer, or film. These gases generally include a small amount (i.e. less than about 5%) of a carbonaceous material, such as methane, diluted in hydrogen. A variety of specific CVD processes, including equipment and conditions, as well as those used for boron nitride layers, are well known to those skilled in the art. In another aspect, PVD techniques such as sputtering, cathodic arc, and thermal evaporation may be utilized. Further, specific deposition conditions may be used in order to adjust the exact type of material to be formed, whether DLC, amorphous diamond, or pure diamond. It should also be noted that many semiconductor devices such as LEDs may be degraded by high temperature. Care may need to be taken to avoid damage during diamond deposition by forming at lower temperatures. For example, if the semiconductor contains InN, deposition temperatures of up to about 600° C. may be used. In the case of GaN, layers may be thermally stable up to about 1000° C. Additionally, preformed layers can be brazed, glued, or otherwise affixed to the semiconductor layer or to a support substrate of the semiconductor device using methods which do not unduly interfere with the heat transference of the diamond layer or the functionality of the device. An optional nucleation enhancing layer can be formed on the growth surface of a substrate in order to improve the quality and deposition time of a diamond layer. Specifically, a diamond layer can be formed by depositing applicable nuclei, such as diamond nuclei, on a diamond growth surface of a substrate and then growing the nuclei into a film or layer using a vapor deposition technique. In one aspect of the present invention, a thin nucleation enhancer layer can be coated upon the substrate to enhance the growth of the diamond layer. Diamond nuclei are then placed upon the nucleation enhancer layer, and the growth of the diamond layer proceeds via CVD. A variety of suitable materials will be recognized by those in skilled in the art which can serve as a nucleation enhancer. In one aspect of the present invention, the nucleation enhancer may be a material selected from the group consisting of metals, metal alloys, metal compounds, carbides, carbide formers, and mixtures thereof. Examples of carbide forming materials may include, without limitation, tungsten (W), tantalum (Ta), titanium (Ti), zirconium (Zr), chromium (Cr), molybdenum (Mo), silicon (Si), and manganese (Mn). Additionally, examples of carbides include tungsten carbide (WC), silicon carbide (SiC), titanium carbide (TiC), zirconium carbide (ZrC), and mixtures thereof among others. The nucleation enhancer layer, when used, is a layer which is thin enough that it does not to adversely affect the thermal transmission properties of the diamond layer. In one aspect, the thickness of the nucleation enhancer layer may be less than about 0.1 micrometers. In another aspect, the thickness may be less than about 10 nanometers. In yet another aspect, the thickness of the nucleation enhancer layer is less than about 5 nanometers. In a further aspect of the invention, the thickness of the nucleation enhancer layer is less than about 3 nanometers. Various methods may be employed to increase the quality of the diamond in the nucleation surface of the diamond layer which is created by vapor deposition techniques. For example, diamond particle quality can be increased by reducing the methane flow rate, and increasing the total gas pressure during the early phase of diamond deposition. Such measures, decrease the decomposition rate of carbon, and increase the concentration of hydrogen atoms. Thus a significantly higher percentage of the carbon will be deposited in a sp3 bonding configuration, and the quality of the diamond nuclei formed is increased. Additionally, the nucleation rate of diamond particles deposited on the growth surface of the substrate or the nucleation enhancer layer may be increased in order to reduce the amount of interstitial space between diamond particles. Examples of ways to increase nucleation rates include, but are not limited to; applying a negative bias in an appropriate amount, often about 100 volts, to the growth surface; polishing the growth surface with a fine diamond paste or powder, which may partially remain on the growth surface; and controlling the composition of the growth surface such as by ion implantation of C, Si, Cr, Mn, Ti, V, Zr, W, Mo, Ta, and the like by PVD or PECVD. PVD processes are typically at lower temperatures than CVD processes and in some cases can be below about 200° C. such as about 150° C. Other methods of increasing diamond nucleation will be readily apparent to those skilled in the art. In one aspect of the present invention, the diamond layer may be formed as a conformal diamond layer. Conformal diamond coating processes can provide a number of advantages over conventional diamond film processes. Conformal diamond coating can be performed on a wide variety of substrates, including non-planar substrates. A growth surface can be pretreated under diamond growth conditions in the absence of a bias to form a carbon film. The diamond growth conditions can be conditions that are conventional CVD deposition conditions for diamond without an applied bias. As a result, a thin carbon film can be formed which is typically less than about 100 angstroms. The pretreatment step can be performed at almost any growth temperature such as from about 200° C. to about 900° C., although lower temperatures below about 500° C. may be preferred. Without being bound to any particular theory, the thin carbon film appears to form within a short time, e.g., less than one hour, and is a hydrogen terminated amorphous carbon. Following formation of the thin carbon film, the growth surface may then be subjected to diamond growth conditions to form a conformal diamond layer. The diamond growth conditions may be those conditions which are commonly used in traditional CVD diamond growth. However, unlike conventional diamond film growth, the diamond film produced using the above pretreatment steps results in a conformal diamond film that typically begins growth substantially over the entire growth surface with substantially no incubation time. In addition, a continuous film, e.g. substantially no grain boundaries, can develop within about 80 nm of growth. Diamond layers having substantially no grain boundaries may move heat more efficiently than those layers having grain boundaries. Various techniques may be employed to render a diamond layer conductive. Such techniques are known to those of ordinary skill in the art. For example, various impurities may be doped into the crystal lattice of the diamond layer. Such impurities may include elements such as Si, B, P, N, Li, Al, Ga, etc. In one specific aspect, for example, the diamond layer may be doped with B. Impurities may also include metallic particles within the crystal lattice, provided they do not interfere with the function of the device, such as by blocking light emitted from an LED. For some diamond layers, particularly those on which semiconductor layers are to be formed, it may be beneficial to create a growth substrate upon which the semiconductor material can be formed with minimal crystal lattice dislocations as a substantially single crystal. Additionally, diamond layers having low crystal lattice dislocations tend to be transparent to light. Minimizing crystal lattice dislocations may be facilitated by utilizing a growth substrate that is substantially a single crystal and has properties such that strong bonding interactions with the semiconductor material may be achieved. In one aspect, such a substrate includes a substantially single crystal diamond layer having a substantially single crystal SiC layer epitaxially coupled thereto. The substantially single crystal nature of the SiC layer facilitates the deposition of a semiconductor such as GaN or AlN as a substantially single crystal. Additionally, the epitaxial relationship from the diamond layer through the SiC layer and to the semiconductor layer increases thermal conduction to the diamond layer, thus improving the cooling properties of the device. Various methods are possible for building such a diamond/SiC composite substrate. Any such method would be considered to be within the scope of the present invention. For example, in one aspect such a substrate may be created by grading a single crystal Si wafer into a single crystal diamond layer. In other words, the Si wafer would gradually transition from Si to SiC and then to diamond. Techniques for such grading are further discussed in the Applicant's copending U.S. patent application entitled “Graded Crystalline Materials And Associated Methods”, and filed on May 31, 2007 under Attorney Docket No. 00802-32733.NP, which is incorporated herein by reference. In addition to the above described benefits of minimizing crystal dislocations, substantially single crystal diamond layers are substantially transparent to light and are thus useful in constructing light-emitting semiconductor devices such as LEDs and laser diodes. The resulting structure includes a substantially single crystal diamond layer having a substantially single crystal SiC layer epitaxially coupled thereto. Semiconductor layers may be epitaxially formed on the SiC layer by any method know to one of ordinary skill in the art. In one aspect such deposition may occur in a graded manner similar to the techniques used in forming the diamond layer on the Si wafer. Following formation of the semiconductor layers, a diamond support may be coupled thereto. Numerous methods of coupling are known to one of ordinary skill in the art, such as brazing, gluing, annealing, etc. It should be noted that any coupling method may be used, provided the functionality of the diamond support is not substantially affected. In one specific aspect, a reflective layer of a carbide forming metal may be applied to a surface of a semiconductor layer. One example of such a metal is titanium. The diamond support may then be formed on the titanium reflective layer and thus coupled to the semiconductive layer by titanium carbide bonds forming between the reflective layer and the diamond substrate. The diamond layers according to aspects of the present invention may be of any thickness that would allow thermal cooling of a semiconductor device. Thicknesses may vary depending on the application and the semiconductor device configuration. For example, greater cooling requirements may require thicker diamond layers. The thickness may also vary depending on the material used in the diamond layer. That being said, in one aspect a diamond layer may be from about 10 to about 50 microns thick. In another example, a diamond layer may be less than or equal to about 10 microns thick. In yet another example, a diamond layer may be from about 50 microns to about 100 microns thick. In a further example, a diamond layer may be greater than about 50 microns thick. In yet a further example, a diamond layer may be an adynamic diamond layer. SiC layers according to aspects of the present invention may have a variety of thicknesses, depending on the method of deposition of the SiC layer and the intended uses of the device. In some aspects the SiC layer may be merely thick enough to orient the crystal lattice of the layers being formed thereon. In other aspects, thicker SiC layers may be beneficial. With such variation in mind, in one aspect the SiC layer may be less than or equal to about 1 micron thick. In another aspect, the SiC layer may be less than or equal to about 500 nanometers thick. In yet another aspect, the SiC layer may be less than or equal to about 1 nanometer thick. In a further aspect, the SiC layer may be greater than about 1 micron thick. As has been described, the semiconductor devices according to aspects of the present invention include a plurality of semiconductor layers associated with one or more diamond layers. These semiconductor layers may be associated with a diamond layer by a variety of methods known to one of ordinary skill in the art. In one aspect of the present invention, however, one or more semiconductor layers may be formed on a diamond layer, or as is described above, on a SiC layer coupled to a diamond layer. A semiconductor layer may be formed on a substrate such as a SiC layer using a variety of techniques known to those of ordinary skill in the art. One example of such a technique is a MOCVD process. The semiconductor layer may include any material that is suitable for forming electronic devices, semiconductor devices, or the like. Many semiconductors are based on silicon, gallium, indium, and germanium. However, suitable materials for the semiconductor layer can include, without limitation, silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, germanium, zinc sulfide, gallium phosphide, gallium antimonide, gallium indium arsenide phosphide, aluminum phosphide, aluminum arsenide, aluminum gallium arsenide, gallium nitride, boron nitride, aluminum nitride, indium arsenide, indium phosphide, indium antimonide, indium nitride, and composites thereof. In one aspect, however, the semiconductor layer can include silicon, silicon carbide, gallium arsenide, gallium nitride, gallium phosphide, aluminum nitride, indium nitride, indium gallium nitride, aluminum gallium nitride, or composites of these materials. In some additional embodiments, non-silicon based devices can be formed such as those based on gallium arsenide, gallium nitride, germanium, boron nitride, aluminum nitride, indium-based materials, and composites thereof. In another embodiment, the semiconductor layer can comprise gallium nitride, indium gallium nitride, indium nitride, and combinations thereof. In one specific aspect, the semiconductor material is gallium nitride. In another specific aspect, the semiconductor material is aluminum nitride. Other semiconductor materials which can be used include Al2O3, BeO, W, Mo, c-Y2O3, c-(Y0.9La0.1)2O3, c-Al23O27N5, c-MgAl2O4, t-MgF2, graphite, and mixtures thereof. It should be understood that the semiconductor layer may include any semiconductor material known, and should not be limited to those materials described herein. Additionally, semiconductor materials may be of any structural configuration known, for example, without limitation, cubic (zincblende or sphalerite), wurtzitic, rhombohedral, graphitic, turbostratic, pyrolytic, hexagonal, amorphous, or combinations thereof. As has been described, the semiconductor layer 14 may be formed by any method known to one of ordinary skill in the art. Various known methods of vapor deposition can be utilized to deposit such layers and that allow deposition to occur in a graded manner. Additionally, surface processing may be performed between any of the deposition steps described in order to provide a smooth surface for subsequent deposition. Such processing may be accomplished by any means known, such as by chemical etching, polishing, buffing, grinding, etc. In one aspect of the present invention, at least one of the semiconductor layers may be gallium nitride (GaN). GaN semiconductor layers may be useful in constructing LEDs and other semiconductor devices. In some cases it may be beneficial to gradually transition between the SiC or other substrate and the semiconductor layer. For example, gradually transitioning an indium nitride (InN) semiconductor substrate into a GaN semiconductor layer may occur by fixing the concentration of the N being vapor deposited and varying the deposited concentration of Ga and of In such that a ratio of Ga:In gradually transitions from about 0:1 to about 1:0. In other words, the sources of Ga and In are varied such that as the In concentration is decreased, the Ga concentration is increased. The gradual transition functions to greatly reduce the lattice mismatch observed when forming GaN directly on InN. In another aspect, at least one of the semiconductor layers may be a layer of aluminum nitride (AlN). The AlN layer may be deposited onto a substrate by any means known to one of ordinary skill in the art. As with the GaN layer described above, gradually transitioning between semiconductor layers may improve the functionality of the semiconductor device. For example, in one aspect AlN may be deposited onto a semiconductor substrate of InN by gradually transitioning the layer of InN into the layer of AlN. Such a gradual transition may include, for example, gradually transitioning the layer of InN into the layer of AlN by fixing the concentration of N being deposited and varying the deposited concentration of In and of Al such that a ratio of In:Al gradually transitions from about 0:1 to about 1:0. Such a gradual transition may greatly reduce the lattice mismatch observed when forming AlN on InN directly. Surface processing may be performed between any of the deposition steps described in order to provide a smooth surface for subsequent deposition. Such processing may be accomplished by any means known, such as by chemical etching, polishing, buffing, grinding, etc. As has been described, electrodes may be incorporated into an LED device as an electrical contact for the semiconductive layers. Various electrodes, particularly p-type and n-type electrodes, including their use and formation, are well known to those of ordinary skill in the art, and will not be discussed in detail herein. In one specific aspect of the present invention as shown in FIG. 4, a “flip-chip” design for an LED device is described. A semiconductor substrate 42 is made as described above and as shown in FIG. 3. An n-type semiconductive material 44 such as n-Gan is formed on the semiconductor substrate 42, followed by the formation of MQW layers 46, and a p-type semiconductor material 48 such as p-GaN. The n-type semiconductive material 44 is electrically coupled to an n-type electrode 50, and the p-type semiconductive material 48 is electrically coupled to a p-type electrode 52. A reflective layer 54 and associated diamond substrate 56 may then be flip-chip bonded to the n-type electrode 50 and the p-type electrode 52. If the reflective layer 54 is conductive it may require division into two electrically isolated portions to facilitate functionality of the device (not shown). As is shown in FIG. 5, in order to emit light the nontransparent layers of the semiconductor substrate need to be removed to expose the transparent diamond layer 58. Upon activation of the LED device, light is generated by the semiconductor layers and emitted 62 through the SiC layer 60 and the transparent diamond layer 58. Additionally, light that is transmitted toward the diamond substrate 56 is reflected by the reflective layer 54 and transmitted back through the semiconductor layers to be emitted through the transparent diamond layer 58. EXAMPLES The following examples illustrate various techniques of making a semiconductor device such as an LED according to aspects of the present invention. However, it is to be understood that the following are only exemplary or illustrative of the application of the principles of the present invention. Numerous modifications and alternative compositions, methods, and systems can be devised by those skilled in the art without departing from the spirit and scope of the present invention. The appended claims are intended to cover such modifications and arrangements. Thus, while the present invention has been described above with particularity, the following Examples provide further detail in connection with several specific embodiments of the invention. Example 1 A semiconductor substrate may be formed as follows: A single crystal Si wafer is obtained and cleaned by soaking in KOH and ultrasound cleaning with distilled water to remove any non-crystalline Si and foreign debris. A conformal amorphous carbon coating is applied to the cleaned surface of the Si wafer by exposing the wafer to CVD deposition conditions without an applied bias. Following carbonization of the surface, amorphous diamond is deposited for approximately 30 minutes at 800° in 1% CH4 and 99% H2. The amorphous carbon coating is then removed with H2 or F2 treatment for about 60 minutes, at 900°. Removal of the amorphous carbon coating exposes an epitaxial SiC layer that has formed in situ between the Si wafer and the amorphous carbon coating. The thickness of the SiC layer is approximately 10 nm. A transparent diamond coating 10 microns thick is then deposited onto the SiC layer by CVD deposition of CH4 for approximately 10 hours. After 10 hours, the CH4 source is then switched to SiH4 for approximately 10 minutes to deposit a 1 micron thick Si layer. A Si carrier substrate having a SiO2 surface is wafer bonded to the 1 micron thick Si layer at the SiO2 surface. Following wafer bonding, the single crystal Si wafer is removed to expose the SiC layer by etching with HF+3HNO2+H2O. Further details regarding etching Si materials may be found in U.S. Pat. No. 4,981,818, which is incorporated herein by reference. Example 2 An LED device may be constructed as follows: A semiconductor substrate is obtained as in Example 1. GaN semiconductor layers are deposited onto the exposed SiC layer by MOCVD with GaH3 and NH3 source materials. Of course, it is to be understood that the above-described arrangements are only illustrative of the application of the principles of the present invention. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of the present invention and the appended claims are intended to cover such modifications and arrangements. Thus, while the present invention has been described above with particularity and detail in connection with what is presently deemed to be the most practical and preferred embodiments of the invention, it will be apparent to those of ordinary skill in the art that numerous modifications, including, but not limited to, variations in size, materials, shape, form, function and manner of operation, assembly and use may be made without departing from the principles and concepts set forth herein.	H	67H01	185H01L	3103	12
10534956	US20070273013A1-20071129	Packaging for Micro Electro-Mechanical Systems and Methods of Fabricating Thereof	ACCEPTED	20071114	20071129	[]	H01L2320	["H01L2320", "H01L2154"]	8476096	20070427	20130702	438	050000	58033.0	GEBREYESUS	YOSEF	[{"inventor_name_last": "Kohl", "inventor_name_first": "Paul", "inventor_city": "Atlanta", "inventor_state": "GA", "inventor_country": "US"}, {"inventor_name_last": "Ayazi", "inventor_name_first": "Farrokh", "inventor_city": "Atlanta", "inventor_state": "GA", "inventor_country": "US"}]	Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Other systems and methods are also provided.	1. A micro electro-mechanical device packaging system, comprising: a micro electro-mechanical device formed on a substrate layer; and a protective structure protecting at least a portion of the micro electro-mechanical device, wherein the protective structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device, the protective structure being a solid. 2. The system of claim 1, wherein the substrate layer comprises silicon material. 3. The system of claim 1, wherein the substrate layer comprises non-silicon material. 4. The system of claim 1, wherein the protective structure comprises a metal material. 5. The system of claim 4, wherein the metal material is deposited by sputtering. 6. The system of claim 1, wherein the protective structure comprises an overcoat polymer material. 7. The system of claim 6, wherein the overcoat polymer material is deposited by spin-coating. 8. The system of claim 6, further comprising: an additional protective structure surrounding the overcoat polymer material. 9. The system of claim 8, wherein the additional protective structure comprises a metal material. 10. The system of claim 1, wherein the protective structure comprises a modular polymer that includes the characteristic of being permeable to the decomposition gases produced by the decomposition of a sacrificial polymer while forming the gas cavity. 11. The system of claim 1, wherein the gas cavity is substantially free of residue. 12. The system of claim 11, wherein the gas cavity is vacuum-packed. 13. The system of claim 1, wherein protective structure has not been preformed before being applied to the substrate layer. 14. The system of claim 13, further comprising: a metal packaging frame, the micro electro-mechanical device being attached to the metal packaging frame; and a coating material encapsulating a portion of the micro electro-mechanical device and metal packaging frame assembly. 15. A micro electro-mechanical device packaging system, comprising: a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, wherein the sacrificial structure is formed into a gas cavity enclosing an active surface of the micro electro-mechanical device. 16. The system of claim 15, wherein the sacrificial structure comprises a photo-definable polycarbonate material. 17. The system of claim 15, wherein the sacrificial structure is deposited by spin-coating followed by patterning. 18. The system of claim 17, wherein the sacrificial structure comprises a photo-definable material. 19. The system of claim 15, wherein the sacrificial structure is dispensed by a syringe dispensing tool. 20. The system of claim 19, wherein the sacrificial structure comprises a non-photo-definable material. 21. The system of claim 15, further comprising: a metal packaging frame, the micro electro-mechanical device being attached to the metal packaging frame; and a coating material encapsulating a portion of the micro electro-mechanical device and metal packaging frame assembly, the coating material including the characteristic of being permeable to the decomposition gases produced by the decomposition of a sacrificial polymer at a temperature exceeding a curing temperature of the coating material. 22. The system of claim 21, wherein the coating material comprises an epoxy resin. 23. The system of claim 21, further comprising: an overcoat structure surrounding the sacrificial structure, the overcoat structure comprising a modular polymer that includes the characteristic of being permeable to the decomposition gases produced by the decomposition of a sacrificial polymer from inside the gas cavity. 24. A method for producing a micro electro-mechanical device package, comprising the steps of: forming a thermally decomposable sacrificial layer on a substrate of a micro electro-mechanical device, the sacrificial layer encapsulating a portion of the micro electro-mechanical device; forming a protective layer around the sacrificial layer; and thermally decomposing the sacrificial layer, wherein decomposed molecules of the sacrificial layer permeate through the protective layer, and wherein a gas cavity is formed where the thermally decomposable sacrificial layer was formed. 25. The method of claim 24, further comprising the steps of: depositing the sacrificial layer by spin-coating; and patterning the sacrificial layer. 26. The method of claim. 24, wherein the sacrificial layer has a decomposition temperature less than a decomposition temperature of the substrate and a decomposition temperature of the protective layer. 27. The method of claim 24, wherein the substrate comprises a silicon material. 28. The method of claim. 24, wherein the substrate comprises a non-silicon material. 29. The method of claim 24, wherein the thickness of the protective layer is within the range of 50 nm and 500 μm. 30. The method of claim 24, wherein the protective layer has not been perforated. 31. The method of claim 24, wherein the protective layer is substantially free of sacrificial material after the sacrificial material has been thermally decomposed. 32. The method of claim 24, wherein the protective layer provides an airtight enclosure around the gas cavity. 33. The method of claim 32, wherein the protective layer provides protection from mechanical forces. 34. The method of claim 33, wherein the protective layer further provides protection against water. 35. The method of claim 34, wherein the protective layer further provides protection against oxygen gas. 36. The method of claim 34, wherein the protective layer further provides protection against exposure to gaseous materials. 37. The method of claim 24, wherein the micro electro-mechanical device includes a released mechanical structure before the sacrificial material is formed. 38. The method of claim 24, further comprising the steps of: before the protective layer is formed, attaching the micro electro-mechanical device to a metal packaging frame, wherein the protective layer comprises an epoxy resin encapsulating the micro electro-mechanical device and metal packaging frame assembly. 39. The method of claim 38, further comprising the step of: heating the micro assembly at a temperature for curing the protective layer; and heating the micro assembly at a temperature for decomposing the sacrificial layer, the temperature for decomposing the sacrificial layer exceeding the temperature for curing the protective layer. 40. The method of claim 24, further comprising the step of: forming a barrier layer around the protective layer, the barrier layer providing a stronger protection against mechanical forces than the protective layer. 41. The method of claim 40, wherein the barrier layer comprises a metal material. 42. The method of claim 40, further comprising the steps of: creating a vacuum inside the gas cavity by heating the micro electro-mechanical device in a chamber; and after the vacuum is created, forming a barrier layer around the protective layer within the chamber to provide a vacuum-packed enclosure around the gas cavity, the barrier layer comprising a metal material. 43. The method of claim 42, further comprising the steps of: after the barrier layer is formed, attaching the micro electro-mechanical device to an integrated circuit package structure; and encapsulating the electro-mechanical device and integrated circuit package structure in a protective coating. 44. The method of claim 42, wherein the integrated circuit package structure comprises a leadframe. 45. The method of claim 42, wherein the integrated circuit package structure comprises a ceramic package. 46. The method of claim 42, wherein the step of thermally decomposing the sacrificial layer occurs inside the vacuum chamber. 47. The method of claim 24, further comprising the steps of: after the sacrificial layer is decomposed, attaching the micro electro-mechanical device to an integrated circuit package structure; and encapsulating the electro-mechanical device and package structure in a protective coating. 48. The method of claim 47, wherein the integrated circuit package structure comprises a leadframe. 49. The method of claim 47, wherein the integrated circuit package structure comprises a ceramic package. 50. The method of claim 24, wherein thermal decomposition temperature of the sacrificial material is less than 100 degrees Celsius.	<SOH> BACKGROUND <EOH>Adapting microelectronic packages to micro electro-mechanical system (MEMS) devices involves several challenging packaging requirements. The typical three-dimensional and moving elements of many MEMS devices generally require some sort of cavity package to provide free space above the active surface of the MEMS device. The interior of the cavity must generally be free of contaminants, including excessive outgassing of materials. The MEMS device might also require thermal isolation within the package, and a mounting method that minimizes mechanical stress on the device. The cavity may be evacuated or be filled with atmosphere-controlling agents such as getters. In addition to these requirements, MEMS devices are vulnerable to damage during what would otherwise be normal micropackaging procedures. The presence of three-dimensional mechanical structures that can move adds fragility to unpackaged MEMS devices. For example, movable MEMS structures make contact and permanently stick together (stiction effect) if roughly handled. Further, the cost of MEMS packaging has become a critical issue for many applications. For instance, 50-90% of the cost in producing most MEMS devices is spent in packaging the MEMS devices. For instance, the surface features and cavity requirements of MEMS devices typically prohibit application of low-cost transfer-molded plastic packaging used for most integrated circuits. Moreover, common encapsulation techniques such as injection molding, often requiring high pressures that may easily damage microstructures Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.	<SOH> SUMMARY <EOH>Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Embodiments of the present disclosure can also be viewed as providing methods for producing micro electro-mechanical device packages. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: forming a thermally decomposable sacrificial layer on a substrate of a micro electro-mechanical device, where the sacrificial layer surrounds a gas cavity encapsulating a portion of the micro electro-mechanical device; forming a protective layer around the sacrificial layer; and thermally decomposing the sacrificial layer, where decomposed molecules permeate through the protective layer and a gas cavity is formed where the thermally decomposable sacrificial layer was formed. Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure.	CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to copending U.S. provisional application entitled, “Hermetic Packaging for MEMS,” having Ser. No. 60/553,178, filed Mar. 15, 2004, which is entirely incorporated herein by reference. TECHNICAL FIELD The present disclosure is generally related to micro electro-mechanical devices and, more particularly, is related to packaging of micro electro-mechanical devices. BACKGROUND Adapting microelectronic packages to micro electro-mechanical system (MEMS) devices involves several challenging packaging requirements. The typical three-dimensional and moving elements of many MEMS devices generally require some sort of cavity package to provide free space above the active surface of the MEMS device. The interior of the cavity must generally be free of contaminants, including excessive outgassing of materials. The MEMS device might also require thermal isolation within the package, and a mounting method that minimizes mechanical stress on the device. The cavity may be evacuated or be filled with atmosphere-controlling agents such as getters. In addition to these requirements, MEMS devices are vulnerable to damage during what would otherwise be normal micropackaging procedures. The presence of three-dimensional mechanical structures that can move adds fragility to unpackaged MEMS devices. For example, movable MEMS structures make contact and permanently stick together (stiction effect) if roughly handled. Further, the cost of MEMS packaging has become a critical issue for many applications. For instance, 50-90% of the cost in producing most MEMS devices is spent in packaging the MEMS devices. For instance, the surface features and cavity requirements of MEMS devices typically prohibit application of low-cost transfer-molded plastic packaging used for most integrated circuits. Moreover, common encapsulation techniques such as injection molding, often requiring high pressures that may easily damage microstructures Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies. SUMMARY Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Embodiments of the present disclosure can also be viewed as providing methods for producing micro electro-mechanical device packages. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: forming a thermally decomposable sacrificial layer on a substrate of a micro electro-mechanical device, where the sacrificial layer surrounds a gas cavity encapsulating a portion of the micro electro-mechanical device; forming a protective layer around the sacrificial layer; and thermally decomposing the sacrificial layer, where decomposed molecules permeate through the protective layer and a gas cavity is formed where the thermally decomposable sacrificial layer was formed. Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. FIG. 1 is a diagram of a MEMS package in accordance with one embodiment of the present disclosure. FIG. 2 is a flowchart diagram describing an illustrative process for fabricating the MEMS package of FIG. 1. FIG. 3 is a diagram showing the fabrication steps in the process of FIG. 2. FIG. 4 is a diagram describing one embodiment of a process for performing the step of applying a sacrificial layer as performed in FIG. 2. FIG. 5 is a diagram shown an embodiment of a MEMS device that is suited for the process of FIG. 4. FIG. 6 is a diagram describing one embodiment of a process for performing the step of applying a sacrificial layer as performed in FIG. 2. FIG. 7 is a diagram shown an embodiment of a MEMS device that is suited for the process of FIG. 6. FIG. 8 is diagram. shown an embodiment of a MEMS device that is suited for an etching process for performing the process of applying a sacrificial layer as performed in FIG. 2. FIGS. 9A-9D are pictures illustrating a packaging process of FIG. 4 for a SOI beam resonator. FIGS. 10A-10F are pictures illustrating a packaging process of FIG. 6 for a HARPSS Polysilicon ring gyrcoscope. FIGS. 11A-11B are diagrams showing the frequency response of the SOI beam resonator of FIGS. 9A-9D before and after packaging. FIGS. 12-15 are diagrams showing different embodiments of a MEMS package that may be performed using portions of the process of FIG. 2. FIG. 16 is a diagram describing a fabrication process for attaching a MEMS device to a leadframe package, in accordance with the present disclosure. FIG. 17 is a diagram showing a variety of packaging technologies that can be employed with MEMS packages of the present disclosure. DETAILED DESCRIPTION FIG. 1 shows a MEMS device package 100 in accordance with one embodiment of the present disclosure. Accordingly, the MEMS device package 100 is used to package a freestanding MEMS structure 110 and generally includes a substrate layer 105, one or more MEMS structure(s) 110 formed on the substrate layer 105; a cavity or air gap or gas cavity 108 surrounding the freestanding MEMS structure 110; a barrier layer 120 around the cavity 108 to provide mechanical, electrical, chemical, and/or environmental protection for the MEMS device; a plurality of electrical feedthroughs extending from inside of the cavity to the outside (through or under the barrier layer 120, to guide electrical signals from outside to inside); and contacts 130 formed on the substrate 105 for connecting the package 100 to external points or terminals. After packaging the freestanding or released MEMS structure 110 in a MEMS package 100, the package 100 may then be attached to a circuit board or system in a variety of unique and different approaches, as is discussed hereinafter. Substrate layer 105 can be made of materials appropriate for a particular MEMS system or device. Exemplar materials include, but are not limited to, glasses, diamond, quartz, sapphire, silicon, silicon compounds, germanium, germanium compounds, gallium, gallium compounds, indium, indium compounds, or other semiconductor materials and/or compounds. In addition, substrate layer l 05 can include non-semiconductor substrate materials, including any dielectric materials, metals (e.g., copper and aluminum), or ceramics or organic materials found in printed wiring boards, for example. The contacts 130 are formed from conductors such as metals and/or metal alloys, subject to appropriate considerations such as adhesion and thermal properties. As previously stated, the barrier layer 120 around the cavity 108 provides mechanical, electrical, chemical, and/or environmental protection for the MEMS device(s). Depending on the particular MEMS device or the particular application, different levels of protection may be desired. Generally, the air gap or cavity is an enclosed region containing a gas that is not necessarily breathing air and in some embodiments, the air gap is under vacuum conditions. The air gap or cavity is generally enclosed by a super structure. Generally, the MEMS structure 110 is packaged to ensure protection of the device from the working environment and protection of the environment from device material and operation. For example, one level of protection provides protection from interference from other mechanical structure or objects to ensure structural integrity of the MEMS structure 110. In this type of enclosure, the barrier layer 120 should be made of a material that can withstand the general rigors of a particular operating environment of a MEMS device. Another additional level of protection may further provide protection from exposure to oxygen or water (e.g., a hermetic enclosure). Accordingly, for this type of protection, the barrier layer 120 is generally made of a metal material that provides an airtight seal around the air cavity 108. In addition, some barrier levels 120 may also provide an additional level of protection which further provides protection from exposure to any outside gases. For this last level of protection, a vacuum is produced inside the air cavity 108 and the barrier layer 20 is generally made of a metal material that maintains the vacuum inside the air cavity 108. In accordance with one embodiment of the present disclosure, a process 200 for fabricating the MEMS device package 100 is discussed with regard to FIG. 2 and FIG. 3. This process 200 is based upon thermal decomposition of a sacrificial material, as described herein. It should be noted that for clarity, some portions of the fabrication process are not included in FIG. 2. As such, the following fabrication process is not intended to be an exhaustive list that includes all steps required for fabricating the MEMS device package 100. In addition, the fabrication process is flexible because the process steps may be performed in a different order than the order illustrated in FIG. 2 or some steps may be performed simultaneously. Referring now to FIGS. 2 and 3, a thermally decomposable sacrifical polymer (e.g., Unity 200, Promerus, LLC, Brecksville, Ohio) is applied (210) to the surface of a released MEMS device 310 to produce a MEMS device package 320 having a sacrificial layer 325. Sacrificial polymer material is patterned so as to encapsulate the surface or portions of the surface of the MEMS device 310 to produce the sacrificial layer 325. For example, a photosensitive or photodefinable sacrificial polymer material may be used to make the sacrificial layer 325. Accordingly, the photodefinable polymer can be deposited onto the substrate 328 using techniques such as, for example, spin-coating, doctor-blading, sputtering, lamination, screen or stencil-printing, melt dispensing, chemical vapor deposition (CVD), and plasma-based deposition systems. Then, after patterning with the sacrificial material 325, the MEMS device is overcoated with a dielectric material (e.g., Avatrel, Polymide, SU8) 335 on top of the sacrificial layer 325 and any other desired areas on the MEMS structure. As such, the overcoat layer is applied (220) to the MEMS structure 320 to produce the MEMS device package 330 having sacrificial layer 325 and overcoat layer 335. The overcoat layer 335 can be deposited onto the substrate 328 using techniques such as, for example, spin coating, photo-defining methods, doctor-blading, sputtering, lamination, screen or stencil-printing, melt dispensing, chemical vapor deposition (CVD), and plasma-based deposition systems. The overcoat materials can also be patterned to expose features, such as bond pads or contacts. After the overcoat 335 is prepared, the sacrificial layer 325 is decomposed by heating the sacrifical polymer material of the sacrifical layer 325 to a temperature sufficient to decompose the polymer (e.g., 200-250° C.). For example, the sacrificial layer 325 may be decomposed (230) in. an oven by exceeding the thermal decomposition temperature of the sacrificial layer 325 to produce a MEMS device package 340 having a substantially residue-free, low-residue air gap, or a residue-free cavity 348 surrounded by overcoat layer 335. Residues below a “substantial” value have little or no effect on the final product and can be considered “residue free.” For example, in MEMS devices, residues less than 10 nm typically have no effect on the end-product and are considered residue free. During this process, the decomposition products of the sacrificial layer 325 diffuse or permeate through the overcoat layer 335. In an additional step, additional metal material 355 is added (240) to the MEMS structure over the overcoat layer 335 (e.g., via sputtering and patterning the metal material) to produce a MEMS device package 350 with a metal cap or barrier 355 protecting an active surface 358 of a MEMS device. The metal barrier 355 provides one type of protection for the MEMS device 310 from external forces or elements. In particular, metals are known to provide a hermetic barrier. Therefore, the metal hermetic barrier 355 allows the MEMS device to be brought into ambient conditions. In some embodiments, vacuum packaging of a MEMS device is desired. One embodiment, among others, for implementing vacuum packaging of a MEMS device employs the previously described process 200. However, to add the additional metal material in step 335, the MEMS device 340 is placed in a vacuum chamber, such as in an evaporator, and air within the air cavity region 348 is evacuated. While under vacuum, metal is then deposited over the overcoat material, as previously described in step 255. The metal barrier 355 prevents air from entering the region encapsulated by metal, thus providing a vacuum package for the MEMS device. Note, in some embodiments, the step for removing the sacrificial layer may also be performed in a vacuum chamber such that multiple steps may then be performed simultaneously. Further note, that in some embodiments, a MFMS package is produced without undergoing each of the aforementioned steps of FIG. 2 and is still readily suitable for further processing in order to provide electrical connections to external points or terminals, as is discussed hereinafter. A sacrificial polymer used to produce the sacrificial layer 325 can be a polymer that slowly decomposes and does not produce undue pressure build-up while forming the air cavity region 348 within the surrounding materials. In addition, the decomposition of the sacrificial polymer produces gas molecules small enough to permeate the overcoat layer 335. Further, the sacrificial polymer has a decomposition temperature less than the decomposition or degradation temperature of the MEMS structure and overcoat material. Still further, the sacrificial material should have a decomposition temperature above the deposition or curing temperature of an overcoat material but less than the degradation temperature of the components in the structure in which the sacrificial polymer is being used. The sacrificial polymer can include compounds such as, but not limited to, polynorbomenes, polycarbonates, polyethers, polyesters, functionalized compounds of each, and combinations thereof. The polynorbomene can include, but is not limited to, alkenyl-substituted norbonene (e.g., cyclo-acrylate norbornene). The polycarbonate can include, but is not limited to, norbornene carbonate, polypropylene carbonate, polyethylene carbonate, polycyclohexene carbonate, and combinations thereof. In addition, the sacrificial polymer can include additional components that alter the processability (e.g., increase or decrease the stability of the sacrificial polymer to thermal and/or light radiation) of the sacrificial polymer. In this regard, the components can include, but are not limited to, photoinitiators and photoacid initiators. Embodiments of the disclosed sacrificial composition include, but are not limited to, a sacrificial polymer and one or more positive tone or negative tone component. The positive tone component can include a photoacid generator. For example, the sacrificial component can include either a negative tone component and/or a positive tone component. The negative tone component can include compounds that generate a reactant that would cause the crosslinking in the sacrificial polymer. The negative tone component can include compounds, such as, but not limited to, a photosensitive free radical generator. Alternative negative tone components can be used, such as photoacid generators (e.g., in epoxide-functionalized systems). A negative tone photosensitive free radical generator is a compound which, when exposed to light breaks into two or more compounds, at least one of which is a free radical. In particular, the negative tone photoinitiator can include, but is not limited to, bis(2,4,6-trimethylbenzoyl)-phenylphosphineoxide (Irgacure 819, Ciba Specialty Chemicals Inc.); 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butanone-1 (Irgacure 369, Ciba); 2,2-dimethoxy-1,2-diphenylethan-1-one (Irgacure 651, Ciba); 2-methyl-1[4-(methylthio)-phenyl]-2-morpholinopropan-1-one (Irgacure 907, Ciba); benzoin ethyl ether (BEE, Aldrich); 2-methyl-4′-(methylthio)-2-morpholino-propiophenone; 2,2′-dimethoxy-2-phenyl-acetophenone (Irgacure 1300, Ciba); 2, 6-bis(4-azidobenzylidene)-4-ethylcyclohexanone (BAC-E), and combinations thereof. The positive tone components can include, but is not limited to, photoacid generator(s). More specifically, the positive tone photoacid generator can include, but is not limited to, nucleophilic halogenides (e.g., diphenyliodonium salt, diphenylfluoronium salt) and complex metal halide anions (e.g., triphenylsulphonium salts). In particular, the photoacid generator can be tetrakis(pentafluorophenyl)borate-4-methylphenyl[4-(1-methylethyl)phenyl]iodonium (DPI-TPFPB); tris(4-t-butylphenyl)sulfonium tetrakis-(pentafluorophenyl)borate (TTBPS-TPFPB); tris(4-t-butylphenyl)sulfonium hexafluorophosphate (TTBPS-HFP); triphenylsulfonium triflate (TPS-Tf); bis(4-tert-butylphenyl)iodonium triflate (DTBPI-Tf); triazine (TAZ-101); triphenylsulfonium hexafluoroantimonate (TPS-103); Rhodosilm Photoinitiator 2074 (FABA); triphenylsulfonium bis(perfluoromethanesulfonyl) imide (TPS-N1); di-(p-t-butyl) phenyliodonium bis(perfluoromethanesulfonyl) imide (DTBPI-N1); triphenylsulfonium; tris(perfluoromethanesulfonyl) methide (TPS-C1); di-(p-t-butylphenyl)iodonium tris(perfluoromethanesulfonyl)methide (DTBPI-C1); and combinations thereof. The photoacid generator can be from about 0.5% to 5% by weight of the sacrificial composition. In particular, the photoacid generator can be from about 1% to 3% by weight of the sacrificial composition. The remaining percentage of the sacrificial composition not accounted for in the photoacid generator and sacrificial polymer (e.g., from about 50% to about 99%) can be made up with solvent, such as, but not limited to, mesitylene, N-methyl-2-pyrrolidinone, propylene carbonate, anisole, cyclohexanone, propyleneglycol monomethyl ether acetate, N-butyl acetate, diglyme, ethyl 3-ethoxypropionate, and combinations thereof. The thermal decomposition of the sacrificial polymer can be performed by heating the MEMS device package to the decomposition temperature of the sacrificial polymer and holding at that temperature for a certain period of time (e.g., 1-2 hours). Thereafter, the decomposition products diffuse or permeate through the overcoat polymer layer leaving a virtually residue-free hollow structure (air cavity). The overcoat layer 335 can be any modular polymer or deposited film (e.g. silicon dioxide, silicon nitride, etc.) that includes the characteristic of being permeable or semi-permeable to the decomposition gases produced by the decomposition of a sacrificial polymer while forming the air gap or cavity. In addition, the overcoat polymer layer has elastic properties so as to not rupture or collapse under fabrication and use conditions. Further, the overcoat layer 335 is stable in the temperature range in which the sacrificial polymer decomposes. Examples of the overcoat layer 335 include compounds such as, for example, polyimides, polynorbomenes, epoxides, polyarylenes ethers, and parylenes. More specifically, the overcoat layer 335 includes compounds such as Amoco Ultradel™ 7501, BF Goodrich Avatrel™ Dieelectric Polymer, DuPont 2611, DuPont 2734, DuPont 2771, and DuPont 2555. The overcoat layer 335 can be deposited on the substrate using techniques such as, for example, spin coating, doctor-blading, sputtering, lamination, screen or stencil-printing, chemical vapor deposition (CVD), plasma based deposition systems, etc. A variety of approaches may be used to apply the thermally decomposable sacrificial layer and overcoat layer to a MEMS device. As such, FIG. 4 shows a diagram describing one such process this is aptly suited for packaging surface micromachined MEMS devices such as silicon on insulator (SOI) resonators or other MEMS devices with small holes (e.g., H>>g and t<<50 μm, where H is height of air cavity; g is width of hole; and t is thickness of sacrificial layer), as represented by FIG. 5. In this packaging via patterning (PVP) approach, a photo-definable sacrificial polymer Unity 200 (Promerus, LLC, Brecksville, Ohio) is first spin-coated on the surface of a MEMS device 410 to produce a thin sacrificial layer 412, and the MEMS device is soft-baked (420). Then, deep UV exposure (λ=248 nm) is performed (420) to pattern the thin sacrificial layer 412. The sacrificial layer 412 is bake-developed (430) at about 110° C. to decompose the exposed area, followed by encapsulation (440) of the sacrificial material using a photo-definable polymer overcoat Avatrel (Promerus, LLC) 414. After the encapsulation (440), the bond pads 416 are opened via photo-patterning (450) of the overcoat material 414. The sacrificial material under the overcoat that covers the MEMS structure is then thermally decomposed (460) at about 200-300° C. to create an air-cavity 418. This is the highest temperature step in this process. The by-products of thermal decomposition can easily diffuse out of the cavity 418 through the overcoat 414. An aluminum layer 417 can be sputtered (470) to hermetically seal the packaged MEMS device. After decomposition of the sacrificial material, the inside of the cavity 418 is clean of sacrificial material, and the device structure 419 is intact and free to move without any residue on the device. For example in one experimental trial, a 25 μm thick SOI beam resonator (2.6 MHz frequency) with a 1 μm gap was packaged via PVP with a Unity sacrificial material. The Unity sacrificial material is a photo-definable polycarbonate that has good adhesion to silicon, oxide, and metals and is thermally decomposable at low temperatures. Moreover, the Unity sacrificial material is characterized by clean decomposition in a narrow temperature range. In this trial, the Q-factor (Q=8000) did not change for this device after packaging and removal of the sacrificial material. Alternatively, FIG. 6 describes a packaging via dispensing (PVD) approach for applying the thermally decomposable sacrificial layer. This approach is more suitable to package bulk micromachined structures (e.g., HARPSS gyros/accelerometers) with fragile elements and wide and deep cavities (e.g., L>>g, where L represents the length of an air cavity 710 and g represents the width of a hole 720), as represented by FIG. 7. In this approach, thermally decomposable sacrificial material 610 (which does not have to be photo-definable) is applied (620) via a syringe dispensing tool (e.g., manually or automatically) with adjustable droplet size (e.g., 1 mm to 1 cm) to cover the air cavity 612. The sacrificial material 610 is then overcoated (630) using Avatrel overcoat material, and the process sequence continues similar to the PVP process, including a thermal release step (640) for decomposing the sacrificial layer 610 and a metallization step (650) for adding a metal barrier layer 617 over the air cavity 616. The final metallization step (650) enables a hermetically sealed package 618. The aforementioned processes are examples of techniques for applying a sacrificial material 105 and/or barrier materials 120 (e.g., overcoat materials, metal layers, other protective barriers, etc.) to MEMS devices. However, the present disclosure is not limited to the processes discussed with regard to FIGS. 4-7. For example, other lithography and etching techniques used in semiconductor fabrication processes may be used. As such, a MEMS device could also be packaged using a masked etching process on a thick sacrificial material which is aptly suited for packing small MEMS devices (e.g., HARPSS resonator, RF switch) with fragile elements or wide and deep holes (e.g., t>L>50 μm, where t represents the thickness of a sacrificial layer 810 and L is measures the length of an air cavity 820), as represented by FIG. 8. As such, an oxygen mask may be used to remove sacrificial material from undesired areas with an oxygen plasma. The feasibility of applying the aforementioned methods to package MEMS devices has been successfully verified. For example, a 15 μm thick 2.6 MHz SOI beam resonator (released) with 1 μm gap spacing, shown in FIG. 9A (with SCS beam and isolation trench noted), was packaged via PVP. Narrow trenches were etched down to the buried oxide to define the shape of the resonator and the sense/drive pads, followed by the removal of the buried oxide in HF solution. FIG. 9B shows the picture of the resonator after PVP. As shown, the resonator features a 15 μm tall cavity with a 20 μm thick overcoat layer. FIG. 9C shows the packaged resonator, after DC sputtering of gold to hermetically seal the device. In this device, the Avatrel overcoat was extended on top of isolation trenches. FIG. 9D shows the cross section of a broken packaged resonator (with SCS beam noted), showing a 15 μm tall, 80 μm wide cavity under a 20 μm thick Avatrel cap. In order to evaluate the PVD method, a 50 μm thick polysilicon HARPSS ring gyroscope with 1 μm gap and 200 μm deep cavity was fabricated, as shown in FIG. 10A. HARPSS sequence starts with patterning the nitride anchors and defining the trench. A thin layer of sacrificial oxide is deposited to uniformly cover the trench sidewalls and define the capacitive gap in between the SCS and polysilicon electrodes. Trenches are refilled with doped polysilicon to form the ring, springs, and the electrodes. Finally, the sensor is released in a DRIE tool, followed by removing the sacrificial oxide in HF solution. FIG. 10B shows the same device after manual dispensing of the sacrificial material. FIG. 10C is the view of the device after forming a thick (120 μm) overcoat cap and decomposing the sacrificial material from inside the cavity. FIG. 10D shows the device after breaking the 2 mm wide Avatrel capsule, confirming a very clean cavity and intact device structure (device is free to vibrate). The close-up view of the electrodes, the 1 μm capacitive gap, and the 4 μm wide polysilicon ring and support springs are shown in FIGS. 10E and 10F. This clearly shows that the sacrificial material can be decomposed through a very thick overcoat to create a stiff cap. It takes a few hours in room temperature before the air molecules can outgas through the Avatrel cap inside a vacuum chamber and the structure can start to resonate with high Q-factor. The packaged resonator of FIGS. 9A-9D was tested at wafer-level inside a vacuum probe station. A DC polarization voltage in the range of 70-80V was applied while the electrodes were directly connected to the network analyzer. FIG. 11A shows the frequency response of the resonator in vacuum before packaging and FIG. 11B shows the frequency response of the resonator in vacuum after packaging. The high Q-factor of approximately 5000 did not change for this device, proving that thermal decomposition of the Unity sacrificial material after packaging does not affect the performance of the device. As previously mentioned, a variety of MEMS device packages may be fabricated with varying levels of protection against environmental elements. Accordingly, examples of embodiments of MEMS packages include, but are not limited to, the following. In FIG. 12, one embodiment of a MEMS device package 1200 is shown In this embodiment, the MEFMS device package 1200 includes a substrate layer 1210, active region of MEMS device 1220, a vacuum packed air cavity region 1225, the contacts 1230, an overcoat layer 1240, and a barrier layer 1250. The package 1200 is fabricated by a process similar to that described with regard to the process of FIG. 2 where a sacrificial layer 325 has been removed to form the overcoat layer 1240 and barrier layer 1250 which may provide varying degrees of hermetic protection for the MEMS device. During this process, air inside the cavity 1225 was evacuated to produce a vacuum inside the cavity 1225, where the metal barrier 1250 prevents air from entering the air cavity region 1225. By converting the sacrificial material 325 to a gaseous material that permeates the overcoat layer 1240, the cavity 1225 is free of residue, including any residual sacrificial material. Correspondingly, the overcoat layer 1240 is also free of residue and maintains structural integrity, since perforations were not drilled into the overcoat layer to remove any sacrificial material. The MEMS package 1200 may be connected to external points or undergo further packaging by a variety of methods, including wirebond technology, flip-chip technologies, utilizing leadframe packaging, surface mount packaging, ceramic packaging, or other high performance techniques, as is described hereinafter. A particular processing technique available for a MEMS device may be dependent upon the level of protection offered by the overcoat and barrier layers, since different processing techniques exert different amounts of pressure and rigors on microelectronic devices. Referring now to FIG. 13, another embodiment of a MEMS package 1300 is shown. In FIG. 13, the MEMS device package 1300 includes a substrate layer 1310, active surface of a MEMS device 1320, an air cavity 1325 surrounding the active surface of the MEMS device, the contacts 1330, an overcoat layer 1340, and a barrier layer 1350. The package 1300 is fabricated by a process similar to that process described with regard to FIG. 2 where a sacrificial layer 325 has been removed to form the overcoat layer 1340 and barrier layer 1350. However, for this embodiment, the process of forming a vacuum inside the air cavity 1325 is not performed, since there are many MEMS devices that do not require vacuum packing. As such, the barrier layer 1350 may still prevent air and moisture from entering the air cavity region 1325 encapsulated by the barrier layer 1350 (e.g., a metal layer). Further, by converting the sacrificial material 325 to a gaseous material that permeates the overcoat layer 1340, the air cavity 1325 is free of residue, including any residual sacrificial material. Correspondingly, the overcoat layer 1340 is also free of residue and maintains structural integrity, since perforations were not drilled into the overcoat layer to remove any sacrificial material. The MEMS device package 1300 may be connected to external points by a variety of methods, including wirebond technology, flip-chip technologies, utilizing leadframe packaging, surface mount packaging, ceramic packaging, or other high performance techniques, as is described hereinafter. A particular processing technique available for a MEMS device may be dependent upon the level of protection offered by the overcoat and barrier layers, since different processing techniques exert different amounts of pressure and rigors on microelectronic devices. In another embodiment, FIG. 14 shows a MEMS device package 1400 with a substrate layer 1410, an active surface of MEMS device 1420, an air cavity region 1425 around the active surface of MEMS device, the contacts 1430, and an overcoat layer 1440 that also serves as a protective layer. This package 1400 is fabricated by a process similar to a portion of the process that is described with regard to FIG. 2 where a sacrificial layer 325 has been removed to form the overcoat layer 1440. However, in this example, the package 1400 is complete after the sacrificial layer 325 has been removed (230) and the overcoat layer 1440 remains. Accordingly, as part of adding (220) the overcoat layer, the overcoat material is generally baked in order to make the overcoat rigid and hard, which may serve as adequate protection against external forces for many applications and types of MEMS devices. Moreover, by converting the sacrificial material 325 to a gaseous material that permeates the overcoat layer 1440, the air cavity 1425 is free of residue, including any residual sacrificial material. Correspondingly, the overcoat layer 1440 is also free of residue and maintains structural integrity, since perforations were not drilled into the overcoat layer to remove any sacrificial material. The MEMS device package 1400 may be connected to external points by a variety of methods, including wirebond technology, flip-chip technologies, utilizing leadframe packaging, surface mount packaging, ceramic packaging, or other high performance techniques, depending upon the particular qualities of the packaging processes and the protection requirements of particular MEMS devices. Referring now to FIG. 15, another embodiment of a MEMS device package 1500 is shown. In this embodiment, the MEMS device package 1500 includes a substrate layer 1510, an active surface of MEMS device 1520, an air cavity 1525 surrounding the active surface of the MEMS device, the contacts 1530, and a sacrificial layer 1540. The package 1500 is fabricated by a process similar to a portion of the process described with regard to FIG. 2 where a sacrificial material has been applied to form a sacrificial layer 325. However, in this particular example, the process is completed after the step of adding the sacrificial layer has been performed (210). Accordingly, as part of adding the sacrificial layer, the sacrificial material is encased around the active surface of a MEMS device 1520, which may serve as adequate protection against external forces before the MEMS device package is subsequently attached to external points or terminals by current wirebonding techniques and/or surface mounting practices. After packaging of the MEMS device, the MEMS device package may not only resemble an integrated circuit (e.g., it has wire bond pads, a coated surface, etc.), but may also be treated like many integrated circuits and may be packaged like many integrated circuits. For example, consider the following process for attaching a MEMS device to a support structure, such as a metal frame traditionally used for mounting integrated circuits (e.g., leadframe). As described in FIG. 16, a process for attaching a MEMS device 1500 having a sacrificial layer 1540 surrounding a MEMS device is discussed. Accordingly, a leadframe (1600) is provided. In this example, a thin metal sheet (e.g., Copper) is processed into a leadframe 1600 having a die pad 1610 for attaching a microelectronic device package and lead fingers 1620 for connecting wires to bond pads or contacts on the microelectronic device. Correspondingly, a MEMS device package 1630 having a sacrificial layer 1540 is attached (1625) to the leadframe 1600 (by mounting or bonding the package 1630 to the die pad 1610 of the leadframe 1600). Further, metal wires 1640 are connected (1625) from the lead fingers 1620 or terminals of the leadframe 1600 and the bond pads or contacts 130 of the MEMS device package 1630. Then, a coating material 1650 (e.g., plastic molding compounds, thermosetting polymers, epoxy resin, etc.) is applied (1645) to the surface of the MEMS device package and a portion of the leadframe 1600 as part of a molding process. The coating material 1650 used in this process has a curing temperature that is lower than the temperature for thermal decomposition of the sacrificial material 1540 in the MEMS device package 1500. Thus, the coating material 1650 is cured at a lower temperature (that is less than the temperature for thermal decomposition of the sacrificial material) to harden the coating material. The coating material 1650 includes the characteristic of being permeable or semi-permeable to the decomposition gases produced by the decomposition of a sacrificial polymer of the sacrificial layer 1540. The coating material 1650 serves to provide a moisture-resistive material over the surface of the MEMS device and lead frame assembly or “chip” for the purpose of minimizing package stresses on the surface of the chip and provide additional protection against corrosion. This is a standard step in low-cost microelectronic packaging of integrated circuits. However, with MEMS devices, such as step would typically negatively interfere and harm the workings of a MEMS structure that does not have a protective covering. Accordingly, with the presence of the sacrificial layer 1540, the coating 1650 is not in contact with the active surface of the MEMS device. After the coating 1650 has cured and is hardened, the MEMS chip is then baked at a temperature that exceeds the thermal decomposition of the sacrificial material. After which, the sacrificial material is converted into a gaseous state and permeates or diffuses through the coating material 1650. After decomposition of the sacrificial layer, an air cavity is formed around the active surface of the MEMS device, and the coating material 1650 now serves as a protective layer to prohibit elements from entering the air cavity and to protect the MEMS device, in general. The MEMS “chip” 1660 is then removed (1655) from the leadframe via a singulation process and the leads of chip are bent into a desired shape, as part of standard chip packaging process. A process, as just described, has worked well in thin epoxy packages (such as TSOP (thin small outline package) and TQFP (thin quad flat package). However, the process is not limited to thin epoxy coatings and may also work with other coating variants. Further, other embodiments of the MEMS device package may also be employed in a similar process. For example, for one embodiment (as represented by FIG. 14), the MEMS device package includes an overcoat layer 1440 that provides additional support for the MEMS device without affecting the thermal decomposition of a sacrificial material 1425. Thus, such a MEMS device package may also be added to a leadframe using the process described in FIG. 16. Additionally, in other embodiments (as represented by FIGS. 12 and 13), MEMS device packages may not include a sacrificial layer and alternatively, includes additional support structures, such as a barrier level 1250, 1350. As such, these MEMS device package will not need to baked at a temperature exceeding the curing temperature of the coating material, since a sacrificial material is not present. Otherwise, the process described in FIG. 16 may be used to further package such MEMS device packages using common integrated circuit packaging processes (e.g., leadframe packaging). According to the present disclosure, some embodiments of the micro electro-mechanical device packages generally include one or more MEMS devices; interconnection from the device(s) to the package; a surrounding or containing structure to provide both mechanical and electrical, chemical, and environmental protection; and a joining structure to attach the package to a circuit board or system. Such embodiments provide a versatile packaging process at a wafer-level for MEMS devices that is generally applicable to package devices fabricated by different processes for various applications. Accordingly, embodiments of the present disclosure are capable of adapting to well-developed integrated circuit packaging technologies, as demonstrated in FIG. 17. Referring now to FIG. 17, a MEMS device package 1710 of the present disclosure can be produced to meet an assortment of packaging requirements and preferences. For example, a MEMS device package 1710 can be packaged to provide varying levels or degrees of hermetic protection for a MEMS device. As shown in FIG. 17, hermetic protection levels include, but is not limited to, mechanical protection 1720 (e.g., from inadvertent touching, further packaging, etc.), protection from oxygen and water in addition to mechanical protection 1730, and protection from all exposure to all gases (e.g., have a pure vacuum) in addition to mechanical protection 1740. In addition to varying degrees of hermetic protection, a MEMS device package 1710 can also utilize a variety of bonding techniques to provide electrical connections to external points or terminals. Such bonding techniques include, but are not limited to, wire bonding techniques 1750 and flip chip bonding techniques 1760. Moreover, a MEMS device package 1710 of the present disclosure can be further utilized in a variety of microelectronic device packaging techniques that are already in common use. For example, a MEMS device package may utilize common integrated circuit techniques that include, but are not limited, to low cost plastic packaging techniques 1770 and ceramic or other high performance packaging techniques 1780. For either of these approaches, additional packaging technologies are also available including, but not limited to, surface mount processes 1790 and through-hole mounting processes 1795. Advantageously, embodiments of the present disclosure provide a variety of improved approaches for protecting MEMS devices. For example, in accordance with the present disclosure, a sacrificial layer on a MEMS device may be removed without perforating an overcoat layer surrounding the sacrificial layer and active structures of a MEMS device. Further, the thickness of the overcoat layer and/or barrier layer may be adjusted or tailored (e.g., between range of 50 nm and 500 μm) to withstand external pressures or pressures encountered during packaging processes and provide adequate protection for a MEMS device. For example, the overcoat layer can be spin-coated at a different speed or the viscosity of the overcoat material may be changed to adjust the thickness of the overcoat layer that is formed on a MEMS device. Therefore, the thickness of the overcoat material could be made as thick as reasonably necessary (e.g., 5 cm). Advantageously, embodiments of the present disclosure may also provide a protective layer on any substrate material, since the sacrificial and overcoat materials are polymer substances and have good thermal mismatch characteristics with common substrate materials which does not result in deformations in MEMS structures. Additionally, there are a wide variety of sacrificial materials that can be employed in accordance with the present disclosure within a wide range of thermal decomposition temperatures. Thus, a desired thermal decomposition temperature can be selected (e.g., from 80° C. to 400° C.), and based upon the selected temperature, a sacrificial material can be chosen. Accordingly, decomposition time and temperature may be optimized for each application according to overcoat thickness. Further, sacrificial materials can be chosen based on whether a photosensitive sacrificial material is desired or not. It should be emphasized that the above-described embodiments of the present disclosure are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.	H	67H01	185H01L	23	20
11862174	US20080179696A1-20080731	Micromechanical Device with Microfluidic Lubricant Channel	ACCEPTED	20080716	20080731	[]	H01L2984	["H01L2984"]	7932569	20070926	20110426	257	415000	99963.0	PERT	EVAN	[{"inventor_name_last": "Chen", "inventor_name_first": "Dongmin", "inventor_city": "Saratoga", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Worley", "inventor_name_first": "William Spencer", "inventor_city": "Half Moon Bay", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "Hung-Nan", "inventor_city": "Kaohsiung Hsien", "inventor_state": "", "inventor_country": "TW"}]	A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held therein via surface tension of the lubricant against the internal surfaces of the lubrication channel. The lubricant channel containing the lubricant provides a ready supply of fresh lubricant to prevent stiction from occurring between interacting components of the micromechanical device disposed within the processing region.	1. A device assembly, comprising: a micromechanical device enclosed within a processing region; and a lubricant channel formed through at least one interior wall of the processing region to be in fluid communication with the processing region, wherein a substantial length of the lubricant channel extends into said at least one interior wall to be completely enclosed thereby. 2. The device assembly of claim 1, wherein a volume of the lubricant channel is between about 0.1 nanoliter and about 1000 nanoliters. 3. The device assembly of claim 2, wherein a lubricant is disposed in the lubricant channel. 4. The device assembly of claim 1, wherein a hydraulic diameter of the lubricant channel is less than about 1 mm, and a length of the lubricant channel is substantially larger than a hydraulic diameter of the lubricant channel. 5. The device assembly of claim 1, further comprising a channel inlet in fluid communication with the lubricant channel, wherein the channel inlet is formed through an external surface of the device assembly. 6. The device assembly of claim 5, further comprising a plug disposed in the channel inlet proximate the external surface of the device assembly. 7. The device assembly of claim 1, further comprising a particle filter disposed in the lubricant channel. 8. The device assembly of claim 7, wherein the particle filter comprises a plurality of obstructions formed on an interior surface of the lubricant channel. 9. The device assembly of claim 1, wherein first and second lubricant channels are formed respectively through different interior walls of the processing region to be in fluid communication with the processing region. 10. The device assembly of claim 9, wherein lubricants are disposed in the first and second lubricant channels, and the lubricant disposed in the first lubricant channel is different from the lubricant disposed in the second lubricant channel. 11. A device assembly, comprising: a micromechanical device enclosed within a processing region; and a lubricant channel formed on at least one interior wall of the processing region, wherein the lubricant channel is in fluid communication with the processing region along the entire length thereof, and the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. 12. The device assembly of claim 11, wherein a width of the lubricant channel is 10 μm to 800 μm and a depth of the lubricant channel is 10 μm to 200 μm. 13. The device assembly of claim 12, wherein a volume of the lubricant channel is between about 0.1 nanoliter and about 1000 nanoliters, and a hydraulic diameter of the lubricant channel is less than about 1 mm. 14. The device assembly of claim 11, further comprising another lubricant channel formed through at least one interior wall of the processing region to be in fluid communication with the processing region, wherein a substantial length of said another lubricant channel extends into said at least one interior wall to be completely enclosed thereby. 15. The device assembly of claim 11, wherein first and second lubricant channels are formed on at least one interior wall of the processing region, wherein each of the first and second lubricant channels are in fluid communication with the processing region along the entire length thereof. 16. A packaged micromechanical device, comprising: a lid, a base, and an interposer that define a processing region for a micromechanical device; a micromechanical device disposed within the processing region; and a lubricant channel formed through at least one interior wall of the processing region and in fluid communication with the processing region, wherein the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. 17. The packaged micromechanical device of claim 16, wherein an epoxy layer is interposed between the lid and the interposer and between the interposer and the base. 18. The packaged micromechanical device of claim 17, wherein the lubricant channel extends into said at least one interior wall to be completely enclosed thereby. 19. The packaged micromechanical device of claim 18, further comprising a cap disposed in the lubricant channel proximate an opening of the lubricant channel into the processing region. 20. The packaged micromechanical device of claim 19, wherein the cap comprises a material that becomes porous in response to optical radiation or heating. 21. The packaged micromechanical device of claim 17, further comprising another lubricant channel formed on at least one interior wall of the processing region, wherein said another lubricant channel is in fluid communication with the processing region along the entire length thereof. 22. The packaged micromechanical device of claim 16, wherein the lid and the interposer are frit- or eutectic-bonded, and the interposer and the base are frit- or eutectic-bonded 23. The packaged micromechanical device of claim 22, further comprising a channel inlet in fluid communication with the lubricant channel, wherein the channel inlet is formed through an external surface of the device. 24. The packaged micromechanical device of claim 23, further comprising a plug disposed in the channel inlet proximate the external surface of the device. 25. The packaged micromechanical device of claim 16, wherein the lubricant channel is formed in the base.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention Embodiments of the present invention relate generally to micro-electro-mechanical and nano-electro-mechanical systems and more specifically to such systems having one or more microfluidic lubricant channels. 2. Description of the Related Art As is well known, atomic level and microscopic level forces between device components become far more critical as devices become smaller. Problems related to these types of forces are quite prevalent with micromechanical devices, such as micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS). In particular, “stiction” forces created between moving parts that come into contact with one another, either intentionally or accidentally, during operation are a common problem with micromechanical devices. Stiction-type failures occur when the interfacial attraction forces created between moving parts that come into contact with one another exceed restoring forces. As a result, the surfaces of these parts either permanently or temporarily adhere to each other, causing device failure or malfunction. Stiction forces are complex surface phenomena that generally include capillary forces, Van der Waal's forces and electrostatic attraction forces. As used herein, the term “contact” refers generally to any interaction between two surfaces and is not limited to the actual physical touching of the surfaces. Some examples of typical micromechanical devices are RF switches, optical modulators, microgears, accelerometers, worm gears, transducers, fluid nozzles, gyroscopes, and other similar devices or actuators. It should be noted that the term “MEMS device” is used hereafter to generally describe a micromechanical device, and to cover both MEMS and NEMS devices discussed above. Stiction is especially problematic in devices such as the RF switch, optical modulator, microgears, and other actuators. Various elements in these devices often interact with each other during operation at frequencies between a few hertz (Hz) and a few gigahertz (GHz). Various analyses have shown that, without adding some form of lubrication to these types of devices to reduce stiction and wear between component surfaces, product lifetimes may range from only a few contacts to a few thousand contacts, which is generally well below a commercially viable lifetime. Consequently, one of the biggest challenges facing the MEMS and NEMS industries is the long-term reliability of contacting microstructures in the face of stiction. Several techniques to address stiction between two contacting surfaces have been discussed in various publications. One such technique is to texture the contact surfaces (e.g., via micro patterning or laser patterning) to reduce the overall adhesion force by reducing the effective contact area. Another such technique involves selecting specific materials from which the contacting surfaces are made to lower the surface energy, reduce charging, or contact potential difference between components. Moreover, some prior references have suggested the insertion of a lubricant into the region around the interacting devices to reduce the chance of stiction-related failures. Such a lubricant often times is in a solid or liquid state, depending on the properties of the material, and the temperature and pressure or environment in which the lubricant is placed. In general, the terms a “solid” lubricant or a “liquid” lubricant is a lubricant that is in a solid or liquid state under ambient conditions, i.e., room temperature and atmospheric pressure. Some prior art references describe a lubricant as being in a “vapor” state. These references use the term vapor phase lubricant to generally describe a mixture of components that contain a carrier gas (e.g., nitrogen) and a vaporized second component that is a solid or liquid at temperatures and pressures near ambient conditions (e.g., STP). In most conventional applications, the solid or liquid lubricant remains in a solid or liquid state at temperatures much higher than room temperature and pressures much lower than atmospheric pressure conditions. Examples of typical lubricants that are solid or liquid at ambient conditions and temperatures well above ambient temperature can be found in references such as U.S. Pat. No. 6,930,367. Such prior art lubricants include dichlorodimethylsilane (“DDMS”), octadecyltrichlorosilane (“OTS”), perfluoroctyltrichlorsilane (“PFOTCS”), perfluorodecanoic acid (“PFDA”), perfluorodecyl-trichlorosilane (“FDTS”), perfluoro polyether (“PFPE”) and/or fluoroalkylsilane (“FOTS”), that are deposited on various interacting components by use of a vapor deposition process, such as atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other similar deposition processes. The technique of forming the low-surface energy organic passivation layer on the surface of a MEMS component is commonly referred to in the art as “vapor lubricant” coating. One serious draw back to using a low-surface energy organic passivation layer, such as self-assembled monolayer (SAM) coatings, is that they typically are on the order of one monolayer thick. Generally, these types of coatings have a very limited usable lifetime, since they are easily damaged or displaced due to impact or wear created by the interaction of the various moving components. This inevitably happens in MEMS devices with contacting surfaces that are subject to frequent contact in use and a large number of contacts during the product lifetime, such as in light modulators and RF switches. Without some way to reliably restore or repair the damaged coatings, stiction occurs, and device failure results. As shown in FIG. 1A , one approach for lubricating MEMS components is to provide a getter 110 within the package 100 (that includes a base 111 , a lid 104 , and a seal 106 ) in which an array of MEMS devices 108 resides. FIG. 1B illustrates one conventional package 120 that contains a MEMS device 108 and a getter 110 positioned within the head space 124 of the package 120 . The package 120 also contains a package substrate 128 , window 126 and spacer ring 125 . These two configurations are further described in U.S. Pat. No. 6,843,936 and U.S. Pat. No. 6,979,893, respectively. These conventional devices employ some type of reversibly-absorbing getter to store the lubricant molecules in zeolite crystals or the internal volume of a micro-tube. In these designs, a supply of lubricant is maintained in the getter 110 , and an amount of lubricant needed to lubricate the MEMS device 108 is discharged during normal operation. However, adding the reversibly absorbing getter, or reservoirs, to retain the liquid lubricants increases package size and packaging complexity and adds steps to the fabrication process, all of which increase piece-part cost as well as the overall manufacturing cost of MEMS or NEMS devices. Thus, forming a device that uses these techniques generally requires a number of labor-intensive and costly processing steps, such as mixing the getter material, applying the getter material to the device-containing package, curing the getter material, conditioning or activating the getter material, and then sealing the MEMS device and the getter within the sealed package. Particles, moisture, and other contaminants found in our everyday atmospheric environment deleteriously effect device yield of a MEMS fabrication process and the average lifetime of a MEMS device. In an effort to prevent contamination during fabrication, the multiple process steps used to form a MEMS device are usually completed in an ultra-high grade clean room environment, e.g., class 10 or better. Due to the high cost required to produce and maintain a class 10 or better clean room environment, the more MEMS device fabrication steps that require such a clean room environment, the more expensive the MEMS device is to make. Therefore, there is a need to create a MEMS device fabrication process that reduces the number of processing steps that require an ultra-high grade clean room environment. As noted above, in an effort to isolate the MEMS components from the everyday atmospheric environment, MEMS device manufacturers typically enclose the MEMS device within a device package so that a sealed environment is formed around the MEMS device. Conventional device packaging processes commonly require the lubricating materials that are contained within the MEMS device package be exposed to high temperatures during the MEMS device package sealing processes, particularly wafer level hermetic packaging. Typically, conventional sealing processes, such as glass frit bonding or eutectic bonding, require that the MEMS device, lubricants, and other device components are heated to temperatures between about 250° C. to 450° C. These high-bonding temperatures severely limit the type of lubricants that can be used in a device package and also cause the lubricant to evaporate away or break down after a prolonged period of exposure. In addition, lubricant that has evaporated during high temperature bonding processes can later re-condense onto and contaminate sealing surfaces. Therefore, there is also a need for a MEMS device package-fabricating process that eliminates or minimizes the exposure of lubricants to high temperatures during the device fabrication process.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention generally relates to a micromechanical device that has an improved usable lifetime due to the presence of one or more channels that contain and deliver a lubricant that can reduce the likelihood of stiction occurring between the various moving parts of the device. A device assembly according to an embodiment of the invention includes a micromechanical device enclosed within a processing region and a lubricant channel formed through at least one interior wall of the processing region to be in fluid communication with the processing region, wherein a substantial length of the lubricant channel extends into said at least one interior wall to be completely enclosed thereby. The volume of the lubricant channel may be between 0.1 nanoliter and 1000 nanoliters. The hydraulic diameter of the lubricant channel may be less than about 1 mm, and a length of the lubricant channel is substantially larger than a hydraulic diameter of the lubricant channel. A device assembly according to another embodiment of the invention comprises a micromechanical device enclosed within a processing region and a lubricant channel formed on at least one interior wall of the processing region, wherein the lubricant channel is in fluid communication with the processing region along the entire length thereof, and the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. Embodiments of the invention also provide a packaged micromechanical device that includes a lid, a base, and an interposer that define a processing region for a micromechanical device, a micromechanical device disposed within the processing region, and a lubricant channel formed through at least one interior wall of the processing region and in fluid communication with the processing region, wherein the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. An epoxy layer may be interposed between the lid and the interposer and between the interposer and the base. Typically, a channel inlet that is in fluid communication with the lubrication channel is formed through an exterior wall of the micromechanical device assembly or package. Lubricant is injected into the lubrication channel through this channel inlet. However, when an epoxy layer is used, the lubricant may be injected into the lubricant channel prior to the sealing of the package and the channel inlet becomes no longer necessary. One advantage of the invention is that a reservoir of a lubricating material is formed within a device package so that an amount of “fresh” lubricating material can be delivered to areas where stiction may occur. In one aspect, the lubricating material is contained in one or more microchannels that are adapted to evenly deliver a mobile lubricant to interacting areas of the MEMS device. In another aspect, different lubricant materials can be brought into the device in a sequential manner via one channel, or contained concurrently in separate channels. Consequently, the lubricant delivery techniques described herein more reliably and cost effectively prevent stiction-related device failures relative to conventional lubricant delivery schemes.	CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/847,831, filed Sep. 27, 2006, entitled “Method of Sealing a Microfluidic Lubricant Channel Formed in a Micromechanical Device,” which is herein incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention Embodiments of the present invention relate generally to micro-electro-mechanical and nano-electro-mechanical systems and more specifically to such systems having one or more microfluidic lubricant channels. 2. Description of the Related Art As is well known, atomic level and microscopic level forces between device components become far more critical as devices become smaller. Problems related to these types of forces are quite prevalent with micromechanical devices, such as micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS). In particular, “stiction” forces created between moving parts that come into contact with one another, either intentionally or accidentally, during operation are a common problem with micromechanical devices. Stiction-type failures occur when the interfacial attraction forces created between moving parts that come into contact with one another exceed restoring forces. As a result, the surfaces of these parts either permanently or temporarily adhere to each other, causing device failure or malfunction. Stiction forces are complex surface phenomena that generally include capillary forces, Van der Waal's forces and electrostatic attraction forces. As used herein, the term “contact” refers generally to any interaction between two surfaces and is not limited to the actual physical touching of the surfaces. Some examples of typical micromechanical devices are RF switches, optical modulators, microgears, accelerometers, worm gears, transducers, fluid nozzles, gyroscopes, and other similar devices or actuators. It should be noted that the term “MEMS device” is used hereafter to generally describe a micromechanical device, and to cover both MEMS and NEMS devices discussed above. Stiction is especially problematic in devices such as the RF switch, optical modulator, microgears, and other actuators. Various elements in these devices often interact with each other during operation at frequencies between a few hertz (Hz) and a few gigahertz (GHz). Various analyses have shown that, without adding some form of lubrication to these types of devices to reduce stiction and wear between component surfaces, product lifetimes may range from only a few contacts to a few thousand contacts, which is generally well below a commercially viable lifetime. Consequently, one of the biggest challenges facing the MEMS and NEMS industries is the long-term reliability of contacting microstructures in the face of stiction. Several techniques to address stiction between two contacting surfaces have been discussed in various publications. One such technique is to texture the contact surfaces (e.g., via micro patterning or laser patterning) to reduce the overall adhesion force by reducing the effective contact area. Another such technique involves selecting specific materials from which the contacting surfaces are made to lower the surface energy, reduce charging, or contact potential difference between components. Moreover, some prior references have suggested the insertion of a lubricant into the region around the interacting devices to reduce the chance of stiction-related failures. Such a lubricant often times is in a solid or liquid state, depending on the properties of the material, and the temperature and pressure or environment in which the lubricant is placed. In general, the terms a “solid” lubricant or a “liquid” lubricant is a lubricant that is in a solid or liquid state under ambient conditions, i.e., room temperature and atmospheric pressure. Some prior art references describe a lubricant as being in a “vapor” state. These references use the term vapor phase lubricant to generally describe a mixture of components that contain a carrier gas (e.g., nitrogen) and a vaporized second component that is a solid or liquid at temperatures and pressures near ambient conditions (e.g., STP). In most conventional applications, the solid or liquid lubricant remains in a solid or liquid state at temperatures much higher than room temperature and pressures much lower than atmospheric pressure conditions. Examples of typical lubricants that are solid or liquid at ambient conditions and temperatures well above ambient temperature can be found in references such as U.S. Pat. No. 6,930,367. Such prior art lubricants include dichlorodimethylsilane (“DDMS”), octadecyltrichlorosilane (“OTS”), perfluoroctyltrichlorsilane (“PFOTCS”), perfluorodecanoic acid (“PFDA”), perfluorodecyl-trichlorosilane (“FDTS”), perfluoro polyether (“PFPE”) and/or fluoroalkylsilane (“FOTS”), that are deposited on various interacting components by use of a vapor deposition process, such as atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other similar deposition processes. The technique of forming the low-surface energy organic passivation layer on the surface of a MEMS component is commonly referred to in the art as “vapor lubricant” coating. One serious draw back to using a low-surface energy organic passivation layer, such as self-assembled monolayer (SAM) coatings, is that they typically are on the order of one monolayer thick. Generally, these types of coatings have a very limited usable lifetime, since they are easily damaged or displaced due to impact or wear created by the interaction of the various moving components. This inevitably happens in MEMS devices with contacting surfaces that are subject to frequent contact in use and a large number of contacts during the product lifetime, such as in light modulators and RF switches. Without some way to reliably restore or repair the damaged coatings, stiction occurs, and device failure results. As shown in FIG. 1A, one approach for lubricating MEMS components is to provide a getter 110 within the package 100 (that includes a base 111, a lid 104, and a seal 106) in which an array of MEMS devices 108 resides. FIG. 1B illustrates one conventional package 120 that contains a MEMS device 108 and a getter 110 positioned within the head space 124 of the package 120. The package 120 also contains a package substrate 128, window 126 and spacer ring 125. These two configurations are further described in U.S. Pat. No. 6,843,936 and U.S. Pat. No. 6,979,893, respectively. These conventional devices employ some type of reversibly-absorbing getter to store the lubricant molecules in zeolite crystals or the internal volume of a micro-tube. In these designs, a supply of lubricant is maintained in the getter 110, and an amount of lubricant needed to lubricate the MEMS device 108 is discharged during normal operation. However, adding the reversibly absorbing getter, or reservoirs, to retain the liquid lubricants increases package size and packaging complexity and adds steps to the fabrication process, all of which increase piece-part cost as well as the overall manufacturing cost of MEMS or NEMS devices. Thus, forming a device that uses these techniques generally requires a number of labor-intensive and costly processing steps, such as mixing the getter material, applying the getter material to the device-containing package, curing the getter material, conditioning or activating the getter material, and then sealing the MEMS device and the getter within the sealed package. Particles, moisture, and other contaminants found in our everyday atmospheric environment deleteriously effect device yield of a MEMS fabrication process and the average lifetime of a MEMS device. In an effort to prevent contamination during fabrication, the multiple process steps used to form a MEMS device are usually completed in an ultra-high grade clean room environment, e.g., class 10 or better. Due to the high cost required to produce and maintain a class 10 or better clean room environment, the more MEMS device fabrication steps that require such a clean room environment, the more expensive the MEMS device is to make. Therefore, there is a need to create a MEMS device fabrication process that reduces the number of processing steps that require an ultra-high grade clean room environment. As noted above, in an effort to isolate the MEMS components from the everyday atmospheric environment, MEMS device manufacturers typically enclose the MEMS device within a device package so that a sealed environment is formed around the MEMS device. Conventional device packaging processes commonly require the lubricating materials that are contained within the MEMS device package be exposed to high temperatures during the MEMS device package sealing processes, particularly wafer level hermetic packaging. Typically, conventional sealing processes, such as glass frit bonding or eutectic bonding, require that the MEMS device, lubricants, and other device components are heated to temperatures between about 250° C. to 450° C. These high-bonding temperatures severely limit the type of lubricants that can be used in a device package and also cause the lubricant to evaporate away or break down after a prolonged period of exposure. In addition, lubricant that has evaporated during high temperature bonding processes can later re-condense onto and contaminate sealing surfaces. Therefore, there is also a need for a MEMS device package-fabricating process that eliminates or minimizes the exposure of lubricants to high temperatures during the device fabrication process. SUMMARY OF THE INVENTION The present invention generally relates to a micromechanical device that has an improved usable lifetime due to the presence of one or more channels that contain and deliver a lubricant that can reduce the likelihood of stiction occurring between the various moving parts of the device. A device assembly according to an embodiment of the invention includes a micromechanical device enclosed within a processing region and a lubricant channel formed through at least one interior wall of the processing region to be in fluid communication with the processing region, wherein a substantial length of the lubricant channel extends into said at least one interior wall to be completely enclosed thereby. The volume of the lubricant channel may be between 0.1 nanoliter and 1000 nanoliters. The hydraulic diameter of the lubricant channel may be less than about 1 mm, and a length of the lubricant channel is substantially larger than a hydraulic diameter of the lubricant channel. A device assembly according to another embodiment of the invention comprises a micromechanical device enclosed within a processing region and a lubricant channel formed on at least one interior wall of the processing region, wherein the lubricant channel is in fluid communication with the processing region along the entire length thereof, and the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. Embodiments of the invention also provide a packaged micromechanical device that includes a lid, a base, and an interposer that define a processing region for a micromechanical device, a micromechanical device disposed within the processing region, and a lubricant channel formed through at least one interior wall of the processing region and in fluid communication with the processing region, wherein the lubricant channel is configured so that a lubricant for the micromechanical device is held within the lubricant channel via surface tension of the lubricant against internal surfaces of the lubrication channel. An epoxy layer may be interposed between the lid and the interposer and between the interposer and the base. Typically, a channel inlet that is in fluid communication with the lubrication channel is formed through an exterior wall of the micromechanical device assembly or package. Lubricant is injected into the lubrication channel through this channel inlet. However, when an epoxy layer is used, the lubricant may be injected into the lubricant channel prior to the sealing of the package and the channel inlet becomes no longer necessary. One advantage of the invention is that a reservoir of a lubricating material is formed within a device package so that an amount of “fresh” lubricating material can be delivered to areas where stiction may occur. In one aspect, the lubricating material is contained in one or more microchannels that are adapted to evenly deliver a mobile lubricant to interacting areas of the MEMS device. In another aspect, different lubricant materials can be brought into the device in a sequential manner via one channel, or contained concurrently in separate channels. Consequently, the lubricant delivery techniques described herein more reliably and cost effectively prevent stiction-related device failures relative to conventional lubricant delivery schemes. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. FIG. 1A schematically illustrates a cross-sectional view of a prior art device package containing a getter. FIG. 1B schematically illustrates a cross-sectional view of another prior art device package containing a getter. FIG. 2A illustrates a cross-sectional view of a device package assembly, according to one embodiment of the invention. FIG. 2B schematically illustrates a cross-sectional view of a single mirror assembly, according to one embodiment of the invention. FIG. 2C schematically illustrates a cross-sectional view of a single mirror assembly in a deflected state, according to one embodiment of the invention. FIG. 3A illustrates a cross-sectional plan view of a device package assembly, according to one embodiment of the invention. FIGS. 3B and 3C illustrate close-up views of a partial section and a lubricant channel in FIG. 3A, according to one embodiment of the invention. FIG. 3D illustrates a lubricant channel that has a volume of lubricant disposed therein to provide a ready supply of lubricant to a processing region, according to one embodiment of the invention. FIG. 3E illustrates a cross-sectional plan view of a device package assembly, according to one embodiment of the invention. FIG. 3F illustrates a cross-sectional plan view of a device package assembly having channels inside the processing region of the device package assembly, according to one embodiment of the invention. FIG. 3G illustrates a cross-sectional plan view of a device package assembly having lubricant-containing channels on an interior wall of the processing region, according to one embodiment of the invention. FIGS. 4A-C illustrate process sequences for forming a MEMS device package that includes lubrication channels, according to embodiments of the invention. FIGS. 5A-5P illustrate the various states of one or more of the components of a MEMS device package after performing each step in the process sequences illustrated in FIGS. 4A, 4B and 4C. FIG. 6A illustrates a cross-sectional plan view of a device package assembly after performing multiple steps in the process sequence illustrated in FIG. 4A, according to one embodiment of the invention. FIGS. 6B and 6C illustrate a channel inlet formed into a lubricant channel, according to embodiments of the invention. FIG. 6D illustrates a cross-sectional plan view of a device package assembly after a lubricant has been drawn into a lubricant channel, according to an embodiment of the invention. FIG. 6E illustrates a cap is installed over a channel inlet to seal a lubricant channel, according to an embodiment of the invention. FIGS. 6F and 6G illustrate methods of sealing a lubricant channel using an IR laser, according to embodiments of the invention. FIG. 7A illustrates a cross-sectional plan view of a device package assembly, according to one embodiment of the invention. FIG. 7B illustrates a close-up of a partial section view of a device package assembly, according to one embodiment of the invention. FIG. 7C illustrates a close-up of a partial section view of a device package assembly, according to one embodiment of the invention; FIG. 7D illustrates a close-up of a partial section view illustrated in FIG. 7C, according to one embodiment of the invention; FIG. 7E illustrates a close-up of a partial section view of a device package assembly, according to one embodiment of the invention; FIG. 8 illustrates a close-up of a partial section view of a device package assembly, according to one embodiment of the invention; FIGS. 9A and 9B illustrate a close-up of a partial section view of a device package assembly, according to one embodiment of the invention. FIG. 10A is a plan view of a MEMS device package having a lubricant channel formed with a particle trap, according to an embodiment of the invention. FIG. 10B is a plan view of a MEMS device package having a lubricant channel formed with a non-linear particle trap, according to an embodiment of the invention. For clarity, identical reference numbers have been used, where applicable, to designate identical elements that are common between figures. It is contemplated that features of one embodiment may be incorporated in other embodiments without further recitation. DETAILED DESCRIPTION The present invention generally relates to a micromechanical device that has an improved usable lifetime due to the presence of one or more channels that contain and deliver a lubricant that can reduce the likelihood of stiction occurring between the various moving parts of the device. Embodiments of the present invention include an enclosed device package, and a method of forming the same, where the enclosed device package has one or more lubricant-containing channels for delivering lubricant to a MEMS device disposed within the enclosed region of the device package. The one or more lubricant-containing channels act as a ready supply of fresh lubricant to prevent stiction between interacting components of the device disposed within the enclosed region of the device package. This supply of fresh lubricant may also be used to replenish damaged lubricants (worn-off, broken down, etc.) between various contacting surfaces. In one example, aspects of this invention may be especially useful for fabricating micromechanical devices, such as MEMS devices, NEMS devices, or other similar thermal or fluidic devices. In one embodiment, the amount and type of lubricant disposed within the channel is selected so that fresh lubricant can readily diffuse or be transported in a gas or vapor phase to all areas of the processing region to reduce the chances of stiction-related failure. In another embodiment, the lubricant and the surfaces of walls of the processing region, in particular the wettability of the surfaces, are selected so that fresh lubricant is transported in a liquid phase onto surfaces of walls of the processing region via capillary forces, and subsequently released to the internal region of the device as molecules or molecular vapor. One of skill in the art recognizes that the term lubricant, as used herein, is intended to describe a material adapted to provide lubrication, anti-stiction, and/or anti-wear properties to contact surfaces. In addition, the term lubricant, as used herein, is generally intended to describe a lubricant that is in a liquid, vapor and/or gaseous state during the operation and storage of a MEMS device. Aspects of the present invention take advantage of characteristics of the microfluidics. In particular, microchannels or lubricant channels are configured in view of the lubricant material to be used so that capillary forces can be used to manipulate liquid lubricants into one or more lubricant channels that are in fluid communication with a process region of a MEMS device. The lubricant channel has at least two types of applications. The first application is to serve as a storage for the lubricants for lifetime use of the MEMS device. The second application is to provide a controllable way to deliver lubricants into the process region in a well-controller manner. In certain cases, simple external mechanical pressure from a pipette or a pump, for example, may be used alone, or in conjunction with the capillary forces to manipulate liquid lubricants into the lubricant channels. Overview of Exemplary System In an effort to prevent contamination from affecting the longevity of MEMS or NEMS components, these devices are typically enclosed within an environment that is isolated from external contamination, such as particles, moisture, or other foreign material. FIG. 2A illustrates a cross-sectional view of a typical MEMS device package 230 that contains a MEMS device 231 enclosed within a processing region 234 formed between a lid 232, interposer 235 and a base 233. Typically, the lid 232, interposer 235 and base 233 are all hermetically or non-hermetically sealed so that the components within the processing region 234 are isolated from external contamination that may interfere with the use of the device. FIG. 2B illustrates a representative micromechanical device that may be formed within the MEMS device 231 of FIG. 2A, which is used herein to describe various embodiments of the invention. The device shown in FIG. 2B schematically illustrates a cross-sectional view of a single mirror assembly 101 contained in a spatial light modulator (SLM). One should note that the MEMS device shown in FIG. 2B is not intended in any way to limit the scope of the invention described herein, since one skilled in the art would appreciate that the various embodiments described herein could be used in other MEMS, NEMS, larger scale actuators or sensors, or other comparable devices that experience stiction or other similar problems. While the discussion below specifically discusses the application of one or more of the various embodiments of the invention using a MEMS or NEMS type of device, these configurations also are not intended to be limiting as to the scope of the invention. In general, a single mirror assembly 101 may contain a mirror 102, base 103, and a flexible member 107 that connects the mirror 102 to the base 103. The base 103 is generally provided with at least one electrode (elements 106A or 106B) formed on a surface 105 of the base 103. The base 103 can be made of any suitable material that is generally mechanically stable and can be formed using typical semiconductor processing techniques. In one aspect, the base 103 is formed from a semiconductor material, such as a silicon-containing material, and is processed according to standard semiconductor processing techniques. Other materials may be used in alternative embodiments of the invention. The electrodes 106A, 106B can be made of any materials that conduct electricity. In one aspect, the electrodes 106A, 106B are made of a metal (e.g., aluminum, titanium) deposited on the surface 105 of the base 103 and etched to yield desired shape. A MEMS device of this type is described in the commonly assigned U.S. patent application Ser. No. 10/901,706, filed Jul. 28, 2004. The mirror 102 generally contains a reflective surface 102A and a mirror base 102B. The reflective surface 102A is generally formed by depositing a metal layer, such as aluminum or other suitable material, on the mirror base 102B. The mirror 102 is attached to the base 103 by a flexible member 107. In one aspect, the flexible member 107 is a cantilever spring that is adapted to bend in response to an applied force and to subsequently return to its original shape after removal of the applied force. In one embodiment, the base 103 is fabricated from a first single piece of material, and the flexible member 107 and the mirror base 102B are fabricated from a second single piece of material, such as single crystal silicon. Importantly, the use of any device configuration that allows the surface of one component (e.g., mirror 102) to contact the surface of another component (e.g., base 103) during device operation, thereby leading to stiction-related problems, generally falls within the scope of the invention. For example, a simple cantilever beam that pivots about a hinge in response to an applied force such that one end of the cantilever beam contacts another surface of the device is within the scope of the invention. In one aspect, one or more optional landing pads (elements 104A and 104B in FIG. 2B) are formed on the surface 105 of the base 103. The landing pads are formed, for example, by depositing a metal layer containing aluminum, titanium nitride, tungsten or other suitable materials. In other configurations, the landing pads may be made of silicon (Si), polysilicon (poly-Si), silicon nitride (SiN), silicon carbide (SiC), diamond like carbon (DLC), copper (Cu), titanium (Ti) and/or other suitable materials. FIG. 2C illustrates the single mirror assembly 101 in a distorted state due to the application of an electrostatic force FE created by applying a voltage VA between the mirror 102 and the electrode 106A using a power supply 112. As shown in FIG. 2C, it is often desirable to bias a landing pad (e.g., elements 104A) to the same potential as the mirror 102 to eliminate electrical breakdown and electrical static charging in the contacting area relative to mirror 102. During typical operation, the single mirror assembly 101 is actuated such that the mirror 102 contacts the landing pad 104A to ensure that a desired angle is achieved between the mirror 102 and the base 103 so that incoming optical radiation “A” is reflected off the surface of the mirror 102 in a desired direction “B.” The deflection of the mirror 102 towards the electrode 106A due to the application of voltage VA creates a restoring force (e.g., moment), due to the bending of the flexible member 107. The magnitude of the restoring force is generally defined by the physical dimensions and material properties of the flexible member 107, and the magnitude of distortion experienced by the flexible member 107. The maximum restoring force is typically limited by the torque applied by the electrostatic force FE that can be generated by the application of the maximum allowable voltage VA. To assure contact between the mirror 102 and the landing pad 104A the electrostatic force FE must be greater than the maximum restoring force. As the distance between the mirror 102 and the landing pad 104A decreases, the interaction between the surfaces of these components generally creates one or more stiction forces that acts on the mirror 102. When the stiction forces equal or exceed the restoring force, device failure results, since the mirror 102 is prevented from moving to a different position when the electrostatic force generated by voltage VA is removed or reduced. As previously described herein, stiction forces are complex surface phenomena that generally include three major components. The first is the so-called “capillary force” that is created at the interface between a liquid and a solid due to an intermolecular force imbalance at the surface of a liquid (e.g., Laplace pressure differences) that generates an adhesive-type attractive force. Capillary force interaction in MEMS and NEMS devices usually occurs when a thin layer of liquid is trapped between the surfaces of two contacting components. A typical example is the water vapor in the ambient. The second major component of stiction forces is the Van der Waal's force, which is a basic quantum mechanical intermolecular force that results when atoms or molecules come very close to one another. When device components contact one another, Van der Waal's forces arise from the polarization induced in the atoms of one component by the presence of the atoms of the second component. When working with very planar structures, such as those in MEMS and NEMS devices, these types of stiction forces can be significant due to the size of the effective contact area. The third major component of stiction forces is the electrostatic force created by the coulombic attraction between trapped charges found in the interacting components. Device Package Configurations FIG. 3A is a plan view of the MEMS device package 230 illustrated in FIG. 2A having a microfluidic channel or lubricant channel 301 formed in the MEMS device package 230. For clarity, MEMS device package 230 is illustrated with a partial section 391 of lid 232 removed. The lubricant channel 301 is a microchannel, i.e., a conduit with a hydraulic diameter of a few micrometers to less than about 1 mm, and may be formed in any one of the walls that enclose the processing region 234. In one embodiment, as shown in FIG. 3A, the lubricant channel 301 is formed in the interposer 235 just below the lid 232. Alternatively, lubricant channel 301 may be formed in the lid 232 or in the base 233 of MEMS device package 230. In one embodiment, the lubricant channel 301 extends from an interior surface 235B of one of the walls that encloses the processing region 234 to a channel inlet 302 (see FIG. 3B). The channel inlet 302 penetrates an exterior surface 235A to allow the introduction of one or more lubricants into the lubricant channel 301. In alternative embodiments, the lubricant channel 301 does not extend to an exterior surface (see FIG. 5L) and may be formed on one of the walls that enclose the processing region 234 (see FIG. 3G). To prevent ingress of particles, moisture, and other contamination into the processing region 234 and lubricant channel 301 from the outside environment, lubricant channel 301 is configured so that it is sealed from the outside environment. In one embodiment, channel inlet 302 is sealed with a closure 302A after a lubricant (not shown for clarity) is introduced into lubricant channel 301, as illustrated in FIG. 3B. Methods for forming closure 302A to seal channel inlet 302 according to this embodiment are described below in conjunction with FIGS. 6F and 6G. In another embodiment, a cap 304 is positioned over the channel inlet 302 after lubricant channel 301 is filled with lubricant, as shown in FIG. 3C. The cap 304 may be a polymer, such as epoxy or silicone, or other solid material that is bonded to the exterior surface 235A using conventional sealing techniques. In one aspect, cap 304 is a plug of material that is positioned inside the channel inlet 302 after lubricant channel 301 is filled with lubricant. The plug of material sealing channel inlet 302 may be an indium metal plug, which may be applied as a molten solder droplet to channel inlet 302 without the use of flux, a potential contaminant. This is because indium alloys with silicon and therefore wets exterior surface 235A and channel inlet 302. The plug of material sealing channel inlet 302 may also include a hydrophobic, high-vacuum grease, such as Krytox®. The lubricant channel 301 is adapted to contain a desired amount of a lubricant (not shown) that vaporizes or diffuses into the processing region 234 over time. The rate at which the lubricant migrates into the processing region is affected by a number of factors, including the geometry of the lubricant channel 301, lubricant molecular weight, bond strength of the lubricant to processing region surfaces (e.g., via physisorption, chemisorption), capillary force created by the surface tension of the lubricant against internal surfaces of the lubrication channel 301, lubricant temperature, and pressure of the volume contained within the processing region 234. In one embodiment, lubricant channel 301 is adapted to contain a volume of lubricant between about 0.1 nanoliters (nl) and about 1000 nl. Referring to FIG. 3B, the volume of the lubricant channel 301 is defined by the formed length times the cross-sectional area of the lubricant channel 301. The length of the lubricant channel 301 is the channel length extending from the exterior surface 235A to the interior surface 235B, i.e., the sum of the length of segments A, B and C, as shown in FIG. 3B. The channel length is between 10 micrometers to 1 mm. In one aspect, the cross-section of lubricant channel 301 is rectangular and the cross-sectional area (not shown) is defined by the depth (not shown) and the width W of the lubricant channel 301. In one embodiment, the width W of the lubricant channel 301 is between about 10 micrometers (μm) and about 800 μm and the depth is between about 10 micrometers (μm) and about 200 μm. The cross-section of the lubricant channel 301 need not be square or rectangular, and can be any desirable shape without varying from the basic scope of the invention. FIG. 3D illustrates a lubricant channel 301 that has a volume of lubricant 505 disposed therein to provide a ready supply of lubricant to the processing region 234. During normal operation of the MEMS device 231, molecules of the lubricant tend to migrate to all areas within the processing region 234. The continual migration of the lubricant 505 to the areas of the MEMS device 231 where stiction may occur is useful to prevent stiction-related failures at contact regions between two interacting MEMS components. As lubricant molecules breakdown at the contact regions and/or adsorb onto other surfaces within the processing region 234 during operation of the MEMS device 231, fresh lubricant molecules from lubricant channel 301 replace the broken-down or adsorbed lubricant molecules, thereby allowing the lubricant 505 in the lubricant channel 301 to act as a lubricant reservoir. The movement or migration of molecules of the lubricant 505 is generally performed by two transport mechanisms. The first mechanism is a surface diffusion mechanism, where the lubricant molecules diffuse across the internal surfaces of processing region 234 to reach the contact region between two interacting MEMS components. In one aspect, the lubricant 505 is selected for good diffusivity over the surfaces contained within the processing region 234. The second mechanism is a vapor phase, or gas phase, migration of the lubricant 505 stored in lubricant channel 301 to the contact region between two interacting MEMS components. In one aspect, the lubricant 505 stored in the lubricant channels 301 of the device package is selected so that molecules of lubricant 505 desorb from these areas and enter into the process region 234 as a vapor or gas. During operation of the device, the lubricant molecules reach an equilibrium partial pressure within processing region 234 and then, in a vapor or gaseous state, migrate to an area between the interacting surfaces of process region 234 and MEMS device 231. Since these two types of transport mechanisms aid in the build-up of a lubricant layer, thereby reducing the interaction of moving MEMS components, the act of delivering lubricant to an exposed region of the MEMS device is generally referred to hereafter as “replenishment” of the lubricant layer, and a lubricant delivered by either transport mechanism is referred to as a “mobile lubricant.” Generally, a sufficient amount of replenishing lubricant molecules are stored inside the lubricant channel 301 so that the sufficient lubricant molecules are available to prevent stiction-induced failures at the interacting areas of the MEMS device during the entire life cycle of the product. In one embodiment, illustrated in FIG. 3E, the size of the lubricant channel 301 is selected and the internal surface 234A is selectively treated, so that the surface tension of a liquid lubricant 505 against the surfaces of the lubricant channel 301 and the internal surface 234A causes the lubricant 505 to be drawn from a position outside of the MEMS device package 230 into lubricant channel 301 and then into the processing region 234. In this way, the lubricant channel 301 acts as a liquid injection system that allows the user to deliver an amount of the lubricant 505 into the processing region 234, by use of capillary forces created when the lubricant 505 contacts the walls of the lubricant channel 301. In one example, the cross-section of lubricant channel 301 is rectangular, and the width of the lubricant channel 301 is between about 100 micrometers (μm) and about 600 μm, and the depth is between about 100 μm±50 μm. When in use, capillary forces can deliver an amount of lubricant 505 to the processing region 234 that is smaller or larger than the volume of the lubricant channel 301. In this configuration it may be possible to sequentially deliver different volumes of two or more different lubricants through the same lubricant channel 301. Alternatively, a first lubricant may be transmitted through the lubricant channel 301 and then a second lubricant is retained in the lubricant channel 301 in a subsequent step. In another embodiment, the lubricant 505 is selected so that a portion of the lubricant 505 vaporizes to form a vapor or gas within the processing region during normal operation of the device. In cases where the MEMS device is a spatial light modulator (SLM), typical device operating temperatures may be in a range between about 0° C. and about 70° C. The ability of the lubricant to form a vapor or gas is dependent on lubricant equilibrium partial pressure, which varies as a function of the temperature of the lubricant, the pressure of the region surrounding the lubricant, lubricant bond strength to internal surfaces of the processing region 234, and lubricant molecular weight. In another embodiment, the lubricant 505 is selected due to its ability to rapidly diffuse along the surfaces within the processing region 234. In this embodiment, internal surfaces 234B of the processing region 234 and/or the lubricant channel 301 may be treated to act as wetting surfaces for the lubricant 505, as illustrated in FIG. 3F. In this way, the lubricant 505 is brought into processing region 234 in a liquid form to act as a reservoir of mobile lubricant for MEMS device package 230 throughout the MEMS device lifetime. To prevent interference with contact surfaces within the processing region 234, selected areas of internal surfaces 234C of processing region 234 may be treated to act as non-wetting surfaces for the lubricant 505. In this way, a liquid reservoir of mobile lubricant is formed in processing region 234 with no danger of interfering with components of MEMS device 231. In one aspect, channels or grooves 234D are formed in one or more internal surfaces of the processing region 234 to better retain lubricant 505, as shown in FIG. 3G. In another embodiment, the lubricant 505 is adapted to operate at a temperature that is within an extended operating temperature range, which is between about 0° C. and about 70° C. In yet another embodiment, the lubricant is selected so that it will not decompose when the device is exposed to temperatures that may be experienced during a typical MEMS or NEMS packaging process, i.e., between about −30° C. and about 400° C. Examples of lubricants 505 that may be disposed within a lubricant channel 301 and used to prevent stiction of the interacting components within a MEMS device are perfluorinated polyethers (PFPE), self assembled monolayer (SAM) or other liquid lubricants. Some known types of PFPE lubricants are Y or Z type lubricants (e.g., Fomblin® Z25) available from Solvay Solexis, Inc. of Thorofare, N.J., Krytoxe from DuPont, and Demnum® from Daikin Industries, LTD. Examples of SAM include dichlorodimethylsilane (“DDMS”), octadecyltrichlorosilane (“OTS”), perfluoroctyltrichlorsilane (“PFOTCS”), perfluorodecyl-trichlorosilane (“FDTS”), fluoroalkylsilane (“FOTS”). In alternative embodiments, it may be desirable to modify the properties of the surfaces within the lubricant channel 301 to change the lubricant bond strength to surfaces with the internal region 305, shown in FIG. 3B, of the lubricant channel 301. For example, it may be desirable to coat the surfaces of the lubricant channel 301 with an organic passivating material, such as a self-assembled-monolayer (SAM). Useful SAM materials include, but are not limited to, organosilane type compounds such as octadecyltrichlorosilane (OTS), perfluorodecyltrichlorosilane (FDTS). The surfaces of the lubricant channel 301 may also be modified by exposing them to microwaves, UV light, thermal energy, or other forms of electromagnetic radiation to alter the properties of the surface of the lubricant channel 301. As noted above, conventional techniques that require the addition of a reversibly absorbing getter to MEMS device package to retain a lubricant substantially increase the device package size and the complexity of forming the device, and also add steps to the fabrication process. Such device package designs have an increased piece-part cost and an increased overall manufacturing cost, due to the addition of extra getter components. Therefore, by disposing a mobile lubricant in a lubricant channel formed in or on one or more of the walls enclosing the processing region, an inexpensive and reliable MEMS device can be formed. The use of the lubricant channel 301 eliminates the need for a reversibly adsorbing getter and thus reduces the device package size, the manufacturing cost, and the piece-part cost. The embodiments described herein also improve device reliability by reducing the likelihood that during operation additional components positioned within the processing region, such as getter materials, contact the moving or interacting MEMS components within the device package. Lubricant Channel Formation Process According to embodiments of the invention, a lubricant channel similar to lubricant channel 301 of MEMS device package 230 can be formed in one or more of the walls of an enclosure containing a MEMS or any other stiction-sensitive device. Typically, MEMS devices are enclosed in a MEMS device package 230, as illustrated above in FIG. 2A, using a chip-level or wafer-level packaging process. An example of a chip-level packaging process can be found in U.S. Pat. No. 5,936,758 and U.S. Patent Publication No. 20050212067. The process sequence discussed below can also be applied to wafer-level hermetic packaging, in which a plurality of MEMS devices are packaged simultaneously by aligning and assembling a number of silicon and glass wafers into a stack. For example, a plurality of MEMS device packages substantially similar to MEMS device 230 may be formed via wafer-level hermetic packaging by using a base 233 from which the MEMS device packages 230 will be formed. A plurality of MEMS devices 231 may be formed on the base 233 or individually bonded to the base 233. The sealed MEMS devices 230 can be formed by bonding the base 233, an interposer wafer, and a glass wafer. The individual MEMS device packages are then formed by singulating the bonded wafer stack by dicing, laser cutting or other methods of die separation. The remaining packaging assembly and testing processes following wafer-level hermetic packaging and die singulation do not require an ultra-high clean room environment and hence reduce the overall packaging cost to manufacture a device. In addition, embodiments of the invention described below have a particular advantage over conventional MEMS device packaging processes, since they eliminate the requirement that the MEMS device lubricant be exposed to a high temperature during the steps used to form the sealed processing region 234. While the discussion below focuses on a wafer-level packaging method, the techniques and general process sequence need not be limited to this type of manufacturing process. Therefore, the embodiments of the invention described herein are not intended to limit the scope of the present invention. Examples of MEMS device packages and processes of forming the MEMS device packages that may benefit from one or more embodiments of the invention described herein are further described in the following commonly assigned U.S. patent application Ser. No. 10/693,323, Attorney Docket No. 021713-000300, filed Oct. 24, 2003, U.S. patent application Ser. No. 10/902,659, Attorney Docket No. 021713-001000, filed Jul. 28, 2004, and U.S. patent application Ser. No. 11/008,483, Attorney Docket No. 021713-001300, filed Dec. 8, 2004. FIG. 4A illustrates a process sequence 400 for forming a MEMS device package 230 that includes lubrication channels 301, according to one embodiment of the invention. FIGS. 5A-5F illustrate the various states of one or more of the components of the MEMS device package 230 after each step of process sequence 400 has been performed. FIG. 5A is a cross-sectional view of a wafer 235C that may be used to form the multiple MEMS device packages 230, as shown in FIG. 5F. The wafer 235C may be formed from a material such as silicon (Si), a metal, a glass material, a plastic material, a polymer material, or other suitable material. Referring now to FIGS. 4A and 5B, in step 450, conventional patterning, lithography and dry etch techniques are used to form the lubricant channels 301 and the optional depressions 401 on a top surface 404 of the wafer 235C. The depth D of the lubricant channels 301 and the depressions 401 are set by the time and etch rate of the conventional dry etching process performed on the wafer 235C. It should be noted that the lubricant channels 301 and depressions 401 may be formed by other conventional etching, ablation, or other manufacturing techniques without varying from the scope of the basic invention. Referring now to FIGS. 4A and 5C, in step 452, conventional patterning, lithography and dry etch techniques are used to remove material from the back surface 405 through the base wall 403 of the depressions 401 to form a through hole 402 that defines the interior surface 235B. Interior surface 235B, together with the lid 232 and the base 233 (shown in FIGS. 5E-5F), defines processing region 234 of MEMS device package 230. The process of removing material from the wafer 235C to form the through hole 402 may also be performed by conventional etching, ablation, or other similar manufacturing techniques. Alternatively, the wafer 235C may be formed with the through holes 402 in a previous step. In step 454, as shown in FIGS. 4A and 5D, the lid 232 is bonded to the top surface 404 of the wafer 235C to enclose the lubricant channels 301 and cover one end of each through hole 402. Typical bonding processes may include anodic bonding (e.g., an electrolytic process), eutectic bonding, fusion bonding, covalent bonding, and/or glass frit fusion bonding processes. In one embodiment, the lid 232 is a display grade glass material (e.g., Corning® Eagle 2000™) and the wafer 235C is a silicon-containing material, and the lid 232 is bonded to the wafer 235C by use of a conventional anodic bonding technique. Typically the temperature of one or more of the components in the MEMS device package reaches between about 350° C. and about 450° C. during a conventional anodic bonding process. Additional information related to the anodic bonding process is provided in the commonly assigned U.S. patent application Ser. No. 11/028,946, filed on Jan. 3, 2005, which is herein incorporated by reference in its entirety. In step 456, as shown in FIGS. 4A and 5E, the base 233, which has a plurality of MEMS devices 231 mounted thereon, is bonded to the back surface 405 of the wafer 235C to form an enclosed processing region 234 in which the MEMS device 231 resides. Typically, the base 233 is bonded to the wafer 235C using an anodic bonding (e.g., an electrolytic process), eutectic bonding, fusion bonding, covalent bonding, and/or glass frit fusion bonding process. In one embodiment, the base 233 is a silicon-containing substrate and wafer 235C is a silicon-containing wafer, and base 233 is bonded to the wafer 235C using a glass frit bonding process. Typically, the temperature of at least one or more of the components in the MEMS device package reaches a temperature between about 350° C. and about 450° C. during a glass frit bonding process. Additional information related to the glass frit bonding process is provided in the commonly assigned U.S. patent application Ser. No. 11/028,946, filed on Jan. 3, 2005, which has been incorporated by reference in its entirety. Referring now to FIGS. 4A and 5F, in step 458, the wafer stack consisting of base 233, wafer 235C, and lid 232, is separated by use of a conventional dicing technique to form multiple MEMS device packages 230. The excess or scrap material 411, which is left over after the dicing process, may then be discarded. As part of step 458, conventional wire bonding and testing can be performed on the formed MEMS device to assure viability thereof and prepare the MEMS device for use in a system that may utilize the MEMS device package 230. Other dicing techniques can also be used to first expose the bond pads to allow wafer level probing and die sorting, followed by a full singulation. FIG. 6A is a plan view of a MEMS device package 230 having a partially formed lubricant channel 301 that may be formed using process steps 450 through step 458 shown in FIG. 4A. For clarity, MEMS device package 230 is illustrated with a partial section 601 of lid 232 removed. As shown, the lubricant channel 301 is only partially formed in the interposer 235 so that the end of the lubricant channel 301 proximate the exterior surface 235A is blocked by an excess interposer material 501 having a material thickness 502. In general, the material thickness 502 can be relatively thin to allow for easy removal of the excess interposer material 501 and may be about 10 micrometers (μm) to about 1 mm in thickness. In this configuration, the lubricant channel 301 is formed to extend from the exit port 303, which penetrates the interior surface 235B, to the opposing end, which is blocked by the excess interposer material 501. In this way, the processing region 234 remains sealed until the excess interposer material 501 is removed for injection of lubricant into the lubricant channel 301 during step 460 of FIG. 4A as described below. In step 460 of the process sequence 400, a channel inlet 302 is formed into the lubricant channel 301, as illustrated in FIGS. 6B and 6C. The channel inlet 302 may be formed by a step of puncturing the excess interposer material 501, as illustrated in FIG. 6B. Alternatively, the channel inlet 302 may be formed by performing a conventional abrasive, grinding, or polishing technique to remove substantially all of the excess interposer material 501 to expose the lubricant channel 301, as illustrated in FIG. 6C. In one aspect, it may be desirable to clean and remove any particles from the lubricant channel 301 created when the excess interposer material is removed to assure that particles cannot make their way into the processing region 234. Because the precision with which the excess interposer material 501 of the MEMS device package 230 can be removed is limited, a thickness control aperture 503 may be formed proximate the lubricant channel 301 during the formation of lubricant channel 301, as shown in FIG. 6A. During the process step of 458, materials on the right side of the aperture 503 is removed to expose the aperture 503. The presence of thickness control aperture 503 allows for a variation 504 (see FIG. 6A) in the removal of excess interposer material 501 without affecting material thickness 502. In one embodiment, as illustrated in FIG. 6B, the channel inlet 302 is created by delivering energy, such as a laser pulse or an electron-beam pulse, to drill a hole through the excess interposer material 501 and into the lubricant channel 301. Laser drilling of channel inlet 302 may be performed using a short-pulse laser, such as an ultraviolet (UV) laser, or a long-pulse laser, such as an infra-red (IR) laser or constant (CW) laser. For example, when excess interposer material 501 is a silicon-containing material and material thickness 502 is about 100 to 200 μm thick, a Rofin 20E/SHG 532 nm Q-switch laser may be used. In this case, average power setting for the drilling process is between about 1.0 and about 2.5 W, approximately 3000 to 6000 pulses are used (depending on the exact thickness and composition of excess interposer material 501), Q switch frequency is less than about 15000 Hz, and pulse width is between about 6 ns and 18 ns. Alternatively, an IR laser may be used for laser drilling to form channel inlet 302, such as a 20 W fiber laser having a laser wavelength of 1.06 μm. In this case, between about 2,000 and 10,000 pulses are delivered, depending on the exact value of material thickness 502, and the pulses are delivered at a frequency between 25 kHz and 40 kHz. It is believed that the use of an IR laser versus a UV laser will reduce the number of particles produced during the drilling process due to the higher absorption of the energy at these wavelengths, which causes the heated material to form a liquid that will tend to adhere to the internal surfaces of the lubricant channel 301. Therefore, use of an IR laser can result in significant reduction in particulate contamination formed in the lubricant channel 301 and/or the processing region 234. The inventors have also determined that particle generation during IR laser drilling can be minimized by optimizing settings of the laser. For example, when excess interposer material 501 is a silicon-containing material and material thickness 502 is about 100 to 200 μm thick, particle generation can also be minimized by adjusting the IR laser to form channel inlet 302 with a diameter between about 10 μm and about 30 μm. In addition, to minimize oxidation of the excess interposer material 501 during the laser drilling of step 460, the laser drilling process may be performed in an oxygen-free environment. For example, step 460 may take place in a chamber filled with an inert gas, e.g., nitrogen, or a noble gas, e.g., argon. Alternatively, the inert gas or noble gas may be used as a localized purge gas shield. In one embodiment, the processing region 234 is filled with a gas during the formation of MEMS device package 230 to a pressure that is greater than atmospheric pressure so that any particles created during the removal of the excess interposer material 501 are urged away from the processing region 234 by the escaping gas. In one aspect, the processing region 234 is filled with a gas to a pressure higher than atmospheric pressure during step 456, i.e., the process of bonding the base 233 to the back surface 405 of the wafer 235C. In this case, the environment in which step 456 is performed is maintained at a pressure higher than atmospheric pressure so that higher than atmospheric pressure gas is trapped in the processing region 234 when fully formed. The gas retained in the processing region 234 may be an inert gas, such as nitrogen or argon. In another embodiment, the device is placed in an o-ring sealed container with a transparent wall to allow the penetration of a UV or IR laser beam. The container is evacuated to a vacuum pressure in the millitorr regime prior to laser drilling to form channel inlet 302. The large pressure difference between the processing region 234 and the evacuated chamber further suppress the ingress of particles produced by laser drilling into the lubricant channel 301 during the formation of channel inlet 302. The container and the device are subsequently back-filled with desired gases, such as dry nitrogen or argon, prior to removing the device from the sealed container. Referring to FIG. 4A, in step 461, one or more lubricants are introduced into lubricant channel 301. As noted above in conjunction with FIG. 3E, lubricant channel 301 and channel inlet 302 may be configured so that capillary force draws the lubricant 505 into lubricant channel 301A, as illustrated in FIG. 6D. Hence, lubricant channel 301 may be filled with the lubricant 505 by placing a suitable quantity of lubricant 505 adjacent the channel inlet 302 on the exterior surface 235A with a syringe, pipette, or other similar device. Referring to FIG. 4A, in step 462, channel inlet 302 is sealed to isolate the lubricant channel 301, the processing region 234, and the lubricant 505 disposed therein from the environment external to the MEMS device package 230. In one embodiment, a cap 304 is installed over the channel inlet 302 to seal lubricant channel 301, as illustrated in FIG. 6E. The composition of cap 304 is described above in conjunction with FIG. 3C. In another embodiment, a spot welding method, such as laser welding, may be used to seal channel inlet 302. In one aspect, a long-pulse laser or continuous laser, such as an IR laser, is used for this process. To minimize production costs, an IR laser substantially similar to the laser used in step 460, i.e., the step of forming channel inlet 302 through excess interposer material 501, may also be used in step 462, i.e., the step of sealing lubricant channel 301. For example, when excess interposer material 501 is a silicon-containing material and channel inlet 302 has a diameter of between about 10 μm and about 30 μm, a Rofin StarWeld 40 having a laser wavelength of 1.06 μm may be used in single pulse mode to seal channel inlet 302 with a pulse width of about 1 ms, an energy of between about 0.1 and 0.6 J, and a spot size between about 100 μm and 400 μm. FIG. 6F illustrates a method of sealing lubricant channel 301 according to one embodiment, using an IR laser, wherein a laser is used to heat an area that is adjacent to the channel inlet 302, and thus some of the excess interposer material 501 is melted and is pushed over channel inlet 302. In this embodiment, a weld puddle 520 is formed on the exterior surface 235A with an IR or other long-pulse laser, and a portion 521 of the weld puddle 520 is displaced over channel inlet 302, thereby sealing lubricant channel 301. FIG. 6G illustrates another method of sealing lubricant channel 301 with an IR laser according to an embodiment, wherein one or more laser pulses are used to heat areas on the exterior surface 235A to create one or more seals 522 inside the lubricant channel 301. In this embodiment, one or more weld puddles 523 are formed in a sealing region 524 with sufficient energy to seal the lubricant channel 301 internally as shown. The geometry of lubricant channel 301 may be configured in weld region 524 to ensure that weld puddles 523 completely seal lubricant channel 301 from the ambient environment. For example, the portion of lubricant channel 301 corresponding to the location of weld puddles 523 may be positioned closer to exterior surface 235A and/or may be formed substantially narrower than the remaining portions of lubricant channel 301. Using weld puddles 523 to seal lubricant channel 301 as illustrated in FIG. 6G can minimize the amount of oxidized material that is contained in the seal. FIG. 4B illustrates a process sequence 410 for forming a MEMS device package 230 that contains a lubricant channel 301, according to one embodiment of the invention. Steps 450 and 452 in process sequence 410 are substantially the same as steps 450 and 452 in process sequence 400, and are described above in conjunction with FIGS. 4A, 5A, 5B, and 5C. Referring now to FIG. 4B, in step 494, a lid 432 with a plurality of channel inlets 302 is aligned with and bonded to the top surface 404 of the wafer 235C to enclose the lubricant channels 301 and cover one end of each through hole 402, as illustrated in FIG. 5G. FIG. 5G is a cross-sectional view of the wafer 235C and the lid 432 after bonding. Step 494 is substantially similar to step 454 of process sequence 410, except that the lid 432 includes a plurality of channel inlets 302 positioned to align with a portion of each lubricant channel 301 formed in the wafer 235C. Alternatively, the channel inlets 302 may be formed in the lid 432 after the lid 432 is bonded to the wafer 235C. In this case, the channel inlets 302 may be formed via lithographic, ablation, and/or etching techniques commonly known and used in the art. In either case, formation or alignment of the channel inlets 302 is part of the wafer-level process. As noted above, wafer-level processes generally reduce the cost to manufacture a device compared to chip-level processes. In step 496, as shown in FIGS. 4B and 5H, the base 233, which has a plurality of MEMS devices 231 mounted thereon, is bonded to the back surface 405 of the wafer 235C to form an enclosed processing region 234 in which the MEMS device 231 resides. Step 496 is substantially similar to step 456 of process sequence 400 in FIG. 4A. In step 498, as shown in FIGS. 4B and 5I, lubricant 505 is introduced into each lubricant channel 301 in a wafer-level process. In this embodiment, it is not necessary to dice the wafer stack consisting of the base 233, the wafer 235C, and the lid 232 into multiple MEMS device packages 230 prior to introducing the lubricant 505 into lubricant channels 301. Instead, a suitable quantity of the lubricant 505 may be placed adjacent to each opening in the channel inlet 302 on the upper surface 432A of the lid 432 by use of a syringe, pipette, or other similar device, and using capillary forces draw the lubricant 505 into each lubricant channel 301. In this way, the number of chip-level fabrication steps required to produce the MEMS device packages 230 is minimized. In step 499, as shown in FIGS. 4B and 5J, each channel inlet 302 is sealed to isolate the lubricant channels 301, the processing regions 234, and the lubricant 505 disposed therein from the environment external to the MEMS device package 230. Step 499 of process sequence 410 is substantially similar to step 462 of process sequence 400, except that in step 499 a wafer-level rather than chip-level process is used, thereby further reducing the number of chip-level fabrication steps required to produce the MEMS device packages 230. In the embodiment illustrated in FIG. 5J, the lubrication channels 301 have been sealed using laser welding, wherein a portion of the weld puddle formed on the upper surface 432A by an energy source (e.g., laser) is displaced to seal lubricant channel 301. Alternatively, the seal can be achieved by epoxy, eutectic solder, glass frit or other typical sealing materials. In step 458, as shown in FIGS. 4B and 5K, the wafer stack consisting of base 233, wafer 235C, and lid 232, is separated by use of a conventional dicing technique to form multiple MEMS device packages 230. Step 458 of process sequence 410 is substantially the same as step 458 in process sequence 400, and is described above in conjunction with FIGS. 4A and 5F. The excess or scrap material 411, which is left over after the dicing process, may then be discarded. As part of step 458, conventional wire bonding and testing can be performed on the formed MEMS device to assure viability thereof and prepare the MEMS device for use in a system that may utilize the MEMS device package 230. Other dicing techniques can also be used to first expose the bond pads to allow wafer level probing and die sorting, followed by a full singulation. FIG. 5L illustrates a cross-sectional plan view of the device package assembly 230, where channel inlet 302 is formed in the lid 432 and does not penetrate exterior surface 235A, according to this embodiment of the invention. FIG. 4C illustrates a process sequence 420 for forming a MEMS device package 230 that contains a lubricant channel 301 and a removable lubricant plug, according to one embodiment of the invention. Steps 450 and 452 in process sequence 420 are substantially the same as steps 450 and 452 in process sequence 400, and are described above in conjunction with FIGS. 4A, 5A, 5B, and 5C. Referring now to FIG. 4C, in step 484, the base 233, which has a plurality of MEMS devices 231 mounted thereon, is aligned with and bonded to the back surface 405 of the wafer 235C with an epoxy layer 506, as illustrated in FIG. 5M. FIG. 5M is a cross-sectional view of the wafer 235C and the base 233 partially forming processing region 234 after bonding. The epoxy bonding process of step 484 is a low temperature process compared to anodic bonding, eutectic bonding, fusion bonding, covalent bonding, and/or glass frit fusion bonding. A lubricant plug 508 is also formed in each lubricant channel 301 as shown, to separate the processing region 234 from the lubricant channel 301. As described above, lubricant plug 508 may be a polymer, such as a photoresist, that converts to a porous material when exposed to UV or other wavelengths of radiation. Alternatively, lubricant plug 508 may be a polymer or other heat-sensitive material that breaks down or otherwise changes physical properties when exposed to heat. In step 486, as shown in FIGS. 4C and 5N, one or more lubricants are introduced into lubricant channel 301. Because in this process step lubricant channel 301 is an open channel, capillary force is not necessary to draw the lubricant 505 into lubricant channel 301. Lubricant plug 508 prevents lubricant 505 from entering processing region 234. In step 487, as shown in FIGS. 4C and 5O, a lid 432 is aligned with and bonded to the top surface 404 of the wafer 235C with a second epoxy layer 507, as illustrated in FIG. 5O. FIG. 5O is a cross-sectional view of the wafer 235C, the base 233, and the lid 432 after bonding with the second epoxy layer 507. Bonding the lid 432 onto the top surface 404 encloses the lubricant channels 301 and the lubricant 505 contained therein, and completes the processing region 234 in which the MEMS device 231 resides. In step 488, as shown in FIGS. 4C and 5P, the seal of lubricant plug 508 is broken or physically altered to allow lubricant 505 into processing region 234. The removal process may involve exposure to UV radiation directed through lid 232 or exposure to heat. In step 458, as shown in FIG. 4C, the wafer stack consisting of base 233, wafer 235C, and lid 232, is separated by use of a conventional dicing technique to form multiple MEMS device packages 230. Step 458 is described above in conjunction with FIGS. 4A and 5F. In an alternative embodiment, the lubricant channel 301 is formed so that the contents of the lubricant channel 301 can be viewed through an optically transparent wall that encloses the processing region, such as the lid 232. In this configuration, the lubricant channel 301 is formed in the lid 232 or the interposer 235, so that the contents of the lubricant channel 301 can be viewed through the optically transparent lid 232. This configuration is useful since it allows the user to inspect the contents of the lubricant channel 301 to see how much lubricant 505 is left in the lubricant channel 301 so that corrective measures can be taken if necessary. In another embodiment, control over the quantity of lubricant introduced into the lubricant channel 301 and the processing region 234 is improved by diluting the lubricant with another liquid prior to insertion of the lubricant into the MEMS device package 230. In some applications, accurate and repeatable delivery of the quantity of lubricant into the lubricant channel 301 is important. Too much lubricant can supersaturate the processing region 234 with lubricant vapor, resulting in condensed lubricant droplets that can produce stiction-related failures at contact regions between interacting MEMS components. Too little lubricant can shorten the lifetime of the MEMS device 231 contained in the MEMS device package 230. However, the volume of lubricant required for the MEMS device package 230 can be as little as on the order of nanoliters, and accurate volumetric delivery of liquids is only known for liquid volumes one or more orders of magnitude greater than this. The inventors have determined that by diluting the lubricant in another liquid, the volume of liquid introduced into the MEMS device package 230 can be increased significantly, e.g., ten times, or 100 times, without increasing the quantity of lubricant introduced into the MEMS device package 230. In one aspect of this embodiment, the lubricant is diluted with a significantly larger volume of solvent having a lower vapor pressure than the lubricant. After sealing the lubricant-solvent solution in lubricant channel 301, the MEMS device package 230 undergoes a bake-out and pump-down process to remove the solvent as overpressure causes vaporized solvent molecules to diffuse out of the MEMS package 230. In another aspect of this embodiment, the lubricant is mixed with a significantly larger volume of a liquid that has a higher vapor pressure than the lubricant and is at least slightly miscible with the lubricant. After sealing the combined lubricant and higher vapor pressure liquid in lubricant channel 301, the MEMS device package is baked-out at a temperature higher than the vaporization temperature of the lubricant, e.g., 200° C., and lower than the vaporization temperature of the higher vapor pressure liquid, e.g., 600° C. In this way the lubricant is activated, i.e., vaporized and allowed to diffuse into the processing region 234, while the miscible liquid containing the lubricant remains in place in the lubricant channel 301. One advantage of the embodiments of the invention described herein relates to the general sequence and timing of delivering the lubricant 505 to the formed MEMS device package 230. In general, one or more embodiments of the invention described herein provide a sequence in which the lubricant 505 is delivered into the processing region after all high temperature MEMS device packaging processes have been performed, e.g., anodic bonding and glass frit bonding. This sequence reduces or prevents the premature release or breakdown of the lubricant that occurs during such high temperature bonding processes, which reach temperatures of 250° C. to 450° C. The ability to place the lubricant 505 into the lubricant channel 301 and processing region 234 after performing the high temperature bonding steps allows one to select a lubricant material that would degrade at the typical bonding temperatures and/or reduce the chances that the lubricant material will breakdown or be damaged during the MEMS device forming process. One skilled in the art will also appreciate that a lubricant channel 301 formed in a MEMS device package using a chip-level packaging process versus a wafer-level packaging process benefits from the delivery of the lubricant 505 after the MEMS device package sealing processes (e.g., anodic bonding, TIG welding, e-beam welding) are performed. Another advantage of the embodiments of the invention described herein relate to the reduced number of processing steps required to form a MEMS device package and the reduced number of steps that need to be performed in a clean room environment. Conventional MEMS device fabrication processes that utilize a reversibly absorbing getter require the additional steps of 1) bonding the getter material to a surface of the lid or other component prior to forming a sealed MEMS device package, and 2) heating the package to activate the getter device. The removal of these steps reduces the number of process sequence steps that need to performed in a clean room environment and thus reduces the cost of forming the MEMS device. The presence of the conventional reversibly absorbing getter also limits the temperature at which the MEMS device package can be hermetically sealed, especially for wafer-level processing. Lubricant Channel Configurations While the preceding discussion only illustrates a MEMS device package that has a single lubricant channel to deliver the lubricant material to the processing region 234, it may be advantageous to form a plurality of lubricant channels 301 having different geometric characteristics and positions within the MEMS device package 230 to better distribute the mobile lubricant within the MEMS package. It is also contemplated that geometrical features may be advantageously incorporated into a lubricant channel to act as particle filters or particle traps. The geometric attributes of each lubricant channel can be used to deliver differing amounts of mobile lubricants at different stages of the products lifetime. FIG. 7A is a cross-sectional plan view of a MEMS device package 230 that has multiple lubricant channels 301A-301C that are formed having differing lengths, shapes and volumes. In one aspect, it is desirable to uniformly distribute the lubricant channels, such as lubricant channels 301A and 301B, in different areas of the MEMS device package 230 so that the distribution of lubricant molecules from the lubricant channels is relatively uniform throughout the MEMS device package. This is particularly beneficial to device with large die dimensions. In one case, the length of the lubricant channels 301A and 301C may be adjusted to reduce the manufacturing cost or optimize the volume of lubricant contained within the lubricant channel. In one embodiment, it may be desirable to form a plurality of lubricant channels that each deliver or contain a different lubricant material having different lubricating properties and/or migration properties. In one embodiment, a first type of mobile lubricant molecule could be transported through or stored in the lubricant channel 301A and a second type of mobile lubricant molecule could be transported through or stored in the lubricant channel 301B, where the first and second mobile lubricant molecules each have different equilibrium partial pressures during normal operation of the device and/or each lubricant has a different migration rate throughout the package. In another embodiment, first and second type of mobile lubricant molecules are introduced into the processing region 234, where the first type of mobile lubricant molecule is selected for its bonding properties to the internal surfaces of the processing region 234 and the second type of mobile lubricant molecule is selected for its bonding properties to the first type of mobile lubricant molecule. In this way, the first type of lubricant molecule is introduced into the processing region 234 via one or more lubricant channels to form a uniform monolayer on internal surfaces of the processing region 234. The second type of mobile lubricant molecule is then introduced into the processing region 234 via one or more lubricant channels to form one or more monolayers on the first lubricant. The multiple monolayers of mobile lubricant molecules then serve as a lubricant reservoir throughout the life of the MEMS device. In one aspect, it may be desirable to tailor the geometry, volume, and surface roughness of the lubricant channels described herein to correspond to the type of lubricant processed within them. FIG. 7B is a cross-sectional view of a wall containing two lubricant channels 301D and 301E that have an exit port 303A or 303B that have a differing geometry to control the rate of lubricant migrating into the processing region. As shown, it may be desirable to have a first lubricant channel 301D that has an exit port 303A with a small cross-sectional area to reduce the diffusion and/or effusion of lubricant into the processing region 234, and a second lubricant channel 301E that has an exit port 303B that has a large cross-sectional area to allow for a rapid diffusion and/or effusion of lubricant into the processing region 234. When these two configurations are used in conjunction with each other, the second lubricant channel 301E can be used to rapidly saturate the surfaces within the processing region 234 during the startup of the MEMS device. However, the first lubricant channel 301D can be used to slowly deliver fresh lubricant to the processing region 234 throughout the life of the device. FIGS. 7C and 7D illustrate another embodiment of a lubricant channel 301F that contains a filter region 605 that contains a plurality of obstructions 601 that are used to minimize the influx of particles of a certain size into the processing region 234 from the environment outside the MEMS device package 230. The obstructions 601 are generally configured to have a desired length 603, width 604 and height (not shown, i.e., into the page) and have a desired spacing 602 between each of the obstructions 601, and thus act as a filter to prevent the influx of particles of a certain size into the processing region 234. The obstructions 601 may be formed in the lubricant channel 301F using conventional patterning, lithography and dry etch techniques during the process of forming the lubricant channel 301F. In one embodiment, the width W of lubricant channel 301F and the orientation of the obstructions 601 disposed in the lubricant channel 301F are configured to maximize the influx of the lubricant into the processing region. In another embodiment, the width W of lubricant channel 301F and the orientation of the obstructions 601 disposed therein are configured to control the flow of the lubricant. Generally, it is desirable to select the number and orientation of the obstructions 601, and the spacing 602 and depth (not shown; i.e., into the page of FIG. 7D) of the spaces between the obstructions 601 so that a particle of desired size is unable to pass into the processing region 234. In one embodiment, the obstructions 601 have a length between about 50 μm and about 200 μm, a width between about 1 μm and about 50 μm, and the spacing 602 is between about 1 μm and about 20 μm. In this embodiment, particles as small as 1 μm in size can be prevented from entering processing region 234. In one aspect, the depth of the spacings 602 may be the same as the depth of the channel. In another embodiment, the lubricant channel 301G contains a number of arrays of obstructions 601 that are staggered relative to each other along a portion of the length of the lubricant channel 301G. In this configuration, particles having a dimension smaller than the clearance of the filter, i.e., spacing 602, can also be blocked efficiently. In another embodiment, multiple groups of obstructions 601, or multiple filter regions 605, are placed in different areas of the lubricant channel to further prevent particles from entering the processing region of the formed device. For example, as shown in FIG. 7C, it may be desirable to have one filter region 605A near the inlet of the lubricant channel to collect particles that may enter from outside of the MEMS device package and another filter region 605B positioned in the lubricant channel near the processing region that acts as a final filtration device before entering the processing region 234. FIG. 7E is a cross-sectional view of a wall containing two lubricant channels that have differing exit port configurations that may be useful to enhance the distribution or delivery of the lubricant to the processing region 234. In one embodiment, a lubricant channel 301G has multiple outlets (e.g., exit ports 303C-303D) that are adapted to improve the rate of delivery of the lubricant to the processing region and/or improve the distribution of lubricant to different areas of the processing region. In another embodiment, the lubricant channel 301H has a large exit port 303E that acts a nozzle, which promotes the delivery of lubricant to the processing region 234. In another embodiment, as shown in FIG. 8, the temperature of the lubricant contained in the lubricant channel 301 may be controlled using a resistive element 921 and a temperature controller 922 for more controlled delivery of the lubricant. In this configuration, the controller 922 is adapted to deliver a desired amount of power to the resistive elements 921 to control the temperature of the lubricant disposed in the lubricant channel 301, and thus control the rate of lubricant migration to the processing region 234. In another aspect, the resistive element 921 is mounted on the exterior surface 235A of one of the walls that encloses the processing region 234, to facilitate control of lubricant temperature within the lubricant channel 301. In one aspect, the resistive element 921 is a metal foil that is deposited on a surface of one of the walls that encloses the processing region 234. One should note that the migration rate of the lubricant from the lubricant channel 301 is strongly dependent on the temperature of the lubricant, since vaporization and diffusion are both thermally activated processes. In one embodiment, a volume of gas 901 (FIG. 8) may be purposely injected into the lubricant channel 301 prior to covering the channel inlet 302 with the cap 304 to provide a buffer and a temperature-compensating mechanism that controls the rate of delivery to the processing region 234. In this configuration, the volume of gas 901 expands as the temperature increases, which causes the lubricant disposed in the lubricant channel 301 to be pushed towards the exit port 303, and retract when the temperature in the lubricant channel 301 drops. In one embodiment, where the lubricant is a viscous liquid and/or has a strong adhesion to internal surfaces of the lubricant channel 301, the volume of gas 901 may be added at a pressure that is slightly higher than the pressure in the processing region 234. This allows the gas to slowly deliver the lubricant to the processing region as the volume of gas expands to compensate for the pressure difference. In one embodiment, as shown in FIG. 9A, a cap 304A may be inserted at the exit port 303 to isolate the lubricant channel 301 from the processing region 234, until it is desirable to remove the cap 304A to allow the lubricant 505 to enter the processing region 234. In one aspect, the cap 304A is a polymer, such as a photoresist, that remains in place over the exit port 303 until it is exposed to some form of optical radiation or heating that induces a phase separation or change of the physical properties of the material contained in the cap 304, thereby converting cap 304A into a porous material. This configuration is especially useful in configurations in which the lubricant channel 301 is positioned adjacent to a lid 232 (see FIGS. 2A and 6B) formed from an optically transparent material that passes the desired wavelength of light to break down the material of cap 304A. In another embodiment, the cap 304A is adapted to breakdown at an elevated temperature. This configuration allows the encapsulation of a desired quantity of lubricant in the lubricant channel 301 prior to bonding the device substrate with a lower temperature sealing method, e.g., epoxy sealing. Release of the lubricant can be initiated any time after the sealing process is completed. In one embodiment, at least a portion of the lubricant channel 301 and a MEMS device element 950 are formed on the base 233 as illustrated in FIG. 9B. The remainder of lubricant channel 301 may be formed in a wall of an interposer 235, as shown, or entirely in base 233. The MEMS device element 950 is disposed proximate the portion of lubricant channel 301 formed in base 233 so that a portion 951 of the MEMS device element 950 can be actuated to cover the exit port 303 of the lubricant channel 301. The MEMS device element 950 can be formed in base 233 at the same time that MEMS device 231 is formed. In this configuration, the MEMS device element 950 can be externally actuated by a power supply 112 to cover or expose the exit port 303 so that the MEMS device element 950 acts as a valve that can regulate the flow of lubricant material from the lubricant channel 301. The portion 951 may pivot (see “P” in FIG. 9B) to cover the exit port 303 by use of a bias applied by the power supply 112. In one embodiment, a lubricant channel contained in a wall that encloses the processing region of a MEMS package includes one or more geometrical features that serve as particle traps, as illustrated in FIGS. 10A and 10B. FIG. 10A is a plan view of a MEMS device package 1030 having a lubricant channel 1001 formed with a particle trap 1002, according to an embodiment of the invention. For clarity, MEMS device package 1030 is illustrated with a partial section 1091 of the lid 232 removed. As shown, lubricant channel 1001 is formed in the interposer 235 and extends from the exterior surface 235A to the interior surface 235B of the interposer 235. The lubricant channel 1001 is substantially similar to the lubricant channel 301, described above, except that the lubricant channel 1001 is formed with the particle trap 1002. The particle trap 1002 is a cavity formed in fluid communication with the internal region 305 of the lubricant channel 1001 and positioned opposite the channel inlet 302. Because of the placement of the particle trap 1002, a substantial portion of particles urged into the internal region 305 when the channel inlet 302 is formed by a material removal or other similar process will be collected inside the particle trap 1002. This is particularly true when a laser drilling process is used to form channel inlet 302. As shown, particle trap 1002 is a dead space, i.e., a “dead end” volume that is not a part of the fluid passage between the exterior surface 235A and the interior surface 235B of the interposer 235. Therefore, particles collected in the particle trap 1002 are not carried into the processing region 234 inside the MEMS device package 1030 when lubricant is introduced into the lubricant channel 1001 via the channel inlet 302. To further reduce the number of particles carried into the processing region 234, particle trap 1002 may also be configured to reduce the number of particles generated in internal region 305 when laser drilling is used to form channel inlet 302. The inventors have determined that a laser beam can blaze surfaces of internal region 305 during laser drilling, producing particles. An internal surface 1003 of internal region 305 can be ablated by the drilling laser after channel inlet 302 is formed and prior to laser shut-off. To minimize the number of particles produced by ablation of the surface 1003 by the drilling laser, the particle trap 1002 may be configured so that the surface 1003 is positioned away from the focal point 1004 of the drilling laser. Focal point 1004, which is indicated by the intersection of rays 1006 and 1007, is substantially coincident with the channel inlet 302. By positioning the surface 1003 away from the focal point 1004 and the channel inlet 302, the energy density of the penetrating laser beam is reduced when incident on the surface 1003. It is believed that by so doing, fewer particles are formed in internal region 305. It is also believed that particles that are present in internal region 305 are generally fused onto surface 1003 and other internal surfaces, and are therefore immobile particles that cannot be carried into processing region 234. FIG. 10B is a plan view of a MEMS device package 1031 having a lubricant channel 1011 formed with a non-linear particle trap 1009, according to an embodiment of the invention. In this embodiment, the lubricant channel 1011 is substantially similar to the lubricant channel 1001 in FIG. 10A, except that the lubricant channel 1011 is formed with the non-linear particle trap 1009. In this embodiment, the non-linear particle trap 1009 positions a surface 1013 a distance from the focal point 1004 of the penetrating laser beam and further isolates particles collected in non-linear particle trap 1009 from the fluid passage between the exterior surface 235A and the interior surface 235B of the interposer 235. In the embodiment illustrated in FIG. 10B, non-linear particle trap 1009 is configured with a single 90° bend, but it is contemplated that non-linear particle trap 1009 may also be configured with one or more bends of greater than or less than 90° to collect particles formed during the formation of the channel inlet 302. Lubricant Removal Steps In one embodiment, it is desirable to connect a pump (not shown) to the channel inlet 302 (shown in FIG. 6B) so that it can be used to evacuate the processing region to remove one or more of the mobile lubricants and/or dilutent contained therein. In this case the pump may be used to evacuate the processing region to a sufficient pressure to cause the lubricant to vaporize and thus be swept from the device package. In another embodiment, it may be desirable to connect a gas source (not shown) to one injection port (e.g., element 301A in FIG. 7A) and then remove a cap (e.g., element 304 in FIG. 7A) from another injection port (e.g., element 301B in FIG. 7A) so that gas delivered from the gas source can be used to sweep out any used or degraded lubricant material. In either case, these types of techniques can be used to remove old and/or degraded lubricant material so that new lubricant material can be added to the processing region, using the methods described above, to extend the life of the MEMS device. While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.	H	67H01	185H01L	29	84
11755814	US20080157368A1-20080703	MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE HAVING EXCELLENT DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME	ACCEPTED	20080619	20080703	[]	H01L21768	["H01L21768", "H01L23538"]	7531902	20070531	20090512	257	751000	83468.0	QUACH	TUAN	[{"inventor_name_last": "KIM", "inventor_name_first": "Jeong Tae", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "KIM", "inventor_name_first": "Baek Mann", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "KIM", "inventor_name_first": "Soo Hyun", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "LEE", "inventor_name_first": "Young Jin", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "JUNG", "inventor_name_first": "Dong Ha", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}]	A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer.	1. A multi-layered metal line of a semiconductor device comprising: a lower metal line; an upper metal line; and a diffusion barrier formed between the lower and upper metal lines, wherein the diffusion barrier comprises a stack of a first WNx layer, a WCyNx layer, and a second WNx layer. 2. The multi-layered metal line according to claim 1, wherein the first WNx layer has a thickness of 10˜200 Å. 3. The multi-layered metal line according to claim 1, wherein the composition ratio x in the first WNx layer is in the range of 0.1˜10. 4. The multi-layered metal line according to claim 1, wherein the WCyNx layer has a thickness of 5˜50 Å. 5. The multi-layered metal line according to claim 1, wherein the second WNx layer has a thickness of 10˜200 Å. 6. A method for forming a diffusion barrier layer to prevent diffusion of a metal line in a semiconductor device formed with a multi-layered metal line structure, the method for forming a diffusion barrier comprising the steps of: depositing a first WNx layer; surface-treating the first WNx layer; and depositing a second WNx layer on the surface-treated first WNx layer. 7. The method according to claim 6, wherein the first WNx layer is formed in a CVD or ALD process. 8. The method according to claim 6, wherein the first WNx layer is formed to a thickness of 10-200 Å. 9. The method according to claim 6, wherein the composition ratio x in the first WNx layer is 0.1˜10. 10. The method according to claim 6, wherein the step of surface-treating the first WNx layer comprises the step of: forming a WCyNx layer on a surface of the first WNx layer through an heat treatment or plasma treatment under high temperature using a hydrocarbon-based source gas. 11. The method according to claim 10, wherein the hydrocarbon-based gas is CH3 or C2H5 gas. 12. The method according to claim 10, wherein the plasma treatment is implemented under an atmosphere of CH3 or C2H5 at a temperature of 200˜500 ° C., a pressure of 1˜100 torr, and an RF power of 0.1˜1 kW. 13. The method according to claim 10, wherein the WCyNx layer is formed to a thickness of 5˜50 Å. 14. The method according to claim 6, wherein the second WNx layer is formed in a CVD or ALD process. 15. The method according to claim 6, wherein the second WNx layer is formed to a thickness of 10˜200 Å. 16. A method for forming a multi-layered metal line of a semiconductor device, comprising the steps of: forming an interlayer dielectric layer on a semiconductor substrate, the interlayer dielectric layer having a damascene pattern for defining a metal line forming region; depositing a first WNx layer on the interlayer dielectric layer including the damascene pattern; surface-treating the first WNx layer; depositing a second WNx layer on the surface-treated first WNx layer so as to form a diffusion barrier comprising the surface-treated first WNx layer and the second WNx layer; and forming a wiring metal layer on the diffusion barrier to fill the damascene pattern. 17. The method according to claim 16, wherein the damascene pattern is a single type or a dual type. 18. The method according to claim 17, wherein the single type damascene pattern has a trench. 19. The method according to claim 17, wherein the dual type damascene pattern has a via hole and a trench. 20. The method according to claim 16, wherein the first WNx layer is formed in a CVD or ALD process. 21. The method according to claim 16, wherein the first WNx layer is formed to a thickness of 10˜200 Å. 22. The method according to claim 16, wherein the composition ratio x in the first WNx layer is 0.1˜10. 23. The method according to claim 16, wherein the step of surface-treating the first WNx layer comprises the step of: forming a WCyNx layer on a surface of the first WNx layer through an heat treatment or plasma treatment under high temperature using a hydrocarbon-based source gas. 24. The method according to claim 23, wherein the hydrocarbon-based gas is CH3 or C2H5 gas. 25. The method according to claim 23, wherein the plasma treatment is implemented under an atmosphere of CH3 or C2H5 at a temperature of 200˜500° C., a pressure of 1˜100 torr, and an RF power of 0.1˜1 kW. 26. The method according to claim 23, wherein the WCyNx layer is formed to a thickness of 5˜50 Å. 27. The method according to claim 16, wherein the second WNx layer is formed in a CVD or ALD process. 28. The method according to claim 16, wherein the second WNx layer is formed to a thickness of 10˜200 Å. 29. The method according to claim 16, wherein the wiring metal layer is made of a copper layer.	<SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to a multi-layered metal line of a semiconductor device and a method for forming the same, and more particularly to a multi-layered metal line of a semiconductor device, which has an excellent diffusion barrier and a method for forming the same. Memory cells in a highly integrated semiconductor device are formed in a stacked structure in order to meet the high operational speed requirements. Further, a metal line for carrying the electric signals to the memory cells are formed in a multi-layered structure. The multi-layered metal lines provides advantageous design flexibility and allows more leeway in setting the margins for the wiring resistance, the current capacity, etc. Aluminum has been the choice material for a metal line for its superior electric conductivity and the ease of being applied in a fabrication process. However, it is not the case when the design rule is so decreased for higher integration of a semiconductor device, because the resistance of the metal line made of aluminum increases to a undesirable level. To cope with this problem, copper is used as the material for a metal line instead of aluminum as the resistance of copper is relatively lower. In a process for forming a metal line using copper, the copper, unlike aluminum, diffuses through an interlayer dielectric. The copper diffused to a semiconductor substrate acts as deep-level impurities in the semiconductor substrate and induces a leakage current. Therefore, in the case of a metal line formed using copper, a diffusion barrier must be necessarily formed not only where the copper comes into contact with hetero-metal but also on a portion of an interlayer dielectric on which the copper is formed in order to decrease the leakage current due to diffusion of copper. In general, as a diffusion barrier for a metal line formed using copper, a Ti/TiN layer or a Ta/TaN layer is mainly used. Nevertheless, the Ti/TiN layer or Ta/TaN layer, which is used as a diffusion barrier in the metal line formed using copper, is significantly decreased in suppressing the diffusion of copper in an ultra-highly integrated device below 40 nm and cannot properly perform its function as a copper diffusion barrier.	<SOH> SUMMARY OF THE INVENTION <EOH>An embodiment of the present invention is directed to a multi-layered metal line of a semiconductor device which has a diffusion barrier having superior capability for preventing diffusion of copper and a method for forming the same. In one embodiment, there is provided a multi-layered metal line of a semiconductor device having a lower metal line and an upper metal line, wherein the upper metal line includes a diffusion barrier which is made of a stack of a first WN x layer, a WC y N x layer and a second WN x layer. The first WN x layer has a thickness of 10˜200 Å. The composition ratio x in the first WN x layer is 0.1˜10. The WC y N x layer has a thickness of 5˜50 Å. The second WN x layer has a thickness of 10˜200 Å. In another embodiment, there is provided a method for forming a multi-layered metal line of a semiconductor device, including a process for forming a diffusion barrier to prevent diffusion of a metal line, the process for forming a diffusion barrier comprising the steps of depositing a first WN x layer; surface-treating the first WN x layer; and depositing a second WN x layer on the first WN x layer which is surface-treated. The first WN x layer is formed through CVD or ALD. The first WN x layer is formed to have a thickness of 10˜200 Å. The composition ratio x in the first WN x layer is 0.1˜10. The step of surface-treating the first WN x layer comprises the step of forming a WC y N x layer on a surface of the first WN x layer through heat treatment or plasma treatment under a high temperature using a hydrocarbon-based source gas. The hydrocarbon-based gas is CH 3 or C 2 H 5 gas. The plasma treatment is implemented under an atmosphere of CH 3 or C 2 H 5 at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW. The WC y N x layer is formed to have a thickness of 5˜50 Å. The second WN x layer is formed through CVD or ALD. The second WN x layer is formed to have a thickness of 10˜200 Å. In still another embodiment, there is provided a method for forming a multi-layered metal line of a semiconductor device, comprising the steps of forming an interlayer dielectric having a damascene pattern for delimiting a metal line forming region, on a semiconductor substrate; depositing a first WN x layer on the interlayer dielectric including the damascene pattern; surface-treating the first WN x layer; depositing a second WN x layer on the surface-treated first WN x layer and thereby forming a diffusion barrier composed of the surface-treated first WN x layer and the second WN x layer; and forming a wiring metal layer on the diffusion barrier to fill the damascene pattern. The damascene pattern is a single type or a dual type. The single type damascene pattern has a trench. The dual type damascene pattern has a via hole and a trench. The first WN x layer is formed through CVD or ALD. The first WN x layer is formed to have a thickness of 10˜200 Å. The composition ratio x in the first WN x layer is 0.1˜10. The step of surface-treating the first WN x layer comprises the step of forming a WC y N x layer on a surface of the first WN x layer through heat treatment or plasma treatment under a high temperature using a hydrocarbon-based source gas. The hydrocarbon-based gas is CH 3 or C 2 H 5 gas. The plasma treatment is implemented under an atmosphere of CH 3 or C 2 H 5 at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW. The WC y N x layer is formed to have a thickness of 5˜50 Å. The second WN x layer is formed through CVD or ALD. The second WN x layer is formed to have a thickness of 10˜200 Å. The wiring metal layer is made of a copper layer.	CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to Korean patent application number 10-2006-0137251 filed on Dec. 28, 2006, which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION The present invention relates to a multi-layered metal line of a semiconductor device and a method for forming the same, and more particularly to a multi-layered metal line of a semiconductor device, which has an excellent diffusion barrier and a method for forming the same. Memory cells in a highly integrated semiconductor device are formed in a stacked structure in order to meet the high operational speed requirements. Further, a metal line for carrying the electric signals to the memory cells are formed in a multi-layered structure. The multi-layered metal lines provides advantageous design flexibility and allows more leeway in setting the margins for the wiring resistance, the current capacity, etc. Aluminum has been the choice material for a metal line for its superior electric conductivity and the ease of being applied in a fabrication process. However, it is not the case when the design rule is so decreased for higher integration of a semiconductor device, because the resistance of the metal line made of aluminum increases to a undesirable level. To cope with this problem, copper is used as the material for a metal line instead of aluminum as the resistance of copper is relatively lower. In a process for forming a metal line using copper, the copper, unlike aluminum, diffuses through an interlayer dielectric. The copper diffused to a semiconductor substrate acts as deep-level impurities in the semiconductor substrate and induces a leakage current. Therefore, in the case of a metal line formed using copper, a diffusion barrier must be necessarily formed not only where the copper comes into contact with hetero-metal but also on a portion of an interlayer dielectric on which the copper is formed in order to decrease the leakage current due to diffusion of copper. In general, as a diffusion barrier for a metal line formed using copper, a Ti/TiN layer or a Ta/TaN layer is mainly used. Nevertheless, the Ti/TiN layer or Ta/TaN layer, which is used as a diffusion barrier in the metal line formed using copper, is significantly decreased in suppressing the diffusion of copper in an ultra-highly integrated device below 40 nm and cannot properly perform its function as a copper diffusion barrier. SUMMARY OF THE INVENTION An embodiment of the present invention is directed to a multi-layered metal line of a semiconductor device which has a diffusion barrier having superior capability for preventing diffusion of copper and a method for forming the same. In one embodiment, there is provided a multi-layered metal line of a semiconductor device having a lower metal line and an upper metal line, wherein the upper metal line includes a diffusion barrier which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer. The first WNx layer has a thickness of 10˜200 Å. The composition ratio x in the first WNx layer is 0.1˜10. The WCyNx layer has a thickness of 5˜50 Å. The second WNx layer has a thickness of 10˜200 Å. In another embodiment, there is provided a method for forming a multi-layered metal line of a semiconductor device, including a process for forming a diffusion barrier to prevent diffusion of a metal line, the process for forming a diffusion barrier comprising the steps of depositing a first WNx layer; surface-treating the first WNx layer; and depositing a second WNx layer on the first WNx layer which is surface-treated. The first WNx layer is formed through CVD or ALD. The first WNx layer is formed to have a thickness of 10˜200 Å. The composition ratio x in the first WNx layer is 0.1˜10. The step of surface-treating the first WNx layer comprises the step of forming a WCyNx layer on a surface of the first WNx layer through heat treatment or plasma treatment under a high temperature using a hydrocarbon-based source gas. The hydrocarbon-based gas is CH3 or C2H5 gas. The plasma treatment is implemented under an atmosphere of CH3 or C2H5 at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW. The WCyNx layer is formed to have a thickness of 5˜50 Å. The second WNx layer is formed through CVD or ALD. The second WNx layer is formed to have a thickness of 10˜200 Å. In still another embodiment, there is provided a method for forming a multi-layered metal line of a semiconductor device, comprising the steps of forming an interlayer dielectric having a damascene pattern for delimiting a metal line forming region, on a semiconductor substrate; depositing a first WNx layer on the interlayer dielectric including the damascene pattern; surface-treating the first WNx layer; depositing a second WNx layer on the surface-treated first WNx layer and thereby forming a diffusion barrier composed of the surface-treated first WNx layer and the second WNx layer; and forming a wiring metal layer on the diffusion barrier to fill the damascene pattern. The damascene pattern is a single type or a dual type. The single type damascene pattern has a trench. The dual type damascene pattern has a via hole and a trench. The first WNx layer is formed through CVD or ALD. The first WNx layer is formed to have a thickness of 10˜200 Å. The composition ratio x in the first WNx layer is 0.1˜10. The step of surface-treating the first WNx layer comprises the step of forming a WCyNx layer on a surface of the first WNx layer through heat treatment or plasma treatment under a high temperature using a hydrocarbon-based source gas. The hydrocarbon-based gas is CH3 or C2H5 gas. The plasma treatment is implemented under an atmosphere of CH3 or C2H5 at conditions including a temperature of 200˜500° C., a pressure of 1˜100 torr and an RF power of 0.1˜1 kW. The WCyNx layer is formed to have a thickness of 5˜50 Å. The second WNx layer is formed through CVD or ALD. The second WNx layer is formed to have a thickness of 10˜200 Å. The wiring metal layer is made of a copper layer. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 5 are cross-sectional views illustrating the process steps of a method for forming a multi-layered metal line of a semiconductor device in accordance with an embodiment of the present invention. DESCRIPTION OF SPECIFIC EMBODIMENTS In the present invention, as a diffusion barrier comprising a stack of a first WNx layer, a WCyNx layer and a second WNx layer is used to prevent diffusion of the metal line formed using copper. Since the WCyNx layer has excellent diffusion prevention characteristics, the diffusion barrier made of the stack of the first WNx layer, the WCyNx layer and the second WNx layer retains excellent capability for preventing diffusion of copper even in an ultra-highly integrated semiconductor device below 40 nm. Accordingly, in the present invention, in a process for forming a metal line using copper in conformity with the ultra-high integration of a semiconductor device, it is possible to form a metal line having an excellent diffusion barrier, whereby the characteristics of a semiconductor device can be improved. Hereafter, a method for forming a multi-layered metal line of a semiconductor device in accordance with an embodiment of the present invention will be described in detail with reference to FIGS. 1 through 5. Referring to FIG. 1, an interlayer dielectric 110 and a lower metal line 120 made of an aluminum layer are formed on a semiconductor substrate 100. A passivation layer 130 is formed on the interlayer dielectric 110 to prevent the lower metal line 120 from being damaged in a subsequent etching process. The passivation layer 130 is made of a nitride-based layer. A first insulation layer 140 and an etch barrier 150 for preventing the first insulation layer 140 from being etched in a subsequent process for etching a second insulation layer 160 are sequentially formed on the passivation layer 130. The second insulation layer 160 is then formed on the etch barrier 150. Each of the first and second insulation layers 140 and 160 is made of an oxide-based layer, and the etch barrier 150 is made of a nitride-based layer. By etching the second insulation layer 160, the etch barrier 150, the first insulation layer 140, and the passivation layer 130, a via hole 171 is defined to expose the lower metal line 120. By additionally etching the second insulation layer 160 over the via hole 171 using the etch barrier 150 as an etch stop layer until the etch barrier 150 is exposed, a trench 172 is formed to delimit (or define) a metal line forming region. In this way, a dual type damascene pattern 170 comprised of the via hole 171 and the trench 172 is formed. Here, while the dual type damascene pattern 170 is formed by defining the trench 172 after defining the via hole 171, the sequence of forming the dual type damascene pattern 170 can be reversed. Referring to FIG. 2, a first WNx layer 210 is deposited on the second insulation layer 160 including the damascene pattern 170 comprised of the via hole 171 and the trench 172 to a thickness of 10˜200 Å. The first WNx layer 210 is formed through a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The composition ratio x in the first WNx layer 210 is in the range of 0.1˜10. Referring to FIG. 3, by surface-treating the first WNx layer 210, a WCyNx layer 220 is formed on the surface of the first WNx layer 210 to a thickness of 5˜50 Å. The surface treatment of the first WNx layer 210 is implemented through an heat treatment or plasma treatment under high temperature using a hydrocarbon-based gas such as CH3 or C2H5 gas containing “C—H—”. In the case where the surface treatment of the first WNx layer 210 is implemented through a plasma treatment, the plasma treatment is conducted under an atmosphere of CH3 or C2H5 at a temperature of 200˜500° C., a pressure of 1˜100 torr, and an RF power of 0.1˜1 kW. Referring to FIG. 4, a second WNx layer 230 is deposited on the WCyNx layer 220 (which was formed through a surface treatment of the first WNx layer 210) to a thickness of 10˜200 Å. In this way, a diffusion barrier 240 made of a stack of the first WNx layer 210, the WCyNx layer 220, and the second WNx layer 230 is formed. The second WNx layer 230 is formed through a CVD or ALD process to improve the adhesion characteristics between a copper layer (to be subsequently formed) and the diffusion barrier 240. Referring to FIG. 5, a copper layer is deposited on the second WNx layer 230 to fill the trench 172 including the via hole 171 in which the diffusion barrier 240 made of the stack of the first WNx layer 210, the WCyNx layer 220, and the second WNx layer 230 is formed. Then, by performing a chemical mechanical polishing process (“CMPing”) on the copper layer until the second insulation layer 160 is exposed, a via contact 250 is formed in the via hole 171, and an upper metal line 260 made of copper is formed in the trench 172. As is apparent from the above description, because the diffusion barrier of the present invention for preventing the diffusion of a copper metal line is formed in a stack structure of a first WNx layer, a WCyNx layer formed through surface treatment of the first WNx layer, and a second WNx layer, it is possible to form a diffusion barrier having superior diffusion prevention characteristics. As a consequence, it is possible to form a metal line having an excellent diffusion barrier in an ultra-highly integrated semiconductor device. As a result, in the present invention, a metal line having an excellent diffusion barrier for copper can be formed in an ultra-highly integrated semiconductor device, whereby the characteristics of the semiconductor device can be improved. In the above embodiment, a multi-layered metal line was illustrated and explained, which is formed through a dual damascene process wherein a copper layer is deposited in the first insulation layer 140 and the second insulation layer 160 having the dual type damascene pattern 170 including the via hole 171 and the trench 172 and the copper layer is then CMPed to form the via contact 240 in the via hole 171 and the upper metal line 250 in the trench 172. However, it is to be noted that the present invention is not limited to this exemplary embodiment such that the present invention can be applied to a multi-layered metal line which is formed through a single damascene process wherein a copper layer is deposited in an insulation layer having a trench for delimiting (or defining) a metal line forming region and the copper layer is then CMPed to form an upper metal line in the trench. Although specific embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the invention as disclosed in the accompanying claims.	H	67H01	185H01L	217	68
11968099	US20090166769A1-20090702	METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES	ACCEPTED	20090617	20090702	[]	H01L2900	["H01L2900", "H01L21336"]	8021940	20071231	20110920	438	199000	67292.0	PHAM	THANHHA	[{"inventor_name_last": "Metz", "inventor_name_first": "Matthew V.", "inventor_city": "Hillsboro", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Doczy", "inventor_name_first": "Mark L.", "inventor_city": "Meridian", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "Dewey", "inventor_name_first": "Gilbert", "inventor_city": "Hillsboro", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Kavalieros", "inventor_name_first": "Jack", "inventor_city": "Portland", "inventor_state": "OR", "inventor_country": "US"}]	Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.	1. A method comprising: forming a gate dielectric layer on a substrate; forming a metal gate layer on the gate dielectric layer; and forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. 2. The method of claim 1 further comprising wherein the substrate comprises source/drain regions, and wherein the metal gate layer comprises a work function from about 4.8 electron volts to about 5.1 electron volts. 3. The method of claim 1 further comprising wherein the metal gate layer comprises at least one of tantalum nitride, titanium nitride, zirconium nitride, hafnium nitride, tantalum carbide, hafnium carbide and zirconium carbide. 4. The method of claim 1 further comprising wherein the polysilicon layer comprises a substantially amorphous polysilicon layer. 5. The method of claim 5 further comprising wherein the amorphous polysilicon layer comprises less than about 20 percent oxygen. 6. The method of claim 1 further comprising annealing source/drain regions disposed within the substrate at a temperature of about 800 to about 1100 degrees Celsius. 7. The method of claim 1 wherein forming the metal gate layer comprises forming a layer of TiN using an ALD process. 8. The method of claim 7 wherein the TiN layer is formed using TMAT and NH3 gases at a temperature of about 150 to about 300 degrees Celsius. 9. The method of claim 1 further comprising wherein the metal gate layer comprises a thickness of at least about 75 angstroms. 10. The method of claim 1 further comprising wherein the polysilicon layer is formed at a temperature of about 500 to about 600 degrees Celsius. 11. A method comprising; forming a high k gate dielectric layer on a substrate; forming a PMOS metal gate electrode on the high k gate dielectric layer; and forming an amorphous polysilicon layer on the PMOS metal gate electrode, wherein the PMOS metal gate electrode comprises a melting point greater than about 800 degrees Celsius. 12. The method of claim 11 further comprising wherein the PMOS metal gate electrode comprises at least one of tantalum nitride, titanium nitride, zirconium nitride, hafnium nitride, tantalum carbide, hafnium carbide and zirconium carbide. 13. The method of claim 11 further comprising wherein an inversion thin oxide formed beneath the high k gate oxide is below about 14 angstroms. 14. The method of claim 11 further comprising wherein the amorphous polysilicon layer and the PMOS metal gate electrode are formed in a cluster tool, and wherein there is no breaking of vacuum between the formation of the PMOS metal gate electrode and the formation of the amorphous polysilicon layer. 15. The method of claim 11 further comprising wherein the substrate comprises doped source/drain regions, and wherein the source drain regions are annealed at a temperature above about 800 degrees Celsius. 16. A structure comprising: a gate dielectric layer on a substrate; a metal gate layer disposed on the gate dielectric layer; and a polysilicon layer disposed on the metal gate layer, wherein the polysilicon layer comprises less than about 20 percent oxygen. 17. The structure of claim 16 further comprising wherein the metal gate layer comprises a PMOS metal gate electrode, wherein the melting point of the PMOS metal gate electrode is greater than about 800 degrees Celsius. 18. The structure of claim 16 wherein the gate dielectric layer comprises at least one of hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide and combinations thereof. 19. The structure of claim 16 wherein the metal gate layer comprises at least one of tantalum nitride, titanium nitride, zirconium nitride, hafnium nitride, tantalum carbide, hafnium carbide and zirconium carbide. 20. A structure comprising: a high k gate dielectric layer disposed on a substrate, wherein the substrate comprises source/drain regions; a PMOS metal gate electrode disposed on the high k gate dielectric layer, wherein the PMOS metal gate electrode comprises a melting point greater than about 800 degrees Celsius; and an amorphous polysilicon layer disposed on the PMOS metal gate electrode. 21. The structure of claim 20 wherein the amorphous polysilicon layer comprises a thickness greater than about 200 angstroms, and comprises an oxygen percentage of less than about 15 percent. 22. The structure of claim 20 wherein the PMOS metal gate electrode comprises at least one of tantalum nitride, titanium nitride, zirconium nitride, tantalum carbide, hafnium carbide and zirconium carbide and hafnium nitride, and wherein the PMOS metal gate electrode comprises a thickness of greater then about 75 angstroms. 23. The structure of claim 20 further comprising an electrical thin oxide that is below about 13 angstroms in thickness. 24. The structure of claim 20 further comprising wherein the metal gate layer comprises an oxygen percentage of below about 1 percent. 25. The structure of claim 20 wherein the structure comprises a portion of transistor structure, wherein the transistor structure comprises a flatband voltage of greater than about zero.	<SOH> BACKGROUND OF THE INVENTION <EOH>Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. The MOSFET may comprise a gate structure, such as a metal and/or a polysilicon gate structure, as are known in the art.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which: FIGS. 1 a - 1 f represent structures according to embodiments of the present invention. FIG. 2 represents a flow chart according to an embodiment of the present invention. FIG. 3 represents a system according to embodiments of the present invention. detailed-description description="Detailed Description" end="lead"?	BACKGROUND OF THE INVENTION Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. The MOSFET may comprise a gate structure, such as a metal and/or a polysilicon gate structure, as are known in the art. BRIEF DESCRIPTION OF THE DRAWINGS While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which: FIGS. 1a-1f represent structures according to embodiments of the present invention. FIG. 2 represents a flow chart according to an embodiment of the present invention. FIG. 3 represents a system according to embodiments of the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views. Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a gate oxide on a substrate, forming a metal gate layer on the gate oxide, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. Methods of the present invention enable simpler integration with high temperature metal PMOS metal gates. FIGS. 1a-1f illustrate embodiments of the present invention. FIG. 1a illustrates a cross-section of a portion of a substrate 100 that may comprise a P type silicon substrate 100 in some embodiments, and may comprise a portion of a P channel for a metal oxide semiconductor (MOS). The silicon substrate 100 may be comprised of materials such as, but not limited to, silicon, silicon-on-insulator, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, or combinations thereof. The substrate 100 may further comprise source drain regions 104 and a channel region 106. A gate dielectric layer 102 may be disposed on the substrate 100. The gate dielectric layer 102 may comprises a high-k gate dielectric layer 102. Some of the materials that may be used to make high-k gate dielectric layer 102 may include: hafnium oxide, zirconium oxide, titanium oxide, and aluminum oxide. Although a few examples of materials that may comprise the gate dielectric layer 102 are described here, that layer may be made from other high-k gate dielectric materials according to the particular application. A metal gate layer 108 may be formed on the gate dielectric layer 102 (FIG. 1b). In one embodiment, the metal gate layer 108 may comprise at least one of tantalum nitride, titanium nitride, zirconium nitride, and hafnium nitride, tantalum carbide, hafnium carbide and zirconium carbide. The metal gate layer 108 may comprise a material that possesses a melting point greater than about 800 degrees Celsius. In one embodiment, the metal gate layer 108 may be formed using an ALD (Atomic Layer Deposition) process. In one embodiment, the ALD process may be performed in a multi-chamber tool system, as are known in the art, which may comprise a metal gate layer formation chamber and a polysilicon formation chamber, for example. In one embodiment, the metal gate layer 108 may be formed at a pressure of about 0.5 to about 1.5 Torr, a temperature of about 150 to about 300 degrees Celsius, a nitrogen flow rate of about 1.5 to about 2.5 SLM, an NH3 flow rate of about 350 to about 450 sccm, and a TDMAT (please spell out) flow rate of about 75 to about 150 sccm. In one embodiment, the TDMAT may be pulsed with nitrogen followed by a nitrogen purge, and then NH3 and nitrogen may be pulsed, followed by a nitrogen purge. Such a cycle may be repeated according to the particular application. In one embodiment, the metal gate layer 108 that is disposed on the substrate 100 may be kept in the ALD deposition tool under vacuum after the formation of the metal gate layer 108, and may not be exposed to air (i.e. may not be exposed to a pressure greater than about 50 Torr). The metal gate layer 108 may comprise a thickness 110 of about 75 angstroms or greater in some applications. The metal gate layer 108 may preferably comprise a PMOS metal gate layer 108, that is, the metal gate layer 108 may comprise a suitable work function value for operation in a PMOS portion of microelectronic device. For example, the metal gate layer 106 may preferably comprise a work function value that is compatible with a PMOS gate electrode (which typically comprises a work function value of about 4.8-5.1 electron volts). A substantially amorphous polysilicon layer 112 may be formed on the metal gate layer 108 in situ, without exposing the metal gate layer 108 to air, to form a portion of a transistor structure, such as a portion of a PMOS transistor structure 116 (FIG. 1c). In one embodiment, the metal gate layer 108 disposed on the substrate 100 (that may comprise a silicon wafer in some embodiments) may be moved from the metal gate layer formation chamber within the multi-chamber deposition tool to the polysilicon formation chamber while maintaining a pressure in the deposition tool below about 30 Torr). The amorphous polysilicon layer 112 may provide a cap for the metal gate layer 108, wherein the metal gate layer 108 may comprise less moisture, oxygen, and hydrogen than the metal gate layer 108 may comprise if not so capped by the amorphous polysilicon layer 112. In one embodiment, about 1 percent to about 0 percent oxygen may be present in the metal gate layer with the use of the amorphous polysilicon layer 112. In one embodiment, the amorphous polysilicon layer 112 may be formed at a pressure of about 10-20 Torr, a temperature of about 500 to about 600 degrees Celsius, a flow rate of about 300 to about 500 sccm of disilane, and a flow rate of about 1- to about 20 sccm of nitrogen gas. The particular process parameters will vary depending upon the particular application. In one embodiment, the amorphous polysilicon layer 112 may comprise less than about 20 percent oxygen. By forming the amorphous polysilicon layer 112 on the metal gate layer 108 in situ, much less oxygen will be formed within the amorphous polysilicon layer 112 than if the amorphous polysilicon layer 112 was formed ex situ (formed after the metal gate layer 108 is exposed to air. For example, an ex situ polysilicon film may contain greater than about 25 percent oxygen. In one embodiment, the amorphous polysilicon layer 112 may comprise a thickness 114 of about 100 angstroms or greater. In one embodiment, the portion of the PMOS transistor structure 116 may be exposed to an anneal process 118 (FIG. 1d). The anneal process 118 may comprise any type of process that provides sufficient energy to activate the source/drain regions 112, and may comprise a temperature of about 800 degrees to about 1100 degrees Celsius. The particular process parameters will vary depending upon the particular application. Because the metal gate layer 108 may comprises a relatively high melting point (greater than about 800 degrees Celsius) the metal gate layer 108 may withstand the anneal process 188 without melting and/or exhibiting degradation of device performance of the transistor structure 116. A transition layer oxide 120 may be formed beneath the high k gate oxide during the anneal, and may comprise a thickness 122 of about 3-9 angstroms in some embodiments. In one embodiment, a total electrical oxide thickness 121 may comprise the transition layer oxide 120, the high K gate oxide thickness plus a quantum mechanical oxide portion (not shown), and may comprise a total electrical thickness of about 14 angstrom or less. The thickness 122 of the transition layer oxide 120 may comprise a lower thickness (which may be about 3-5 angstroms lower in some embodiments) than a transition layer oxide that may form with an ex-situ polysilicon layer formed on the metal gate layer 108. Thus, the in-situ capping of the metal gate layer 108 by the amorphous polysilicon layer 112 may reduce the thickness of the transition layer oxide 120 and consequently the total electrical oxide thickness 121. FIG. 1e depicts a flat band voltage 124 for a transistor structure (such as the PMOS transistor structure 116 of FIG. 1d, for example) as a function of an electrical oxide thickness 126 for in situ polysilicon 128 and ex-situ polysilicon 130. The flatband voltage 124 for the in situ polysilicon 128 is about 0.25 volts at about 12 angstroms inversion thin oxide thickness 126, whereas the flatband voltage 124 for the ex situ polysilicon 130 is about 0.20 volts at about 14 angstroms inversion thin oxide thickness 126. Thus, the flatband voltage 124 for the in situ polysilicon 126 is greater than about 0 volts relative to P type silicon with an inversion thin oxide thickness 126 of about 12 angstroms, less than that for the ex situ polysilicon 130. FIG. 1f depicts a portion of a trigate transistor structure 132, comprising a trigate source region 134, a trigate drain region 136 and trigate gate regions 138. Some features of the trigate transistor structure 132, such as, for example, a sidewall region 140 wherein the trigate source region 134 and a trigate gate region 138 may meet, may be more easily filled/covered with a metal gate material by using embodiments of the present invention (such as ALD deposition as compared with sputtering process, for example) than with prior art processes utilizing replacement metal gate process, for example. FIG. 2 depicts a flow chart according to an embodiment of the present invention. At step 201, a high k gate oxide may be formed on a substrate. At step 203, a PMOS metal gate layer may be formed on the high k gate oxide. At step 205, a polysilicon layer may be formed on the PMOS metal gate layer in situ, wherein the PMOS metal gate layer is not exposed to air. FIG. 3 depicts a diagram illustrating an exemplary system 300 capable of being operated with methods for fabricating a microelectronic structure, such as the transistor structure 116 of FIG. 1d, for example. It will be understood that the present embodiment is but one of many possible systems in which the transistor structures of the present invention may be used. In the system 300, the transistor structure 324 may be communicatively coupled to a printed circuit board (PCB) 318 by way of an I/O bus 308. The communicative coupling of the transistor structure 324 may be established by physical means, such as through the use of a package and/or a socket connection to mount the transistor structure 324 to the PCB 318 (for example by the use of a chip package, interposer and/or a land grid array socket). The transistor structure 324 may also be communicatively coupled to the PCB 318 through various wireless means (for example, without the use of a physical connection to the PCB), as are well known in the art. The system 300 may include a computing device 302, such as a processor, and a cache memory 304 communicatively coupled to each other through a processor bus 305. In one embodiment, the computing device 302 may comprise at least one transistor structure. The processor bus 305 and the I/O bus 308 may be bridged by a host bridge 306. Communicatively coupled to the I/O bus 308 and also to the transistor structure 324 may be a main memory 312. Examples of the main memory 312 may include, but are not limited to, static random access memory (SRAM) and/or dynamic random access memory (DRAM), and/or some other state preserving mediums. In one embodiment, the main memory 312 may comprise at least one transistor structure. The system 300 may also include a graphics coprocessor 313, however incorporation of the graphics coprocessor 313 into the system 300 is not necessary to the operation of the system 300. Coupled to the I/O bus 308 may also, for example, be a display device 314, a mass storage device 320, and keyboard and pointing devices 322. In one embodiment, the mass storage device 320 may comprise at least one transistor structure. These elements perform their conventional functions well known in the art. In particular, mass storage 320 may be used to provide long-term storage for the executable instructions for a method for forming and/or utilizing transistor structures in accordance with embodiments of the present invention, whereas main memory 312 may be used to store on a shorter term basis the executable instructions of a method for forming and/or utilizing transistor structures in accordance with embodiments of the present invention during execution by computing device 302. In addition, the instructions may be stored, or otherwise associated with, machine accessible mediums communicatively coupled with the system, such as compact disk read only memories (CD-ROMs), digital versatile disks (DVDs), and floppy disks, carrier waves, and/or other propagated signals, for example. In one embodiment, main memory 312 may supply the computing device 302 (which may be a processor, for example) with the executable instructions for execution. Thus, the methods of the present invention enable the formation of high temperature PMOS metal gates for use with high-K dielectrics that may survive high temperature processing. Benefits of the present invention include enabling of device scaling and metal gate fabrication without the use of a replacement metal gate process for PMOS channel structures. The subtractive (high-temperature compliant) based integration of metal gate electrodes is enabled. Complex tri-gate integration is achieved without the need for replacement metal gate processes. The novel in-situ stack of the present invention significantly reduces oxidation below the high-K layer. This enables high temperature PMOS metal gate with concomitant electrical inversion oxide thickness (Toxe) of below about 14 Å. Replacement metal gate process flow has been used in prior art processes to achieve below 14 Å Tox, but this requires avoidance of placing the metal on the gate stack prior to anneal, thus increasing process complexity. Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that a microelectronic device, such as a transistor is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.	H	67H01	185H01L	29	00
11834367	US20080035998A1-20080214	PSEUDO SOI SUBSTRATE AND ASSOCIATED SEMICONDUCTOR DEVICES	ACCEPTED	20080130	20080214	[]	H01L29786	["H01L29786", "H01L2900"]	7538392	20070806	20090526	257	347000	67400.0	BOOTH	RICHARD	[{"inventor_name_last": "Ramaswamy", "inventor_name_first": "Nirmal", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "Blomiley", "inventor_name_first": "Eric", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "Drewes", "inventor_name_first": "Joel", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}]	The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.	1.-34. (canceled) 35. A device, comprising: a substrate comprised of a semiconductor material; and a plurality of spaced apart dielectric layers encapsulated within the substrate. 36. The device of claim 1, wherein each of the plurality of spaced apart dielectric layers are surrounded by the semiconductor material. 37. The device of claim 1, wherein each of the plurality of spaced apart dielectric layers has a substantially planar upper surface, wherein the substrate has a substantially planar upper surface, and wherein the substantially planar upper surface of the substrate is spaced apart from the substantially planar upper surface of each of the plurality of spaced apart dielectric layers by a substantially uniform distance. 38. The device of claim 37, wherein the distance ranges from 100-1000 Å. 39. The device of claim 38, wherein each of the spaced apart dielectric layers has the same approximate thickness. 40. The device of claim 39, wherein the thickness of the spaced apart dielectric layers is approximately 200-3000 Å. 41. The device of claim 35, wherein each of the plurality of spaced apart dielectric layers is a portion of a deposited layer of dielectric material. 42. The device of claim 35, wherein each of the plurality of spaced apart dielectric layers is a portion of a thermally grown layer of dielectric material. 43. The device of claim 35, further comprising a plurality of transistors, wherein, for each transistor, a gate insulation layer and a gate electrode of the transistor is positioned above one of the spaced apart dielectric layers. 44. The device of claim 35, further comprising a plurality of transistors, wherein, for each transistor, a gate insulation layer and a gate electrode of the transistor is positioned above and between adjacent spaced apart dielectric layers. 45. The device of claim 37, further comprising a plurality of isolation structures, each of which extends from the upper surface of the substrate and terminates proximate one of the plurality of spaced apart dielectric layers. 46. The device of claim 35, wherein the spaced apart dielectric layers are comprised of silicon dioxide, silicon nitride or silicon oxynitride. 47. The device of claim 35, wherein each of the plurality of spaced apart dielectric layers has a substantially trapezoidal configuration. 48. The device of claim 35, wherein each of the plurality of dielectric layers has an upper surface and a lower surface, wherein a length of the upper surface is greater than a length of the lower surface. 49. The device of claim 48, wherein each of the plurality of spaced apart dielectric layers has sloped sidewalls that extend from the upper surface to the lower surface. 50. A device, comprising: a substrate comprised of a semiconductor material, the substrate having a substantially planar upper surface; and a plurality of spaced apart dielectric layers, wherein each of the plurality of spaced apart dielectric layers are surrounded by the semiconductor material, and wherein each of the plurality of spaced apart dielectric layers has a substantially planar upper surface and a substantially planar lower surface, and wherein the substantially planar upper surface of the substrate is spaced apart from the substantially planar upper surface of each of the plurality of spaced apart dielectric layers by a substantially uniform distance, wherein a length of the upper surface of the dielectric layer is greater than a length of the substantially planar lower surface of the dielectric layer. 51. The device of claim 50, wherein the substantially uniform distance ranges from 100-1000 Å. 52. The device of claim 50, wherein each of the spaced apart dielectric layers has the same approximate thickness. 53. The device of claim 52, wherein the thickness of the spaced apart dielectric layers is approximately 200-3000 Å. 54. The device of claim 50, wherein each of the plurality of spaced apart dielectric layers is a portion of a deposited layer of dielectric material. 55. The device of claim 50, wherein each of the plurality of spaced apart dielectric layers is a portion of a thermally grown layer of dielectric material. 56. The device of claim 50, further comprising a plurality of transistors, wherein, for each transistor, a gate insulation layer and a gate electrode of the transistor is positioned above one of the spaced apart dielectric layers. 57. The device of claim 50, further comprising a plurality of transistors, wherein, for each transistor, a gate insulation layer and a gate electrode of the transistor is positioned above and between adjacent spaced apart dielectric layers. 58. The device of claim 50, further comprising a plurality of isolation structures, each of which extends from the upper surface of the substrate and terminates proximate one of the plurality of spaced apart dielectric layers. 59. The device of claim 50, wherein the spaced apart dielectric layers are comprised of silicon dioxide, silicon nitride or silicon oxynitride. 60. The device of claim 50, wherein each of the plurality of spaced apart dielectric layers has a substantially trapezoidal configuration. 61. The device of claim 50, wherein each of the plurality of spaced apart dielectric layers has sloped sidewalls that extend from the upper surface of the dielectric layer to the lower surface of the dielectric layer.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming a pseudo SOI substrate and integrated circuit devices thereabove. 2. Description of the Related Art There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. As transistors are continually scaled in keeping with the requirements of advancing technology, device reliability dictates an associated reduction in the power supply voltage. Hence, every successive technology generation is often accompanied by a reduction in the operating voltage of the transistor. It is known that transistor devices fabricated on silicon-on-insulator (SOI) substrates exhibit better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. The superior performance of SOI devices at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. The buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, thus reducing junction capacitance. Transistors fabricated in SOI substrates offer several performance advantages over transistors fabricated in bulk silicon substrates. For example, complementary-metal-oxide-semiconductor (CMOS) devices fabricated in SOI substrates are less prone to disabling capacitive coupling, known as latch-up. In addition, transistors fabricated in SOI substrates, in general, have large drive currents and high transconductance values. Also, the sub-micron SOI transistors have improved immunity to short-channel effects when compared with bulk transistors fabricated to similar dimensions. However, SOI substrates are expensive as compared to bulk silicon substrates and thus tend to increase the cost of manufacturing. Moreover, some of the techniques for forming SOI substrates, e.g., epitaxial growth of silicon on a previously formed oxide layer, can result in defects being present in the silicon layer where elements of the integrated circuit device will be formed. The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems.	<SOH> SUMMARY OF THE INVENTION <EOH>The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate. In another illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above and encapsulate the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate. In yet another illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment having a partial pressure of 1-200 Torr to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate, wherein the anneal process is performed at a temperature ranging from approximately 800-1200° C.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming a pseudo SOI substrate and integrated circuit devices thereabove. 2. Description of the Related Art There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. As transistors are continually scaled in keeping with the requirements of advancing technology, device reliability dictates an associated reduction in the power supply voltage. Hence, every successive technology generation is often accompanied by a reduction in the operating voltage of the transistor. It is known that transistor devices fabricated on silicon-on-insulator (SOI) substrates exhibit better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. The superior performance of SOI devices at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. The buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, thus reducing junction capacitance. Transistors fabricated in SOI substrates offer several performance advantages over transistors fabricated in bulk silicon substrates. For example, complementary-metal-oxide-semiconductor (CMOS) devices fabricated in SOI substrates are less prone to disabling capacitive coupling, known as latch-up. In addition, transistors fabricated in SOI substrates, in general, have large drive currents and high transconductance values. Also, the sub-micron SOI transistors have improved immunity to short-channel effects when compared with bulk transistors fabricated to similar dimensions. However, SOI substrates are expensive as compared to bulk silicon substrates and thus tend to increase the cost of manufacturing. Moreover, some of the techniques for forming SOI substrates, e.g., epitaxial growth of silicon on a previously formed oxide layer, can result in defects being present in the silicon layer where elements of the integrated circuit device will be formed. The present invention is directed to a device and various methods that may solve, or at least reduce, some or all of the aforementioned problems. SUMMARY OF THE INVENTION The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate. In another illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above and encapsulate the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate. In yet another illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment having a partial pressure of 1-200 Torr to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate, wherein the anneal process is performed at a temperature ranging from approximately 800-1200° C. BRIEF DESCRIPTION OF THE DRAWINGS The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: FIGS. 1A-1C are cross-sectional views depicting one illustrative process flow for forming a pseudo SOI substrate in accordance with the present invention; FIGS. 2A-2C depict an illustrative example of forming an insulating layer in accordance with the present invention; FIGS. 3A-3C depict yet another illustrative example of forming a layer of insulating material in accordance with one aspect of the present invention; FIG. 4 depicts an illustrative transistor device formed above the pseudo SOI substrate depicted in FIG. 1C; FIG. 5 depicts an illustrative capacitor device formed above the pseudo SOI substrate depicted in FIG. 1C; FIG. 6 depicts an illustrative structure wherein the source/drain regions of the illustrative transistors are body tied to the substrate; and FIG. 7 depicts an illustrative example wherein the gates of the transistors are body tied to the substrate. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. DETAILED DESCRIPTION OF THE INVENTION Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. The present invention will now be described with reference to the attached figures. Although the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features and doped regions depicted in the drawings may be exaggerated or reduced as compared to the size of those features or regions on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. FIGS. 1A-1C depict one illustrative embodiment of a method of forming pseudo SOI substrates in accordance with the present invention. As will be recognized by those skilled in the art after a complete reading of the present application, the present invention has broad application and may be employed in manufacturing a variety of integrated circuit devices. Thus, the illustrative examples depicted herein should not be considered as limitations of the present invention. FIG. 1A depicts an illustrative semiconducting substrate 10 which may be employed as the starting material in manufacturing the pseudo SOI substrate disclosed herein. The semiconducting substrate 10 may be comprised of a variety of semiconducting materials such as doped or undoped silicon. In one illustrative embodiment, the substrate 10 is a bulk silicon substrate doped with an appropriate dopant material, i.e., an N-type or P-type dopant, depending on the particular application. Initially, as shown in FIG. 1A, a plurality of trenches 12 are formed in the substrate 10. The trenches 12 may be formed by performing known photolithography and etching processes, e.g., an anisotropic reactive ion etching process. The size and shape of the trenches 12 may vary depending upon the particular application. For example, the width 14 of the trenches 12 may vary from approximately 50-5000 nm, and the depth 16 may vary from approximately 500-5000 Å. The profile of the trenches 12, as defined by the sidewalls 13, may also vary. Moreover, the trenches 12 need not be formed over the entirety of the substrate 10, and the width and configuration of such trenches on a single substrate 10 may be varied if desired. As shown in FIG. 1B, after the trenches 12 are formed, a layer of insulating material 18 is formed within the trenches 12. The thickness 20 of the layer of insulating material 18, as well as its composition, may vary depending upon the particular application. For example, the layer of insulating material 18 may be comprised of a variety of insulating materials, e.g., silicon dioxide, silicon nitride or silicon oxynitride, and it may have a thickness 20 ranging from approximately 200-3000 Å. The layer of insulating material 18 may be formed by a variety of techniques. FIGS. 2A-2C depict an illustrative example of forming an insulating layer 18 comprised of silicon dioxide. As shown therein, a layer of silicon dioxide 18A is blanket-deposited across the substrate 10 and completely fills the trenches 12. The layer of silicon dioxide 18A may be formed by performing a variety of known deposition processes, e.g., a chemical vapor deposition process. As shown in FIG. 2B, a planarization step, such as, for example, a chemical mechanical polishing step, is performed to substantially planarize the surface 17A of the silicon dioxide layer 18A with the surface 12A of the trenches 12. Thereafter, as shown in FIG. 2C, a wet etching process may be performed to recess or reduce the thickness of the layer of insulating material 18A to the desired thickness 20 shown in FIG. 1B. Alternatively, the layer of insulating material 18 could be a thermally grown layer of silicon dioxide, as depicted in FIGS. 3A-3C. As shown in FIG. 3A, the layer of silicon dioxide 18A is initially formed by performing a well known thermal growth process. Thereafter, as indicated in FIG. 3B, a planarization step is performed to eliminate the portions of the thermally grown silicon dioxide positioned above the surface 12A of the trenches 12. At that point, a wet etching process may be performed to reduce the thickness of the layer of silicon dioxide 18A to the final desired thickness 20 depicted in FIG. 1C. As yet another alternative, the layer of insulating material 18 may be comprised of a material, such as well known silicon oxide or silicon oxynitride precursors, that may be applied by a spin coating technique. Next, the substrate 10 is subjected to an anneal process performed in a hydrogen ambient at a relatively high temperature. The anneal process increases the surface mobility of the silicon substrate 10 causing the portions of the substrate positioned above the insulating layer 18 to merge with adjacent silicon material to thereby result in the pseudo SOI structure 30 depicted in FIG. 1C. The pseudo SOI substrate 30 comprises a continuous region of silicon 22 positioned above the upper surfaces 24 of a plurality of regions 26 comprised of insulating material. In a sense, the anneal process causes the silicon material to merge above the insulating material 18 within the trenches 12 to thereby define the regions 26 of insulating material. The regions 26 of insulating material may be of any desired shape or configuration. For example, the regions 26 may take the shape of a line, a rectangular area, etc. In some applications, the trench 12 may be formed such that, after the anneal process is performed, the region 26 of insulating material is encapsulated by silicon. The thickness 24 of the layer of silicon 22 may vary depending upon the particular application. In one illustrative embodiment, the thickness 24 may range from approximately 100-1000 Å. The hydrogen anneal process described above may be performed in a traditional furnace, in an RTA chamber or any other tool capable of performing the anneal process described herein. The temperature of the anneal process may vary depending upon the particular application. In general, the anneal process may be performed at a temperature ranging from approximately 800-1000° C. if the insulating material 18 is comprised of silicon dioxide or other like materials. If the insulating material 18 is comprised of a material that can withstand higher temperatures, e.g., silicon nitride, then the anneal process may be performed at a slightly higher temperature, e.g., 800-1200° C. The duration of the anneal process may also vary depending on the particular application. In one illustrative embodiment, the anneal process may be performed for a duration ranging from approximately 10 seconds (for an RTA anneal) to 2 minutes. The partial pressure of hydrogen during the anneal process may range from approximately 1-200 Torr depending on the particular application. Performing the anneal process in the hydrogen environment increases the surface mobility of the silicon, thus allowing the portions of the silicon material to merge with one another as depicted in FIG. 1C. After the anneal process is performed, a planarization process, e.g., a chemical mechanical planarization process, may be performed on the surface 22A of the merged silicon material 22 if desired or needed. The substantially continuous layer of silicon 22 has a relatively low occurrence of defects and, in some cases, may be substantially defect free as the silicon material is allowed to merge together during the anneal process described above. That is, the present invention is fundamentally different from an epitaxial silicon growth process wherein defects in the resulting layer of epitaxial silicon are known to exist. After the pseudo SOI substrate 30 depicted in FIG. 1C is formed, traditional processing operations may be performed to form any of a variety of different integrated circuit devices on and above the pseudo SOI substrate 30. For example, FIG. 4 depicts an illustrative transistor 40 formed above the pseudo SOI substrate 30. The transistor 40 is comprised of a variety of known components and it may be manufacturing using a variety of known techniques. For example, the transistor 40 may comprise a gate insulation layer 41, a gate electrode 42, a sidewall spacer 43 and source/drain regions 44. A trench isolation region 45 may be formed in the layer of silicon material 22 to electrically isolate the transistor 40. Note that, in this illustrative example, the channel region of the transistor 40 is positioned above the region 26 of insulating material. The materials of construction of the various components of the transistor 40, as well as the manner in which such components are made, are well known to those skilled in the art and will not be described any further so as not to obscure the present invention. The illustrative transistor 40 may be part of a larger integrated circuit that is part of a semiconductor device, such as a memory chip, a logic chip and/or an application specific integrated circuit (ASIC). FIG. 5 depicts yet another illustrative semiconductor device that may be formed on the pseudo SOI substrate 30. As shown therein, portions of an illustrative capacitor 60 are schematically depicted. The capacitor 60 comprises a control transistor 61 having a gate insulation layer 62, a gate electrode 63, sidewall spacers 64 and source/drain regions 65. A plurality of capacitor contacts 66 formed above the surface of the silicon material 22 are also schematically depicted. An illustrative isolation region 67 is formed in the silicon material 22 to electrically isolate the capacitor 60. Again, the manner in which such devices are formed are well known to those skilled in the art. FIGS. 6 and 7 also depict illustrative structures wherein the present invention may be employed. FIG. 6 depicts an illustrative example wherein the channel regions of the illustrative transistors 40 are positioned approximately above a region 26 of insulating material. In the embodiment depicted in FIG. 6, those skilled in the art will understand that the source/drain regions (not shown in FIG. 6) are body tied to the substrate 10. FIG. 7 depicts an illustrative structure wherein the channel regions of the illustrative transistors 40 are positioned approximately over the gaps or space between the regions 26. Those skilled in the art will understand that this structure depicts the situation where the gate of the transistor is body tied to the substrate 10. The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate. In another illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment having a partial pressure of 1-200 Torr to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate, wherein the anneal process is performed at a temperature ranging from approximately 800-1200° C. The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.	H	67H01	185H01L	297	86
11735009	US20070254456A1-20071101	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE	ACCEPTED	20071018	20071101	[]	H01L2130	["H01L2130"]	8900970	20070413	20141202	438	458000	75592.0	HENRY	CALEB	[{"inventor_name_last": "MARUYAMA", "inventor_name_first": "Junya", "inventor_city": "Ebina,", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "JINBO", "inventor_name_first": "Yasuhiro", "inventor_city": "Atsugi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "SHOJI", "inventor_name_first": "Hironobu", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}]	A technique for peeling an element manufactured through a process at relatively low temperature (lower than 500° C.) from a substrate and transferring the element to a flexible substrate (typically, a plastic film). With the use of an existing manufacturing device for a large glass substrate, a molybdenum film (Mo film) is formed over a glass substrate, an oxide film is formed over the molybdenum film, and an element is formed over the oxide film through a process at relatively low temperature (lower than 500° C.). Then, the element is peeled from the glass substrate and transferred to a flexible substrate.	1. A method for manufacturing a semiconductor device, comprising the steps of: forming a molybdenum film over a substrate; forming a molybdenum oxide film over the molybdenum film; forming an insulating film over the molybdenum oxide film; forming a semiconductor film having an amorphous structure over the insulating film; separating the insulating film and the semiconductor film having an amorphous structure from the substrate; and disposing the insulating film and the semiconductor film having an amorphous structure over a flexible substrate after the separation. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the molybdenum film is formed in contact with the substrate. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the molybdenum oxide film is formed in contact with the molybdenum film. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of partially performing laser light irradiation before the separation. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is selected from the group consisting of a glass substrate, a ceramic substrate, and a quartz substrate. 6. A method for manufacturing a semiconductor device, comprising the steps of: forming a molybdenum film over a substrate; forming a molybdenum oxide film over the molybdenum film; forming an insulating film over the molybdenum oxide film; forming a semiconductor film including an organic compound over the insulating film; separating the insulating film and the semiconductor film including an organic compound from the substrate; and disposing the insulating film and the semiconductor film including an organic compound over a flexible substrate after the separation. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the molybdenum film is formed in contact with the substrate. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the molybdenum oxide film is formed in contact with the molybdenum film. 9. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of partially performing laser light irradiation before the separation. 10. The method for manufacturing a semiconductor device according to claim 6, wherein the substrate is selected from the group consisting of a glass substrate, a ceramic substrate, and a quartz substrate. 11. A method for manufacturing a semiconductor device, comprising the steps of: forming a molybdenum film over a substrate; forming a molybdenum oxide film over the molybdenum film; forming an insulating film over the molybdenum oxide film; forming a first electrode over the insulating film; forming a light emitting layer over the first electrode; forming a second electrode over the light emitting layer; separating the insulating film, the first electrode, the light emitting layer, and the second electrode from the substrate; and disposing the insulating film, the first electrode, the light emitting layer, and the second electrode over a flexible substrate after the separation. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the molybdenum film is formed in contact with the substrate. 13. The method for manufacturing a semiconductor device according to claim 11, wherein the molybdenum oxide film is formed in contact with the molybdenum film. 14. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of partially performing laser light irradiation before the separation. 15. The method for manufacturing a semiconductor device according to claim 11, wherein the substrate is selected from the group consisting of a glass substrate, a ceramic substrate, and a quartz substrate. 16. The method for manufacturing a semiconductor device according to claim 11, wherein the light emitting layer comprises an organic compound or an inorganic compound. 17. A method for manufacturing a semiconductor device, comprising the steps of: forming a molybdenum film over a substrate; forming a molybdenum oxide film over the molybdenum film; forming a conductive layer over the molybdenum oxide film by a printing method; baking the conductive layer; forming an insulating film to cover the conductive layer; separating the insulating film and the conductive layer from the substrate; and disposing the insulating film and the conductive layer over a flexible substrate after the separation. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the conductive layer is an antenna. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the conductive layer is formed in contact with the molybdenum oxide film. 20. The method for manufacturing a semiconductor device according to claim 17, wherein the molybdenum film is formed in contact with the substrate. 21. The method for manufacturing a semiconductor device according to claim 17, wherein the molybdenum oxide film is formed in contact with the molybdenum film. 22. The method for manufacturing a semiconductor device according to claim 17, further comprising a step of partially performing laser light irradiation before the separation. 23. The method for manufacturing a semiconductor device according to claim 17, wherein the substrate is selected from the group consisting of a glass substrate, a ceramic substrate, and a quartz substrate.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor device which has a circuit including a thin film transistor (hereinafter referred to as a TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electronic device which has as a component an electro-optical device typified by a liquid crystal display panel or a light emitting display device including an organic light emitting element. Note that the term “semiconductor device” in this specification refers to a device in general that can operate by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor device. 2. Description of the Related Art In recent years, attention has been focused on a technique for forming a thin film transistor (TFT) with the use of a semiconductor thin film (with a thickness of approximately several to several hundred nanometers) which is formed over a substrate having an insulating surface. The thin film transistor is widely applied to an electronic device such as an IC or an electro-optical device, and its development especially as a switching element of an image display device is rushed. Various applications using such an image display device have been devised. In particular, application to a portable device has attracted attention. Currently, a glass substrate or a quartz substrate is often used; however, these substrates have the disadvantages of being fragile and heavy. Moreover, it is difficult to increase the size of a glass substrate or a quartz substrate, so that these substrates are unsuitable for mass production. Consequently, a TFT element is attempted to be formed over a substrate having flexibility, typically, a flexible plastic film. Thus, several techniques have been proposed to peel an element formed over a glass substrate from the substrate and transfer the peeled element to another base material such as a plastic film. The assignee of this application has proposed peeling and transferring techniques disclosed in References 1 and 2. Reference 1 discloses a peeling technique in which a silicon oxide film serving as a peeling layer is removed by wet etching. Reference 2 discloses a peeling technique in which a silicon film serving as a peeling layer is removed by dry etching. In addition, the assignee of this application has proposed a peeling and transferring technique disclosed in Reference 3. Reference 3 discloses a peeling technique in which, when a metal layer (Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Ru, Rh, Pd, Os, Ir) is formed over a substrate and an oxide layer is stacked thereover, a metal oxide layer of the metal layer is formed at the interface between the metal layer and the oxide layer and this metal oxide layer is used for peeling in a later step. [Reference 1] Japanese Published Patent Application No. H08-288522 [Reference 2] Japanese Published Patent Application No. H08-250745	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention discloses a technique for separating (in other words, peeling) an element which is formed through a process at relatively low temperature (lower than 500° C.), typically a TFT using an amorphous silicon film or the like, a TFT using an organic semiconductor film, a light emitting element, or a passive element (such as a sensor, an antenna, a resistor, or a capacitor) from a glass substrate and disposing (in other words, transferring) the element to a flexible substrate (typically, a plastic film). Although a TFT using an amorphous silicon film or the like or a TFT using an organic semiconductor film can be formed directly over a plastic film, a special manufacturing apparatus is required to handle a plastic film because of its softness. For mass production, a manufacturing apparatus which supplies a plastic film by a roll-to-roll method is needed. In a case of forming a TFT using an amorphous silicon film or the like or a TFT using an organic semiconductor film directly over a plastic film, the plastic film may change its quality by exposure to a solvent or an etching gas used during the process of manufacturing the TFT. In a case of forming a TFT using ZnO directly over a plastic film, the plastic film changes its quality when exposed to plasma which is generated by a sputtering method or the like. Further, a plastic film may contaminate an element by absorbing or releasing moisture or the like during the process of manufacturing a TFT. Furthermore, a plastic film has lower heat resistance and is more significantly expanded and contracted due to heat as compared to a glass substrate, but it is difficult to finely control all treatment temperatures during the manufacturing process. A feature of the present invention is to form a molybdenum film (Mo film) over a glass substrate and an oxide film over the molybdenum film; to form an element which is formed through a process at relatively low temperature (lower than 500° C.) (a TFT using an amorphous silicon film or the like, a TFT using an organic semiconductor film, a light emitting element, or a passive element (such as a sensor, an antenna, a resistor, or a capacitor)) over the oxide film; to peel the element from the glass substrate; and to transfer the element to a flexible substrate. Molybdenum has the disadvantage of being inferior in heat resistance to tungsten. For example, a molybdenum film causes peeling when subjected to heat treatment at 500° C. or higher; therefore, the temperature during the manufacturing process is preferably lower than 500° C. Further, a molybdenum film formed by a sputtering method is fragile, and is particularly fragile at the crystal grain boundary in a polycrystalline state. In the present invention, this molybdenum film having a fragile property is used to cause peeling. With the use of a molybdenum film having a fragile property, peeling can be performed with high yield even in a case of using a relatively large substrate. In peeling an element including an organic compound (such as a light emitting element or an organic TFT) which is formed over a metal layer over a glass substrate, the element may be peeled not near the metal layer but in or at the interface of a layer including an organic compound because the organic compound has low adhesion, which may damage the element including an organic compound. A material layer formed by a printing method also has low adhesion; therefore, peeling may similarly occur in or at the interface of the material layer. However, in a case of employing a peeling method of the present invention in which a molybdenum film is used, peeling can be performed by weak force relative to other metals because a molybdenum film is fragile. Further, since heat treatment, laser light irradiation, or the like is not particularly necessary for the peeling, the process can be simplified. In tape peel test in which peeling was performed by attaching tape immediately after formation of a silicon oxide film over a molybdenum film, peeling of the silicon oxide film could be confirmed. In other words, peeling can be performed without heat treatment. Note that FIG. 4A is a photograph showing a result of this tape peel test. FIG. 4B shows a schematic diagram of the photograph. Note that a sample shown in FIG. 4A was formed by stacking a silicon oxynitride film with a thickness of 100 nm over a glass substrate, a molybdenum film (with a thickness of 50 nm) thereover, and a silicon oxide film (200 nm) by a sputtering method. As shown in FIG. 4B , peeling with tape 1003 was confirmed in a region 1002 . Note that a substrate 1001 , over which a molybdenum film is formed entirely, has a mirror surface; therefore, the appearance of a ceiling (such as a hose) at the time of shooting is shown in the photograph of FIG. 4A . In addition, it was also confirmed that peeling could be performed even in a case of performing heat treatment as long as it is lower than 500° C. From these test results and characteristics of a molybdenum film, it can be said that molybdenum is a more suitable material than other metals for peeling and transferring an element including an organic compound, or the like. In addition, molybdenum has the advantages of having lower vapor pressure and releasing less gas than other metal elements. Therefore, contamination of an element formed over a molybdenum film can be minimized. Although it is described that a molybdenum film is formed over a glass substrate, there is no limitation to a glass substrate, and a quartz substrate, a ceramic substrate, a semiconductor substrate, or the like can also be used. According to the present invention, an element such as a TFT formed using an existing manufacturing apparatus for a large glass substrate can be transferred to a flexible substrate. Therefore, equipment cost can be significantly reduced. One aspect of the present invention disclosed in this specification is a method of forming an element such as an amorphous TFT over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a semiconductor film having an amorphous structure is formed over the insulating film; and the insulating film and the semiconductor film having an amorphous structure are peeled from the substrate and transferred to a flexible substrate. An experiment was conducted as to whether or not a semiconductor film having an amorphous structure could be peeled without heat treatment. A silicon oxynitride film with a thickness of 100 nm was formed over a glass substrate; a molybdenum film (with a thickness of 50 nm) was formed thereover; and a silicon oxide film (200 nm) was formed by a sputtering method. After that, a silicon oxynitride film with a thickness of 100 nm was formed by a PCVD method, and an amorphous silicon film (54 nm) was formed thereover. When tape was attached to and peeled from a part of an experiment substrate 1 formed as described above, the peeling could be performed as shown in FIG. 15A . As shown in FIG. 15B , which is a schematic diagram of FIG. 15A , peeling with tape could be confirmed in a region 1002 . Note that a substrate 1001 , over which the molybdenum film is formed entirely, has a mirror surface; therefore, the appearance of a ceiling (such as a hose) at the time of shooting is shown in the photograph of FIG. 15A . In tape peel test similarly conducted to an experiment substrate 2 to which heat treatment was performed, peeling could be performed as shown in FIG. 16A . As shown in FIG. 16B , which is a schematic diagram of FIG. 16A , peeling with tape could be confirmed in a region 1002 . A feature of the present invention is not to form an amorphous TFT by sequentially stacking material layers over a flexible substrate but to peel an element such as an amorphous TFT formed over a glass substrate, a ceramic substrate, or a quartz substrate from the substrate and fix the element to a flexible substrate. Note that treatment for fixing the element to the flexible substrate may be performed either before or after the peeling. Further, the element may be fixed between two flexible substrates. Another aspect of the present invention is a method of forming an element such as an organic TFT over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a semiconductor film including an organic compound is formed over the insulating film; and the insulating film and the semiconductor film including an organic compound are peeled from the substrate and transferred to a flexible substrate. Still another aspect of the present invention is a method of forming a light emitting element such as an organic light emitting element or an inorganic light emitting element over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a first electrode is formed over the insulating film; a light emitting layer including an organic compound or an inorganic compound is formed over the first electrode; a second electrode is formed over the light emitting layer; and the insulating film, the first electrode, the light emitting layer, and the second electrode are peeled from the substrate and transferred to a flexible substrate. Yet another aspect of the present invention is a method of forming a passive element such as an antenna over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an antenna is printed by a printing method over the molybdenum oxide film; the antenna is baked; an insulating film is formed to cover the antenna; and the insulating film and the antenna are peeled from the substrate and transferred to a flexible substrate. According to the above aspect, the antenna is preferably formed in contact with the molybdenum oxide film. Since molybdenum oxide which is exposed after the peeling is a semiconductor, electrical connection can be obtained by placing a terminal portion of another element substrate to overlap a part of the antenna. In this case, the molybdenum oxide film is preferably thin and formed as a natural oxide film. According to each of the above aspects, the molybdenum film is preferably formed in contact with the substrate because a process can be simplified. However, when the adhesion between the substrate and the molybdenum film is poor, a material film serving as a buffer layer (such as a silicon oxynitride film or a molybdenum nitride film) may be formed between the substrate and the molybdenum film. According to each of the above aspects, pretreatment may be performed to promote the peeling, and for example, laser light irradiation is preferably performed partially before the peeling. Specifically, a solid-state laser (a pulse-excited Q-switch Nd:YAG laser) may be used, a second harmonic (532 nm) or a third harmonic (355 nm) of a fundamental wave may be used, and relatively weak laser light (with an irradiation energy of a laser light source of 1 mJ to 2 mJ) may be used for the irradiation. The present invention can be applied regardless of an element structure, for example a TFT structure. For example, a top-gate TFT, a bottom-gate (inverted staggered) TFT, or a forward staggered TFT can be used. Further, there is no limitation to a single-gate transistor, and a multi-gate transistor having a plurality of channel formation regions, for example a double-gate transistor, may be used. According to the present invention, a large display device using a flexible substrate can be manufactured, and not only a passive-matrix liquid crystal display device or a passive-matrix light emitting device but also an active-matrix liquid crystal display device or an active-matrix light emitting device can be manufactured. Note that the term “molybdenum film” in this specification refers to a film which mainly contains molybdenum, and is not particularly limited as long as a composition ratio of molybdenum in the film is 50% or more. In order to increase mechanical strength of the film, Co, Sn, or the like may be added. A molybdenum film may also contain nitrogen in order to reduce its fragility. The term “flexible substrate” refers to a plastic film substrate, for example a plastic substrate of polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), or the like. According to the present invention, a peeling step can be carried out smoothly even in a case of using a large substrate with a diagonal length of more than 1 m.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which has a circuit including a thin film transistor (hereinafter referred to as a TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electronic device which has as a component an electro-optical device typified by a liquid crystal display panel or a light emitting display device including an organic light emitting element. Note that the term “semiconductor device” in this specification refers to a device in general that can operate by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all included in the semiconductor device. 2. Description of the Related Art In recent years, attention has been focused on a technique for forming a thin film transistor (TFT) with the use of a semiconductor thin film (with a thickness of approximately several to several hundred nanometers) which is formed over a substrate having an insulating surface. The thin film transistor is widely applied to an electronic device such as an IC or an electro-optical device, and its development especially as a switching element of an image display device is rushed. Various applications using such an image display device have been devised. In particular, application to a portable device has attracted attention. Currently, a glass substrate or a quartz substrate is often used; however, these substrates have the disadvantages of being fragile and heavy. Moreover, it is difficult to increase the size of a glass substrate or a quartz substrate, so that these substrates are unsuitable for mass production. Consequently, a TFT element is attempted to be formed over a substrate having flexibility, typically, a flexible plastic film. Thus, several techniques have been proposed to peel an element formed over a glass substrate from the substrate and transfer the peeled element to another base material such as a plastic film. The assignee of this application has proposed peeling and transferring techniques disclosed in References 1 and 2. Reference 1 discloses a peeling technique in which a silicon oxide film serving as a peeling layer is removed by wet etching. Reference 2 discloses a peeling technique in which a silicon film serving as a peeling layer is removed by dry etching. In addition, the assignee of this application has proposed a peeling and transferring technique disclosed in Reference 3. Reference 3 discloses a peeling technique in which, when a metal layer (Ti, Al, Ta, W, Mo, Cu, Cr, Nd, Fe, Ni, Co, Ru, Rh, Pd, Os, Ir) is formed over a substrate and an oxide layer is stacked thereover, a metal oxide layer of the metal layer is formed at the interface between the metal layer and the oxide layer and this metal oxide layer is used for peeling in a later step. [Reference 1] Japanese Published Patent Application No. H08-288522 [Reference 2] Japanese Published Patent Application No. H08-250745 [Reference 3] Japanese Published Patent Application No. 2003-174153 SUMMARY OF THE INVENTION The present invention discloses a technique for separating (in other words, peeling) an element which is formed through a process at relatively low temperature (lower than 500° C.), typically a TFT using an amorphous silicon film or the like, a TFT using an organic semiconductor film, a light emitting element, or a passive element (such as a sensor, an antenna, a resistor, or a capacitor) from a glass substrate and disposing (in other words, transferring) the element to a flexible substrate (typically, a plastic film). Although a TFT using an amorphous silicon film or the like or a TFT using an organic semiconductor film can be formed directly over a plastic film, a special manufacturing apparatus is required to handle a plastic film because of its softness. For mass production, a manufacturing apparatus which supplies a plastic film by a roll-to-roll method is needed. In a case of forming a TFT using an amorphous silicon film or the like or a TFT using an organic semiconductor film directly over a plastic film, the plastic film may change its quality by exposure to a solvent or an etching gas used during the process of manufacturing the TFT. In a case of forming a TFT using ZnO directly over a plastic film, the plastic film changes its quality when exposed to plasma which is generated by a sputtering method or the like. Further, a plastic film may contaminate an element by absorbing or releasing moisture or the like during the process of manufacturing a TFT. Furthermore, a plastic film has lower heat resistance and is more significantly expanded and contracted due to heat as compared to a glass substrate, but it is difficult to finely control all treatment temperatures during the manufacturing process. A feature of the present invention is to form a molybdenum film (Mo film) over a glass substrate and an oxide film over the molybdenum film; to form an element which is formed through a process at relatively low temperature (lower than 500° C.) (a TFT using an amorphous silicon film or the like, a TFT using an organic semiconductor film, a light emitting element, or a passive element (such as a sensor, an antenna, a resistor, or a capacitor)) over the oxide film; to peel the element from the glass substrate; and to transfer the element to a flexible substrate. Molybdenum has the disadvantage of being inferior in heat resistance to tungsten. For example, a molybdenum film causes peeling when subjected to heat treatment at 500° C. or higher; therefore, the temperature during the manufacturing process is preferably lower than 500° C. Further, a molybdenum film formed by a sputtering method is fragile, and is particularly fragile at the crystal grain boundary in a polycrystalline state. In the present invention, this molybdenum film having a fragile property is used to cause peeling. With the use of a molybdenum film having a fragile property, peeling can be performed with high yield even in a case of using a relatively large substrate. In peeling an element including an organic compound (such as a light emitting element or an organic TFT) which is formed over a metal layer over a glass substrate, the element may be peeled not near the metal layer but in or at the interface of a layer including an organic compound because the organic compound has low adhesion, which may damage the element including an organic compound. A material layer formed by a printing method also has low adhesion; therefore, peeling may similarly occur in or at the interface of the material layer. However, in a case of employing a peeling method of the present invention in which a molybdenum film is used, peeling can be performed by weak force relative to other metals because a molybdenum film is fragile. Further, since heat treatment, laser light irradiation, or the like is not particularly necessary for the peeling, the process can be simplified. In tape peel test in which peeling was performed by attaching tape immediately after formation of a silicon oxide film over a molybdenum film, peeling of the silicon oxide film could be confirmed. In other words, peeling can be performed without heat treatment. Note that FIG. 4A is a photograph showing a result of this tape peel test. FIG. 4B shows a schematic diagram of the photograph. Note that a sample shown in FIG. 4A was formed by stacking a silicon oxynitride film with a thickness of 100 nm over a glass substrate, a molybdenum film (with a thickness of 50 nm) thereover, and a silicon oxide film (200 nm) by a sputtering method. As shown in FIG. 4B, peeling with tape 1003 was confirmed in a region 1002. Note that a substrate 1001, over which a molybdenum film is formed entirely, has a mirror surface; therefore, the appearance of a ceiling (such as a hose) at the time of shooting is shown in the photograph of FIG. 4A. In addition, it was also confirmed that peeling could be performed even in a case of performing heat treatment as long as it is lower than 500° C. From these test results and characteristics of a molybdenum film, it can be said that molybdenum is a more suitable material than other metals for peeling and transferring an element including an organic compound, or the like. In addition, molybdenum has the advantages of having lower vapor pressure and releasing less gas than other metal elements. Therefore, contamination of an element formed over a molybdenum film can be minimized. Although it is described that a molybdenum film is formed over a glass substrate, there is no limitation to a glass substrate, and a quartz substrate, a ceramic substrate, a semiconductor substrate, or the like can also be used. According to the present invention, an element such as a TFT formed using an existing manufacturing apparatus for a large glass substrate can be transferred to a flexible substrate. Therefore, equipment cost can be significantly reduced. One aspect of the present invention disclosed in this specification is a method of forming an element such as an amorphous TFT over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a semiconductor film having an amorphous structure is formed over the insulating film; and the insulating film and the semiconductor film having an amorphous structure are peeled from the substrate and transferred to a flexible substrate. An experiment was conducted as to whether or not a semiconductor film having an amorphous structure could be peeled without heat treatment. A silicon oxynitride film with a thickness of 100 nm was formed over a glass substrate; a molybdenum film (with a thickness of 50 nm) was formed thereover; and a silicon oxide film (200 nm) was formed by a sputtering method. After that, a silicon oxynitride film with a thickness of 100 nm was formed by a PCVD method, and an amorphous silicon film (54 nm) was formed thereover. When tape was attached to and peeled from a part of an experiment substrate 1 formed as described above, the peeling could be performed as shown in FIG. 15A. As shown in FIG. 15B, which is a schematic diagram of FIG. 15A, peeling with tape could be confirmed in a region 1002. Note that a substrate 1001, over which the molybdenum film is formed entirely, has a mirror surface; therefore, the appearance of a ceiling (such as a hose) at the time of shooting is shown in the photograph of FIG. 15A. In tape peel test similarly conducted to an experiment substrate 2 to which heat treatment was performed, peeling could be performed as shown in FIG. 16A. As shown in FIG. 16B, which is a schematic diagram of FIG. 16A, peeling with tape could be confirmed in a region 1002. A feature of the present invention is not to form an amorphous TFT by sequentially stacking material layers over a flexible substrate but to peel an element such as an amorphous TFT formed over a glass substrate, a ceramic substrate, or a quartz substrate from the substrate and fix the element to a flexible substrate. Note that treatment for fixing the element to the flexible substrate may be performed either before or after the peeling. Further, the element may be fixed between two flexible substrates. Another aspect of the present invention is a method of forming an element such as an organic TFT over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a semiconductor film including an organic compound is formed over the insulating film; and the insulating film and the semiconductor film including an organic compound are peeled from the substrate and transferred to a flexible substrate. Still another aspect of the present invention is a method of forming a light emitting element such as an organic light emitting element or an inorganic light emitting element over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an insulating film is formed over the molybdenum oxide film; a first electrode is formed over the insulating film; a light emitting layer including an organic compound or an inorganic compound is formed over the first electrode; a second electrode is formed over the light emitting layer; and the insulating film, the first electrode, the light emitting layer, and the second electrode are peeled from the substrate and transferred to a flexible substrate. Yet another aspect of the present invention is a method of forming a passive element such as an antenna over a flexible substrate. A molybdenum film is formed over a substrate; a molybdenum oxide film is formed over the molybdenum film; an antenna is printed by a printing method over the molybdenum oxide film; the antenna is baked; an insulating film is formed to cover the antenna; and the insulating film and the antenna are peeled from the substrate and transferred to a flexible substrate. According to the above aspect, the antenna is preferably formed in contact with the molybdenum oxide film. Since molybdenum oxide which is exposed after the peeling is a semiconductor, electrical connection can be obtained by placing a terminal portion of another element substrate to overlap a part of the antenna. In this case, the molybdenum oxide film is preferably thin and formed as a natural oxide film. According to each of the above aspects, the molybdenum film is preferably formed in contact with the substrate because a process can be simplified. However, when the adhesion between the substrate and the molybdenum film is poor, a material film serving as a buffer layer (such as a silicon oxynitride film or a molybdenum nitride film) may be formed between the substrate and the molybdenum film. According to each of the above aspects, pretreatment may be performed to promote the peeling, and for example, laser light irradiation is preferably performed partially before the peeling. Specifically, a solid-state laser (a pulse-excited Q-switch Nd:YAG laser) may be used, a second harmonic (532 nm) or a third harmonic (355 nm) of a fundamental wave may be used, and relatively weak laser light (with an irradiation energy of a laser light source of 1 mJ to 2 mJ) may be used for the irradiation. The present invention can be applied regardless of an element structure, for example a TFT structure. For example, a top-gate TFT, a bottom-gate (inverted staggered) TFT, or a forward staggered TFT can be used. Further, there is no limitation to a single-gate transistor, and a multi-gate transistor having a plurality of channel formation regions, for example a double-gate transistor, may be used. According to the present invention, a large display device using a flexible substrate can be manufactured, and not only a passive-matrix liquid crystal display device or a passive-matrix light emitting device but also an active-matrix liquid crystal display device or an active-matrix light emitting device can be manufactured. Note that the term “molybdenum film” in this specification refers to a film which mainly contains molybdenum, and is not particularly limited as long as a composition ratio of molybdenum in the film is 50% or more. In order to increase mechanical strength of the film, Co, Sn, or the like may be added. A molybdenum film may also contain nitrogen in order to reduce its fragility. The term “flexible substrate” refers to a plastic film substrate, for example a plastic substrate of polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), or the like. According to the present invention, a peeling step can be carried out smoothly even in a case of using a large substrate with a diagonal length of more than 1 m. BRIEF DESCRIPTION OF DRAWINGS FIGS. 1A to 1E are cross-sectional views showing a manufacturing process of a liquid crystal display device (Embodiment Mode 1). FIGS. 2A to 2D are cross-sectional views showing a manufacturing process of a light emitting device (Embodiment Mode 2). FIGS. 3A and 3B are diagrams each showing an example of a cross-sectional structure of an organic TFT (Embodiment Mode 2). FIGS. 4A and 4B are a photograph and a schematic diagram showing results of a tape peel test, respectively. FIG. 5A is a top view and FIGS. 5B and 5C are cross-sectional views of a passive-matrix light emitting device (Embodiment Mode 3). FIG. 6 is a perspective view of a passive-matrix light emitting device (Embodiment Mode 3). FIG. 7 is a top view of a passive-matrix light emitting device (Embodiment Mode 3). FIGS. 8A and 8B are top views of a passive-matrix light emitting device (Embodiment Mode 3). FIG. 9 is a cross-sectional view of a passive-matrix light emitting device (Embodiment Mode 3). FIGS. 10A to 10D are cross-sectional views showing a manufacturing process of an antenna, and FIG. 10E is a perspective view showing a manufacturing process of a semiconductor device. FIGS. 11A to 11D are top views each showing a semiconductor device functioning as a wireless chip. FIG. 12A is a block diagram illustrating a semiconductor device obtained by the present invention, and FIG. 12B is a diagram showing an example of an electronic device. FIGS. 13A to 13G are diagrams each showing an example of a semiconductor device. FIGS. 14A to 14C are diagrams each showing an example of an electronic device. FIGS. 15A and 15B are a photograph and a schematic diagram showing a result of a tape peel test, respectively. FIGS. 16A and 16B are a photograph and a schematic diagram showing a result of a tape peel test, respectively. DETAILED DESCRIPTION OF THE INVENTION Embodiment modes and embodiments of the present invention will be described hereinafter. Embodiment Mode 1 An example of manufacturing a liquid crystal display device is explained here with reference to FIGS. 1A to 1E. First, a molybdenum film 102 is formed over a substrate 101. The substrate 101 used here is a glass substrate. The molybdenum film 102 is a molybdenum film formed by a sputtering method with a thickness of 30 nm to 200 nm. Since the substrate may be fixed for a sputtering method, the thickness of the molybdenum film on the edge portion of the substrate tends to be nonuniform. Therefore, the molybdenum film on the edge portion is preferably removed by dry etching. Next, a molybdenum oxide film 103 is formed by oxidation of a surface of the molybdenum film 102. The molybdenum oxide film 103 may be formed by oxidation of the surface with the use of pure water or ozone water or with the use of oxygen plasma. Alternatively, the molybdenum oxide film 103 may be formed by heating in an atmosphere including oxygen. FIG. 1A shows a cross-sectional view at a stage where the steps up to here are completed. A first conductive film is formed over the molybdenum oxide film 103, and a mask is formed over the first conductive film. The first conductive film is formed using a single layer or a stacked layer of an element selected from Ta, W, Ti, Al, Cu, Cr, Nd, and the like, or an alloy material or a compound material mainly containing the element. The first conductive film is appropriately formed by a sputtering method, an evaporation method, a CVD method, a coating method, or the like. Next, a gate electrode 104 is formed by etching the first conductive film with the use of the mask. Then, a first insulating film 105 functioning as a gate insulating film is formed over the gate electrode 104. The first insulating film 105 used here is an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The first insulating film 105 may alternatively be a film obtained by applying and baking a solution including polysilazane or a siloxane polymer, a photo-curing organic resin film, a thermosetting organic resin film, or the like. Next, a semiconductor film 106 having an amorphous structure is formed over the first insulating film 105. The semiconductor film 106 having an amorphous structure is formed using an amorphous semiconductor film or a microcrystalline semiconductor film produced by a vapor deposition method, a sputtering method, or a thermal CVD method using a semiconductor material gas typified by silane or germane. This embodiment mode describes an example of using an amorphous silicon film as the semiconductor film. The semiconductor film may be formed using ZnO or oxide of zinc gallium indium produced by a sputtering method or a pulsed laser deposition (PLD) method. In that case, the gate insulating film is preferably formed using oxide including aluminum or titanium. A semiconductor film containing an impurity element imparting one conductivity type is formed. Here, an amorphous semiconductor film 107 containing an impurity element imparting n-type conductivity is formed with a thickness of 20 nm to 80 nm. The amorphous semiconductor film 107 containing an impurity element imparting n-type conductivity is entirely formed by a plasma CVD method, a sputtering method, or the like. FIG. 1B shows a cross-sectional view at a stage where the steps up to here are completed. Then, an island-like semiconductor layer and a conductive semiconductor layer are obtained by patterning using a photolithography technique. Note that instead of a photolithography technique, a mask may be formed by a droplet discharge method or a printing method (such as relief printing, planography, intaglio printing, or screen printing), and etching may be performed selectively. After that, a source electrode 112 and a drain electrode 113 are formed by selectively discharging a composition including a conductive material (such as silver (Ag), gold (Au), copper (Cu), tungsten (W), or aluminum (Al)) by a droplet discharge method. Note that instead of a droplet discharge method, the source electrode 112 and the drain electrode 113 may be formed by forming a metal film (such as Ta, W, Ti, Al, Cu, Cr, or Nd) by a sputtering method and performing patterning using a photolithography technique. Then, conductive semiconductor layers 110 and 111 are formed using the source electrode 112 and the drain electrode 113 as masks. A semiconductor layer 109 is formed by etching the upper semiconductor layer using the source electrode 112 and the drain electrode 113 as masks to expose a part of the lower semiconductor layer and by further removing a portion of an upper portion of the lower semiconductor layer. The exposed portion of the semiconductor layer 109 functions as a channel formation region of a TFT. A protective film 114 is formed to prevent impurity contamination of the channel formation region of the semiconductor layer 109. The protective film 114 is formed using a material mainly containing silicon nitride or silicon nitride oxide by a sputtering method or a PCVD method. In this embodiment mode, hydrogenation treatment is carried out after the protective film is formed. In this manner, a TFT 108 is manufactured. An interlayer insulating film 115 is formed over the protective film 114. The interlayer insulating film 115 is formed using a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin. Alternatively, it may be formed using an organic material such as benzocyclobutene, parylene, or permeable polyimide, a compound material produced by polymerization of a siloxane-based polymer or the like, a composition material including a water-soluble homopolymer and a water-soluble copolymer, or the like. The interlayer insulating film 115 may be an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or may be formed by stacking any of these insulating films and a resin material. The protective film 114 and the interlayer insulating film 115 are selectively removed by patterning using a photolithography technique to form a contact hole reaching the drain electrode 113. A first electrode 116 is formed by selectively discharging a composition including a conductive material (such as silver (Ag), gold (Au), copper (Cu), tungsten (W), or aluminum (Al)) by a droplet discharge method to be electrically connected to the drain electrode 113. A second electrode 117, which generates an electric field parallel to a substrate plane with the first electrode 116, is also formed by a droplet discharge method. Note that the first electrode 116 and the second electrode 117 are preferably positioned at a regular interval, and the shape of the electrode when seen from above may be pectinate. An orientation film 118 is formed to cover the first electrode 116 and the second electrode 117. FIG. 1C shows a cross-sectional view at a stage where the steps up to here are completed. A flexible substrate 121 is fixed using a liquid crystal material, here a polymer dispersed liquid crystal, so as to face the substrate 101. The polymer dispersed liquid crystal can be roughly divided into two types depending on the dispersion state of liquid crystal and a polymer material. One of these two types is that in which droplets of liquid crystal are dispersed in a polymer material and liquid crystal is discontinuous (called PDLC). The other is that a polymer material forms a network in liquid crystal and liquid crystal is continuous (called PNLC). Note that although either type may be used in this embodiment mode, PDLC is used here. In this embodiment mode, a polymer material 119 including liquid crystal 120 fixes the flexible substrate 121. If necessary, a sealant may be provided to surround the polymer material 119. Further, if necessary, a spacer (such as a bead spacer, a column spacer, or a fiber) may be used to control the thickness of the polymer material 119. The TFT 108 and the flexible substrate 121 are peeled from the molybdenum film 102 and the substrate 101. The peeling can be performed by weak force relative to other metals because the molybdenum film is fragile. FIG. 1D is a diagram showing that separation occurs at the interface between the molybdenum oxide film 103 and the molybdenum film 102. However, separation may occur anywhere between the gate electrode 104 and the substrate 101 that does not destroy the TFT. Separation may be caused in the molybdenum film or the molybdenum oxide film, at the interface between the substrate and the molybdenum film, or at the interface between the gate electrode and the molybdenum oxide film. Note that in a case of manufacturing a transmissive liquid crystal display device, when separation is caused at the interface between the substrate and the molybdenum film and the molybdenum film remains, the molybdenum film is preferably removed later. As shown in FIG. 1E, a flexible substrate 123 is fixed using an adhesive layer 122 to the side on which the peeling has been caused, in order to increase mechanical strength of a liquid crystal display device. Note that the flexible substrate 121 and the flexible substrate 123 are preferably formed using materials having the same thermal expansion coefficient in order to maintain a constant substrate interval independently of temperature change. If the liquid crystal display device has sufficient mechanical strength, the flexible substrate 123 may be omitted. Through the above-described steps, an active-matrix liquid crystal display device using an amorphous-silicon TFT can be manufactured. A conductive film formed by a droplet discharge method has low adhesion. However, in a case of employing the peeling method of the present invention in which a molybdenum film is used, peeling can be performed near the molybdenum film (in this embodiment mode, at the interface between the molybdenum oxide film 103 and the molybdenum film 102) even when a conductive film formed by a droplet discharge method is used as a part of a wiring. This embodiment mode describes an example of forming the gate electrode 104 on the molybdenum oxide film. When a terminal electrode is formed over the same layer and using the same material as the gate electrode on the periphery of a pixel portion, the terminal electrode can be connected to an external terminal such as an FPC through the molybdenum oxide film which also functions as a semiconductor material. In this case, electrical connection can be made by placing an FPC so as to overlap the terminal electrode after peeling. Further in this case, external connection is achieved by providing not only a gate electrode but also a terminal electrode over the same layer and using the same material as the gate electrode separately, and connecting the terminal electrode to a source wiring, a common wiring, or a capacitor wiring. In addition, a driver IC may be connected to the terminal electrode through the molybdenum oxide film. After external connection is achieved as described above, sealing may be performed using another flexible substrate 123. Sealing with the flexible substrate 123 enables an FPC or an IC to be fixed more firmly. Alternatively, an electrophoretic display may be manufactured using electronic ink instead of the polymer dispersed liquid crystal. In that case, after formation of the first electrode 116 and the second electrode 117, electronic ink may be applied by a printing method and then baked, and the flexible substrate 121 may be fixed. Then, the substrate may be peeled, and sealing may be performed using another flexible substrate. Embodiment Mode 2 Described here with reference to FIGS. 2A to 2D is an example of manufacturing an active-matrix light emitting device using an organic TFT. First, a molybdenum film 202 is formed over a substrate 201. The substrate 201 used here is a glass substrate. The molybdenum film 202 is a molybdenum film formed by a sputtering method with a thickness of 30 nm to 200 nm. Next, a molybdenum oxide film 203 is formed by oxidation of a surface of the molybdenum film 202. The molybdenum oxide film 203 may be formed by oxidation of the surface with the use of pure water or ozone water or with the use of oxygen plasma. Alternatively, the molybdenum oxide film 203 may be formed by heating in an atmosphere including oxygen. Further alternatively, it may be formed in a later step of forming an insulating film. When a silicon oxide film or a silicon oxynitride film is formed as the insulating film by a plasma CVD method, the surface of the molybdenum film 202 is oxidized; accordingly, the molybdenum oxide film 203 is formed. Then, an insulating film 204 is formed over the molybdenum oxide film 203. The insulating film 204 is an insulating film such as a silicon oxide film, a silicon nitride film, or silicon oxynitride film (SiOxNy). A typical example of the insulating film 204 has a two-layer structure of a silicon nitride oxide film formed having a thickness of 50 nm to 100 nm by a PCVD method using SiH4, NH3, and N2O as reactive gases and a silicon oxynitride film formed having a thickness of 100 nm to 150 nm using SiH4 and N2O as reactive gases. One layer of the insulating film 204 is preferably a silicon nitride film (SiN film) or a silicon nitride oxide film (SiNxOy film (x>y)) having a thickness of 10 nm or less. Alternatively, a three-layer structure, in which a silicon nitride oxide film, a silicon oxynitride film, and a silicon nitride film are sequentially stacked, may be employed. Although the example of forming the insulating film 204 as a base insulating film is given here, the insulating film 204 may be omitted if not necessary. FIG. 2A shows a cross-sectional view at a stage where the steps up to here are completed. A conductive layer serving as a gate electrode is formed over the insulating film 204. It is acceptable as long as a material used for the conductive layer is a metal to have an insulating property by being nitrided and/or oxidized. In particular, tantalum, niobium, aluminum, copper, or titanium is preferable. Further, tungsten, chromium, nickel, cobalt, magnesium, or the like can also be given as an example. There is no particular limitation on a method of forming the conductive layer. The conductive layer may be formed by forming a film by a sputtering method, an evaporation method, or the like and then processing the film into a desired shape by an etching method or the like. Alternatively, it may be formed by an ink-jet method or the like using droplets including a conductive material. The conductive layer is then nitrided and/or oxidized to form a gate insulating film 212 of nitride, oxide, or oxynitride of the above-mentioned metal. Note that a part of the conductive layer other than the gate insulating film 212 which is obtained by insulating a part of the conductive layer functions as a gate electrode 211. A semiconductor layer 213 is formed to cover the gate insulating film 212. An organic semiconductor material for forming the semiconductor layer 213 may be either a low-molecular or high-molecular organic material as long as it has a carrier transport property and possibly causes a change in carrier density by electric field effect. There is no particular limitation on kinds thereof. Examples are: a polycyclic aromatic compound, a conjugated double bond compound, a metal phthalocyanine complex, a charge-transfer complex, condensed ring tetracarboxylic acid diimides, oligothiophenes, fullerenes, carbon nanotube, and the like. It is possible to use, for example, polypyrrole, polythiophene, poly(3-alkylthiophene), polyphenylenevinylene, poly(p-phenylenevinylene), polyaniline, polydiacetylene, polyazulene, polypyrene, polycarbazole, polyselenophene, polyfuran, poly(p-phenylene), polyindole, polypyridazine, naphthacene, hexacene, heptacene, pyrene, chrysene, perylene, coronene, terrylene, ovalene, quaterrylene, circumanthracene, triphenodioxazine, triphenodithiazine, hexacene-6,15-quinone, polyvinylcarbazole, polyphenylenesulfide, polyvinylenesulfide, polyvinylpyridine, naphthalenetetracarboxylic acid diimide, anthracenetetracarboxylic acid diimide, C60, C70, C76, C78, C84, or a derivative thereof. In addition, specific examples thereof are: tetracene, pentacene, sexithiophene (6T), copper phthalocyanine, bis-(1,2,5-thiadiazolo)-p-quinobis(1,3-dithiole), rubrene, poly(2,5-thienylene vinylene) (PTV), poly(3-hexylthiophene-2,5-diyl) (P3HT), are poly(9,9′-dioctylfluorene-co-bithiophene) (F8T2), which are generally referred to as p-type semiconductors; 7,7,8,8-tetracyanoquinodimethane (TCNQ), 3,4,9,10-perylenetetracarboxylic dianhydride (PTCDA), 1,4,5,8-naphthalenetetracarboxylic dianhydride (NTCDA), N,N′-dioctyl-3,4,9,10-perylenetetracarboxylic diimide (PTCDI-C8H), copper hexadecafluorophthalocyanine (F16CuPc), N,N′-2,2,3,3,4,4,5,5,6,6,7,7,8,8,8-pentadecafluorooctyl-1,4,5,8-naphthalenetetracarboxy lic diimide (NTCDI-C8F), 3′,4′-dibutyl-5,5″-bis(dicyanomethylene)-5,5″-dihydro-2,2′:5′,2″-terthiophene) (DCMT), and methanofullerene[6,6]-phenyl C6, butyric acid methyl ester (PCBM), which are generally referred to as n-type semiconductors; and the like. Note that characteristics of a p-type or n-type organic semiconductor are not peculiar to the substance but depend on the relation with an electrode which injects carriers or the intensity of an electric field at the time of the injection. The semiconductor material can be used as either a p-type or n-type semiconductor, while it has a tendency to easily become one of them. Note that a p-type semiconductor is more preferable in this embodiment mode. Films of these organic semiconductor materials can be formed by an evaporation method, a spin coating method, a droplet discharge method, or the like. Then, a buffer layer 214 is formed over the semiconductor layer 213 to improve adhesion and interfacial chemical stability. The buffer layer 214 may be formed using a conductive organic material (an organic compound having an electron accepting property such as 7,7,8,8-tetracyanoquinodimethane (TCNQ) or 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4-TCNQ)) or a composite material of an organic compound and metal oxide. Note that the buffer layer 214 may be omitted if not necessary. Conductive layers 215, one of which functions as a source electrode and the other as a drain electrode, are formed over the buffer layer 214. Although a material used for the conductive layers 215 is not particularly limited, a metal such as gold, platinum, aluminum, tungsten, titanium, copper, tantalum, niobium, chromium, nickel, cobalt, or magnesium or an alloy containing any of them can be used. Other examples of the material used for the conductive layers 215 are conductive high-molecular compounds such as polyaniline, polypyrrole, polythiophene, polyacetylene, and polydiacetylene, and the like. Note that a method of forming the conductive layers 215 is not particularly limited unless the semiconductor layer 213 is decomposed. The conductive layers 215 may be formed by forming a film by a sputtering method, an evaporation method, or the like and then processing the film into a desired shape by an etching method or the like. Alternatively, the conductive layers 215 may be formed by an ink-jet method using droplets including a conductive material. Through the above steps, an organic transistor 227 can be manufactured. A film of an organic insulating material such as polyimide, polyamic acid, or polyvinyl phenyl may be formed in contact with a lower surface of the semiconductor layer 213. With such a structure, orientation of the organic semiconductor material can further be improved, and adhesion between the gate insulating film 212 and the semiconductor layer 213 can further be improved. A method for manufacturing a light emitting device using the organic transistor 227 is described below. An interlayer insulating film 228 is formed to cover the organic transistor 227. The interlayer insulating film 228 is selectively etched to form a contact hole reaching one of the conductive layers 215. A first electrode 210 is formed to be electrically connected to the one of the conductive layers 215. A partition 221 is formed to cover an end portion of the first electrode 210. The partition 221 is formed using an insulating material and functions to insulate between a plurality of first electrodes 210 adjacent to each other. A light emitting layer 222 is formed over a region of the first electrode 210 which is not in contact with the partition 221. In many cases, the light emitting layer 222 is formed using a single layer or a stacked layer of an organic compound or a single layer or a stacked layer of an inorganic compound. However, in this specification, it is also considered that an inorganic compound is used for a part of a film made of an organic compound. There is no limitation on a stacking method of layers in a light emitting element. Any method that achieves stacking may be selected, such as a vacuum evaporation method, a spin coating method, an ink-jet method, or a dip coating method. A second electrode 223 is formed over the light emitting layer 222. A portion in which the first electrode 210, the second electrode 223, and the light emitting layer 222 overlap each other constitutes a light emitting element. Note that this light emitting element includes an anode, a cathode, and a layer containing an organic compound or a layer containing an inorganic compound, which generates electroluminescence by application of an electric field (hereinafter referred to as an EL layer). An inorganic EL element using an inorganic thin film of ZnS:Mn or an organic EL element using an organic thin film formed by evaporation is particularly bright, shows high-efficiency electroluminescence, and is suitable for application to a display. Note that there is no particular limitation on the structure of the light emitting element. Then, a protective film 224 is formed over the second electrode 223. Note that the protective film 224 may be omitted if not necessary. A flexible substrate 225 is fixed over the protective film 224 with an adhesive layer 226. A sealant may be provided to surround the adhesive layer 226 in order to strengthen sealing. FIG. 2B shows a cross-sectional view at a stage where the steps up to here are completed. Next, the organic transistor 227 and the flexible substrate 225 are peeled from the molybdenum film 202, the molybdenum oxide film 203, and the substrate 201. FIG. 2C is a diagram showing that separation occurs at the interface between the molybdenum oxide film 203 and the insulating film 204. Then, as shown in FIG. 2D, a flexible substrate 206 is fixed using an adhesive layer 205 to the side on which the peeling has been caused, in order to increase mechanical strength of the light emitting device. If the light emitting device has sufficient mechanical strength, the flexible substrate 206 may be omitted. Through the above-described steps, an active-matrix light emitting device using an organic transistor can be manufactured. For example, a light emitting layer formed by an evaporation method has low adhesion. However, in a case of employing the peeling method of the present invention in which a molybdenum film is used, peeling can be performed near the molybdenum film (in this embodiment mode, at the interface between the molybdenum oxide film 203 and the insulating film 204) even when a light emitting layer formed by an evaporation method is used. The structure of the organic transistor is not limited to that shown in FIG. 2C and may be that shown in FIG. 3A or 3B. FIG. 3A shows a structure called a bottom-contact structure. Note that the same reference numeral is used to denote a part in common with FIGS. 2A to 2D. When the bottom-contact structure is employed, a step of photolithography or the like can easily be employed to perform microfabrication of a source wiring and a drain wiring. Therefore, the structure of the organic transistor may be selected appropriately in consideration of its advantage and disadvantage. The molybdenum film 202, the molybdenum oxide film 203, and the insulating film 204 are stacked over the substrate 201. A gate electrode 331 is formed over the insulating film 204. There is no particular limitation on a material used for the gate electrode 331. An example is: a metal such as gold, platinum, aluminum, tungsten, titanium, copper, molybdenum, tantalum, niobium, chromium, nickel, cobalt, or magnesium; an alloy thereof; a conductive high-molecular compound such as polyaniline, polypyrrole, polythiophene, polyacetylene, or polydiacetylene; polysilicon doped with an impurity; or the like. There is no particular limitation on a method of forming the gate electrode 331. The gate electrode 331 may be formed by forming a film by a sputtering method, an evaporation method, or the like and then processing the film into a desired shape by an etching method or the like. Alternatively, it may be formed by an ink-jet method or the like using droplets including a conductive material. Then, an insulating film 332 is formed to cover the gate electrode 331. The insulating film 332 is formed using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Note that the insulating film 332 can be formed by a coating method such as a dipping method, a spin coating method, or a droplet discharge method; a CVD method; a sputtering method; or the like. This insulating film 332 may be subjected to nitridation treatment and/or oxidation treatment using high-density plasma. High-density plasma nitridation can provide a silicon nitride film containing nitrogen at higher concentration. High-density plasma is generated using a high-frequency microwave, for example, 2.45 GHz. With the use of such high-density plasma, oxygen (or a gas including oxygen), nitrogen (or a gas including nitrogen), or the like is activated by plasma excitation and reacted with the insulating film. High-density plasma, a feature of which is low electron temperature, has low kinetic energy of active species; therefore, a film can be formed with less plasma damage and fewer defects as compared with a conventional plasma treatment. In addition, surface roughness of the insulating film 332 can be reduced by using high-density plasma, so that carrier mobility can be increased. Further, orientation of an organic semiconductor material used for forming a semiconductor layer over the insulating film 332 functioning as a gate insulating film can be improved. Next, a source electrode 314 and a drain electrode 315 are formed over the insulating film 332. A semiconductor layer 313 is then formed between the source electrode 314 and the drain electrode 315. The semiconductor layer 313 can be formed using the same material as that of the semiconductor layer 213 shown in FIG. 2B. After an organic transistor having such a structure is formed, the organic transistor is peeled and transferred to a flexible substrate. The structure of FIG. 3B is also described. FIG. 3B shows a structure called a top-gate structure. Note that the same reference numeral is used to denote a part in common with FIGS. 2A to 2D. The molybdenum film 202, the molybdenum oxide film 203, and the insulating film 204 are stacked over the substrate 201. A source electrode 414 and a drain electrode 415 are formed over the insulating film 204. A semiconductor layer 413 is formed between the source electrode 414 and the drain electrode 415. An insulating film 442 is formed to cover the semiconductor layer 413, the source electrode 414, and the drain electrode 415. A gate electrode 441 is formed over the insulating film 442. The gate electrode 441 overlaps the semiconductor layer 413 with the insulating film 442 interposed therebetween. After an organic transistor having such a structure is formed, the organic transistor is peeled and transferred to a flexible substrate. Thus, even organic transistors having various structures can be peeled and transferred to a flexible substrate according to the present invention. For example, a semiconductor layer formed by a coating method has low adhesion. However, in a case of employing the peeling method of the present invention in which a molybdenum film is used, peeling can be performed near the molybdenum film (in this embodiment mode, at the interface between the molybdenum oxide film 203 and the insulating film 204) even when a semiconductor layer formed by a coating method is used. The organic transistor may be replaced by a transistor, a semiconductor film of which is formed using ZnO or oxide of zinc gallium indium by a sputtering method or a PLD method. In that case, the structure of FIG. 3A or 3B can be employed. When ZnO or oxide of zinc gallium indium is used for the semiconductor layer, the gate insulating film is preferably formed using oxide including aluminum or titanium. The present invention is also useful in forming a transistor through a process which includes a step of exposing a substrate to plasma as described above. After a transistor is formed over a substrate which can withstand plasma, the transistor can be peeled and transferred to a flexible substrate. This embodiment mode can be freely combined with Embodiment Mode 1. For example, a liquid crystal display device can be manufactured using the organic transistor described in Embodiment Mode 2 instead of the amorphous TFT described in Embodiment Mode 1. Further, a light emitting device can be manufactured using the amorphous TFT described in Embodiment Mode 1 instead of the organic transistor described in Embodiment Mode 2. Embodiment Mode 3 An example of manufacturing a passive-matrix light emitting device over a flexible substrate is described here with reference to FIGS. 5A to 9. In a passive (simple-matrix) light emitting device, a plurality of anodes arranged in stripes (strip-form) are provided perpendicularly to a plurality of cathodes arranged in stripes. A light emitting layer or a fluorescent layer is interposed at each intersection. Therefore, a pixel at an intersection of an anode selected (to which a voltage is applied) and a cathode selected emits light. FIG. 5A shows a top view of a pixel portion before sealing. FIG. 5B shows a cross-sectional view taken along a dashed line A-A′ in FIG. 5A. FIG. 5C shows a cross-sectional view taken along a dashed line B-B′. A molybdenum film 502, a molybdenum oxide film 503, and an insulating film 504 are stacked over a first substrate 501 similarly to Embodiment Mode 2. A plurality of first electrodes 513 are arranged in stripes at regular intervals over the insulating film 504. A partition 514 having openings each corresponding to a pixel is provided over the first electrodes 513. The partition 514 having openings is formed using an insulating material (a photosensitive or nonphotosensitive organic material (polyimide, acrylic, polyamide, polyimide amide, or benzocyclobutene) or an SOG film (such as a SiOx film including an alkyl group)). Note that each opening corresponding to a pixel is a light emitting region 521. A plurality of inversely tapered partitions 522 parallel to each other are provided over the partition 514 having openings to intersect with the first electrodes 513. The inversely tapered partitions 522 are formed by a photolithography method using a positive-type photosensitive resin, of which portion unexposed to light remains as a pattern, and by adjusting the amount of light exposure or the length of development time so that a lower portion of a pattern is etched more. FIG. 6 shows a perspective view immediately after formation of the plurality of inversely tapered partitions 522 parallel to each other. Note that the same reference numerals are used to denote the same portions as those in FIGS. 5A to 5C. The thickness of each of the inversely tapered partitions 522 is set to be larger than the total thickness of a stacked film including a light emitting layer, and a conductive film. When a stacked film including a light emitting layer, and a conductive film are stacked over the first substrate having the structure shown in FIG. 6, they are separated into a plurality of regions which are electrically isolated from each other, so that stacked films 515R, 515G, and 515B each including a light emitting layer, and second electrodes 516 are formed as shown in FIGS. 5A to 5C. The second electrodes 516 are electrodes in stripe form which are parallel to each other and extend along a direction intersecting with the first electrodes 513. Note that the stacked films each including a light emitting layer and the conductive films are also formed over the inversely tapered partitions 522; however, they are separated from the stacked films 515R, 515G, and 515B each including a light emitting layer and the second electrodes 516. This embodiment mode describes an example of forming a light emitting device, which provides three kinds of light emission (R, G, B) and is capable of performing full color display, by selectively forming the stacked films 515R, 515G, and 515B each including a light emitting layer. The stacked films 515R, 515G, and 515B each including a light emitting layer are formed into a pattern of stripes parallel to each other. Alternatively, stacked films each including a light emitting layer which emits light of the same color may be formed over the entire surface to provide monochromatic light emitting elements, so that a light emitting device capable of performing monochromatic display or a light emitting device capable of performing area color display may be provided. Still alternatively, a light emitting device capable of performing full color display may be provided by combining a light emitting device which provides white light emission with color filters. FIG. 7 shows a top view of a light emitting module mounted with an FPC or the like. Note that the light emitting device in this specification refers to an image display device, a light emitting device, or a light source (including a lighting system). Further, the light emitting device includes any of the following modules in its category: a module in which a connector such as an FPC (Flexible Printed Circuit), a TAB (Tape Automated Bonding) tape, or a TCP (Tape Carrier Package) is attached to a light emitting device; a module having a TAB tape or a TCP provided with a printed wiring board at the end thereof; and a module having an IC (Integrated Circuit) directly mounted over a light emitting device by a COG (Chip On Glass) method. In a pixel portion for displaying images, scan lines and data lines intersect with each other perpendicularly as shown in FIG. 7. The first electrodes 513 in FIGS. 5A to 5C correspond to scan lines 603 in FIG. 7, the second electrodes 516 correspond to data lines 602, and the inversely tapered partitions 522 correspond to partitions 604. Light emitting layers are interposed between the data lines 602 and the scan lines 603, and an intersection portion indicated by a region 605 corresponds to one pixel. Note that the scan lines 603 are electrically connected at their ends to connection wirings 608, and the connection wirings 608 are connected to an FPC 609b through an input terminal 607. The data lines 602 are connected to an FPC 609a through an input terminal 606. Then, a first flexible substrate is fixed using a first adhesive layer. Light emitting elements are peeled from a first substrate 601. A second flexible substrate is then fixed using a second adhesive layer to the side on which the peeling has been caused, in order to seal the light emitting device more firmly. If necessary, a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (a quarter-wave plate or a half-wave plate), or an optical film such as a color filter may be appropriately provided over a light emitting surface. Further, the polarizing plate or the circularly polarizing plate may be provided with an anti-reflection film. For example, anti-glare treatment may be carried out by which reflected light can be diffused by projections and depressions on the surface so as to reduce the glare. Through the above-described steps, a flexible passive-matrix light emitting device can be manufactured. An FPC is preferably mounted over a hard substrate because thermocompression bonding is performed at the time of the mounting. According to the present invention, after an FPC is mounted, the light emitting device can be peeled and transferred to a flexible substrate. FIG. 7 shows an example where a driver circuit is not provided over a substrate. Hereinafter, an example of a method for manufacturing a light emitting module mounted with an IC chip including a driver circuit is described with reference to FIGS. 8A and 8B. First, a molybdenum film, a molybdenum oxide film, and an insulating film are stacked over a first substrate 701 similarly to Embodiment Mode 2. Over this insulating film, data lines 702 (also functioning as anodes), each of which has a stacked-layer structure of a reflective metal film as a lower layer and a transparent conductive oxide film as an upper layer, are formed. At the same time, connection wirings 708, 709a, and 709b, and input terminals are formed. Next, a partition having openings each corresponding to a pixel 705 is provided. A plurality of inversely tapered partitions 704 parallel to each other are provided over the partition having openings to intersect with the data lines 702. FIG. 8A shows a top view at a stage where the steps up to here are completed. When a stacked film including a light emitting layer, and a transparent conductive film are stacked, they are separated into a plurality of regions which are electrically isolated from each other as shown in FIG. 8B, so that stacked layers each including a light emitting layer, and scan lines 703 made of the transparent conductive film are formed. The scan lines 703 made of the transparent conductive film are electrodes in stripe form which are parallel to each other and extend along a direction intersecting with the data lines 702. Then, a data line side IC 706 and a scan line side IC 707, in each of which a driver circuit for transmitting a signal to the pixel portion is formed, are mounted on the periphery of (outside) the pixel portion by a COG method. The mounting may be performed using TCP or a wire bonding method other than the COG method. TCP is a TAB tape mounted with an IC, and a TAB tape is connected to a wiring over an element formation substrate and an IC is mounted. Each of the data line side IC 706 and the scan line side IC 707 may be formed using a silicon substrate. Alternatively, it may be that a driver circuit is formed using TFTs over a glass substrate, a quartz substrate, or a plastic substrate. Although described here is an example in which a single IC is provided on one side, a plurality of ICs may be provided on one side. Note that the scan lines 703 are electrically connected at their ends to the connection wirings 708, and the connection wirings 708 are connected to the scan line side IC 707. This is because it is difficult to provide the scan line side IC 707 over the inversely tapered partitions 704. The data line side IC 706 provided with the aforementioned structure is connected to an FPC 711 through the connection wirings 709a and an input terminal 710. The scan line side IC 707 is connected to an FPC through the connection wirings 709b and an input terminal. Further, an IC chip 712 (such as a memory chip, a CPU chip, or a power source circuit chip) is mounted to achieve higher integration. Next, a first flexible substrate is fixed using a first adhesive layer to cover the pixel portion. Light emitting elements are peeled from the first substrate 701. Then, a second flexible substrate is fixed using a second adhesive layer to the side on which the peeling has been caused, in order to seal the light emitting device more firmly. FIG. 9 shows an example of a cross-sectional structure after the second flexible substrate is fixed, which is taken along a dashed line C-D of FIG. 8B. A base insulating film 811 is provided over a second flexible substrate 810 with a second adhesive layer 819 interposed therebetween. A lower layer 812 is a reflective metal film, and an upper layer 813 is a transparent conductive oxide film. The upper layer 813 is preferably formed using a conductive film having a high work function. For example, it is possible to use a film including a transparent conductive material such as indium tin oxide (ITO), indium tin oxide containing Si elements (ITSO), or IZO (Indium Zinc Oxide) obtained by mixing indium oxide with zinc oxide (ZnO), or a compound of a combination of such conductive materials. The lower layer 812 is formed using Ag, Al, or an Al alloy film. A partition 814 for insulating between adjacent data lines is made of a resin, and regions surrounded by the partition correspond to and have the same area as light-emitting regions. Scan lines 816 (cathodes) are formed to intersect with data lines (anodes). The scan lines 816 (cathodes) are formed using a transparent conductive film made of ITO, indium tin oxide containing Si elements (ITSO), or IZO obtained by mixing indium oxide with zinc oxide (ZnO). Since this embodiment mode describes an example of a top-emission light emitting device where light is emitted through a first flexible substrate 820, it is important for the scan lines 816 to be transparent. A pixel portion, in which a plurality of light emitting elements are arranged at intersections of the scan lines and the data lines with a stacked film 815 including a light emitting layer interposed therebetween, is sealed with the first flexible substrate 820 and filled with a first adhesive layer 817. The first adhesive layer 817 may be formed using an ultraviolet-curing resin, a thermosetting resin, a silicone resin, an epoxy resin, an acrylic rein, a polyimide resin, a phenol resin, PVC (polyvinyl chloride), PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). A terminal electrode is formed at an end portion of the second flexible substrate 810, and an FPC (flexible printed circuit) 832 to be connected to an external circuit is attached to this portion. Although the terminal electrode is formed by a stack of a reflective metal film 830, a transparent conductive oxide film 829, and a conductive oxide film extending from the scan line 816, or a stack of a reflective metal film 827 and a transparent conductive oxide film 826, the present invention is not particularly limited to this example. The FPC 832 can be mounted by a connecting method using an anisotropic conductive material or a metal bump, or a wire bonding method. In FIG. 9, connection is achieved using an anisotropic conductive adhesive material 831. On the periphery of the pixel portion, an IC chip 823 in which a driver circuit for transmitting a signal to the pixel portion is formed is electrically connected by anisotropic conductive materials 824 and 825. In order to form a pixel portion capable of performing color display, 3072 data lines and 768 scan lines are required for the XGA display class. Such number of the data lines and scan lines are segmented per several blocks at an end portion of the pixel portion and provided with lead wirings, and then gathered in accordance with the pitch of output terminals of ICs. Through the above-described steps, a light emitting module mounted with an IC chip, which is sealed with the second flexible substrate 810 and the first flexible substrate 820, can be manufactured. An IC chip is preferably mounted over a hard first substrate because thermocompression bonding is performed at the time of the mounting. According to the present invention, after an IC chip is mounted, the light emitting module can be peeled and transferred to a flexible substrate. Embodiment Mode 4 This embodiment mode describes an example of manufacturing a semiconductor device which functions as a wireless chip. The semiconductor device described in this embodiment mode has the feature of being capable of reading and writing data without contact. Data transmission methods are broadly classified into three categories: an electromagnetic coupling method in which communication is performed by mutual induction with a pair of coils disposed to face each other; an electromagnetic induction method in which communication is performed by an inductive electromagnetic field; and an electric wave method in which communication is performed by using electric waves. Any of these methods may be employed. An antenna that is used for data transmission can be provided in two ways. One is to provide an antenna over an element substrate provided with a plurality of elements and memory elements, and the other is to provide a terminal portion over an element substrate provided with a plurality of elements and memory elements and connect an antenna provided over another substrate to the terminal portion. Hereinafter, this embodiment mode describes a manufacturing method in the case of connecting an antenna provided over another substrate to a terminal portion over an element substrate. First, a molybdenum film 902 and a molybdenum oxide film 903 are stacked over a heat-resistant substrate 901 similarly to Embodiment Mode 1. FIG. 10A shows a cross-sectional view of the substrate after the steps up to here are completed. A glass substrate is used as the heat-resistant substrate 901. This heat-resistant substrate is not limited to a glass substrate. It is acceptable as long as the substrate withstands a baking temperature (approximately 300° C.) of a conductive layer formed by a coating method and does not change its shape significantly. Note that a plastic substrate with low heat resistance may bend when heat treatment is performed at 300° C. for 30 minutes; therefore, a plastic substrate is unsuitable for the heat-resistant substrate 901. Next, a conductive layer 904 functioning as an antenna is formed over the molybdenum oxide film 903 as shown in FIG. 10B. The conductive layer 904 functioning as an antenna is formed by discharging droplets or a paste including a conductive material such as gold, silver, or copper by a droplet discharge method (such as an ink-jet method or a dispenser method) and drying and baking the droplets or paste. When the conductive layer 904 is formed by a droplet discharge method, the number of steps can be reduced and corresponding cost can also be reduced. Alternatively, the conductive layer 904 may be formed using a screen printing method. In the case of employing a screen printing method, the conductive layer 904 functioning as an antenna is formed by selectively printing a conductive paste in which conductive particles each having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin. As the conductive particle, a fine particle or a dispersive nanoparticle of one or more metals selected from silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo), titanium (Ti), and the like or silver halide can be used. In addition, the organic resin included in the conductive paste can be one or more organic resins each functioning as a binder, a solvent, a dispersant, or a coating of the metal particle. Typically, an organic resin such as an epoxy resin or a silicon resin can be used. In forming the conductive layer, baking is preferably performed after the conductive paste is applied. Alternatively, fine particles mainly containing solder or lead-free solder may be used; in this case, it is preferable to use fine particles each having a particle size of 20 μm or less. Solder or lead-free solder has the advantages of low cost and the like. Other than the above-mentioned materials, ceramic, ferrite, or the like may be used for an antenna. In a case of manufacturing an antenna by a screen printing method or a droplet discharge method, the antenna is formed in a desired shape and then baked. The baking temperature is 200° C. to 300° C. Although the baking is possible at a temperature lower than 200° C., the conductivity of the antenna cannot be secured and the communication distance of the antenna may also be shortened in that case. In view of these points, the antenna is preferably formed over another substrate, that is, a heat-resistant substrate and then peeled and transferred to an element substrate. When a memory element using an organic material is provided over the element substrate, the memory element may change its quality depending on a baking temperature of the antenna, which may affect data writing or the like. In view of this point, it is advantageous to connect an antenna provided over another substrate to a terminal portion of an element substrate. Alternatively, an antenna may be formed using a gravure printing or the like besides a screen printing method or may be formed using a conductive material by a plating method or the like. Since the antenna formed by a plating method may have poor adhesion depending on a plating material or plating conditions, it is effective to use the peeling method of the present invention in which a molybdenum film is used. Next, a flexible substrate 906 is attached using a resin layer 905 in order to protect the conductive layer 904 as shown in FIG. 10C. Then, the heat-resistant substrate 901 and the molybdenum film 902 can be peeled and separated from the molybdenum oxide film 903, the conductive layer 904, the resin layer 905, and the flexible substrate 906 as shown in FIG. 10D. Note that the separation may occur in the molybdenum oxide film 903, at the interface between the molybdenum oxide film 903 and the conductive layer 904, or at the interface between the molybdenum oxide film 903 and the resin layer 905. If sufficient adhesion between the flexible substrate 906 and the conductive layer 904 is secured with the resin layer 905, the peeling can be performed by pulling the flexible substrate 906 after the resin layer 905 is fixed. By the peeling method of the present invention in which a molybdenum film is used, the peeling can be performed only by application of relatively weak force, which leads to an increase in yield. Since only relatively weak force is applied in the peeling method of the present invention in which a molybdenum film is used, a change in shape of the flexible substrate 906 at the time of the peeling can be suppressed and damage to the conductive layer 904 can also be reduced. Then, an element substrate 907 is positioned in contact with a side on which the conductive layer 904 is provided as shown in FIG. 10E. Since the molybdenum oxide film 903 also has a characteristic of a semiconductor, electrical connection can be made when a terminal portion of the element substrate is positioned to overlap the conductive layer 904. It is needless to say that electrical connection between the terminal portion of the element substrate and the conductive layer 904 can be made by pressure bonding using an anisotropic conductive material. FIG. 10E shows an example of providing the element substrate 907 which has a smaller area than the flexible substrate 906; however, there is no particular limitation. An element substrate having approximately the same area as the flexible substrate 906 may be provided, or an element substrate having a larger area than the flexible substrate 906 may be provided. Lastly, another flexible substrate is attached to cover the antenna and the element substrate 907 for protection; thus, a semiconductor device functioning as a wireless chip is completed. Note that the another flexible substrate may be omitted if not necessary. Here, an electromagnetic coupling method or an electromagnetic induction method (for example, a 13.56 MHz band) is employed as the signal transmission method in the semiconductor device. In order to utilize electromagnetic induction caused by a change in magnetic field density, the conductive layer functioning as an antenna in FIG. 10E is formed to have an annular shape (for example, a loop antenna) or a spiral shape when seen from above. However, the shape is not particularly limited. Alternatively, a microwave method (for example, a UHF band (860 to 960 MHz band), a 2.45 GHz band, or the like) can be employed as the signal transmission method in the semiconductor device. In that case, the length, shape, or the like of the conductive layer functioning as an antenna may be appropriately set in consideration of a wavelength of an electromagnetic wave used for signal transmission. Each of FIGS. 11A to 11D shows an example of a conductive layer 912 functioning as an antenna and a chip semiconductor device 913 including an integrated circuit, which are formed over a flexible substrate 911. For example, the conductive layer 912 functioning as an antenna may be formed to have a linear shape (for example, a dipole antenna (see FIG. 11A)), a flat shape (for example, a patch antenna (see FIG. 11B)), or a ribbon shape (see FIG. 11C or 11D) when seen from above. The shape of the conductive layer functioning as an antenna is not limited to a linear shape, and the conductive layer may be formed to have a curved shape, a meander shape, or a combination thereof in consideration of a wavelength of an electromagnetic wave. A structure of the semiconductor device obtained through the above-mentioned steps is described with reference to FIG. 12A. As shown in FIG. 12A, a semiconductor device 1120 obtained according to the present invention functions to exchange data without contact, and includes a power supply circuit 1111, a clock generation circuit 1112, a data demodulation or modulation circuit 1113, a control circuit 1114 which controls another circuit, an interface circuit 1115, a memory circuit 1116, a data bus 1117, an antenna 1118, a sensor 1121, and a sensor circuit 1122. The power supply circuit 1111 generates various kinds of power to be supplied to circuits in the semiconductor device 1120, based on an AC signal inputted from the antenna 1118. The clock generation circuit 1112 generates various kinds of clock signals to be supplied to circuits in the semiconductor device 1120, based on the AC signal inputted from the antenna 1118. The data demodulation or modulation circuit 1113 functions to demodulate or modulate data to be exchanged with a reader/writer 1119. The control circuit 1114 functions to control the memory circuit 1116. The antenna 1118 functions to transmit and receive an electric wave. The reader/writer 1119 communicates with and controls the semiconductor device, and controls the processing of data thereof. Note that the structure of the semiconductor device is not limited to the above structure. For example, the semiconductor device may be additionally provided with another component such as a limiter circuit of power source voltage or hardware dedicated to cryptographic processing. A feature of the memory circuit 1116 is to include a memory element in which an organic compound layer or a phase change layer is interposed between a pair of conductive layers. Note that the memory circuit 1116 may include only the memory element in which an organic compound layer or a phase change layer is interposed between a pair of conductive layers or may include a memory circuit having another structure. The memory circuit having another structure corresponds to one or more of, for example, a DRAM, an SRAM, a FeRAM, a mask ROM, a PROM, an EPROM, an EEPROM, and a flash memory. The sensor 1121 is formed by a semiconductor element such as a resistor element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 1122 detects a change of impedance, reactance, inductance, voltage, or current and outputs a signal to the control circuit 1114 after analog-digital conversion (A/D conversion). This embodiment mode can be freely combined with Embodiment Mode 1 or 2. For example, electrical connection can be made by attachment of a peeled element substrate (flexible substrate) where an integrated circuit is formed using the TFT obtained in Embodiment Mode 1 or 2, and a flexible substrate provided with the antenna obtained in this embodiment mode. According to the present invention, a semiconductor device functioning as a chip including a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The application of the semiconductor device obtained by the present invention is wide-ranging. For example, the semiconductor device of the present invention can be used while being provided in paper money, coins, securities, certificates, bearer bonds, packing containers, books, recording media, personal belongings, vehicles, food, clothing, health products, commodities, medicine, electronic devices, and the like. Paper money and coins are money distributed to the market and include ones valid like money in a certain area (cash voucher), memorial coins, and the like. Securities refer to checks, certificates, promissory notes, and the like, and can be provided with a chip 90 including a processor circuit (see FIG. 13A). Certificates refer to driver's licenses, certificates of residence, and the like, and can be provided with a chip 91 including a processor circuit (see FIG. 13B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 97 including a processor circuit (see FIG. 13C). Bearer bonds refer to stamps, rice coupons, various gift certificates, and the like. Packing containers refer to wrapping paper for food containers and the like, plastic bottles, and the like, and can be provided with a chip 93 including a processor circuit (see FIG. 13D). Books refer to hardbacks, paperbacks, and the like, and can be provided with a chip 94 including a processor circuit (see FIG. 13E). Recording media refer to DVD software, video tapes, and the like, and can be provided with a chip 95 including a processor circuit (see FIG. 13F). Vehicles refer to wheeled vehicles such as bicycles, ships, and the like, and can be provided with a chip 96 including a processor circuit (see FIG. 13G). Food refers to food articles, drink, and the like. Clothing refers to clothes, footwear, and the like. Health products refer to medical instruments, health instruments, and the like. Commodities refer to furniture, lighting equipment, and the like. Medicine refers to medical products, pesticides, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV sets and thin TV sets), cellular phones, and the like. The semiconductor device obtained according to the present invention is fixed to an article by being mounted on a printed board, being attached to a surface of the article, being embedded in the article, or the like. For example, the semiconductor device is fixed to an article by being embedded in paper in the case of a book, or by being embedded in an organic resin in the case of a package made of the organic resin. The semiconductor device of the present invention achieves smallness, thinness, and lightness, and therefore does not harm the design of the article itself. In addition, by providing paper money, coins, securities, bearer bonds, certificates, and the like with the semiconductor devices obtained according to the present invention, an authentication function can be provided, and this authentication function can be utilized to prevent falsification. Further, by providing containers for wrapping, recording media, personal belongings, food, clothing, commodities, electronic devices, and the like with the semiconductor device obtained according to the present invention, a system such as an inspection system becomes more efficient. Next, one mode of the electronic device mounted with the semiconductor device obtained according to the present invention is described with reference to a drawing. The electronic device given as an example here is a cellular phone, which includes casings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 12B). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted into the printed wiring board 2703. The shape and size of the housing 2702 are changed appropriately in accordance with the electronic device into which the panel 2701 is to be incorporated. On the printed wiring board 2703, a plurality of packaged semiconductor devices are mounted; the semiconductor device obtained according to the present invention can be used as one of the packaged semiconductor devices. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any function of a controller, a central processing unit (CPU), a memory, a power supply circuit, an audio processing circuit, a transmitting/receiving circuit, and the like. The panel 2701 is connected to the printed wiring board 2703 via a connection film 2708. The above-described panel 2701, housing 2702, and printed wiring board 2703 are contained together with the operation buttons 2704 and the battery 2705, inside the casings 2700 and 2706. A pixel region 2709 in the panel 2701 is provided so as to be viewed through an opening window provided in the casing 2700. As described above, the semiconductor device obtained according to the present invention has features of being thin and lightweight because a flexible substrate is used. These features make it possible to efficiently use the limited space inside the casings 2700 and 2706 of the electronic device. The semiconductor device of the present invention includes a memory element with a simple structure in which an organic compound layer is interposed between a pair of conductive layers; therefore, an inexpensive electronic device using the semiconductor device can be provided. Note that the shapes of the casings 2700 and 2706 are mere examples of exterior shape of the cellular phone; the electronic devices according to this embodiment mode can be changed into various modes in accordance with the function or application. The present invention with the above-described structure is described more in detail in the following embodiments. Embodiment 1 The liquid crystal display device or the light emitting device obtained according to the present invention can be used for various modules (such as an active-matrix liquid crystal module, an active-matrix EL module, and an active-matrix electrochromic (EC) module). That is, the present invention can be applied to all electronic devices incorporating them in display portions. Examples of such electronic devices are as follows: a camera such as a video camera or a digital camera, a head mounted display (goggle type display), a car navigation system, a projector, a car stereo component, a personal computer, a portable information terminal (a mobile computer, a cellular phone, an electronic book, or the like), and the like. Examples thereof are shown in FIGS. 14A to 14C. FIGS. 14A and 14B each show a television set. A display panel may employ any of the following modes: a case where only a pixel portion is formed and a scan line side driver circuit and a signal line side driver circuit are mounted by a TAB method; a case where only the pixel portion is formed and the scan line side driver circuit and the signal line side driver circuit are mounted by a COG method; a case where a TFT is formed, the pixel portion and the scan line side driver circuit are formed over the same substrate, and the signal line side driver circuit is separately mounted as a driver IC; a case where the pixel portion, the signal line driver circuit, and the scan line driver circuit are formed over the same substrate; and the like. As a structure of another external circuit, a video signal amplifier circuit that amplifies a video signal among signals received by a tuner, a video signal processing circuit that converts the signal outputted from the video signal amplifier circuit into a chrominance signal corresponding to each color of red, green, and blue, a control circuit that converts the video signal into a signal which meets the input specification of a driver IC, and the like are provided on an input side of the video signal. The control circuit outputs respective signals to a scan line side and a signal line side. In a case of digital driving, a signal dividing circuit may be provided on the signal line side and an input digital signal may be divided into a plurality of pieces to be supplied. An audio signal among the signals received by the tuner is transmitted to an audio signal amplifier circuit and the output is supplied to a speaker through an audio signal processing circuit. A control circuit receives control information of a receiving station (reception frequency) or sound volume from an input portion and transmits a signal to the tuner or the audio signal processing circuit. Such a display module is incorporated in a casing as shown in FIG. 14A or 14B, thereby a television device can be completed. A display panel provided with components up to an FPC is also referred to as a display module. A main screen 2003 is formed using the display module, and a speaker portion 2009, an operation switch, and the like are provided as accessory equipment. In such a manner, a television device can be completed. As shown in FIG. 14A, a display panel 2002 using a display element is incorporated in a casing 2001, and general TV broadcast can be received by a receiver 2005. Further, by connection to a communication network with or without wires via a modem 2004, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can also be carried out. The television device can be operated by using a switch built in the casing or a remote control unit 2006. This remote control unit 2006 may also be provided with a display portion 2007 for displaying output information. Further, the television device may include a sub-screen 2008 formed using a second display panel for displaying channels, volume, or the like, in addition to the main screen 2003. In this structure, the main screen 2003 may be formed using an EL display panel having a superior viewing angle, and the sub-screen 2008 may be formed using a liquid crystal display panel capable of displaying images with less power consumption. In order to reduce the power consumption preferentially, the main screen 2003 may be formed using a liquid crystal display panel, and the sub-screen 2008 may be formed using an EL display panel such that the sub-screen can flash on and off. FIG. 14B shows a television device having a large display portion with a size of, for example, 20 to 80 inches. The television device includes a casing 2010, a display portion 2011, a keyboard portion 2012 that is an operation portion, a speaker portion 2013, and the like. The present invention is applied to the manufacturing of the display portion 2011. The display portion of FIG. 14B is formed using a flexible substrate which can be curved; thus, the television device has a curved display portion. Since the shape of a display portion can be freely designed as described above, a television device having a desired shape can be manufactured. Since the display device can be formed through a simplified process in accordance with the present invention, a cost reduction can also be achieved. Therefore, the television device using the present invention can be formed at low cost even when formed to have a large-area display portion. It is needless to say that the present invention is not limited to the television device, and can be applied to various uses as large-area display media such as an information display board at a train station, an airport, or the like, and an advertisement display board on the street, as well as a monitor of a personal computer. FIG. 14C shows a portable information terminal (electronic book device), which includes a main body 3001, display portions 3002 and 3003, a memory medium 3004, an operating switch 3005, an antenna 3006, and the like. The peeling method of the present invention can be applied to the display portions 3002 and 3003. The weight of the portable information terminal can be reduced by using a flexible substrate. When an antenna is formed over a flat substrate and incorporated instead of the antenna shown in FIG. 14C, the peeling method of the present invention can be employed. This embodiment can be freely combined with any one of Embodiment Modes 1 to 3. Embodiment 2 This embodiment describes an example of using an electrophoretic display device as the display portion described in Embodiment 1. Typically, an electrophoretic display device is applied to the display portion 3002 or the display portion 3003 of the portable information terminal (electronic book device) shown in FIG. 14C. The electrophoretic display device (electrophoretic display) is also called electronic paper and has the advantage of being as easy as paper to be read, and consuming less power and being thinner and lighter in weight than other display devices. A variety of modes of electrophoretic displays can be considered, but the electrophoresis display of this embodiment is a device in which a plurality of microcapsules each including first particles having a positive charge and second particles having a negative charge are dispersed in a solvent or a solute, and an electrical field is applied to the microcapsules so that the particles in the microcapsules move in opposite directions from each other, and only a color of the particles gathered on one side is displayed. Note that the first particles or the second particles include a dye, and does not move in a case where there is no electric field. Also, the first particles have a color which is different from that of the second particles (the particles may also be colorless). Thus, the electrophoretic display utilizes a so-called dielectrophoretic effect, in which a substance with high dielectric constant moves to a region with high electric field. The electrophoretic display does not require a polarizing plate and an opposite substrate, which are necessary for a liquid crystal display device, so that the thickness and weight thereof are about half. That which the microcapsules are dispersed in a solvent is called electronic ink, and this electronic ink can be printed on a surface of glass, plastic, fabric, paper, or the like. Color display is also possible with the use of a color filter or particles including a coloring matter. In addition, a display device can be completed by appropriately providing a plurality of the microcapsules over a substrate to be interposed between two electrodes, and can perform display by application of electric field to the microcapsules. For example, the active-matrix substrate obtained in Embodiment Mode 1 can be used. Although electronic ink can be printed directly over a plastic substrate, it is preferable in a case of the active-matrix type to form an element and electronic ink over a glass substrate, peel the glass substrate, and attach the element and the electronic ink to a plastic substrate that is a flexible substrate according to Embodiment Mode 1 or 2, rather than forming an element over a plastic substrate which is sensitive to heat and an organic solvent. This is because a manufacturing process can be carried out under a wide range of conditions. Note that the first particles and the second particles in the microcapsule may be formed of one of a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophoretic material or a composite material thereof. This embodiment can be freely combined with any one of Embodiment Modes 1 to 3 and Embodiment 1. According to the present invention, an element such as a TFT formed using an existing manufacturing apparatus for a large glass substrate can be transferred to a flexible substrate. Therefore, equipment cost can be significantly reduced. In addition, the peeling method of the present invention has almost no limitation on a process; accordingly, various elements can be transferred to a flexible substrate. This application is based on Japanese Patent Application serial no. 2006-126708 filed in Japan Patent Office on Apr. 28, 2006, the entire contents of which are hereby incorporated by reference.	H	67H01	185H01L	21	30
11962386	US20080268624A1-20081030	Method of Fabricating Semiconductor Device	ACCEPTED	20081016	20081030	[]	H01L21425	["H01L21425"]	7858491	20071221	20101228	438	433000	96173.0	NICELY	JOSEPH	[{"inventor_name_last": "Kwak", "inventor_name_first": "Noh Yeal", "inventor_city": "Icheon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Jang", "inventor_name_first": "Min Sik", "inventor_city": "Icheon-si", "inventor_state": "", "inventor_country": "KR"}]	This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore stress remaining within the semiconductor substrate may be minimized. Accordingly, Number Of Program (NOP) fail by disturbance caused by stress remaining within a channel junction may be reduced. Further, a broad doping profile may be formed at the interface of trenches by using BF2 as the dopant when the P well is formed. A fluorine getter layer may be formed on an oxide film of the trench sidewalls and may be used as a boron diffusion barrier. Although a Spin On Dielectric (SOD) insulating layer may be used as an isolation layer, loss of boron (B) may be prevented. Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted and a NOP disturbance characteristic may be improved.	1. A method of fabricating a semiconductor device, the method comprising: forming a Triple N (TN) well in a semiconductor substrate; forming a P well within the TN well by employing a zero tilt-angle; forming an isolation mask over the semiconductor substrate; etching the isolation mask and the semiconductor substrate of an isolation region, thus forming trenches within the P well; and forming isolation layers that gap fills the trenches. 2. The method of claim 1, further comprising forming a screen oxide layer over the semiconductor substrate to a thickness of approximately 300 to 500 angstrom. 3. The method of claim 1, wherein the TN well is formed using an ion implantation process. 4. The method of claim 3, wherein the ion implantation process is performed using ion implantation energy of approximately 800 to 2000 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2 by applying a N type dopant at a tilt angle of approximately 2 to 10 degrees. 5. The method of claim 1, further comprising performing an annealing process at a temperature ranging from 900 to 1000 degrees Celsius after the TN well is formed. 6. The method of claim 1, wherein the P well is formed by an ion implantation process. 7. The method of claim 6, wherein the ion implantation process is performed using ion implantation energy of 200 to 500 keV with a dose of 1×1011 to 1×1014 ions/cm2 using boron difluoride (BF2) as a dopant. 8. The method of claim 6, wherein the ion implantation process is performed in a single type. 9. The method of claim 1, further comprising forming an ion implantation region for threshold voltage control within the P well after the P well is formed. 10. The method of claim 9, wherein a threshold voltage control using boron (B) ion implantation, thus forming an ion implantation region. 11. The method of claim 10, wherein the ion implantation process is performed using ion implantation energy of 5 to 50 keV with a dose of 1×1011 to 1×1014 ions/cm2 by using BF2 as a dopant. 12. The method of claim 1, further comprising forming an ion implantation region for compensating for boron (B) on sidewalls of the trenches after the trenches are formed. 13. The method of claim 12, wherein the ion implantation region for boron (B) compensation is formed by an ion implantation process using ion implantation energy of 5 to 50 keV with a dose of 1×1011 to 1×1014 ions/cm2 by using boron (B) as a dopant. 14. The method of claim 12, wherein the ion implantation region for boron (B) compensation is formed using an ion implantation process in nitrogen (N2) gas atmosphere. 15. The method of claim 1, further comprising forming an oxide film on sidewalls of the trenches. 16. The method of claim 16, wherein a fluorine getter layer in which fluorine ions (F-) implanted when the P well is formed are condensed is formed on the oxide film of the trenches sidewalls. 17. The method of claim 1, wherein the formation of the isolation layer comprising: forming an insulating layer by depositing an insulating material on the patterned isolation mask, including the trenches, so that the trenches are gap filled; and etching the insulating layer until a surface of the isolation mask is exposed. 18. The method of claim 1, wherein the isolation layer is formed from a Spin on Dielectric (SOD) insulating layer. 19. The method of claim 18, wherein the process of forming the SOD insulating layer comprises a SOD coating process, a baking process, and a curing process. 20. The method of claim 19, wherein the SOD coating process is performed using a polysilazane (PSZ)-based material. 21. The method of claim 19, wherein the baking process is performed at a temperature ranging from 50 to 250 degrees Celsius. 22. The method of claim 19, wherein the curing process is performed at a temperature ranging from 200 to 400 degrees Celsius.	<SOH> BACKGROUND OF THE INVENTION <EOH>Generally, in a semiconductor device, a well junction may be formed by performing an ion implantation process in order to control the threshold voltage of a transistor. In recent years, as devices are highly integrated, the well junction may be formed by implanting an impurity of a high concentration so as to secure the characteristics of the transistor when the ion implantation process is performed. Further, in forming a Shallow Trench Isolation (STI) layer a STI structure in which trenches may be formed in a semiconductor substrate and then gap filled with an insulating material may be used rather than an existing LOCal Oxidation of Silicon (LOCOS) structure. Thus, etch damage to sidewall of a silicon (Si) substrate due to excessive Si etch is inevitable. Stress within a channel junction may be increased by implant damage. The increased stress grows into defects due to a subsequent annealing process, thus generating disturbances caused by Transit Enhanced Diffusion (TED). In the case of a flash memory device on which program and erase may be performed using channel boosting, Number Of Program (NOP) fail occurs due to the existence of disturbances within the channel junction. This becomes more severe at certain portions, which becomes a cause of remaining stress within an active region. Further, a method of gap filling trenches using a Spin on Dielectric (SOD) material as a trench gap-fill material has recently been introduced because of the trench gap-fill limits of a High Density Plasma (HDP) oxide film. In particular, there is a method of fully gap filling trenches using polysilazane (PSZ) that has a low viscosity and a flowing property like water. However, if the trenches are gap filled with the SOD material, dopant segregation may be increased due to the stress of the material and a subsequent annealing process. Accordingly, the leakage current may be increased due to the occurrence of hump. Furthermore, compensation for the lost dopant through additional ion implantation may cause cell disturbances to further increase.	<SOH> SUMMARY OF THE INVENTION <EOH>This invention is directed to a method of fabricating a semiconductor device wherein a P well is formed by performing an ion implantation process at a zero tilt condition, so that a stress caused by collision of a dopant and a Si lattice may be minimized. NOP fail due to disturbance caused by stress remaining within a channel junction of a semiconductor substrate may be reduced. A method of fabricating a semiconductor device according to one embodiment, includes: forming a Triple N (TN) well in a semiconductor substrate, forming a P well within the TN well region by performing an ion implantation process employing a zero tilt condition, forming an isolation mask over the semiconductor substrate, etching the isolation mask and the semiconductor substrate of an isolation region, thus forming trenches within the P well region, and forming isolation layers that gap fills the trenches. In one embodiment, a screen oxide layer may be further formed over the semiconductor substrate to a thickness of approximately 300 to 500 angstrom. The TN well may be formed using an ion implantation process employing ion implantation energy of approximately 800 to 2000 keV with a dose of approximately 1×10 11 to 1×10 14 ions/cm 2 by applying a N type dopant at a tilt condition of approximately 2 to 10 degrees. An annealing process may be further performed, for example, using furnace annealing at a temperature ranging from 900 to 1000 degrees Celsius after the TN well is formed. In one embodiment, the P well may be formed by performing the ion implantation process using boron difluoride (BF 2 ) as a dopant. The ion implantation process may be performed using ion implantation energy of approximately 200 to 500 keV with a dose of approximately 1×10 11 to 1×10 14 ions/cm 2 . The ion implantation process may be performed in a single type. An ion implantation region for threshold voltage control may be further formed within the P well region by performing the ion implantation process using ion implantation energy of approximately 5 to 50 keV with a dose of approximately 1×10 11 to 1×10 14 ions/cm 2 by using BF 2 as a dopant. In one embodiment, an ion implantation region for compensating for boron (B) may be further formed on sidewalls of the trenches. The ion implantation region for boron (B) compensation may be formed by performing the ion implantation process using ion implantation energy of approximately 5 to 50 keV with a dose of 1×10 11 to 1×10 14 ions/cm 2 by using boron (B) as a dopant. Alternatively, the ion implantation region for boron (B) compensation may be formed by performing the ion implantation process in nitrogen (N 2 ) gas atmosphere. In one embodiment, an oxide film may be further formed on sidewalls of the trenches. A fluorine getter layer in which fluorine ions (F-) implanted when the P well is formed are condensed may be formed on the oxide film of the trenches sidewalls. The formation of the isolation layer may include: forming an insulating layer by depositing an insulating material on the patterned isolation mask, including the trenches so that the trenches are gap filled, and etching the insulating layer until a surface of the nitride film of the isolation mask is exposed. In one embodiment, the isolation layer may be formed from a Spin on Dielectric (SOD) insulating layer. The process of forming the SOD insulating layer may include a SOD coating process, a baking process, and a curing process. The SOD coating process may be performed using a polysilazane (PSZ)-based material. The baking process may be performed at a temperature ranging from 50 to 250 degrees Celsius. The curing process may be performed at a temperature ranging from 200 to 400 degrees Celsius.	CROSS-REFERENCES TO RELATED APPLICATIONS This invention claims priority to Korean patent application number 10-2007-41414, filed on Apr. 27, 2007, the disclosure of which is incorporated by reference in its entirety. TECHNICAL FIELD This invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device with improved disturbance characteristic. BACKGROUND OF THE INVENTION Generally, in a semiconductor device, a well junction may be formed by performing an ion implantation process in order to control the threshold voltage of a transistor. In recent years, as devices are highly integrated, the well junction may be formed by implanting an impurity of a high concentration so as to secure the characteristics of the transistor when the ion implantation process is performed. Further, in forming a Shallow Trench Isolation (STI) layer a STI structure in which trenches may be formed in a semiconductor substrate and then gap filled with an insulating material may be used rather than an existing LOCal Oxidation of Silicon (LOCOS) structure. Thus, etch damage to sidewall of a silicon (Si) substrate due to excessive Si etch is inevitable. Stress within a channel junction may be increased by implant damage. The increased stress grows into defects due to a subsequent annealing process, thus generating disturbances caused by Transit Enhanced Diffusion (TED). In the case of a flash memory device on which program and erase may be performed using channel boosting, Number Of Program (NOP) fail occurs due to the existence of disturbances within the channel junction. This becomes more severe at certain portions, which becomes a cause of remaining stress within an active region. Further, a method of gap filling trenches using a Spin on Dielectric (SOD) material as a trench gap-fill material has recently been introduced because of the trench gap-fill limits of a High Density Plasma (HDP) oxide film. In particular, there is a method of fully gap filling trenches using polysilazane (PSZ) that has a low viscosity and a flowing property like water. However, if the trenches are gap filled with the SOD material, dopant segregation may be increased due to the stress of the material and a subsequent annealing process. Accordingly, the leakage current may be increased due to the occurrence of hump. Furthermore, compensation for the lost dopant through additional ion implantation may cause cell disturbances to further increase. SUMMARY OF THE INVENTION This invention is directed to a method of fabricating a semiconductor device wherein a P well is formed by performing an ion implantation process at a zero tilt condition, so that a stress caused by collision of a dopant and a Si lattice may be minimized. NOP fail due to disturbance caused by stress remaining within a channel junction of a semiconductor substrate may be reduced. A method of fabricating a semiconductor device according to one embodiment, includes: forming a Triple N (TN) well in a semiconductor substrate, forming a P well within the TN well region by performing an ion implantation process employing a zero tilt condition, forming an isolation mask over the semiconductor substrate, etching the isolation mask and the semiconductor substrate of an isolation region, thus forming trenches within the P well region, and forming isolation layers that gap fills the trenches. In one embodiment, a screen oxide layer may be further formed over the semiconductor substrate to a thickness of approximately 300 to 500 angstrom. The TN well may be formed using an ion implantation process employing ion implantation energy of approximately 800 to 2000 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2 by applying a N type dopant at a tilt condition of approximately 2 to 10 degrees. An annealing process may be further performed, for example, using furnace annealing at a temperature ranging from 900 to 1000 degrees Celsius after the TN well is formed. In one embodiment, the P well may be formed by performing the ion implantation process using boron difluoride (BF2) as a dopant. The ion implantation process may be performed using ion implantation energy of approximately 200 to 500 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2. The ion implantation process may be performed in a single type. An ion implantation region for threshold voltage control may be further formed within the P well region by performing the ion implantation process using ion implantation energy of approximately 5 to 50 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2 by using BF2 as a dopant. In one embodiment, an ion implantation region for compensating for boron (B) may be further formed on sidewalls of the trenches. The ion implantation region for boron (B) compensation may be formed by performing the ion implantation process using ion implantation energy of approximately 5 to 50 keV with a dose of 1×1011 to 1×1014 ions/cm2 by using boron (B) as a dopant. Alternatively, the ion implantation region for boron (B) compensation may be formed by performing the ion implantation process in nitrogen (N2) gas atmosphere. In one embodiment, an oxide film may be further formed on sidewalls of the trenches. A fluorine getter layer in which fluorine ions (F-) implanted when the P well is formed are condensed may be formed on the oxide film of the trenches sidewalls. The formation of the isolation layer may include: forming an insulating layer by depositing an insulating material on the patterned isolation mask, including the trenches so that the trenches are gap filled, and etching the insulating layer until a surface of the nitride film of the isolation mask is exposed. In one embodiment, the isolation layer may be formed from a Spin on Dielectric (SOD) insulating layer. The process of forming the SOD insulating layer may include a SOD coating process, a baking process, and a curing process. The SOD coating process may be performed using a polysilazane (PSZ)-based material. The baking process may be performed at a temperature ranging from 50 to 250 degrees Celsius. The curing process may be performed at a temperature ranging from 200 to 400 degrees Celsius. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 11 are sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the invention. DETAILED DESCRIPTION Now, specific embodiments according to the present invention will now be described in further details with reference to the accompanying drawings. While the invention is susceptible to various manners, certain embodiments as shown by way of example in the drawings and these embodiments will be described in detail herein. It will be understood, however, that this disclosure is not intended to limit the invention to the particular forms described, but to the contrary, the invention is intended to cover all modifications, alternatives, and equivalents falling within the spirit and scope of the invention defined by the appended claims. Referring to FIG. 1A, a screen oxide layer 102 is formed over a semiconductor substrate 100. The screen oxide layer 102 may be formed, for example, using an oxidation process, preferably, a wet oxidization process at a temperature ranging from 750 to 800 degrees Celsius. Other types of oxidation techniques may be used. The screen oxide layer 102 may be formed to a thickness of approximately 300 to 500 angstrom in order to prevent an ion channeling when forming a P well (See FIG. 1B). A Triple N (TN) well 104 may be formed, for example, using an ion implantation process employing an ion implantation energy of approximately 800 to 2000 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2, for example, by applying a N type dopant having a tilt-angle of approximately 2 to 10 degrees such that a concentration at a Projected Range (Rp) may be maximized for clarifying the boundary between the TN well 104 and the P type semiconductor substrate 100. To compensate for damaging the semiconductor substrate 100 due to the high-energy ion implantor when forming the TN well 104, an annealing process may be performed, preferably, a furnace annealing process at a temperature ranging from 900 to 1000 degrees Celsius. Other types of annealing techniques may be used. Referring to FIG. 1B, a P well 106 is formed within the TN well 104 by performing, for example, an ion implantation process at a zero tilt-angle. The ion implantation process may be performed using ion implantation energy of approximately 200 to 500 keV with a dose of approximately 1÷1011 to 1×1014 ion/cm2, for example, using boron difluoride (BF2) as a dopant. The zero tilt-angle ion implantation refers to an angle where an impurity (dopant) is implanted being substantially vertical to the semiconductor substrate 100. Further, the zero tilt-angle ion implantation may be performed in a single type in order to maximize the uniformity of doping within the large-sized semiconductor substrate 100. Thus, collision between the dopant and the silicon (Si) lattice within the semiconductor substrate 100 may be minimized, and stress within the P well 106 may be minimized. Accordingly, NOP fail by disturbance caused by stress remaining due to collision may be prevented and a cell disturbance characteristic may be improved. Further, the ion implantation process for forming the P well 106 may be performed using BF2, having a mass greater than boron (B), as a dopant in a single type. Thus, a broad doping profile may be formed at interface sidewalls of trenches (as shown in FIG. 1E), so that abnormal channeling, which may occur due to the zero tilt-angle may be minimized. Meanwhile, when the broad doping profile is formed, an end of range (EOR) defect-caused profile within the semiconductor substrate 100 may become a broad profile. Referring to FIG. 1C, in order to control the threshold voltage (Vth) of a transistor, an ion implantation process employing a P type dopant may be further carried out. The ion implantation process may be performed using an ion implantation energy of approximately 5 to 50 keV with a dose of approximately 1×1011 to 1×1014 ions/cm2, for example, by using BF2 as a dopant. Thus, an ion implantation region 108 for threshold voltage control may be formed on an upper side of the P well 106 and within the P well 106. Referring to FIG. 1D, the screen oxide layer 102 is removed, for example, by performing an etching process. The screen oxide layer 102 may be removed, for example, using a wet etching process, for example, employing buffered oide etchant (BOE) or diluted solution of HF (DHF). Other types of etchant may be used. An isolation mask 116 for forming an isolation layer of a STI structure may be formed over the semiconductor substrate 100, including upper surfaces of the TN well 104 and the P well 106. The isolation mask 116 may include a buffer oxide film 110, a nitride film 112 and a hard mask 114. The buffer oxide film 110 may be formed, for example, from silicon oxide (SiO2), for example, using an oxidization process. The nitride film 112 may be formed from a nitride-based material, for example, silicon nitride (SixNy) or silicon oxynitride (SiON). The hard mask 114 may be formed, for example, from oxide-based or carbon polymer-based material. The nitride film 112 and the hard mask 114 may be formed, for example, using a chemical vapor deposition (CVD) method. Other types of technique may be used. Referring to FIG. 1E, the isolation mask 116 formed over an isolation region may be partially removed, for example, using an etching process, for example, employing a photoresist patterned isolation mask (not shown), such that at least a surface of the ion implantation region 108, the P well 106, the TN well 104, and the semiconductor substrate 100 of the isolation region are exposed. The isolation region may be etched to a thickness, thereby The isolation region of the exposed semiconductor substrate 100 may be etched to a specific thickness using an etch process employing the patterned isolation mask 116 as a mask, thus forming a plurality of trenches 118 in the isolation region. The photoresist mask (not shown) may be formed by coating a photoresist on the hard mask 114 to form a photoresist film and then performing exposure and development employing a previously designed mask. The photoresist pattern may be removed through etching in the process of forming the trenches 118, or may be removed through an additional etching process when the photo mask is to remain on the isolation region. Other techniques may be substituted without varying from the scope of the invention. Referring to FIG. 1F, an ion implantation process may be performed to compensate for loss of boron (B) ions and thus prevent hump. As shown, an ion implantation region 120 for B ions compensation may be formed on sidewalls of the trenches 118. The ion implantation process may be performed using an ion implantation energy of approximately 5 to 50 keV with a dose of 1×1011 to 1×1014 ions/cm2, for example, by using B as a dopant. The ion implantation process may be performed, for example, in nitrogen (N2) gas atmosphere in order to form Si—N bonding in the semiconductor substrate 100. Referring to FIG. 1G, an oxide film 122 may formed on the sidewalls of the trenches 118, including the ion implantation 108, the P well 106, and the TN well 104 to compensate for etch damage occurred when the trenches 118 are formed, and to help prevent fail bits due to the stress of the gap-fill material of the trenches 118, an oxide film 122 is formed on the sidewalls of the trenches 1 18. The oxide film 122 may be formed, for example, from silicon oxide (SiO2) using a wet oxidization process at a temperature ranging from 750 to 800 degrees Celsius to prohibit the behavior of the dopant for threshold voltage control to the greatest extent. Alternatively, the oxide film 122 may be formed on the exposed surfaces of the buffer oxide film 110, the nitride film 112, and the hard mask 114 when the oxidization process is performed. The oxide film 122 formed on the side walls of the exposed surfaces of the buffer oxide film 110, the nitride film 112, and the hard mask 114 may be thinner compared with the oxide film 122 formed on the sidewall of the trenches 118. A fluorine getter layer (not shown) in which fluorine ions (F-) implanted when forming the P well 106 are condensed, may be formed at an interface (an interface of Si/SiO2) of the trenches 118 and the oxide film 122 due to oxidation enhanced diffusion (OEF). Getter broun (B) may be gathered by the fluorine getter layer formed in the oxide film 122 of trenches 118, thus preventing the leakage current of a cell region. Further, P type getters that are not caused by remnant rebonding within the cell region may be generated, thereby removing stress of the semiconductor substrate 100. Referring to FIG. 1H, an insulating layer 124 may be deposited on the patterned isolation mask 116, including the trenches 118, so that the trenches 118 are gap filled. The insulating layer 124 may be formed, for example, from a SOD insulating layer having a good flow property and a trench gap-fill characteristic, using a SOD method. Other types of film deposition may be used. The SOD insulating layer 124 may be formed, for example, from a PSZ-based material, thus gap fill the trenches 118 without void. The process of forming the SOD insulating layer 124 may include an optional baking process, a curing process, and a coating process. The baking process for hardening a coated film may be performed at a temperature ranging from 50 to 250 degrees Celsius. The curing process for out-gasing impurities gas included in the PSZ layer and densifying the film quality may be performed at a temperature ranging from 200 to 400 degrees Celsius so that bending may be prevented in the active region of the semiconductor substrate 100 due to internal stress of the isolation region. Referring to FIG. 1I, the insulating layer 124 over the isolation mask 116 may be etched until a surface of the nitride film 112 of the isolation mask 116 is exposed, leaving the insulating layer 124 within the trench 118 un-etched, defining isolation layers 124a. The etching process may be performed, for example, using a CMP process. In order to control the Effective Field oxide Height (EFH), at least a portion of the isolation layer 124a may be etched, for example, using a dry etch process or a wet etch process. To prevent lowering of a cycling characteristic. The isolation layer 124a may be etched to a thickness substantially the same or higher than the semiconductor substrate 100. The nitride film 112 may be removed completely, for example, using a phosphoric acid (H3PO4) after the etching process. The buffer oxide film 110 may also be removed when the process of removing the nitride film 112 is performed. A cleaning process, for example, using BOE or DHF may be performed to completely remove the buffer oxide film 110 that remains during the process of removing the nitride film 112 and the buffer oxide film 110. Though not shown in the drawings, a tunnel insulating film and a conductive layer for a floating gate may be formed over the semiconductor substrate 100 and then patterned. A dielectric layer and the conductive layer for a control gate may be laminated over the semiconductor substrate 100 and then patterned, thus forming a gate consisting of the tunnel insulating film, the floating gate, the dielectric layer and a control gate. Subsequent processes are then performed. As described above, in the method of fabricating the semiconductor device according to a preferred embodiment of the invention, the P well for the cell junction may be formed by performing the ion implantation process employing the zero tilt-angle. Thus, stress caused by collision between a dopant and the Si lattice within the semiconductor substrate may be minimized and any stress remaining within the semiconductor substrate may be minimized. Accordingly, NOP fail by disturbance caused by stress remaining within the channel junction may be reduced. A broad doping profile may be formed at the interface of the trenches by using BF2 as the dopant when the P well is formed. The fluorine getter layer may be formed on the oxide film of the trench sidewalls and may be used as a boron diffusion barrier. A SOD insulating layer may be used as an isolation layer so as to prevent from loss of boron (B). Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted and a NOP disturbance characteristic may be improved. Further, the leakage current of the cell region may be prevented when the boron (B) is gettered by the fluorine getter layer formed in the oxide film of the trench sidewalls. Any P type getters that are not caused by remaining rebonding within the cell region may be generated. The isolation layer formed from the SOD insulating layer, thus improving a trench gap-fill capability and the reliability of devices. Accordingly, an additional ion implantation process for compensating for lost boron (B) may be omitted, thus simplifying the whole process.	H	67H01	185H01L	214	25
11752955	US20080001284A1-20080103	Heat Dissipation Structure With Aligned Carbon Nanotube Arrays and Methods for Manufacturing And Use	ACCEPTED	20071218	20080103	[]	H01L23373	["H01L23373", "C01B3102"]	8890312	20070524	20141118	257	712000	67733.0	NGUYEN	DUY	[{"inventor_name_last": "Yuen", "inventor_name_first": "Matthew", "inventor_city": "Hong Kong", "inventor_state": "", "inventor_country": "CN"}, {"inventor_name_last": "Zhang", "inventor_name_first": "Kai", "inventor_city": "Hong Kong", "inventor_state": "", "inventor_country": "CN"}]	A heat dissipation structure with aligned carbon nanotube arrays formed on both sides. The carbon nanotube arrays in between a heat source and a cooler are used as thermal interface material extending and dissipating heat directly from a heat source surface to a cooler surface. In some embodiments, an adhesive material can be used to dispense around carbon nanotube arrays and assemble the heat dissipation structure in between a heat source and a cooler. In some other embodiments, carbon nanotube arrays are formed on at least one of a heat source surface and a cooler surface and connect them together by further growing. The carbon nanotube arrays can be exposed to the environment instead of being in between a heat source and a solid cooler, and can serve as fins to enlarge heat dissipation area and improve thermal convection.	1. A packaged semiconductor structure, comprising: a heat source; a heat sink; an aligned array of carbon nanotubes which thermally connects said source to said sink; and a peripheral connecting material which runs along at least some edges of said aligned array, while mechanically contacting said source and said sink to provide a fixed positional relationship there between. 2. The packaged semiconductor structure of claim 1, wherein the heat sink is an electronic structure which dissipates heat when operating. 3. The packaged semiconductor structure of claim 1, wherein the heat sink comprises a high thermal conductivity substrate; and a plurality of carbon nanotube arrays are grown on both sides of the substrate. 4. The packaged semiconductor structure of claim 1, wherein said heat sink comprises a metal substrate. 5. The packaged semiconductor structure of claim 1, wherein said carbon nanotube arrays are synthesized by chemical vapor deposition. 6. The packaged semiconductor structure of Claim 1, wherein said heat sink carries said aligned carbon nanotube arrays in a patterned configuration. 7. The packaged semiconductor structure of Claim 1, wherein said heat sink carries said aligned array of carbon nanotubes in a patterned configuration which is determined by patterning of a preformed catalyst. 8. The packaged semiconductor structure of Claim 1, wherein said heat sink carries said aligned array of carbon nanotubes in a patterned configuration which is determined by patterning of a modification layer when using a sublimed catalyst. 9. The packaged semiconductor structure of Claim 1, wherein said heat sink carries said aligned array of carbon nanotubes, some of which are patterned to form fins for convective cooling. 10. The packaged semiconductor structure of Claim 1, wherein said heat source is an electronic structure which generates heat when operating. 11. A packaged semiconductor structure, comprising: an extended structure which carries heat; and first and second mutually separate aligned carbon nanotube arrays which are thermally connected to opposite surfaces of said extended structure; wherein said first array terminates in a connection to another heat-conducting structure, and said second array terminates in bare carbon nanotube ends. 12. The packaged semiconductor structure of Claim 11, wherein the extended structure is an electronic structure which dissipates heat when operating. 13. The packaged semiconductor structure of Claim 11, wherein the extended structure comprises a high thermal conductivity substrate, and a plurality of carbon nanotube arrays are grown on both sides of the substrate. 14. The packaged semiconductor structure of Claim 11, wherein the extended structure comprises a metal substrate. 15. The packaged semiconductor structure of Claim 11, wherein said aligned carbon nanotube arrays are synthesized by chemical vapor deposition. 16. The packaged semiconductor structure of Claim 11, wherein said extended structure carries the aligned carbon nanotube arrays in a patterned configuration. 17. The packaged semiconductor structure of Claim 11, wherein said extended structure carries the aligned carbon nanotube arrays in a patterned configuration which is determined by patterning of a preformed catalyst. 18. The packaged semiconductor structure of Claim 11, wherein said extended structure carries the aligned carbon nanotube arrays in a patterned configuration which is determined by patterning of a modification layer when using a sublimed catalyst. 19. The packaged semiconductor structure of Claim 11, wherein said extended structure carries the aligned carbon nanotube arrays, some of which are patterned to form fins for convective cooling. 20. A method of transferring heat from a microelectronic heat source, comprising: conducting heat through an array of aligned nanotube fibers; separating a heat source and heat sink by placing a spacer in a positional relationship with the heat source and heat sink; and mechanically stabilizing the position of the heat source relative to the heat sink, using an adhesive material. 21-57. (canceled)	<SOH> BACKGROUND OF THE INVENTIONS <EOH>The present application generally relates to thermal management solutions, and more specifically to heat dissipation structures using aligned carbon nanotube arrays, and to methods of fabricating such a heat dissipation structure and applying it to a package. With the development of microelectronic systems, for example, high brightness light emitting diode (HB-LED) for solid-state lighting, significant challenges of thermal management have to be faced to meet the increasing requirements of smaller profile, higher performance and longer product life time. More heat generated by devices needs to be effectively dissipated from a smaller area. Several kinds of heat sink are developed to expect to dissipate more heat from device to the environment. However it is very important to first conduct heat from device to heat sink by thermal interface materials. Unfortunately, conventional thermal interface materials, such as thermal grease thermal adhesives, phase change materials, etc., cannot meet the increasing requirement of the heat dissipation from a small area. Carbon nanotube (CNT) is an attractive candidate to improve the thermal performance of thermal interface materials because of their ultrahigh thermal conductivity up to 3000 W/m·K for multi-walled carbon nanotube (MWNT). Further information regarding CNT properties may be found in the Journal of the American Physical Society, Physical Review Letters , Vol. 87, page 215502 (2001), herein incorporated by reference. However thermal interface materials with randomly directed carbon nanotubes dispersed in epoxy resins or other matrix materials does not perform well because of the highly anisotropic nature of the thermal conduction by carbon nanotubes. Aligned carbon nanotube arrays directly extending from a first surface, for example a heat source surface, to a second surface, for example a cooler surface, is expected. U.S. Pat. No. 6,965,513 and U.S. Pat. No. 6,924,335, incorporated by reference herein for all purposes, disclose thermal interface materials with carbon nanotube bundles embedded in matrix materials. However, the phonon heat transfer modes in matrix materials and carbon nanotubes are not compatible, which significantly limits the advantage of heat conduction by carbon nanotube. In addition, solidified matrix material is less flexible to fill in the uneven surfaces of heat source and heat sink. As a result, the thermal conductivity of thermal interface material with aligned carbon nanotube arrays in matrix is only 1.21 W/m·K and the contact thermal resistance is more than 50 mm 2 ·K/W. Additional information regarding the thermal conductivity of thermal interface materials are detailed in Advanced Materials, Vol. 17, page 1652 (2005) incorporated by reference herein. U.S. Pat. No. 6,856,01 and U.S. Patent Application Publication US 2004/0150100, both incorporated by reference herein for all purposes, disclose a thermal interface layer with carbon nanotubes grown on the surface of semiconductor die. However, the processes are not compatible for carbon nanotubes synthesis and device fabrication. If carbon nanotubes are grown before device fabrication, the decreased wafer cleanliness and ability to protect carbon nanotubes will make it difficult to conduct device fabrication using normal processes and equipments. Alternatively, if a device is fabricated before carbon nanotubes growth, the high temperature required by growing carbon nanotubes will damage the device or increasing the device cost by changing the processes and materials. As for the connecting methods, U.S. Patent Application Publication U.S. 2004/0261987, incorporated by reference herein for all purposes, use an adhesion promoting layer to connect heat source and the array of carbon nanotubes. However, it is very difficult to form a very thin layer so that the tips of carbon nanotubes can still make contact with the heat source surface. As a result, there is actually another added layer with additional thermal resistance, which reduces the thermal performance of the thermal management solution. In U.S. Pat. No. 6,891,724, incorporated by reference herein for all purposes, carbon nanotubes grown from the opposed surfaces intermesh as the surfaces are mated. However, it is difficult for carbon nanotubes from any surface to extend directly to the other surface.	<SOH> SUMMARY OF THE INVENTIONS <EOH>The present inventions provide a new way to use high thermal conductivity carbon nanotube (CNT) arrays. To avoid the process incompatibility of carbon nanotube growth and device fabrication the aligned CNT arrays are formed on heat dissipation structure surfaces instead of a heat source surface. To simplify the fabrication process and decrease the cost, aligned CNT arrays are grown on both sides of heat dissipation structure surfaces at one time. The heat dissipation structure with CNT arrays are used to directly dissipate heat from a heat source to a cooler. The CNT arrays in between a heat source and a cooler are used as thermal interface material extending and dissipate heat directly from a heat source surface to a cooler surface. The CNT arrays exposed to the environment instead of being in between a heat source and a solid cooler serve as fins to enlarge heat dissipation area and improve thermal convection. In various embodiments, the disclosed inventions provide several of the following advantages: lower cost and more scalable manufacturing fast and simple process using efficient CNT synthesis and assembly method better heat sinking better convective cooling Other advantages and detailed novel features of the inventions will be explained with the descriptions of the example drawings.	CROSS-REFERENCE TO OTHER APPLICATION The present application claims priority under 35 U.S.C. § 119(e) of U.S. Patent Application No. 60/808,433, filed May 26, 2006, and entitled Heat Dissipation Structure with Carbon Nanotube Arrays and Method for Manufacturing the Same. BACKGROUND OF THE INVENTIONS The present application generally relates to thermal management solutions, and more specifically to heat dissipation structures using aligned carbon nanotube arrays, and to methods of fabricating such a heat dissipation structure and applying it to a package. With the development of microelectronic systems, for example, high brightness light emitting diode (HB-LED) for solid-state lighting, significant challenges of thermal management have to be faced to meet the increasing requirements of smaller profile, higher performance and longer product life time. More heat generated by devices needs to be effectively dissipated from a smaller area. Several kinds of heat sink are developed to expect to dissipate more heat from device to the environment. However it is very important to first conduct heat from device to heat sink by thermal interface materials. Unfortunately, conventional thermal interface materials, such as thermal grease thermal adhesives, phase change materials, etc., cannot meet the increasing requirement of the heat dissipation from a small area. Carbon nanotube (CNT) is an attractive candidate to improve the thermal performance of thermal interface materials because of their ultrahigh thermal conductivity up to 3000 W/m·K for multi-walled carbon nanotube (MWNT). Further information regarding CNT properties may be found in the Journal of the American Physical Society, Physical Review Letters, Vol. 87, page 215502 (2001), herein incorporated by reference. However thermal interface materials with randomly directed carbon nanotubes dispersed in epoxy resins or other matrix materials does not perform well because of the highly anisotropic nature of the thermal conduction by carbon nanotubes. Aligned carbon nanotube arrays directly extending from a first surface, for example a heat source surface, to a second surface, for example a cooler surface, is expected. U.S. Pat. No. 6,965,513 and U.S. Pat. No. 6,924,335, incorporated by reference herein for all purposes, disclose thermal interface materials with carbon nanotube bundles embedded in matrix materials. However, the phonon heat transfer modes in matrix materials and carbon nanotubes are not compatible, which significantly limits the advantage of heat conduction by carbon nanotube. In addition, solidified matrix material is less flexible to fill in the uneven surfaces of heat source and heat sink. As a result, the thermal conductivity of thermal interface material with aligned carbon nanotube arrays in matrix is only 1.21 W/m·K and the contact thermal resistance is more than 50 mm2·K/W. Additional information regarding the thermal conductivity of thermal interface materials are detailed in Advanced Materials, Vol. 17, page 1652 (2005) incorporated by reference herein. U.S. Pat. No. 6,856,01 and U.S. Patent Application Publication US 2004/0150100, both incorporated by reference herein for all purposes, disclose a thermal interface layer with carbon nanotubes grown on the surface of semiconductor die. However, the processes are not compatible for carbon nanotubes synthesis and device fabrication. If carbon nanotubes are grown before device fabrication, the decreased wafer cleanliness and ability to protect carbon nanotubes will make it difficult to conduct device fabrication using normal processes and equipments. Alternatively, if a device is fabricated before carbon nanotubes growth, the high temperature required by growing carbon nanotubes will damage the device or increasing the device cost by changing the processes and materials. As for the connecting methods, U.S. Patent Application Publication U.S. 2004/0261987, incorporated by reference herein for all purposes, use an adhesion promoting layer to connect heat source and the array of carbon nanotubes. However, it is very difficult to form a very thin layer so that the tips of carbon nanotubes can still make contact with the heat source surface. As a result, there is actually another added layer with additional thermal resistance, which reduces the thermal performance of the thermal management solution. In U.S. Pat. No. 6,891,724, incorporated by reference herein for all purposes, carbon nanotubes grown from the opposed surfaces intermesh as the surfaces are mated. However, it is difficult for carbon nanotubes from any surface to extend directly to the other surface. SUMMARY OF THE INVENTIONS The present inventions provide a new way to use high thermal conductivity carbon nanotube (CNT) arrays. To avoid the process incompatibility of carbon nanotube growth and device fabrication the aligned CNT arrays are formed on heat dissipation structure surfaces instead of a heat source surface. To simplify the fabrication process and decrease the cost, aligned CNT arrays are grown on both sides of heat dissipation structure surfaces at one time. The heat dissipation structure with CNT arrays are used to directly dissipate heat from a heat source to a cooler. The CNT arrays in between a heat source and a cooler are used as thermal interface material extending and dissipate heat directly from a heat source surface to a cooler surface. The CNT arrays exposed to the environment instead of being in between a heat source and a solid cooler serve as fins to enlarge heat dissipation area and improve thermal convection. In various embodiments, the disclosed inventions provide several of the following advantages: lower cost and more scalable manufacturing fast and simple process using efficient CNT synthesis and assembly method better heat sinking better convective cooling Other advantages and detailed novel features of the inventions will be explained with the descriptions of the example drawings. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the inventions are illustrated by examples shown in the following figures but not limited in these figures. These drawings are not necessarily drawn to scale. The inventions will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: FIG. 1 is a heat dissipation structure with carbon nanotube arrays on both sides, showing the surfaces of the heat dissipation structure are fully covered with grown carbon nanotube arrays without any pattern; FIG. 2 is a heat dissipation structure with carbon nanotube arrays on both sides, showing an example of carbon nanotubes with pattern on one side; FIG. 3 is a schematic cross sectional side view of an electronic package including a heat dissipation structure with carbon nanotube arrays on both sides in accordance with an embodiment of the present invention; FIG. 4 is a heat dissipation structure with carbon nanotube arrays on both sides having modification layers in between the carbon nanotube arrays and the heat dissipation structure surfaces; FIG. 5 is a detailed view of a heat dissipation structure showing some connecting methods with adhesive materials formed around the outside edges of the gap between the coupling heat source surface and cooler surface with carbon nanotube arrays in between; FIG. 6 is a detailed view of a heat dissipation system with carbon nanotube arrays directly grown on a heat source surface and a cooler surface and directly connected together by further growth; FIG. 7 shows some applications of the heat dissipation structure with some carbon nanotube arrays exposed to the environment; FIG. 8 is a general flowchart for manufacturing a heat dissipation structure in accordance with the present invention; FIG. 9 is a flowchart for manufacturing an embodiment of a heat dissipation structure in accordance with the present invention with the least processes; FIG. 10 is a general flowchart for manufacturing a heat dissipation system with carbon nanotube arrays directly grown on a heat source surface and a cooler surface and further growing to connect together; FIG. 11 is a chart showing the experimental results of thermal resistance of different TIM; FIG. 12 is a plan view of a device illustrating the relationship between the adhesive material and a heat source as well as a heat sink; FIG. 13 is a side view of the device of FIG. 12 illustrating the relationship between a heat source, the CNT-TIM, the adhesive material and a heat sink; FIG. 14 illustrates the heat conduction and heat convection flow paths of a CNT structure; and FIG. 15 illustrates a schematic of a thermal Chemical Vapor Deposition (CVD) system for CNT synthesis. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present application discloses embodiments of a heat dissipation structure with aligned carbon nanotube (CNT) arrays on both sides that serve as thermal interface material or heat dissipation fins for enlarging the thermal convection area and methods for manufacturing it. Details are set forth to provide a thorough understanding of the embodiments of the present inventions with the help of the drawings but not limited to. The features, structures, materials, and characteristics of the inventions can be combined in any suitable manner in one or more embodiments. In one embodiment, to simplify the fabrication process and decrease the cost, the aligned CNT arrays are grown on both sides of heat dissipation structure surfaces at one time. No catalyst is predeposited on heat dissipation structure surfaces or pretreated for growing. Sublimed catalyst, such as Ferrocence, is used as raw material. In addition, carbon nanotubes are synthesized on heat dissipation structure surfaces without pattern or pretreatment. Therefore, no microelectronic fabrication is needed for manufacturing the inventive heat dissipation structure with carbon nanotube arrays. Thermal chemical vapor deposition is adopted to synthesize carbon nanotube arrays because it is much cheaper than plasma enhanced chemical vapor deposition. A heat dissipation structure with CNT arrays can be simply connected to the heat source surface and cooler surface by mechanical attachment with contact pressure. In some embodiments for high performance application with special requirements, modification layers and catalyst predeposition may be needed to modify the thermal and other properties of heat dissipation structure with CNT arrays. In some embodiments, an adhesive material can be formed around the outside edges of the gap between heat source and a cooler with CNT arrays in between. This connecting method avoids adding an additional thermal resistance to the heat dissipation structure. In some embodiments, CNT arrays are directly formed on at least one of the heat source surface and cooler surface and then connected together by further growth. The strong or good bonding formed by direct growth of the CNT arrays on both coupling surfaces is beneficial to reduce the thermal contact resistance. In some other embodiments, some CNT arrays are exposed to the environment to which the heat will dissipate instead of being in between a heat source and a solid cooler. In this case, carbon nanotube arrays serve as fins of heat dissipation structure to significantly enlarge the heat dissipation area and dissipate heat more effectively to the environment by thermal convection. The measured thermal contact resistance of CNT thermal interface material (TIM) synthesized by thermal chemical vapor deposition (CVD) is only about 15 mm2W/K, which is much less than that of commercial available TIM. Further information regarding TIMs is disclosed in the Proceedings of the 56th Electronics Components and Technology Conference, pp. 177-182, herein incorporated by reference. The measured thermal contact resistance of heat spreader with CNT arrays on both sides synthesized by thermal CVD is only about 51 mm2W/K, which is only 30% of that of conventional heat spreader with TIM. Further experimental results show that CNTs synthesized by Plasma Enhanced Chemical Vapor Deposition (PECVD) has better thermal performance. References throughout this specification to “heat source” mean a structure that generates heat when operating or only a body with higher temperature, for example, a die or a device or a module or combination of several dies, devices or modules, or even a heat spreader dissipating heat to a heat sink. References throughout this specification to “cooler” mean a structure that serves to absorb heat and may further help dissipate the heat to other media, for example, a heat spreader absorbing heat from a heat source, a heat sink, or even an air environment or a fluid, etc. References throughout this specification to “coupling surface” mean the surface used to connect to other structures or materials. FIG. 1 shows an embodiment of inventive heat dissipation structure with CNT arrays 2 and 4 grown on heat dissipation structure surfaces 8 and 9. In the present invention, heat dissipation structure 3 can be made of any suitable high thermal conductivity materials, such as silicon, silicon oxide, silicon with silicon oxide layer, glass, some metals such as aluminum, copper, some metal alloys, such as aluminum alloy, copper alloy, or these metals or metal alloys with their oxide layers, or oxide of these metals or metal alloys, or any material containing at least one of the above materials. CNT arrays 2 and 4 can be grown on heat dissipation structure surfaces by thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, arc-discharge, or laser ablation method. FIG. 2 shows an embodiment with a smaller area of CNT arrays 2 on heat dissipation structure surface 8 than the area of CNT arrays 4 on heat dissipation structure surface 9 in some specific applications. For example, the area of CNT arrays 2 is the same as the area of heat source surface 6 and the area of CNT arrays 4 is the same as the area of the cooler surface 7. In other embodiment, the area of CNT array 2 and 4 can be larger or smaller than the area of heat source surface 6 and the area of cooler surface 7. Heat dissipation structure surfaces 8 and/or 9 can also be patterned to other desired features to make carbon nanotube arrays grow to the desired pattern in different applications. In FIG. 3, an application of an embodiment of the inventions in an electronic package with the inventive heat dissipation structure is shown schematically. A heat source 1 is connected to a cooler 5 through a heat dissipation structure 3 with carbon nanotube arrays 2 and 4 grown on both sides. In this embodiment, high density carbon nanotubes (CNTs) are grown on heat dissipation structure surfaces 8 and 9 without pattern by chemical vapor deposition using a sublimed catalyst, such as Ferrocene. Other sublimed catalysts can comprise at least one of dicyclopentadienyl iron (Ferrocene), dicyclopentadienyl cobalt (Cobaltocene), dicyclopentadienyl nickel (Nickelocene), iron titanium hydride, cobalt titanium hydride, nickel titanium hydride, or any materials containing at least one of these materials. A specific example of CNT array growth and CNT array growth conditions including temperature, pressure, source gases, and growth time is provided later in this application. There is no need for a microelectronic fabrication process to prepare the substrate and catalyst and, as a result, the manufacturing method is easy and low cost. High density CNT arrays are benefit to heat conduction because there are more heat conduction paths. In addition, CNT arrays with higher density can withstand the contact pressure in normal electronic packaging process without collapse. Therefore, aligned CNT arrays 2 are vertically extending from heat source surface 6 to heat dissipation structure surface 8 and CNT arrays 4 vertically extending from heat dissipation structure surface 9 to cooler surface 7, respectively. Under the contact pressure, some tips of CNT arrays 2 fill in the voids of uneven surface 6 and some even insert into the surface 6 of heat source 1. Similarly, some tips of CNT arrays 4 fill in the voids of uneven surface 7 and some even insert into the surface 7 of cooler 5. As a result, the inventive heat dissipation structure 3 with carbon nanotube arrays 2 and 4 as thermal interface material forms a high thermal conductive path from a heat source 1 to a cooler 5. FIG. 4. shows an embodiment with a layer 10 between CNT arrays 2 and heat dissipation structure surface 8 and layer 11 between CNT arrays 4 and heat dissipation structure surface 9. In some embodiments, the layers 10 and 11 can be a catalyst layer and/or multiple catalyst layers deposited on at least one of heat dissipation structure surfaces 8 and 9 for growing CNT arrays. Iron, nickel, cobalt, aluminum, silicon, copper, platinum, palladium, gold, silver, oxides of these materials, any combination of these materials and/or their oxides, or any materials containing at least one of these materials or their oxides can be the catalyst. In other embodiments, the layers 10 and 11 can be a modification layer or multiple modification layers formed on at least one of heat dissipation structure surfaces 8 and 9. They may be used to improve the bonding between CNT arrays and heat dissipation structure surfaces, and therefore reduce the thermal contact resistance between them. They may also be used to improve the distribution uniformity of CNT arrays on heat dissipation structure surfaces. Titanium, tungsten, silicon, aluminum, oxide of these materials, any combination of these materials, or any materials containing at least one of them can be used to form the modification layers. The layers 10 and 11 can also be multiple layers consisting of a catalyst layer and a modification layer. In some embodiments layers 10 and 11 may not be used at all or only one of them be used. FIG. 5 is a detail part of a heat dissipation structure showing some connecting methods with adhesive materials formed around the outside edges of the gap between a heat source and a cooler where there are CNT arrays grown in between. In FIGS. 5(a) and (b), the dimensions of the heat source 1 and the cooler 5 are the safe. The adhesive material 12 formed around the outside edges of the gap may only cover the gap and connect the heat source 1, CNT arrays 13 and the cooler 5, as shown in FIG. 5(a). It can also extend to a larger area, as shown in FIG. 5(b). The adhesive material can be an epoxy resin with or without fillers, thermal conductive polymers, a low melting metal or alloy, a phase change material, adhesive materials, or any materials containing any of these materials. In FIG. 5(c), the dimensions of the heat source 1 and the cooler 5 are not the same. The adhesive material 12 formed around the outside edges of the gap may shape like a fillet or any other shapes to connect the heat source 1 and the cooler 5 together with CNT arrays 13 extending from the heat source surface 6 to the cooler surface 7. The adhesive material 12 around the outside edges of the gap can help make CNT arrays have a good contact to the coupling surfaces as well as assembly the heat source and the cooler together. The adhesive material can be epoxy resins with or without fillers, thermal conductive polymers, low melting metals or alloys, phase change materials, adhesive materials, or any materials containing any of these materials. FIG. 6 is a detailed view of one embodiment of an inventive heat dissipation system. In this embodiment, CNT arrays 13 are directly grown face-to-face on a heat source surface 6 and a cooler surface 7 and further grow to connect together. In another embodiment, CNT arrays 13 can start to grow on one of the two coupling surfaces 6 and 7 till bonded to the opposite surface. FIG. 7 shows embodiments with some CNT arrays exposed to environment. In this case, CNT arrays serve as fins of heat dissipation structure to significantly enlarge the heat dissipation area and dissipate heat more effectively to the environment by thermal convection. In FIG. 7(a), heat dissipation structure serves as a heat spreader. CNT arrays 15 that are not in between the heat source, the heat dissipation structure and the cooler serve as fins to improve heat convection. In FIG. 7(b), heat dissipation structure serves as a heat sink. Part of CNT arrays on surface 8 of heat dissipation structure and all CNT arrays on surface 9 of heat dissipation structure function as fins to enlarge heat convection area. In FIG. 7(c), heat dissipation structure serves as a heat sink. Only part of CNT arrays on surface 8 of heat dissipation structure functions as fins to enlarge heat convection area. There are no CNT arrays grown on surface 9 of heat dissipation structure. CNT arrays can be formed with desired pattern. For example, in. FIG. 7(d). CNT arrays are formed with the center area the same as the heat resource and leaving a gap around the center CNT arrays to apply the adhesive material 12. More CNT arrays can be further grown on the outer surface to serve as fins to improve heat convection. CNT arrays can also be grown to form CNT bundles instead of uniformly distributed CNTs. FIG. 8 shows a flowchart for manufacturing the heat dissipation structure in accordance with the present invention. The method comprises the following steps: Step 801: providing a heat dissipation structure 3 with the desired dimension. Step 802: forming catalyst layers and/or modification layers 10 and 11 on at least one of heat dissipation structure surfaces 8 and 9; or no catalyst layer or modification layers at all. Step 803: growing carbon nanotube arrays 2 and 4 on both sides of heat dissipation structure surfaces 8 and 9. Step 804: forming adhesive material 12 around outside edges of CNT arrays; or no adhesive material at all. Step 805: assembling the heat source 1, heat dissipation structure 3 with CNT arrays 2 and 4 on both sides and the cooler 5 by mechanical contact pressure or by solidifying the adhesive material 12. FIG. 9 shows a flowchart for manufacturing one embodiment of the heat dissipation structure in accordance with the present invention with the least processes. The method comprises the following steps: Step 901: providing a heat dissipation structure 3 with the desired dimension. Step 902: growing carbon nanotube arrays 2 and 4 on both sides of heat dissipation structure surfaces 8 and 9 at one time with sublimed catalyst such as Ferrocene. No pretreatment of heat dissipation structure surfaces is needed. No pretreatment or deposition of catalyst is needed. Step 903: assembling the heat source 1, heat dissipation structure 3 with carbon nanotube arrays 2 and 4 on both sides and the cooler 5 by mechanical contact pressure. FIG. 10 shows a flowchart for manufacturing one embodiment of the inventive heat dissipation structure with CNT arrays directly grown on a heat source surface and a cooler surface and further growing to connect together. The method comprises the following steps: Step 1001: providing a heat source 1 and a cooler 5 with desired dimensions. Step 1002: putting the heat source 1 and the cooler 5 together while leaving them separated by spacers 14. Step 1003: forming catalyst layers and/or modification layers 10 and 11 on at least one of the heat source surface 6 and the cooler surface 7; or no catalyst layer or modification layer at all. Step 1004 growing CNT arrays 13 on the heat source surface 6 and/or the cooler surface 7 and further growing to connect them together. FIG. 11 is the experimental results of thermal resistance of different thermal interface material (TIM). The thermal resistance includes the contact resistance of TIM and coupling surfaces as well as thermal resistance of TIM layer. The thermal resistance of CNT-TIM is much less than that of commercial TIM with silver particles in epoxy resin. It is also less than that of solder TIM with Titanium (Ti) and copper (Cu) as the supporting layers. CNT-TIM synthesized by Plasma Enhanced Chemical Vapor Deposition (PECVD) has less thermal resistance than CNT-TIN synthesized by thermal chemical vapor deposition (CVD). However, PECVD equipment is more expensive than thermal CVD furnace. FIG. 12 is a view of a is a plan view of a high brightness light emitting diode device package 20 that shows the structural relationship of the heat sink 5, adhesive material 12 and the device 1. FIG. 13 illustrates a side view of the high brightness light emitting diode device package 20 that depicts the relationship of the CNT-TIM 2 to the adhesive material 12 and the heat sink 5. FIG. 14 illustrates a two-sided CNT array structure that shows the convective heat transfer flow and conductive heat transfer flow through the structure of one embodiment of the invention. FIG. 15 is merely one embodiment of a CNT synthesis process in which a CNT arrays has been synthesized by thermal Chemical Vapor Deposition (CVD) using sublimed Ferrocene. In this embodiment, a one-stage CVD furnace system 40 was employed to grow CNT arrays on Silicon (SI) based substrates 48. The diameter of the internal quartz reactor (not shown) is 1.5 inches. The flow rate of gases was controlled by mass controllers. A volume of Argon (Ar) 42 equaling 200 standard cubic centimeters per minute (sccm) was input as the carrier gas and 50 sccm of Ethylene 44 was used as one part of the carbon source. 100-200 milligrams (mg) of Ferrocene 46 was used as a catalyst and as another part of the carbon source. The Ferrocene 46 was introduced into the quartz reactor of the system at a location having a temperature of 200 degrees Celsius. CNTs were grown at 750 degrees Celsius (750° C.) for 10-20 minutes. Finally, the whole system was naturally cooled down to room temperature. During the CNT synthesis the pressure in the quartz tube was kept at atmospheric pressure. In one embodiment, there is disclosed a packaged semiconductor structure, comprising a heat source, a heat sink, an aligned array of carbon nanotubes which thermally connects said source to said sink; and a peripheral connecting material which runs along at least some edges of said aligned array, while mechanically contacting said source and said sink to provide a fixed positional relationship there between. In another embodiment there is disclosed a packaged semiconductor structure, comprising an extended structure which carries heat; and first and second mutually separate aligned carbon nanotube arrays which are thermally connected to opposite surfaces of said extended structure, wherein said first array terminates in a connection to another heat conducting structure, and said second array terminates in bare carbon nanotube ends. In some embodiments, a method of transferring heat from a microelectronic heat source, comprises conducting heat through an if array of aligned nanotube fibers; separating a heat source and heat sink by placing a spacer in a positional relationship with the heat source and heat sink; and mechanically stabilizing a relative position of the heat source to the heat sink using an adhesive material. In some embodiments there is disclosed a method of operating an electronic system, comprising operating at least one electronic component, coupling heat from said electronic component into a thermal plane, the thermal plane having thermal interface material; laterally conducting heat along said plane; and conducting heat out of said plane through the thermal interface material, wherein the thermal interface material are aligned carbon nanotube arrays. In other embodiments, a method for thermal connection is disclosed. The method comprises separating a heat source and a heat sink by placing a spacer in a positional relationship with the heat source and heat sink; growing a first aligned carbon nanotube array in a first perpendicular direction from a heat source; growing a second aligned carbon nanotube array in a second perpendicular direction opposite to the first perpendicular direction from a heat sink; coupling the first and second carbon nanotube arrays by allowing the growth of the first carbon nanotube array to connect with the growth of the second nanotube array. In some embodiments, there is disclosed a method of fabricating an electronic system, comprising actions of a) forming a dry carbon nanotube (CNT) array on a heat spreader; b) thereafter positioning a packaged electronic device in a position which is spaced from at least part of said dry CNT array; and c) growing carbon nanotubes from both said CNT array and said packaged device, to thereby form a unified CNT array which provides a low-resistance heat path from said device to said heat spreader. In another embodiment, there is disclosed a method of fabricating an electronic system, comprising actions of a) forming a dry CNT array on a heat spreader; b) thereafter positioning a packaged electronic device in a position which is spaced from at least part of said dry CNT array by a spacer; and c) growing carbon nanotubes from both said CNT array and said packaged device, to thereby, form a unified CNT array which provides a low-resistance heat path from said device to said heat spreader. Another embodiment discloses a thermal management structure, comprising a heat source, thermally linked to a heat spreader by an aligned nanotube array and a heat sink, also thermally linked to said heat spreader by another aligned nanotube array. In another embodiment, a method is disclosed for operating an electronic device, comprising actions of conducting heat from a heat source to a heat spreader through an aligned nanotube array; and conducting heat from said heat spreader to a heat sink through another aligned nanotube array. In another embodiment, a cooling structure is disclosed comprising a heat source, which is operatively coupled to drive heat flow through an aligned nanotube array; and a convective cooling area, where at least some of said aligned nanotube array couples heat to a fluid. Some other embodiments disclose a method for operating an electronic device, comprising actions of conducting heat from a heat source to a heat spreader through an aligned nanotube array; and conducting heat from said heat spreader to a heat sink through another aligned nanotube array. The foregoing, detailed description and accompanying drawings are only illustrative and not restrictive. It is to be understood that the general nature revealed in the invention may be sufficient to those skilled in the art to devise with addition, deletion, modification and adaptation in various applications as well as alternative arrangements without departing from the spirit of the disclosed embodiments and the scope of the appended claims. Modifications and Variations As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given. For example, it should be noted that a heat source may be a heat dissipation structure that generates heat when in operation or may be a structure having a high temperature. The heat dissipation structure could be a die, device, a module or a combination of several dies, devices, modules or even a heat spreader that dissipates heat to a heat sink. Similarly, a cooler may be a structure that absorbs heat and further may help to dissipate heat to other media including a heat spreader, a heat sink, or even ambient air or a fluid. Note that the carbon nanotube array can be used not only to couple to a gas phase for convective or forced cooling, but also to a liquid phase. The carbon nanotube (CNT) arrays of the inventions may be grown or synthesized using processes such as thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, arc discharging, or laser ablation. The carbon nanotubes (CNTs) are usually grown in a perpendicular alignment to the substrate. In some embodiments a high thermal conductivity substrate may, form particular patterns specific to certain applications and the CNT arrays may be grown within the particular pattern. The high thermal conductivity substrate comprises one of silicon, silicon oxide, silicon with silicon oxide layer, glass, some metals such as aluminum, copper, some metal alloys such as aluminum alloy, copper alloy, or these metals or metal alloys with their oxide layers, or oxide of these metals or metal alloys, or any materials containing at least one of the above materials. The CNT arrays may be grown by using sublimed catalysts such as dicyclopentadienyl iron (Ferrocene), dicyclopentadienyl cobalt (Cobaltocene), dicyclopentadienyl nickel (Nickelocene), iron titanium hydride, cobalt titanium hydride, nickel titanium hydride, or similar compounds containing at least one of these substances. CNT arrays may be grown from preformed catalyst dispersed on the high thermal conductivity substrate surfaces. Deformed catalyst types include iron, nickel, cobalt, aluminum, silicon, copper, platinum, palladium, gold, silver, oxides of these materials, and any combination or compound of these substances and/or their oxides. Some embodiments may, include a modification layer formed on the high thermal conductivity substrate surface that is operational to modify the distribution and density of the CNT arrays and modify the bonding between the CNT and the high thermal conductivity substrate surfaces. The modification layer may at least one of titanium, tungsten, silicon, aluminum, oxides of these elements, or any compounds containing at least one of these elements. In some embodiments, the electronic system is comprised of CNT arrays disposed in a gap exposed between a heat source and a cooler. Adhesive material may be placed around the outside edges of the exposed gap. The adhesive material may include epoxy resin with or without fillers, thermal conductive polymers, a low melting metal or alloy, a phase change material, adhesive materials, or any substances containing any of these materials. In some embodiments, the CNT arrays increase the heat dissipation from the electronic structure by operating as heat fins. The CNT heat fins significantly increase the heat dissipation area of the heat, dissipation structure resulting in increased heat dissipation to the environment by heat convection. The CNT arrays are positioned to effectively dissipate the heat into the environment by thermal convection. CNT arrays may be grown or synthesized into a specific pattern required for a particular application or may be adapted for a specific feature of an application. In some embodiments, aligned CNT arrays may be grown to vertically extend from a heat source surface or a cooler surface and may be grown until contact is made to the opposite surface. In other embodiments, aligned CNT arrays may be grown to vertically extend from a heat source surface and a cooler surface and may be grown until the opposite CNT arrays overlap. In one embodiment, the dimensions of the heat source and the cooler may be the same; the dimensions of the electronic structures may be device and application dependent. One example may be a 1 W LED package where the heat source is 1 millimeter (mm) by 1 mm and the cooler or heat sink is 20 mm by 20 mm. In other applications, the heat source may be much larger than 1 mm by 1 mm and the heat sink will be a corresponding dimension. None of the description the present application should be construed as implying that any particular element, step, or function is an essential element which must be included in the claim scope THE SCOPE OF PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none of these claims are intended to invoke paragraph six of 35 U.S.C. section 112 unless the exact words “means for” are followed by a participle. The claims as filed are intended to be as comprehensive as possible, and NO subject matter is intentionally relinquished, dedicated, or abandoned.	H	67H01	185H01L	233	73
11761080	US20070284566A1-20071213	COMPOSITE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME	ACCEPTED	20071129	20071213	[]	H01L2906	["H01L2906"]	7880180	20070611	20110201	257	088000	98225.0	FOX	BRANDON	[{"inventor_name_last": "Tada", "inventor_name_first": "Yasuhiro", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Hanya", "inventor_name_first": "Akihiko", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}]	The disclosed subject matter provides a composite semiconductor device which can include a common substrate, a first semiconductor light emitting structure, and a second semiconductor light emitting structure. The first semiconductor light emitting structure can include an epitaxial grown layer containing a light emitting layer formed on part of the common substrate either directly or via a bonding layer. The second semiconductor light emitting structure can be provided in a notch at at least one location to which the epitaxial grown layer is not bonded, or in a recess formed in the notch at one location. The disclosed subject matter also provides a method of manufacturing a composite semiconductor device having the above-described and other structures.	1. A composite semiconductor device, comprising: a common substrate; a first semiconductor light emitting structure; and a second semiconductor light emitting structure, wherein the first semiconductor light emitting structure includes an epitaxial grown layer having a light emitting layer and is located adjacent at least part of the common substrate, and the first semiconductor light emitting structure includes a notch formed in the epitaxial grown layer, and wherein the second semiconductor light emitting structure is located in the notch of the epitaxial grown layer. 2. The composite semiconductor device according to claim 1, wherein the second semiconductor light emitting structure includes an epitaxial grown layer having a light emitting layer, the second semiconductor light emitting structure being located adjacent a grown substrate, the grown substrate being different from the common substrate, and a bonding electrode is located between the second semiconductor light emitting structure and the common substrate. 3. The composite semiconductor device according to claim 1, wherein the first semiconductor light emitting structure includes a bonding layer having an ohmic electrode layer and a bonding material layer composed of a metal, and the bonding layer is formed in contact with the epitaxial grown layer in the first semiconductor light emitting structure. 4. The composite semiconductor device according to claim 1, wherein the first semiconductor light emitting structure includes a first bonding layer located adjacent the common substrate, and the second semiconductor light emitting structure includes a bonding electrode located in the notch and adjacent the common substrate, the bonding electrode extending at least one of continuously from and separately from the first bonding layer of the first semiconductor light emitting structure. 5. The composite semiconductor device according to claim 1, wherein the first semiconductor light emitting structure and the second semiconductor light emitting structure have different respective emission spectra. 6. The composite semiconductor device according to claim 1, further comprising: a light transmissive resin including at least one kind of wavelength conversion material, the light transmissive resin located in at least one recess in the common substrate in which the second semiconductor light emitting structure is located. 7. The composite semiconductor device according to claim 1, wherein the common substrate includes a recess formed therein, and the second light emitting structure is located in the recess. 8. The composite semiconductor device according to claim 1, further comprising: a bonding layer located adjacent the epitaxial grown layer and bonding the epitaxial grown layer to the common substrate. 9. The composite semiconductor device according to claim 2, wherein the second semiconductor light emitting structure is bonded to the common substrate via the bonding electrode. 10. The composite semiconductor device according to claim 1, further comprising: at least one of a motherboard and a transparent substrate; and a spacer structure located between the common substrate and the at least one of a motherboard and a transparent substrate. 11. The composite semiconductor device according to claim 10, wherein the spacer structure is configured as a bump ball. 12. A method of manufacturing a composite semiconductor device, comprising: forming an epitaxial grown layer including a light emitting layer on a grown substrate; forming a first electrode on the epitaxial grown layer; providing a common substrate having a top surface and a bottom surface; forming a second electrode and a third electrode on the top surface and bottom surface of the common substrate, respectively; bonding the first electrode and the second electrode together to form a bonded assembly; forming a fourth electrode on a surface of the bonded assembly adjacent the epitaxial grown layer to form a first semiconductor light emitting structure; forming a notch at at least one location in the epitaxial grown layer in the first semiconductor light emitting structure extending to at least one of the first electrode, the second electrode, and the common substrate; forming a fifth electrode on an inner bottom of the notch; and mounting a second semiconductor light emitting structure in the notch. 13. The method of manufacturing a composite semiconductor device of claim 12, wherein forming a fourth electrode on a surface of the bonded assembly adjacent the epitaxial grown layer includes removing the grown substrate from the bonded assembly. 14. The method of manufacturing a composite semiconductor device of claim 12, wherein forming a notch includes forming a recess in the common substrate. 15. The method of manufacturing a composite semiconductor device of claim 12, wherein the method is accomplished in a sequential manner. 16. The method of manufacturing a composite semiconductor device of claim 12, further comprising: providing at least one of a motherboard and a transparent substrate; and attaching the common substrate to the at least one of a motherboard and a transparent substrate via a spacer structure. 17. A composite semiconductor device having a light emission direction, comprising: a common substrate; a first semiconductor light emitting structure configured to emit light substantially along the light emission direction of the device and including a top electrode and a bottom electrode, the bottom electrode being connected to the common substrate; and a second semiconductor light emitting structure configured to emit light substantially along the light emission direction of the device and including a top electrode and a bottom electrode, the bottom electrode being connected to the common substrate; wherein the first semiconductor light emitting structure and the second semiconductor light emitting structure are configured to have at least one of the following configurations, a top surface of the top electrode of the first semiconductor light emitting structure being spaced from a top surface of the top electrode of the second semiconductor light emitting structure along the emission direction of the device, and a bottom surface of the bottom electrode of the first semiconductor light emitting structure being spaced from a bottom surface of the bottom electrode of the second semiconductor light emitting structure along the emission direction of the device. 18. The composite semiconductor device according to claim 17, wherein the second semiconductor light emitting structure includes an epitaxial grown layer having a light emitting layer, the second semiconductor light emitting structure being located adjacent a grown substrate, the grown substrate being different from the common substrate, and a bonding electrode is located between the second semiconductor light emitting structure and the common substrate. 19. The composite semiconductor device according to claim 17, wherein the first semiconductor light emitting structure includes a first bonding layer located adjacent the common substrate, and the second semiconductor light emitting structure includes a bonding electrode located adjacent the common substrate, the bonding electrode extending continuously from the first bonding layer of the first semiconductor light emitting structure. 20. The composite semiconductor device according to claim 17, wherein the first semiconductor light emitting structure and the second semiconductor light emitting structure have different respective emission spectra. 21. The composite semiconductor device according to claim 17, further comprising: a light transmissive resin including at least one kind of wavelength conversion material, the light transmissive resin located in at least one recess in the common substrate in which the second semiconductor light emitting structure is located.	<SOH> BACKGROUND <EOH>1. Field The present disclosed subject matter relates to a semiconductor composite device and method of manufacturing the same. More particularly, it relates to a composite semiconductor device including a plurality of light emitting units on the same substrate and method of manufacturing the same. 2. Description of the Related Art There have been proposed semiconductor light emitting sources which include a plurality of light emitting units with respective different emission spectra and which are formed on the same substrate composed of a semiconductor material or on the same device. These conventional are devices are described as follows: (1) a semiconductor composite light emitting device which includes semiconductor crystal layers having a plurality of active layers (light emitting layers) with different respective emission spectra that are sequentially grown on the same substrate (see, for example, Patent Document 1: JP Patent No. 3298390); (2) an LED display which includes semiconductor crystal layers having light emitting layers with different respective emission spectra that are sequentially or simultaneously grown on the same substrate (see, for example, Patent Document 2: JP 2004-79933A); (3) a semiconductor light emitting device which includes a GaN-based LED mounted facedown on an Si diode via micro-bumps (see, for example, Patent Document 3: WO 98/34285); and (4) a full-color semiconductor light emitting device which includes semiconductor light emitting devices of the flip-chip type that are operative to emit red, green and blue lights and which are mounted on an Si diode via micro-bumps (see, for example, Patent Document 4: JP 11-307818A). In the above-listed conventional art document (1), an increase in the number of the light emitting layers extensively increases the steps in the epitaxial growth process. This results in an elongated lead-time, with a lowered producibility and an increased production cost, and also makes it difficult to insure excellent reproducibility on respective growth conditions in all growth processes. Therefore, the light emitting layers cause variations in emission spectra and thus the exit light from the resultant composite semiconductor light emitting device exhibits a large variation in color tone, which makes it difficult to control color tone. In the above-listed conventional art document (2), the composition ratio and growth temperature associated with the compound semiconductor may be controlled to form the light emitting layers having a plurality of desired emission spectra selectively in order or at the same time. In this case, a highly precise execution of selective composition control and temperature control are required for growth regions for use in formation of the light emitting layers therein, which also requires the use of high technology products and methods. Therefore, it is difficult for this method to be used to realize an LED display with less variation in color tone. In the above-listed conventional art document (3), if the LED mounted on the Si diode has an upper electrode that is wire bonded, the heat, pressure and vibrations on the wire bonding apply a stress on the micro-bumps that connect the Si diode with the LED. This stress impairs the reliability of the connection strength and electrical properties. Therefore, the LED is limited to one that has a structure capable of facedown mounting, which restricts the flexibility of LED selection. In addition, suppression of the load imposed on the LED and the Si diode on mounting the LED requires a certain restriction on the mount condition. In this case, the bonding strength between devices may become lower to possibly deteriorate the reliability of the device. In the above-listed conventional art document (4), the semiconductor light emitting devices are mounted independently. Therefore, the interval between adjacent devices is extended which can deteriorate the color mixture properties of the device.	<SOH> SUMMARY <EOH>The disclosed subject matter has been made in consideration of the above described characteristics, deficiencies, problems and features of the above described conventional art and can include providing a composite semiconductor device that is excellent in heat radiation, color mixture, quality, stability and reliability, with higher brightness and larger flexibility in the selection of the light emitting devices for mounting. In accordance with an aspect of the disclosed subject matter, a composite semiconductor device can include: a common substrate; a first semiconductor light emitting device; and a second semiconductor light emitting device, wherein the first semiconductor light emitting device is structured to include an epitaxial grown layer containing a light emitting layer formed on part of the common substrate directly or via a bonding layer, and wherein the second semiconductor light emitting device is provided in a notch at one location at least to which the epitaxial grown layer is not bonded or in a recess formed in the notch at one location at least. In accordance with another aspect of the disclosed subject matter, the second semiconductor light emitting device may include an epitaxial grown layer containing a light emitting layer formed on a grown substrate that is different from the common substrate, and is bonded to the common substrate via a bonding electrode. In yet another aspect of the disclosed subject matter, the bonding layer in the first semiconductor light emitting device may include an ohmic electrode layer and a bonding material layer composed of a metal, and can be formed in contact with the epitaxial grown layer in the first semiconductor light emitting device. In another aspect of the disclosed subject matter, the bonding electrode for bonding the second semiconductor light emitting device may be formed in the notch on the common substrate in part, or all continuously, or separately, from the bonding layer in the first semiconductor light emitting device. In still another aspect of the disclosed subject matter, the first semiconductor light emitting device and the second semiconductor light emitting device may have different respective emission spectra. In another aspect of the disclosed subject matter, the composite semiconductor device may further include a light transmissive resin containing at least one kind of wavelength conversion material, such as a phosphor, filled in at least one recess in which the second semiconductor light emitting device is provided. The disclosed subject matter also relates to a method of manufacturing a composite semiconductor device, that can include: forming an epitaxial grown layer containing a light emitting layer on a grown substrate; forming a first electrode on the epitaxial grown layer; forming a second electrode and a third electrode on both surfaces of a common substrate, respectively; bonding the first electrode and the second electrode together; forming a fourth electrode on a surface of the bonded assembly near the epitaxial grown layer after removing or not removing the grown substrate from the bonded assembly to form a first semiconductor light emitting device; forming a notch at one location or more extending from the epitaxial grown layer in the first semiconductor light emitting device to at least one of the first electrode, the second electrode, and/or the common substrate, or further forming a recess in the notch extended to the common substrate; forming a fifth electrode on an inner bottom of the notch or the recess; and, mounting a second semiconductor light emitting device in the notch or the recess. In accordance with the disclosed subject matter, it can be possible to realize a composite semiconductor device that is excellent in heat radiation, color mixture, quality, stability and/or reliability, and which has higher brightness and larger flexibility in the selection of light emitting devices for mounting.	This application claims the priority benefit under 35 U.S.C. §119 of Japanese Patent Application No. 2006-162534 filed on Jun. 12, 2006, which is hereby incorporated in its entirety by reference. BACKGROUND 1. Field The present disclosed subject matter relates to a semiconductor composite device and method of manufacturing the same. More particularly, it relates to a composite semiconductor device including a plurality of light emitting units on the same substrate and method of manufacturing the same. 2. Description of the Related Art There have been proposed semiconductor light emitting sources which include a plurality of light emitting units with respective different emission spectra and which are formed on the same substrate composed of a semiconductor material or on the same device. These conventional are devices are described as follows: (1) a semiconductor composite light emitting device which includes semiconductor crystal layers having a plurality of active layers (light emitting layers) with different respective emission spectra that are sequentially grown on the same substrate (see, for example, Patent Document 1: JP Patent No. 3298390); (2) an LED display which includes semiconductor crystal layers having light emitting layers with different respective emission spectra that are sequentially or simultaneously grown on the same substrate (see, for example, Patent Document 2: JP 2004-79933A); (3) a semiconductor light emitting device which includes a GaN-based LED mounted facedown on an Si diode via micro-bumps (see, for example, Patent Document 3: WO 98/34285); and (4) a full-color semiconductor light emitting device which includes semiconductor light emitting devices of the flip-chip type that are operative to emit red, green and blue lights and which are mounted on an Si diode via micro-bumps (see, for example, Patent Document 4: JP 11-307818A). In the above-listed conventional art document (1), an increase in the number of the light emitting layers extensively increases the steps in the epitaxial growth process. This results in an elongated lead-time, with a lowered producibility and an increased production cost, and also makes it difficult to insure excellent reproducibility on respective growth conditions in all growth processes. Therefore, the light emitting layers cause variations in emission spectra and thus the exit light from the resultant composite semiconductor light emitting device exhibits a large variation in color tone, which makes it difficult to control color tone. In the above-listed conventional art document (2), the composition ratio and growth temperature associated with the compound semiconductor may be controlled to form the light emitting layers having a plurality of desired emission spectra selectively in order or at the same time. In this case, a highly precise execution of selective composition control and temperature control are required for growth regions for use in formation of the light emitting layers therein, which also requires the use of high technology products and methods. Therefore, it is difficult for this method to be used to realize an LED display with less variation in color tone. In the above-listed conventional art document (3), if the LED mounted on the Si diode has an upper electrode that is wire bonded, the heat, pressure and vibrations on the wire bonding apply a stress on the micro-bumps that connect the Si diode with the LED. This stress impairs the reliability of the connection strength and electrical properties. Therefore, the LED is limited to one that has a structure capable of facedown mounting, which restricts the flexibility of LED selection. In addition, suppression of the load imposed on the LED and the Si diode on mounting the LED requires a certain restriction on the mount condition. In this case, the bonding strength between devices may become lower to possibly deteriorate the reliability of the device. In the above-listed conventional art document (4), the semiconductor light emitting devices are mounted independently. Therefore, the interval between adjacent devices is extended which can deteriorate the color mixture properties of the device. SUMMARY The disclosed subject matter has been made in consideration of the above described characteristics, deficiencies, problems and features of the above described conventional art and can include providing a composite semiconductor device that is excellent in heat radiation, color mixture, quality, stability and reliability, with higher brightness and larger flexibility in the selection of the light emitting devices for mounting. In accordance with an aspect of the disclosed subject matter, a composite semiconductor device can include: a common substrate; a first semiconductor light emitting device; and a second semiconductor light emitting device, wherein the first semiconductor light emitting device is structured to include an epitaxial grown layer containing a light emitting layer formed on part of the common substrate directly or via a bonding layer, and wherein the second semiconductor light emitting device is provided in a notch at one location at least to which the epitaxial grown layer is not bonded or in a recess formed in the notch at one location at least. In accordance with another aspect of the disclosed subject matter, the second semiconductor light emitting device may include an epitaxial grown layer containing a light emitting layer formed on a grown substrate that is different from the common substrate, and is bonded to the common substrate via a bonding electrode. In yet another aspect of the disclosed subject matter, the bonding layer in the first semiconductor light emitting device may include an ohmic electrode layer and a bonding material layer composed of a metal, and can be formed in contact with the epitaxial grown layer in the first semiconductor light emitting device. In another aspect of the disclosed subject matter, the bonding electrode for bonding the second semiconductor light emitting device may be formed in the notch on the common substrate in part, or all continuously, or separately, from the bonding layer in the first semiconductor light emitting device. In still another aspect of the disclosed subject matter, the first semiconductor light emitting device and the second semiconductor light emitting device may have different respective emission spectra. In another aspect of the disclosed subject matter, the composite semiconductor device may further include a light transmissive resin containing at least one kind of wavelength conversion material, such as a phosphor, filled in at least one recess in which the second semiconductor light emitting device is provided. The disclosed subject matter also relates to a method of manufacturing a composite semiconductor device, that can include: forming an epitaxial grown layer containing a light emitting layer on a grown substrate; forming a first electrode on the epitaxial grown layer; forming a second electrode and a third electrode on both surfaces of a common substrate, respectively; bonding the first electrode and the second electrode together; forming a fourth electrode on a surface of the bonded assembly near the epitaxial grown layer after removing or not removing the grown substrate from the bonded assembly to form a first semiconductor light emitting device; forming a notch at one location or more extending from the epitaxial grown layer in the first semiconductor light emitting device to at least one of the first electrode, the second electrode, and/or the common substrate, or further forming a recess in the notch extended to the common substrate; forming a fifth electrode on an inner bottom of the notch or the recess; and, mounting a second semiconductor light emitting device in the notch or the recess. In accordance with the disclosed subject matter, it can be possible to realize a composite semiconductor device that is excellent in heat radiation, color mixture, quality, stability and/or reliability, and which has higher brightness and larger flexibility in the selection of light emitting devices for mounting. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of an embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is an exemplary internal wiring diagram for the embodiment of FIG. 1. FIG. 4 is another exemplary internal wiring diagram for the embodiment of FIG. 1. FIG. 5 is a plan view of another embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 6 is a cross-sectional view taken along line A-A of FIG. 5. FIG. 7 is a cross-sectional side view of the embodiment of FIG. 5 when mounted. FIG. 8 is a cross-sectional side view of another embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 9 is a cross-sectional side view of the embodiment of FIG. 8 when mounted. FIG. 10 is a cross-sectional view of the embodiment of FIG. 8 when mounted in another configuration. FIG. 11 is a top view of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 12 is a side view of another composite semiconductor device made in accordance with principles of the disclosed subject matter. FIGS. 13(a)-(n) show process views related to an exemplary manufacturing process for a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 14 is a partial cross-sectional view of an embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 15 is a top view of an embodiment of a composite semiconductor device when mounted made in accordance with principles of the disclosed subject matter. FIG. 16 is a top view of a conventional composite semiconductor device when mounted. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Exemplary embodiments of the disclosed subject matter will now be described in detail below with reference to FIGS. 1-15. The below-described embodiments are specific examples of the disclosed subject matter and are given various technical features. However, the scope of the disclosed subject matter is not limited to these embodiments. FIG. 1 is a plan view of an embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter, and FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. The composite semiconductor device (hereinafter abbreviated as “composite device”) 1 can include a first semiconductor light emitting device (hereinafter abbreviated as “first light emitting device”) 3 for configuring a first light emitting region 2, and a second semiconductor light emitting device (hereinafter abbreviated as “second light emitting device”) 5 for configuring a second light emitting region 4. The first light emitting device 3 can be configured as follows. A material is appropriately selected from Si, Al2O3, SiC and GaP having desired properties (such as high electric conductivity, high transmissivity, high thermal conductivity and high strength) to form a common substrate 6. A first external connection electrode 7 is formed on one surface of the common substrate 6. The first external connection electrode 7 includes a wet layer of Ti or Ni and an external connection electrode layer of Au in order from the common substrate 6. On the other surface of the common substrate 6, a later-described bonding layer 8, an epitaxial grown layer (hereinafter abbreviated as “grown layer”) 9 containing a light emitting layer, and a second external connection electrode 10 composed of an AuGeNi alloy are formed in order from the common substrate 6. The second external connection electrode 10 serves as a light-exit surface and accordingly may be composed of a fine wire electrode or an entirely transparent electrode that does not block the exit of light as much as possible. On the common substrate 6, a notch 11 is formed without the grown layer 9 formed therein. The notch 11 is a region where the second external connection electrode 10 and the grown layer 9 are not present. A light emitting device bonding electrode 12 is formed on the common substrate 6 exposed through the bottom of the notch 11 for mounting and bonding the second light emitting device 5. The light emitting device bonding electrode 12 can be composed of Au or AuZn, for example, to insure excellent electric conductivity. A eutectic bond between a lower electrode 13 on the second light emitting device 5 and the light emitting device bonding electrode 12 formed in the notch 11 on the common substrate 6 fixes the second light emitting device 5 in the notch 11. It also achieves electric conduction between both electrodes. The second light emitting device 5 has an upper electrode 14 formed on the other side opposite the lower electrode 13. In addition, the second light emitting device 5 can include a grown substrate 56 located adjacent an epitaxial grown layer 59. It should be noted that various adhesive, conductive, transmissive, or other layers can be interposed between the layers disclosed in the specific embodiments herein without departing from the spirit and scope of the disclosed subject matter. The composite semiconductor device 1 configured as described above can be internally wired in both ways as shown FIGS. 3 and 4. If the device 1 is wired as shown in FIG. 3, the first light emitting device 3 is configured such that the first external connection electrode 7 serves as the N-electrode and the second external connection electrode 10 serves as the P-electrode. In this case, the second light emitting device 5 is configured such that the lower electrode 13 serves as the N-electrode and the upper electrode 14 serves as the P-electrode. On the other hand, if the device 1 is wired as shown in FIG. 4, the first light emitting device 3 is configured such that the first external connection electrode 7 serves as the P-electrode and the second external connection electrode 10 serves as the N-electrode. In this case, the second light emitting device 5 is configured such that the lower electrode 13 serves as the P-electrode and the upper electrode 14 serves as the N-electrode. FIG. 5 is a plan view of another embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter. FIG. 6 is a cross-sectional view taken along line A-A of FIG. 5, and FIG. 7 is a side view of the device when mounted. In the embodiment of FIG. 5, notches 11 are formed at two opposite locations on the common substrate 6. The notches 11 are formed without the presence of the second external connection electrode 10 and the grown layer 9 in the first light emitting device 3. A recess 15 is formed in the common substrate 6 that is exposed through the bottom of each notch 11. A second light emitting device bonding electrode 12 is formed on the inner bottom of the recess 15. A eutectic bond between the lower electrode 13 on the second light emitting device 5 and the bonding electrode 12 fixes the second light emitting device 5 in the recess 15 and also achieves electric conduction between both electrodes. The remaining structures can be substantially similar to those in the above embodiment of FIG. 1, and therefore a detailed description thereof is omitted from the following description. FIG. 7 shows the composite semiconductor device 1 of FIG. 5 mounted on a motherboard. The composite semiconductor device 1 is fixed on the motherboard 16 such that the first external connection electrode 7 on the composite semiconductor device 1 is bonded to wiring patterns 17 on the motherboard 16 via a conductive bonding material such as a solder and a conductive adhesive (not shown). These electrodes are brought into electrical conduction with each other. The second external connection electrode 10 on the first light emitting device 3 and the upper electrode 14 on the second light emitting device 5 are connected to a separate portion of the wiring patterns 17 on the motherboard 16 via respective bonding wires 18. The recess 15, in which the second light emitting device 5 is mounted, is filled with a sealing resin 19 composed of a light transmissive resin that can include at least one kind of wavelength conversion material such as a phosphor to seal the second light emitting device 5. The light transmissive resin configuring the sealing resin 19 protects the second light emitting device 5 from external environments such as water, dirt, gases, etc. The refractive index of the sealing resin 19, which forms an interface with the light-exit surface of the second light emitting device 5, may be made closer to the refractive index of the semiconductor material, which forms the light-exit surface of the second light emitting device 5. In this case, it is possible to improve the efficiency of extracting the emitted light traveling from the light-exit surface of the second light emitting device 5 into the sealing resin 19. In operation, a phosphor contained in the sealing resin 19 is excited by a part of the light emitted from the second light emitting device 5 and thus converts the emitted light into a light with a longer wavelength than the emitted light. With an additional color mixture of the emitted light with the converted light, it is operative to release a light with a different chromaticity from that of the light emitted from the second light emitting device 5. Consequently, an appropriately selected combination of the light from the first light emitting device 3, the light from the second light emitting device 5, and the phosphor can realize a composite semiconductor device 1 that emits a light with a desired chromaticity. It is further possible to seal the composite semiconductor device 1 and the bonding wires 18 in a sealing resin composed of a light transmissive resin. In this case, the sealing resin protects the composite semiconductor device 1 from external environments such as water, dirt, gases, etc., similar to the above, and also protects the bonding wires 18 from mechanical stresses such as vibrations and impacts. In addition, the sealing resin can also function to efficiently lead the light that is released from the composite semiconductor device 1 and into the light transmissive resin through the light-exit surface of the composite semiconductor device 1. FIG. 8 is a cross-sectional view of another embodiment of a composite semiconductor device made in accordance with principles of the disclosed subject matter, and FIGS. 9 and 10 are side views of the device when mounted. In the embodiment of FIG. 8, the second external connection electrode 10 on the first light emitting device 3 and the upper electrode 14 on the second light emitting device 5 have respective upper surfaces located on the same or substantially same plane, which is different from the above-described embodiments. In order to ensure the positional relation between the electrodes 10 and 14, the first light emitting device 3 is fabricated such the thickness of the first light emitting device 3 is thicker than the thickness of the second light emitting device 5. In addition, the depth of the recess 15 that is formed in the common substrate 6 is determined in consideration of the thickness of the second light emitting device 5. A spacer structure such as a bump ball 28a composed of Au or the like is formed on the second external connection electrode 10 and another spacer structure such as bump ball 28b similarly composed of Au or the like is formed on the second light emitting device 5. The bump balls 28a and 28b have respective upper ends located on the same or substantially the same plane. In FIG. 8 the pair of electrodes on the second light emitting device 5 are composed of the upper electrode 14 and the lower electrode 13. Both of the pair of electrodes may be provided on the upper side of the second light emitting device 5. In this case, the upper surfaces of the two electrodes provided on the upper side of the second light emitting device 5 and the upper surface of the second external connection electrode 10 on the first light emitting device 3 can be located on the same or substantially the same plane. Other structures of the device 1 can be the same or similar to those in the above described embodiment of FIG. 5 and a detailed description is therefore omitted from the following description. FIG. 9 shows the composite semiconductor device of the embodiment of FIG. 8 mounted in a sandwiched configuration between a motherboard and a transparent substrate. The composite semiconductor device 1 is fixed on the motherboard 16 such that the first external connection electrode 7 on the composite semiconductor device 1 is bonded to wiring patterns 17 on the motherboard 16 via a conductive bonding material such as a solder and a conductive adhesive (not shown). These electrodes are brought into electrical conduction with each other. The bump ball 28a on the first light emitting device 3 and the bump ball 28b on the second light emitting device 5 are bonded to wiring patterns (not shown) formed on the transparent substrate 29 and brought into electrical conduction with each other. The light emitted from both the first light emitting device 3 and the second light emitting device 5 is released through the transparent substrate 29 to an area outside of the transparent substrate 29. A variety of processing (such as lens processing and diffusion processing) may be performed on the transparent substrate 29 in accordance with a desired device characteristic. Such a mounting method is possible because the second external connection electrode 10 on the first light emitting device 3 and the upper electrode 14 on the second light emitting device 5 have respective upper surfaces located on the same plane. In addition, the bump ball 28a provided on the second external connection electrode 10 on the first light emitting device 3 and the bump ball 28b provided on the upper electrode 14 on the second light emitting device 5 have respective upper ends located on the same plane. FIG. 10 shows the composite semiconductor device of the embodiment of FIG. 8 mounted on a motherboard 16. The composite semiconductor device 1 is fixed on the motherboard 16 for electrical conduction such that the bump ball 28a on the first light emitting device 3 and the bump ball 28b on the second light emitting device 5 are bonded to respective wiring patterns 17 on the motherboard 16. The first external connection electrode 7 can be partly formed on the first light emitting device 3 and bonded via a bonding wire 18 to another wiring pattern 17 for electrical conduction. The portion of the wiring patterns 17 to which the bonding wire 18 is attached can be separate from those portions of the wiring patterns 17 bonded to the bump balls 28a, 28b on the motherboard 16. In this case, the common substrate 6 in the first light emitting device 3 is composed of a semiconductor material having light transmissivity. Therefore, of the light emitted from inside the epitaxial grown layer 9, a portion of the light traveling toward the first external connection electrode 7 is released through the common substrate 6 to an area outside of the common substrate 6. In addition, a portion of the light traveling toward the motherboard 16 is reflected at the surface of the motherboard 16 and similarly released through the common substrate 6 to an area outside of the common substrate 6. Accordingly, this particular example of the mounting method can enhance the efficiency of extraction of the emitted light. The light extraction efficiency can be further enhanced by providing a reflecting layer, for example, printed on a surface of the motherboard 16 on which the composite semiconductor device 1 is mounted. Such a mounting method is possible because the second external connection electrode 10 on the first light emitting device 3 and the upper electrode 14 on the second light emitting device 5 have respective upper surfaces that are located on the same plane. In addition, the bump ball 28a provided on the second external connection electrode 10 on the first light emitting device 3 and the bump ball 28b provided on the upper electrode 14 on the second light emitting device 5 have respective upper ends located on the same plane. The composite semiconductor device 1 of the disclosed subject matter can be mounted in a generally usable package. For example, the device can include a surface mount package as shown in FIG. 11 or a bullet-shaped package as shown in FIG. 12. An exemplary method of manufacturing a semiconductor light emitting device in accordance with principles of the disclosed subject matter is described next with reference to FIGS. 13(a)-(n). First, in the FIG. 13(a), a grown substrate 20 is prepared. The grown substrate 20 is composed of a material having a lattice constant that can match that of the later-described epitaxial grown material. If a light emitting layer for red light emission is formed, a GaAs-based semiconductor is employed. In FIG. 13(b), an epitaxial grown layer 9 containing a light emitting layer is formed on the grown substrate 20. The epitaxial grown layer 9 may be manufactured from an AlGaInP-based semiconductor. In FIG. 13(c), a first electrode 21 is formed on the epitaxial grown layer 9. The first electrode includes an ohmic electrode layer of AuZn or Au, etc., and a bonding material layer composed of a eutectic material such as AuSn and becomes a part of the bonding layer 8 as shown in FIG. 13(d). In this case, a reflecting layer of SiO2 may be provided partly on a side of the first electrode 21 against the epitaxial grown layer 9. In FIG. 13(d), aside from the process shown in FIGS. 13(a)-(c), a common substrate 6 is prepared. The common substrate 6 may be manufactured of a Si-based semiconductor. In this case, the material is not limited to the Si-based semiconductor so long as it is higher in thermal conductivity and better in electrical conductivity than the GaAs-based grown substrate 20, for example. Further, a material having desired properties (such as high electric conductivity, high transmissivity, high thermal conductivity and high strength) may be selected from Al2O3, SiC and GaP for the use in accordance with the targeted composite semiconductor device. Further, in FIG. 13(e), a second electrode 22 that is to be turned into a part of the bonding layer 8 is formed on one surface of the common substrate 6 and a third electrode 23 that is to be turned into the first external connection electrode 7 is formed on the other surface. The second electrode 22 includes a wet layer of Ti or Ni and a bonding metal layer of Au formed in order from the common substrate 6. The third electrode 23 includes a wet layer of Ti or Ni and an external connection metal layer of Au formed in order from the common substrate 6. Next, the grown substrate 20 (after the completion of the processes shown in FIGS. 13(a)-(c)) and the common substrate 6 (after the completion of the processes shown in FIGS. 13(d)-(e)) are assembled. In FIG. 13(f), the first electrode 21 on the grown substrate 20 is opposed to the second electrode 22 on the common substrate 6. In FIG. 13(g), the first electrode 21 on the grown substrate 20 and the second electrode 22 on the common substrate 6 are brought into contact with each other and heated and pressurized to bond both the electrodes 21 and 22 together. In this case, the bonding layer of AuSn contained in the first electrode 21 and the bonding metal layer of Au contained in the second electrode 22 are mainly molten and mixed such that the bonded portion becomes the bonding layer 8. It is possible to provide layers in accordance with desired light emitting device properties, such as a barrier layer, a light reflecting layer, a wet layer and an intimate contact layer, between the common substrate 6 and the epitaxial grown layer 9. These layers may be previously provided on the first electrode. Further, other than bonding both together via the eutectic material such as AuSn as is shown in the above FIG. 13(g), processes for bonding both together via a solder material, or bonding both together via a resinous adhesive may also be available. Alternatively, bonding both together only by thermal crimping without interposing a metal material therebetween may be available (in this case, the electrodes 21, 22 and the bonding layer 8 are not formed). In FIG. 13(h), the grown substrate 20 is removed through a method of etching or the like. Depending on the composite semiconductor device, this process may not be executed to leave the grown substrate. In FIG. 13(i), a plurality of fourth electrodes 24 composed of AuGeNi or the like which can be turned into the second external connection electrodes 10 are formed at certain positions on the epitaxial grown layer 9 and alloyed. In FIG. 13(j), a plurality of notches 11 having a certain shape and size are formed by etching or the like at certain positions so as to extend from the epitaxial grown layer 9 through the bonding layer 8 to the common substrate 6. The process shown in FIG. 13(j) may be executed simultaneously with the removal of the grown substrate 20 shown in FIG. 13(h). It is further possible to form recesses into the common substrate. The notch 1 is not always required to reach the common substrate 6 but may be formed to reach the bonding layer 8 located between the epitaxial grown layer 9 and the common substrate 6. In the above FIG. 13(b), the epitaxial grown layer 9 may not be previously provided in the region to be turned into the recess, thereby omitting the above process shown in FIG. 13(j). In FIG. 13(k), a fifth electrode 26 composed of AuZn or Au or the like which can be turned into the light emitting device bonding electrode 12 is formed on the bottom 25 of each recess 11. In this case, if the notches 11 formed as shown in FIG. 13(j) are stopped in the epitaxial grown layer 9 to leave the bonding layer 8 as it is, this process is not required. In FIG. 13(l), a light emitting device 27 which can be turned into the second light emitting device 5 is mounted on the fifth electrode 26 through a method using eutectics or bumps or the like. If a semiconductor light emitting device of the flip-chip type is used as the second semiconductor light emitting device 5 (not shown), the electrode on the semiconductor light emitting device is mounted on the fifth electrode 26 via bumps. In FIG. 13(m), certain dicing positions are set. In FIG. 13(n), the assembly is diced to individual pieces to complete the composite semiconductor device 1. It is also possible to omit the process shown in FIG. 13(l) and establish a flow of processes for mounting the light emitting device 27 on the diced individual piece. The notch 11 for receiving the light emitting device 27 mounted therein may be formed by forming a hole through the subassembly after the process shown in FIG. 13(c) is accomplished and at the position for forming the notch 11 therein. Then, this subassembly is bonded with the common substrate 6, thereby forming the notch at the position of the through-hole on the common substrate. In this case, forming of the notch 11 and forming of the fifth electrode 26 can be omitted. The second light emitting device 5 corresponds to an LED, which is classified in accordance with the structure of the light emitting layer into a simple PN junction structure, a single-hetero (SH) structure, a double-hetero (DH) structure and a quantum well structure. An appropriate light emitting device is selected from those to realize a desired composite semiconductor device 1. The combination of the first light emitting device 3 and the second light emitting device 5 for configuring the composite semiconductor device 1 may be set arbitrarily or according to certain desires, etc. For example, it is possible to realize a composite semiconductor device capable of emitting a multi-colored light through a combination of light emitting devices having different emission spectra. It is also possible to realize a composite semiconductor device capable of executing light output control and distribution control through a combination of light emitting devices having the same emission spectrum. The number and arrangement of the second light emitting devices 5 mounted on the common substrate 6 can also be set arbitrarily or according to particular desires. For example, in order to suppress the variation in chromaticity of light from the composite semiconductor device 1, the devices 5 can be arranged at symmetrical positions about the center of the composite semiconductor device 1. The position for providing the notch or the recess is not limited to the corner of the common substrate as shown. The first semiconductor light emitting device 3 can be shaped and sized in accordance with the second light emitting device 5. In particular, it can be formed in a desired shape along the shape of the second light emitting device 5. The fifth electrode 26 (light emitting device bonding electrode 12) on the common substrate 6 and the lower electrode 13 on the second light emitting device 5 may be bonded with each other arbitrarily or at certain desired locations. For example, it is possible to perform eutectic bonding or flip-chip mounting with interposition of bump balls 28 of Au or the like as shown in FIG. 14. In particular, from the viewpoint of shortening the distance between the light emitting region in the first light emitting device and the second light emitting device, the use of flip-chip mounting can be used. The first external connection electrode 7 on the first light emitting device 3 and the lower electrode 13 on the second light emitting device 5 can be of the same conduction type. Therefore, the second external connection electrode 10 on the first light emitting device 3 and the upper electrode 14 on the second light emitting device 5 can be of the same conduction type as well. The embodiments associated with the semiconductor composition device of the disclosed subject matter and the manufacturing method are described above. The following description is given to describe at least some of the effects exerted by the disclosed subject matter and the embodiments. (1) Heat Radiation The second light emitting device (LED) can be mounted on the common substrate composed of a material higher in thermal conductivity than the material (for example, a GaAs-based semiconductor) of the epitaxial grown layer containing a light emitting layer. (If the epitaxial grown layer is composed of the GaAs-based semiconductor, the common substrate is composed of a Si-based semiconductor). Therefore, self-produced heat can be transferred externally efficiently from the LED (for example, to the mounting board), thereby improving the effect on heat radiation, at least more so than the case when the LED is mounted on the epitaxial grown layer,. (2) Color Mixture A plurality of light emitting units operative to emit light having different emission spectra may be provided to obtain an arbitrary (or particularly desired) chromaticity light through the additional color mixture of lights from the light emitting units. In this case, in order to ensure an excellent color mixture with less variation in chromaticity, the distance between adjacent light emitting units can be shortened. As described above, in the disclosed subject matter, the first light emitting device 3 can be shaped and sized in accordance with the second light emitting device 5. In particular, it can be formed in a desired shape that is similar to the shape of the second light emitting device 5. Therefore, this semiconductor composition device of the disclosed subject matter can be fabricated without leaving any useless space between both light emitting devices (between light emitting regions) and thus it is obviously excellent in color mixture. When a light emitting device is mounted on a substrate, an electrode on the light emitting device and the corresponding electrode of the substrate are connected via either one of a eutectic material, a solder, a bump ball, a conductive paste, etc. In mounting the light emitting device, high-reflectance, white plastic casing such as a nylon-based material may be used to effectively utilize the light emitted from the light emitting device as illuminative light through the use of the reflection from the plastic casing. When mounting the light emitting device in the plastic casing, it may be considered to use one of the above eutectic material, the solder, the bump ball, the conductive paste, etc., though, in practice, conditions for use impart restrictions, which leave some of the materials inappropriate. For example, eutectic bonding of a material such as AuSn generally requires heating at around 280° C. The heat on eutectic bonding also acts on the plastic casing and thermally deteriorates the plastic casing (changes the color to brown or yellow) to lower the reflectance. As a result, the efficiency of extracting the emitted light from the light emitting device lowers and causes a reduction in brightness. A conductive paste (silver paste) that is configured for use at a temperature lower than the eutectic temperature is employed to avoid such a problem. The conductive paste has a hardening temperature of around 160° C. Therefore, it is possible to ensure high brightness without deteriorating the plastic casing. If the conductive paste is used to mount a plurality of individual light emitting devices, the spread of the conductive paste upon mounting is wider than those of other bonding materials and accordingly causes the following problem. Namely, when the light emitting device has a size of 0.3 mm×0.3 mm as shown in FIG. 16, the spread of the conductive paste has a diameter of 0.5 mm. Therefore, if three light emitting devices are located on apexes of a right triangle, respectively, the distance between adjacent conductive pastes may be set at a minimum distance of 0.1 mm to prevent them from short-circuiting. In this case, the distance between adjacent light emitting devices becomes 0.22 mm at a minimum. On the other hand, another composite semiconductor device of the disclosed subject matter can be configured as shown in FIG. 15 in which spacer structures such as eutectic material or bump balls can be employed in bonding between the common substrate and the second light emitting device. Namely, if the second light emitting device has dimensions of 0.3 mm×0.3 mm and is mounted on the common substrate through eutectic bonding as described above, the distance between the first light emitting device and the second light emitting device can be 0.1 mm. Further, flip mounting with interposition of bump balls can shorten it to 0.05 mm. If the light emitting devices as shown in FIGS. 15 and 16 are devices that emit light having different emission spectra, a composite semiconductor device of the disclosed subject matter with a shorter distance between adjacent light emitting devices is obviously better in color mixture. If a composite semiconductor device of the disclosed subject matter is mounted in the plastic casing, the conductive paste can be used even though a nice color mixture has been already ensured at that moment and, accordingly, the above problem is prevented or not caused. (3) Quality/Stability In a composite semiconductor device made in accordance with principles of the disclosed subject matter, the second light emitting device with selected properties such as a particular optical property and electrical property can be mounted on the common substrate. This is different from the direction for forming a plurality of grown layers each containing a light emitting layer on the common substrate as in the conventional art. Accordingly, it is possible to fabricate a composite semiconductor device with less variation in properties and with excellent reproducibility. For example, a combination of a second light emitting device selected in accordance with the emission of light from the light emitting device facilitates the color tone control of the composite semiconductor device. (4) Flexibility of Selection of Light Emitting Devices In another composite semiconductor device made in accordance with principles of the disclosed subject matter, the second semiconductor light emitting device can be mounted on the common substrate through methods such as various mounting methods of eutectic bonding and of flip-chip mounting with interposition of bump balls, etc., as described above. In accordance with the methods, the second semiconductor light emitting device may be one of a light emitting device of the type that comprises a pair of electrodes on opposite sides and types that comprise a pair of electrodes on one side. Even if the second semiconductor light emitting device 5 has an upper electrode 14 that requires wire bonding, the reliability of the first semiconductor light emitting device is not impaired. As it is possible to select various mounting methods in this way, the range of usable light emitting devices can be extended so as to increase the flexibility of design and device selection. (5) High Brightness A composite semiconductor device made in accordance with principles of the disclosed subject matter may be used to configure a full-color light emitting device. In this case, a green (G) light emitting device is mounted as the first light emitting device on the common substrate, and two devices or a red (R) light emitting device and a blue (B) light emitting device can be configured as the second light emitting devices. When a white (W) light is formed through additional color mixture of R, G, B lights, it is generally appropriate to use a proportion of the amounts of R, G, B light as R:G:B=3:6:1. The green light requires the largest amount of light. In the current state, however, green light emitting devices are generally inferior in terms of emission efficiency as compared to other devices. Therefore, a device for emitting white light supplies a larger current to the green light emitting device than to other light emitting devices to keep the amounts of R, G, B lights in balance. If the red, green and blue light emitting devices have almost the same emission area, the rating current can be determined from the green light emitting device and only a slight current is allowed to flow in the red and blue light emitting devices at that time. Therefore, the white light is of lower brightness even if it can be obtained. On the contrary, in at least one example of a composite semiconductor device of the disclosed subject matter, as described above, the first light emitting device that is larger in emission area is mounted as the green light emitting device on the common substrate, and two devices (i.e., the red and blue light emitting devices) are smaller in emission area than the green light emitting device to form the second light emitting devices. Therefore, it is possible to increase the amount of the green light while keeping the current density in the emission surface almost unchanged, thereby realizing high brightness while retaining reliability. A composite semiconductor device of the disclosed subject matter can be formed in the following exemplary configurations: a LCD back light in mobile instruments such as cell phones; a LCD back light in vehicular instruments; a LCD back light in TV and PC monitors; and a light source in various indicators. While there has been described what are at present considered to be exemplary embodiments of the invention, it will be understood that various modifications may be made thereto, and it is intended that the appended claims cover such modifications as fall within the true spirit and scope of the invention. All conventional art references described above are herein incorporated in their entirety by reference.	H	67H01	185H01L	29	06
11683648	US20080220609A1-20080911	Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing	ACCEPTED	20080828	20080911	[]	H01L21302	["H01L21302"]	7541290	20070308	20090602	438	689000	95738.0	CHEN	KIN CHAN	[{"inventor_name_last": "Chang", "inventor_name_first": "Chong Kwang", "inventor_city": "Kangwon", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Park", "inventor_name_first": "Wan Jae", "inventor_city": "Kyunggi", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Tsou", "inventor_name_first": "Len Yuan", "inventor_city": "New York City", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Zhuang", "inventor_name_first": "Haoren", "inventor_city": "Hopewell Junction", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Lipinski", "inventor_name_first": "Matthias", "inventor_city": "Poughkeepsie", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Mishra", "inventor_name_first": "Shailendra", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}]	Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).	1. A method of forming an integrated circuit device, comprising the steps of: forming a first electrically insulating layer on a semiconductor wafer; forming mask pattern on the first electrically insulating layer; selectively widening first portions of the mask pattern extending adjacent a periphery of the semiconductor wafer relative to second portions of the mask pattern extending adjacent an interior of the semiconductor wafer, by depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern while simultaneously controlling a temperature of the semiconductor wafer to having a nonuniform center-to-edge temperature profile; and selectively etching the electrically insulating layer using the mask pattern with the selectively widened portions as an etching mask. 2. The method of claim 1, wherein the second electrically insulating layer is an organic polymer layer. 3. The method of claim 1, wherein the second electrically insulating layer comprises carbon and fluorine. 4. The method of claim 1, wherein the second electrically insulating layer is a CxFy or CxHyFz layer. 5. A method of forming an integrated circuit device, comprising the steps of: forming mask pattern on a semiconductor wafer; and selectively widening first portions of the mask pattern extending adjacent a periphery of the semiconductor wafer relative to second portions of the mask pattern extending adjacent an interior of the semiconductor wafer, by depositing an electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern while simultaneously controlling a temperature of the semiconductor wafer to having a nonuniform center-to-edge temperature profile. 6. The method of claim 5, wherein the electrically insulating layer is an organic polymer layer. 7. The method of claim 5, wherein the electrically insulating layer comprises carbon and fluorine. 8. The method of claim 5, wherein the electrically insulating layer is a CxFy or CxHyFz layer.	<SOH> BACKGROUND OF THE INVENTION <EOH>Processes for fabricating integrated circuit devices typically include the formation of a relatively large array of integrated circuits that are replicated at side-by-side locations on an integrated circuit wafer. These fabricating processes also typically include the formation of multiple levels of electrically insulating layers that extend across the entire surface of a wafer and are selectively and individually patterned using conventional photolithography techniques. During photolithography, an organic material layer, such as a photo-resist (PR) mask layer, may be deposited on an electrically insulating layer and then patterned to define a mask. This mask may contain a pattern that is replicated for each of the integrated circuits to be formed adjacent an interior of the semiconductor wafer and adjacent an edge (i.e., periphery) of the semiconductor wafer. Unfortunately, the steps to pattern the mask layer into a mask may result in mask patterns having non-uniform lateral dimensions that vary according to location on the semiconductor wafer. For example, it is not uncommon for a mask pattern that defines a critical dimension (CD) of a structure within in an integrated circuit extending adjacent the edge of the semiconductor wafer to be narrower than the corresponding mask pattern extending adjacent an interior of the semiconductor wafer (i.e., near the center of the wafer). This nonuniformity in the mask pattern dimensions, which frequently results from the non-uniform etching characteristics associated with wafer-scale etching processes, can lead to complications in wafer level processing and result in poor device yield and reliability.	<SOH> SUMMARY OF THE INVENTION <EOH>Methods of forming integrated circuit devices according to embodiments of the present invention include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographic patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.). These methods include forming a first electrically insulating layer on a semiconductor wafer and then forming a mask pattern on the first electrically insulating layer. First portions of the mask pattern, which extend adjacent a periphery of the semiconductor wafer, are selectively widened relative to corresponding second portions of the mask pattern extending adjacent an interior of the semiconductor wafer. This selective widening step is achieved by depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern. These temperature-dependent characteristics result in a second electrically insulating layer that is thicker on the peripheral portions of the semiconductor wafer and thinner on the interior portions of the semiconductor wafer. This fast (near edge) versus slow (near center) difference in the deposition rate characteristics of the second electrically insulating layer compensates for the narrower portions of the mask pattern extending adjacent the periphery of the semiconductor wafer. In some of these embodiments, the second electrically insulating layer may be an organic polymer layer, including an organic polymer layer containing carbon and fluorine, such as C x F y or C x H y F z . Moreover, the step of depositing the second electrically insulating layer is performed while simultaneously controlling a temperature of the semiconductor wafer to have a nonuniform center-to-edge temperature profile. This nonuniform temperature profile may be achieved by establishing a corresponding nonuniform temperature profile in an underlying wafer support structure (e.g., wafer stage) within a processing chamber. A photolithographically defined etching step is then performed to pattern the electrically insulating layer. This selective etching step is performed using the mask pattern with the selectively widened portions as an etching mask.	FIELD OF THE INVENTION The present invention relates to integrated circuit fabrication methods and, more particularly, to methods of fabricating mask patterns on semiconductor wafers. BACKGROUND OF THE INVENTION Processes for fabricating integrated circuit devices typically include the formation of a relatively large array of integrated circuits that are replicated at side-by-side locations on an integrated circuit wafer. These fabricating processes also typically include the formation of multiple levels of electrically insulating layers that extend across the entire surface of a wafer and are selectively and individually patterned using conventional photolithography techniques. During photolithography, an organic material layer, such as a photo-resist (PR) mask layer, may be deposited on an electrically insulating layer and then patterned to define a mask. This mask may contain a pattern that is replicated for each of the integrated circuits to be formed adjacent an interior of the semiconductor wafer and adjacent an edge (i.e., periphery) of the semiconductor wafer. Unfortunately, the steps to pattern the mask layer into a mask may result in mask patterns having non-uniform lateral dimensions that vary according to location on the semiconductor wafer. For example, it is not uncommon for a mask pattern that defines a critical dimension (CD) of a structure within in an integrated circuit extending adjacent the edge of the semiconductor wafer to be narrower than the corresponding mask pattern extending adjacent an interior of the semiconductor wafer (i.e., near the center of the wafer). This nonuniformity in the mask pattern dimensions, which frequently results from the non-uniform etching characteristics associated with wafer-scale etching processes, can lead to complications in wafer level processing and result in poor device yield and reliability. SUMMARY OF THE INVENTION Methods of forming integrated circuit devices according to embodiments of the present invention include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographic patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.). These methods include forming a first electrically insulating layer on a semiconductor wafer and then forming a mask pattern on the first electrically insulating layer. First portions of the mask pattern, which extend adjacent a periphery of the semiconductor wafer, are selectively widened relative to corresponding second portions of the mask pattern extending adjacent an interior of the semiconductor wafer. This selective widening step is achieved by depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern. These temperature-dependent characteristics result in a second electrically insulating layer that is thicker on the peripheral portions of the semiconductor wafer and thinner on the interior portions of the semiconductor wafer. This fast (near edge) versus slow (near center) difference in the deposition rate characteristics of the second electrically insulating layer compensates for the narrower portions of the mask pattern extending adjacent the periphery of the semiconductor wafer. In some of these embodiments, the second electrically insulating layer may be an organic polymer layer, including an organic polymer layer containing carbon and fluorine, such as CxFy or CxHyFz. Moreover, the step of depositing the second electrically insulating layer is performed while simultaneously controlling a temperature of the semiconductor wafer to have a nonuniform center-to-edge temperature profile. This nonuniform temperature profile may be achieved by establishing a corresponding nonuniform temperature profile in an underlying wafer support structure (e.g., wafer stage) within a processing chamber. A photolithographically defined etching step is then performed to pattern the electrically insulating layer. This selective etching step is performed using the mask pattern with the selectively widened portions as an etching mask. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow diagram of steps that illustrates methods of forming integrated circuit devices according to embodiments of the present invention. FIGS. 2A-2C are cross-sectional illustrations of intermediate structures that illustrate methods of forming integrated circuit devices according to embodiments of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout. Referring now to the flow diagram of FIG. 1, methods 100 of forming integrated circuit devices include forming a first electrically insulating layer on a primary surface of semiconductor wafer, Block 102. This first electrically insulating layer may be formed relatively close to the primary surface, or may be an inter-layer dielectric layer that is separated from the primary surface by one or more underlying layers and integrated circuit structures. This first electrically insulating layer may be formed of a material such as silicon oxide or silicon nitride, for example, however, other electrically insulating and dielectric materials may also be used. As illustrated by Blocks 104-106, an antireflective coating (ARC) layer (optional) is deposited on the first electrically insulating layer and then a mask layer is deposited on the coating. This mask layer is then photolithographically patterned to define a mask that extends across the semiconductor wafer. Portions of mask that extend adjacent a periphery of the semiconductor wafer are then selectively widened to compensate for a relative narrowing of these portions during the step of patterning the mask layer, Block 108. This step of selectively widening portions of the mask pattern is achieved by depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics, on the mask pattern. These temperature-dependent characteristics result in a second electrically insulating layer that is thicker on the peripheral portions of the semiconductor wafer and thinner on the interior portions of the semiconductor wafer. This fast (near edge) versus slow (near center) difference in the deposition rate characteristics of the second electrically insulating layer compensates for the narrower portions of the mask extending adjacent the periphery of the semiconductor wafer. The second electrically insulating layer may be an organic polymer layer, including an organic polymer layer containing carbon and fluorine, such as CxFy or CxHyFz. The step of depositing the second electrically insulating layer is performed while simultaneously controlling a temperature of the semiconductor wafer to have a nonuniform center-to-edge temperature profile. In particular, a chuck (e.g., wafer stage), which supports the semiconductor wafer in a processing chamber, may be configured to provide a high-to-low temperature profile across the wafer, with the center of the wafer being held at a higher temperature relative to an edge of the wafer. Referring now to Block 110, the first electrically insulating layer is then selectively etched, using the patterned mask layer (with selectively widened portions) as an etching mask. The patterned mask layer is then removed to complete the photolithography process, Block 112. The steps described above with respect to FIG. 1 will now be described more fully with reference to FIGS. 2A-2C. As illustrated by FIG. 2A, an electrically insulating layer 12 may be formed on a semiconductor wafer 10. This electrically insulating layer 12 may be a silicon dioxide layer that is conformally deposited across an entire surface of the semiconductor wafer 12, which includes edge, intermediate and center portions having integrated circuit structures (not shown) thereon. The edge portion extends adjacent a periphery of the semiconductor wafer 10 and the center portion extends adjacent an interior portion of the semiconductor wafer 10. The intermediate portion of the semiconductor wafer extends between the interior and edge portions of the semiconductor wafer 10. Referring still to FIG. 2A, another electrically insulating layer 14 is conformally deposited on the underlying electrically insulating layer 12. This electrically insulating layer 14 may be a silicon nitride layer or other dielectric material layer that can be etched selectively relative to the underlying electrically insulating layer 12. A bottom anti-reflective coating (i.e., BARC) layer (optional) and a layer of photoresist are then formed in sequence on the electrically insulating layer 14. Conventional mask developing and photolithographic patterning techniques may then be performed to generate a mask pattern 18 from the layer of photoresist. During this mask patterning step, the anti-reflective coating may also be selectively etched to define an anti-reflective coating pattern 16. These steps of developing the layer of photoresist may result in the generation of a mask pattern 18 having corresponding shapes with nonuniform lateral dimensions, including nonuniform critical dimensions that are wider adjacent a center of the semiconductor wafer 10 relative to an edge of the semiconductor wafer 10. Referring now to FIG. 2B, portions of the mask pattern 18 are then selectively widened by depositing an electrically insulating layer 20 having temperature-dependent deposition rate characteristics, on the mask pattern 18. According to some embodiments of the present invention, this electrically insulating layer 20 may be an organic polymer layer, such as an organic polymer layer including carbon and fluorine (e.g., CxFy or CxHyFz). During this step of depositing the electrically insulating layer 20, the semiconductor wafer 10 is maintained at a nonuniform temperature, which results in an electrically insulating layer 20 having a nonuniform thickness. In particular, the center of the semiconductor wafer 10 is maintained at a higher temperature (Tc) relative to a temperature (Ti) of an intermediate portion of the semiconductor wafer 10 and a temperature (Te) of an edge portion of the semiconductor wafer 10, where Tc>Ti>Te. These relative temperatures can be adjusted to achieve a nonuniform thickness of the electrically insulating layer 20 that compensates for the nonuniform lateral dimensions in the mask pattern 18 illustrated by FIG. 2A. This nonuniform temperature may be achieved in a deposition processing chamber, by using a wafer support stage (e.g., wafer chuck) that is configured to provide different temperatures across its surface. Based on these different temperatures, the edge, intermediate and center portions of the electrically insulating layer 20 will have different thicknesses, with the edge portion 20e being thicker than the intermediate portion 20i and the intermediate portion 20i being thicker than the center portion 20c. Referring now to FIG. 2C, a selective etching step is then performed to etch through the electrically insulating layer 14, using the mask pattern 18 and the electrically insulating layer 20 as an etching mask. This etching step results in the generation of a patterned electrically insulating layer having edge regions 14e, intermediate regions 14i and center regions 14c with sufficiently equivalent dimensions (i.e., We≈Wi≈Wc). The mask pattern 18 and the electrically insulating layer 20 is then removed. Thus, as described above with respect to FIGS. 1 and 2A-2C, methods of forming integrated circuit devices according to embodiments of the invention include forming a first electrically insulating layer on a semiconductor wafer and forming mask pattern on the first electrically insulating layer. First portions of the mask pattern that extend adjacent a periphery of the semiconductor wafer are then selectively widened relative to second portions of the mask pattern that extend adjacent an interior of the semiconductor wafer. This selective widening step is performed by depositing a second electrically insulating layer having temperature-dependent deposition rate characteristics on the mask pattern while simultaneously controlling a temperature of the semiconductor wafer to having a nonuniform center-to-edge temperature profile. The electrically insulating layer is then selectively etched using the mask pattern with the selectively widened portions as an etching mask. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.	H	67H01	185H01L	213	02
11907904	US20080136293A1-20080612	Multilayer piezoelectric element	ACCEPTED	20080530	20080612	[]	H01L41083	["H01L41083", "H01L41187"]	7518295	20071018	20090414	310	366000	92130.0	DOUGHERTY	THOMAS	[{"inventor_name_last": "Mochizuki", "inventor_name_first": "Kazuo", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Nagata", "inventor_name_first": "Kazuo", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Sawara", "inventor_name_first": "Yuzo", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}]	A multilayer piezoelectric element has a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered. The plurality of internal electrodes comprise a first electrode and a second electrode. The laminate body is provided with a metal oxide layer formed of a material with a melting point higher than a sintering temperature of the piezoelectric bodies. The laminate body has an active portion in which the first electrode and the second electrode are arranged to overlap in a laminate direction of the laminate body, and inactive portions in which the first electrode and the second electrode are arranged not to overlap in the laminate direction of the laminate body. The inactive portions are provided on both sides of the active portion. The metal oxide layer has a first region formed in the same layer as the internal electrode in the inactive portion, and a second region formed so as to extend from the first region toward the active portion and overlap the internal electrode.	1. A multilayer piezoelectric element comprising a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered, wherein the plurality of internal electrodes comprise a first electrode and a second electrode, wherein the laminate body is provided with a metal oxide layer formed of a material with a melting point higher than a sintering temperature of the piezoelectric bodies, wherein the laminate body has: an active portion in which the first electrode and the second electrode are arranged to overlap in a laminate direction of the laminate body; and inactive portions which are provided on both sides of the active portion and in which the first electrode and the second electrode are arranged not to overlap in the laminate direction of the laminate body, wherein the metal oxide layer has: a first region formed in the same layer as the internal electrode in the inactive portion; and a second region formed so as to extend from the first region toward the active portion and overlap the internal electrode. 2. The multilayer piezoelectric element according to claim 1, wherein the second region is formed so as to overlap a part of the internal electrode. 3. The multilayer piezoelectric element according to claim 1, wherein the second region is formed so as to overlap the entire internal electrode. 4. The multilayer piezoelectric element according to claim 1, wherein the piezoelectric bodies are formed of a piezoelectric material whose principal ingredient is lead zirconate titanate, and wherein the metal oxide layer is formed of a material containing at least one of ZrO2, MgO, Nb2O5, Ta2O5, CeO2, and Y2O3.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a multilayer piezoelectric element used in a fuel injection device or the like. 2. Related Background Art A conventionally known multilayer piezoelectric element is, for example, the one described in Japanese Patent Application Laid-Open No. 5-243635. The multilayer piezoelectric element described in the Laid-Open No. 5-243635 has a laminate body in which piezoelectric bodies and internal electrodes are alternately laminated, and external electrodes provided on side faces of this laminate body and connected to the internal electrodes. Metal oxide layers (alumina layers) for relaxing stress concentration occurring in the laminate body during driving of the element are provided in the same layers as the internal electrodes in the laminate body.	<SOH> SUMMARY OF THE INVENTION <EOH>When the metal oxide layers were provided simply in the same layers as the internal electrodes in the laminate body as in the above-described conventional technology, it was, however, sometimes the case that occurrence of cracks extending in the laminate direction of the laminate body was not avoided during the driving of the element. In this case, a short circuit could occur between the internal electrodes of different polarities and bring about dielectric breakdown of the element. An object of the present invention is to provide a multilayer piezoelectric element capable of surely preventing the occurrence of cracks extending in the laminate direction of the laminate body. The present invention provides a multilayer piezoelectric element comprising a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered, wherein the plurality of internal electrodes comprise a first electrode and a second electrode, wherein the laminate body is provided with a metal oxide layer formed of a material with a melting point higher than a sintering temperature of the piezoelectric bodies, wherein the laminate body has: an active portion in which the first electrode and the second electrode are arranged to overlap in a laminate direction of the laminate body; and inactive portions which are provided on both sides of the active portion and in which the first electrode and the second electrode are arranged not to overlap in the laminate direction of the laminate body, wherein the metal oxide layer has: a first region formed in the same layer as the internal electrode in the inactive portion; and a second region formed so as to extend from the first region toward the active portion and overlap the internal electrode. “The same layer as the internal electrode” stated herein is not limited only to perfectly the same layer as the internal electrode, but also includes approximately the same layer as the internal electrode. In the multilayer piezoelectric element of the present invention as described above, when a voltage is applied between the first electrode and the second electrode, an electric field is produced between them to displace portions of the piezoelectric bodies existing in the active portion, in the laminate direction of the laminate body. At this time, stress due to the displacement of the piezoelectric bodies acts on the laminate body. However, the laminate body is provided with the metal oxide layer formed of the material with the melting point higher than the sintering temperature of the piezoelectric bodies. This metal oxide layer is not fully sintered in comparison with the piezoelectric bodies, during firing of the laminate body in a production process of the element. As a result, the metal oxide layer has strength lower than the piezoelectric bodies. Such a metal oxide layer has the first region formed in the same layer as the internal electrode in the inactive portion of the laminate body, and the second region formed so as to extend from this first region toward the active portion and overlap the internal electrode. Namely, the metal oxide layer extends fully up to the interface between the piezoelectric body and the internal electrode, but the interface is weak in strength. Therefore, during the aforementioned displacement of the element, the metal oxide layer relaxes stress concentration on the laminate body and cracks (lateral cracks) are likely to run along the interface between the piezoelectric body and the internal electrode. This can surely prevent occurrence of cracks (vertical cracks) extending in the laminate direction of the laminate body. Preferably, the second region is formed so as to overlap a part of the internal electrode. In this case, the material making up the metal oxide layer does not have to be used more than necessary. Therefore, this allows us to save material cost of the metal oxide layer and reduce the time necessary for production of the multilayer piezoelectric element. The second region may be formed so as to overlap the entire internal electrode. In this case, the strength of the interface becomes much weaker between the piezoelectric body and the internal electrode, and therefore lateral cracks become more likely to run along the interface between the piezoelectric body and the internal electrode. Preferably, the piezoelectric bodies are formed of a piezoelectric material whose principal ingredient is lead zirconate titanate, and the metal oxide layer is formed of a material containing at least one of ZrO 2 , MgO, Nb 2 O 5 , Ta 2 O 5 , CeO 2 , and Y 2 O 3 . ZrO 2 , MgO, Nb 2 O 5 , Ta 2 O 5 , CeO 2 , and Y 2 O 3 are materials which have the melting point higher than the sintering temperature of lead zirconate titanate and which are soluble in the lead zirconate titanate. Therefore, when such a material is used for the metal oxide layer, a component of the metal oxide layer becomes less likely to separate out in grain boundaries of the piezoelectric bodies during the firing of the laminate body and it suppresses increase in the number of grain boundaries per unit thickness in the piezoelectric bodies. This is believed to suppress thermal loss occurring in grain boundaries of the piezoelectric bodies when a voltage (electric field) is applied between the first electrode and the second electrode. Therefore, a desired displacement against the applied electric field can be achieved upon displacement of the element. The decrease in the number of grain boundaries per unit thickness in the piezoelectric bodies makes vertical cracks less likely to occur in the laminate body. The present invention surely prevents the occurrence of cracks extending in the laminate direction of the laminate body and improves durability of the multilayer piezoelectric element. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer piezoelectric element used in a fuel injection device or the like. 2. Related Background Art A conventionally known multilayer piezoelectric element is, for example, the one described in Japanese Patent Application Laid-Open No. 5-243635. The multilayer piezoelectric element described in the Laid-Open No. 5-243635 has a laminate body in which piezoelectric bodies and internal electrodes are alternately laminated, and external electrodes provided on side faces of this laminate body and connected to the internal electrodes. Metal oxide layers (alumina layers) for relaxing stress concentration occurring in the laminate body during driving of the element are provided in the same layers as the internal electrodes in the laminate body. SUMMARY OF THE INVENTION When the metal oxide layers were provided simply in the same layers as the internal electrodes in the laminate body as in the above-described conventional technology, it was, however, sometimes the case that occurrence of cracks extending in the laminate direction of the laminate body was not avoided during the driving of the element. In this case, a short circuit could occur between the internal electrodes of different polarities and bring about dielectric breakdown of the element. An object of the present invention is to provide a multilayer piezoelectric element capable of surely preventing the occurrence of cracks extending in the laminate direction of the laminate body. The present invention provides a multilayer piezoelectric element comprising a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered, wherein the plurality of internal electrodes comprise a first electrode and a second electrode, wherein the laminate body is provided with a metal oxide layer formed of a material with a melting point higher than a sintering temperature of the piezoelectric bodies, wherein the laminate body has: an active portion in which the first electrode and the second electrode are arranged to overlap in a laminate direction of the laminate body; and inactive portions which are provided on both sides of the active portion and in which the first electrode and the second electrode are arranged not to overlap in the laminate direction of the laminate body, wherein the metal oxide layer has: a first region formed in the same layer as the internal electrode in the inactive portion; and a second region formed so as to extend from the first region toward the active portion and overlap the internal electrode. “The same layer as the internal electrode” stated herein is not limited only to perfectly the same layer as the internal electrode, but also includes approximately the same layer as the internal electrode. In the multilayer piezoelectric element of the present invention as described above, when a voltage is applied between the first electrode and the second electrode, an electric field is produced between them to displace portions of the piezoelectric bodies existing in the active portion, in the laminate direction of the laminate body. At this time, stress due to the displacement of the piezoelectric bodies acts on the laminate body. However, the laminate body is provided with the metal oxide layer formed of the material with the melting point higher than the sintering temperature of the piezoelectric bodies. This metal oxide layer is not fully sintered in comparison with the piezoelectric bodies, during firing of the laminate body in a production process of the element. As a result, the metal oxide layer has strength lower than the piezoelectric bodies. Such a metal oxide layer has the first region formed in the same layer as the internal electrode in the inactive portion of the laminate body, and the second region formed so as to extend from this first region toward the active portion and overlap the internal electrode. Namely, the metal oxide layer extends fully up to the interface between the piezoelectric body and the internal electrode, but the interface is weak in strength. Therefore, during the aforementioned displacement of the element, the metal oxide layer relaxes stress concentration on the laminate body and cracks (lateral cracks) are likely to run along the interface between the piezoelectric body and the internal electrode. This can surely prevent occurrence of cracks (vertical cracks) extending in the laminate direction of the laminate body. Preferably, the second region is formed so as to overlap a part of the internal electrode. In this case, the material making up the metal oxide layer does not have to be used more than necessary. Therefore, this allows us to save material cost of the metal oxide layer and reduce the time necessary for production of the multilayer piezoelectric element. The second region may be formed so as to overlap the entire internal electrode. In this case, the strength of the interface becomes much weaker between the piezoelectric body and the internal electrode, and therefore lateral cracks become more likely to run along the interface between the piezoelectric body and the internal electrode. Preferably, the piezoelectric bodies are formed of a piezoelectric material whose principal ingredient is lead zirconate titanate, and the metal oxide layer is formed of a material containing at least one of ZrO2, MgO, Nb2O5, Ta2O5, CeO2, and Y2O3. ZrO2, MgO, Nb2O5, Ta2O5, CeO2, and Y2O3 are materials which have the melting point higher than the sintering temperature of lead zirconate titanate and which are soluble in the lead zirconate titanate. Therefore, when such a material is used for the metal oxide layer, a component of the metal oxide layer becomes less likely to separate out in grain boundaries of the piezoelectric bodies during the firing of the laminate body and it suppresses increase in the number of grain boundaries per unit thickness in the piezoelectric bodies. This is believed to suppress thermal loss occurring in grain boundaries of the piezoelectric bodies when a voltage (electric field) is applied between the first electrode and the second electrode. Therefore, a desired displacement against the applied electric field can be achieved upon displacement of the element. The decrease in the number of grain boundaries per unit thickness in the piezoelectric bodies makes vertical cracks less likely to occur in the laminate body. The present invention surely prevents the occurrence of cracks extending in the laminate direction of the laminate body and improves durability of the multilayer piezoelectric element. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention. Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a multilayer piezoelectric element according to the first embodiment. FIG. 2 is a side view of the multilayer piezoelectric element shown in FIG. 1. FIG. 3 is a partly enlarged sectional view showing a layer structure of a laminate body shown in FIG. 1. FIG. 4 is a drawing showing steps of forming an electrode pattern and a ZrO2 paste layer over a green sheet, in production of the multilayer piezoelectric element shown in FIG. 1. FIG. 5 is an exploded perspective view of a green laminate body obtained by laminating plural types of green sheets including those as shown in FIG. 4. FIG. 6 is a side view showing a multilayer piezoelectric element according to the second embodiment. FIG. 7 is a partly enlarged sectional view showing a layer structure of a laminate body shown in FIG. 6. FIG. 8 is a partly enlarged sectional view showing a modification example of the layer structure of the laminate body. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the multilayer piezoelectric element according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a perspective view showing the multilayer piezoelectric element according to the first embodiment, FIG. 2 a side view of the multilayer piezoelectric element shown in FIG. 1, and FIG. 3 a partly enlarged sectional view showing a layer structure of the multilayer piezoelectric element shown in FIG. 1. In each drawing, the multilayer piezoelectric element 1 of the present embodiment is one used, for example, in a fuel injection device of an internal combustion engine mounted on an automobile. The multilayer piezoelectric element 1 has a laminate body 2 of quadrangular prism shape. The laminate body 2 is formed by laminating a plurality of piezoelectric bodies 3 and a plurality of internal electrodes 4A, 4B in a predetermined order and sintering them. The dimensions of the laminate body 2 are, for example, width 10 mm×depth 10 mm×height 35 mm. The piezoelectric bodies 3 are made, for example, of a piezoelectric ceramic material whose main ingredient is PZT (lead zirconate titanate). The thickness of the piezoelectric bodies 3 is, for example, approximately 80-100 μm per layer. The composition of PZT used herein is, for example, as follows. Pb0.999[(Zn1/3Nb2/3)0.11 Ti0.425 Zr0.465]O3+0.2 wt % Fe2O3+0.2 wt % Sb2O3 The powder characteristics of PZT employed herein are, for example, the BET specific surface area of about 2.5 m2/g and the average particle size of about 0.6 μm. The sintering temperature of PZT is about 950° C. The melting point of PZT-based materials is about 1300° C. The internal electrodes 4A, 4B are made, for example, of an electroconductive material whose principal ingredients are Ag and Pd. The thickness of the internal electrodes 4A, 4B is, for example, approximately 2 μm. The internal electrodes 4A, 4B are alternately laminated with a piezoelectric body 3 in between. One end of each internal electrode 4A is exposed in one side face 2a of the laminate body 2 and the other end of the internal electrode 4A is located inside the other side face 2b of the laminate body 2. One end of each internal electrode 4B is exposed in the side face 2b of the laminate body 2 and the other end of the internal electrode 4B is located inside the side face 2a of the laminate body 2. This arrangement causes parts of the internal electrodes 4A, 4B to overlap each other in the laminate direction of the laminate body 2. In the laminate body 2, the portions where the internal electrodes 4A, 4B overlap in the laminate direction constitute an active portion P in which the piezoelectric bodies 3 are displaced with application of a voltage to the internal electrodes 4A, 4B. In the laminate body 2, the portions where the internal electrodes 4A, 4B do not overlap in the laminate direction (i.e., the two side ends of the laminate body 2) constitute inactive portions Q in which the piezoelectric bodies 3 are not displaced with application of the voltage to the internal electrodes 4A, 4B. In the laminate body 2 a plurality of metal oxide layers 5 are formed of an electrical insulating material with the density (strength) lower than that of the piezoelectric bodies 3. Each metal oxide layer 5 consists of an isolayer region 5a formed in the same layer as the internal electrode 4A, 4B in the inactive portion Q, and an overlap region 5b formed so as to extend from the isolayer region 5a toward the active portion P and overlap a part of the upper surface of the internal electrode 4A, 4B. The isolayer region 5a located in the same layer as the internal electrode 4A is exposed in the side face 2b of the laminate body 2. The isolayer region 5a located in the same layer as the internal electrode 4B is exposed in the side face 2a of the laminate body 2. Namely, each metal oxide layer 5 extends from the side face 2a, 2b of the laminate body 2 up to the active portion P so as to contact the internal electrode 4A, 4B. The thickness of the isolayer region 5a is, for example, equal to the thickness of the internal electrode 4A, 4B. The metal oxide layers 5 are made of a material which has the melting point higher than the sintering temperature of PZT being the principal ingredient of the piezoelectric bodies 3 and which is soluble in PZT. Such materials include materials containing at least one of ZrO2, MgO, Nb2O5, Ta2O5, CeO2, and Y2O3. The metal oxide layers 5 and the piezoelectric bodies 3 are made of their respective materials of mutually different composition systems. The melting points of ZrO2, MgO, Nb2O5, Ta2O5, CeO2, and Y2O3 are approximately 1500-2800° C. An external electrode 6A electrically connected to each internal electrode 4A is disposed on the side face 2a of the laminate body 2, and an external electrode 6B electrically connected to each internal electrode 4B is disposed on the side face 2b of laminate body 2. Each external electrode 6A, 6B has an electrode portion 7 of rectangular plate shape and a corrugated electrode portion 8. The electrode portions 7 extend in the laminate direction of the laminate body 2 so as to cover the center region of the side faces 2a, 2b, respectively, of the laminate body 2. The electrode portions 8 are located outside the electrode portions 7 and extend in the laminate direction of the laminate body 2. Each electrode portion 8 is bonded to the corresponding electrode portion 7 so as to have a stretch property (flexibility) in the laminate direction of the laminate body 2. The electrode portions 7 are made, for example, of an electroconductive material whose principal ingredient is any one of Ag, Au, and Cu. The electrode portions 8 are made, for example, of Cu, a Cu alloy, Ni, an Ni alloy, a flexible board, or the like. A method of producing the above-described multilayer piezoelectric element 1 will be described below. First, an organic binder resin, an organic solvent, etc. are mixed in a ceramic powder whose principal ingredient is PZT, to prepare a paste for green sheets. Then the paste for green sheets is applied onto a carrier film (not shown), for example, by the doctor blade method to form a plurality of green sheets 9 for formation of the aforementioned piezoelectric bodies 3. Subsequently, an organic binder resin, an organic solvent, etc. are mixed in an electroconductive material to prepare a paste for electrode patterns. The electroconductive material contains Ag and Pd and, for example, can be prepared at the ratio of Ag:Pd=85:15. Then the paste for electrode patterns is printed, for example, by screen printing, as shown in FIG. 4 (a), to form electrode patterns 10A, 10B corresponding to the aforementioned internal electrodes 4A, 4B, on the respective individual green sheets 9. At this time, the electrode patterns 10A, 10B are formed in regions except for one-end-side portions corresponding to the inactive portions Q on the upper surfaces of the green sheets 9. Furthermore, an organic binder resin, an organic solvent, etc. are mixed, for example, in a ceramic powder containing ZrO2 powder, to prepare a ZrO2 paste. Particle sizes of the ZrO2 powder used herein are preferably larger than particle sizes of the piezoelectric material powder (ceramic powder) and smaller than the thickness of the electrode patterns 10A, 10B. Then the ZrO2 paste is printed, for example, by screen printing, as shown in FIG. 4 (b), to form a ZrO2 paste layer 11 on the green sheet 9 and on the electrode pattern 10A, 10B. At this time, the ZrO2 paste layer 11 is formed in an electrode-unprinted region without print of the electrode pattern 10A, 10B (the region corresponding to the aforementioned inactive portion Q) on the upper surface of each green sheet 9 and the ZrO2 paste layer 11 is also formed so as to overlap the end region on the electrode-unprinted region side on the upper surface of each electrode pattern 10A, 10B. Subsequently, as shown in FIG. 5, the green sheets 9 with the electrode pattern 10A and ZrO2 paste layer 11, and the green sheets 9 with the electrode pattern 10B and ZrO2 paste layer 11 are laminated in a predetermined order. Furthermore, a predetermined number of green sheets 9 without electrode patterns 10A, 10B nor ZrO2 paste layer 11 are laminated as protecting layers in the outermost layers. This forms a green laminate body 12. Subsequently, the green laminate body 12 is pressed in the laminate direction while being heated at the temperature of about 60° C. Thereafter, the green laminate body 12 is cut in a predetermined size, for example, with a diamond blade to obtain a chip. Then the green laminate body 12 after cut is mounted on a setter (not shown) and a degreasing (debindering) process of the green laminate body 12 is carried out at the temperature of about 400° C. for about ten hours. Then the degreased green laminate body 12 is put in a sagger furnace and the green laminate body 12 is fired, for example, at the temperature of 950-1000° C. for about two hours. This results in sintering the green sheets 9, electrode patterns 10A, 10B, and ZrO2 paste layers 11 and obtaining the laminate body 2 as a sintered body. At this time, since the ZrO2 paste layers 11 are made of the material of the composition system, different from that of the green sheets 9, sintering reactivity is suppressed between the ZrO2 paste layers 11 and the green sheets 9, without occurrence of unwanted chemical reaction between them. In addition, since the melting point of the ZrO2 paste layers 11 is higher than the sintering temperature of the green sheets 9, the ZrO2 paste layers 11 are less likely to be sintered than the green sheets 9. For this reason, after the sintering step, the ZrO2 paste layers 11 become the metal oxide layers 5 with low bond strength to the piezoelectric bodies 3. Each metal oxide layer 5 has the isolayer region 5a and overlap region 5b as described above. However, constriction of the green laminate body 12 due to the firing makes the thickness of the overlap region 5b over the internal electrode 4A, 4B, smaller than the thickness of the isolayer region 5a. Next, the external electrodes 6A, 6B are formed on the side faces 2a, 2b, respectively, of the laminate body 2. Specifically, for example, an electroconductive paste whose principal ingredient is Ag is printed by screen printing on the side faces 2a, 2b of the laminate body 2 and a baking treatment is carried out, for example, at the temperature of about 700° C. to form the electrode portions 7 on the side faces 2a, 2b of the laminate body 2. The electrode portions 7 may also be formed by any other method such as sputtering or electroless plating. Then the corrugated electrode portions 8 are bonded to the respective electrode portions 7, for example, by soldering. Finally, a polarization process is carried out by applying a predetermined voltage, for example, at the temperature of 120° C., for example, for three minutes so that the intensity of the electric field in the thickness direction of the piezoelectric bodies 3 becomes about 2 kV/mm. The above completes the multilayer piezoelectric element 1 as shown in FIGS. 1 to 3. In the multilayer piezoelectric element 1 produced in this manner, when a voltage is applied between the external electrodes 6A, 6B, the voltage is applied between the internal electrodes 4A, 4B connected to the external electrodes 6A, 6B, to produce an electric field between them, whereby the portions of the piezoelectric bodies 3 in the active portion P are displaced in the laminate direction of the laminate body 2. At this time, stress appears in the borders between the active portion P and the inactive portions Q in the laminate body 2. Since the plurality of metal oxide layers 5 are formed in the inactive portions Q, the stress on the laminate body 2 is concentrated on the ends on the isolayer region 5a side of the metal oxide layers 5. Therefore, cracks extending in the laminate direction of the laminate body 2 (vertical cracks) are less likely to occur. Each metal oxide layer 5 has the isolayer region 5a formed in the same layer as the internal electrode 4A, 4B in the inactive portion Q of the laminate body 2, and the overlap region 5b formed so as to extend from this isolayer region 5a toward the active portion P and overlap on the internal electrode 4A, 4B. Namely, each metal oxide layer 5 extends from the side face 2a, 2b of the laminate body 2 to the interface between the piezoelectric body 3 and the internal electrode 4A, 4B. The piezoelectric bodies 3 are made of the piezoelectric ceramic material whose principal ingredient is PZT, and the internal electrodes 4A, 4B are made of the electroconductive material; therefore, the adhesive force is weak between the piezoelectric bodies 3 and the internal electrodes 4A, 4B and the interfaces between them are low in strength. Therefore, when the voltage is applied between the external electrodes 6A, 6B to drive (displace) the multilayer piezoelectric element 1, cracks (lateral cracks) are likely to run along the interfaces between the piezoelectric bodies 3 and the internal electrodes 4A, 4B. For this reason, vertical cracks become more unlikely to occur in the laminate body 2. During the aforementioned polarization process stress is also produced in the laminate body 2 because of application of the electric field, but the existence of the metal oxide layers 5 makes vertical cracks less likely to occur in the laminate body 2, as during the driving of the multilayer piezoelectric element 1. Incidentally, if the material for making up the metal oxide layers 5 is a material that reacts with the Pb-based material to form a liquid phase, e.g., like Al2O3, SiO2, or P2O5, these materials are not dissolved in PZT and are likely to form grain boundaries. Therefore, for example, when the green laminate body including Al2O3 paste layers is fired, Al2O3 separates out in grain boundaries of the green sheets 9. For this reason, it impedes growth of particles of PZT and increases the number of grain boundaries per unit thickness in the green sheets 9. In this case, when the electric field is applied between the internal electrodes 4A, 4B in the multilayer piezoelectric element after produced, thermal loss occurs because of the grain boundaries of the piezoelectric bodies 3. This could result in failing to achieve sufficient displacement of the piezoelectric bodies 3 against the applied electric field. In the present embodiment the material to be soluble in PZT, such as ZrO2, MgO, Nb2O5, Ta2O5, CeO2, or Y2O3, is used as the material for making up the metal oxide layers 5. For this reason, the component such as ZrO2 does not separate out in the grain boundaries of the green sheets 9 during the firing of the green laminate body 12, and this facilitates growth of particles of PZT and suppresses increase in the number of grain boundaries per unit thickness in the green sheets 9. Therefore, the thermal loss due to grain boundaries in the piezoelectric bodies 3 is reduced when the electric field is applied between the internal electrodes 4A, 4B in the multilayer piezoelectric element 1 after produced. This results in achieving sufficient displacement of the piezoelectric bodies 3 against the applied electric field and thus ensuring a desired piezoelectric property. Since the number of grain boundaries per unit thickness is reduced in the piezoelectric bodies 3, cracks are prevented from running in random directions along grain boundaries in the piezoelectric bodies 3. This also makes vertical cracks less likely to occur in the laminate body 2. In the present embodiment, as described above, the vertical cracks are prevented from occurring in the laminate body 2 during the driving and the polarization process of the multilayer piezoelectric element 1. This prevents a short circuit between the internal electrodes 4A, 4B and thus avoids dielectric breakdown of the multilayer piezoelectric element 1. It is also feasible to suppress degradation of the piezoelectric property of the multilayer piezoelectric element 1. As a result, it is feasible to improve the durability and performance of the multilayer piezoelectric element 1. FIG. 6 is a side view of the multilayer piezoelectric element according to the second embodiment and FIG. 7 a partly enlarged sectional view showing a layer structure of the multilayer piezoelectric element shown in FIG. 6. In the drawings identical or equivalent elements to those in the first embodiment will be denoted by the same reference symbols, without redundant description. In each drawing, the multilayer piezoelectric element 1 of the present embodiment has the laminate body 2 consisting of the piezoelectric bodies 3, internal electrodes 4A, 4B, and metal oxide layers 5 as in the first embodiment. Each metal oxide layer 5 consists of an isolayer region 5a formed in the same layer as the internal electrode 4A, 4B in the inactive portion Q of the laminate body 2, and an overlap region 5b formed so as to extend from this isolayer region 5a toward the active portion P and overlap the entire upper surface of the internal electrode 4A, 4B. Namely, each metal oxide layer 5 extends from the side face 2a to the side face 2b of the laminate body 2 so as to contact the internal electrode 4A, 4B. For forming the metal oxide layers 5 of this configuration, as shown in FIG. 4 (a) described above, the electrode pattern 10A, 10B is first formed in a partial region on the upper surface of each green sheet 9, thereafter, for example, the aforementioned ZrO2 paste is printed by screen printing to form the ZrO2 paste layer 11 (cf. FIG. 4) on the electrode-unprinted region of the upper surface of the green sheet 9 and on the entire upper surface of the electrode pattern 10A, 10B. Thereafter, laminating, pressing, cutting, debindering, and firing are successively carried out in the same manner as in the first embodiment. In the present embodiment of this configuration, occurrence of vertical cracks in the laminate body 2 can also be prevented during the driving and the polarization process of the multilayer piezoelectric element 1, and this leads to improvement in the durability of the multilayer piezoelectric element 1. It is noted that the present invention is by no means limited to the above embodiments. For example, the above embodiments showed the configurations wherein the overlap region 5b of each metal oxide layer 5 overlapped over the internal electrode 4A, 4B, but it is also possible to adopt a configuration wherein at least a part of the internal electrode 4A, 4B overlaps over the overlap region 5b of the metal oxide layer 5. From the invention thus described, it will be obvious that the invention may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.	H	67H01	185H01L	410	83
11925352	US20080044959A1-20080221	BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES	ACCEPTED	20080206	20080221	[]	H01L2186	["H01L2186"]	7608506	20071026	20091027	438	257000	61099.0	LEBENTRITT	MICHAEL	[{"inventor_name_last": "Cheng", "inventor_name_first": "Kangguo", "inventor_city": "Guilderland", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Hsu", "inventor_name_first": "Louis", "inventor_city": "Fishkill", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Mandelman", "inventor_name_first": "Jack", "inventor_city": "Flat Rock", "inventor_state": "NC", "inventor_country": "US"}]	A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.	1. A method for forming a semiconductor structure in a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, the method comprising: forming a plurality of trenches in the semiconductor wafer; building a plurality of vertical memory cells each in a corresponding one of the trenches; and forming a body contact that extends substantially through the buried dielectric layer and electrically couples one of the semiconductor bodies with the semiconductor substrate. 2. The method of claim 1 wherein forming the body contact further comprising: implanting ions that stop in a region of the buried dielectric layer between two of the trenches to define the at least one body contact. 3. The method of claim 2 wherein the buried dielectric layer is a buried oxide layer containing silicon and oxygen in a first stoichiometry, and implanting ions further comprises: implanting silicon ions into the region of buried oxide layer to provide a second stoichiometry in the implanted region that differs from the first stoichiometry. 4. The method of claim 3 wherein an implanted dose of silicon ions is sufficient to sufficient to provide a second stoichiometry including about 1 atomic percent to about 6 atomic percent of silicon in excess of the first stoichiometry of the buried oxide layer. 5. The method of claim 1 wherein the vertical memory cells further include a first vertical memory cell and a second vertical memory cell adjacent to the first vertical memory cell, and further comprising: forming an insulating layer on the semiconductor body; building a plurality of word lines on the semiconductor wafer including a first word line on the insulating layer between the first and second memory cells and electrically isolated from the first and second memory cells; and removing a portion of the first word line to provide a body contact opening that exposes an area of the insulating layer overlying a region in the buried dielectric layer in which the body contact is subsequently formed. 6. The method of claim 5 wherein forming the at least one body contact further comprises: implanting ions into the region in the buried dielectric layer through the body contact opening. 7. The method of claim 6 wherein the implanted ions penetrate through the insulating layer area and an area of the semiconductor body registered vertically with the insulating layer area to reach the buried dielectric layer region. 8. The method of claim 7 wherein implanting ions further comprises: selecting a kinetic energy of the implanted ions such that the implanted ions stop predominantly in the buried dielectric layer underlying the removed portion of the first word line to define the at least one body contact. 9. The method of claim 5 wherein the word lines further include a second word line connected with an access device of the first vertical memory cell and a third word line connected with an access device of the second vertical memory cell, the second and third word lines electrically isolated from the first word line. 10. The method of claim 1 wherein each of the vertical memory cells including a storage capacitor and an access device with a vertical channel defined in the semiconductor body and a gate configured to switch current flow through the vertical channel to the storage capacitor.	<SOH> BACKGROUND OF THE INVENTION <EOH>Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. DRAM devices are also frequently embedded into application specific integrated circuits, such as processors and logic devices. A generic DRAM device includes a plurality of substantially identical semiconductor memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each memory cell array includes a plurality of memory cells arranged in rows and columns and each individual memory cell in the array is located at the intersection of a respective word line and a respective bit line. Each individual memory cell includes a storage capacitor for storing data and an access device, such as a planar or vertical metal oxide semiconductor field-effect transistor (MOSFET), for allowing the transfer of data charges to and from the storage capacitor during reading and writing operations. Either the source or drain of the access device is connected to a corresponding bit line and the gate of the access device is connected to a corresponding word line. In certain DRAM device designs, memory cells are arranged in pairs to allow sharing of a bit line contact, which significantly reduces the overall memory cell size. When the access device of one of the memory cells is activated by a signal on the word line, a data signal is transferred from the storage capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the storage capacitor of the memory cell. Because DRAM devices are a type of volatile memory that leaks stored charge, the data charge on the storage capacitor (corresponding to a “1” or “0”) is periodically refreshed during a refresh operation. When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell, which form a data line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair. One goal of memory device designers is to pack more memory cells more densely into a smaller integrated circuit. Vertical memory cells feature an architecture in which the storage capacitor and access device are stacked vertically in a common trench. Vertical memory cells afford increased packing densities and other advantages in comparison to planar memory cells, in which size reduction was realized in the past primarily by reduction of the linear dimensions (i.e., the minimum lithographic feature size, F). For example, the packing density of vertical memory cells in a DRAM device is increased because the length of the vertical access device channel is decoupled from the minimum lithographic feature size. Consequently, vertical memory cells lack the scaling problems with, for example, reducing the gate-oxide thickness and increasing the channel doping concentration encountered when scaling planar access devices to smaller sizes. The vertical memory cell architecture also allows longer channel lengths without a proportional decrease in memory density, as is true in planar memory cells. Channel length may also be properly scaled in vertical memory cells relative to gate oxide thickness and relative to junction depth to reduce channel doping, minimize junction leakage, and increase data retention times. Constructing DRAM devices using semiconductor-on-insulator (SOI) technology offers many advantages over counterpart devices built in bulk semiconductor substrates including, but not limited to, higher performance, absence of latch-up, higher packing density, and low voltage applications. In SOI technology, a thin semiconductor layer, often referred to as an SOI layer, is electrically isolated from a thicker semiconductor substrate by an insulating or dielectric material, e.g., a buried oxide or BOX layer. The access devices for the memory cells are built in a portion of the SOI layer termed the SOI body. Floating body effects occur in vertical memory cells built using SOI technology. SOI technology eliminates junction capacitance problems observed in comparable bulk devices by electrically isolating the SOI body of transistor-type access devices from the underlying semiconductor material of the substrate. However, the SOI body may float at a potential that varies according to various conditions in which the transistor-type access device is operated. Floating body effects are known to significantly degrade cell data retention time, which is most evident in long data retention time memory cells. Floating body effects originate from the accumulation of charge carriers in the channel region of the access device defined in the SOI body. A resultant leakage current is established via a parasitic bipolar transistor structure arising from the accumulated charge carriers. If uncompensated, the leakage current gradually discharges the storage capacitor. Floating body effects also cause fluctuations in the threshold voltage for the memory cell arising from the charge build up, which is extremely detrimental to conventional operation of transistor-type access devices. What is needed, therefore, is a semiconductor structure for an SOI DRAM cell array with improved cell data retention times and methods of fabricating such semiconductor structures that overcome the disadvantages of conventional semiconductor structures and conventional methods of manufacturing such semiconductor structures.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is generally directed to a semiconductor-on-insulator (SOI) structure that incorporates a body contact extending through the buried dielectric layer and, thereby, coupling an SOI body with an underlying semiconductor substrate and methods of forming such body contacts, desirably, with an ion implantation process. The structure improves the cell data retention time for a vertical memory cell in an SOI dynamic random access memory (DRAM) device by reducing floating body effects that, if uncompensated, may affect the memory cell access device and result in charge loss from the associated storage capacitor in the vertical memory cell. Specifically, charge carriers that would otherwise accumulate in the channel region of the access device are drained or discharged through a high-resistance leakage path defined by the body contact that extends to the underlying semiconductor substrate. In accordance with one aspect of the present invention, a semiconductor structure comprises a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, a buried dielectric layer separating the semiconductor substrate from the semiconductor body, and a plurality of memory cells built in an array on the semiconductor wafer. Each of the memory cells includes a storage capacitor and an access device. The access device has a vertical channel defined in one of the semiconductor bodies and a gate configured to switch current flow through the vertical channel to the storage capacitor. The structure further comprises a body contact in the buried dielectric layer. The body contact electrically couples one of the semiconductor bodies with the semiconductor substrate. In accordance with another aspect of the invention, a method for forming a semiconductor structure in a semiconductor wafer includes forming a plurality of trenches in a semiconductor wafer including a semiconductor substrate, a semiconductor layer with a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, and then building a memory cell in each of the trenches. The method further includes forming a body contact that extends substantially through the buried dielectric layer and electrically couples one of the semiconductor bodies with the semiconductor substrate.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of application Ser. No. 11/216,386, filed Aug. 31, 2005, which is hereby incorporated by reference herein in its entirety. This application is related to commonly-assigned application Ser. No. 11/216,395, filed on Aug. 31, 2005, entitled “SEMICONDUCTOR STRUCTURES WITH BODY CONTACTS AND FABRICATION METHODS THEREOF” and bearing Attorney Docket No. ROC920050178US1, which is hereby incorporated by reference herein in its entirety. FIELD OF THE INVENTION The invention relates generally to semiconductor structures and, in particular, to semiconductor structures with multiple vertical memory cells arranged to form a memory array and methods of forming such semiconductor structures. BACKGROUND OF THE INVENTION Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. DRAM devices are also frequently embedded into application specific integrated circuits, such as processors and logic devices. A generic DRAM device includes a plurality of substantially identical semiconductor memory cell arrays, a plurality of bit lines, and a plurality of word lines that intersect the bit lines. Each memory cell array includes a plurality of memory cells arranged in rows and columns and each individual memory cell in the array is located at the intersection of a respective word line and a respective bit line. Each individual memory cell includes a storage capacitor for storing data and an access device, such as a planar or vertical metal oxide semiconductor field-effect transistor (MOSFET), for allowing the transfer of data charges to and from the storage capacitor during reading and writing operations. Either the source or drain of the access device is connected to a corresponding bit line and the gate of the access device is connected to a corresponding word line. In certain DRAM device designs, memory cells are arranged in pairs to allow sharing of a bit line contact, which significantly reduces the overall memory cell size. When the access device of one of the memory cells is activated by a signal on the word line, a data signal is transferred from the storage capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the storage capacitor of the memory cell. Because DRAM devices are a type of volatile memory that leaks stored charge, the data charge on the storage capacitor (corresponding to a “1” or “0”) is periodically refreshed during a refresh operation. When data stored in one of the memory cells is read onto one of the bit lines, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell, which form a data line pair. A bit line sense amplifier connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair. One goal of memory device designers is to pack more memory cells more densely into a smaller integrated circuit. Vertical memory cells feature an architecture in which the storage capacitor and access device are stacked vertically in a common trench. Vertical memory cells afford increased packing densities and other advantages in comparison to planar memory cells, in which size reduction was realized in the past primarily by reduction of the linear dimensions (i.e., the minimum lithographic feature size, F). For example, the packing density of vertical memory cells in a DRAM device is increased because the length of the vertical access device channel is decoupled from the minimum lithographic feature size. Consequently, vertical memory cells lack the scaling problems with, for example, reducing the gate-oxide thickness and increasing the channel doping concentration encountered when scaling planar access devices to smaller sizes. The vertical memory cell architecture also allows longer channel lengths without a proportional decrease in memory density, as is true in planar memory cells. Channel length may also be properly scaled in vertical memory cells relative to gate oxide thickness and relative to junction depth to reduce channel doping, minimize junction leakage, and increase data retention times. Constructing DRAM devices using semiconductor-on-insulator (SOI) technology offers many advantages over counterpart devices built in bulk semiconductor substrates including, but not limited to, higher performance, absence of latch-up, higher packing density, and low voltage applications. In SOI technology, a thin semiconductor layer, often referred to as an SOI layer, is electrically isolated from a thicker semiconductor substrate by an insulating or dielectric material, e.g., a buried oxide or BOX layer. The access devices for the memory cells are built in a portion of the SOI layer termed the SOI body. Floating body effects occur in vertical memory cells built using SOI technology. SOI technology eliminates junction capacitance problems observed in comparable bulk devices by electrically isolating the SOI body of transistor-type access devices from the underlying semiconductor material of the substrate. However, the SOI body may float at a potential that varies according to various conditions in which the transistor-type access device is operated. Floating body effects are known to significantly degrade cell data retention time, which is most evident in long data retention time memory cells. Floating body effects originate from the accumulation of charge carriers in the channel region of the access device defined in the SOI body. A resultant leakage current is established via a parasitic bipolar transistor structure arising from the accumulated charge carriers. If uncompensated, the leakage current gradually discharges the storage capacitor. Floating body effects also cause fluctuations in the threshold voltage for the memory cell arising from the charge build up, which is extremely detrimental to conventional operation of transistor-type access devices. What is needed, therefore, is a semiconductor structure for an SOI DRAM cell array with improved cell data retention times and methods of fabricating such semiconductor structures that overcome the disadvantages of conventional semiconductor structures and conventional methods of manufacturing such semiconductor structures. SUMMARY OF THE INVENTION The present invention is generally directed to a semiconductor-on-insulator (SOI) structure that incorporates a body contact extending through the buried dielectric layer and, thereby, coupling an SOI body with an underlying semiconductor substrate and methods of forming such body contacts, desirably, with an ion implantation process. The structure improves the cell data retention time for a vertical memory cell in an SOI dynamic random access memory (DRAM) device by reducing floating body effects that, if uncompensated, may affect the memory cell access device and result in charge loss from the associated storage capacitor in the vertical memory cell. Specifically, charge carriers that would otherwise accumulate in the channel region of the access device are drained or discharged through a high-resistance leakage path defined by the body contact that extends to the underlying semiconductor substrate. In accordance with one aspect of the present invention, a semiconductor structure comprises a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, a buried dielectric layer separating the semiconductor substrate from the semiconductor body, and a plurality of memory cells built in an array on the semiconductor wafer. Each of the memory cells includes a storage capacitor and an access device. The access device has a vertical channel defined in one of the semiconductor bodies and a gate configured to switch current flow through the vertical channel to the storage capacitor. The structure further comprises a body contact in the buried dielectric layer. The body contact electrically couples one of the semiconductor bodies with the semiconductor substrate. In accordance with another aspect of the invention, a method for forming a semiconductor structure in a semiconductor wafer includes forming a plurality of trenches in a semiconductor wafer including a semiconductor substrate, a semiconductor layer with a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, and then building a memory cell in each of the trenches. The method further includes forming a body contact that extends substantially through the buried dielectric layer and electrically couples one of the semiconductor bodies with the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the principles of the invention. FIG. 1 is a top plan view of an array of vertical memory cells built on a portion of a semiconductor-on-insulator substrate in accordance with an embodiment of a processing method of the invention and in which the bit lines are omitted for purposes of clarity in describing the invention. FIG. 2 is a diagrammatic cross-sectional view of the substrate portion of FIG. 1 taken generally along lines 2-2. FIGS. 3-7 are diagrammatic cross-sectional views similar to FIG. 2 of the substrate portion at various subsequent fabrication stages in accordance with the embodiment of the processing method of the invention. FIG. 8 is a schematic view of an implant profile simulation showing a predicted depth profile for implanted silicon ions having a concentration profile predominately located in a buried dielectric layer of the semiconductor-on-insulator substrate of FIG. 7. FIGS. 9 and 10 are diagrammatic cross-sectional views similar to FIG. 7 of the substrate portion at various subsequent fabrication stages of the embodiment of the processing method of the invention. DETAILED DESCRIPTION The present invention provides a semiconductor structure including an array of vertical memory cells built using semiconductor-on-insulator (SOI) technology, as well as methods of making such semiconductor structures. Specifically, the access device for at least one vertical memory cell and, typically, every vertical memory cell in the memory cell array has an associated relatively high-resistance body contact established through the buried insulating or dielectric layer separating the floating SOI body of an SOI wafer, in which the access device is built, from the underlying semiconductor substrate. The present invention may be particularly applicable and beneficial for merged isolation and node trench (MINT) memory cells, although the invention is not so limited. The requisite high resistance for the body contact may be achieved by creating a localized silicon rich oxide (SRO) region of relatively high resistance in the buried dielectric layer. The present invention will now be described in greater detail by referring to the drawings that accompany the present application. With reference to FIGS. 1 and 2, a portion of a semiconductor wafer 10 is shown that includes multiple substantially identical vertical memory cells, generally indicated by reference numeral 12, that are arranged in electrically-isolated pairs of a considerably larger DRAM device built on semiconductor wafer 10. The larger DRAM device may constitute, but is not limited to, a plurality of substantially identical memory cells 12 each having a known eight square feature or 8F2 DRAM cell, as depicted in FIG. 1, and a plurality of substantially identical 8F2 DRAM cells arranged in a larger array across the semiconductor wafer 10. A bit of data can be stored as a data charge in each of the 8F2 DRAM cell arrays. Before building the vertical memory cells 12, SOI semiconductor wafer 10 comprises a semiconductor substrate 14, which is typically a single crystal or monocrystalline bulk silicon substrate and may be doped with a p-type dopant, a buried insulating or dielectric layer, which may be a buried oxide (BOX) layer 18, and an SOI body 16 of a larger semiconductor layer separated from the semiconductor substrate 14 by the intervening buried dielectric layer 18. The SOI body 16, which is considerably thinner than the semiconductor substrate 14 and is also typically single crystal or monocrystalline silicon, is electrically isolated from the semiconductor substrate 14 by the BOX layer 18. The semiconductor wafer 10 may be fabricated by any suitable conventional technique, such as a wafer bonding technique or a separation by implantation of oxygen (SIMOX) technique, familiar to persons of ordinary skill in the art. The stoichiometry of the BOX layer 18 may be expressed by the chemical or molecular formula SiOx, where the variable x represents the nominal proportion of oxygen atoms to silicon atoms in the constituent compound and may have any suitable value. For example, if x is equal to 2, the BOX layer 18 is stoichiometric with a stoichiometric ratio of two oxygen atoms per silicon atom and a molecular formula expressed as SiO2. Device isolation regions 24 (FIG. 1) are defined between adjacent rows of vertical memory cells 12 in the cell array, such that the memory cells 12 are paired together. One specific pair of electrically-isolated memory cells 12 is shown in FIG. 2. These device isolation regions 24 may be formed by, for example, a shallow trench isolation (STI) technique that includes a conventional lithography and dry etching process to create trenches followed by filling the trenches with a dielectric material, such as an oxide anisotropically deposited by a high density plasma (HDP) chemical vapor deposition (CVD) process, and then planarization with a conventional chemical mechanical planarization (CMP) process. The device isolation regions 24 partition the SOI body 16 into isolated active area regions or islands 15 on the BOX layer 18 and, thereby, assist in preventing carrier migration between adjacent memory cells 12. Each of the islands 15 may be considered to used in the construction of a pair of memory cells 12. Each of the vertical memory cells 12 is formed in a corresponding one of a plurality of trenches 19. Each of the trenches 19 extends into the semiconductor wafer 10 at locations dispersed across the surface of wafer 10. Each trench 19, which is formed by a conventional lithography and etching process familiar to a person having ordinary skill in the art, extends from a top planar surface 25 of the semiconductor wafer 10 through the SOI body 16 and the BOX layer 18 and continues for a depth into the semiconductor substrate 14 underlying the BOX layer 18. Each memory cell 12 includes a storage capacitor 20, typically having the form of a deep trench (DT) capacitor, and an access device 22, typically having the form of a vertical metal oxide semiconductor field-effect transistor, that are disposed within the trench 19 with a vertically stacked arrangement. The access device 22 is electrically coupled with the storage capacitor 20 for allowing the transfer of data charges to and from the storage capacitor 20 during reading and writing operations of the DRAM device. Because the memory cells 12 are substantially identical, the constituent features of one pair of memory cells 12 will be described with the understanding that this description applies to all equivalent pairs of memory cells 12 in the memory cell array and DRAM device. The storage capacitor 20 of each vertical memory cell 12 is located in a bottom or lower portion of the trench 19. The storage capacitor 20 includes a capacitor node or plate 26 constituted by a conductor, such as n+-doped polycrystalline silicon (i.e., polysilicon). The capacitor plate 26, which includes a portion that projects vertically into the BOX layer 18, is electrically isolated from the SOI body 16 by the BOX layer 18. A buried capacitor plate 28 is present in the material of the semiconductor substrate 14 bordering a lower portion of the trench 19. Buried plate doping may be formed by conventional processes such as out-diffusing an n-type dopant like arsenic from a layer of dopant-doped silicon glass on the sidewall of trench 19, gas phase doping, plasma doping, plasma immersion ion implantation, or any combination of these processes that are well known to a person having ordinary skill in the prior art. A thin node dielectric 30, which lines the lower portion of trench 19, separates and electrically isolates the buried capacitor plate 28 from capacitor plate 26. The node dielectric 30 may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, combinations of these dielectric materials, or another high-k material. With continued reference to FIGS. 1 and 2, the access device 22 of each vertical memory cell 12 is situated in a top or upper portion of the trench 19 and, generally, is stacked vertically above the storage capacitor 20. A trench-top insulator 32, which typically has the form of a trench-top oxide, overlies the capacitor plate 26 vertically and electrically isolates a vertical gate 34 of the access device 22 from the capacitor plate 26. Oxide for the trench-top insulator 32 may be formed in trench 19 above capacitor plate 26 by a suitable conventional process, such as a HDP-CVD process. The vertical gate 34 is constituted by an electrically conductive material, such as polysilicon deposited in the upper portion of trench 19 using low-pressure CVD (LPCVD). A buried deep strap connection 36 is provided in the BOX layer 18 vertically between the vertical gate 34 and the capacitor plate 26. An outdiffusion region 38, which originates from the n-type dopant (e.g., arsenic, phosphorous, or antimony) of buried deep strap connection 36 and may be produced during annealing of wafer 10, extends into the SOI body 16. The outdiffusion region 38 defines a lower source/drain region 35 of the access device 22, depending upon the operation of access device 22. Capacitor plate 26 of the storage capacitor 20 is tied to the lower source/drain region 35 of the access device 22 and buried capacitor plate 28 is tied to a reference potential or voltage. A thin gate oxide 40 is disposed on the vertical sidewall of trench 19 between the confronting sidewall of the vertical gate 34 and the SOI body 16. A doped region 42, which may be formed by implantation or diffusion of an n-type dopant such as arsenic or phosphorous into the SOI body 16, is provided in an upper region of the SOI body 16 and is coextensive with surface 25. The doped region 42 defines an upper source/drain region 43 of the access device 22, depending upon the operation of access device 22. A vertical channel 45 is defined in the SOI body 16 near the vertical gate 34 and generally between the source/drain regions 35, 43 of the access device 22. Current flowing through channel 45 between the source/drain regions 35, 43 is controlled or switched by potential or voltage applied to the vertical gate 34. When the access device 22 is switched “on” by application of a suitable voltage to the vertical gate 34, channel 45 becomes electrically conductive to allow current flow between the source/drain regions 35, 43. The access device 22 is considered by a person having ordinary skill in the art to constitute a vertical device structure because of the three-dimensional vertical arrangement of the gate 34, the channel region 45, and the source/drain regions 35, 43. An array top insulator 44, which overlies the doped region 42, operates to electrically isolate the source/drain region 43 from word lines 46, 48, 50, 51. The array top insulator 44 may be formed, for example, by depositing oxide using a conventional HDP CVD oxide process and optionally planarizing with a conventional planarization process, such as CMP. Word line 46 is electrically coupled with the storage capacitor 20 of one vertical memory cell 12 visible in FIG. 2 by the underlying access device 22. A potential applied from word line 46 to vertical gate 34 controls the data charge on the storage capacitor 20 by selectively transferring current between the source/drain regions 35, 43 through the channel 45 in the SOI body 16. Similarly, word line 48 is electrically coupled with the storage capacitor 20 of the other memory cell 12 visible in FIG. 2 by the underlying access device 22. A potential applied from word line 48 to the vertical gate 34 of the access device 22 of this memory cell 12 likewise controls the data charge on the corresponding storage capacitor 20 by selectively transferring current between the source/drain regions 35, 43 through channel 45 in the SOI body 16. Source/drain region 43 of each access device 22 is further connected to a corresponding bit line (not shown). To provide the electrical coupling, the vertical gate 34 of each access device 22 for the exemplary pair of vertical memory cells 12 visible in FIG. 2 is contacted by one of the word lines 46, 48. As a consequence, these word lines 46, 48 are referred to as active word lines. The other two word lines 50, 51, of which only word line 50 is visible in FIG. 2 and which do not contact either of the memory cells 12 visible in FIG. 2, are referred to as passing word lines. Word lines 50, 51, which are passing in FIG. 2, are connected with the access device 22 in other memory cells 12 in the memory cell array (FIG. 1) and in the DRAM device. Similarly, word lines 46, 48, which are active in FIG. 2, are not connected with the access device 22 of certain other memory cells 12 in the memory cell array (FIG. 1) and in the DRAM device. Consequently, as appreciated by a person having ordinary skill in the art, ascribing the terms active and passing to the word lines 46, 48, 50, 51 depends upon which specific pair of word lines 46, 48, 50, 51 is coupled with each electrically-isolated pair of memory cells 12 in the memory cell array and DRAM device. Each of the word lines 46, 48, 50, 51 consists of one or more conducting layers constituted by a conductor, such as polysilicon, tungsten nitride (WN), tungsten (W), tungsten silicide (WSi), or combinations of these materials. Each of the word lines 46, 48, 50, 51 includes an electrically-insulating cap 52 of, for example, nitride stationed atop the conducting layer(s), and electrically-insulating sidewall spacers 54 of, for example, nitride flanking the conducting layer(s). Gaps between adjacent pairs of word lines 46, 48, 50, 51 are filled by a layer 56 of a suitable gap fill material, such as oxide or borophosphosilicate glass (BPSG). The material of the gap fill layer 56 is planarized by a conventional planarization process, such as CMP, to establish an upper horizontal surface 58 by relying on caps 52 as a polish stop. With reference to FIG. 3 in which like reference numerals refer to like features in FIG. 2 and at a subsequent fabrication stage, a relatively thin etch stop layer 60 is deposited on the upper horizontal surface 58. The etch stop layer 60 may be oxide (SiO2) deposited by a conventional thermal CVD process. A relatively thick pad nitride layer 62 is formed on the etch stop layer 60. The pad nitride layer 62 may be composed of silicon nitride (Si3N4) formed utilizing a conventional deposition process, such as CVD or plasma-assisted CVD. With reference to FIG. 4 in which like reference numerals refer to like features in FIG. 3 and at a subsequent fabrication stage, a body contact resist layer 64 is applied to an exposed planar surface 66 of the pad nitride layer 62 and patterned with openings 67 by any conventional lithography technique that exposes the resist layer 64 to a pattern of radiation defined by a body mask (not shown) and develops the transferred pattern in the exposed resist 64. Each of the openings 67 coincides with the future location of one of a plurality of body contact openings 68 (FIGS. 1, 5). Suitable lithography techniques for use in forming the openings 67 in the resist layer 64 include, but are not limited to, photolithography with or without phase shift, x-ray lithography, electron beam lithography, or a combination of these techniques. With reference to FIG. 5 in which like reference numerals refer to like features in FIG. 4 and at a subsequent fabrication stage, a conventional anisotropic dry etching process selective to the material constituting the etch stop layer 60, such as reactive-ion etching (RIE) or plasma etching, is used to transfer the pattern of openings 67 from the resist layer 64 into the pad nitride layer 62 to the depth of the etch stop layer 60 and, thereby, initiate formation of the body contact openings 68. The chemistry of this etching process, which may be conducted in a single etching step or multiple steps, removes portions of the pad nitride layer 62 visible through the openings 67 in resist layer 64 and stops vertically on the etch stop layer 60. Each body contact opening 68 is further extended to the depth of the passing word line 50 by another conventional anisotropic dry etching process, such as RIE or plasma etching, that removes the constituent materials of the etch stop layer 60 and the insulating cap 52 selective to the electrically conductive material constituting the passing word line 50. The chemistry of this etching process, which may also be conducted in a single etching step or multiple steps, successively removes portions of the etch stop layer 60 and the insulating cap 52 on passing word line 50 visible through the body contact openings 68 and stops vertically on the electrically conductive material constituting the passing word line 50. This etching process also recesses the portion of the gap fill layer 56 exposed and circumscribed by the boundary of each body contact opening 68 and that overlies the corresponding device isolation region 24. With reference to FIG. 6 in which like reference numerals refer to like features in FIG. 5 and at a subsequent fabrication stage, the portion of the conductor constituting the passing word line 50 exposed through each body contact opening 68 is removed by yet another conventional anisotropic dry etching process, such as RIE or plasma etching, selective to the material constituting the array top insulator 44. The chemistry of the etching process, which is conducted in one or more individual etching steps, removes a portion of each word line 50 visible through the corresponding one of the body contact openings 68 and stops vertically on the material constituting the array top insulator 44. With reference to FIG. 7 in which like reference numerals refer to like features in FIG. 6 and at a subsequent fabrication stage, an ion implantation process is used to introduce silicon ions, as indicated diagrammatically by vertical arrows 70, into the semiconductor structure. Specifically, the implanted silicon ions 70 impinge the array top insulator 44 with near-normal incidence through a window defined by the openings 67 in resist layer 64 and the body contact openings 68 registered vertically with openings 67 in a self-aligned ion implantation process. The implanted silicon ions 70 penetrate successively through the array top insulator 44, the SOI body 16, and the BOX layer 18, and predominately come to rest in a depth profile extending into the BOX layer 18 to define a localized silicon rich oxide (SRO) region 72 within the BOX layer 18. Typically, the implantation of silicon ions 70 is performed with the semiconductor wafer 10 held at room or ambient temperature, although the invention is not so limited. The SRO region 72 has a stoichiometry that differs from adjacent regions of the BOX layer 18 flanking SRO region 72, which are substantially unaffected by the ion implantation. The implanted silicon ions 70 locally modify the stoichiometry of the BOX layer 18 within the confines of the SRO region 72 such that the molecular formula of the resulting silicon-enriched compound of the SRO region 72 departs from the SiOx molecular formula of the laterally adjacent regions of the BOX layer 18. For example, if x is equal to 2 (i.e., SiO2), the BOX layer 18 is stoichiometric and includes a stoichiometry characterized by a stoichiometric ratio of two oxygen atoms per every silicon atom, and the SRO region 72 has a silicon-enriched stoichiometry with a stoichiometric ratio in which fewer than two atoms of oxygen are associated with each silicon atom. As a more specific example, if the BOX layer 18 is SiO2 and the average concentration of the implanted ions is six (6) atomic percent (at. %), the average stoichiometry of the SRO region 72 across the depth profile is 100 oxygen atoms per 56 silicon atoms. The pad nitride layer 62 and resist layer 64 vertically mask underlying regions of the vertical memory cells 12 from the implanted silicon ions 70. In particular, the implanted silicon ions 70 do not penetrate or traverse the vertical gate 34 of the access device 22 of each adjacent memory cell 12, thus avoiding damage to the access device 22. The sidewall spacers 54 and a portion of the gap fill layer 56 exposed by the body contact opening 68 roughly define a lateral mask that sets the lateral boundaries of the SRO region 72. As a result, the lateral boundaries of the SRO region 72 coincide approximately with the now-open area formerly occupied by the removed portion of the passing word line 50, if lateral range straggle of the implanted silicon ions 70 is disregarded. This lateral masking self-aligns the implanted silicon ions 70 with the BOX layer 18 to enter only the SRO region 72 between the pair of adjacent memory cells 12. Portions of the BOX layer 18 that isolate the access device 22 from the storage capacitor 20 are unaffected by the implantation of silicon ions 70. The kinetic energy of the implanted silicon ions 70 is adjusted to deliver the peak concentration in the resulting depth profile centered approximately within the thickness of the BOX layer 18 (i.e., near the mid-plane of the BOX layer 18). In order to provide the SRO region 72 with a suitable resistance, a suitable dose of implanted silicon ions 70 may range from about 1×1013 to about 1×1016 cm−2. The kinetic energy of the implanted silicon ions 70 may range from about 50 keV to about 1000 keV (i.e., 1 MeV). The selection of a kinetic energy is contingent upon, among other parameters, the thickness and composition of the various layers in the layered structure (i.e., the array top insulator 44, the SOI body 16, and the BOX layer 18) that the ion trajectories traverse. Typically, the kinetic energy is selected such that the end-of-range tail of the depth profile for the implanted silicon ions 70 does not extend into the semiconductor substrate 14. Due to the vertical extent of the depth profile, a leading tail in the depth profile of the implanted silicon ions 70 will stop within the array top insulator 44 and the SOI body 16. However, the silicon concentration in this leading tail is significantly less than the concentration within the BOX layer 18 forming the SRO region 72. As is apparent to a person ordinarily skilled in the art, a series of several relatively low dose implantations may be substituted for a single implantation of a higher implantation dose and/or a series of implantations at different kinetic energies (i.e., different ranges) may be substituted for a single implantation at one kinetic energy. In particular, sequential implantations at different kinetic energies and different doses may be required to establish an implanted depth profile of silicon in the SRO region 72 that extends substantially across or through the thickness of the BOX layer 18. Typically, the SRO region 72 bridges the entire thickness of the BOX layer 18. The resulting stoichiometry of the BOX layer 18 in the SRO region 72 is enriched in silicon due to the introduction of excess silicon atoms by ion implantation. The enrichment may vary across the thickness of the BOX layer 18 due to the graded depth profile of silicon atoms. For example, the SRO region 72 may include about one (1) at. % to about six (6) at. % of silicon in excess of the initial SiOx stoichiometry of the BOX layer 18, which is understood to still exist in regions of the BOX layer 18 near the SRO region 72 that are substantially unaffected by the implantation. The silicon-rich stoichiometry of the SRO region 72 makes the BOX layer 18 between the SOI body 16 and the semiconductor substrate 14 locally leaky across the SRO region 72. An optional thermal treatment may be performed at a substrate temperature in the range from about 700° C. to about 1050° C. to anneal any implantation damage in the SOI body 16 and/or to improve the conductivity of the SRO region 72. The thermal treatment may be performed in either an inert or vacuum environment, where an inert environment may comprise, for example, an atmosphere of helium (He), argon (Ar), or nitrogen (N2). The invention contemplates that, in the event that the dielectric layer represented by BOX layer 18 comprises a dielectric material other than SiOx, the implanted species creating the SRO region 72 may depart from the exemplary silicon ions 70, as described herein, and may be selected accordingly to provide the local non-stoichiometry that supplies the leaky body contact between the SOI body 16 and the semiconductor substrate 14. The implanted species may or may not be an elemental component of the constituent dielectric material of BOX layer 18. For example, the implanted species may be germanium (Ge) if the BOX layer 18 is silicon oxide. With reference to FIG. 8, computer modeling may be used to predict a set of implantation conditions characterizing a predicted depth profile 74 that is capable of forming the SRO regions 72 (FIG. 7). The predicted depth profile 74 is representative of the actual depth profile of the implanted silicon ions 70 (FIG. 7) and provides an indication as to an appropriate ion energy and dose given a specific layer construction for the semiconductor wafer 10 and memory cell 12. The set of implantation conditions may subsequently be used to perform the actual ion implantation process with silicon ions 70 to create the SRO regions 72. The predicted depth profile 74 may be simulated on a suitable computing platform by implementing any of various publicly available implantation simulation software programs that model the implantation process. For example, the predicted depth profile 74 may be determined using a Monte-Carlo simulation program, such as the widely-available TRIM software application that relies on a quantum mechanical treatment of ion-atom collisions, as described in the book, “The Stopping and Range of Ions in Solids”, by J. F. Ziegler, J. P. Biersack, and U. Littmark, Pergammon Press, New York, 1985, to calculate the depth profile of ions implanted into matter consisting of compound materials with multiple layers, each of different materials. The implantation dose is optimized by the TRIM software given the implanted ion type and target materials and dimensions. As a specific example, the predicted depth profile 74 may be determined for an exemplary layered construction for the memory cell array in which the array top insulator 44 is silicon oxide and has a thickness of 100 nm, the SOI body 16 is silicon and has a thickness of 300 nm, and the BOX layer 18 is oxide and has an arbitrary thickness. The implanted ion species is Si+ and the ion kinetic energy is 400 keV, which produces a calculated range of about 530 nm and a calculated range straggle of about 122 nm. The depth profile 74 falls predominantly within the vertical boundaries of the BOX layer 18 and has a peak concentration in the BOX layer 18 at a depth of about 130 nm beneath the interface between the SOI body 16 and the BOX layer 18. As a result and taking into consideration the range straggle, this selection of implantation conditions is suitable if the BOX layer 18 has a thickness of about 300 nm so that the SRO region 72 substantially spans the entire thickness of the BOX layer 18. With reference to FIG. 9 in which like reference numerals refer to like features in FIG. 7 and at a subsequent fabrication stage, the body contact resist layer 64 is stripped to expose an upper horizontal surface 66 of the pad nitride layer 62. A layer of an electrically conductive fill material, such as polysilicon or doped polysilicon, is deposited by a conventional process on surface 66. A portion of the conductive fill material fills each body contact opening 68 with an electrically conductive plug 76. With reference to FIG. 10 in which like reference numerals refer to like features in FIG. 9 and at a subsequent fabrication stage, the semiconductor structure of FIG. 9 is planarized by a conventional planarization process, such as CMP, that stops vertically on the upper horizontal surface 66 of the pad nitride layer 62. The planarization process removes excess conductive fill material from surface 66 to re-expose the pad nitride layer 62. The pad nitride layer 62 is stripped by an etch process that removes the material of the pad nitride layer 62 selective to the materials constituting etch stop layer 60. For example, a wet isotropic etch process using hot acid, such as phosphoric acid, may be employed to remove Si3N4 relative to oxide. The etch stop layer 60 is removed by a conventional planarization process, such as a CMP process, that stops vertically at the upper horizontal surface 58 by relying on the caps 52 as a polish stop. The upper surface of the conductive plug 76 is recessed by, for example, an anisotropic dry etch process selective to the constituent material of etch stop layer 60. In particular, the etch process recesses the conductive plug 76 to a depth below planar surface 58 and, therefore, below with the upper surfaces of the gap fill layer 56 and the caps 52. The conductive plug 76 re-establishes the continuity of the passing word line 50. After the SRO regions 72 and conductive plugs 76 are formed, normal processing is used to complete the DRAM integrated circuit as understood by a person having ordinary skill in the art. Normal processing may include, but is not limited to, deposition of an interlayer dielectric such as BPSG or another suitable insulator, formation of the borderless bit line contacts and bit lines, and formation of higher level metallizations and insulating layers. Each SRO region 72 electrically couples the SOI body 16 of the access device 22 with the semiconductor substrate 14 to define a leaky current path therebetween. In each instance, the body contact opening 68 is established by removing a portion of one of the word lines 46, 48, 50, 51 that is passing for each particular pair of memory cells 12 and between each pair of memory cells 12. Each body contact or SRO region 72 serves a pair of access devices 22 in a contiguous island 15 of monocrystalline semiconductor defined by the SOI body 16 on SOI wafer 10. It should be noted that one embodiment of the present invention is described herein with semiconductor structures being doped for a particular device type, i.e. n-type FET's (N-channel FET's). However, the invention is not so limited as a person having ordinary skill would understand how to replace N-channel FET's with p-type FET's (P-channel FET's) and n-type dopant with p-type dopant (e.g., boron or indium) where appropriate without departing from the spirit or scope of the invention. The present invention provides various advantages in comparison with the construction of conventional DRAM cell arrays. In particular, the present invention provides for ultra-scalable and high performance SOI vertical array DRAM device having a high-resistance body contact to potentially eliminate and, at the least, significantly reduce the floating body effect by providing a conduction or leakage path through the BOX layer 18 from the SOI body 16 to the semiconductor substrate 14. The present invention is compatible with the current DRAM and enhanced dynamic random access memory (eDRAM) processes. The present invention is easy to implement in a circuit design and cost-effective, which is beneficial for purposes of manufacturability. The present invention is based upon the realization that a high-resistance body contact, defined by the SRO region 72, is sufficient for body charge equilibration in the access device 22 of long data retention time DRAM device and enables the use of a leaky BOX layer 18 as a high-resistance conduction or leakage path. The leaky interface between the BOX layer 18 and SOI body 16 supplied by the SRO region 72 provides a relatively low interface carrier recombination velocity. The beneficial result is that the leakage current from storage capacitor 20, arising from diffusion of charge carriers to this interface, is significantly reduced. Although Applicants do not wish to be bound by theory, it is believed that the relatively low body currents required for steady-state charge equilibration and the relatively low body capacitance dictate the benefit of a relatively high resistance body contact. For example, a body contact resistance of less than 10 Megohms per cell (about 105 ohm-um for 90 nm ground rules) is believed sufficient to maintain the body at an equilibrated condition within 1 nanosecond (ns) of a disturbance. In particular, a body contact resistance of less than 1000 Gigohms per cell is believed to be sufficient for sinking reasonably anticipated generation currents if the cell is sitting in standby. References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of semiconductor wafer 10, before processing and regardless of the actual spatial orientation of semiconductor wafer 10. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “beneath” and “under”, are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing the present invention without departing from the spirit and scope of the present invention. The fabrication of the semiconductor structure herein has been described by a specific order of fabrication stages and steps. However, it is understood that the order may differ from that described. For example, the order of two or more fabrication steps may be switched relative to the order shown. Moreover, two or more fabrication steps may be conducted either concurrently or with partial concurrence. In addition, various fabrication steps may be omitted and other fabrication steps may be added. It is understood that all such variations are within the scope of the present invention. It is also understood that features of the present invention are not necessarily shown to scale in the drawings. While the present invention has been illustrated by a description of various embodiments and while these embodiments have been described in considerable detail, it is not the intention of the applicants to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. Thus, the invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative example shown and described. Accordingly, departures may be made from such details without departing from the spirit or scope of applicants' general inventive concept.	H	67H01	185H01L	21	86
11777276	US20080054946A1-20080306	SEMICONDUCTOR INTEGRATED CIRCUIT	ACCEPTED	20080220	20080306	[]	H01L2702	["H01L2702", "H03K190944"]	7569899	20070712	20090804	257	393000	79459.0	MANDALA	VICTOR	[{"inventor_name_last": "KANNO", "inventor_name_first": "Yusuke", "inventor_city": "Kodaira", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Yoshizumi", "inventor_name_first": "Kenichi", "inventor_city": "Fukuoka", "inventor_state": "", "inventor_country": "JP"}]	Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.	1. A semiconductor integrated circuit comprising: a plurality of first power switches for receiving a ground voltage; first ground lines connected to the first power switches; a plurality of second power switches that are connected to the first ground lines, and have gate insulating films being thinner than gate insulating films of the first power switches; second ground lines provided for the plurality of second power switches respectively; a first power lines for receiving a power voltage; a plurality of circuit blocks connected to the second ground lines and the first power lines respectively; first control circuits for controlling the first power switches individually; and second control circuits for controlling the second power switches individually. 2. The semiconductor integrated circuit according to claim 1, further comprising: external input/output circuits plurally arranged on a semiconductor substrate; wherein the first power switches are formed by the same transistors as transistors arranged in regions of the external input/output circuits, and the second power switches are formed by the same transistors as transistors arranged in regions of the circuit blocks. 3. The semiconductor integrated circuit according to claim 1: wherein the second ground lines are wired with being approximately uniformly conducted in the regions of the circuit blocks, and the second power switches are arranged dispersedly on the second ground lines. 4. The semiconductor integrated circuit according to claim 1, further comprising: a plurality of third power switches formed by p-channel MOS transistors in which the gate insulting films have the same thickness as the gate insulting films of the second power switches; wherein the plurality of first power switches and second power switches are formed by n-channel MOS transistors, each of the plurality of circuit blocks is connected to each of the first power lines via a corresponding switch among the plurality of third power switches, and the plurality of third power switches are controlled by the second control circuits. 5. The semiconductor integrated circuit according to claim 1: wherein the second power switches has the gate insulting films being thicker than gate insulting films of the transistors arranged in the regions of the circuit blocks. 6. The semiconductor integrated circuit according to claim 5: wherein the second control circuits have level conversion circuits for conversing voltage levels applied to gates of the second power switches. 7. A semiconductor integrated circuit comprising: a plurality of first power switches that receive a ground voltage, and are formed by n-channel MOS transistors; first ground lines connected to the first power switches; a plurality of second power switches that receive a power voltage, and are formed by p-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches; first power lines connected to the plurality of second power switches respectively; a plurality of circuit blocks connected to the first ground lines and the first power lines respectively; first control circuits for controlling the first power switches individually; and second control circuits for controlling the second power switches individually. 8. The semiconductor integrated circuit according to claim 7, further comprising: third control circuits that are connected to gates of the second power switches, and perform control of allowing the second power switches to function as regulators. 9. A semiconductor integrated circuit comprising: a plurality of first power switches that receive a power voltage, and are formed by p-channel MOS transistors; a plurality of second power switches that receive a ground voltage, and are formed by n-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches; first ground lines connected to the plurality of second power switches respectively; first power lines connected to the first power switches; a plurality of third power switches that are connected to the first power lines, and formed by p-channel MOS transistors in which the gate insulting films have the same thickness as the gate insulting films of the second power switches; second power lines connected to the plurality of third power switches respectively; a plurality of circuit blocks connected to the first ground lines and the second power lines respectively; first control circuits for controlling the first power switches individually; and second control circuits for controlling the second power switches and the third power switches individually. 10. A semiconductor integrated circuit comprising: a plurality of first power switches for receiving a ground voltage; first ground lines connected to the first power switches; a plurality of second power switches connected to the first ground lines; second ground lines connected to the plurality of second power switches respectively; a first power lines for receiving a power voltage; a plurality of circuit blocks connected to the second ground lines and the first power lines respectively; first control circuits for controlling the first power switches individually; and second control circuits for controlling the second power switches individually; wherein the first power switches and the second power switches are formed by transistors in which the gate insulating films have the same thickness as thickness of gate insulating films of transistors arranged in regions of the circuit blocks, and the first control circuits apply a voltage lower than the ground voltage to gates of the first power switches. 11. The semiconductor integrated circuit according to claim 1: wherein the number of gates is 100 or more.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly relates to a technique useful for use in system LSI for mobile device, microprocessor and the like. 2. Description of Related Art The number of circuit blocks integrated in one LSI is remarkably increased due to progress in fine processing technology of semiconductors, and therefore usually unimaginable, complicated information processing can be achieved in one chip. Such LSI is called SoC (System on a Chip), and used for a system for mobile device and the like. However, a leakage current in a single transistor tends to increase due to progress in fine processing technology of semiconductors. As a result, the total leakage current in SoC is becoming extremely increased. To such SoC in which a large number of circuit blocks are integrated in one chip, demand on further high-speed operation of the circuit blocks is becoming increased with improvement in functions which is required for mobile devices and the like. For example, even if a transistor that can perform high-speed operation such as a transistor having a low threshold voltage or a transistor having a small thickness of a gate insulating film is used to achieve such high-speed operation, increase in leakage current is inevitable. Therefore, it is an important issue for SoC that increase in leakage current is prevented, in addition, high-speed operation is achieved. In SoC used for a system for mobile device or the like, the integrated circuit blocks can be exclusively used, and currently, only a necessary circuit is typically operated correspondingly to a scene to be used (hereinafter, simply called mode) or the like. That is, in SoC, an operation period can be definitely distinguished from a non-operation period in the integrated circuit blocks. When such technology is used, an idea is given, that is, circuits are configured by high-speed devices that can be operated at high speed, and power shutdown is closely performed during non-operation period so that the circuits are operated at extremely high speed in the operation period, and the leakage current is reduced in the non-operation period. JP-A-2004-235470 discloses a control method of power shutdown that can extremely reduce the leakage current by performing control using a switch having a large thickness of a gate insulating layer of transistors. However, since such a switch having the large thickness of the gate insulating layer takes large area, when a large number of power shutdown regions are provided within a chip, a real overhead costs are extremely increased, and therefore the switch is becoming hard to be mounted. On the other hand, when power is shut down using a switch having a small thickness of the gate insulating layer, while increase in area of the power switch can be reduced, an effect of reducing the leakage current cannot be sufficiently obtained compared with a case that power is shut down using the transistor having the large thickness of the gate insulating layer. JP-A-6-203558 discloses a technique that power shutdown of LSI is hierarchically carried out, thereby a period is reduced, in which a voltage level of a circuit being subjected to power shutdown is unstable, so that time for subsequently returning the circuit to an original state by voltage application is made faster. In a non-patent document 1, Y. Kanno, et al., “Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor,” ISSCC Dig. Tech. Papers, PP. 540-541, 671, February, 2006; SoC is disclosed, which has a plurality of power domains provided within a chip, power switches (PSW) for the power domains, and SRAM macros arranged in the power domains. Here, the power domain refers to a region where power shutdown can be performed using a power switch, which corresponds to the above power shutdown region. The power switch includes n-channel MOS transistors, each transistor having a large thickness of a gate oxide film and a high threshold voltage, for which transistors used in an external input/output circuit (I/O) are used. In the SRAM macros, special power switches are provided for reducing the leakage current.	<SOH> SUMMARY OF THE INVENTION <EOH>In consideration of layout or area of the power switches, and furthermore thickness of the gate insulating film, the inventor made investigation on a unit that enables high-speed operation of circuit blocks, and performs close power shutdown control while reducing the leakage current. In JP-A-6-203558, while power shutdown of LSI is hierarchically carried out, no description is made on thickness of the gate insulating film of the transistor. Regarding the layout of the power switches, vertical stacking or series connection of the power switches has not been typically used. This is because on-resistances of transistors configuring the power switches are connected in series, causing reduction in on-currents, which may concernedly affect degradation in performance (reduction in speed). Therefore, for example, vertically-stacked power switches are provided in a circuit block consuming a large current only in the case that speed reduction is allowed. However, the inventor made detailed investigation on an effect of the power switches on a circuit block that operates at high speed, as a result, found that even if power shutdown was performed with the power switches being vertically stacked, only slight reduction in speed was given by considering a circuit scale of the circuit block or area of the power switches (hereinafter, called SW area) compared with a case that the power switches were not vertically stacked. Here, the circuit scale corresponds to the number of gates in a circuit block. Moreover, area of a circuit block corresponding to the number of gates is called logic part area. In this specification, a ratio (%) of the SW area to the total area of the logic part area and the SW area is called area overhead (hereinafter, called area OH). While the non-patent document 1 discloses a configuration of stacking the power switches that use gate oxide films having different thickness from one another, it does not consider area OH based on area of a memory cell array in the SRAM macro, and area of a special power switch corresponding to the memory cell array to reduce the leakage current. An object of an embodiment of the invention is to provide a semiconductor integrated circuit that enables high-speed operation of a circuit block, and can perform close power shutdown control while reducing the leakage current. The above and other objects and novel features of an embodiment of the invention will be clarified from description of the specification and accompanying drawings. Summaries of typical inventions disclosed in the application are briefly described as follows. (1) A semiconductor integrated circuit (LSI: FIG. 2 ) according to an embodiment of the invention includes a plurality of first power switches (SW 1 to SW 4 ), first ground lines (VSSM 1 to VSSM 4 ), a plurality of second power switches (SWN 11 to SWN 42 ), second ground lines (SVSSM 11 to SVSSM 42 ), first power lines (VDDM 1 to VDDM 4 ), a plurality of circuit blocks (IP: FIG. 1 ), first control circuits (PSWC 1 to PSWC 4 ), and second control circuits (SCB 1 to SCB 4 ). The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines, and have gate insulating films being thinner than gate insulating films of the first power switches. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage. The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. From the above, the first power switches are connected with the plurality of second power switches via the first ground lines, and the first power switches and the plurality of second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively. Since the first power switches have the gate insulating films being thicker than the gate insulating films of the second power switches, each of them has a high threshold voltage, and therefore can reduce a leakage current. Since the first control circuits individually control the first power switches respectively, for example, in a mode that all circuit blocks are not used, which are supplied with currents via a plurality of second power switches connected to a particular first power switch, when the particular first power switch is allowed to be off, the circuit blocks can be collectively subjected to power shutdown. In particular, when a semiconductor integrated circuit as a whole is in a standby state, the first control circuits allow all the plurality of first power switches to be off, so that the leakage current can be extremely reduced. Since the second power switches have the gate insulating films being thinner than the gate insulating films of the first power switches, each of them has a low threshold voltage, and therefore can perform high-speed operation. Since the second control circuits individually control the second power switches respectively, for example, in a mode that a circuit block is not used, which is supplied with a current via a particular second power switch, when the particular second power switch is allowed to be off, power shutdown of the particular circuit block can be performed at high speed. In a word, the first power switches and the second power switches, in which the gate insulating films are different in thickness from each other, are in the hierarchical structure, and they are individually controlled by the first control circuits and the second control circuits, thereby high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. As a specific mode of the embodiment of the invention, the semiconductor integrated circuit further has external input/output circuits (I/O) plurally arranged on a semiconductor substrate (SUB: FIG. 6 ). The first power switches are formed by the same transistors as transistors arranged in regions of the external input/output circuits. The second power switches are formed by the same transistors as transistors arranged in regions of the circuit blocks. From the above, since each of the first power switches has a thick gate insulating film, and a high threshold voltage, it can reduce the leakage current. Since each of the second power switches has a thin gate insulating film, and a low threshold voltage, it can perform high-speed operation. As a specific mode of the embodiment of the invention, the second ground lines are wired with being approximately uniformly conducted in the regions of the circuit blocks. The second power switches are dispersedly arranged on the second ground lines. From the above, the second power switches are dispersedly arranged in the regions of the circuit blocks, and the transistors having thin gate insulating films, which configure the respective, second power switches, are connected in parallel with the second ground lines. Therefore, in the case that predetermined processing is performed in a circuit block, when an activation ratio of a plurality of logic circuits included in the circuit block is assumed to be, for example, about 10%, all transistors connected in parallel with the second ground lines contribute to supply currents to the about 10% of logic circuits. Thus, an increase rate of SW area of the second power switches is reduced compared with an increase rate of a circuit scale of the circuit block, that is, an increase rate of logic part area corresponding to the number of gates of transistors configuring the logic circuits. In a word, considering difference between the increase rate of SW area and the increase rate of logic part area, when the number of gates is somewhat increased, area OH can be decreased to less than a predetermined value, for example, about 10%. As a result, integration of the semiconductor integrated circuit can be increased. (2) A semiconductor integrated circuit (LSI: FIG. 8 ) according to another embodiment of the invention includes a plurality of first power switches (SW 1 to SW 4 ), first ground lines (VSSM 1 to VSSM 4 ), a plurality of second power switches (SWP 11 to SWP 42 ), first power lines (SVDDM 11 to SVDDM 42 ), a plurality of circuit blocks (IP), first control circuits (PSWC 1 to PSWC 4 ), and second control circuits (SCB 1 to SCB 4 ). The first power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors. The first ground lines are connected to the first power switches. The second power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The first power lines are connected to the plurality of second power switches respectively. The circuit blocks are connected to the first ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. From the above, the first power switches, which are formed by the n-channel MOS transistors having thick gate insulating films, and can reduce the leakage current, and the second power switches, which are formed by the p-channel MOS transistors having thin gate insulating films, and can perform high-speed operation, are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and furthermore, the power switches are individually controlled using the first control circuits and the second control circuits. Consequently, as in the semiconductor integrated circuit of the above (1), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. As a specific mode of the embodiment of the invention, the semiconductor integrated circuit further has third control circuits (RC 1 to RC 4 ) that are connected to gates of the second power switches, and perform control of allowing the second power switches to function as regulators. From the above, for example, while a voltage of a predetermined circuit block is lowered during standby to reduce the leakage current, an internal condition of the circuit block can be kept. Moreover, for example, a voltage is lowered during low-speed operation, so that power consumption can be reduced. (3) A semiconductor integrated circuit (LSI: FIG. 9 ) according to still another embodiment of the invention includes a plurality of first power switches (SW 1 to SW 4 ), first ground lines (VSSM 1 to VSSM 4 ), a plurality of second power switches (SWN 11 to SWN 42 ), second ground lines (SVSSM 11 to SVSSM 42 ), a plurality of third power switches (SWP 11 to SWP 42 ), first power lines (SVDDM 11 to SVDDM 42 ), a plurality of circuit blocks (IP), first control circuits (PSWC 1 to PSWC 4 ), and second control circuits (SCB 1 to SCB 4 ). The first power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors. The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines, and are formed by n-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The second ground lines are connected to the plurality of second power switches respectively. The third power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors in which the gate insulating films have the same thickness as thickness of the gate insulating films of the second power switches. The first power lines are connected to the plurality of third power switches respectively. The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches and the third power switches individually. From the above, the second power switches formed by the n-channel MOS transistors having the thin gate insulating films are provided at a ground side, and the third power switches formed by the p-channel MOS transistors having the thin gate insulating films are provided at a power side, and furthermore, the first power switches formed by the n-channel MOS transistors having the thick gate insulating films and the second power switches are made in a hierarchical structure respectively. According to this, while an increase rate of SW area corresponding to the number of gates in a circuit block is somewhat increased, since threshold voltages of the second power switches and the third power switches are apparently increased due to a substrate effect, the leakage current can be further reduced. Moreover, the first to third power switches are individually controlled using the first control circuits and the second control circuits, thereby, as in the semiconductor integrated circuit of the above (1), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. (4) A semiconductor integrated circuit (LSI: FIG. 10 ) according to still another embodiment of the invention includes a plurality of first power switches (SW 21 to SW 24 ), a plurality of second power switches (SWN 11 to SWN 42 ), first ground lines (SVSSM 11 to SVSSM 42 ), first power lines (VDDM 1 to VDDM 4 ), a plurality of third power switches (SWP 11 to SWP 42 ), second power lines (SVDDM 11 to SVDDM 42 ), a plurality of circuit blocks (IP), first control circuits (PSWC 1 to PSWC 4 ), and second control circuits (SCB 1 to SCB 4 ). The first power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors. The second power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The first ground lines are connected to the plurality of second power switches respectively. The first power lines are connected to the first power switches. The third power switches are connected to the first power lines, and formed by p-channel MOS transistors in which the gate insulating films have the same thickness as thickness of the gate insulating films of the second power switches. The second power lines are connected to the plurality of third power switches. The circuit blocks are connected to the first ground lines and the second power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches and the third power switches individually. From the above, the second power switches formed by the n-channel MOS transistors having the thin gate insulating films are provided at a ground side, and the third power switches formed by the p-channel MOS transistors having the thin gate insulating films are provided at a power side, and furthermore, while the first power switches formed by the n-channel MOS transistors having the thick gate insulating films are provided at the power side, and the first power switches and the third power switches are made in a hierarchical structure respectively. Moreover, the first to third power switches are individually controlled using the first control circuits and the second control circuits. Consequently, as in the semiconductor integrated circuit of the above (3), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. (5) A semiconductor integrated circuit (LSI: FIG. 11 ) according to still another embodiment of the invention includes a plurality of first power switches (SW 1 to SW 4 ), first ground lines (VSSM 1 to VSSM 4 ), a plurality of second power switches (SWN 110 to SWN 420 ), second ground lines, first power lines, a plurality of circuit blocks (IP), first control circuits (PSWC 1 to PSWC 4 ), and second control circuits (SCB 1 to SCB 4 ) The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage (VDD). The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. The second power switches are formed by transistors in which the gate insulating films are thicker than gate insulating films of transistors arranged in regions of the circuit blocks, and thinner than gate insulating films of the first power switches. From the above, the first power switches and the second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and the power switches are individually controlled using the first control circuits and the second control circuits, therefore close power shutdown control can be performed correspondingly to each kind of mode. Moreover, since thickness of the gate insulating film of the second power switch is an intermediate thickness between thickness of the gate insulating film of the transistor included in the circuit block, and thickness of the gate insulating film of the transistor included in the first power switch, a threshold voltage of the second power switch can be made higher than the transistor included in the circuit block, consequently the leakage current can be further reduced compared with in the semiconductor integrated circuit of the (1). As a specific mode of the embodiment of the invention, the second control circuits have level conversion circuits (LS 1 to LS 4 ) for converting voltage levels to be applied to gates of the second power switches. From the above, since the transistor included in the second power switch is high in threshold voltage compared with the transistor included in the circuit block, when a signal level is converted by the level conversion circuit, even if area of the transistor included in the second control circuit is reduced, a sufficient current can be obtained. Thus, area of the second control circuits can be reduced. (6) A semiconductor integrated circuit (LSI: FIG. 13 ) according to still another embodiment of the invention includes a plurality of first power switches (SW 11 to SW 14 ), first ground lines (VSSM 11 to VSSM 42 ), a plurality of second power switches (SWN 11 to SWN 42 ), second ground lines (SVSSM 11 to SVSSM 42 ), first power lines, a plurality of circuit blocks (IP), first control circuits (PSWC 11 to PSWC 14 ), and second control circuits (SCB 1 to SCB 4 ). The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage (VDD). The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. The first power switches and the second power switches are formed by transistors in which the gate insulating films have the same thickness as thickness of gate insulating films of transistors arranged in regions of the circuit blocks. The first control circuits apply a voltage (VBN) lower than the ground voltage to gates of the first power switches. From the above, the first power switches and the second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and the power switches are individually controlled using the first control circuits and the second control circuits, therefore close power shutdown control can be performed correspondingly to each kind of mode. Here, while thickness of the gate insulating films of the first power switches is the same as thickness of the gate insulating films of the transistors included in the circuit blocks, that is, thin, since the first control circuits apply a negative gate voltage, the leakage current can be reduced. In addition, since the first power switch can perform the same high-speed operation as the second power switch, the semiconductor integrated circuit can perform further high-speed operation compared with the semiconductor integrated circuit of the (1). As a specific mode of the embodiment of the invention, the number of gates in the circuit block is 100 or more. From the above, according to a result of simulation of calculating area OH based on difference in increase rate between logic part area of the circuit block corresponding to the number of gates, and SW area of the second power switches, when the number of gates is 100 or more, the area OH can be sufficiently reduced. Thus, integration of the semiconductor integrated circuit can be increased.	CLAIM OF PRIORITY The present application claims priority from Japanese application JP 2006-236119 filed on Aug. 31, 2006, the content of which is hereby incorporated by reference into this application. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly relates to a technique useful for use in system LSI for mobile device, microprocessor and the like. 2. Description of Related Art The number of circuit blocks integrated in one LSI is remarkably increased due to progress in fine processing technology of semiconductors, and therefore usually unimaginable, complicated information processing can be achieved in one chip. Such LSI is called SoC (System on a Chip), and used for a system for mobile device and the like. However, a leakage current in a single transistor tends to increase due to progress in fine processing technology of semiconductors. As a result, the total leakage current in SoC is becoming extremely increased. To such SoC in which a large number of circuit blocks are integrated in one chip, demand on further high-speed operation of the circuit blocks is becoming increased with improvement in functions which is required for mobile devices and the like. For example, even if a transistor that can perform high-speed operation such as a transistor having a low threshold voltage or a transistor having a small thickness of a gate insulating film is used to achieve such high-speed operation, increase in leakage current is inevitable. Therefore, it is an important issue for SoC that increase in leakage current is prevented, in addition, high-speed operation is achieved. In SoC used for a system for mobile device or the like, the integrated circuit blocks can be exclusively used, and currently, only a necessary circuit is typically operated correspondingly to a scene to be used (hereinafter, simply called mode) or the like. That is, in SoC, an operation period can be definitely distinguished from a non-operation period in the integrated circuit blocks. When such technology is used, an idea is given, that is, circuits are configured by high-speed devices that can be operated at high speed, and power shutdown is closely performed during non-operation period so that the circuits are operated at extremely high speed in the operation period, and the leakage current is reduced in the non-operation period. JP-A-2004-235470 discloses a control method of power shutdown that can extremely reduce the leakage current by performing control using a switch having a large thickness of a gate insulating layer of transistors. However, since such a switch having the large thickness of the gate insulating layer takes large area, when a large number of power shutdown regions are provided within a chip, a real overhead costs are extremely increased, and therefore the switch is becoming hard to be mounted. On the other hand, when power is shut down using a switch having a small thickness of the gate insulating layer, while increase in area of the power switch can be reduced, an effect of reducing the leakage current cannot be sufficiently obtained compared with a case that power is shut down using the transistor having the large thickness of the gate insulating layer. JP-A-6-203558 discloses a technique that power shutdown of LSI is hierarchically carried out, thereby a period is reduced, in which a voltage level of a circuit being subjected to power shutdown is unstable, so that time for subsequently returning the circuit to an original state by voltage application is made faster. In a non-patent document 1, Y. Kanno, et al., “Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor,” ISSCC Dig. Tech. Papers, PP. 540-541, 671, February, 2006; SoC is disclosed, which has a plurality of power domains provided within a chip, power switches (PSW) for the power domains, and SRAM macros arranged in the power domains. Here, the power domain refers to a region where power shutdown can be performed using a power switch, which corresponds to the above power shutdown region. The power switch includes n-channel MOS transistors, each transistor having a large thickness of a gate oxide film and a high threshold voltage, for which transistors used in an external input/output circuit (I/O) are used. In the SRAM macros, special power switches are provided for reducing the leakage current. SUMMARY OF THE INVENTION In consideration of layout or area of the power switches, and furthermore thickness of the gate insulating film, the inventor made investigation on a unit that enables high-speed operation of circuit blocks, and performs close power shutdown control while reducing the leakage current. In JP-A-6-203558, while power shutdown of LSI is hierarchically carried out, no description is made on thickness of the gate insulating film of the transistor. Regarding the layout of the power switches, vertical stacking or series connection of the power switches has not been typically used. This is because on-resistances of transistors configuring the power switches are connected in series, causing reduction in on-currents, which may concernedly affect degradation in performance (reduction in speed). Therefore, for example, vertically-stacked power switches are provided in a circuit block consuming a large current only in the case that speed reduction is allowed. However, the inventor made detailed investigation on an effect of the power switches on a circuit block that operates at high speed, as a result, found that even if power shutdown was performed with the power switches being vertically stacked, only slight reduction in speed was given by considering a circuit scale of the circuit block or area of the power switches (hereinafter, called SW area) compared with a case that the power switches were not vertically stacked. Here, the circuit scale corresponds to the number of gates in a circuit block. Moreover, area of a circuit block corresponding to the number of gates is called logic part area. In this specification, a ratio (%) of the SW area to the total area of the logic part area and the SW area is called area overhead (hereinafter, called area OH). While the non-patent document 1 discloses a configuration of stacking the power switches that use gate oxide films having different thickness from one another, it does not consider area OH based on area of a memory cell array in the SRAM macro, and area of a special power switch corresponding to the memory cell array to reduce the leakage current. An object of an embodiment of the invention is to provide a semiconductor integrated circuit that enables high-speed operation of a circuit block, and can perform close power shutdown control while reducing the leakage current. The above and other objects and novel features of an embodiment of the invention will be clarified from description of the specification and accompanying drawings. Summaries of typical inventions disclosed in the application are briefly described as follows. (1) A semiconductor integrated circuit (LSI: FIG. 2) according to an embodiment of the invention includes a plurality of first power switches (SW1 to SW4), first ground lines (VSSM1 to VSSM4), a plurality of second power switches (SWN11 to SWN42), second ground lines (SVSSM11 to SVSSM42), first power lines (VDDM1 to VDDM4), a plurality of circuit blocks (IP: FIG. 1), first control circuits (PSWC1 to PSWC4), and second control circuits (SCB1 to SCB4). The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines, and have gate insulating films being thinner than gate insulating films of the first power switches. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage. The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. From the above, the first power switches are connected with the plurality of second power switches via the first ground lines, and the first power switches and the plurality of second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively. Since the first power switches have the gate insulating films being thicker than the gate insulating films of the second power switches, each of them has a high threshold voltage, and therefore can reduce a leakage current. Since the first control circuits individually control the first power switches respectively, for example, in a mode that all circuit blocks are not used, which are supplied with currents via a plurality of second power switches connected to a particular first power switch, when the particular first power switch is allowed to be off, the circuit blocks can be collectively subjected to power shutdown. In particular, when a semiconductor integrated circuit as a whole is in a standby state, the first control circuits allow all the plurality of first power switches to be off, so that the leakage current can be extremely reduced. Since the second power switches have the gate insulating films being thinner than the gate insulating films of the first power switches, each of them has a low threshold voltage, and therefore can perform high-speed operation. Since the second control circuits individually control the second power switches respectively, for example, in a mode that a circuit block is not used, which is supplied with a current via a particular second power switch, when the particular second power switch is allowed to be off, power shutdown of the particular circuit block can be performed at high speed. In a word, the first power switches and the second power switches, in which the gate insulating films are different in thickness from each other, are in the hierarchical structure, and they are individually controlled by the first control circuits and the second control circuits, thereby high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. As a specific mode of the embodiment of the invention, the semiconductor integrated circuit further has external input/output circuits (I/O) plurally arranged on a semiconductor substrate (SUB: FIG. 6). The first power switches are formed by the same transistors as transistors arranged in regions of the external input/output circuits. The second power switches are formed by the same transistors as transistors arranged in regions of the circuit blocks. From the above, since each of the first power switches has a thick gate insulating film, and a high threshold voltage, it can reduce the leakage current. Since each of the second power switches has a thin gate insulating film, and a low threshold voltage, it can perform high-speed operation. As a specific mode of the embodiment of the invention, the second ground lines are wired with being approximately uniformly conducted in the regions of the circuit blocks. The second power switches are dispersedly arranged on the second ground lines. From the above, the second power switches are dispersedly arranged in the regions of the circuit blocks, and the transistors having thin gate insulating films, which configure the respective, second power switches, are connected in parallel with the second ground lines. Therefore, in the case that predetermined processing is performed in a circuit block, when an activation ratio of a plurality of logic circuits included in the circuit block is assumed to be, for example, about 10%, all transistors connected in parallel with the second ground lines contribute to supply currents to the about 10% of logic circuits. Thus, an increase rate of SW area of the second power switches is reduced compared with an increase rate of a circuit scale of the circuit block, that is, an increase rate of logic part area corresponding to the number of gates of transistors configuring the logic circuits. In a word, considering difference between the increase rate of SW area and the increase rate of logic part area, when the number of gates is somewhat increased, area OH can be decreased to less than a predetermined value, for example, about 10%. As a result, integration of the semiconductor integrated circuit can be increased. (2) A semiconductor integrated circuit (LSI: FIG. 8) according to another embodiment of the invention includes a plurality of first power switches (SW1 to SW4), first ground lines (VSSM1 to VSSM4), a plurality of second power switches (SWP11 to SWP42), first power lines (SVDDM11 to SVDDM42), a plurality of circuit blocks (IP), first control circuits (PSWC1 to PSWC4), and second control circuits (SCB1 to SCB4). The first power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors. The first ground lines are connected to the first power switches. The second power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The first power lines are connected to the plurality of second power switches respectively. The circuit blocks are connected to the first ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. From the above, the first power switches, which are formed by the n-channel MOS transistors having thick gate insulating films, and can reduce the leakage current, and the second power switches, which are formed by the p-channel MOS transistors having thin gate insulating films, and can perform high-speed operation, are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and furthermore, the power switches are individually controlled using the first control circuits and the second control circuits. Consequently, as in the semiconductor integrated circuit of the above (1), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. As a specific mode of the embodiment of the invention, the semiconductor integrated circuit further has third control circuits (RC1 to RC4) that are connected to gates of the second power switches, and perform control of allowing the second power switches to function as regulators. From the above, for example, while a voltage of a predetermined circuit block is lowered during standby to reduce the leakage current, an internal condition of the circuit block can be kept. Moreover, for example, a voltage is lowered during low-speed operation, so that power consumption can be reduced. (3) A semiconductor integrated circuit (LSI: FIG. 9) according to still another embodiment of the invention includes a plurality of first power switches (SW1 to SW4), first ground lines (VSSM1 to VSSM4), a plurality of second power switches (SWN11 to SWN42), second ground lines (SVSSM11 to SVSSM42), a plurality of third power switches (SWP11 to SWP42), first power lines (SVDDM11 to SVDDM42), a plurality of circuit blocks (IP), first control circuits (PSWC1 to PSWC4), and second control circuits (SCB1 to SCB4). The first power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors. The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines, and are formed by n-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The second ground lines are connected to the plurality of second power switches respectively. The third power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors in which the gate insulating films have the same thickness as thickness of the gate insulating films of the second power switches. The first power lines are connected to the plurality of third power switches respectively. The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches and the third power switches individually. From the above, the second power switches formed by the n-channel MOS transistors having the thin gate insulating films are provided at a ground side, and the third power switches formed by the p-channel MOS transistors having the thin gate insulating films are provided at a power side, and furthermore, the first power switches formed by the n-channel MOS transistors having the thick gate insulating films and the second power switches are made in a hierarchical structure respectively. According to this, while an increase rate of SW area corresponding to the number of gates in a circuit block is somewhat increased, since threshold voltages of the second power switches and the third power switches are apparently increased due to a substrate effect, the leakage current can be further reduced. Moreover, the first to third power switches are individually controlled using the first control circuits and the second control circuits, thereby, as in the semiconductor integrated circuit of the above (1), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. (4) A semiconductor integrated circuit (LSI: FIG. 10) according to still another embodiment of the invention includes a plurality of first power switches (SW21 to SW24), a plurality of second power switches (SWN11 to SWN42), first ground lines (SVSSM11 to SVSSM42), first power lines (VDDM1 to VDDM4), a plurality of third power switches (SWP11 to SWP42), second power lines (SVDDM11 to SVDDM42), a plurality of circuit blocks (IP), first control circuits (PSWC1 to PSWC4), and second control circuits (SCB1 to SCB4). The first power switches receive a power voltage (VDD), and are formed by p-channel MOS transistors. The second power switches receive a ground voltage (VSS), and are formed by n-channel MOS transistors in which the gate insulating films are thinner than gate insulating films of the first power switches. The first ground lines are connected to the plurality of second power switches respectively. The first power lines are connected to the first power switches. The third power switches are connected to the first power lines, and formed by p-channel MOS transistors in which the gate insulating films have the same thickness as thickness of the gate insulating films of the second power switches. The second power lines are connected to the plurality of third power switches. The circuit blocks are connected to the first ground lines and the second power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches and the third power switches individually. From the above, the second power switches formed by the n-channel MOS transistors having the thin gate insulating films are provided at a ground side, and the third power switches formed by the p-channel MOS transistors having the thin gate insulating films are provided at a power side, and furthermore, while the first power switches formed by the n-channel MOS transistors having the thick gate insulating films are provided at the power side, and the first power switches and the third power switches are made in a hierarchical structure respectively. Moreover, the first to third power switches are individually controlled using the first control circuits and the second control circuits. Consequently, as in the semiconductor integrated circuit of the above (3), high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to each kind of mode while reducing the leakage current. (5) A semiconductor integrated circuit (LSI: FIG. 11) according to still another embodiment of the invention includes a plurality of first power switches (SW1 to SW4), first ground lines (VSSM1 to VSSM4), a plurality of second power switches (SWN110 to SWN420), second ground lines, first power lines, a plurality of circuit blocks (IP), first control circuits (PSWC1 to PSWC4), and second control circuits (SCB1 to SCB4) The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage (VDD). The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. The second power switches are formed by transistors in which the gate insulating films are thicker than gate insulating films of transistors arranged in regions of the circuit blocks, and thinner than gate insulating films of the first power switches. From the above, the first power switches and the second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and the power switches are individually controlled using the first control circuits and the second control circuits, therefore close power shutdown control can be performed correspondingly to each kind of mode. Moreover, since thickness of the gate insulating film of the second power switch is an intermediate thickness between thickness of the gate insulating film of the transistor included in the circuit block, and thickness of the gate insulating film of the transistor included in the first power switch, a threshold voltage of the second power switch can be made higher than the transistor included in the circuit block, consequently the leakage current can be further reduced compared with in the semiconductor integrated circuit of the (1). As a specific mode of the embodiment of the invention, the second control circuits have level conversion circuits (LS1 to LS4) for converting voltage levels to be applied to gates of the second power switches. From the above, since the transistor included in the second power switch is high in threshold voltage compared with the transistor included in the circuit block, when a signal level is converted by the level conversion circuit, even if area of the transistor included in the second control circuit is reduced, a sufficient current can be obtained. Thus, area of the second control circuits can be reduced. (6) A semiconductor integrated circuit (LSI: FIG. 13) according to still another embodiment of the invention includes a plurality of first power switches (SW11 to SW14), first ground lines (VSSM11 to VSSM42), a plurality of second power switches (SWN11 to SWN42), second ground lines (SVSSM11 to SVSSM42), first power lines, a plurality of circuit blocks (IP), first control circuits (PSWC11 to PSWC14), and second control circuits (SCB1 to SCB4). The first power switches receive a ground voltage (VSS). The first ground lines are connected to the first power switches. The second power switches are connected to the first ground lines. The second ground lines are connected to the plurality of second power switches respectively. The first power lines receive a power voltage (VDD). The circuit blocks are connected to the second ground lines and the first power lines respectively. The first control circuits control the first power switches individually. The second control circuits control the second power switches individually. The first power switches and the second power switches are formed by transistors in which the gate insulating films have the same thickness as thickness of gate insulating films of transistors arranged in regions of the circuit blocks. The first control circuits apply a voltage (VBN) lower than the ground voltage to gates of the first power switches. From the above, the first power switches and the second power switches are arranged in a vertically stacked manner so as to be in a hierarchical structure respectively, and the power switches are individually controlled using the first control circuits and the second control circuits, therefore close power shutdown control can be performed correspondingly to each kind of mode. Here, while thickness of the gate insulating films of the first power switches is the same as thickness of the gate insulating films of the transistors included in the circuit blocks, that is, thin, since the first control circuits apply a negative gate voltage, the leakage current can be reduced. In addition, since the first power switch can perform the same high-speed operation as the second power switch, the semiconductor integrated circuit can perform further high-speed operation compared with the semiconductor integrated circuit of the (1). As a specific mode of the embodiment of the invention, the number of gates in the circuit block is 100 or more. From the above, according to a result of simulation of calculating area OH based on difference in increase rate between logic part area of the circuit block corresponding to the number of gates, and SW area of the second power switches, when the number of gates is 100 or more, the area OH can be sufficiently reduced. Thus, integration of the semiconductor integrated circuit can be increased. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram illustrating a schematic configuration of LSI configured as SoC as an example of a semiconductor integrated circuit according to embodiment 1 of the invention; FIG. 2 is an explanatory diagram illustrating a circuit configuration of logic LSI as a part of the LSI illustrated in FIG. 1; FIG. 3A is a diagram showing a simulation result of logic part area corresponding to the number of gates; FIG. 3B is a diagram showing a simulation result of area OH based on SW area; FIG. 4 is a diagram showing delay time in a circuit block corresponding to an increase rate of a ground voltage VSS to a power voltage VDD; FIG. 5 is an explanatory diagram illustrating the amount of leakage current in each mode; FIG. 6 is an explanatory diagram illustrating a layout configuration of LSI configured as SoC; FIG. 7 is an explanatory diagram illustrating an example of integrating thick-film power switches and thin-film power switches in LSI; FIG. 8 is an explanatory diagram illustrating a circuit configuration of logic LSI according to embodiment 2 of the invention; FIG. 9 is an explanatory diagram illustrating a circuit configuration of logic LSI according to embodiment 3 of the invention; FIG. 10 is an explanatory diagram illustrating a circuit configuration of logic LSI according to embodiment 4 of the invention; FIG. 11 is an explanatory diagram illustrating a circuit configuration of logic LSI according to embodiment 5 of the invention; FIG. 12 is an explanatory diagram illustrating a schematic configuration of a power switch for achieving high-speed return from power shutdown; FIG. 13 is an explanatory diagram illustrating a circuit configuration of logic LSI in the case that respective power switches have the same gate insulating films; and FIG. 14 is an explanatory diagram showing an example of integrating power switches, different from that in FIG. 7, and an example of wiring power lines. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Embodiment 1 FIG. 1 illustrates a schematic configuration of LSI configured as SoC as an example of a semiconductor integrated circuit according to embodiment 1 of the invention. The LSI has first power domains PD1, PD2 which can be subjected to power shutdown using power switches SW1, SW2 for receiving a ground voltage VSS or the like, power switch controllers PSWC1, PSWC2 for controlling the power switches SW1, SW2, a global interrupt control circuit GINTC for controlling interrupt from the outside of the LSI, and a system controller SYSC for performing basic control of the LSI as a whole; which are integrated on a semiconductor substrate. The power switches SW1, SW2 are, while not particularly limited, formed by a transistor manufactured by a process common to a not-shown external input/output circuit I/O, that is, n-channel MOS transistors (hereinafter, sometimes described as thick-film power transistors) in which a gate tunnel leakage current is small because of a large thickness of a gate insulating film and a high threshold voltage. Hereinafter, the power switches SW1, SW2 are called thick-film power switches. Moreover, while two, first power domains are shown in the LSI, the number of the domains is not limited, and the domains may be integrated in the LSI by the number according to need. The insides of the first power domains PD1, PD2 are divided into a plurality of sub power domains, and second power domains SPD11 to SPD1n and SPD21 to SPD2n which can be subjected to power shutdown using power switches SWN11 to SWN1n and SWN21 to SWN2n, and control circuit blocks SCB1, SCB2 which are not by way of the power switches respectively. In the second power domains, a plurality of logic blocks IP11 to IP1n and IP21 to IP2n, which are sometimes called a plurality of IP (Intellectual Properties) modules, having predetermined functions are integrated. The logic blocks are integrated in the LSI via glue logics GLC11 to GLC1n and GLC21 to GLC2n being connection interface circuits. The power switches SWN11 to SWN1n and SWN21 to SWN2n are, while not particularly limited, formed by transistors manufactured by a process common to the logic blocks, that is, n-channel MOS transistors (hereinafter, sometimes described as thin-film power transistors) that can perform high-speed operation because of a small thickness of a gate insulating film and a low threshold voltage. Hereinafter, the power switches SWN11 to SWN1n and SWN21 to SWN2n are called thin-film power switches. Next, description is made on operation that LSI shuts down power of a particular logic block in a mode where the logic block is not used. The mode corresponds to a scene of using a mobile device in the case that the LSI is used for a system for mobile device. In this case, since a logic block to be unnecessary is varied depending on a mode, the LSI needs to perform power shutdown control of a particular logic block. Hereinafter, description is made on control that the logic block IP11 is assumed as such a particular logic block, and power of the logic block IP11 is shut down with an interrupt signal SINTEX0 from the outside of the LSI. First, when the interrupt signal SINTEX0 is inputted into the GINTIC, the GINTIC outputs an interrupt signal SINT1 to an interrupt control circuit INTC1 of a control circuit block SCB1 that performs control of the logic block IP11. When the interrupt signal SINT1 is inputted into the INTC1, an internal control circuit CTL1 outputs a control signal SGL11 to the logic block IP11. The control signal SGL11 is a power shutdown request signal, and inputted into the glue logic GLC11 of the logic block IP11. As control of stopping operation of the logic block IP11, the glue logic GLC11 allows data, which have been held in a storage element such as an appropriate memory or a flip-flop, to be held in a not-shown backup circuit as needed. As control by the glue logic GLC11, which is not particularly limited, the data may be saved into a register, SRAM memory, latch circuit or the like provided outside the second power domain SPD11, or held in an information hold circuit for power shutdown period, which is formed by a flip-flop having a latch circuit driven by a different power supply. In some logic block, data holding is not necessary, and in that case, the above save or hold of data can be omitted. Next, after the glue logic GLC11 allows the data in the logic block IP11 to be saved or held as necessary, it outputs a signal ACK11 to a register REG1 integrated in the control circuit block SCB1. The signal ACK11 is a signal for rewriting a specified bit of the REG1 for instructing execution of power shutdown control. For example, when a value of the specified bit is “0”, shutdown of power of the logic block IP11 is enabled, and when the value is “1”, use of the logic block IP11 is enabled. The CTL1 reads the value of the specified bit of the REG1, and when the value is “0”, it applies a voltage shown by GTN11 to a gate of a corresponding thin-film power switch SWN11 to allow the thin-film power switch SWN11 to be off. When a signal is outputted from the logic block IP11 to an external circuit such as the control circuit block SCB1, transmission of an irregular signal needs to be prevented during power shutdown, however, such control can be performed by the CTL1 using the control signal SGL11. Next, description is made on operation of returning the logic block IP11 being shut down in power. First, the CTR1 performs control of allowing the thin-film power switch SWN11 for the logic block IP11 to be on, and after the thin-film power switch SWN11 is perfectly on, the CTR1 performs operation setting of the logic block IP11. Whether the thin-film power switch SWN11 is perfectly into an on-state or not may be determined by measuring a fact that a gate signal of the thin-film power switch SWN11 is in high by, for example, using an unshown sensor circuit, or may be determined by setting a sequencer or the like such that timing at which the switch is perfectly into the on-state is previously calculated by simulation, and subsequent control is performed at an interval of such timing. Next, description is made on operation setting of the logic block IP11 after the thin-film power switch SWN11 is into the on-state. First, when the thin-film power switch SWN11 is into the on-state, the CTL11 outputs a signal instructing start of operation to the GLC11 of the logic block IP11. When the signal is inputted, the GLC11 drives a sequencer or the like within the GLC11 such that data saved before power shutdown is returned, and thus controls data transfer from an external storage device. When data are not saved before power shutdown, the above operation can be omitted. Then, for example, the GLC11 cancels gating of clock to start supply of clock in order to start operation of the logic block IP11. When the processing for starting operation of the logic block IP11 in this way is completed, the GLC11 rewrites a value of the specified bit of the REG1, which corresponds to the logic block, to be “1”. Thus, the logic block IP11 becomes available. Other logic blocks IP12 to IP1n can be subjected to power shutdown control by the control circuit block SCB1 as the logic block IP11. Next, description is made on a case of performing power shutdown of the first power domain PD1. The first power domain PD1 is subjected to power shutdown when none of the control circuit block SCB1 and the second power domains SCB11 to SCB1n is operated, that is, in a mode that the logic blocks IP11 to IP1n are not used. The power shutdown is controlled by the system controller SYSC. The SYSC outputs a REQ1 signal for allowing the thick-film power switch SW1 to be off to the PSWC1 for controlling a corresponding thick-film power switch SW1. When the REQ1 signal is inputted, the PSWC1 allows the thick-film power switch SW1 to be off, and furthermore, informs the SYSC of a fact that the first power domain PD1 is in a power shutdown condition by outputting an ACK1 signal to the SYSC. On the other hand, in the case that power of the first power domain PD1 is allowed to be on, the SYSC outputs a REQ1 signal for allowing the thick-film power switch SW1 to be on to the PSWC1. Then, the PSWC1 allows the thick-film power switch SW1 to be on, and furthermore, informs the SYSC of a fact that the first power domain PD1 becomes operable by outputting an ACK1 signal to the SYSC. FIG. 2 shows the logic LSI as a part of the LSI illustrated in FIG. 1. Here, connection relationships between various wiring lines in the logic LSI are shown in detail. The logic LSI has a plurality of first power domains PD1 to PD4 each of which is divided into sub power domains as described before. The sub power domains include a plurality of second power domains SPD11 to SPD42, and control circuit blocks SCB1 to SCB4. Each of the second power domains SPD11 to SPD42 is configured by a logic block including many transistors having a low threshold voltage. Therefore, the logic block is a circuit block that can perform high-speed operation. Here, since configurations of the first power domains PD1 to PD4 are approximately the same, only the first power domain PD1 is described for convenience of description. The first power domain PD1 includes virtual ground lines VSSM1 for receiving a ground voltage VSS, the lines VSSM1 being connected to the thick-film power switch SW1; a plurality of thin-film power switches SWN11, SWN12 connected to the virtual ground lines VSSM1; the second power domains SPD11, SPD12; and a control circuit block SCB1, and the like. The second power domains SPD11, SPD12 include sub virtual ground lines SVSSM11, SVSSM12 connected to the thin-film power switches SWN11, SWN12 respectively, and a logic block. The logic blocks are connected to the sub virtual ground lines SVSSM11, SVSSM12, and power lines VDDM1 for receiving a power voltage VDD. In the control circuit block SCB1, a control circuit for individually controlling the plurality of thin-film power switches SWN11, SWN12 or the like, and a circuit block such as various registers or control circuits being most fundamental in the first power domain PD1 are integrated. In the second power domains SPD11 and SPD12, CPU or DSP being omitted to be shown, other hardware accelerators and the like are integrated. In the LSI, the thick-film power switches SW1 to SW4 are controlled by power switch controllers PSWC1 to PSWC4 each of which can apply a high voltage to a gate of the power switch. As described before, the thick-film power switches SW1 to SW4 are formed by thick-film power transistors having a large thickness of the gate insulating film compared with the thin-film transistors included in the logic block, so that the gate tunnel leakage current can be reduced therein compared with in the thin-film transistor. Furthermore, since the thick-film power transistor is a highly-durable transistor that can be applied with a high gate voltage compared with the thin-film transistor, even if a high threshold voltage is set therein, a sufficiently low on-resistance is obtained. Therefore, the power switch controllers PSWC1 to PSWC4 allow the thick-film power switches SW1 to SW4 to be off, thereby a sub threshold leakage current can be reduced compared with in the thin-film transistor. Moreover, since the thick-film VCC power switches SW1 to SW4 can be operated at a higher voltage than the power voltage VDD, they cannot be designed by the same circuits as circuits of the second power domains SPD11 to SPD42, or circuits of the control circuit blocks SCB1 to SCB4. Therefore, the power switch controllers PSWC1 to PSWC4 are needed. The power switch controllers PSWC1 to PSWC4 are arranged in a partial region on a semiconductor substrate in a concentrated manner to reduce area in consideration of wiring of lines of the power voltage VCC (see FIG. 6). The thin-film power switches SWN11 to SWN42 control power supply to the second power domains SPD11 to SPD42, which are enabled to be controlled by control signals by the control circuit blocks SCB1 to SCB4 in the first power domains PD1 to PD4 respectively. This is because the thin-film power switches SWN11 to SWN42 can be operated at the same power voltage VDD as in the transistors configuring the control circuit blocks SCB1 to SCB4 or circuit blocks of the second power domains SPD11 to SPD42. In this way, since the thin-film power switches SWN11 to SWN42 can be controlled by the control circuit blocks SCB1 to SCB4, circuits of the switches can be designed using logic synthesis. Thus, the thin-film power switches SWN11 to SWN42 can be easily controlled by the control circuit blocks SCB1 to SCB4. Next the area OH is described. The area OH refers to a ratio (%) of SW area of the thin-film power switch SWN11 to the total area of a logic part area corresponding to the number of gates of the circuit block such as the logic block IP11 and the SW area. The thin-film power switch SWN11 is controlled in the following way; transistors in the same kind of those in the logic part such as N-channel MOS transistors are connected in series, and one of the transistors is subjected to off-control, thereby the switch SWN11 is controlled. When the power switch is integrated, transistors added as the switch are seen as a resistance during operation (on-resistance of transistor), which typically cause reduction in speed. For example, while a 2-input NAND circuit is considered as the simplest circuit using the N-channel MOS transistors as a switch, it is a well-known fact to those skilled in the art that delay in signal transmission is significantly increased in the NAND circuit compared with in an inverter circuit being simplest in CMOS circuits. This is because increase in on-resistance by vertically stacking the transistors significantly affects the delay. Typically, transistors are vertically stacked, thereby in a transistor of a second stage connected via a transistor of a first stage from a power line, since a source potential of the transistor of the second stage rises due to potential drop caused by on-resistance of the transistor of the first stage, even if a gate voltage of the transistor of the first stage is equal to a gate voltage of the transistor of the second stage, on-resistance of the transistor of the second stage is higher than on-resistance of the transistor of the first stage due to a substrate effect. Therefore, the NAND circuit operates slow compared with the inverter circuit. Since the NAND circuit and the like are required to have a logic operation function rather than high operation speed, they are designed with minimal area, thereby they are slow in operation speed compared with the inverter circuit. To increase speed of the 2-input NAND circuit, it is necessary that gate width of the transistor of the first stage as a switch is increased to gain a current, and potential drop of the first transistor is minimized to reduce on-resistance of the transistor of the second stage. Generally, a transistor has a feature that a current flows more easily therein in proportion to increase in gate width. This means that on-resistance is reduced in inverse proportion to gate width. Therefore, gate width of the transistor of the first stage needs to be set approximately 5 to 10 times as large as original width in order to make the speed of the NAND circuit approach original speed of the inverter. Next, a case that such a power switch is used for a region of a circuit block is considered. Typically, in a CMOS circuit, a signal is transmitted to a circuit of a subsequent stage at a speed of several tens of picoseconds to several hundred picoseconds. Such transmission time is approximately equal to time of circuit operation (for example, time in which a state of an inverter is changed from HI into LO). Moreover, in a typical synchronous CMOS logic circuit, operation is repeated in a period of a clock signal. While a combination of logic is changed in each period, operation probability of a circuit is considered to be approximately the same. When 300 MHz operation is considered, a period of a clock is 3.3 ns, and signal transmission is performed from a flip-flop (FF) to another FF in the period. Logic circuits can be integrated by the number corresponding to the number of circuits to which signals can reach in the period. For example, when the number of stages of logic of signal transmission is assumed to be 20, for example, 10 stages of circuits having logic delay of 30 ps, and 9 stages of circuits having logic delay of 300 ps can be mounted as details. This is merely an example, and the logic circuits can be designed such that circuits having various periods of delay are set within 3.3 ns. Considering in this way, current consumption can be regarded as consumption of a current averaged with a clock period. That is, since a signal outputted from FF is inputted into a circuit of a first stage, then the signal is sequentially transmitted while a current consumption position is changed, and finally the signal arrives at FF of a final stage, when power consumption in each moment is considered, current consumption in such circuits can be considered as power consumption of one circuit or adjacent, several circuits, rather than current consumption in such circuits in the case that all the circuits are concurrently operated. Therefore, when a power switch is used for a logic circuit block, the power switch is commonly provided in the logic circuit block, thereby a current consumed by a plurality of circuits is supplied by one power switch in a temporally dividing manner, and therefore size of the power switch can be reduced compared with a case that each circuit is added with a switch. In other words, when a power switch is provided in each circuit, while the power switch is used during operation of each circuit, after signal transmission into the relevant circuit is finished, the power switch does not fulfill a function of current supply. On the contrary, when a plurality of circuits share a power switch, the power switch effectively continues to work during a period in which a circuit covered by the power switch operates. Even in the case, since a supply current can have size enough to suit operation of at most several circuits, size of the power switch can be reduced. Furthermore, a case that the power switch is used for a somewhat larger circuit block is considered. In that case, probability of activation of a signal path itself from FF to another FF is newly added to items to be considered. Generally, a logic circuit has a plurality of signal processing paths, and a signal transmission path is typically changed depending on the content of operation. For example, when a program is considered, conditional branching is given. In the conditional branching, a plurality of calculation paths are selected according to a condition for operation. Therefore, when a circuit scale is increased, distribution of operation or non-operation of circuits tends to effectively appear. While operation probability (hereinafter, called activation ratio) of a circuit is changed depending on a property of a program to be operated, it is considered to be at most about 10%. Such an activation ratio can be defined only in a somewhat large circuit scale. Using the activation ratio as an index, simulation was carried out on a relationship between a circuit scale and size of a power switch. FIG. 3A illustrates area of a logic part and SW area corresponding to the number of gates. In the figure, a horizontal axis shows the number of gates, and a vertical axis shows area (arbitrary value). Since area of the logic part is in proportion to the number of gates, it is normalized with the number of gates, and area of the power switch is normalized with gate area. A result of the simulation was obtained under a condition that an activation ratio of the circuit block was constant, and a precondition described later. As a result, an expression (1) showing the area of the logic part corresponding to the number of gates, and an expression (2) showing the SW area were obtained. However, the number of gates≧10 was assumed in the simulation. Area of the logic part=number of gates expression (1) SW area=0.06*(number of gates)+5.15 expression (2) In the precondition of the simulation, a case that the power switch is used for a high-speed inverter (for example, inverter including transistors having a low threshold voltage) while keeping high speed of the inverter is considered. As clear from the above expressions, a feature is given, that is, while area of the logic part is in proportion to the number of gates, area of the power switch takes a constant value in a range of small gate number, in addition, increase in acceleration is one order of magnitude smaller than increase in acceleration of area of the logic part. In this example, since circuits needs to be designed using transistors having a small threshold voltage of the logic part circuit, and a large threshold voltage of the power switch, the constant value (y-intercept in the expression 2) is comparatively large, and consequently the area OH is large. Here, it is shown that in the case that the number of gates is 10, a power switch having area 5.75 times as large as original area is necessary. However, it is further shown that as the number of gates increases, overhead area of the power switch is relatively reduced. It reflects a fact that increase in operational average of a circuit becomes sufficiently small compared with increase in gate scale due to time-sharing operation of the circuit as described before. While the y-intercept in the expression 2 is an important factor in considering the area OH, since on-resistance of a transistor is in inverse proportion to gate width, even if size of the power switch is further increased, an effect of increase in speed is reduced. Therefore, the y-intercept shows minimum necessary area for satisfying speed to be required. When a value of the y-intercept is smaller than the relevant value, operation speed does not meet the speed to be required. When the value of the y-intercept is larger than the relevant value, cost increase is caused due to increase in area. While this is merely a numerical value in the case that one process technology is supposed, it is considered that an essential relationship does not deviate from such a relationship as long as a CMOS technology is used. According to the expressions (1) and (2), it is known that a ratio of increase in area of the logic part is larger than a ratio of increase in SW area due to difference in slope of a linear function. The reason for this is as follows: for example, when predetermined processing is performed in the logic block IP11, an activation ratio of the logic block IP11 is typically about 10%, and in this case, all the thin-film power transistors configuring the thin-film power switch SWN11 are responsible for supplying currents to activated logic circuits among a plurality of logic circuits included in the logic block IP11. In a word, while area (size) of the thin-film power transistors to be necessary for activating respective logic circuits included in the logic block IP11 is not changed, other thin-film power transistors arranged near logic circuits being unnecessary to be activated also supply currents to the logic circuits being necessary to be activated. In other words, this means that since other thin-film power transistors take part of power supply to the logic circuits, effective SW area, that is, total area of all the thin-film power transistors configuring the thin-film power switch SWN11 can be reduced. Thus, when the number of gates increases in some degree, the area OH can be controlled to be small. FIG. 3B illustrates area OH corresponding to the number of gates. In the figure, a horizontal axis shows the number of gates, and a vertical axis shows area OH (%). Here, for example, data are plotted such that a rate of increase in potential of the virtual ground lines VSSM1 is constant to voltage drop of the thin-film power switch SWN11 due to DC-like current consumed by the logic circuits in the logic block IP11. As a result, as the number of gates is increased, the area OH is decreased as shown in the figure. Specifically, as the number of gates is increased in order of 10, 20, 30, 40, 50, 100, 1000, 10000, and 100000, the area OH is decreased in order of 36.54, 24.13, 18.83, 15.9, 14.1, 10.11, 6.14, 5.74 and 5.7 respectively. According to the simulation result, it is known that the area OH is abruptly decreased in a gate number range of 10 to 100, and gradually decreased in a gate number range of 100 to 100000. In a word, when the number of gates is 100 or more, the area OH can be sufficiently reduced. In actual LSI, when a circuit scale is small, a high activation ratio must be considered in most cases as described before. Considering that the activation ratio is increased in the case that the number of gates is smaller in this way, it is highly possible that area OH in a region of small number of gates is large compared with that in the above estimation. Since a logic block defined by a logic circuit is generally considered to be a basic unit of the block to be subjected to bus connection, a logic scale of the block is designed to be sufficiently large compared with a logic scale of a bus connection interface. Therefore, the logic scale of the block typically reaches to about 10 kilo gates, that is, the number of gates is about 10,000 even in a logic block having the smallest logic scale. Calculation is made assuming that one gate corresponds to one 2-input NAND. When power shutdown is performed with such a logic block as a unit, the area OH illustrated in the figure can be set extremely small, 5.74%. For such a large-scale circuit, supposition in the above simulation is approximately true, consequently the area OH is also true. In this way, the reason for dividing the second power domains SPD11 to SPD42 with the logic block as a unit is that when the number of gates of the logic block is 100 or more, the area OH can be sufficiently reduced. Next, description is made on a relationship between vertical stacking of the thick-film power switch SW1 and the thin-film power switch SWN11 via the virtual ground line VSSM1, namely, series connection of the power switches, and operation speed. Vertical stacking of power switches has been regarded to be not preferable. This is because on-resistances of transistors are connected in series, causing reduction in on-current, consequently reduction in operation speed is concernedly caused. Therefore, vertically-stacked power switches are provided in a circuit block consuming a large current such as the logic block only in the case that speed reduction is allowed. On the contrary, in the LSI, for example, the sub virtual ground lines SVSSM11 connected to the thin-film power switch SWN11 are in a mesh structure, that is, wired with being approximately uniformly conducted in a region of the logic block IP11, and furthermore, thin-film power transistors of the thin-film power switch SWN11 are dispersedly arranged on the sub virtual ground lines SVSSM11, thereby reduction in impedance can be sufficiently achieved (see FIG. 7). Therefore, the thin-film power switch SWN11 as a whole can be grasped as a parallel resistance of a plurality of thin-film power transistors. Therefore, when the number of gates is, for example, 100 or more, since an effective on-resistance of the thin-film power switch SWN11 corresponding to the gates can be sufficiently reduced, increase in on-resistance due to vertical stacking is avoided. Furthermore, focusing the logic circuits activated when predetermined processing is performed in the logic block, the thin-film power transistors are shared, and therefore effective size of the thin-film power switch SWN11 is not reduced. As a result, even if the area OH is reduced correspondingly to the number of gates of the integrated logic block IP11, reduction in operation speed is not caused. Hereinafter, this is specifically described. FIG. 4 illustrates delay time in a circuit block corresponding to a rising rate of the ground voltage VSS to the power voltage VDD. The delay time in the circuit block can be grasped as speed reduction in the case that voltage drop occurs due to the power switch, and thereby potential of the virtual ground line VSSM rises. Evaluation results in the figure are results of investigation on reduction in speed of a single inverter circuit. Here, reduction in speed of the logic block as a circuit block has an extremely slight effect on operation speed in the case of potential rise of about 0.5%. In such a case, a rate of speed reduction was about 1%. The area OH according to the above simulation is calculated on a condition that potential rise of 0.5% is allowed. Even in the case of potential rise of about 1%, the rate of speed reduction was about 2%. In this way, an effect of the power switch on speed reduction was investigated in detail, as a result, it was known that even if the thick-film power switch SW1 and the thin-film power switch SWN11 were vertically stacked, when the area OH was about 10%, operation speed performance was obtained, which bore comparison with operation speed in the case that power shutdown was performed without stacking the switches. In a word, the thin-film power switches are appropriately used, thereby an effect is given: power shutdown control can be closely carried out without causing usually concerned, increase in speed reduction due to vertically-stacked power switches. FIG. 5 illustrates a leakage current in each mode. In the figure, a horizontal axis shows the mode, and vertical axis shows the leakage current. Modes 1 to 5 are modes during operation. Modes 6 to 10 are modes during standby. In the mode 1, all the circuit blocks are on, and a leakage current is 100 mA in this case. In the mode 2, circuit blocks being unnecessary to be operated are 10% of all the circuit blocks, which are subjected to power shutdown with the second domain SPD as a unit. An effect of reducing the leakage current due to power shutdown of the second domain SPD is varied by a relationship between the threshold voltage of the transistors configuring the logic block included in the second domain SPD and the threshold voltage of the thin-film power transistors of the thin-film power switches, and a current necessary for operating the logic block. For example, when it is assumed that the threshold voltage of the transistors configuring the logic block is different by 0.1 V from the threshold voltage of the thin-film power transistors of the thin-film power switches, the leakage current is changed approximately one digit. Furthermore, when width of the thin-film power transistors is tenth part of width of the transistors configuring the logic block, the leakage current is decreased to hundredth part in conjunction with an effect of difference in threshold voltage. In a word, since the leakage current is decreased two digits, it is known that in consideration of the amount of leakage current in the mode 1, power consumption can be reduced by 10% in the mode 2 by performing power shutdown of the circuits being unnecessary to be operated. In the modes 3 and 4, a ratio of the circuit blocks being unnecessary to be operated is increased compared with in the mode 2, consequently the leakage current can be further reduced. In this way, a circuit scale to be necessary is reduced, and the amount of leakage current can be reduced with increase in mode number. In the mode 5, all the second power domains SPD are subjected to power shutdown. At that time, when 10% of the whole circuit block is assumed to be supplied with current, the leakage current is decreased to tenth part compared with in the mode 1, that is, 10 mA. In a word, the thin-film power switches are controlled for each second power domain PD in the modes 1 to 5. On the contrary, in modes 6 to 9, power shutdown is performed for each first power domain PD during standby. The first power domain PD is subjected to power shutdown by the thick-film power switches, so that the leakage current can be drastically reduced. For example, the threshold voltage of the transistors configuring the logic block is different by at least about 0.3 V from the threshold voltage of the thick-film power transistors of the thick-film power switches. Therefore, the leakage current can be reduced to about thousandth part. Furthermore, when width of all gates of the thick-film power switch is tenth part compared with width of all gates of transistors included in the circuit block in the first power domain PD, the leakage current can be reduced to ten-thousandth part. For example, in the mode 6, only one circuit block is supplied with current to be in a standby state, and the leakage current is 1 mA. In the mode 7, only one circuit block is subjected to limited current supply to be in a standby state, and the leakage current is 500 μA. The limited current supply refers to current supply to a circuit block which is limitedly used in a partial region in the second power domain SPD. In this case, the circuit block may be a logic block, for example, in a logic scale of the number of gates of about 100, and the area OH can be controlled to be about 10% as shown in the FIG. 3B. In the mode 8, only one circuit block is subjected to limited current supply, and furthermore, the circuit block is made into a standby state with a voltage being lowered for low-speed operation, and the leakage current is 100 μA. In the mode 9, all the first power domains PD are subjected to power shutdown, and the leakage current is 10 μA. Consequently, control in combination of power shutdown by the thin-film power switches in the modes 1 to 5 and power shutdown by the thick-film power switches in the modes 6 to 9 is performed, thereby the circuit blocks being unnecessary to be operated are subjected to power shutdown, and only the minimum necessary circuit blocks are supplied with current, and consequently the leakage current can be reduced. According to this, logic LSI can be designed, which performs appropriate power supply corresponding to a mode, while many functions are integrated in one LSI. As a result, high-performance LSI can be achieved while the total leakage current in LSI configured as SoC is reduced. FIG. 6 illustrates a layout of LSI configured as SoC. Here, twenty, first power domains PD, and a plurality of second power domains SPD are illustrated, which are integrated on a semiconductor substrate SUB. The thick-film power switches SW are arranged in both ends of each first power domain PD. Power switch controllers PSWC are arranged in limited regions on the semiconductor substrate SUB. In the LSI, since when the number of gates of the logic block in the second power domain SPD is 100 or more, the area OH can be reduced as illustrated in FIG. 3B, for example, about one hundred, first power domains PD can be defined on the semiconductor substrate SUB. The number of the first power domains PD is increased, and the thick-film power switches SW and the thin-film power switches are combined for power shutdown control, thereby power shutdown control is performed more closely, and consequently reduction in leakage current corresponding to each mode can be achieved. FIG. 7 shows an integration example of the thick-film power switches and the thin-film power switches in LSI. In the figure, a region shown by oblique lines is assumed as a standard cell, and VDD for supplying current to the standard cell is also illustrated. The standard cell corresponds to the circuit block. Here, SW in the figure is shown as a plurality of thick-film power transistors configuring the thick-film power switch SW1 illustrated in FIG. 1, and similarly SWN in the figure is shown as a plurality of thin-film power transistors configuring the thin-film power switch SWN11 illustrated in FIG. 1. In the LSI, the virtual ground lines VSSM for receiving the ground voltage VSS, which are connected via the thick-film power transistors SW, are wired in a mesh pattern in the first power domain PD so as to be reduced in impedance. Similarly, power lines for receiving the power voltage VDD are wired in a mesh pattern in the first power domain PD so as to be reduced in impedance. Moreover, the sub virtual ground lines SVSSM connected to one another via the virtual ground lines VSSM and the thin-film power transistors SWN are similarly wired in a mesh pattern so as to be reduced in impedance. Since the sub virtual ground lines SVSSM are ground lines near the circuit blocks to be subjected to power shutdown, they are desirably in a mesh structure using a lower power line layer in a semiconductor substrate. Moreover, the virtual ground lines VSSM are made in a mesh structure using a higher power line layer in a semiconductor substrate, thereby area of the lines can be reduced. The thin-film power switches SWN11 are formed by the thin-film power transistors SWN having the same thickness of the gate insulating film as that of the circuit block as described before, and a large number of the switches SWN11 need to be integrated to achieve reduction in impedance. Therefore, the thin-film power transistors SWN are dispersedly arranged in the second power domain SPD as the standard cells. Furthermore, stabilizing capacitances DCP are integrated between the power voltage VDD and the sub virtual ground lines SVSSM. According to this, voltage drop can be controlled to be minimal. The thick-film power transistors SW are desirably integrated under longitudinal power trunk lines so as to be mounted while being prevented from increase in area. Embodiment 2 FIG. 8 shows a circuit configuration example of logic LSI according to embodiment 2 of the invention. Hereinafter, in each embodiment, portions having the same function and the like as those of the logic LSI according to the embodiment 1 are marked with the same references, and overlapped description is appropriately omitted. Here, the logic LSI includes a plurality of first power domains PD1 to PD4, thick-film power switches SW1 to SW4 that receives the ground voltage VSS, and are formed by n-channel MOS transistors, and power switch controllers PSWC1 to PSWC4 for controlling the thick-film power switches SW1 to SW4, therein. The first power domains PD1 to PD4 have a plurality of second power domains SPD11 to SPD42; control circuit blocks SCB1 to SCB4; power lines VDDM1 to VDDM4 for receiving the power voltage VDD; thin-film power switches SWP11 to SWP42 that are connected to the power lines VDDM1 to VDDM4 respectively, and formed by p-channel MOS transistors; and control circuits RC1 to RC4. The thick-film power switches SW1 to SW4 are connected with virtual ground lines VSSM1 to VSSM4. The thin-film power switches SWP11 to SWP42 are connected with virtual power lines SVDDM11 to SVDDM42. Logic blocks as circuit blocks are connected between the virtual ground lines VSSM1 to VSSM4 and the virtual power lines SVDDM11 to SVDDM42. Gates of the thin-film power switches SWP11 to SWP42 are connected with control circuits RC1 to RC4. The control circuits RC1 to RC4 allow the thin-film power switches SWP11 to SWP42 to function as regulators. According to this, while voltages of the second power domains SPD11 to SPD42 are lowered during standby to reduce a leakage current, an internal condition can be kept. For example, when a voltage is lowered by the thin-film power switch SWP11, the control circuit RC1 performs switch control intermittently to the thin-film power switch SWP11. Furthermore, the control circuit allows the second power domains to operate with a voltage being lowered during low-speed operation, thereby power consumption can be reduced. Embodiment 3 FIG. 9 shows a circuit configuration example of logic LSI according to embodiment 3 of the invention. Here, the logic LSI includes a plurality of first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4, therein. The first power domains PD1 to PD4 include a plurality of second power domains SPD11 to SPD42; control circuit blocks SCB1 to SCB4; power lines VDDM1 to VDDM4 for receiving the power voltage VDD; thin-film power switches SWP11 to SWP42 that are connected to the power lines VDDM1 to VDDM4 respectively, and formed by p-channel MOS transistors; and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches SW1 to SW4 via virtual ground lines VSSM1 to VSSM4 respectively, and formed by n-channel MOS transistors. The control circuit blocks SCB1 to SCB4 can control the thin-film power switches SWP11 to SWP42 and SWN11 to SWN42. The second power domains SPD11 to SPD42 include virtual power lines SVDDM11 to SVDDM42 connected to the thin-film power switches SWP11 to SWP42, sub virtual ground lines SVSSM11 to SVSSM42 connected to the thin-film power switches SWN11 to SWN42, and circuit blocks. As the circuit blocks, logic blocks connected between the virtual power lines SVDDM11 to SVDDM42 and the sub virtual ground lines SVSSM11 to SVSSM42 are given. In this way, the thin-film power switches SWP11 to SWP42 are arranged at a power side, and the thin-film power switches SWN11 to SWN42 are arranged at a ground side, and furthermore, the thin-film power switches SWP11 to SWP42 and the thick-film power switches SW1 to SW4 are in a hierarchical structure respectively. Thus, while an increase rate of SW area corresponding to the number of gates of a circuit block is somewhat increased, since threshold voltages of the thin-film power switches are apparently increased due to a substrate effect, the leakage current can be further reduced. Moreover, the thick-film power switches and the thin-film power switches are combined, thereby close power shutdown control can be performed correspondingly to a mode. Moreover, gates of the thin-film power switches SWP11 to SWP42 may be connected with the control circuits RC1 to RC4 illustrated in the embodiment 2. In this case, reduction in leakage current during standby, and reduction in power consumption during low-speed operation can be achieved as described before. Embodiment 4 FIG. 10 shows a circuit configuration example of logic LSI according to embodiment 4 of the invention. Here, the logic LSI includes a plurality of first power domains PD1 to PD4, thick-film power switches SW21 to SW24, and power switch controllers PSWC1 to PSWC4, therein. The thick-film power switches SW21 to SW24 receive the power voltage VDD, and are formed by p-channel MOS transistors. The first power domains PD1 to PD4 include a plurality of second power domains SPD11 to SPD42; control circuit blocks SCB1 to SCB4; thin-film power switches SWP11 to SWP42 that are connected to the thick-film power switches SW21 to SW24 via the virtual power lines VDDM1 to VDDM4 respectively, and formed by p-channel MOS transistors; and thin-film power switches SWN11 to SWN42 that receive the ground voltage VSS, and are formed by n-channel MOS transistors. The control circuit blocks SCB1 to SCB4 can control the thin-film power switches SWP11 to SWP42 and SWN11 to SWN42. The second power domains SPD11 to SPD42 include virtual power lines SVDDM11 to SVDDM42 connected to the thin-film power switches SWP11 to SWP42, sub virtual ground lines SVSSM11 to SVSSM42 connected to the thin-film power switches SWN11 to SWN42, and circuit blocks. As the circuit blocks, logic blocks connected between the sub virtual power lines SVDDM11 to SVDDM42 and the sub virtual ground lines SVSSM11 to SVSSM42 are given. According to this, high-speed operation of the circuit blocks is enabled, and close power shutdown control can be performed correspondingly to a mode while reducing the leakage current as the logic LSI of the embodiment 3. Embodiment 5 FIG. 11 shows a circuit configuration example of logic LSI according to embodiment 5 of the invention. Here, the logic LSI includes a plurality of first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4, therein. The first power domains PD1 to PD4 include a plurality of second power domains SPD11 to SPD42; control circuit blocks SCB10 to SCB40; and power switches SWN110 to SWN420 being connected to the thick-film power switches SW1 to SW4 via the virtual ground lines VSSM1 to VSSM4 respectively. The second power domains SPD11 to SPD42 include circuit blocks connected to power lines VDDM1 to VDDM4 for receiving the power voltage VDD, and not-shown sub virtual ground lines connected to the power switches SWN110 to SWN420. The power switches SWN110 to SWN420 are formed by power transistors in which the gate insulating films are thicker than gate insulating films of thin-film transistors arranged in regions of the circuit blocks, and thinner than gate insulating films of the thick-film power switches SW1 to SW4. The control circuit blocks SCB10 to SCB40 include level conversion circuits LS1 to LS4 for converting levels of voltages applied to gates of the power switches SWN110 to SWN420. According to this, since the power transistors forming the power switches SWN110 to SWN420 may have high threshold voltage compared with the thin-film transistors, the leakage current can be further reduced. Moreover, since the power switches SWN110 to SWN420 need to be applied with a high voltage compared with the thin-film transistors, the level conversion circuits LS1 to LS4 convert signal levels, thereby even if area of transistors included in the control circuit blocks SCB10 to SCB40 is reduced, a sufficient current can be obtained. Therefore, area of the control circuit blocks SCB10 to SCB40 can be reduced. High-Speed Return from Power Shutdown FIG. 12 illustrates a schematic configuration of a power switch achieving high-speed return from power shutdown. Here, description is made on a case that power shutdown is performed in the second power domain SPD while data of the flip-flop FF are backed up. Hereinafter, a flip-flop FF that holds a state even during power shutdown is called state-holding FF. For the state-holding FF, power, which is different from power for a typical standard cell, is controlled by a power switch SWNA. The power for the typical standard cell is controlled by a power switch SWNB. Thus, even if the typical standard cell is subjected to power shutdown, data of the state-holding FF is held. When such a state-holding FF is integrated, substrate potential is essentially made common between the cells in the light of reduction in area. However, when a substrate of the state-holding FF is in common with a substrate of the typical standard cell, in the case that the typical standard cell is subjected to power shutdown, substrate potential of the state-holding FF is shut down at the same time. Thus, the substrate of the state-holding FF is also into a floating condition, and therefore a relationship in substrate potential is reversed to power for the state-holding FF, and consequently a forward junction current may flow. When the substrate of the typical standard cell is separated from the substrate of the state-holding FF to avoid this, area OH is increased due to integration of the separated cells. Thus, as shown in the figure, a substrate of the typical standard cell and a substrate of the state-holding FF are made into common, so that even if the typical standard cell is subjected to power shutdown, the substrate is not subjected to power shutdown. In such a condition, increase in area OH can be suppressed. However, in this case, a large amount of junction leakage current passing through the substrate may flow in a fine processing process. Therefore, a power switch SWNC in a different system is provided also for substrate power, thereby the leakage current during standby can be reduced. Hereinbefore, while the invention made by the inventor was specifically described according to the embodiments, the invention is not limited to those, and it will be appreciated that the invention can be variously altered or modified within a scope without departing from the gist of the invention. For example, while the thick-film power switches SW1 to SW4 and SW21 to SW24 are formed by the thick-film transistors manufactured by a common process to the external input/output circuit I/O, and have different thickness of gate insulating films from the thin-film switches SWN11 to SWN42 and SWP11 to SWP42 or the power switches SWN110 to SWN420 in the embodiments 1 to 5, the invention is not limited to this. FIG. 13 shows a circuit configuration example of logic LSI in the case that respective power switches have the same gate insulating films. Here, the logic LSI includes a plurality of first power domains PD1 to PD4, power switches SW11 to SW14, and power switch controllers PSWC11 to PSWC14 therein. The first power domains PD1 to PD4 have a plurality of second power domains SPD11 to SPD42; control circuit blocks SCB1 to SCB4; and thin-film power switches SWN11 to SWN42 connected to the power switches SW11 to SW14 via the virtual ground lines VSSM1 to VSSM4 respectively. The second power domains SPD11 to SPD42 have circuit blocks connected to power lines VDDM11 to VDDM42 for receiving the power voltage VDD, and sub virtual ground lines SVSSM11 to SVSSM42 connected to the thin-film power switches SWN11 to SWN42. The power switches SW11 to SW14 are formed by thin-film power transistors in which the gate insulating films are same as those of thin-film transistors arranged in regions of the circuit blocks. In a word, here, in the logic LSI, all the power switches have the same thickness of the gate insulating films. The power switch controllers PSWC11 to PSWC14 applies a negative gate voltage VBN lower than the ground voltage VSS to gates of the power switches SW11 to SW14. Thus, even if the power switches SW11 to SW14 are used, which include transistors in which the gate insulating films are thin and the threshold voltages are low compared with the thick-film power switches, the leakage current can be controlled to be low. While an example of integrating the thick-film power switches and the thin-film power switches in LSI was shown in FIG. 7, the invention is not limited to this. FIG. 14 shows an example of integrating power switches, different from that in FIG. 7, and an example of wiring power lines. Here, an example is shown, in which first metal lines M1 are wired in a direction where standard cells are arranged, that is, in a lateral direction in the figure, and second metal lines M2, that is, VDD, VSS, VSSM and VSSM2 in the figure are wired in a direction perpendicular to the lateral direction. Moreover, regions under the second metal lines M2 are made to be switch regions, and sub power switches, capacitance cells and the like are integrated under the switch regions. Furthermore, regions shown by oblique lines in the figure correspond to switch cells SWcell which are formed only by P-well. The LSI as described hereinbefore can be used not only for the system for mobile devices such as mobile phone, but also various microprocessors to which high-speed operation and power saving are required.	H	67H01	185H01L	27	02
11630930	US20080111231A1-20080515	Semiconductor Device Comprising a Housing and a Semiconductor Chip Partly Embedded in a Plastic Housing Composition, and Method for Producing the Same	ACCEPTED	20080501	20080515	[]	H01L2314	["H01L2314", "H01L2102"]	7781900	20070801	20100824	257	789000	80120.0	NGUYEN	DAO	[{"inventor_name_last": "Carmona", "inventor_name_first": "Manuel", "inventor_city": "Barcelona", "inventor_state": "", "inventor_country": "ES"}, {"inventor_name_last": "Legen", "inventor_name_first": "Anton", "inventor_city": "Muenchen", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Wennemuth", "inventor_name_first": "Ingo", "inventor_city": "Muenchen", "inventor_state": "", "inventor_country": "DE"}]	One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an incorporated component having a phase change temperature. In this case, the softening temperature of the host component is greater than the phase change temperature of the incorporated component.	1.-16. (canceled) 17. A semiconductor device comprising: a housing; and a semiconductor chip partly embedded in a plastic housing composition; wherein the plastic housing composition has at least two mixture components, a host component having a softening temperature range in which the plastic housing composition increasingly softens as the temperature increases, and an incorporated component having a phase change range in which the incorporated component takes up heat of fusion or heat of crystallization and increasingly melts or increasingly undergoes transition to a crystalline form with the temperature of the housing remaining constant and with the heat loss of the semiconductor chip increasing; wherein the melting point or the crystallization temperature of the incorporated component of the plastic housing composition is lower than the softening temperature of the host component of the plastic housing composition. 18. The semiconductor device as claimed in claim 17, wherein the host component comprises an amorphous plastic and the incorporated component comprises a crystallizable plastic having a constant crystallization temperature. 19. The semiconductor device as claimed in claim 17, wherein the host component comprises a softenable thermosetting plastic or softenable thermoplastic having a softening temperature and the incorporated component comprises a fusible plastic having a constant melting point. 20. The semiconductor device as claimed in claim 17, wherein the plastic housing composition has a constant temperature of the phase change range of the incorporated component of between 65° C. and 155° C. 21. The semiconductor device as claimed in claim 17, wherein the plastic housing composition has a constant temperature of the phase change range of the incorporated component of between 80° C. and 130° C. 22. The semiconductor device as claimed in claim 17, wherein the incorporated component comprises a plastic based on terephthalic acid/ethylene glycol ester such as polyethylene terephthalate (PET). 23. The semiconductor device as claimed in claim 17, wherein the incorporated component comprises a paraffin-based plastic. 24. The semiconductor device as claimed in claim 17, wherein the incorporated component comprises a hydrated salt and/or eutectic salt. 25. The semiconductor device as claimed in claim 17, wherein the incorporated component comprises 30% by volume to 90% by volume of the total volume of the plastic housing component. 26. The semiconductor device as claimed in claim 17, wherein the incorporated component comprises 40% by volume to 60% by volume of the total volume of the plastic housing component. 27. The semiconductor device as claimed in claim 17, wherein the incorporated component is arranged in a manner distributed uniformly in the volume of the plastic housing composition in microbubbles of an order of magnitude of a few micrometers. 28. The semiconductor device as claimed in claim 27, wherein the microbubbles have a larger volume than the incorporated component arranged therein in the amorphous or solid state. 29. The semiconductor device as claimed in claim 17, wherein the semiconductor chip is a memory device with a central bonding channel on a carrier substrate. 30. A method for producing a semiconductor device comprising a housing and a semiconductor chip partly embedded in a plastic housing composition, the method comprising: producing a carrier substrate for a semiconductor chip; applying a semiconductor chip to the carrier substrate; producing electrical connections between semiconductor chip and carrier substrate; and packaging the semiconductor chip on the carrier substrate into a plastic housing composition, the plastic housing composition being mixed together from at least two mixture components prior to packaging and the plastic housing composition being heated above a softening temperature of the host component for packaging, and the semiconductor chip being packaged at said temperature, and the host component solidifying before the incorporated component after packaging. 31. The method as claimed in claim 29, wherein during packaging the host component falls below its softening temperature and encloses the incorporated component in a manner distributed uniformly in the volume in microbubbles in an amorphous and/or liquid state, and the volume of the incorporated component shrinks in the microbubbles upon further cooling. 32. The method as claimed in claim 29, wherein for packaging, the plastic housing composition is heated to a temperature between the softening temperature and decomposition temperature of the host component. 33. The method as claimed in claim 29, wherein prior to packaging, the host component and the incorporated component are mixed in the solid state in powder form. 34. The method as claimed in claim 29, wherein prior to the application of the semiconductor chip to the carrier substrate, the latter is coated with a double-sided adhesive film with a central bonding channel being left free, and the semiconductor chip is subsequently applied by its active top side to the carrier substrate with alignment of its contact areas in the central bonding channel, and afterward a connection of the contact areas of the semiconductor chip in the bonding channel to a wiring structure of the carrier substrate is produced and the central bonding channel is filled with a plastic composition comprising only the host component of the plastic housing composition, and the rear side and the edge sides of the semiconductor chip are embedded in the plastic housing composition comprising at least two mixture components. 35. A semiconductor device comprising: a housing; a semiconductor chip partly embedded in a plastic housing composition; wherein the plastic housing composition comprises: host means having a softening temperature for increasingly softening the plastic housing composition as the temperature increases; and incorporated means for taking up heat and increasingly melting or increasingly undergoing transition to a crystalline form with the temperature of the housing remaining constant and with the heat loss of the semiconductor chip increasing; wherein a melting point or a crystallization temperature of the incorporated means is lower than the softening temperature of the host means.	<SOH> BACKGROUND <EOH>The invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition, and to a method for producing the same. The power loss that arises in BGA housings (ball grid array), for example, is not generated with a uniform and constant magnitude over time in most applications. Rather, periods of high power loss are temporally limited and alternate with periods of low power losses. In particular this applies to the customary pulse methods in which no heat loss whatsoever arises in the interpulse intervals. It is only in the active phase of the pulse that a high heat loss arises, which is emitted from the semiconductor chip to the housing. Typical situations for the thermal behavior of a semiconductor device thus arise during these periods of high power losses. Many solutions for improving the thermal behavior of the plastic housing compositions have already been proposed, but most of these solutions are based on optimizing the static thermal behavior of the housing plastic compositions. Moreover, many of these solutions are very cost-intensive and may reduce the reliability of the housing. Said solutions include for example an integrated heat sink or a heat distributing plate within the housing. This is a cost-intensive solution with additional reliability risks, with the result that the thermal problems can be only partly solved thereby. Another solution is concerned with so-called underfill materials. The latter are used to fill interspaces between a semiconductor chip and a superordinate circuit board arranged underneath. This is a cost-intensive thermostatic solution that is usually associated with technological problems. Accordingly, the temperature stabilization of semiconductor devices is a constant problem. As the construction, the speed and the complexity of the semiconductor devices are increasingly improved, increasingly large amounts of heat loss are generated in the semiconductor devices. What is more, the increasing miniaturization of the housings in which semiconductor devices are accommodated provides for a reduction of the possibilities for enabling said semiconductor devices to distribute heat to the surroundings by convection. With increasing miniaturization of the housings it becomes more and more difficult to provide adequate cooling in the surrounding space, especially as the possibility and the efficacy of convection flows are reduced with increasing miniaturization of the housing sizes. There is additionally the problem of the field of application of these increasingly shrinking semiconductor devices, which nowadays are often incorporated in portable electronic devices such as earphones, portable mobile telephones, portable television sets and also miniature computers and schedulers. The demand for smaller housings produced from lighter materials such as plastics is constantly increasing. These housings are generally lighter than metal housings, but these plastic housings of mobile phones, portable telephones or notebook computers have a higher thermal conduction resistance, with the result that the possibility of dissipating the heat loss of the active semiconductor devices via the housing of these devices has diminished. Consequently, the problem of heat loss dissipation in extremely small devices having electronic semiconductor devices is increasing as the use of plastic housings increases. Since the reliability of semiconductor devices is associated with the temperature of the devices, many manufacturers of portable electronic systems have conceived of reducing the amount of heat in the semiconductor devices by distributing the heat that is generated within the devices. In particular, it has been attempted to distribute the heat loss within power devices by thermal conduction in order to avoid peak temperatures. Other manufacturers of power devices have attempted to incorporate metallic heat sinks in their power devices, but the efficacy of said heat sinks is very restricted by virtue of the reduction of the available surroundings in the small portable devices for cooling the heat sinks. In addition, the weight of such metallic components for portable electronic devices is neither a contribution for reducing the size nor a contribution for reducing the weight, so that metallic heat sinks within these devices are not very promising. A further method for reducing the generation of heat loss consists in changing over from an analog design to a digital design. The digital communication systems have therefore substantially replaced analog communication systems, especially as digital systems generally enable improved properties and a generally lower generation of power loss than analog systems, since digital systems operate with a pulse mode. This means that digital systems constantly switch on and off; on the other hand, these pulses may be nested in one another in the form of a plurality of grading systems which can also reduce the total power distribution in a communication system, since these digital systems are operated in only a fraction of the time compared with continuous system. However, precisely these pulse-operated systems can generate considerable peak power losses during the switched-on pulse. Consequently, rapid power changes may lead to considerably increased thermal stress of the devices during switching on and off. Accordingly, precisely in portable communication systems, the rapid switchover of powers may lead to considerable thermal and mechanical stresses in the semiconductor devices. As a result, circuit connections, wire bonding connections and other mechanical components are severely loaded, which likewise reduces the reliability of these systems. However, since portable electronic devices cannot contain heat sinks for reducing the temperature fluctuations on account of rapid power switching sequences, there is a need to reduce said thermal and mechanical stresses without having to use additional metal heat sinks or heat dissipation arrangements. For these and other reasons, there is a need for the present invention.	<SOH> SUMMARY <EOH>One embodiment of the invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition in which the plastic housing composition ensures that a limited heat compensation is provided in the case of an increased power loss occurring momentarily. One embodiment of the invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. The plastic housing composition of this semiconductor device includes at least two mixture components. One of the mixture components is a host component having a softening temperature range in which said plastic housing composition increasingly softens as the temperature increases. The other one of the mixture components is an incorporated component having a phase change range in which the incorporated component takes up heat of fusion or heat of crystallization and increasingly melts or increasingly undergoes transition to a crystalline form with the temperature of the housing remaining constant and with the heat loss of the semiconductor chip increasing. In the case of this semiconductor device, the melting point or crystallization temperature of the incorporated component of the plastic housing composition is lower than the softening temperature of the host component. With a semiconductor device including such a housing based on a plastic composition according to one embodiment of the present invention, the heat loss of a semiconductor chip can be stored in the plastic housing composition if the temperature of the housing composition reaches a specific critical temperature, that is to say the temperature of the phase change range of the incorporated component. During this phase change from, for example, an amorphous state to a crystalline state or from a solid state to a liquid state, the temperature of the plastic housing composition remains constant during the storage phase or phase change. For a limited period of time, with the power loss increasing, for a number of minutes depending on the chosen incorporated material and the ratio between the quantity of the incorporated component with respect to the quantity of the host component, the housing temperature is kept constant before it rises further, when the heat storage capability of the plastic housing material is exceeded, up to the softening temperature range of the host component. In an operating phase of the semiconductor device in which the power loss is reduced, the stored heat can be emitted again from the plastic housing composition, the original phase state of the incorporated component being reestablished. With one embodiment of this semiconductor device, the critical temperature at which the housing temperature remains constant for a period of time can be adapted to the specific temperature of the semiconductor PN junction of the semiconductor chip by selection of the incorporated material. It is thus possible, by way of example, to set the phase change temperature, such as melting point or a crystallization temperature, to 85° C., for example, thereby preventing malfunctions of the semiconductor chip in this plastic housing composition for a limited time. Since this material has completely different mechanical properties at a high temperature than at a low temperature, it is also possible to influence other parameter such as a reduction of thermal stresses with the aid of the plastic housing composition in such a way that the reliability of these semiconductor devices is improved. By way of example, warpage effects such as occur in the case of conventional plastic housing compositions can be reduced. Moreover, it is possible to reduce the stresses induced by warpage on solder balls, for example, in particular during the cyclic temperature tests for semiconductor devices. Through the use of a plastic housing composition having an incorporated component having a phase change range, it is possible to compensate for peak values in the power loss of the semiconductor chip by means of the good thermal contact between the plastic housing composition and the semiconductor chip embedded in the plastic housing composition, so that on average a critical PN junction temperature is not exceeded. In this case, this plastic housing composition composed of a mixture of host component and incorporated component may be used in a conventional molding process. In one embodiment of the invention, the host component includes an amorphous plastic which maintains this amorphous state even at elevated temperature and undergoes transition to a tough viscous state in the event of the softening temperature being exceeded. The incorporated component, by contrast, has a crystallizable phase and undergoes transition from an amorphous state at low temperatures to a crystalline state at a constant crystallization temperature, in which the incorporated component has largely attained the crystalline state. With this embodiment of the invention, a solid-solid phase transition is the basis and no change occurs in the state of matter of the incorporated component. In a further embodiment of the invention, the host component is a softenable thermosetting plastic or a softenable thermoplastic having a corresponding softening temperature and a corresponding softening temperature range, or the incorporated component has a fusible plastic having a constant melting point, the melting point of which lies below the softening temperature. With a semiconductor device having a plastic housing composition of this type, the energy taken up by the plastic housing composition as a result of the change in the state of matter of the incorporated component is greater than in the case of a solid-solid phase transition. In a further embodiment of the invention, the constant temperature of the plastic housing composition and hence the temperature of the phase transition range of the incorporated component is at a temperature of between 65° C. and 155° C., in one example at a temperature of between 80° C. and 130° C. With a semiconductor device which ensures a constant temperature in the given or in preferred temperature ranges, the reliability of the device is increased and malfunctions of the semiconductor device are reduced. In a further embodiment of the invention, the incorporated component includes a plastic based on terephthalic acid/ethylene glycol ester, and in one example a polyethylene terephthalate (PET) ester. With said plastic, it undergoes a phase change between amorphous and crystalline at predetermined crystallization temperatures, with the result that it may be suitable for a plastic housing composition according to the invention. In a further embodiment of the invention, the incorporated component of the plastic housing composition is based on a paraffin basis. Paraffins also have the property of providing phase transitions in the solid state. Finally, it is also possible to use hydrated salts and/or eutectic salts as incorporated components. In this case, the solid-liquid phase transition is utilized in order to keep the temperature in a plastic housing constant for a limited time. However, said salts are electrically conductive upon attaining the liquid phase, so that in the case of the plastic housing composition care must be taken to ensure that said hydrated salts and/or eutectic salts are incorporated in finely distributed fashion as microbubbles in the host component, and no closed electrically conductive bridges can arise between adjacent conductor tracks via the incorporated components. In a further embodiment of the invention, the incorporated component includes 30% by volume to 90% by volume, and in one example 40% by volume to 60% by volume, of the total volume of the plastic housing composition. The percentage proportion by volume made up by the incorporated component in the total volume of the plastic housing composition can be used to set the time duration of the constant temperature phase or the time duration for the phase transition from amorphous to crystalline and/or from solid to liquid. The higher the percentage proportion by volume made up by the incorporated component, the longer it is possible to maintain the constant temperature phase for the housing of the semiconductor device. In a further embodiment of the invention, the incorporated component is distributed uniformly in the form of microbubbles in the volume of the plastic housing composition, the microbubbles being arranged for an order of magnitude of a few micrometers in the plastic housing composition. In this case, the microbubbles have a larger volume than the incorporated component arranged therein in the amorphous or solid state. The larger volume of the microbubbles prevents the occurrence of stresses in the plastic housing composition, which might lead to microcracks in the housing, during the phase transition from solid to liquid or during the phase transition from amorphous to crystalline which are usually associated with an increase in volume. In a further embodiment of the invention, the semiconductor chip is a memory device having a central bonding channel on a carrier substrate. The embedding of the semiconductor chip in a plastic housing composition composed of a mixture of host component and incorporated component has proved worthwhile precisely in the case of memory components. A method for producing a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition has the following method steps. The first step involves providing a carrier substrate for a semiconductor chip. Afterward, a semiconductor chip is applied to the carrier substrate and electrical connections are produced between the semiconductor chip and the carrier substrate. The semiconductor chip on the carrier substrate is then embedded in a plastic housing composition, the plastic housing composition being mixed together from at least two mixture components, a host component and an incorporated component, prior to packaging. The plastic housing composition is heated beyond the softening temperature of the host component for packaging, and the semiconductor chip is packaged at this temperature. In this case, the incorporated component has a phase change range whose phase change temperature lies below the softening temperature of the host component. After packaging, the host component solidifies before the incorporated component. With this method, during packaging a housing made from a plastic composition arises which can take up heat loss of the semiconductor chips for a limited time without the temperature of the housing increasing. What is more, with this method, the semiconductor device can be produced by means of conventional molding tools and only the constitution of the plastic housing composition changes in comparison with conventional synthetic resin housings. The production sequence does not have to be altered further apart from a step of premixing host component and incorporated component. In the case of this production method, a degree of filling of the host component with the material of the incorporated component is achieved which determines the capacity for taking up heat loss of the semiconductor chip and hence the time duration for a constant temperature of the plastic housing despite an increasing power loss of the semiconductor chip. The greater the degree of filling with the incorporated component, the longer the period of time during which the housing is kept at a constant temperature. In one implementation of the method, during packaging or shortly after the application of the viscous plastic housing composition to the semiconductor chip, the host component is cooled below its softening temperature, while the incorporated component forms microbubbles in an amorphous and/or liquid state in a manner distributed uniformly in the volume of the host component in this cooling process. Upon further cooling, the volume of the incorporated component shrinks in the microbubbles and leaves a cavity which ensures that during the operation of the semiconductor device no stresses occur on account of the expansion of the incorporated component during a phase transition. In a further form of implementation of the method, for packaging the plastic housing composition is heated to a temperature between the softening temperature and the decomposition temperature of the host component. This limited range of heating is provided particularly when processing thermosetting plastics as host component, since thermosetting plastics do not have a liquefying temperature after the softening phase, but rather decompose. Consequently, the packaging temperature remains significantly below this critical decomposition temperature for thermosetting plastics. In the case of thermoplastics, this temperature is not known since thermoplastics undergo transition to a liquid state of matter after the softening temperature range. The mixing of host component and incorporated component prior to heating for packaging a semiconductor chip on a carrier substrate is in one example carried out in the solid state of the two components. For this purpose, at least the incorporated component is put into a powder form having an average grain diameter of less than 10 μm. This is associated with the advantage that it is possible to achieve a relatively uniform distribution of the incorporated component in the powder of the host component. In a further form of implementation of the invention, a memory device having a central bonding channel is produced in concrete terms. For this purpose, firstly a semiconductor chip including memory cells is applied to the carrier substrate. A double-sided adhesive film that leaves free the central bonding channel of the semiconductor chip is used during this application. The semiconductor chip is applied by its active top side to the carrier substrate with alignment of its contact areas in the central bonding channel. This is followed by the production of the contact areas of the semiconductor chip in the bonding channel with a wiring structure of the carrier substrate. Finally, the central bonding channel is filled with a plastic composition having at least the host component. The rear side and the edge sides of the semiconductor chip are then embedded in a plastic housing composed of at least two mixture components, the host component and an incorporated component, as described above. With a semiconductor device of this type, on account of the properties of the incorporated component, the housing can be kept for a limited time duration at a constant temperature as the heat loss of the semiconductor chip rises. Furthermore, with this device, the encapsulating plastic housing composition is in close contact with the semiconductor chip material, with the result that an intensive heat transfer to the heat-storing plastic housing composition is possible. With this semiconductor device, a constant housing temperature can be achieved without any metallic heat sink. Rather, the heat sink is formed by the plastic housing material itself, because the incorporated component can take up heat loss and converts the latter into phase change heat such as heat of fusion or heat of crystallization.	BACKGROUND The invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition, and to a method for producing the same. The power loss that arises in BGA housings (ball grid array), for example, is not generated with a uniform and constant magnitude over time in most applications. Rather, periods of high power loss are temporally limited and alternate with periods of low power losses. In particular this applies to the customary pulse methods in which no heat loss whatsoever arises in the interpulse intervals. It is only in the active phase of the pulse that a high heat loss arises, which is emitted from the semiconductor chip to the housing. Typical situations for the thermal behavior of a semiconductor device thus arise during these periods of high power losses. Many solutions for improving the thermal behavior of the plastic housing compositions have already been proposed, but most of these solutions are based on optimizing the static thermal behavior of the housing plastic compositions. Moreover, many of these solutions are very cost-intensive and may reduce the reliability of the housing. Said solutions include for example an integrated heat sink or a heat distributing plate within the housing. This is a cost-intensive solution with additional reliability risks, with the result that the thermal problems can be only partly solved thereby. Another solution is concerned with so-called underfill materials. The latter are used to fill interspaces between a semiconductor chip and a superordinate circuit board arranged underneath. This is a cost-intensive thermostatic solution that is usually associated with technological problems. Accordingly, the temperature stabilization of semiconductor devices is a constant problem. As the construction, the speed and the complexity of the semiconductor devices are increasingly improved, increasingly large amounts of heat loss are generated in the semiconductor devices. What is more, the increasing miniaturization of the housings in which semiconductor devices are accommodated provides for a reduction of the possibilities for enabling said semiconductor devices to distribute heat to the surroundings by convection. With increasing miniaturization of the housings it becomes more and more difficult to provide adequate cooling in the surrounding space, especially as the possibility and the efficacy of convection flows are reduced with increasing miniaturization of the housing sizes. There is additionally the problem of the field of application of these increasingly shrinking semiconductor devices, which nowadays are often incorporated in portable electronic devices such as earphones, portable mobile telephones, portable television sets and also miniature computers and schedulers. The demand for smaller housings produced from lighter materials such as plastics is constantly increasing. These housings are generally lighter than metal housings, but these plastic housings of mobile phones, portable telephones or notebook computers have a higher thermal conduction resistance, with the result that the possibility of dissipating the heat loss of the active semiconductor devices via the housing of these devices has diminished. Consequently, the problem of heat loss dissipation in extremely small devices having electronic semiconductor devices is increasing as the use of plastic housings increases. Since the reliability of semiconductor devices is associated with the temperature of the devices, many manufacturers of portable electronic systems have conceived of reducing the amount of heat in the semiconductor devices by distributing the heat that is generated within the devices. In particular, it has been attempted to distribute the heat loss within power devices by thermal conduction in order to avoid peak temperatures. Other manufacturers of power devices have attempted to incorporate metallic heat sinks in their power devices, but the efficacy of said heat sinks is very restricted by virtue of the reduction of the available surroundings in the small portable devices for cooling the heat sinks. In addition, the weight of such metallic components for portable electronic devices is neither a contribution for reducing the size nor a contribution for reducing the weight, so that metallic heat sinks within these devices are not very promising. A further method for reducing the generation of heat loss consists in changing over from an analog design to a digital design. The digital communication systems have therefore substantially replaced analog communication systems, especially as digital systems generally enable improved properties and a generally lower generation of power loss than analog systems, since digital systems operate with a pulse mode. This means that digital systems constantly switch on and off; on the other hand, these pulses may be nested in one another in the form of a plurality of grading systems which can also reduce the total power distribution in a communication system, since these digital systems are operated in only a fraction of the time compared with continuous system. However, precisely these pulse-operated systems can generate considerable peak power losses during the switched-on pulse. Consequently, rapid power changes may lead to considerably increased thermal stress of the devices during switching on and off. Accordingly, precisely in portable communication systems, the rapid switchover of powers may lead to considerable thermal and mechanical stresses in the semiconductor devices. As a result, circuit connections, wire bonding connections and other mechanical components are severely loaded, which likewise reduces the reliability of these systems. However, since portable electronic devices cannot contain heat sinks for reducing the temperature fluctuations on account of rapid power switching sequences, there is a need to reduce said thermal and mechanical stresses without having to use additional metal heat sinks or heat dissipation arrangements. For these and other reasons, there is a need for the present invention. SUMMARY One embodiment of the invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition in which the plastic housing composition ensures that a limited heat compensation is provided in the case of an increased power loss occurring momentarily. One embodiment of the invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. The plastic housing composition of this semiconductor device includes at least two mixture components. One of the mixture components is a host component having a softening temperature range in which said plastic housing composition increasingly softens as the temperature increases. The other one of the mixture components is an incorporated component having a phase change range in which the incorporated component takes up heat of fusion or heat of crystallization and increasingly melts or increasingly undergoes transition to a crystalline form with the temperature of the housing remaining constant and with the heat loss of the semiconductor chip increasing. In the case of this semiconductor device, the melting point or crystallization temperature of the incorporated component of the plastic housing composition is lower than the softening temperature of the host component. With a semiconductor device including such a housing based on a plastic composition according to one embodiment of the present invention, the heat loss of a semiconductor chip can be stored in the plastic housing composition if the temperature of the housing composition reaches a specific critical temperature, that is to say the temperature of the phase change range of the incorporated component. During this phase change from, for example, an amorphous state to a crystalline state or from a solid state to a liquid state, the temperature of the plastic housing composition remains constant during the storage phase or phase change. For a limited period of time, with the power loss increasing, for a number of minutes depending on the chosen incorporated material and the ratio between the quantity of the incorporated component with respect to the quantity of the host component, the housing temperature is kept constant before it rises further, when the heat storage capability of the plastic housing material is exceeded, up to the softening temperature range of the host component. In an operating phase of the semiconductor device in which the power loss is reduced, the stored heat can be emitted again from the plastic housing composition, the original phase state of the incorporated component being reestablished. With one embodiment of this semiconductor device, the critical temperature at which the housing temperature remains constant for a period of time can be adapted to the specific temperature of the semiconductor PN junction of the semiconductor chip by selection of the incorporated material. It is thus possible, by way of example, to set the phase change temperature, such as melting point or a crystallization temperature, to 85° C., for example, thereby preventing malfunctions of the semiconductor chip in this plastic housing composition for a limited time. Since this material has completely different mechanical properties at a high temperature than at a low temperature, it is also possible to influence other parameter such as a reduction of thermal stresses with the aid of the plastic housing composition in such a way that the reliability of these semiconductor devices is improved. By way of example, warpage effects such as occur in the case of conventional plastic housing compositions can be reduced. Moreover, it is possible to reduce the stresses induced by warpage on solder balls, for example, in particular during the cyclic temperature tests for semiconductor devices. Through the use of a plastic housing composition having an incorporated component having a phase change range, it is possible to compensate for peak values in the power loss of the semiconductor chip by means of the good thermal contact between the plastic housing composition and the semiconductor chip embedded in the plastic housing composition, so that on average a critical PN junction temperature is not exceeded. In this case, this plastic housing composition composed of a mixture of host component and incorporated component may be used in a conventional molding process. In one embodiment of the invention, the host component includes an amorphous plastic which maintains this amorphous state even at elevated temperature and undergoes transition to a tough viscous state in the event of the softening temperature being exceeded. The incorporated component, by contrast, has a crystallizable phase and undergoes transition from an amorphous state at low temperatures to a crystalline state at a constant crystallization temperature, in which the incorporated component has largely attained the crystalline state. With this embodiment of the invention, a solid-solid phase transition is the basis and no change occurs in the state of matter of the incorporated component. In a further embodiment of the invention, the host component is a softenable thermosetting plastic or a softenable thermoplastic having a corresponding softening temperature and a corresponding softening temperature range, or the incorporated component has a fusible plastic having a constant melting point, the melting point of which lies below the softening temperature. With a semiconductor device having a plastic housing composition of this type, the energy taken up by the plastic housing composition as a result of the change in the state of matter of the incorporated component is greater than in the case of a solid-solid phase transition. In a further embodiment of the invention, the constant temperature of the plastic housing composition and hence the temperature of the phase transition range of the incorporated component is at a temperature of between 65° C. and 155° C., in one example at a temperature of between 80° C. and 130° C. With a semiconductor device which ensures a constant temperature in the given or in preferred temperature ranges, the reliability of the device is increased and malfunctions of the semiconductor device are reduced. In a further embodiment of the invention, the incorporated component includes a plastic based on terephthalic acid/ethylene glycol ester, and in one example a polyethylene terephthalate (PET) ester. With said plastic, it undergoes a phase change between amorphous and crystalline at predetermined crystallization temperatures, with the result that it may be suitable for a plastic housing composition according to the invention. In a further embodiment of the invention, the incorporated component of the plastic housing composition is based on a paraffin basis. Paraffins also have the property of providing phase transitions in the solid state. Finally, it is also possible to use hydrated salts and/or eutectic salts as incorporated components. In this case, the solid-liquid phase transition is utilized in order to keep the temperature in a plastic housing constant for a limited time. However, said salts are electrically conductive upon attaining the liquid phase, so that in the case of the plastic housing composition care must be taken to ensure that said hydrated salts and/or eutectic salts are incorporated in finely distributed fashion as microbubbles in the host component, and no closed electrically conductive bridges can arise between adjacent conductor tracks via the incorporated components. In a further embodiment of the invention, the incorporated component includes 30% by volume to 90% by volume, and in one example 40% by volume to 60% by volume, of the total volume of the plastic housing composition. The percentage proportion by volume made up by the incorporated component in the total volume of the plastic housing composition can be used to set the time duration of the constant temperature phase or the time duration for the phase transition from amorphous to crystalline and/or from solid to liquid. The higher the percentage proportion by volume made up by the incorporated component, the longer it is possible to maintain the constant temperature phase for the housing of the semiconductor device. In a further embodiment of the invention, the incorporated component is distributed uniformly in the form of microbubbles in the volume of the plastic housing composition, the microbubbles being arranged for an order of magnitude of a few micrometers in the plastic housing composition. In this case, the microbubbles have a larger volume than the incorporated component arranged therein in the amorphous or solid state. The larger volume of the microbubbles prevents the occurrence of stresses in the plastic housing composition, which might lead to microcracks in the housing, during the phase transition from solid to liquid or during the phase transition from amorphous to crystalline which are usually associated with an increase in volume. In a further embodiment of the invention, the semiconductor chip is a memory device having a central bonding channel on a carrier substrate. The embedding of the semiconductor chip in a plastic housing composition composed of a mixture of host component and incorporated component has proved worthwhile precisely in the case of memory components. A method for producing a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition has the following method steps. The first step involves providing a carrier substrate for a semiconductor chip. Afterward, a semiconductor chip is applied to the carrier substrate and electrical connections are produced between the semiconductor chip and the carrier substrate. The semiconductor chip on the carrier substrate is then embedded in a plastic housing composition, the plastic housing composition being mixed together from at least two mixture components, a host component and an incorporated component, prior to packaging. The plastic housing composition is heated beyond the softening temperature of the host component for packaging, and the semiconductor chip is packaged at this temperature. In this case, the incorporated component has a phase change range whose phase change temperature lies below the softening temperature of the host component. After packaging, the host component solidifies before the incorporated component. With this method, during packaging a housing made from a plastic composition arises which can take up heat loss of the semiconductor chips for a limited time without the temperature of the housing increasing. What is more, with this method, the semiconductor device can be produced by means of conventional molding tools and only the constitution of the plastic housing composition changes in comparison with conventional synthetic resin housings. The production sequence does not have to be altered further apart from a step of premixing host component and incorporated component. In the case of this production method, a degree of filling of the host component with the material of the incorporated component is achieved which determines the capacity for taking up heat loss of the semiconductor chip and hence the time duration for a constant temperature of the plastic housing despite an increasing power loss of the semiconductor chip. The greater the degree of filling with the incorporated component, the longer the period of time during which the housing is kept at a constant temperature. In one implementation of the method, during packaging or shortly after the application of the viscous plastic housing composition to the semiconductor chip, the host component is cooled below its softening temperature, while the incorporated component forms microbubbles in an amorphous and/or liquid state in a manner distributed uniformly in the volume of the host component in this cooling process. Upon further cooling, the volume of the incorporated component shrinks in the microbubbles and leaves a cavity which ensures that during the operation of the semiconductor device no stresses occur on account of the expansion of the incorporated component during a phase transition. In a further form of implementation of the method, for packaging the plastic housing composition is heated to a temperature between the softening temperature and the decomposition temperature of the host component. This limited range of heating is provided particularly when processing thermosetting plastics as host component, since thermosetting plastics do not have a liquefying temperature after the softening phase, but rather decompose. Consequently, the packaging temperature remains significantly below this critical decomposition temperature for thermosetting plastics. In the case of thermoplastics, this temperature is not known since thermoplastics undergo transition to a liquid state of matter after the softening temperature range. The mixing of host component and incorporated component prior to heating for packaging a semiconductor chip on a carrier substrate is in one example carried out in the solid state of the two components. For this purpose, at least the incorporated component is put into a powder form having an average grain diameter of less than 10 μm. This is associated with the advantage that it is possible to achieve a relatively uniform distribution of the incorporated component in the powder of the host component. In a further form of implementation of the invention, a memory device having a central bonding channel is produced in concrete terms. For this purpose, firstly a semiconductor chip including memory cells is applied to the carrier substrate. A double-sided adhesive film that leaves free the central bonding channel of the semiconductor chip is used during this application. The semiconductor chip is applied by its active top side to the carrier substrate with alignment of its contact areas in the central bonding channel. This is followed by the production of the contact areas of the semiconductor chip in the bonding channel with a wiring structure of the carrier substrate. Finally, the central bonding channel is filled with a plastic composition having at least the host component. The rear side and the edge sides of the semiconductor chip are then embedded in a plastic housing composed of at least two mixture components, the host component and an incorporated component, as described above. With a semiconductor device of this type, on account of the properties of the incorporated component, the housing can be kept for a limited time duration at a constant temperature as the heat loss of the semiconductor chip rises. Furthermore, with this device, the encapsulating plastic housing composition is in close contact with the semiconductor chip material, with the result that an intensive heat transfer to the heat-storing plastic housing composition is possible. With this semiconductor device, a constant housing temperature can be achieved without any metallic heat sink. Rather, the heat sink is formed by the plastic housing material itself, because the incorporated component can take up heat loss and converts the latter into phase change heat such as heat of fusion or heat of crystallization. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. FIG. 1 illustrates a schematic cross section through a semiconductor device in accordance with one embodiment of the invention. FIG. 2 illustrates a schematic temperature diagram of a housing of a semiconductor device in accordance with FIG. 1 as a function of time with increasing heat loss in the semi-conductor chip of the semiconductor device. DETAILED DESCRIPTION In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. FIG. 1 shows a schematic cross section through a semiconductor device 1 in accordance with one embodiment of the invention. The semiconductor device 1 has a semiconductor chip 4, which is fixed by its active top side 13 on a carrier substrate 9 by means of a double-sided adhesive film 11. The semiconductor chip 4 is embedded with its rear side 17 and its edge sides 18 and 19 in a plastic housing composition 3. Said plastic housing composition 3 forms a housing 2 which, on account of the particular material choice for the plastic housing composition 3, with the heat loss of the semiconductor chip 4 increasing, takes up and stores said heat loss without the housing temperature increasing. For this purpose, the plastic housing composition 3 includes at least one host component 5, which is amorphous plastic having a softening temperature range if said host component 5 is heated above the softening point or the softening temperature. The plastic housing composition 3 furthermore has the incorporated component 6 including a plastic or a salt, the incorporated component 6 being present in the manner finely distributed in the volume of the host component 5. Said incorporated component 6 may be arranged in microbubbles 22, the dimensions of which may be a few micrometers, the material of the incorporated component 6 not completely filling the microbubbles 7 as long as the incorporated material is in the solid state or in the amorphous state. The microbubbles 7 ensure that there is enough space for a phase transition of the incorporated component 6 from an amorphous to a crystalline structure or from a solid to a liquid phase, so that this phase can expand in the microbubbles 7 without bursting the plastic housing composition or producing microcracks. The behavior of the incorporated component 6 in interaction with the semiconductor device housing 2 is examined in detail below in the discussion of FIG. 2. The plastic housing composition also covers a top side 23 of the carrier substrate 9 alongside the semiconductor chip 4 provided that said top side 23 is taken up neither by the double-sided adhesive film 11 nor by the semiconductor chip 4. The underside 24 of the carrier substrate 9 simultaneously forms the underside of the semiconductor device 1 and has external contacts 12 in the form of solder balls. Said external contacts 12 are arranged on external contact areas 20 left free of a soldering resist layer in order to position the solder balls on the external contact areas 20 in delimited fashion. The soldering resist layer 21 simultaneously covers a wiring structure 15 that connects the external contact areas 20 by means of electrical connections 10 in the form of bonding wires 25 through the central bonding channel 8 to corresponding contact areas 14 of the active top side 13 of the semiconductor chip 4. The central bonding channel 8 is covered by a further plastic composition 16, which protects the bonding wires 25 against mechanical damage. Said plastic composition 16 has at least the host component 5 of the plastic housing composition 3. The thermal behavior of this semiconductor device is influenced by the plastic housing composition 3. This influence can be seen in the following FIG. 2. FIG. 2 shows a schematic temperature diagram of a housing of a semiconductor device in accordance with FIG. 1 as a function of time t in minutes (min) with increasing heat loss in the semiconductor chip of the semiconductor device that can be seen in FIG. 1. As the heat loss increases, the temperature T in ° C. of the plastic housing of the semiconductor device rises until the time t1. The phase change of the incorporated component subsequently commences in this example of the diagram of FIG. 2 at Ts of 85° C. and keeps the temperature Ts of the plastic housing constant until the phase change or phase transformation of the incorporated component from an amorphous to a crystalline state or from a solid state to a melted state has concluded at the instant t2. If there is then a decrease in the heat loss on account of the operation of the semiconductor device in the semiconductor chip, the storage capability of the plastic housing composition can be reestablished by heat of fusion or heat of crystallization then being emitted to the plastic housing composition, so that if in the event of an increase in the heat loss, the housing temperature can again be stabilized by being kept constant for a limited time from t1 to t2. With this interrelationship between heat loss generation in phases of high operational performance of the semiconductor device and diminishing heat loss in the case of lower operational deployment of the semiconductor device, what can thus be achieved is that the plastic housing does not exceed the critical constant temperature of 85° C. It is only when the power loss increases further that the temperature can rise further after reaching the instant t2 and lead to the destruction of the semiconductor device in the extreme case. The plastic housing composition thus acts like a heat accumulator and can therefore replace heat sinks made of metal, so that, on the one hand, the weight of the semiconductor devices in use decreases and, on the other hand, possible forced cooling of the device by convection can be dispensed with. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.	H	67H01	185H01L	23	14
11795251	US20080122052A1-20080529	Member for Semiconductor Device and Production Method Thereof	ACCEPTED	20080514	20080529	[]	H01L2314	["H01L2314", "C22C105", "B22F314", "B22F704"]	7749430	20070713	20100706	419	026000	69222.0	CHU	CHRIS	[{"inventor_name_last": "Fukui", "inventor_name_first": "Akira", "inventor_city": "Toyama", "inventor_state": "", "inventor_country": "JP"}]	A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with solder, and a production method thereof are provided. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10−6/K to 15×10−6/K inclusive, and heat conductivity at 100° C. of more than or equal to 180 W/m·K, has: a base material (11) formed of an aluminum-silicon carbide composite material starting from powder material in which particulate silicon carbide is dispersed in aluminum or aluminum alloy, and the content of the silicon carbide is from 30% by mass to 85% by mass inclusive; and a superficial layer (12) containing aluminum or aluminum alloy starting from a melt material bonded on top and bottom faces of the base material (11).	1. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10−6/K to 15×10−6/K inclusive, and heat conductivity at 100° C. of more than or equal to 180 W/m·K, comprising: a base material (11) formed of an aluminum-silicon carbide composite material starting from powder material in which particulate silicon carbide is dispersed in aluminum or aluminum alloy, and the content of the silicon carbide is from 30% by mass to 85% by mass inclusive, the base material having a first surface, and a second surface which is opposite face of the first surface; and a superficial layer (12) containing aluminum or aluminum alloy starting from a melt material bonded on the first surface and the second surface of the base material (11). 2. The member for a semiconductor device (1) according to claim 1, wherein the bonding strength between the base material (11) and the superficial layer (12) is more than or equal to (2×9.8) MPa. 3. The member for a semiconductor device (1) according to claim 1, wherein the base material (11) and the superficial layer (12) are bonded by a metal bond in at least a part of interface. 4. The member for a semiconductor device (1) according to claim 1, wherein the average thickness of superficial layer (12) is from 2% to 30% inclusive, of the average thickness of the member for a semiconductor device (1). 5. The member for a semiconductor device (1) according to claim 1, wherein the variation in the thickness of the superficial layer (12) is within ±30% of the average thickness of the superficial layer (12). 6. The member for a semiconductor device (1) according to claim 1, wherein the superficial layer (12) contains a recrystallized structure of aluminum or aluminum alloy. 7. The member for a semiconductor device (1) according to claim 1, wherein the aluminum alloy of the superficial layer (12) contains at least one element selected from the group consisting of magnesium, silicon, titanium, copper, zinc, manganese, chromium, iron and nickel, and the total content of the elements is from 0.005% by mass to 15% by mass inclusive. 8. The member for a semiconductor device (1) according to claim 1, wherein the purity of the aluminum in the superficial layer (12) is more than or equal to 99%. 9. The member for a semiconductor device (1) according to claim 1, wherein the hardness of the superficial layer (12) is from 25 to 185 inclusive by Vickers hardness. 10. The member for a semiconductor device (1) according to claim 1, wherein the average particle diameter of particles of the silicon carbide is from 10 μm to 150 μm inclusive. 11. The member for a semiconductor device (1) according to claim 1, further comprising a plating layer formed on an outer face. 12. The member for a semiconductor device (1) according to claim 11, wherein the plating layer contains at least one element selected from the group consisting of nickel, copper, silver and gold, and has a thickness ranging from 0.1 μm to 10 μm inclusive. 13. The member for a semiconductor device (1) according to claim 11, wherein the plating layer has a surface roughness of less than or equal to 2 μm by Ra. 14. The member for a semiconductor device (1) according to claim 1, wherein when the length of a long side of the member for a semiconductor device is X mm, and the warp is Y mm, the value of (Y/X) is less than or equal to 0.2%. 15. A method of producing a member for a semiconductor device (1) comprising the steps of preparing mixed powder by mixing powder of aluminum or aluminum alloy and powder of silicon carbide so that the content of the silicon carbide is from 30% by mass to 85% by mass inclusive; obtaining a molded body by molding while placing the mixed powder between first and second melt materials of aluminum or aluminum alloy; and compressing the molded body by heating the molded body to a temperature of (Tm-100)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt materials is denoted by Tm° C. 16. The method of producing a member for a semiconductor device (1) according to claim 15, wherein the average thickness of the first and second melt materials is from 0.1 mm to 2.0 mm inclusive. 17. The method of producing a member for a semiconductor device (1) according to claim 15, wherein the molding pressure in the step of obtaining a molded body is more than or equal to (2×98) MPa. 18. The method of producing a member for a semiconductor device (1) according to claim 15, further comprising, between the step of obtaining a molded body and the step of compressing, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of aluminum or aluminum alloy is denoted by Tm° C. 19. The method of producing a member for a semiconductor device (1) according to claim 15, wherein the step of compressing is conducted in non-oxidizing atmosphere. 20. A method of producing a member for a semiconductor device (1) comprising the steps of: preparing mixed powder by mixing powder of aluminum or aluminum alloy and powder of silicon carbide so that the content of silicon carbide is from 30% by mass to 85% by mass inclusive; obtaining a molded body by molding while placing the mixed powder between first and second melt materials of aluminum or aluminum alloy; and heating and rolling the molded body at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of aluminum or aluminum alloy is denoted by Tm° C. 21. The method of producing a member for a semiconductor device (1) according to claim 20, wherein the average thickness of the first and second melt materials is from 0.1 mm to 2.0 mm inclusive. 22. The method of producing a member for a semiconductor device (1) according to claim 20, wherein the molding pressure in the step of obtaining a molded body is more than or equal to (2×98) MPa. 23. The method of producing a member for a semiconductor device (1) according to claim 20, further comprising, between the step of obtaining a molded body and the step of heating and rolling, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. 24. The method of producing a member for a semiconductor device (1) according to claim 20, wherein the step of heating and rolling is conducted in non-oxidizing atmosphere.	<SOH> BACKGROUND ART <EOH>For example, in a power device which is a semiconductor device of high performance, for insulation of a silicon (Si) chip serving as a semiconductor integrated circuit device (IC), such a structure is employed that an Si chip is soldered on aluminum nitride (AlN) sintered substrate having copper (Cu) or aluminum (Al) on its surface, and under the AlN sintered substrate; a member for a semiconductor device which is an object of the present invention is soldered; and the member for a semiconductor device is fixed with screw to a radiator formed of aluminum alloy in order to cool the member for a semiconductor device with water. At present, as such a member for a semiconductor device, copper (Cu)-molybdenum (Mo)-based composite alloy is mainly used. However, Mo has problems of high costs and a high specific gravity. To the contrary, an aluminum (Al)-silicon carbide (SiC) composite material can be produced from inexpensive materials such as Al and SiC without causing pollution problems, and its coefficient of thermal expansion can be adjusted in wide range in accordance with an incorporated Si chip, peripheral member and the like, so that it is a light-weight and excellent member for a semiconductor device. However, there still remain several problems in using an Al—SiC composite material as a member for a power device, and an Al—SiC composite material is not regularly adopted except for in certain devices. For example, when an Al—SiC composite material is used as a member for a power device which is one exemplary application of a member for a semiconductor device, the following problems arise. (1) Since a member for a semiconductor device is soldered to other member, it is necessary to plate the surface with, for example, nickel (Ni). For example, when the resultant plating has a defect, a void occurs in solder, which may deteriorate performance and shorten the lifetime of the semiconductor device. Plating on the surface of the Al—SiC composite material faces the problem that porous defects occur in the case of an Al—SiC composite material produced by sintering or self-infiltration, and cracking occurs in SiC in the case of an Al—SiC composite material produced by sintering plus forging, and shedding of SiC particles occurs due to grinding which is a pre treatment in any of these production methods. Therefore, there is a problem that it is impossible to form a plated layer with high quality on the surface of the member for a semiconductor device. (2) With increased performance and decreased size of power device, it becomes more apparent that low heat conductivity at a high temperature of the member for a semiconductor device decreases the performance of the device, and shortens lifetime. For this reason, it is currently requested that heat conductivity at high temperature (100° C.) is more than or equal to 180 W/m·K. Therefore, it is necessary to further increase heat conductivity of Al—SiC composite material at high temperature. (3) It is important for a power converter device which is one kind of power device, to efficiently transfer generated heat at Si chip to a radiator. A member for a semiconductor device is fixed to a radiator of Al alloy with screw, however, since the Al—SiC composite material is fragile, it may break, and breaking occur particularly at the site of screwing, leading device failure. (4) In a power device, heat resistance is decreased by bonding constituting parts or members with solder for improvement of heat radiation property. In recent years, as power devices are used in hybrid EV cars or EV cars, and lighter weight, higher reliability and longer lifetime are demanded. On the other hand, as the environmental problems increase, solder materials tend to be free from lead (Pb). When a solder material having less ductility is bonded with a material having high Young's module, heat stress concentrates the solder part, and breaking may occur, leading the problem of shortening device lifetime. In particular, since a Pb-free solder material is inferior in ductility to the Pb-containing solder material, this problem tends to be further closed up. (5) A member for a semiconductor device is requested to be low in cost. In order to obtain a member for a semiconductor device having the coefficient of thermal expansion which is adjustable in wide range, in particular in the range of 6.5×10 −6 /K to 15×10 −6 /K inclusive, in accordance with the incorporated Si chip, peripheral members and the like, and having high heat conductivity for realizing a high heat radiation property and light weight, various cases using composite materials of aluminum and silicon carbide as described below have been proposed. JP-A 11-310843 publication (Patent document 1) discloses a member for a semiconductor device having excellent heat conductivity which is produced by a method including a step of sintering at temperature between 600° C. and the melting point of Al, inclusive, in non-oxidizing atmosphere, following a powder mixing and molding step, or produced by a so-called hot forging method (atmosphere is preferably non-oxidizing atmosphere, upper limit temperature is 800° C.) including a step of heating under pressure at a temperature of more than or equal to 700° C. (upper limit 900° C.) or a step of heating under pressure after preheating a sintered body at a temperature of more than or equal to 600° C. and pouring it into a dye. In such a member for a semiconductor device, when plating is conducted on the surface, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Further, such a member for a semiconductor device realizes improvement in heat conductivity by being produced through pressuring process at temperature at which liquid phase arises. JP-A 2000-192182 publication (Patent document 2) discloses a silicon carbide-based composite material having excellent heat conductivity despite high porosity, produced by a method including heat treating a molded body in vacuo at temperature less than melting point, starting from a material which is used for a heat radiator substrate of semiconductor device, and sintering at temperature not less than the melting point. When such a material is used for a member for a semiconductor device, voids will occur in solder due to high porosity and plating defects, which may deteriorate the performance of semiconductor device and shorten the lifetime. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Further, such a silicon carbide-based composite material realizes improvement in heat conductivity by being produced through forging at temperature at which liquid phase arises. JP-A 2000-160267 publication (Patent document 3) discloses a silicon carbide-based composite material having excellent heat conductivity, produced by a method of heating a molded body of material used for a radiator substrate of semiconductor device at a temperature of melting point or higher, followed by forging under pressurizing to make a forged body. In such a material, when plating is conducted, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at a part where screwing is conducted and of breaking of solder due to concentration of heat stress. Further, such a silicon carbide-based composite material realizes improvement in heat conductivity by being produced through forging at temperature at which liquid phase arises. JP-A 2004-288912 publication (Patent document 4) discloses a lid-type member for a semiconductor device having high dimension accuracy as a semiconductor heat radiator substrate which is subjected to forging process at a temperature ranging from 650 to 800° C. in atmospheric air after sintering a molded body at a temperature of not more than melting point. In such a member for a semiconductor device, when plating is conducted, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Since it is produced through forging at temperature at which liquid phase arises, a lid-type member for a semiconductor device having excellent dimension accuracy is obtained. Therefore, when a member for a semiconductor device is formed using a composite material of aluminum and silicon carbide disclosed in any one of the above disclosed publications, it is impossible to obtain a member for a semiconductor device capable of solving the problems (1), (3) and (4) while solving the problems (2) and (5), although the above problems (2) and (5) can be solved. By the way, also disclosed is a member for a semiconductor device shown below using a composite material of aluminum and silicon carbide. JP-A 10-335538 publication (Patent document 5) discloses a member for a semiconductor device having improved bonding strength with resin by providing a covering layer based on aluminum on the surface of a composite material of aluminum and silicon carbide produced by sintering, having heat conductivity of more than or equal to 100 W/m·K (or 180 W/m·K or more) and a coefficient of thermal expansion of less than or equal to 20×10 −6 /K. As a concrete technique for improving bonding strength with resin, there is disclosed post application of an Al layer having a thickness ranging from 1 to 100 μm by plating, vapor deposition or screen printing on the surface of an Al—SiC composite material which is rusticated after production of an Al—SiC composite material. However, as disclosed in the above publications, even when the above problems (1), (3) and (4) are attempted to be solved by forming an Al layer afterward on the surface of an Al—SiC composite material, it is difficult to be achieved due to the following reasons. When such a member for a semiconductor device is applied to a member for used in a power device, it is necessary to make heat resistance smaller, and hence it is necessary to realize stronger bonding between an Al—SiC composite material and an Al layer. The bonding strength between an Al layer which is formed afterward by plating, vapor deposition or screen printing, and an Al—SiC composite material is insufficient. Further, when an Al layer formed by plating, vapor deposition or screen printing is a thin film, defects may occur in the Al layer, so that there is a possibility that voids occur in solder when other member is soldered on surface of the Al layer, and problems of deterioration in the performance of semiconductor device, and shortened lifetime occur. Such possibility can be avoided by making the Al layer a thick film, however, this measure leads increase in production cost. Further, this measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. In order to solve the above problems (1), (3) and (4), it can be conceived that sintering or forging is conducted while an Al layer is previously formed on superficial layer of a molded body which is a starting material of an Al—SiC composite material. However, since any of production methods disclosed in the above JP-A 11-310843 (Patent document 1), JP-A 2000-192182 publication (Patent document 2), JP-A 2000-160267 publication (Patent document 3), and JP-A 2004-288912 publication (Patent document 4) is a production method involving sintering or forging at a temperature at which a liquid phase arises, it is impossible to obtain an Al—SiC composite material on which a thick Al layer is strongly bonded on its surface. Patent document 1: Japanese Unexamined Patent Application No. 11-310843 publication Patent document 2: Japanese Unexamined Patent Application No. 2000-192182 publication Patent document 3: Japanese Unexamined Patent Application No. 2000-160267 publication Patent document 4: Japanese Unexamined Patent Application No. 2004-288912 publication Patent document 5: Japanese Unexamined Patent Application No. 10-335538 publication	<SOH> BRIEF DESCRIPTION OF DRAWINGS <EOH>FIG. 1 A cross section view showing a schematic section of a member for a semiconductor device which is one embodiment of the present invention. FIG. 2 A schematic section view showing an insulated gate bipolar transistor (IGBT) unit incorporated into an automobile or the like, which is one example of a power device given as one embodiment of semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. FIG. 3 A schematic section view showing a semiconductor device having a central processing unit (CPU) such as a computer or server or semiconductor integrated circuit element chip of microprocessor unit (MPU), which is one example of another embodiment of the semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. FIG. 4 A schematic section view showing a test method for measuring peel strength of Al layer which is a superficial layer. FIG. 5 A view showing the influence of heating temperature in heating treatment step exerted on a coefficient of thermal expansion and heat conductivity at 100° C. detailed-description description="Detailed Description" end="lead"?	TECHNICAL FIELD The present invention generally relates to a member for a semiconductor device and a production method thereof, and more specifically to a member for a semiconductor device serving as a heat radiator member such as a heat spreader or lid member constituting a semiconductor device, and a production method thereof. BACKGROUND ART For example, in a power device which is a semiconductor device of high performance, for insulation of a silicon (Si) chip serving as a semiconductor integrated circuit device (IC), such a structure is employed that an Si chip is soldered on aluminum nitride (AlN) sintered substrate having copper (Cu) or aluminum (Al) on its surface, and under the AlN sintered substrate; a member for a semiconductor device which is an object of the present invention is soldered; and the member for a semiconductor device is fixed with screw to a radiator formed of aluminum alloy in order to cool the member for a semiconductor device with water. At present, as such a member for a semiconductor device, copper (Cu)-molybdenum (Mo)-based composite alloy is mainly used. However, Mo has problems of high costs and a high specific gravity. To the contrary, an aluminum (Al)-silicon carbide (SiC) composite material can be produced from inexpensive materials such as Al and SiC without causing pollution problems, and its coefficient of thermal expansion can be adjusted in wide range in accordance with an incorporated Si chip, peripheral member and the like, so that it is a light-weight and excellent member for a semiconductor device. However, there still remain several problems in using an Al—SiC composite material as a member for a power device, and an Al—SiC composite material is not regularly adopted except for in certain devices. For example, when an Al—SiC composite material is used as a member for a power device which is one exemplary application of a member for a semiconductor device, the following problems arise. (1) Since a member for a semiconductor device is soldered to other member, it is necessary to plate the surface with, for example, nickel (Ni). For example, when the resultant plating has a defect, a void occurs in solder, which may deteriorate performance and shorten the lifetime of the semiconductor device. Plating on the surface of the Al—SiC composite material faces the problem that porous defects occur in the case of an Al—SiC composite material produced by sintering or self-infiltration, and cracking occurs in SiC in the case of an Al—SiC composite material produced by sintering plus forging, and shedding of SiC particles occurs due to grinding which is a pre treatment in any of these production methods. Therefore, there is a problem that it is impossible to form a plated layer with high quality on the surface of the member for a semiconductor device. (2) With increased performance and decreased size of power device, it becomes more apparent that low heat conductivity at a high temperature of the member for a semiconductor device decreases the performance of the device, and shortens lifetime. For this reason, it is currently requested that heat conductivity at high temperature (100° C.) is more than or equal to 180 W/m·K. Therefore, it is necessary to further increase heat conductivity of Al—SiC composite material at high temperature. (3) It is important for a power converter device which is one kind of power device, to efficiently transfer generated heat at Si chip to a radiator. A member for a semiconductor device is fixed to a radiator of Al alloy with screw, however, since the Al—SiC composite material is fragile, it may break, and breaking occur particularly at the site of screwing, leading device failure. (4) In a power device, heat resistance is decreased by bonding constituting parts or members with solder for improvement of heat radiation property. In recent years, as power devices are used in hybrid EV cars or EV cars, and lighter weight, higher reliability and longer lifetime are demanded. On the other hand, as the environmental problems increase, solder materials tend to be free from lead (Pb). When a solder material having less ductility is bonded with a material having high Young's module, heat stress concentrates the solder part, and breaking may occur, leading the problem of shortening device lifetime. In particular, since a Pb-free solder material is inferior in ductility to the Pb-containing solder material, this problem tends to be further closed up. (5) A member for a semiconductor device is requested to be low in cost. In order to obtain a member for a semiconductor device having the coefficient of thermal expansion which is adjustable in wide range, in particular in the range of 6.5×10−6/K to 15×10−6/K inclusive, in accordance with the incorporated Si chip, peripheral members and the like, and having high heat conductivity for realizing a high heat radiation property and light weight, various cases using composite materials of aluminum and silicon carbide as described below have been proposed. JP-A 11-310843 publication (Patent document 1) discloses a member for a semiconductor device having excellent heat conductivity which is produced by a method including a step of sintering at temperature between 600° C. and the melting point of Al, inclusive, in non-oxidizing atmosphere, following a powder mixing and molding step, or produced by a so-called hot forging method (atmosphere is preferably non-oxidizing atmosphere, upper limit temperature is 800° C.) including a step of heating under pressure at a temperature of more than or equal to 700° C. (upper limit 900° C.) or a step of heating under pressure after preheating a sintered body at a temperature of more than or equal to 600° C. and pouring it into a dye. In such a member for a semiconductor device, when plating is conducted on the surface, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Further, such a member for a semiconductor device realizes improvement in heat conductivity by being produced through pressuring process at temperature at which liquid phase arises. JP-A 2000-192182 publication (Patent document 2) discloses a silicon carbide-based composite material having excellent heat conductivity despite high porosity, produced by a method including heat treating a molded body in vacuo at temperature less than melting point, starting from a material which is used for a heat radiator substrate of semiconductor device, and sintering at temperature not less than the melting point. When such a material is used for a member for a semiconductor device, voids will occur in solder due to high porosity and plating defects, which may deteriorate the performance of semiconductor device and shorten the lifetime. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Further, such a silicon carbide-based composite material realizes improvement in heat conductivity by being produced through forging at temperature at which liquid phase arises. JP-A 2000-160267 publication (Patent document 3) discloses a silicon carbide-based composite material having excellent heat conductivity, produced by a method of heating a molded body of material used for a radiator substrate of semiconductor device at a temperature of melting point or higher, followed by forging under pressurizing to make a forged body. In such a material, when plating is conducted, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at a part where screwing is conducted and of breaking of solder due to concentration of heat stress. Further, such a silicon carbide-based composite material realizes improvement in heat conductivity by being produced through forging at temperature at which liquid phase arises. JP-A 2004-288912 publication (Patent document 4) discloses a lid-type member for a semiconductor device having high dimension accuracy as a semiconductor heat radiator substrate which is subjected to forging process at a temperature ranging from 650 to 800° C. in atmospheric air after sintering a molded body at a temperature of not more than melting point. In such a member for a semiconductor device, when plating is conducted, it is impossible to prevent plating defects caused by shedding of SiC, porous defects, cracking of SiC and the like, so that voids occur in solder, and the performance of semiconductor device may decrease and lifetime may be shortened. Further, such a measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. Since it is produced through forging at temperature at which liquid phase arises, a lid-type member for a semiconductor device having excellent dimension accuracy is obtained. Therefore, when a member for a semiconductor device is formed using a composite material of aluminum and silicon carbide disclosed in any one of the above disclosed publications, it is impossible to obtain a member for a semiconductor device capable of solving the problems (1), (3) and (4) while solving the problems (2) and (5), although the above problems (2) and (5) can be solved. By the way, also disclosed is a member for a semiconductor device shown below using a composite material of aluminum and silicon carbide. JP-A 10-335538 publication (Patent document 5) discloses a member for a semiconductor device having improved bonding strength with resin by providing a covering layer based on aluminum on the surface of a composite material of aluminum and silicon carbide produced by sintering, having heat conductivity of more than or equal to 100 W/m·K (or 180 W/m·K or more) and a coefficient of thermal expansion of less than or equal to 20×10−6/K. As a concrete technique for improving bonding strength with resin, there is disclosed post application of an Al layer having a thickness ranging from 1 to 100 μm by plating, vapor deposition or screen printing on the surface of an Al—SiC composite material which is rusticated after production of an Al—SiC composite material. However, as disclosed in the above publications, even when the above problems (1), (3) and (4) are attempted to be solved by forming an Al layer afterward on the surface of an Al—SiC composite material, it is difficult to be achieved due to the following reasons. When such a member for a semiconductor device is applied to a member for used in a power device, it is necessary to make heat resistance smaller, and hence it is necessary to realize stronger bonding between an Al—SiC composite material and an Al layer. The bonding strength between an Al layer which is formed afterward by plating, vapor deposition or screen printing, and an Al—SiC composite material is insufficient. Further, when an Al layer formed by plating, vapor deposition or screen printing is a thin film, defects may occur in the Al layer, so that there is a possibility that voids occur in solder when other member is soldered on surface of the Al layer, and problems of deterioration in the performance of semiconductor device, and shortened lifetime occur. Such possibility can be avoided by making the Al layer a thick film, however, this measure leads increase in production cost. Further, this measure is insufficient for solving the problems of breaking at the site of screwing and of breaking of solder due to concentration of heat stress. In order to solve the above problems (1), (3) and (4), it can be conceived that sintering or forging is conducted while an Al layer is previously formed on superficial layer of a molded body which is a starting material of an Al—SiC composite material. However, since any of production methods disclosed in the above JP-A 11-310843 (Patent document 1), JP-A 2000-192182 publication (Patent document 2), JP-A 2000-160267 publication (Patent document 3), and JP-A 2004-288912 publication (Patent document 4) is a production method involving sintering or forging at a temperature at which a liquid phase arises, it is impossible to obtain an Al—SiC composite material on which a thick Al layer is strongly bonded on its surface. Patent document 1: Japanese Unexamined Patent Application No. 11-310843 publication Patent document 2: Japanese Unexamined Patent Application No. 2000-192182 publication Patent document 3: Japanese Unexamined Patent Application No. 2000-160267 publication Patent document 4: Japanese Unexamined Patent Application No. 2004-288912 publication Patent document 5: Japanese Unexamined Patent Application No. 10-335538 publication DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, conventional arts have not proposed a material satisfying all of the following required characteristics as a member for a semiconductor device. i) A surface of a member for a semiconductor device is plated for soldering to other member. When there is a defect in this plating, for example, voids occur in solder, which may lead deterioration in the performance of semiconductor device and shortening in lifetime. Therefore, a plating layer of high quality without defects on surface of member for a semiconductor device is requested. ii) With increased performance and downsizing of a power device, it is necessary that heat conductivity at high temperature of member for a semiconductor device is excellent. Therefore, for example, heat conductivity of member for a semiconductor device at high temperature (100° C.) should be more than or equal to 180 W/m·K. iii) Since in a power converter device it is important to efficiently transfer generated heat at Si chip to a radiator, a member for a semiconductor device is fixed to a radiator of Al alloy with screw. Therefore, the member for a semiconductor device should have toughness of such toughness will not cause breaking screwing and the like. iv) In a power device, parts are bonded with solder to decrease heat resistance and improve heat radiation property. Therefore, solder breaking should not occur due to heat stress even when the member for a semiconductor device is bonded to other member with solder. v) Not only the raw material cost of the member for a semiconductor device, but also production cost should be low and the price of product should be low. In view of the above, it is an object of the present invention to provide a member for a semiconductor device capable of satisfying all of the above characteristic requirements, and more specifically, to provide a member for a semiconductor device and production method thereof of low price, capable of forming high quality plating layer on surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with solder. Means for Solving the Problems The member for a semiconductor device according to the present invention is a member for a semiconductor device having a coefficient of thermal expansion ranging from 6.5×10−6/K to 15×10−6/K inclusive, and heat conductivity at 100° C. of more than or equal to 180 W/m·K, and has a base material and a superficial layer. The base material is formed of an aluminum-silicon carbide composite material starting from a powder material in which particulate silicon carbide is dispersed in aluminum or aluminum alloy, and the content of the silicon carbide is from 30% by mass to 85% by mass inclusive, and has a first surface, and a second surface which is opposite face of the first surface. The superficial layer contains aluminum or aluminum alloy starting from a melt material bonded on the first surface and the second surface. The term “powder material” used herein refers to a material in powder condition or in the form of particles. The term “melt material” used herein refers to a bulky material solidified from melt condition, and implies materials having subjected to plasticizing process such as rolling after solidification. In the member for a semiconductor device according to the present invention, on the first surface and the second surface which are outer surfaces of the base material formed of an aluminum-silicon carbide composite material, a superficial layer containing aluminum or aluminum alloy and having excellent toughness can be bonded thickly without defects. In the member for a semiconductor device according to the present invention, it is preferable that bonding strength between a base material and a superficial layer is more than or equal to 2×9.8 MPa. In the member for a semiconductor device according to the present invention, it is preferable that the base material and the superficial layer are bonded by a metal bond in at least a part of the interface. Further, in the member for a semiconductor device according to the present invention, it is preferable that the average thickness of superficial layer is from 2% to 30% inclusive, of the average thickness of the member for a semiconductor device. In the member for a semiconductor device according to the present invention, it is preferable that variation in thickness of superficial layer is within ±30% of the average thickness of the superficial layer. In the member for a semiconductor device according to the present invention, it is preferable that the superficial layer contains a recrystallized structure of aluminum or aluminum alloy. In the member for a semiconductor device according to the present invention, it is preferable that aluminum alloy of the superficial layer contains at least one element selected from the group consisting of magnesium (Mg), silicon (Si), titanium (Ti), copper (Cu), zinc (Zn), manganese (Mn), chromium (Cr), iron (Fe) and nickel (Ni), and the total content of the elements is from 0.005% by mass to 15% by mass inclusive. In the member for a semiconductor device according to the present invention, the purity of aluminum in the superficial layer may be more than or equal to 99%. In the member for a semiconductor device according to the present invention, it is preferable that hardness of superficial layer is from 25 to 185 inclusive by Vickers hardness. In the member for a semiconductor device according to the present invention, it is preferable that the average particle diameter of particles of silicon carbide is from 10 μm to 150 μm inclusive. Preferably, the member for a semiconductor device according to the present invention further includes a plating layer formed on the outer face. In this case, it is preferred that the plating layer contains at least one element selected from the group consisting of nickel (Ni), copper (Cu), silver (Ag) and gold (Au), and the thickness is from 0.1 μm to 10 μm inclusive. Preferably, the surface roughness of the plating layer is less than or equal to 2 μm by Ra. In the member for a semiconductor device according to the present invention, it is preferable that when the length of the long side of the member for a semiconductor device is X mm, and the warp is Y mm, the value of (Y/X) is less than or equal to 0.2%. A method of producing a member for a semiconductor device according to one aspect of the present invention includes the following steps. a) a step of preparing mixed powder by mixing powder of aluminum or aluminum alloy and powder of silicon carbide so that content of silicon carbide is from 30% by mass to 85% by mass inclusive. b) a step of obtaining a molded body by conducting molding while placing mixed powder between first and second melt materials of aluminum or aluminum alloy. c) a step of compressing a molded body by heating it to a temperature of (Tm-100)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of melt material is denoted by Tm° C. According to the method of producing a member for a semiconductor device in one aspect of the present invention, it is possible to bond a superficial layer containing aluminum or aluminum alloy and having excellent toughness on a first surface and second surface of the aluminum-silicon carbide composite material in a thick manner without occurrence of defects. In the method of producing a member for a semiconductor device according to the present invention, it is preferred that average thickness of the first and second melt materials is from 0.1 mm to 2.0 mm inclusive. In the method of producing a member for a semiconductor device according to the present invention, it is preferred that molding pressure in the step of obtaining a molded body is more than or equal to (2×98) MPa. Preferably, the method of producing a member for a semiconductor device according to the present invention further includes between the step of obtaining a molded body and the step of compressing, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and less than Tm° C. when the melting point or solidus temperature of melt material is denoted by Tm° C. The value of Tm is 660° C. in the case of aluminum, and 577° C. in the case of aluminum −9% by mass silicon alloy as one example of aluminum alloy. In the method of producing a member for a semiconductor device according to the present invention, it is preferable that the heating and compressing step is conducted in non-oxidizing atmosphere. A method of producing member for a semiconductor device according to another aspect of the present invention includes the following steps. a) a step of preparing mixed powder by mixing powder of aluminum or aluminum alloy and powder of silicon carbide so that the content of silicon carbide is from 30% by mass to 85% by mass inclusive. b) a step of obtaining a molded body by conducting molding while placing mixed powder between first and second melt materials of aluminum or aluminum alloy. d) a step of rolling while heating a molded body to a temperature of (Tm-300)° C. or higher and lower than Tm° C., when melting point or solidus temperature of melt material is denoted by Tm° C. According to the method of producing a member for a semiconductor device according to another aspect of the present invention, it is possible to bond a superficial layer containing aluminum or aluminum alloy and having excellent toughness on a first surface and second surface of the aluminum-silicon carbide composite material in a thick manner without occurrence of defects. In the method of producing a member for a semiconductor device according to one aspect of the present invention, it is preferred that average thickness of the first and second melt materials is from 0.1 mm to 2.0 mm. According to the method of producing a member for a semiconductor device according to another aspect of the present invention, it is preferred that the molding pressure in the step of obtaining a molded body is more than or equal to (2×98) MPa. Preferably, the method of producing a member for a semiconductor device according to another aspect of the present invention further includes between the step of obtaining a molded body and the step of heating and rolling, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and less than Tm° C. when melting point or solidus temperature of melt material is denoted by Tm° C. In the method of producing a member for a semiconductor device according to another aspect of the present invention, it is preferable that the step of heating and rolling is conducted in non-oxidizing atmosphere. EFFECT OF THE INVENTION As described above, in accordance with the present invention, since it is possible to bond a superficial layer containing aluminum or aluminum alloy and having excellent toughness on the first surface and second surface which are outer faces of the base material formed of an aluminum-silicon carbide composite material in a thick manner without occurrence of defects, it is possible to form a plating layer of high quality on the surface, and hence it is possible to obtain a member for a semiconductor device of low price capable of forming high quality plating layer on surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when it is bonded to other member with a solder. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 A cross section view showing a schematic section of a member for a semiconductor device which is one embodiment of the present invention. FIG. 2 A schematic section view showing an insulated gate bipolar transistor (IGBT) unit incorporated into an automobile or the like, which is one example of a power device given as one embodiment of semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. FIG. 3 A schematic section view showing a semiconductor device having a central processing unit (CPU) such as a computer or server or semiconductor integrated circuit element chip of microprocessor unit (MPU), which is one example of another embodiment of the semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. FIG. 4 A schematic section view showing a test method for measuring peel strength of Al layer which is a superficial layer. FIG. 5 A view showing the influence of heating temperature in heating treatment step exerted on a coefficient of thermal expansion and heat conductivity at 100° C. EXPLANATION OF REFERENCE NUMERAL 1: member for a semiconductor device, 11: base material, 12: superficial layer DETAILED DESCRIPTION OF THE INVENTION Inventors of the present invention made diligent efforts for achieving a member for a semiconductor device satisfying all of the five required characteristics as described above and a production method thereof, and accomplished the present invention. As to a member for a semiconductor device, it is possible to obtain a material having bonding strength between aluminum-silicon carbide composite material and aluminum or aluminum alloy layer of more than or equal to 2 kgf/mm2 (2×9.8 MPa) and a coefficient of thermal expansion ranging from 6.5×10−6/K to 15×10−6/K inclusive and heat conductivity at 100° C. of more than or equal to 180 W/m·K, by forming a layer of aluminum or aluminum alloy starting from a melt material as a superficial layer on top and bottom faces of an aluminum-silicon carbide composite material starting from a powder material in which 30 to 85% by mass of particulate silicon carbide is dispersed in aluminum or aluminum alloy serving as a base material, and it was found that the resultant material satisfied all the required characteristics. FIG. 1 is a cross section view showing a schematic section of a member for a semiconductor device which is one embodiment of the present invention. As shown in FIG. 1, a member for a semiconductor device 1 includes a base material 11 formed of an aluminum-silicon carbide composite material, and superficial layers 12 containing aluminum or aluminum alloy bonded onto a first and second surface which is an opposite face of the first surface, namely onto the top and bottom faces, of the base material 11. FIG. 2 is a schematic section view showing an insulated gate bipolar transistor (IGBT) unit incorporated into an automobile or the like, which is one example of power device given as one embodiment of semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. As shown in FIG. 2, the member for a semiconductor device 1 of the present invention is fixed, as a heat radiation substrate (heat spreader material), to an aluminum or aluminum alloy substrate 2 forming a radiator with a screw 3 after a plating layer is formed on its surface. On the other hand, an insulation layer 4 realized by an aluminum nitride (AIN) sintered body formed on its top and bottom faces with copper or aluminum layer 5 is fixed via a solder layer 6 on top face of the member for a semiconductor device 1 on which plating layer is formed. On the insulation layer 5 formed on its top face with the copper or aluminum layer 5, an Si chip 7, or in the present case, a semiconductor integrated circuit element chip including an insulated gate bipolar transistor is incorporated while being fixed via a solder layer 6. By making up the power device in the manner as described above, heat generating from the Si chip 7 is conducted and radiated to the member for a semiconductor device 1 of the present invention serving as a heat radiation substrate via the copper or aluminum layer 5, the insulation layer 4 formed of aluminum nitride (AIN) sintered body, and the copper or aluminum layer 5, having respectively high heat conductivity, and absorbed into the aluminum or aluminum alloy substrate 2 which is a constituent of a water-cooled radiator. At this time, in the member for a semiconductor device 1 of the present invention, since it is possible to bond a superficial layer 12 (FIG. 1) containing aluminum or aluminum alloy and having excellent toughness thickly without occurrence of defects, it is possible to form a plating layer of high quality on the surface, and heat conductivity at high temperature (100° C.) is more than or equal to 180 W/m·K, and toughness of such a degree that will not cause breaking, for example, by screwing with the screw 3 is realized, and solder breaking due to heat stress will not occur when bonding to an insulation layer 4 formed of nitride aluminum (AIN) sintered body is realized with the solder layer 6. FIG. 3 is a schematic section view showing a semiconductor device having a central processing unit (CPU) such as computer or server or semiconductor integrated circuit element chip of microprocessor unit (MPU), which is one example of another embodiment of the semiconductor device to which the member for a semiconductor device shown in FIG. 1 is applied. As shown in FIG. 3, a solder ball 9 is used for electric bonding between a semiconductor integrated circuit element chip and a package (ball grid array (BGA) system). The Si chip 7 of CPU or MPU is fixed, via the solder layer 6, to a ceramic substrate in which a plurality of solder balls 9 are arranged as wiring terminus for conduction between top and bottom faces. On the top face of the Si chip 7, the member for a semiconductor device 1 of the present invention serving as a lid member having a plating layer on its surface is fixed via the solder layer 6. Peripheral parts of the member for a semiconductor device 1 are arranged to surround the Si chip 7, and fixed onto the ceramic substrate 8 with resin or the like. By making up the semiconductor device in this manner, heat generating from the Si chip 7 is conducted to the member for a semiconductor device 1 of the present invention serving as a heat radiation substrate and radiated. At this time, in the member for a semiconductor device 1 of the present invention, since the superficial layer 12 (FIG. 1) containing aluminum or aluminum alloy and having excellent toughness can be bonded thickly without occurrence of defects, a plating layer of high quality can be formed on the surface, and heat conductivity at high temperature (100° C.) is more than or equal to 180 W/m·K, and solder breaking due to heat stress will not occur when bonding to the Si chip 7 is realized with the solder layer 6. In the aluminum-silicon carbide composite material serving as a base material constituting the member for a semiconductor device of the present invention, an amount of silicon carbide particles is set at 30 to 85% by mass because an amount less than 30% by mass will result in a large coefficient of thermal expansion and an amount of more than 85% by mass will make condensation difficult. By forming an aluminum or aluminum alloy layer on top and bottom faces of an aluminum-silicon carbide composite material, it becomes possible to form a plating layer of high quality on the outer surface, and excellent soldering characteristic is realized. The bonding strength between an aluminum-silicon carbide composite material and aluminum or aluminum alloy layer is set at more than or equal to 2 kgf/mm2 (2×9.8 MPa) because the bonding strength of less than 2 kgf/mm2 will not only cause deterioration of heat conductivity in the entire member for a semiconductor device but also cause decrease in toughness which is required in screwing, and reduce the effect of preventing breaking of solder due to heat stress. The bonding strength is preferably more than or equal to 3 kgf/mm2 (3×9.8 MPa), and more preferably more than or equal to 5 kgf/mm2 (5×9.8 MPa). The bonding strength is preferably lower than tensile strength of aluminum or aluminum alloy layer, for example, less than or equal to 10 kgf/mm2 (10×9.8 MPa) which is tensile strength of a general aluminum flexible material. A coefficient of thermal expansion is set within the range from 6.5×10−6/K to 15×10−6/K inclusive because the coefficient of thermal expansion can be adjusted in wide range in accordance with an incorporated Si chip, peripheral member and the like as a member for a powder device. Further, heat conductivity at 100° C. is set at more than or equal to 180 W/m·K because heat conductivity less than 180 W/m·K will result in the low heat conductivity of member for a semiconductor device, and the lower performance of semiconductor device and shorten lifetime. Inventors or the present invention found that when an aluminum-silicon carbide composite material and an aluminum or aluminum alloy layer are bonded via a metal bond in a part of interface therebetween, it is possible to improve toughness and heat conductivity of the member for a semiconductor device, and to prevent concentration of heat stress of solder. Whether they are bonded via a metal bond can be determined by observation of lattice image of interface under a transmission electron microscope. The average thickness of aluminum or aluminum alloy layer as a superficial layer is preferably from 2% to 30% inclusive, of the average thickness of the member for a semiconductor device. The average thickness of aluminum or aluminum alloy layer is set within the range from 2% to 30% inclusive, of the average thickness of the member for a semiconductor device because if it is less than 2% of the average thickness of member for a semiconductor device, toughness and alleviating effect of heat stress concentration of solder are insufficient, and if it is more than 30%, a coefficient of thermal expansion becomes too large. Inventors of the present invention also found that allowable variation in thickness of aluminum or aluminum alloy layer as a superficial layer is within ±30% of the average thickness of aluminum or aluminum alloy layer. Allowable variation is within ±30% of the average thickness of aluminum or aluminum alloy layer because sufficient toughness will not be obtained and fluctuations in heat conductivity and in characteristic of the coefficient of thermal expansion increase when the variation exceeds ±30%. The crystal structure of aluminum or aluminum alloy in the crystal superficial layer is more preferably recrystallized structure. When the superficial layer contains recrystallized structure, toughness is further improved, and concentration of heat stress of solder can be further alleviated. The average crystal particle diameter is preferably from 1 μm to 500 μm inclusive, and more preferably from 20 μm to 200 μm inclusive. Any aluminum alloy is applicable insofar as aluminum alloy of superficial layer contains at least one element selected from the group consisting of Mg, Si, Ti, Cu, Zn, Mn, Cr, Fe and Ni, and the content of the total elements is from 0.005% by mass to 15% by mass inclusive. For example, when a higher strength is required for the superficial layer, aluminum may be alloyed for controlling the crystal particle diameter. In such a case, it is preferred to add at least one element selected from the group consisting of Mg, Si, Ti, Cu, Zn, Mn, Cr, Fe and Ni, and an adding amount is set in the range from 0.005% by mass to 15% by mass inclusive because the effect of addition is not obtained in an amount of less than 0.005%, and the effect will saturate in an amount exceeding 15% by mass. When higher heat conductivity is requested by the member for a semiconductor device, it is preferred that purity of aluminum in the superficial layer is more than or equal to 99%. Purity is set at more than or equal to 99% because purity of less than 99% has less effect of improving the heat conductivity. More preferably, purity of aluminum is more than or equal to 99.5%. Preferably, the hardness of aluminum or aluminum alloy of the superficial layer is from 25 to 185 inclusive by Vickers hardness. The hardness is set in the range from 25 to 185 inclusive by Vickers hardness because the Vickers harness of less than 25 makes fastening by screwing difficult, and the Vickers hardness exceeding 185 will result in decrease in toughness and decrease the effect of alleviating concentration of heat stress. The Vickers hardness of aluminum or aluminum alloy of the superficial layer is more preferably from 30 to 120 inclusive, and more preferably from 30 to 70 inclusive. When the member for a semiconductor device of the present invention has excellent toughness, further advantages can be obtained such that breaking will not occur by screwing or the like, and the effect of alleviating concentration of heat stress at a soldered part increases. As an evaluation method of such toughness, the following methods can be exemplified. (A) Drilling a through hole in the surface of member for a semiconductor device by means of super-hard alloy drill of 12 mm in diameter while applying cutting oil thereon. A bolt of M10 is inserted into the resultant through-hole and a nut is screwed via a washer with a torque of 10 kgf·m (98 N·m). At this time, superficial layer should not peel and cracking should not occur around the hole. (B) Punching a hole of 12 mm in diameter in the member for a semiconductor device using 100 ton press. At this time, superficial layer should not peel and cracking should not occur around the hole. (C) Conducting three-point bending test on the member for a semiconductor device. At this time, the superficial layer should not peel and displacement of bending should be larger than that of a comparative material. (D) When tensile test is conducted, m value of Weibull distribution of tensile strength should be more than or equal to 5, and more desirably more than or equal to 15. In the member for a semiconductor device of the present invention, the average particle diameter of silicon carbide particles in the aluminum-silicon carbide composite material is preferably from 10 μm to 150 μm inclusive. The average particle diameter is set within the range from 10 μm to 150 μm inclusive because it is difficult to bond the aluminum or aluminum alloy layer to aluminum-silicon carbide composite material with good adhesivity with particle diameters of larger than 10 μm and smaller than 150 μm. Further, inventors of the present invention found that a member for a semiconductor device having a plating layer on its outer face in order to improve the solderability of the member for a semiconductor device provided with an aluminum or aluminum alloy layer on top and bottom faces of the aluminum-silicon carbide composite material satisfies all of the characteristics requested for a member for a semiconductor device for power device. In particular, it is preferred to apply plating having thickness ranging from 0.1 μm to 10 μm inclusive and containing at least one element selected the group consisting of Ni, Cu, Ag and Au is applied on the surface. In this case, the thickness of plating is set at 0.1 μm and less than or equal to 10 μm because thickness of less than 0.1 μm is insufficient for improving the solderability, and thickness of more than 10 μm gives adverse influence on solderability. The larger the surface roughness of the plating layer, the poorer the solder wettability, so that the surface roughness is preferably less than or equal to 2 μm by Ra. The lower limit of the surface roughness of the plating layer is, but is not particularly limited, 0.03 μm by Ra in consideration of the surface roughness which is industrially achievable. The surface roughness within the above range of the plating layer is achieved by subjecting a substrate to mechanical grinding, chemical grinding or the like prior to formation of the plating layer. A preferred member for a semiconductor device according to the present invention satisfies value of (Y/X) of less than or equal to 0.2% when the length of the long side of the member for a semiconductor device is X mm, and the warp is Y mm. When the value of (Y/X) exceeds 0.2%, bonding with other member is insufficient and heat resistance tends to increase. As a method of producing a member for a semiconductor device satisfying all of the requested characteristics, inventors of the present invention found that a method of producing a member for a semiconductor device which forms an aluminum or aluminum alloy layer on top and bottom faces of an aluminum-silicon carbide composite material, which includes the steps of preparing mixed powder by mixing powder of aluminum or aluminum alloy and powder of silicon carbide so that content of silicon carbide is from 30% by mass to 85% by mass inclusive; obtaining a molded body by conducting molding while placing mixed powder between first and second melt materials of aluminum or aluminum alloy; and compressing the molded body by heating it to a temperature of (Tm-100)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. is preferred. Further, inventors of the present invention found that by placing an aluminum or aluminum alloy on top and bottom faces in a manufacturing step of molded body to make a molded body, and heating and compressing the molded body at a temperature of (Tm-100)° C. or higher and lower than Tm° C., when the melting point or solidus temperature of melt material is denoted by Tm° C., it is possible to obtain a member for a semiconductor device having excellent adhesiveness, small variation in the thickness of layer, giving no damages such as cracking on silicon carbide particles, having excellent toughness, having desired heat conductivity, causing no breaking in solder due to concentration of heat stress, and causing little warp at low costs. According to the production method of the present invention, although the biaxial compression is employed, a similar effect as is the case of hydrostatic pressing is obtained. Therefore, the characteristics as described above are realized. Further, since the number of steps is small, it is possible to obtain a product having excellent characteristics at low costs. Heating and compressing temperature is set at a temperature of (Tm-100)° C. or higher and lower than Tm° C., when melting point or solidus temperature of melt material is denoted by Tm° C., because at temperature of less than (Tm-100)° C., sufficient adhesiveness, toughness, heat conductivity, and small warp cannot be achieved, and at temperature of Tm° C. or higher there arise the problems of occurrence of seizure in a mold and generation of liquid phase. The average thickness of aluminum or aluminum alloy plate is preferably from 0.1 mm to 2.0 mm inclusive. The average thickness of aluminum or aluminum alloy plate is set within the range from 0.1 mm to 2.0 mm inclusive because damages may be caused on silicon carbide particles at a thickness of less than 0.1 mm, and the effect exerted by forming the aluminum or aluminum alloy layer as a superficial layer is saturated at a thickness of more than 2.0 mm. When molding pressure at the molding step is more than or equal to 2 ton/cm2 (2×98 MPa), it is possible to produce a member for a semiconductor device having more excellent adhesiveness and heat conductivity. Inventors of the present invention found that heat conductivity and toughness of the member for a semiconductor device are further improved when it is produced by a method that further includes between the step of obtaining a molded body and the step of heating and compressing step, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. Inventors also found that heat conductivity and toughness can be further improved by conducting the heating and compressing step in the non-oxidizing atmosphere. The heating and compressing step may be conducted in atmospheric air or in oxidizing atmosphere. As another production method of the present invention, inventors found that a member for a semiconductor device having comparable characteristics and performance can be produced at low costs even when the step of heating and compressing a molded body at a temperature of (Tm-100)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. is replaced by the step of heating and rolling the molded body at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. The heating and rolling temperature is set at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. because sufficient adhesiveness, toughness, heat conductivity, and small warp cannot be achieved at temperature of less than (Tm-300)° C., and at a temperature of Tm° C. or higher there arise the problems of occurrence of seizure in a roll and generation of liquid phase. The average thickness of aluminum or aluminum alloy plate is preferably from 0.1 mm to 2.0 mm inclusive. The average thickness of aluminum or aluminum alloy plate is set within the range from 0.1 mm to 2.0 mm inclusive because damages may be caused silicon carbide particles at a thickness of less than 0.1 mm, and the effect exerted by forming the aluminum or aluminum alloy layer as a superficial layer is saturated at a thickness of more than 2.0 mm. When molding pressure at the molding step is more than or equal to 2 ton/cm2 (2×98 MPa), it is possible to produce a member for a semiconductor device having more excellent adhesiveness and heat conductivity. Also in this another production method of the present invention, inventors of the present invention found that heat conductivity and toughness of the member for a semiconductor device are further improved when it is produced by a method that further includes between the step of obtaining a molded body and the step of heating and rolling step, the step of obtaining a heat-treated body by subjecting the molded body to heat treatment in non-oxidizing atmosphere at a temperature of (Tm-300)° C. or higher and lower than Tm° C. when the melting point or solidus temperature of the melt material is denoted by Tm° C. Further, also in this another production method of the present invention, inventors found that heat conductivity and toughness can be further improved by conducting the heating and rolling step in the non-oxidizing atmosphere. The heating and rolling step may be conducted in atmospheric air or in oxidizing atmosphere. EXAMPLES Example 1 Aluminum (Al) powder having an average particle diameter of 10 μm and silicon carbide (SiC) powder having an average particle diameter of 15 μm were mixed so that the content of SiC was as shown in Table 1 while the mixing ratio was varied, and molding was carried out while the resultant mixed powder was placed on the top and bottom faces of an aluminum plate of JIS (Japanese Industrial Standards) 1050, or in other words, in the condition that the mixed powder was sandwiched by an aluminum plate having a thickness shown in Table 1, to prepare a molded body (molding step). Molding of mixed powder was carried out so that the molding pressure was 2 ton/cm2 (2×98 MPa) by applying a load of 72 tons on the powder using 100-ton pressing machine. The molded body obtained in this manner was heated and compressed while it was heated to a temperature of 600° C. so that compression pressure was 2 ton/cm2 (2×98 MPa) by application of a load of 72 tons on the molded body with the use of the same pressuring machine that was used for preparing the molded body (heating and compressing step). In this manner, a sample of 60 mm in high, 60 mm in wide, and 5 mm in thick was prepared. Each sample was evaluated for the characteristics as shown below. The obtained characteristics are shown in Table 1. In Table 1, in comparative examples 4 to 7, an aluminum plate was not placed on top and bottom faces of the mixed powder in the molding step. (I) Thickness of Al Layer [mm], Thickness Ratio of Al Layer/Sample [%] The thickness of Al layer which was the finally obtained superficial layer (thickness on first surface side) was measured, and a ratio of Al layer relative to the thickness of sample was calculated. (II) Variation in Thickness of Al Layer [%] The variation in the thickness, relative to the average value of the thickness of the finally obtained superficial layer was determined. (III) Coefficient of Thermal Expansion [×10−6/K] Using PIL-402PC available from NETZSCH, a sample cut into a size of 4 mm×4 mm×20 mm was heated, and an elongation was detected by a differential transformer to determine a coefficient of thermal expansion. (IV) Heat Conductivity [W/m·K] at a Temperature of 100° C. This was determined by laser flash method using a thermal constant measuring apparatus TC-700 available from ULVAC-RIKO, Inc. To be more specific, on either face of a sample cut out in a size of 10 mm in diameter, and 2 mm in thick was radiated with laser beam for a short time to give thermal energy, and nonstationary temperature change in the opposite face of the sample at this time was measured with a thermocouple and InSb (indium antimony) infrared detector for obtaining specific heat and a coefficient of thermal diffusivity, respectively, and whereby heat conductivity was determined. (V) Peel Strength (Bonding Strength) of Al Layer [×9.8 MPa] FIG. 4 is a schematic section view showing a test method for measuring a peel strength of Al layer which is a superficial layer. As shown in FIG. 4, in a peeling test of Al layer, a tensile test jig 20 having a boding face of 10 mm in diameter and a holding part of tensile test of 8 mm in diameter was pasted on top and bottom faces of a test piece 1 of each sample previously cut out in a disc of 10 mm in diameter by a cutting wire, with the use of an adhesive of Scotch-weld (trade name) DP460 available from Sumitomo 3M Limited, and after curing, the tensile was applied in the direction of arrow to conduct a tensile test. As a tensile test machine, Instron tensile test machine having a tensile axial alignment mechanism was used. By measuring strength until an Al layer serving as the superficial layer 12 peeled with this tensile test, bonding strength between the Al layer serving as the superficial layer 12 and an aluminum-silicon carbide composite material serving as base material 11 was evaluated. (VI) Ratio of Warp Y/X[%] Warp Y[mm] per length 60 [mm] of one side of each sample was measured, and ratio of warp relative to the length was calculated. (VII) Presence/Absence of Void Surface of each sample was plated with nickel of 2 μm thick, and heated to a temperature of 250° C., and then whether voids occurred was observed. In inventive examples 1 to 7 and comparative examples 1 and 2, occurrence of voids was not observed, however in comparative examples 4 to 7, occurrence of voids was observed in every example. Further, similar results were obtained when tests were carried out in a similar manner except that plating was conducted using copper, silver and gold in a thickness ranging from 0.1 μm to 10 μm. (VIII) Solder Wettability Solder wettability of inventive examples 1 to 7 plated with nickel were evaluated. In evaluation, after dipping each sample into an eutectic lead tin solder bath heated to a temperature of 200° C., the sample was drawn up, and degree of solder adhesion was examined. The samples in which a part where solder was not adhered was not observed on the surface of plating a layer after dipping, and good adhesion of solder was observed had surface roughness of plating the layer of less than or equal to 2 μm by Ra. In samples having surface roughness of plating the layer of more than or equal to 2 μm by Ra, a part where solder was not adhered was observed. Surface of each sample of inventive examples 1 to 7 was plated with copper, silver or gold inplace of nickel plating and solder wettability was evaluated, and similar results were obtained. TABLE 1 Variation Ratio of Al plate Al layer Al layer/ of Al layer Coefficient of Heat Al layer peel warp Presence/ SiC thickness thickness sample thickness thermal conductivity strength (Y/X) absence of [mass %] [mm] [mm] [%] [%] expansion [×10−6/K] [W/m · K] [×9.8 MPa] [%] void Inventive 1 30 0.1 0.1 2 6 14.8 208 3.1 0.13 Not example observed 2 40 0.1 0.1 2 5 12.1 196 3.6 0.09 Not observed 3 40 0.5 0.4 8 20 12.5 195 4.1 0.08 Not observed 4 40 2 1.5 30 29 12.7 197 4.3 0.14 Not observed 5 50 1 0.5 10 14 10 196 5.3 0.11 Not observed 6 65 0.5 0.2 4 15 8 200 4.0 0.05 Not observed 7 85 0.5 0.3 6 20 6.8 202 3.3 0.19 Not observed Comparative 1 10 0.5 0.2 4 10 20 230 3.5 0.09 Not example observed 2 20 0.6 0.3 6 20 18 220 3.0 0.14 Not observed 3 87 0.3 Impossible to produce 4 40 — — — — 12.6 164 — 0.33 Observed 5 50 — — — — 10.2 167 — 0.43 Observed 6 65 — — — — 8.1 175 — 0.44 Observed 7 85 — — — — 6.9 169 — 0.50 Observed Results shown in Table 1 demonstrate that in inventive examples 1 to 7 in which the SiC content was from 30 to 85% by mass, a coefficient of thermal expansion was 6.5 to 15×10−6/K and heat conductivity at a temperature of 100° C. was more than or equal to 180 W/m·K. In comparative examples 1 and 2 in which the SiC content was less than 30% by mass, a coefficient of thermal expansion was larger than 15×10−6/K. Production of comparative example 3 in which the SiC content was more than 85% by mass was impossible. In inventive examples 1 to 7 and comparative examples 1 and 2, value of (Y/X) was less than or equal to 0.2%. A cooling and heating cycle test (temperature range from −40° C. to 150° C.) was conducted for samples of inventive examples 1 to 7 having surface plated with nickel of 2 μm thick and for samples which were obtained by plating surface with nickel of 2 μm following vapor deposition of aluminum of 3 μm thick in comparative examples 4 to 7. As a result, in comparative examples 4 to 7, peeling of an Al deposition layer was observed for every case after 100 cycles, however, in inventive examples 1 to 7, peeling of the Al layer was not observed even after 5000 cycles. As shown in FIG. 4, a test for measuring peel strength of an All layer serving as a superficial layer was conducted using an adhesive in a similar manner as described above, and peel strength was measured. In comparative examples 4 to 7, peel strength was 0.3 to 0.4 kgf/mm2 (0.3×9.8 to 0.4×9.8 MPa), while any of inventive examples 1 to 7 had peel strength over 2 kgf/mm2 (2×9.8 MPa). Observation of bonding part under transmission electron microscope revealed that a part of bonding part included a metal bond in inventive examples 1 to 7. Further, cooling and heating cycle test (temperature range from −40° C. to 150° C.) was conducted on samples obtained by soldering an AIN sintered body having a copper or aluminum layer on its surface, to samples of inventive examples 1 to 7 having surface plated with nickel of 2 μm thick, or to samples which were obtained by plating surface with nickel of 2 μm following vapor deposition of aluminum of 3 μm thick in comparative examples 4 to 7, using alloy of tin (Sn)—3% by mass of silver (Ag)—0.5% by mass of copper (Cu) as a solder material. As a result, in comparative examples 4 to 7, breaking was observed in a solder bonding part for every case after 100 cycles, however, in inventive examples 1 to 7, breaking in a solder bonding part was not observed even after 10000 cycles. Example 2 Each sample in Example 1 was drilled while lubricant oil was applied to form a hole of 10.5 mm in diameter by means of a drill, and a bolt of M10 was inserted, and a nut was fastened at a torque of 10 kgf in (98 N·m). Breaking occurred in comparative examples 5 to 7, while breaking was not observed in inventive examples 5 to 7 even torque was elevated to 15 kgf·μm (15×9.8 N·m). The crystal structure of an aluminum layer serving as a superficial layer in inventive examples 5 to 7 was observed, and the average crystal particle diameter was 84 μm, 158 μm, and 34 μm, respectively. Example 3 Samples was prepared in a similar manner as in Example 1 at an SiC content of 60% by mass, with variable the average particle diameter of SiC powder of 5 μm, 10 μm, 80 μm, 150 μm and 200 μm, and a variable thickness of an aluminum layer of 0.050 mm, 0.100 mm, 0.500 mm, 1.000 mm, 2.000 mm, and 2.500 mm. Each sample was evaluated for heat conductivity at a temperature of 100° C., variation in a thickness of an Al layer, and ratio of warp in the same manner as described in Example 1. The results are shown in Table 2, Table 3 and Table 4. TABLE 2 Heat conductivity [W/m · K] SiC average particle diameter Thickness of Al layer [mm] [μm] 0.050 0.100 0.500 1.000 2.000 2.500 5 181 182 180 182 183 187 10 187 206 200 203 201 200 80 186 198 183 185 198 201 150 185 200 200 205 198 210 200 190 190 190 198 197 205 TABLE 3 Variation in thickness of Al layer [%] SiC average particle Thickness of Al layer [mm] diameter [μm] 0.050 0.100 0.500 1.000 2.000 2.500 5 10 9 8 5 4 3 10 30 15 12 10 6 3 80 40 20 15 12 7 3 150 55 25 18 14 8 4 200 80 36 25 20 14 6 TABLE 4 Ratio of warp (Y/X) [%] SiC average particle diameter Thickness of Al layer [mm] [μm] 0.050 0.100 0.500 1.000 2.000 2.500 5 0.11 0.12 0.15 0.16 0.18 0.12 10 0.11 0.11 0.11 0.14 0.17 0.23 80 0.12 0.11 0.16 0.17 0.18 0.24 150 0.12 0.14 0.17 0.18 0.18 0.30 200 0.10 0.13 0.18 0.19 0.20 0.33 Results shown in Table 2, Table 3 and Table 4 demonstrate that when average particle diameter of SiC powder was 5 μm, a coefficient of thermal expansion was comparable, however, heat conductivity at a temperature of 100° C. was lower than those having other particle diameters. Further, when the average particle diameter of SiC powder was 200 μm, a part where the thickness of the aluminum layer was not uniform and thin occurred at a thickness of the aluminum layer of 0.050 mm. When a thickness of the aluminum layer was larger than 2.500 mm, tendency that the warp becomes greater was observed. Example 4 In production methods of inventive examples 1 to 7 shown in Table 1, samples were produced with varied molding pressures. Influence of molding pressure exerted on a coefficient of thermal expansion and heat conductivity at a temperature of 100° C. was examined. The coefficient of thermal expansion and heat conductivity were determined in a similar manner as described in Example 1. Results are shown in Table 5. In Table 5, “α” and “κ” mean a coefficient of thermal expansion and heat conductivity, respectively. TABLE 5 Coefficient of Molding pressure thermal Heat 1.4 × 98 expansion α conductivity κ 98 MPa MPa 2 × 98 MPa 3 × 98 MPa [×10−6/K] [W/m · K] α κ α κ α κ α κ Inventive 1 14.9 190 14.8 208 14.7 208 14.7 208 example 2 12.3 188 12.1 196 11.8 199 11.7 200 3 12.8 187 12.5 195 12.4 198 12.3 199 4 12.9 183 12.7 197 12.6 198 12.6 199 5 11 189 10 196 9.8 198 9.7 199 6 9.1 184 8 200 7.9 204 7.8 206 7 7.7 183 6.8 202 6.7 208 6.7 210 Results shown in Table 5 demonstrate that the higher the molding pressure, the smaller the coefficient of thermal expansion and the higher heat conductivity at a temperature of 100° C. Toughness of samples obtained at molding pressure of 98 MPa and 2×98 MPa in the inventive example 5 was evaluated. Toughness was evaluated by a ratio of number of samples in which breaking occurred when each sample was drilled while lubricant oil was applied to form a hole of 10.5 mm in diameter by means of a drill, and a bolt of M10 was inserted, and a nut was fastened at a torque of 20 kgf·m (2×98 N·m), relative to the total number of samples. Ratio of number of samples in which breaking occurred at a molding pressure of 2×98 MPa was 20%, compared to that at molding pressure of 98 MPa. It can be understood that the higher molding pressure, the more toughness improves. Example 5 In the production methods of inventive examples 1 to 7 shown in Table 1, a sample was prepared in a similar manner as in Example 1 except that between the molding step and the heating and compressing step, the molded body was heated for 5 hours at a temperature of 600° C. in nitrogen gas atmosphere. Influence of the heating process which is an intermediate step exerted on a coefficient of thermal expansion and heat conductivity at a temperature of 100° C. was examined. The coefficient of thermal expansion and heat conductivity were determined in a similar manner as described in Example 1. Results are shown in Table 6. In Table 6, “α” and “κ” mean a coefficient of thermal expansion and heat conductivity, respectively. TABLE 6 Coefficient of Heating process thermal Heat expansion α conductivity κ Conducted Not conducted [×10−6/K] [W/m · K] α κ α κ Inventive 1 14.6 212 14.8 208 example 2 12.1 201 12.1 196 3 12.5 199 12.5 195 4 12.6 202 12.7 197 5 9.9 202 10 196 6 7.8 209 8 200 7 6.7 211 6.8 202 Results shown in Table 6 demonstrate that conducting the heating process as an intermediate step improves heat conductivity. In inventive example 5, toughness was evaluated for samples having experienced heating process and not experienced heating process. Toughness was evaluated by a ratio of number of samples in which breaking occurred when each sample was drilled while lubricant oil was applied to form a hole of 10.5 mm in diameter by means of a drill, and a bolt of M10 was inserted, and a nut was fastened at a torque of 20 kgf·m (2×98 N·m), relative to the total number of samples. The ratio of number of samples in which breaking occurred in the samples having experienced heating process was 10%, compared to the samples not having experienced heating process. It can be understood that toughness improves when heating process is conducted as an intermediate step. Further, in inventive example 3 and inventive example 5 shown in Table 1, by varying the heating temperature in the heating process step in nitrogen gas atmosphere conducted between the molding step and heating and compressing step, influence of the heating temperature exerted on a coefficient of thermal expansion and heat conductivity at a temperature of 100° C. was examined. The coefficient of thermal expansion and heat conductivity were determined in a similar manner as described in Example 1. Results are shown in FIG. 5. In FIG. 5, horizontal axis represents heating temperature, left vertical axis represents heat conductivity κ, and right vertical axis represents a coefficient of thermal expansion α. Results shown in FIG. 5 demonstrate that heat conductivity is improved when heating process is conducted as an intermediate step at heating temperature of more than or equal to (Tm-300)° C. (more than or equal to about 350° C. in inventive example 3 and inventive example 5). Example 6 Aluminum (Al) powder having an average particle diameter of 10 μm and silicon carbide (SiC) powder having an average particle diameter of 15 μm were mixed in variable mixing ratio so that the content of SiC was as shown in Table 7 while varying mixing ratio, and molding was carried out while the resultant mixed powder is placed on the top and bottom faces of an aluminum plate of JIS (Japanese Industrial Standards) 1050, or in other words, in the condition that the mixed powder was sandwiched by an aluminum plate having a thickness shown in Table 7, to prepare a molded body (molding step). Molding of mixed powder was carried out so that the molding pressure is 2 ton/cm2 (2×98 MPa) by applying a load of 72 tons on the powder using 100-ton pressing machine. The molded body obtained in this manner was then heated and rolled by being subjected to hot rolling involving five passages at 5% reduction while it was heated to a temperature of 600° C. (heating and rolling step). In this manner, a sample of 60 mm high×60 mm wide×5 mm thick was prepared. Each sample was evaluated for the characteristics in a similar manner as in Example 1. The obtained characteristics are shown in Table 7. TABLE 7 Variation in Al Coefficient of SiC Al plate Al layer Al layer/ layer thermal Heat Al layer peel Ratio of warp [% by thickness thickness sample thickness expansion conductivity strength (Y/X) mass] [mm] [mm] [%] [%] [×10−6/K] [W/m · K] [×9.8 MPa] [%] Inventive 2 40 0.4 0.3 6 11 12.5 197 4.3 0.10 example 4 50 0.6 0.4 8 14 9.9 197 4.9 0.12 5 65 0.5 0.2 4 17 8.0 203 5.2 0.11 6 85 0.8 0.3 6 22 6.8 206 3.7 0.19 Surface of each sample was plated with nickel of 2 μm thick, and heated to a temperature of 250° C., and then presence of void was observed. However, occurrence of void was not observed. Each sample plated with nickel of 2 μm thick on the surface was subjected to cooling and heating cycle test (temperature range of −40° C. to 150° C.), and no peeling was observed in an Al layer after 5000 cycles. Each sample obtained by plating surface with nickel of 2 μm soldered with alloy of tin (Sn)—3% by mass of silver (Ag)—0.5% by mass of copper (Cu) as a solder material was subjected to cooling and heating cycle test (temperature range of −40° C. to 150° C.), and no breaking was observed in solder bonding part after 10000 cycles. It is to be understood that the embodiments and examples disclosed in the above are given for exemplification and not for limitation in all respects. The scope of the present invention is defined by attached claims and not by the above embodiments and examples, and embraces any changes and modification made within the meanings and coverage of equivalence of claims. INDUSTRIAL APPLICABILITY The member for a semiconductor device of the present invention is used as a heat radiation member such as heat spreader member or lid member in a semiconductor device called a power device such as insulated gate bipolar transistor (IGBT) unit mounted in, e.g., automobile, or in semiconductor device into which semiconductor integrated circuit element chip or central processing unit (CPU) unit such as computer or server, or microprocessor unit (MPU) is incorporated.	H	67H01	185H01L	23	14
11656759	US20080173884A1-20080724	Wafer level phosphor coating method and devices fabricated utilizing method	ACCEPTED	20080709	20080724	[]	H01L3300	["H01L3300"]	9024349	20070122	20150505	257	099000	67597.0	LIGAI	MARIA	[{"inventor_name_last": "Chitnis", "inventor_name_first": "Ashay", "inventor_city": "Santa Barbara", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Ibbetson", "inventor_name_first": "James", "inventor_city": "Santa Barbara", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chakraborty", "inventor_name_first": "Arpan", "inventor_city": "Goleta", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Tarsa", "inventor_name_first": "Eric J.", "inventor_city": "Goleta", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Keller", "inventor_name_first": "Bernd", "inventor_city": "Santa Barbara", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Seruto", "inventor_name_first": "James", "inventor_city": "Orcutt", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Fu", "inventor_name_first": "Yankun", "inventor_city": "Raleigh", "inventor_state": "NC", "inventor_country": "US"}]	Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.	1. A method for fabricating light emitting diode (LED) chips, comprising: providing a plurality of LEDs; depositing pedestals on said LEDs, each of said pedestals in electrical contact with one of said LEDs; forming a coating over said LEDs, said coating burying at least some of said pedestals; and planarizing said coating leaving at least some of said coating on said LEDs while exposing at least some of said buried pedestals. 2. The method of claim 1, wherein said LED chips emit white light. 3. The method of claim 1, further comprising depositing a contact on each said LEDs said pedestals formed on said contacts. 4. The method of claim 1, wherein said LEDs are provided on a growth substrate. 5. The method of claim 1, wherein said LEDs are mounted on a carrier substrate. 6. The method of claim 1, wherein said carrier substrate comprises a phosphor layer. 7. The method of claim 1, wherein said LEDs comprise at least a portion of a growth substrate. 8. The method of claim 7, wherein said substrate is shaped or textured. 9. The method of claim 1, wherein said step of forming a coating over said LEDs comprises providing a prefabricated coating layer and placing it over said LEDs. 10. The method of claim 1, wherein said LEDs are provided on a substrate, further comprising forming trenches in said substrate and forming a second coating filling said trenches. 11. The method of claim 1, further comprising curing said coating prior to planarizing. 12. The method of claim 1, further comprising curing said coating following planarizing. 13. The method of claim 1, further comprising forming a surface texture on said coating. 14. The method of claim 13, wherein said surface texture is formed during said planarizing. 15. The method of claim 13, wherein said surface texture is formed by laser texturing. 16. The method of claim 1, further comprising singulating said LEDs. 17. The method of claim 1, wherein said coating comprises a phosphor loaded binder. 18. The method of claim 17, wherein said phosphor loaded binder comprises multiple phosphors. 19. The method of claim 1, wherein said coating comprises scattering particles. 20. The method of claim 1, wherein said coating comprises multiple layers with different compositions. 21. The method of claim 17, wherein said binder comprises one of the materials from the group consisting of silicone, epoxy, glass, spin-on glass, BCB, polymides and polymers. 22. The method of claim 17, wherein said phosphor comprises YAG:Ce. 23. The method of claim 17, wherein said phosphor comprises a material from the group consisting of Y3Al5O12:Ce (YAG), Tb3-xRExO12:Ce (TAG); RE=Y,Gd,La,Lu, and Sr2-x-yBaxCaySiO4:Eu. 24. The method of claim 1, wherein said planarizing comprises one of the methods from the group consisting of grinding, lapping and polishing. 25. The method of claim 1, wherein said planarizing comprises one or more methods from the group consisting of squeegee, pressure planarization, etching and ablation. 26. The method of claim 1, wherein said coating covers said LEDs by one of the methods from the group consisting of spin coating, electrophoretic deposition, electrostatic deposition, printing, jet printing and screen printing. 27. The method of claim 1, wherein said pedestal is formed using stud bumping. 28. The method of claim 1, further comprising the step of forming a second coating around at least part of said LEDs. 29. The method of claim 28, wherein said second coating has a different composition than said coating. 30. The method of claim 28, further comprising the step of planarizing said second coating. 31. The method of claim 1, further comprising depositing a metal pad on said planarized coating interconnecting at least some of said pedestals to form an LED array. 32. The method of claim 16, further comprising sealing one of said singulated LEDs in a encapsulant. 33. The method of claim 16, further comprising mounting one of said LEDs to a submount or printed circuit board (PCB). 34. The method of claim 1, wherein said planarizing results in a uniform coating thickness. 35. The method of claim 1, wherein said coating thickness has a total thickness variation of less than 50% of the average coating thickness. 36. A method for fabricating LED chips, comprising: flip-chip bonding a plurality of LEDs on a carrier substrate; forming a conductive pedestal in electrical contact with each of the LEDs; forming a coating over said LEDs, said coating burying at least some of said pedestals; and planarizing said coating to expose at least some of said buried pedestals. 37. The method of claim 36, wherein said carrier substrate comprises electrical traces, said LEDs mounted in contact with said electrical traces. 38. The method of claim 36, wherein said pedestals are formed on said conductive traces. 39. The method of claim 36, wherein said LED chips emit white light. 40. A method for fabricating coated semiconductor devices, comprising: providing a plurality of semiconductor devices on a substrate; depositing pedestals on said semiconductor devices, each of which is in electrical contact with one of said semiconductor devices; forming a coating over said semiconductor devices, said coating burying at least some of said pedestals; and planarizing said coating leaving at least some of said coating material on said semiconductor devices while exposing at least some of said buried pedestals for contacting. 41. A light emitting diode (LED) chip wafer, comprising: a plurality of LEDs; a plurality of pedestals, each of which is in electrical contact with one of said LEDs; and a coating at least partially covering said LEDs, at least some of said pedestals extending through and to the surface of said coating and exposed at the surface of said coating. 42. The LED chip wafer of claim 41, wherein said LEDs are on a substrate wafer. 43. The LED chip wafer of claim 41, further comprising a plurality of contacts, each of which is on one of said LEDs, at least some of said pedestals formed on said contacts. 44. The LED chip wafer of claim 41, wherein said substrate wafer is capable of being separated into LED chips. 45. The LED chip wafer of claim 41, wherein said coating has a uniform thickness. 46. The LED chip wafer of claim 41, wherein said coating has a total thickness variation of <50% of the average coating thickness. 47. The LED chip wafer of claim 41, wherein said coating has a textured surface. 48. The LED chip wafer of claim 41, wherein said coating comprises multiple phosphors. 49. The LED chip wafer of claim 41, wherein said coating comprises scattering particles. 50. The LED chip wafer of claim 41, wherein said coating comprises a phosphor loaded binder. 51. The LED chip wafer of claim 50, wherein said binder comprises one of the materials from the group consisting of silicone, epoxy, glass, spin-on glass, BCB, polymides and polymers. 52. The LED chip wafer of claim 50, wherein said phosphor comprises YAG:Ce. 53. The LED chip wafer of claim 41, wherein said pedestals comprise one or more stud bumps. 54. The LED chip wafer of claim 41, wherein said LEDs are made of materials from the Group-III nitride material system. 55. The LED chip wafer of claim 41, wherein said substrate wafer comprises a growth substrate. 56. The LED chip wafer of claim 41, wherein said substrate wafer comprises a carrier substrate. 57. The LED chip wafer of claim 41, wherein said LEDs are interconnected in an LED array. 58. The LED chip wafer of claim 41, a metal pad on the surface of said coating interconnecting at least some of said exposed pedestals to form an LED array. 59. The LED chip wafer of claim 41, further comprising a reflective layer formed integral to said substrate wafer. 60. The LED chip wafer of claim 42, wherein said substrate comprises a phosphor loaded binder layer. 61. The LED chip wafer of claim 41, wherein said LEDs comprise at least of portion of a growth substrate. 62. The LED chip wafer of claim 41, wherein said LEDs are provided on a substrate, further comprising trenches in said substrate and a second coating filling said trenches. 63. The LED chip wafer of claim 41, wherein said coating comprises multiple layers with different compositions. 64. The LED chip wafer of claim 41, further comprising the step of forming a second coating around at least part of said LEDs. 65. The LED chip wafer of claim 64, wherein said second coating has a different composition than said coating. 66. The LED chip wafer of claim 41, capable of emitting white light from said LEDs and coating. 67. An light emitting diode (LED) chip, comprising: an LED; a pedestal in electrical contact with said LED; and a coating at least partially covering said LED, said pedestal extending through and to the surface of said coating and exposed at the surface of said coating. 68. The LED chip of claim 67, wherein said LED emits white light. 69. The LED chip of claim 67, wherein said LED is on a substrate. 70. The LED chip of claim 67, further comprising a contact on said LED, said pedestals formed on said contact. 71. The LED chip of claim 67, wherein said coating comprises a phosphor loaded binder. 72. The LED chip of claim 67, wherein said pedestal comprises one or more stud bumps. 73. The LED chip of claim 67, wherein said LED comprises materials from the Group-III nitride material system. 74. The LED chip of claim 67, wherein said substrate wafer comprises a growth substrate. 75. The LED chip of claim 67, wherein said substrate wafer comprises a carrier substrate. 76. The LED chip wafer of claim 67, further comprising a reflective layer formed integral to said substrate. 77. A light emitting diode (LED) package comprising: an LED chip; a pedestal in electrical contact with said LED chips; and a coating at least partially covering said LED chip, said pedestal extending through and to the surface of said coating and exposed at the surface of said coating; package leads, said pedestal in electrical connection with one of said package leads; and encapsulation surrounding said LED chip and electrical connections. 78. A light emitting diode (LED) package comprising: an LED chip; a pedestal in electrical contact with said LED chips; and a coating at least partially covering said LED chip, said pedestal extending through and to the surface of said coating and exposed at the surface of said coating; and package leads, said pedestal in electrical connection with one of said package leads, wherein the chip is enclosed by a hermetically sealed cover. 79. The LED package of claim 78, wherein an inert atmosphere surrounds the LED chip at or below atmospheric pressure.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention This invention relates to methods for fabricating semiconductor devices and in particular methods for wafer level coating of light emitting diodes. 2. Description of the Related Art Light emitting diodes (LED or LEDs) are solid state devices that convert electric energy to light, and generally comprise one or more active layers of semiconductor material sandwiched between oppositely doped layers. When a bias is applied across the doped layers, holes and electrons are injected into the active layer where they recombine to generate light. Light is emitted from the active layer and from all surfaces of the LED. Conventional LEDs cannot generate white light from their active layers. Light from a blue emitting LED has been converted to white light by surrounding the LED with a yellow phosphor, polymer or dye, with a typical phosphor being cerium-doped yttrium aluminum garnet (Ce:YAG). [See Nichia Corp. white LED, Part No. NSPW300BS, NSPW312BS, etc.; See also U.S. Pat. No. 5,959,316 to Lowrey, “Multiple Encapsulation of Phosphor-LED Devices”]. The surrounding phosphor material “downconverts” the wavelength of some of the LED's blue light, changing its color to yellow. Some of the blue light passes through the phosphor without being changed while a substantial portion of the light is downconverted to yellow. The LED emits both blue and yellow light, which combine to provide a white light. In another approach light from a violet or ultraviolet emitting LED has been converted to white light by surrounding the LED with multicolor phosphors or dyes. One conventional method for coating an LED with a phosphor layer utilizes a syringe or nozzle for injecting a phosphor mixed with epoxy resin or silicone polymers over the LED. Using this method, however, it can be difficult to control the phosphor layer's geometry and thickness. As a result, light emitting from the LED at different angles can pass through different amounts of conversion material, which can result in an LED with non-uniform color temperature as a function of viewing angle. Because the geometry and thickness is hard to control, it can also be difficult to consistently reproduce LEDs with the same or similar emission characteristics. Another conventional method for coating an LED is by stencil printing, which is described in European Patent Application EP 1198016 A2 to Lowery. Multiple light emitting semiconductor devices are arranged on a substrate with a desired distance between adjacent LEDs. The stencil is provided having openings that align with the LEDs, with the holes being slightly larger than the LEDs and the stencil being thicker than the LEDs. A stencil is positioned on the substrate with each of the LEDs located within a respective opening in the stencil. A composition is then deposited in the stencil openings, covering the LEDs, with a typical composition being a phosphor in a silicone polymer that can be cured by heat or light. After the holes are filled, the stencil is removed from the substrate and the stenciling composition is cured to a solid state. Like the syringe method above, using the stencil method can be difficult to control the geometry and layer thickness of the phosphor containing polymer. The stenciling composition may not fully fill the stencil opening such that the resulting layer is not uniform. The phosphor containing composition can also stick to the stencil opening which reduces the amount of composition remaining on the LED. The stencil openings may also be misaligned to the LED. These problems can result in LEDs having non-uniform color temperature and LEDs that are difficult to consistently reproduce with the same or similar emission characteristics. Various coating processes of LEDs have been considered, including spin coating, spray coating, electrostatic deposition (ESD), and electrophoretic deposition (EPD). Processes such as spin coating or spray coating typically utilize a binder material during the phosphor deposition, while other processes require the addition of a binder immediately following their deposition to stabilize the phosphor particles/powder. With these approaches the key challenge is accessing the wire bond pad on the device after the coating process. Accessing the wire bond by standard wafer fabrication techniques is difficult with typical silicone binding material, as well as other binder materials such as epoxies or glass. Silicones are not compatible with commonly used wafer fabrication materials such as acetone, as well as some developers, and resist strippers. This can limit the options and choices for the particular silicones and process steps. Silicones are also cured at high temperature (greater than 150° C.), which is beyond the glass transition temperature of commonly used photoresists. Cured silicone films with phosphor are also difficult to etch and have a very slow etch rate in chlorine and CF 4 plasma, and wet etching of cured silicones is typically inefficient.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention discloses new methods for fabricating semiconductor devices such as LED chips at the wafer level, and discloses LED chips and LED chip wafers fabricated using the methods. One method for fabricating light emitting diode (LED) chips according to the present invention comprises providing a plurality of LEDs typically on a substrate. Pedestals are formed on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over said LEDs, with the coating burying at least some of the pedestals. The coating is then planarized leaving some of said coating material on said LEDs while exposing at least some of the buried pedestals, making them available for contacting. The present invention discloses similar methods used for fabricating LED chips comprising LEDs flip chip mounted on a carrier substrate. Similar methods according to the present invention can also be used for fabricating other semiconductor devices. One embodiment of a light emitting diode (LED) chip wafer fabricated using methods according to the present invention comprises a plurality of LEDs on a substrate wafer and a plurality of pedestals, each of which is in electrical contact with one of the LEDs. A coating at least partially covers the LEDs with at least some of the pedestals extending through and to the surface of the coating. The pedestals are exposed at the surface of the coating. One embodiment of a light emitting diode (LED) chip manufactured using methods according to the present invention comprises an LED on a substrate and a pedestal in electrical contact with the LED. A coating at least partially covering the LED, with the pedestal extending through and to the surface of the coating and exposed at the surface of the coating. In accordance with certain aspects of the present invention, the coating can include phosphor particles that downconvert at least some of the light emitted from the active region of the LED chip to produce white light, thereby producing a white LED chip. These and other aspects and advantages of the invention will become apparent from the following detailed description and the accompanying drawings which illustrate by way of example the features of the invention.	This invention was made with Government support under Contract USAF 05-2-5507. The Government has certain rights in this invention BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to methods for fabricating semiconductor devices and in particular methods for wafer level coating of light emitting diodes. 2. Description of the Related Art Light emitting diodes (LED or LEDs) are solid state devices that convert electric energy to light, and generally comprise one or more active layers of semiconductor material sandwiched between oppositely doped layers. When a bias is applied across the doped layers, holes and electrons are injected into the active layer where they recombine to generate light. Light is emitted from the active layer and from all surfaces of the LED. Conventional LEDs cannot generate white light from their active layers. Light from a blue emitting LED has been converted to white light by surrounding the LED with a yellow phosphor, polymer or dye, with a typical phosphor being cerium-doped yttrium aluminum garnet (Ce:YAG). [See Nichia Corp. white LED, Part No. NSPW300BS, NSPW312BS, etc.; See also U.S. Pat. No. 5,959,316 to Lowrey, “Multiple Encapsulation of Phosphor-LED Devices”]. The surrounding phosphor material “downconverts” the wavelength of some of the LED's blue light, changing its color to yellow. Some of the blue light passes through the phosphor without being changed while a substantial portion of the light is downconverted to yellow. The LED emits both blue and yellow light, which combine to provide a white light. In another approach light from a violet or ultraviolet emitting LED has been converted to white light by surrounding the LED with multicolor phosphors or dyes. One conventional method for coating an LED with a phosphor layer utilizes a syringe or nozzle for injecting a phosphor mixed with epoxy resin or silicone polymers over the LED. Using this method, however, it can be difficult to control the phosphor layer's geometry and thickness. As a result, light emitting from the LED at different angles can pass through different amounts of conversion material, which can result in an LED with non-uniform color temperature as a function of viewing angle. Because the geometry and thickness is hard to control, it can also be difficult to consistently reproduce LEDs with the same or similar emission characteristics. Another conventional method for coating an LED is by stencil printing, which is described in European Patent Application EP 1198016 A2 to Lowery. Multiple light emitting semiconductor devices are arranged on a substrate with a desired distance between adjacent LEDs. The stencil is provided having openings that align with the LEDs, with the holes being slightly larger than the LEDs and the stencil being thicker than the LEDs. A stencil is positioned on the substrate with each of the LEDs located within a respective opening in the stencil. A composition is then deposited in the stencil openings, covering the LEDs, with a typical composition being a phosphor in a silicone polymer that can be cured by heat or light. After the holes are filled, the stencil is removed from the substrate and the stenciling composition is cured to a solid state. Like the syringe method above, using the stencil method can be difficult to control the geometry and layer thickness of the phosphor containing polymer. The stenciling composition may not fully fill the stencil opening such that the resulting layer is not uniform. The phosphor containing composition can also stick to the stencil opening which reduces the amount of composition remaining on the LED. The stencil openings may also be misaligned to the LED. These problems can result in LEDs having non-uniform color temperature and LEDs that are difficult to consistently reproduce with the same or similar emission characteristics. Various coating processes of LEDs have been considered, including spin coating, spray coating, electrostatic deposition (ESD), and electrophoretic deposition (EPD). Processes such as spin coating or spray coating typically utilize a binder material during the phosphor deposition, while other processes require the addition of a binder immediately following their deposition to stabilize the phosphor particles/powder. With these approaches the key challenge is accessing the wire bond pad on the device after the coating process. Accessing the wire bond by standard wafer fabrication techniques is difficult with typical silicone binding material, as well as other binder materials such as epoxies or glass. Silicones are not compatible with commonly used wafer fabrication materials such as acetone, as well as some developers, and resist strippers. This can limit the options and choices for the particular silicones and process steps. Silicones are also cured at high temperature (greater than 150° C.), which is beyond the glass transition temperature of commonly used photoresists. Cured silicone films with phosphor are also difficult to etch and have a very slow etch rate in chlorine and CF4 plasma, and wet etching of cured silicones is typically inefficient. SUMMARY OF THE INVENTION The present invention discloses new methods for fabricating semiconductor devices such as LED chips at the wafer level, and discloses LED chips and LED chip wafers fabricated using the methods. One method for fabricating light emitting diode (LED) chips according to the present invention comprises providing a plurality of LEDs typically on a substrate. Pedestals are formed on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over said LEDs, with the coating burying at least some of the pedestals. The coating is then planarized leaving some of said coating material on said LEDs while exposing at least some of the buried pedestals, making them available for contacting. The present invention discloses similar methods used for fabricating LED chips comprising LEDs flip chip mounted on a carrier substrate. Similar methods according to the present invention can also be used for fabricating other semiconductor devices. One embodiment of a light emitting diode (LED) chip wafer fabricated using methods according to the present invention comprises a plurality of LEDs on a substrate wafer and a plurality of pedestals, each of which is in electrical contact with one of the LEDs. A coating at least partially covers the LEDs with at least some of the pedestals extending through and to the surface of the coating. The pedestals are exposed at the surface of the coating. One embodiment of a light emitting diode (LED) chip manufactured using methods according to the present invention comprises an LED on a substrate and a pedestal in electrical contact with the LED. A coating at least partially covering the LED, with the pedestal extending through and to the surface of the coating and exposed at the surface of the coating. In accordance with certain aspects of the present invention, the coating can include phosphor particles that downconvert at least some of the light emitted from the active region of the LED chip to produce white light, thereby producing a white LED chip. These and other aspects and advantages of the invention will become apparent from the following detailed description and the accompanying drawings which illustrate by way of example the features of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1a through 1e are sectional views of one embodiment of an LED chip wafer at fabrication steps in one method according to the present invention; FIG. 2 is a sectional view of another embodiment of an LED chip wafer according to the present invention having a reflective layer; FIGS. 3 through 3e are sectional views of one embodiment of an flip-wafer bonded LED chip wafer at fabrication steps in another method according to the present invention; FIG. 4 is a sectional view of another embodiment of an LED chip wafer according to the present invention having a reflective layer; FIGS. 5a through 5d are sectional views of another embodiment of an LED chip wafer at fabrication steps in a method according to the present invention utilizing a prefabricated coating; FIGS. 6a through 6c are sectional views of another embodiment of an LED chip wafer at fabrication steps in a method according to the present invention having recesses in the coating; FIG. 7 is a sectional view of another embodiment of an LED chip wafer according to the present invention; FIG. 8 is also a sectional view of another embodiment of an LED chip wafer according to the present invention; FIG. 9 is a sectional view of one embodiment of an LED array according to the present invention; FIG. 10 is a sectional view of another embodiment of an LED array according to the present invention; FIG. 11 is a sectional view of an embodiment of an LED chip wafer according to the present invention having a transparent substrate; FIG. 12 is a sectional view of another embodiment of an LED chip wafer according to the present invention having a transparent substrate; FIG. 13 is a sectional view of another embodiment of an flip-chip LED chip wafer according to the present invention; FIG. 14 is a sectional view of another embodiment of an LED chip having a phosphor loading carrier substrate; FIGS. 15a through 15d are sectional views of another embodiment of an LED chip wafer at fabrication steps in a method according to the present invention utilizing a trenched substrate. DETAILED DESCRIPTION OF THE INVENTION The present invention provides fabrication methods that are particularly applicable to wafer level coating of semiconductor devices such as LEDs. The present invention also provides semiconductor devices, such as LEDs fabricated using these methods. The present invention allows coating of LEDs at the wafer level with a down-converter layer (e.g. phosphor loaded silicone) while still allowing access to one or more of the contacts for wire bonding. According to one aspect of the present invention, electrically conducting pedestals/posts are formed on one or both of the LED contacts (bond pads) while the LEDs are at the wafer level. These pedestals can be fabricated using known techniques such as electroplating, electroless plating, stud bumping, or vacuum deposition. The wafer can then be blanket coated with a down-converter coating layer, burying the LEDs, contacts and pedestals. Each of the pedestals act as a vertical extension of its contact, and although the blanket coating with the down-converter coating temporarily covers the pedestals, the coating can be planarized and thinned to expose the top surface or top portion of the pedestals. The pedestals should be tall enough (10-100 μm) to project through the desired final coating thickness. After planarizing the pedestals are exposed for external connection such as by wire bonding. This process occurs at the wafer level and as a subsequent fabrication step, the individual LEDs chips can be separated/singulated from the wafer using known processes. The present invention eliminates complex wafer fabrication processes to access wire bond pads after blanket coating. Instead a simple and cost effective approach is utilized. It allows for wafer level coating of semiconductor devices without the need for alignment. A wide variety of coating technologies can be used such as spin-coating of phosphor loaded silicone mixture, or electrophoretic deposition of phosphor followed by blanket coating of silicone or other binding material. Mechanical planarization allows thickness uniformity over the wafer and thickness uniformity of the coat can be achieved over a wide thickness range (e.g. 1 to 100 μm). White LED chip color point may be fine tuned by controlling the final coat thickness, including using an iterative approach (e.g. grind, test, grind, etc.) which will result in tightly binned white LEDs. This approach is also scalable to large wafer sizes. The present invention is described herein with reference to certain embodiments but it is understood that the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In particular, the present invention is described below in regards to coating LEDs with a down-converter coating that typically comprises a phosphor loaded binder (“phosphor/binder coating”), but it is understood that the present invention can be used to coat LEDs with other materials for down-conversion, protection, light extraction or scattering. It is also understood that the phosphor binder can have scattering or light extraction particles or materials, and that the coating can be electrically active. The methods according to the present invention can also be used for coating other semiconductor devices with different materials. Additionally, single or multiple coatings and/or layers can be formed on the LEDs. A coating can include no phosphors, one or more phosphors, scattering particles and/or other materials. A coating may also comprise a material such as an organic dye the provides down-conversion. With multiple coatings and/or layers, each one can include different phosphors, different scattering particles, different optical properties, such as transparency, index of refraction, and/or different physical properties, as compared to other layers and/or coatings. It is also understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. Furthermore, relative terms such as “inner”, “outer”, “upper”, “above”, “lower”, “beneath”, and “below”, and similar terms, may be used herein to describe a relationship of one layer or another region. It is understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Embodiments of the invention are described herein with reference to cross-sectional view illustrations that are schematic illustrations of idealized embodiments of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances are expected. Embodiments of the invention should not be construed as limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. A region illustrated or described as square or rectangular will typically have rounded or curved features due to normal manufacturing tolerances. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the invention. FIGS. 1a through 1e show one embodiment of wafer level LED chips 10 manufactured using a method according to the present invention. Referring now to FIG. 1a, the LEDs chips 10 are shown at a wafer level of their fabrication process. That is, the LEDs chips 10 have not been through all the steps necessary before being separated/singulated from wafer into individual LED chips. Phantom lines are included to show separation or dicing line between the LED chips 10 and following additional fabrication steps, and as shown in FIG. 1e the LEDs chips can be separated into individual devices. FIGS. 1a through 1e also show only two devices at the wafer level, but it is understood that many more LED chips can be formed from a single wafer. For example, when fabricating LED chips having a 1 millimeter (mm) square size, up to 4500 LED chips can be fabricated on a 3 inch wafer. Each of the LED chips 10 comprises a semiconductor LED 12 that can have many different semiconductor layers arranged in different ways. The fabrication and operation of LEDs is generally known in the art and only briefly discussed herein. The layers of the LED 10 can be fabricated using known processes with a suitable process being fabrication using metal organic chemical vapor deposition (MOCVD). The layers of the LEDs 12 generally comprise an active layer/region 14 sandwiched between first and second oppositely doped epitaxial layers 16, 18, all of which are formed successively on a substrate 20. In this embodiment the LEDs 12 are shown as separate devices on the substrate 20. This separation can be achieved by having portions of the active region 14 and doped layers 16, 18 etched down to the substrate 20 to form the open areas between the LEDs 12. In other embodiments and as described in more detail below, the active layer 14 and doped layers 16, 18 can remain continuous layers on the substrate 20 and can be separated into individual devices when the LED chips are singulated. It is understood that additional layers and elements can also be included in the LED 12, including but not limited to buffer, nucleation, contact and current spreading layers as well as light extraction layers and elements. The active region 14 can comprise single quantum well (SQW), multiple quantum well (MQW), double heterostructure or super lattice structures. In one embodiment, the first epitaxial layer 16 is an n-type doped layer and the second epitaxial layer 18 is a p-type doped layer, although in other embodiments the first layer 16 can be p-type doped and the second layer 18 n-type doped. The first and second epitaxial layers 16, 18 are hereinafter referred to as n-type and p-type layers, respectively. The region 14 and layers 16, 18 of the LEDs 12 may be fabricated from different material systems, with preferred material systems being Group-III nitride based material systems. Group-III nitrides refer to those semiconductor compounds formed between nitrogen and the elements in the Group III of the periodic table, usually aluminum (Al), gallium (Ga), and indium (In). The term also refers to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN) and aluminum indium gallium nitride (AlInGaN). In a preferred embodiment, the n- and p-type layers 16, 18 are gallium nitride (GaN) and the active region 14 is InGaN. In alternative embodiments the n- and p-type layers 16, 18 may be AlGaN, aluminum gallium arsenide (AlGaAs) or aluminum gallium indium arsenide phosphide (AlGaInAsP). The substrate 20 can be made of many materials such at sapphire, silicon carbide, aluminum nitride (AlN), GaN, with a suitable substrate being a 4H polytype of silicon carbide, although other silicon carbide polytypes can also be used including 3C, 6H and 15R polytypes. Silicon carbide has certain advantages, such as a closer crystal lattice match to Group III nitrides than sapphire and results in Group III nitride films of higher quality. Silicon carbide also has a very high thermal conductivity so that the total output power of Group-III nitride devices on silicon carbide is not limited by the thermal dissipation of the substrate (as may be the case with some devices formed on sapphire). SiC substrates are available from Cree Research, Inc., of Durham, N.C. and methods for producing them are set forth in the scientific literature as well as in a U.S. Pat. Nos. Re. 34,861; 4,946,547; and 5,200,022. In the embodiment shown, the substrate 20 is at the wafer level, with the plurality of LEDs 12 formed on the wafer substrate 20. Each of the LEDs 12 can have first and second contacts 22, 24. In the embodiment shown, the LEDs have a vertical geometry with the first contact 22 on the substrate 20 and the second contact 24 on the p-type layer 18. The first contact 22 is shown as one layer on the substrate, but when the LED chips are singulated from the wafer the first contact 22 will also be separated such that each LED chip 10 has its own portion of the first contact 22. An electrical signal applied to the first contact 22 spreads into the n-type layer 16 and a signal applied to the second contact 24 spreads into the p-type layer 18. In the case of Group-III nitride devices, it is well known that a thin semitransparent current spreading layer typically covers some or all of the p-type layer 18. It is understood that the second contact 24 can include such a layer which is typically a metal such as platinum (Pt) or a transparent conductive oxide such as indium tin oxide (ITO). The first and second contacts 22, 24 are hereinafter referred to as the n-type and p-type contacts respectively. The present invention can also be used with LEDs having lateral geometry wherein both contacts are on the top of the LEDs. A portion of the p-type layer 18 and active region is removed, such as by etching to expose a contact mesa on the n-type layer 16. The boundary of the removed portion of the of the active region 14 and p-type layer 18 is designated by vertical phantom line 25. A second lateral n-type contact 26 (also shown in phantom) is provided on the mesa of the n-type layer 16. The contacts can comprise known materials deposited using known deposition techniques. Referring now to FIG. 1b, and according to the present invention, a p-type contact pedestal 28 is formed on the p-type contact 24 that is utilized to make electrical contact to the p-type contact 24 after coating of the LEDs 12. The pedestal 28 can be formed of many different electrically conductive materials and can be formed using many different known physical or chemical deposition processes such as electroplating, electroless plating, or stud bumping, with the preferred contact pedestal being gold (Au) and formed using stud bumping. This method is typically the easiest and most cost effective approach. The pedestal 28 can be made of other conductive materials beyond Au, such as copper (Cu) or nickel (Ni) or Indium, or combinations thereof. The process of forming stud bumps is generally known and only discussed briefly herein. Stud bumps are placed on the contacts (bond pads) through a modification of the “ball bonding” process used in conventional wire bonding. In ball bonding, the tip of the bond wire is melted to form a sphere. The wire bonding tool presses this sphere against the contact, applying mechanical force, heat, and/or ultrasonic energy to create a metallic connection. The wire bonding tool next extends the gold wire to the connection pad on the board, substrate, or lead frame, and makes a “stitch” bond to that pad, and finishes by breaking off the bond wire to begin another cycle. For stud bumping, the first ball bond is made as described, but the wire is then broken close above the ball. The resulting gold ball, or “stud bump” remains on the contact and provides a permanent, reliable connection through to the underlying contact metal. The stud bumps can then be flattened (or “coined”) by mechanical pressure to provide a flatter top surface and more uniform bump heights, while at the same time pressing any remaining wire into the ball. The height of the pedestal 28 can vary depending on the desired thickness of the phosphor loaded binder coating and should be high enough to match or extend above the top surface of the phosphor loaded binder coating from the LED. The height can exceed 200 μm, with typical pedestal height in the range of 20 to 60 μm. In some embodiments, more than one stud bump can be stacked to achieve the desired pedestal height. The stud bumps or other forms of the pedestal 28 can also have a reflecting layer or can be made of a reflective material to minimize optical losses. For the vertical geometry type LEDs 12 shown, only one pedestal 28 is needed for the p-type contact 24. For alternative lateral geometry LEDs a second n-type pedestal 30 (shown in phantom) is formed on the lateral geometry n-type contact 26, typically of the same materials, to substantially the same height as the p-type pedestal 28, and formed using the same processes. Referring now to FIG. 1c, the wafer is blanketed by a phosphor/binder coating 32 that covers each of the LEDs 12, and its contact 22, and has a thickness such that it covers/buries the pedestal 28. For lateral geometry devices, the contact 26 and pedestal 30 are also buried. The present invention provides the advantage of depositing the phosphor coating over the LEDs 12 at the wafer level without the need for alignment over particular devices or features. Instead, the entire wafer is covered, which provides for a simpler and more cost effective fabrication process. The phosphor coating can be applied using different processes such as spin coating, electrophoretic deposition, electrostatic deposition, printing, jet printing or screen printing. In a preferred embodiment, the phosphor can be deposited over the wafer in a phosphor/binder mixture using spin coating. Spin coating is generally known in the art and generally comprises depositing the desired amount of binder and phosphor mixture at the center of the substrate and spinning the substrate at high speed. The centrifugal acceleration causes the mixture to spread to and eventually off the edge of the substrate. Final layer thickness and other properties depend on the nature of the mixture (viscosity, drying rate, percent phosphor, surface tension, etc.) and the parameters chosen for the spin process. For large wafers it may be useful to dispense the phosphor/binder mixture over the substrate before spinning the substrate at high speed. In another embodiment, the phosphor is deposited on the wafer using known electrophoretic deposition methods. The wafer and its LEDs are exposed to a solution containing phosphor particles suspended in a liquid. An electrical signal is applied between the solution and the LEDs which creates an electrical field that causes the phosphor particles to migrate to and deposit on the LEDs. The process typically leaves the phosphor blanketed over the LEDs in powder form. A binder can then be deposited over the phosphor with the phosphor particles sinking into the binder to form the coating 32. The binder coating can be applied using many known methods and in one embodiment, the binder coating can be applied using spin coating. The phosphor/binder coating 32 can then be cured using many different curing methods depending on different factors such as the type of binder used. Different curing methods include but are not limited to heat, ultraviolet (UV), infrared (IR) or air curing. Different factors determine the amount of LED light that will be absorbed by the phosphor/binder coating in the final LED chips, including but not limited to the size of the phosphor particles, the percentage of phosphor loading, the type of binder material, the efficiency of the match between the type of phosphor and wavelength of emitted light, and the thickness of the phosphor/binding layer. These different factors can be controlled to control the emission wavelength of the LED chips according to the present invention. Different materials can be used for the binder, with materials preferably being robust after curing and substantially transparent in the visible wavelength spectrum. Suitable material include silicones, epoxies, glass, spin-on glass, BCB, polymides and polymers, with the preferred material being silicone because of its high transparency and reliability in high power LEDs. Suitable phenyl- and methyl-based silicones are commercially available from Dow® Chemical. In other embodiments, the binder material can be engineered to be index matched with the features such as the chip (semiconductor material) and growth substrate, which can reduce total internal reflection (TIR) and improve light extraction. Many different phosphors can be used in the coating 32 according to the present invention. The present invention is particularly adapted to LED chips emitting white light. In one embodiment according to the present invention LEDs 12 emit light in the blue wavelength spectrum and the phosphor absorbs some of the blue light and re-emits yellow. The LED chips 10 emit a white light combination of blue and yellow light. In one embodiment the phosphor comprises commercially available YAG:Ce, although a full range of broad yellow spectral emission is possible using conversion particles made of phosphors based on the (Gd,Y)3(Al,Ga)5O12:Ce system, such as the Y3Al5O12:Ce (YAG). Other yellow phosphors that can be used for white emitting LED chips include: Tb3-xRExO12:Ce(TAG); RE=Y, Gd, La, Lu; or Sr2-x-yBaxCaySiO4:Eu. First and second phosphors can also be combined for higher CRI white of different white hue (warm white) with the yellow phosphors above combined with red phosphors. Different red phosphors can be used including: SrxCa1-xS:Eu, Y; Y=halide; CaSiAlN3:Eu; or Sr2-yCaySiO4:Eu Other phosphors can be used to create saturated color emission by converting substantially all light to a particular color. For example, the following phosphors can be used to generate green saturated light: SrGa2S4:Eu; Sr2-yBaySiO4:Eu; or SrSi2O2N2:Eu. The following lists some additional suitable phosphors used as conversion particles in an LED chips 10, although others can be used. Each exhibits excitation in the blue and/or UV emission spectrum, provides a desirable peak emission, has efficient light conversion, and has acceptable Stokes shift: Yellow/Green (Sr,Ca,Ba)(Al,Ga)2S4:Eu2+ Ba2(Mg,Zn)Si2O7:Eu2+ Gd0.46Sr0.31Al1.23OxF1.38:Eu2+0.06 (Ba1-x-ySrxCay)SiO4:Eu Ba2SiO4:Eu2+ Red Lu2O3:Eu3+ (Sr2-xLax)(Ce1-xEux)O4 Sr2Ce1-xEuxO4 Sr2-xEuxCeO4 SrTiO3:Pr3+,Ga3+ CaAlSiN3:Eu2+ Sr2Si5N8:Eu2+ Different sized phosphor particles can be used including but not limited to 10-100 nanometer (nm)-sized particles to 20-30 μm sized particles, or larger. Smaller particle sizes typically scatter and mix colors better than larger sized particles to provide a more uniform light. Larger particles are typically more efficient at converting light compared to smaller particles, but emit a less uniform light. In one embodiment, the particle sizes are in the range of 2-5 μm. In other embodiments, the coating 32 can comprise different types of phosphors or can comprise multiple phosphor coatings for monochromatic or polychromatic light sources. The coating 32 can also have different concentrations or loading of phosphor materials in the binder, with a typical concentration being in range of 30-70% by weight. In one embodiment, the phosphor concentration is approximately 65% by weight, and is preferably uniformly dispersed throughout the binder. Still in other embodiments the coating can comprise multiple layers of different concentrations of types of phosphors, or a first coat of clear silicone can be deposited followed by phosphor loaded layers. As discussed above, the pedestal 28 (and pedestal 30 for lateral devices) are buried by the coating 32, which allows for the LED chips 10 to be coated without the need for alignment. After the initial coating of the LED chips, further processing is needed to expose the pedestal 28. Referring now the FIG. 1d, the coating 32 is thinned or planarized so that the pedestals 28 are exposed through the coating's top surface. Many different thinning processes can be used including known mechanical processes such as grinding, lapping or polishing, preferably after the binder has cured. Other fabrication methods can comprise a squeegee to thin the coating before cured or pressure planarization can also be used before the coating is cured. Still in other embodiments the coating can be thinned using physical or chemical etching, or ablation. The thinning process not only exposes the pedestals, but also allows for planarizing of the coating and for control of the final thickness of the coating. Following planarization, the surface root mean squared roughness of the coating should be approximately 10 nm or less, although the surface can have other surface roughness measurements. In some embodiments the surface can be textured during planarization. In other embodiments, after planarization the coating or other surfaces, can be textured such as by laser texturing, mechanical shaping, etching (chemical or plasma), or other processes, to enhance light extraction. Texturing results in surface features that are 0.1-5 μm tall or deep, and preferably 0.2-1 μm. In other embodiments, the surface of the LEDs 12 can also be textured or shaped for improved light extraction. Referring now to FIG. 1e, the individual LED chips 10 can be singulated from the wafer using known methods such as dicing, scribe and breaking, or etching. The singulating process separates each of the LED chips 10 with each having substantially the same thickness of coating 32, and as a result, substantially the same amount of phosphor and emission characteristics. This allows for reliable and consistent fabrication of LED chips 10 having similar emission characteristics. Following singulating the LED chips can be mounted in a package, or to a submount or printed circuit board (PCB) without the need for further processing to add phosphor. In one embodiment the package/submount/PCB can have conventional package leads with the pedestals electrically connected to the leads. A conventional encapsulation can then surround the LED chip and electrical connections. In another embodiment, the LED chip can be enclosed by a hermetically sealed cover with an inert atmosphere surrounding the LED chip at or below atmospheric pressure. For the LED chips 10, light from the LED 12 that is emitted toward substrate 20 can pass out of the LED chip 10 through the substrate without passing through the phosphor/binder coating 32. This can be acceptable for generating certain colors or hues of light. In embodiments where this substrate emission is to be prevented or minimized, the substrate 20 can be opaque so that light from the LED 12 emitted toward the substrate 20 is blocked or absorbed so that most light emitting from the LED chip 10 comes from light passing through the coating 32. FIG. 2 shows anther embodiment of a LED chips 40 that are similar to the LED chips 10 described above and shown in FIGS. 1a through 1e, but having additional features to encourage emission of LED chip light toward the top of the LED chips 40 and minimize light passing into the substrate 20. For similar features as those in LED chips 10, the same reference numbers will be used herein. Each of the LED chips 40 comprises LEDs 12 formed on a substrate 20 and having n-type layer 16, active region 14 and p-type layer 18 formed successively on the substrate 20. LED chips 40 further comprise n-type contact 22, p-type contact 24, p-type pedestal 28 and coating 32. The coating 32 is planarized to expose the pedestal 28. The LED chips 40 can alternatively have lateral geometry with the additional pedestal 30 LED chips 40 also comprise a reflective layer 42 that is arranged to reflect light emitted from the active region toward the substrate 20, back toward the top of the LED chips 40. This reflective layer 42 reduces the emission of light from the LEDs 12 that does not pass through conversion material before emitting from the LED chips 40, such as through the substrate 20 and encourages emission toward the top of the LED chips 40 and through the coating 32. The reflective layer 42 can be arranged in different ways and in different locations in the LED chip 40, with the layer 42 as shown arranged between the n-type layer 16 and the substrate 20. The layer can also extend on the substrate 20 beyond the vertical edge of the LED chips 12. In other embodiments the reflective layer is only between the n-type layer 16 and the substrate. The layer 42 can comprise different materials including but not limited to a metal or a semiconductor reflector such as a distributed Bragg reflector (DBR). As mentioned above, in some embodiments the active region 14 and the n- and p-type layers 16, 18 can be continuous layers on the substrate 20 as shown by phantom lines between the LEDs 12. In these embodiments, the LEDs are not separated until the step when the LED chips 40 are singulated. Accordingly, the resulting LED chips may have a layer of the coating 32 over the top surface of the LEDs. This can allow for emission of the active region light out the side surfaces of the LEDs 12, but in embodiments utilizing this LEDs in relation to the surrounding features, this emission of light without encountering phosphor material can be minimal compared to the amount of light passing through the phosphor material. The methods according to the present invention can be used to coat many different devices and LEDs. FIGS. 3a through 3e show a different LED chip 60 having a structure different from the LED chip 10 described above and shown in FIGS. 1a through 1e. Referring first to FIG. 3a, the LED chip 60 is also at wafer level and shown prior to singulating. It comprises LEDs 62 that are not on a growth substrate, but are instead flip-wafer bonded to a carrier substrate 64. In this embodiment, the growth substrate can comprise the materials described above for growth substrate 20 in FIGS. 1a through 1e, but in this embodiment the growth substrate is removed after (or before) flip-wafer bonding, with the substrate removed using known grinding and/or etching processes. The LEDs 62 are mounted to the carrier substrate 64 by layer 66, which is typically one or more bond/metal layers, and which also serve to reflect light incident on it. In other embodiments, the growth substrate or at least portions thereof remain. The growth substrate or the remaining portions can be shaped or textured to enhance light extraction from the LEDs 62. Many different material systems can be used for the LEDs, with a preferred material system being the Group-III nitride material system grown using known processes as described above. Like the LEDs 12 in FIGS. 1-5, each of the LEDs 62 generally comprises an active region 68 sandwiched between n-type and p-type epitaxial layers 70, 72 although other layers can also be included. Because LEDs 62 are flip-wafer bonded, the top layer is the n-type layer 70, while the p-type layer 72 is the bottom layer arranged between the active region 68 and the bond/metal layer 66. The carrier substrate can be many different known materials, with a suitable material being silicon. For vertical geometry LED chips 60, an n-type contact 74 can be included on top surface of each of the LEDs, and a p-type contact 76 can be formed on the carrier substrate 64. The n- and p-type contacts 74, 76 can also be made of conventional conductive materials deposited using known techniques similar to the first and second contacts 22, 24 shown in FIGS. 1a through 1e and described above. As also described above, the LEDs can have a lateral geometry with the n- and p-type contacts on the top of the LEDs. Referring now to FIG. 3b, each of the LED chips 60 can have a pedestal 78 formed on its first contact 70, with each pedestal being formed of the same material and using the same methods as those described above for pedestal 28 in FIGS. 1b through 1e. As shown in FIG. 3c the LED chip wafer can then be covered by a blanket coating 80 preferably comprising a phosphor loaded binder. The same phosphors and binder can be used as those for the coating 32 described above and shown in FIGS. 1c through 1e, and can be deposited using the same methods. The coating 80 covers and buries the LEDs 62, their first contacts 74 and the pedestals 78, with the coating 80 being deposited without alignment steps. Referring now to FIG. 3d, the coating 80 can be planarized or thinned to expose the pedestals 78 and to control thickness of the coating 80 using the methods described above. Referring now to FIG. 3e, the individual LED chips 60 can be singulated from the wafer using the methods described above. These devices can then be packaged or mounted to a submount or PCB. In other embodiments the carrier substrate can be removed, leaving a coated LED that can then be packaged or mounted to a submount or PCB. The flip-wafer bonded LEDs can also have reflective elements or layers to encourage light emission in the desired direction. FIG. 4 shows LED chips 90 at the wafer level that are similar to the LED chips 60 shown in FIGS. 3a through 3e and described above. For similar features the same reference numbers are used herein, and although LED chips 90 are shown having vertical geometry LEDs 62, it is understood that lateral geometry LEDs can also be used. The LED chips 90 comprise LEDs 62 mounted to a substrate 64 that can either be a carrier or growth substrate. Each of the LEDs 62 comprises an active layer 68, n-type layer 70, p-type layer 72, p-type contact 76, n-type contact 74, and pedestal 78 as described above, and a phosphor loaded binder coating 80 is formed over the LEDs also as described above. In this embodiment, however, a reflective layer 92 is included between the LEDs 62 and the substrate 64 that can comprise a highly reflective metal or reflective semiconductor structures such as a DBR. The reflective layer 92 reflects LED light that is emitted toward the substrate 64 and helps prevent light from passing into the substrate where at least some of the light can be absorbed by the substrate 64. This also encourages light emission from the LED chips 90 toward the top of the LED chips 90. It is understood that a bond/metal layer (not shown) can also be included below the reflective layer or in other locations, particularly in the embodiments where the substrate 64 is a carrier substrate. The LED chips 90 can also comprise a p-contact layer adjacent to the p-type layer 72 to encourage ohmic contact to the layers below. FIGS. 5a through 5d show another embodiment of LED chips 100 fabricated according to the present invention that are similar to the LED chips 60 described above and shown in FIGS. 3a through 3e. It is understood, however, that this method can also be used with non flip-wafer bonded embodiments such as the embodiment described above and shown in FIGS. 1a through 1e. Referring first to FIG. 5a, the LED chips 100 comprise vertical LEDs 62 mounted to a substrate 64 that in this case is a carrier substrate. It is understood that lateral LEDs can also be used as described above. Each of the LEDs 62 comprises active layer 68, n-type layer 70, p-type layer 72, p-type contact 76, n-type contact 74, and pedestal 78 as described above. For LED chips 100, however, are covered by a prefabricated coating layer 102 that can have the phosphor (and other) materials described above fixed in a binder also made of the materials described above. Referring now to FIG. 5b, the layer 102 is placed over and covering the LEDs 62 and their pedestals 78 to provide a conformal coating. In one embodiment a bonding material can be included between the layer 102 and the LED chips 100 for adhesion, with typical adhesives being used such as silicones or epoxies. To further encourage conformal coating, the layer 102 can be heated or a vacuum can be applied to pull the layer 102 down over the LED chips 100. The layer 102 can also be provided in a state where the binder is not fully cured so that the layer 102 more readily conforms to the LED chips. Following conformal placement of the layer 102, the binder can be exposed to its final curing. Referring now to FIG. 5c, the layer 102 can be planarized using the methods described above to expose the pedestals 78, making them available for contacting. As shown in FIG. 5d, the LED chips 100 can then be singulated using the methods described above. The fabrication method for LED chips 100 allows for the thickness of the phosphor/binder to be accurately controlled by controlling the thickness of the layer 102. This method also allows for the use of different layer thicknesses and composition for different desired emission characteristics for the LED chips 100. FIGS. 6a through 6c show still another embodiment of LED chips 110 according to the present invention similar to LED chips 60. Referring first to FIG. 6a, each of the LED chips 110 has vertical LEDs 62 mounted to a substrate 64 that can either be a carrier or growth substrate. Each of the LEDs 62 comprises active layer 68, n-type layer 70, p-type layer 72, p-type contact 76, n-type contact 74, and pedestal 78 as described above. A coating 112 made of the materials described above is included over the LEDs 62, burying the pedestals 78. Referring to FIG. 6b, in this embodiment the coating 112 is not planarized to expose the pedestals 78. Instead, the coating remains at a level higher than the pedestals and a portion of the coating 112 burying the pedestal 78 is removed leaving recessed portions 114 in the coating 112. The pedestals 78 are exposed through the recessed portions 114 for contacting. Many different methods can be used to remove the coating such as conventional patterning or etching processes. Referring now to FIG. 6c, the LED chips 110 can then be singulated using the methods described above. This method of forming recessed portions 114 can be used in conjunction with planarizing of the coating 112. The layer 112 can be planarized to the level that provides the desired emission characteristics of the LED chip 110, which may be above the pedestals 78. The recessed portions 114 can then be formed to access the pedestals. This allows for forming pedestals of reduced height lower than the coating, which can reduce fabrication costs related to forming the pedestals 78. This process can require some alignment with forming the recessed portions, but the coating 112 is still applied without the need for alignment. The pedestals in the LED chips embodiments above are described as comprising a conductive material such as Au, Cu, Ni or In, preferably formed using stud bumping processes. Alternatively, the pedestals can be made of different materials and can be formed using different methods. FIG. 7 shows another embodiment of LED chips 120 comprising LEDs 122 flip-wafer bonded on a carrier substrate 124. In this embodiment, the pedestal 136 comprises a semiconductor material 138 formed generally in the shape of a pedestal 136. The semiconductor material 138 can be on the first contact, or as shown can be on the first epitixial layer 130. A pedestal layer 140 of conductive material is included on the top surface of the semiconductor material 138 and extending to the top surface of the first epitaxial layer 130 and forming an n-type contact. The semiconductor material 138 can be formed in many different ways and can comprise many different materials, such as the material comprising the LED epitaxial layers or the growth substrate material, e.g. GaN, SiC, sapphire, Si, etc. In one embodiment, the semiconductor material 138 can be etched from the epitaxial layers, and then coated with the pedestal layer 140. In other embodiments, portions of the growth substrate can remain on the epitaxial layers during removal of the growth substrate from the LEDs 122. The remaining growth substrate portions can then be covered by the pedestal layer 140. FIG. 8 shows another embodiment of LED chips 150 still in wafer form that are similar to the LED chips 120 in FIG. 7, and the same reference numbers are used for similar features herein. The LED chips 150 comprise LEDs 122 flip-wafer bonded on a carrier substrate 124 by bond/metal layer 126. A pedestal 154 is formed on each of the LEDs 122, preferably on the n-type contact 155. The pedestal 154 comprises a patternable material 156 in substantially the shape of the pedestal 154 that is covered with a pedestal layer 158 of conductive material that extends to the first contact 152. The patternable material 156 can comprise different materials compatible with LED fabrication and operation such as BCB, polymides and dielectrics. These materials can be formed on the LEDs 112 using known processes. Alternatively, pedestal 154 can be formed using patternable and electrically conducting materials such as silver epoxy or printable inks, in which case layer 158 may not be required. Other methods and approaches for fabricating pedestals can be used, some of which are described in John Lau, “Flip-Chip Technologies”, McGraw Hill, 1996. Like the embodiments above, the wafer comprising the LED chips 120 and 150 can be blanketed by a layer of coating material, burying the LED chips and their pedestals. The coating material can comprise the phosphors and binders described above, and can be thinned using the methods described above to expose the pedestals through the coating materials. The LED chips can then be singulated using the methods described above. The present invention can also be used to fabricate wafer level emitter arrays. FIG. 9 shows one embodiment of wafer level LED array 170 that comprises LEDs 172 flip-wafer bonded on a carrier substrate 174 by a bond/metal layer 176. The LEDs comprise an active region 178 between first and second epitaxial layers 180, 182 with a first contact 184 on the first epitaxial layer 180. A pedestal 186 is included on the first contact 184 and a coating 188 of phosphor loaded binder coating blankets the LEDs 172, contacts 184 and pedestals 186, with the coating being thinned to expose the top of the pedestals 186. For the LED array 170 however, the individual LED chips are not singulated. Instead, an interconnecting metal pad 190 is included on the surface of the LED 172, interconnecting the exposed tops of the pedestals 186 in a parallel fashion. An electrical signal applied to the metal pad 190 conducts to the LEDs having their pedestals 186 coupled to the metal pad 190, illuminating the LEDs in an array. It is understood that the LED array can comprise many different numbers of LEDs arranged in different ways, such as in a row or block, depending on the LEDs that are interconnected by the metal pad 190. FIG. 10 shows another embodiment of an LED array 200 according to the present invention also having LEDs 202 flip-wafer bonded to a carrier substrate 204, with each of the LEDs 202 comprising an active region 208 between first and second epitaxial layers 210, 212. A first contact 214 is on the first epitixial layer 210 with a pedestal 216 formed on the first contact 214. A phosphor loaded binder coating 218 is included over the LEDs 202, first contacts 214 and pedestals 216, with the top surface of the pedestals 216 exposed. The LEDs 202 are mounted to the carrier substrate 204 by an electrically insulating bond layer 220 and a p-contact 222 is between each of the LEDs 202 and the insulating bond layer 220. Conductive vias 224 run between the p-contact and the surface of the coating 218 between the LEDs 202, and respective metal pads 226 run on the surface of the coating 118 between each of the posts 224 and a respective adjacent pedestal 216. This arrangement provides for a conductive path between the LEDs 202 such that the LEDs 202 are connected in series array, with the conductive path between the LEDs isolated from the substrate by the insulating bond layer 220. An electrical signal applied to the metal pads runs through each of the LEDs causing them to emit light in an array. It is understood that the LED array 200 can comprise many different numbers of LEDs arranged in different ways, such as in a row or block, depending on the LEDs that are interconnected by the metal pads 226. Many different LED chips having different structures can be fabricated according to the present invention. FIG. 11 shows another embodiment of LED chips 350 according to the present invention arranged similarly to the LED chips 10 shown in FIGS. 1a through 1e and described above, and for similar features the same reference numbers are used herein. The LED chips 350 have vertical geometry and comprise LEDs 12 each of which comprise an active region 14 between n-type and p-type epitaxial layers 16, 18. A pedestal 28 is formed on the p-type contact 24 with a phosphor loaded binder coating 32 covering the LEDs 12. In this embodiment however, the LEDs 12 are on a transparent substrate 352, which allows for a reflective layer 354 to be formed on the substrate 352 opposite the LEDs 12. Light from the LEDs 12 can pass through the substrate 352 and reflect back from the reflective layer 354 while experiencing minimal losses. The reflective layer 354 is shown between the contact 22 and the substrate 352, but it is understood that the reflective layer 354 can be arranged differently, such as being the bottommost layer with the contact 22 between the reflective layer 354 and the substrate 352. FIG. 12 also shows another embodiment of LED chips 370 according to the present invention also arranged similar to the LED chips in FIGS. 1a through 1e. The LED chips 370 in this embodiment have lateral geometry and comprise LEDs 12 each of which comprise an active region 14 between n-type and p-type epitaxial layers 16, 18. A portion of the p-type layer 18 and the active region 14 is etched to reveal the n-type layer 16, with p-type contact 24 on the p-type layer 18 and the n-type contact 26 on the n-type layer 16. A p-type pedestal 28 is on the p-type contact 24 and n-type pedestal 30 is on the n-type contact 26. A phosphor loaded binder coating 32 covers the LEDs 12 with the pedestals 28, 30 exposed through the coating 32. The LEDs 12 are on a transparent substrate 372 and a reflective layer 374 included on the substrate 372 opposite the LEDs 12. The LEDs 12 have a lateral geometry with an p-type contact 24 and p-type pedestal 28 on the top of each of the LEDs 12. The reflective layer 374 also reflects light from the LEDs with the light experiencing minimal loss through the substrate 372. Many different variations to the LED chips can be fabricated according to the present invention and FIG. 13 shows another embodiment of LED chips 400 having LEDs 402 having an active region 405 between n- and p-type layers 406, 408, on a growth substrate 404. It is understood that the LEDs 402 can also be provided with the growth substrate thinned or after the growth substrate has been removed. The LEDs also have n-type and p-type contacts 407, 409. The LEDs 402 are diced or singulated and flip-chip bonded to a submount/carrier wafer 410. Conductive traces 412 are formed on the submount/carrier wafer 410 with each of the LEDs 402 mounted on the traces 412, with the first trace 412a in electrical contact with the n-type layer 406 and the second trace 412b in contact with the p-type layer 408. Conventional traces can be used comprising aluminum (Al) or Au deposited using known techniques such as sputtering. The LED 402 is mounted to the traces 412 by flip-chip bonds 413 that can be arranged in conventional ways using known materials such as Au, or gold/tin solder bumps or stud bumps. It is further understood that the pedestals in FIG. 13, and in the embodiments discussed above and below, can also be made of an insulating material coated by a conductive layer. In one embodiment, the pedestals can comprise substrate material or submount/carrier wafer materiel. For the LED chips 400, the submount/carrier wafer can be fabricated with pedestals with each of the LEDs mounted between pedestals. A conductive layer can be formed over the pedestals in contact with the conductive traces or in contact with the LED using other arrangements. It is further understood that the pedestals can have many different shapes and sizes, and in one embodiment can comprise a reflective cup with an LED mounted within the cup. The cup can be coated with a conductive layer in contact with the conductive traces or the LED using other arrangements. During planarization of the phosphor binder coating, the top of the cups can be exposed for contacting. In still other embodiments, the cup can have its own pedestals that can be exposed during planarization. An n-type pedestal 414 is formed on the first trace 412a and a p-type pedestal 416 is formed on the second trace 412b, with both pedestals being formed using the methods described above. A phosphor/binder coating 418 is included over the LEDs 402, burying the pedestals 414, 416. The coating 418 can then be planarized to expose the pedestals 414, 416 for contacting, or in other embodiments the recesses can be formed in the coating to expose the pedestals 414, 416. The LED chips can then be singulated using the processes described above. The fabrication method described in conjunction with LED chips 400 allows for the use of good quality singulated LEDs 402 with the desired emission characteristics to be selected for mounting to the wafer 404. The arrangement also allows for the mounting of LEDs 402 to the wafer with larger spaces between the LEDs 402 while not wasting valuable epitaxial material through etching of the material to form the spaces. FIG. 14 shows still another embodiment of LED chips 500 according to the present invention having singulated lateral geometry LEDs 502 mounted to a carrier substrate. Each of the LEDs 502 comprises an active region 504 between n- and p-type layers 506, 508, all formed successively on a growth substrate 510. The substrate 510 can be many different materials, with the preferred substrate being a transparent material such as sapphire. The LEDs 502 are singulated with at least a portion of the growth substrate 510 remaining. The LEDs 502 are then mounted to a carrier substrate 512 with the substrate down. The carrier substrate 512 comprises a first phosphor/binder coating 514 on a transparent substrate 516. The first coating 514 can be adhesive to hold the LEDs 502 or an additional adhesive materials can be used. A p-type contact 518 is provided on the p-type layer 508 and an n-type contact 520 is provided on the n-type layer 506. The contacts 518, 520 can comprise many different materials, with the preferred material being reflective. By being reflective, the contacts 518, 520 reflect active region light making the carrier substrate 512 the primary emission surface. P-type pedestal 522 is formed on the p-type contact 518, and n-type pedestal 524 is formed on the n-type contact 520 as described above. A second phosphor/binder coating 526 is formed over the LEDs 502, burying the pedestals 522, 524. As described above, the second coating 526 can then be planarized to reveal the pedestals 522, 524. The LED chips 500 can then be singulated and this arrangement provides LED chips 500 having LEDs 502 that are surrounded by a phosphor layer provided by the first and second coating 514, 526. The singulated LED chips 500 can also be packaged as a conventional flip-chip device except with the first and second coatings providing a white-emitting LED flip chip without further phosphor processing. This embodiment provides the further advantage of ability to use good quality singulated LEDs 502 with the desired emission characteristics for mounting to the wafer carrier wafer 512, such that the resulting LED chips 502 are of good quality. The LEDs 502 can also be mounted to the wafer with larger spaces between the LEDs 502 while not wasting valuable epitaxial material through etching of the material to form the spaces. FIGS. 15a through 15d show still another embodiment of LED chips 600 according to the present invention. Referring first to FIG. 15a, each of the LED chips comprises LEDs 602 each of which has an active region 604 between n- and p-type layers 606, 608, all formed successively on a growth substrate 610 that is preferably a transparent material such as sapphire. The LEDs 602 have a lateral geometry with a reflective n-type contact 612 on the n-type layer 606 and a reflective p-type contact 614 on the p-type layer 608. An n-type pedestal 616 is formed on the n-type contact 612, and a p-type pedestal 618 is formed on the p-type contact 614. A first phosphor/binder coating 620 is provided over the LEDs 602, initially burying the pedestals 616, 618, with coating then planarized to reveal the pedestal. Referring now to FIG. 15b, trenches 622 are formed through the substrate 610 and partially into the coating 620, with the trenches arranged between the LEDs 602. The trenches 622 can be formed using many different methods such as by etching or cutting. Referring now to FIG. 15c, a second phosphor/binder coating 624 can be formed over the trench side of the substrate 610, filling the trenches 622. The second coating can then be planarized as desired. Referring to FIG. 15d, the LED chips 600 can be singulated with the LEDs 602 being surrounded by a phosphor layer provided by the first and second coatings 620, 624. The LED chips 600 provide similar advantages as the LED chips 500 in FIG. 14, and provides good quality flip-chip devices that can provide white light emission without additional phosphor processing. Referring again to FIGS. 15a and 15b, as an alternative to forming trenches 622, the growth substrate 610 can be removed entirely to expose the bottom surface of the n-type layer 606. The second phosphor/binder coating 624 can then be formed over the exposed n-type layer, and planarized as desired. The present invention can also be used to cover individual LEDs instead of those on formed in an LED chip wafer. In these embodiments, the LED chips can be singulated and then mounted in a package or to a submount or PCB. The LED chips can then be coated and planarized according to the present invention to expose the pedestal(s) for contacting. Although the present invention has been described in detail with reference to certain preferred configurations thereof, other versions are possible. Therefore, the spirit and scope of the invention should not be limited to the versions described above.	H	67H01	185H01L	33	00
11659360	US20080042159A1-20080221	Transparent Electrode for Semiconductor Light-Emitting Device	ACCEPTED	20080206	20080221	[]	H01L3300	["H01L3300", "H01L2128"]	7498611	20070523	20090303	257	099000	87893.0	HO	TU TU	[{"inventor_name_last": "Eitoh", "inventor_name_first": "Nobuo", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Muraki", "inventor_name_first": "Noritaka", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Miki", "inventor_name_first": "Hisayuki", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Watanabe", "inventor_name_first": "Munetaka", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}]	A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device includes a p-type semiconductor layer (5), a contact metal layer (1) formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer (12) formed on the contact metal layer and having a lower magnitude of resistivity on the plane of the transparent electrode than the contact metal, and a bonding pad (13) formed on the current diffusion layer. The transparent electrode is at an advantage in widening the surface of light emission in the p-type semiconductor layer, decreasing the operation voltage in the forward direction, and enabling the bonding pad to provide excellent adhesive strength.	1. A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device, comprising a p-type semiconductor layer, a contact metal layer formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer formed on the contact metal layer and having a lower magnitude of resistivity on a plane of the transparent electrode than the contact metal, and a bonding pad formed on the current diffusion layer. 2. A transparent electrode according to claim 1, wherein the bonding pad has an area of 90% or more held in contact with the current diffusion layer. 3. A transparent electrode according to claim 1, wherein the transparent electrode is formed solely of a metal. 4. A transparent electrode according to claim 1, wherein the transparent electrode contains a layer of an electroconductive oxide. 5. A transparent electrode according to claim 1, wherein the bonding pad has an area of contact with the p-type semiconductor layer that is 10% or less. 6. A transparent electrode according to claim 5, wherein the bonding pad avoids contacting the p-type semiconductor layer. 7. A transparent electrode according to claim 1, wherein the current diffusion layer has an uppermost layer covered with a layer formed of a metal. 8. A transparent electrode according to claim 1, wherein the contact metal layer is formed of a platinum group metal. 9. A transparent electrode according to claim 8, wherein the contact metal layer is formed of platinum. 10. A transparent electrode according to claim 1, wherein the contact metal layer has a thickness in a range of 0.1 to 7.5 nm 11. A transparent electrode according to claim 1, wherein the contact metal layer has a thickness of 5 nm or less. 12. A transparent electrode according to claim 1, wherein the contact metal layer has a thickness in a range of 0.5 to 2.5 nm. 13. A transparent electrode according to claim 1, wherein the current diffusion layer is formed of a metal selected from the group consisting of gold, silver and copper or an alloy containing at least one of these. 14. A transparent electrode according to claim 1, wherein the current diffusion layer is formed of gold. 15. A transparent electrode according to claim 1, wherein the current diffusion layer has a thickness in a range of 1 to 20 nm. 16. A transparent electrode according to claim 1, wherein the current diffusion layer has a thickness of 10 nm or less. 17. A transparent electrode according to claim 1, wherein the current diffusion layer has a thickness in a range of 3 to 6 nm. 18. A transparent electrode according to claim 1, wherein the bonding pad contains a first layer contacting the current diffusion layer, and the first layer is formed of at least one metal selected from the group consisting of Ti, Al, Au, and Cr or an alloy thereof. 19. A transparent electrode according to claim 1, wherein the first layer of the bonding pad has a thickness in a range of 20 to 3000 nm. 20. A transparent electrode according to claim 1, wherein the bonding pad contains a second layer formed on the first layer of the bonding pad, and the second layer is formed of at least one metal selected from Ti and Cr or an alloy thereof. 21. A transparent electrode according to claim 1, wherein the second layer of the bonding pad has a thickness in a range of 20 to 3000 nm. 22. A transparent electrode according to claim 1, wherein the bonding pad has an uppermost layer formed of Au. 23. A light-emitting device using the transparent electrode set forth in claim 1.	<SOH> BACKGROUND ART <EOH>In recent years, the GaN-based compound semiconductor materials have been attracting attention as semiconductor materials for use in the short wavelength light-emitting devices. The GaN-based compound semiconductors are formed on sapphire single crystals and various oxides and Group III-V compounds as substrates by the metal organic chemical vapor deposition method (MOCVD method), the molecular beam epitaxy method (MBE method), etc. The GaN-based compound semiconductor materials have a characteristic feature of inducing small current diffusion in the lateral direction. Though the cause for this phenomenon has not been elucidated in detail, it may be probably ascribed to the presence of numerous dislocations threading the epitaxial crystal from the substrate through the first surface. Further, the p-type GaN compound semiconductor has high specific resistance as compared with the n-type GaN compound semiconductor and is not hardly enabled by simply stacking metal on the first surface to add to the lateral expanse of electric current in the p-layer and, when fabricated in an LED configuration having a p-n junction, is enabled to emit light only directly below the positive electrode. Thus, it is common to use a transparent electrode as the p-electrode. For example, the idea of stacking Ni and Au on a p-layer and subjecting the stacked metals to an alloying treatment and consequently promoting decrease of the resistance of the p-layer and forming a positive electrode with transparent property and ohmic property, has been proposed (refer, for example, to Japanese Patent No. 2804742). For the purpose of acquiring bonding strength in the pad electrode, a structure which is enabled, by cutting off a portion of a transparent electrode and forming a pad electrode throughout on the transparent electrode and a straddle the cut-off portion, to acquire the bonding strength in the part directly contiguous to the GaN layer and at the same time attain current diffusion in the part contiguous to the transparent electrode, has been laid open to public inspection (refer, for example, to JP-A HEI 7-94782). Because a given metal ideally acquires ohmic contact, it does not necessarily follow that this metal shows a high mechanical-contact-strength. When a bonding pad is allowed to contact a semiconductor layer, the contact entails the problem that the part of this contact inevitably gives rise to an increase in the contact resistance and consequently suffers the forward voltage (V F ) to rise. In short, the bonding pad is effective in lowering the operation voltage in the forward direction when the area of contact which it produces with the semiconductor layer is decreased. This invention has for an object the provision of a transparent electrode for a gallium nitride-based compound semiconductor light-emitting device, which transparent electrode produces excellent ohmic contact and current diffusion and abounds in contact strength of bonding pad as well. The term “transparent property” as used in this invention means that the pertinent electrode is transparent to the light of a wavelength in the range of 300 to 600 nm.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a schematic view illustrating the cross section of a light-emitting device provided with a transparent electrode of this invention. FIG. 2 is a schematic view illustrating the cross section of a gallium nitride-based compound semiconductor light-emitting device provided with a transparent electrode of this invention fabricated in Example 1. FIG. 3 is a schematic view illustrating the plan view of a gallium nitride-based compound semiconductor light-emitting device provided with a transparent electrode of this invention fabricated in Example 1. FIG. 4 is a schematic view illustrating the plan view of a transparent electrode part containing a cut-off portion in a transparent electrode fabricated in Comparative Example 1. detailed-description description="Detailed Description" end="lead"?	CROSS REFERENCE TO RELATED APPLICATIONS This application is an application filed under 35 U.S.C. §111(a) claiming the benefit pursuant to 35 U.S.C. §119(e)(1) of the filing dates of Provisional Application No. 60/602,648 filed Aug. 19, 2004 and Japanese Application No. 2004-228968 filed Aug. 5, 2004 pursuant to 35 U.S.C §111 (b). TECHNICAL FIELD This invention relates to a transparent electrode and more particularly to a transparent electrode possessing excellent transparent property and ohmic property suitable for a gallium nitride-based compound semiconductor light-emitting device. BACKGROUND ART In recent years, the GaN-based compound semiconductor materials have been attracting attention as semiconductor materials for use in the short wavelength light-emitting devices. The GaN-based compound semiconductors are formed on sapphire single crystals and various oxides and Group III-V compounds as substrates by the metal organic chemical vapor deposition method (MOCVD method), the molecular beam epitaxy method (MBE method), etc. The GaN-based compound semiconductor materials have a characteristic feature of inducing small current diffusion in the lateral direction. Though the cause for this phenomenon has not been elucidated in detail, it may be probably ascribed to the presence of numerous dislocations threading the epitaxial crystal from the substrate through the first surface. Further, the p-type GaN compound semiconductor has high specific resistance as compared with the n-type GaN compound semiconductor and is not hardly enabled by simply stacking metal on the first surface to add to the lateral expanse of electric current in the p-layer and, when fabricated in an LED configuration having a p-n junction, is enabled to emit light only directly below the positive electrode. Thus, it is common to use a transparent electrode as the p-electrode. For example, the idea of stacking Ni and Au on a p-layer and subjecting the stacked metals to an alloying treatment and consequently promoting decrease of the resistance of the p-layer and forming a positive electrode with transparent property and ohmic property, has been proposed (refer, for example, to Japanese Patent No. 2804742). For the purpose of acquiring bonding strength in the pad electrode, a structure which is enabled, by cutting off a portion of a transparent electrode and forming a pad electrode throughout on the transparent electrode and a straddle the cut-off portion, to acquire the bonding strength in the part directly contiguous to the GaN layer and at the same time attain current diffusion in the part contiguous to the transparent electrode, has been laid open to public inspection (refer, for example, to JP-A HEI 7-94782). Because a given metal ideally acquires ohmic contact, it does not necessarily follow that this metal shows a high mechanical-contact-strength. When a bonding pad is allowed to contact a semiconductor layer, the contact entails the problem that the part of this contact inevitably gives rise to an increase in the contact resistance and consequently suffers the forward voltage (VF) to rise. In short, the bonding pad is effective in lowering the operation voltage in the forward direction when the area of contact which it produces with the semiconductor layer is decreased. This invention has for an object the provision of a transparent electrode for a gallium nitride-based compound semiconductor light-emitting device, which transparent electrode produces excellent ohmic contact and current diffusion and abounds in contact strength of bonding pad as well. The term “transparent property” as used in this invention means that the pertinent electrode is transparent to the light of a wavelength in the range of 300 to 600 nm. DISCLOSURE OF THE INVENTION This invention provides a transparent electrode for a gallium nitride-based compound semiconductor light-emitting device, comprising a p-type semiconductor layer, a contact metal layer formed by ohmic contact on the p-type semiconductor layer, a current diffusion layer formed on the contact metal layer and possessing a lower value of resistivity on a plane of the transparent electrode than the contact metal layer, and a bonding pad formed on the current diffusion layer. In the transparent electrode, the bonding pad has an area of 90% or more held in contact with the current diffusion layer. The transparent electrode is formed solely of a metal. It can contain a layer of an electroconductive oxide. In the transparent electrode, the bonding pad has an area of contact with the p-type semiconductor layer that is 10% or less. It can avoid contacting the p-type semiconductor layer. The current diffusion layer has an uppermost layer covered with a layer formed of a metal. The contact metal layer is formed of a platinum group metal. The contact metal layer can be limited to that formed of platinum. The contact metal layer has a thickness in the range of 0.1 to 7.5 nm, preferably 5 nm or less, more preferably in the range of 0.5 to 2.5 nm. The current diffusion layer is formed of a metal selected from the group consisting of gold, silver and copper or an alloy containing at least one of these. The current diffusion layer can be limited to that formed of gold. The current diffusion layer has a thickness in the range of 1 to 20 nm, preferably 10 nm or less, more preferably in the range of 3 to 6 nm. The bonding pad contains a first layer contacting the current diffusion layer, and the first layer contains a layer containing at least one metal selected from the group consisting of Ti, Al, Au and Cr or an alloy thereof. The first layer of the bonding pad has a thickness in the range of 20 to 3000 nm. The bonding pad can have a second layer formed on the first layer, and the second layer contains a layer formed of at least one metal selected from Ti, Cr and an alloy thereof. The second layer of the bonding pad has a thickness in the range of 20 to 3000 nm. The bonding pad has an uppermost layer formed of Au. The present invention also provides a light-emitting device which uses the transparent electrode. The transparent electrode of this invention has a p-type semiconductor layer, a contact metal layer formed on the p-type semiconductor layer, a current diffusion layer formed on the contact metal layer and a bonding pad formed on the current diffusion layer. The contact metal layer is formed of a material possessing transparent property and acquiring excellent ohmic contact. The current diffusion layer is formed of a material possessing a lower magnitude of resistivity on the plane of the transparent electrode than the contact metal layer. The bonding pad is formed of a material giving rise to fast adhesion to the current diffusion layer. Therefore, the configuration obtained will bring an effect of enlarging the light-emitting plane in the semiconductor layer, decreasing the operation voltage in the forward direction and providing the bonding pad with excellent adhesive strength. The above and other objects, characteristic features and advantages of the present invention will become apparent from the description made herein below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view illustrating the cross section of a light-emitting device provided with a transparent electrode of this invention. FIG. 2 is a schematic view illustrating the cross section of a gallium nitride-based compound semiconductor light-emitting device provided with a transparent electrode of this invention fabricated in Example 1. FIG. 3 is a schematic view illustrating the plan view of a gallium nitride-based compound semiconductor light-emitting device provided with a transparent electrode of this invention fabricated in Example 1. FIG. 4 is a schematic view illustrating the plan view of a transparent electrode part containing a cut-off portion in a transparent electrode fabricated in Comparative Example 1. BEST MODE FOR CARRYING OUT THE INVENTION The transparent electrode of this invention is made of a structure resulting from stacking a contact metal layer, a current diffusion layer and a bonding pad. It will be described below with reference to the accompanying drawings. FIG. 1 is a schematic view illustrating the cross section of a light-emitting device furnished with a transparent electrode of this invention. In FIG. 1, reference numeral 11 denotes a contact metal layer, numeral 12 an current diffusion layer and numeral 13 a bonding pad layer that comprises three layers of a first layer 131, a second layer 132 and a third layer 133. The layers 11 to 13 jointly form a transparent electrode 10 of this invention. Though the bonding pad layer is depicted to be composed of three layers in FIG. 1, it may be composed of more than three layers. Reference numeral 1 denotes a substrate, numeral 2 a GaN-based compound semiconductor layer which is composed of an n-type semiconductor layer 3, a light-emitting layer 4 and a p-type semiconductor layer 5. Reference numeral 6 denotes a buffer layer and numeral 20 a negative electrode. As depicted in FIG. 1, the bonding pad has the whole lower surface thereof contact the current diffusion layer and not contacting the semiconductor layer. For the purpose of acquiring the effect of lowering the operation voltage in the forward direction as aimed at by this invention, it is necessary that the bonding pad have preferably 90% or more, more preferably 95% or more, most preferably the whole (100%), of the area of the lower surface thereof contact the current diffusion layer. The bonding pad layer which forms the bonding part has been known in various structures using various kinds of material. Any of these known bonding pads may be adopted herein without any particular restriction. The lowermost layer 131 of the bonding pad will be called a first layer. The first layer preferably uses a material which shows an excellent adhesive property to the current diffusion layer. Particularly preferably, it contains at least one metal selected from among Ti, Al, Au and Cr or an alloy thereof. The metal to be contained therein is more preferably Au or Cr and most preferably Au. The first layer of the bonding pad preferably has a thickness in the range of 20 to 3000 nm. If the first layer is unduly thin, it will fail to acquire an effect of thorough adhesion. If it is unduly thick, it will fail to give rise to any particular advantage but will elongate the time for the process and incur waste of material. It is normally advantageous to avoid any deviation from the range specified above. The thickness is more preferably in the range of 50 to 1000 nm and most preferably in the range of 100 to 500 nm. The second layer 132 which is formed on the first layer of the bonding pad plays the role of enhancing the strength of the whole bonding pad. It is, therefore, necessary to use a comparatively strong metallic material or increase the film thickness sufficiently. Ti and Cr are preferred materials therefor. Particularly, Ti proves favorable in terms of the strength of material. This layer preferably has a thickness in the range of 20 to 3000 nm. This layer fails to acquire satisfactory strength when it is unduly thin or produce any particular advantage when it is unduly thick. The thickness is more preferably in the range of 50 to 1000 nm and most preferably in the range of 100 to 500 nm The third layer 133 (the outermost layer) of the bonding pad is preferably made of a material which shows an excellent adhesiveness to a bonding electrode. The bonding electrode uses gold more frequently than not. Au and Al are known to be the metals which show excellent adhesiveness to the gold electrode. In the two metals, gold proves particularly advantageous. The transparent electrode may have all component layers thereof formed invariably of metals and may include layers of oxides among them. When the current diffusion layer has a structure which includes a layer formed of an oxide, the oxide layer may be so constructed as to have the surface thereof covered with a thin metal layer for the purpose of increasing the mechanical adhesive strength between the bonding pad and the current diffusion layer. The bonding pad is preferably formed of a plurality of layers. For the purpose of formation thereof, any of the known methods, such as the sputtering method and the vapor deposition method, may be adopted. The plurality of layers forming the bonding pad may be stacked invariably by the same method or by methods changed halfway in the total of component layers. From the viewpoint of the adhesiveness between the adjoining layers, however, it is preferable to have all the component layers stacked in the same chamber without allowing any of the component layers to be taken out into the ambient air. Further, for the purpose of forming the bonding pad in a prescribed shape, the lift-off method which has been known long heretofore may be adopted. When the bonding pad is formed on the current diffusion layer, the deposition of the bonding pad is preferred to be preceded by a treatment which is given to the current diffusion layer for the purpose of cleaning the surface thereof. For the purpose of this, treatment, the irradiation with ultraviolet light and the heat treatment may be adopted besides the wet cleaning using an acid or an alkali and the dry cleaning resorting to exposure to a sputter or a reactive gas. Among other methods mentioned above, the cleaning by the use of a reactive gas is advantageous and the method resorting to the irradiation with ultraviolet light and using ozone proves favorable because it provides facility and promises an effect. The material of the current diffusion layer is a metal of high electric conductivity, such as a metal selected from the group consisting of gold, silver and copper, or an alloy containing at least one of the metals enumerated above, for example. Gold proves most favorable because it shows a high light transmission when it is formed into a thin film. In this case, the thickness of the current diffusion layer is preferably in the range of 1 to 20 nm. If the thickness falls short of 1 nm, the shortage will prevent the effect of electric current diffusion from being manifested fully satisfactorily. If the thickness exceeds 20 nm, the overage will possibly result in markedly lowering the ability of the current diffusion layer to transmit light and degrading the light emitting output. The thickness is more preferably 10 nm or less. By fixing this thickness in the range of 3 to 6 nm, the current diffusion layer is enabled to improve best the balance between the ability to transmit light and the effect of electric current diffusion and, when joined with the contact metal layer, allow the entire surface on the positive electrode to emit light and acquire light emission of high output. The material of the current diffusion layer may be an oxide having high electric conductivity, such as an oxide selected from the group consisting of ITO and zinc oxide or a material containing at least one of such oxides, for example. In the oxides mentioned above, ITO proves most favorable because of high electric conductivity. In this case, the thickness of the current diffusion layer is preferably in the range of 1 to 5000 nm. If this thickness falls short of 1 nm, the shortage will result in preventing the effect of electric current diffusion from being fully manifested. If the thickness exceeds 5000 nm, the overage will possibly result in markedly lowering the ability of the current diffusion layer to transmit light and degrading the output of light emission. By fixing this thickness in the range of 100 to 1000 nm, the current diffusion layer is enabled to improve best the balance between the ability to transmit light and the effect of electric current diffusion and, when joined with the contact metal layer, allow the entire surface on the positive electrode to emit light and acquire light emission of high output. As regards the performance which the contact metal layer is required to possess, the small contact resistance between this layer and the p-layer constitutes an essential factor. Further, the face-up mount type light-emitting device in which the light from the light-emitting layer is taken out from the electrode face side is required to possess an excellent ability to transmit light. As the materials available for the contact metal layer, platinum group metals, such as platinum (Pt), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir) and palladium (Pd), prove favorable from the viewpoint of the contact resistance with the p-layer. Among other materials enumerated above, Pt proves particularly advantageous because it possesses a high work function and an ability to acquire excellent ohmic contact in an unheated state with a p-type GaN compound semiconductor layer of comparatively high resistance which has not undergone a heat treatment at a high temperature. When the contact metal layer is formed of a platinum group metal, it is necessary from the viewpoint of the ability to transmit light that the thickness thereof be extremely small. The thickness of the contact metal layer is preferably in the range of 0.1 to 7.5 nm. If this thickness falls short of 0.1 nm, the shortage will render it difficult to obtain a stable thin film. If the thickness exceeds 7.5 nm, the overage will result in degrading the ability to transmit light. The thickness is more preferably 5 nm or less. It is particularly preferably in the range of 0.5 to 2.5 nm in consideration of the degradation of the ability to transmit light due to the subsequent deposition of the current diffusion layer and the stability of the formation of a film. When the current diffusion layer is absent and the contact metal layer has a small thickness, the contact metal layer suffers the electric resistance thereof in the plane direction to increase and the pad layer, namely an electric current injecting part, in combination with the p layer of comparatively high resistance, is barely allowed to diffuse electric current in the peripheral part thereof. As a result, the pattern of light emission is rendered uneven and the output of light emission is lowered. Thus, by disposing on the contact metal layer the current diffusion layer formed of a highly electroconductive metal thin film or metal oxide having a high coefficient of light transmission as a means to compensate for the electric current diffusing property of the contact metal layer, it is made possible to uniformly widen the electric current without appreciably impairing the low contact resistance or the light transmission of the platinum group metal and consequently enable acquisition of a light-emitting device of high output of light emission. At this time, the current diffusion layer has no meaning of its own entity unless the magnitude of resistivity in the plane of the electrode is smaller than the contact metal. The magnitude of the resistivity is decided by the magnitude of the resistance inherent in the material and the thickness of the film to be deposited thereon. In short, when a metal is used, the current diffusion layer can be formed in a small thickness because the metal has a small coefficient of resistance. When an electroconductive metal oxide is used, the current diffusion layer must be formed in a large thickness because the metal oxide has a large coefficient of resistance than the metal. The method for forming the contact metal layer and the current diffusion layer does not need to be particularly restricted but may be selected from among known methods, such as the vacuum deposition method and the sputtering method. The transparent electrode of this invention can be used without any restriction for the heretofore known gallium nitride-based compound semiconductor light-emitting device which, as illustrated in FIG. 1, has a gallium nitride-based compound semiconductor deposited on a substrate through a buffer layer and has an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer formed thereon. For the substrate, any of the known substrate materials including oxide single crystals, such as sapphire single crystal (Al2O3: A face, C face, M face and R face), spinel single crystal (MgAl2O4), ZnO single crystal, LiAlO2 single crystal, LiGaO2 single crystal and MgO single crystal, Si single crystal, SiC single crystal, GaAs single crystal, AlN single crystal and GaN single crystal, and boride single crystals, such as ZrB2 single crystal can be used without any restriction. Incidentally, the plane direction of the substrate is not particularly restricted. The substrate may be a just substrate or a substrate provided with an off angle. The n-type semiconductor layers, light-emitting layers and p-type semiconductor layers are widely known in various structures. These layers in such universally known structures may be used herein without any restriction. While an ordinary concentration is used particularly for the carrier concentration in the p-type semiconductor layer, the transparent electrode of this invention can be applied to a p-type semiconductor layer having a comparatively low carrier concentration approximating to 1×1017 cm−3. As the gallium nitride-based compound semiconductors available for forming these layers, the semiconductors of varying compositions which are represented by the general formula, AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1 and 0≦x+y<1), are universally known. For the gallium nitride-based compound semiconductors which form the n-type semiconductor layer, the light-emitting layer and the p-type semiconductor contemplated by this invention, the semiconductors of varying compositions which are represented by the general formula, AlxInyGa1-x-yN (0≦x≦1, 0≦y≦1 and 0≦x+y<1), can be used without any restriction. The method for growing these gallium nitride-based compound semiconductors does not need to be particularly restricted. All the methods, such as HVPE (hydride vapor phase epitaxy) and MBE (molecular beam epitaxy), which are known to grow Group III nitride semiconductors may be applied. A preferred method of growth is the MOCVD method from the viewpoint of the film thickness controlling property and the mass-producing property. The MOCVD method uses hydrogen (H2) or nitrogen (N2) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a Group III raw material, trimethyl aluminum (TMA) or triethyl aluminum (TEA) as an Al source, trimethyl indium (TMI) or triethyl indium (TEI) as an In source and ammonia (NH3) or hydrazine (N2H4) as an N source which is a Group V raw material. As the dopant, monosilane (SiH4) or disilane (Si2H6) is used as an Si raw material and germane (GeH4) is used as a Ge raw material in the n-type semiconductor, and biscyclopentadienyl magnesium (Cp2Mg) or bisethylcyclopentadienyl magnesium ((EtCp)2Mg) as a Mg raw material in the p-type semiconductor. For the purpose of forming a negative electrode contiguous to the n-type semiconductor layer of the gallium nitride-based compound semiconductor having the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer sequentially stacked on the substrate, the n-type semiconductor layer is exposed by partially removing the light-emitting layer and the p-type semiconductor layer. Thereafter, the transparent electrode of this invention is formed on the remaining p-type semiconductor layer and a negative electrode is formed on the exposed n-type semiconductor layer. As the negative electrode, negative electrodes of various compositions and structures have been universally known and any of them may be used without any particular restriction. When the light-emitting device is fabricated by using this invention, the produced device is enabled to possess a low operation voltage. Further, electronic devices, such as portable telephones, displays and panels, which incorporate chips produced by this procedure and mechanical devices, such as automobiles, computers and game machines, which incorporate such electronic devices are enabled to be operated with low electric power and are enabled to materialize high characteristic properties. Particularly in battery-operated devices, such as portable telephones, portable game machines, toys, digital cameras and automobile parts, the effect of reducing electric power and the elongation of available time can be materialized. Now, this invention will be described more specifically below with reference to examples. This invention, however, is not limited to these examples. EXAMPLE 1 FIG. 2 is a schematic view illustrating the cross section of a gallium nitride-based compound semiconductor light-emitting device fabricated in this example and FIG. 3 is a schematic view illustrating the plan view thereof. On a substrate 1 made of sapphire, an under layer 3a made of undoped GaN and measuring 8 μm in thickness, an Si-doped n-type GaN contact layer 3b measuring 2 μm in thickness, an n-type In0.1Ga0.9N cladding layer 3c measuring 250 nm in thickness, a Si-doped GaN barrier layer measuring 16 nm and an In0.2Ga0.8N well layer measuring 1.5 nm in thickness were stacked through a buffer layer 6 made of AlN up to five repetitions. Finally, a positive electrode 10 of this invention formed of a bonding pad layer 13 of a five-layer structure consisting of a Pt contact metal layer 11 measuring 1.5 nm in thickness, an Au current diffusion layer 12 measuring 5 nm in thickness, an Au layer 13a measuring 50 nm in thickness, a Ti layer 13b measuring 20 nm in thickness, an Al layer 13c measuring 10 nm in thickness, a Ti layer 13d measuring 100 nm in thickness and an Au layer 13e measuring 200 nm in thickness was formed on the p-type AlGaN contact layer of a gallium nitride-based compound semiconductor resulting from sequentially stacking a light-emitting layer 4 of a multiple quantum well structure provided with a barrier layer, an Mg-doped p-type Al0.07Ga0.93N cladding layer 5a measuring 0.01 μm in thickness, and an Mg-doped p-type Al0.02Ga0.98N contact layer 5b measuring 0.15 μm in thickness. Of the five layers forming the bonding pad, the Au layer 13a of 50 nm constituted the first layer, the Ti layer 13b of 50 nm the second layer, the Al layer 13c of 10 nm the barrier layer, the Ti layer 13d of 100 nm the layer for preventing Al and Au from being alloyed and the Au layer 13e of 200 nm the uppermost layer. Then, a negative electrode 20 of a Ti/Au two-layer structure was formed on the n-type GaN contact layer to give rise to a light-emitting device having a fetching surface on the semiconductor layer side. The positive electrode and the negative electrode were shaped as illustrated in FIG. 3. In this structure, the carrier concentration in the n-type GaN contact layer was 1×1019 cm−3, the amount of Si doped in the GaN barrier layer was 1×1018 cm−3, the carrier concentration in the p-type GaN contact layer was 5×1018 cm−3, and the amount of Mg doped in the p-type AlGaN cladding layer was 5×1019 cm3. The gallium nitride-based compound semiconductor layer was deposited by the MOCVD method under the ordinary conditions well known in the pertinent technical field. Then, the positive electrode and the negative electrode were formed by the following procedure. In the beginning, the part of the n-type GaN contact layer for forming the negative electrode by the reactive ion etching method was exposed by the following procedure. First, an etching mask was formed on the p-type semiconductor layer. This formation was carried out by the following procedure. The resist was uniformly applied to the whole surface, and the resist was removed by the known technique of lithography from the region one margin larger than the region of the positive electrode. The resultant layer was set in a vacuum deposition device and Ni and Ti were deposited in respective approximate thicknesses of 50 nm and 300 nm by the electron beam method under pressure of 4×10−4 Pa or less. Thereafter, the metal films outside the region of the positive electrode were removed together with the resist by the lift-off technique. Then, a substrate for depositing a semiconductor was mounted on the electrode inside the etching chamber of a reactive ion etching device. The substrate, with the etching chamber vacuumed to 10−4 Pa and Cl2 supplied as an etching gas, was etched till the n-type GaN contact layer was exposed. The etched substrate was withdrawn from the reactive ion etching device and was denuded of the etching mask with sulfuric acid and hydrofluoric acid. Then, exclusively in the region for forming the positive electrode on the p-type GaN contact layer, a contact metal layer of Pt and a current diffusion layer of Au were formed by using the known photolithography technique and lift-off technique. The formation of the contact metal layer and the current diffusion layer was implemented by first placing in the vacuum deposition device the substrate having the gallium nitride-based compound semiconductor layer deposited thereon and depositing first Pt in a thickness of 1.5 nm and then Au in a thickness of 5 nm on the p-type GaN contact layer. Subsequently, the resultant stacked structure was withdrawn from the vacuum chamber and processed by the universally known procedure generally called a lift-off technique. By the same procedure, the first layer 13a of Au, the second layer 13b of Ti, the barrier layer 13c of Al, the layer 13d of Ti for preventing Al and Au from being alloyed and the fifth layer 13e of Au were sequentially deposited on part of the current diffusion layer to give rise to the bonding pad layer 13. In this case, the region destined to form the pad electrode was cleaned by being irradiated with the ultraviolet light and swept with an ozone gas. The positive electrode contemplated by this invention was formed on the p-type GaN contact layer as described above. The positive electrode formed by this method showed transparency and possessed light transmission of 60% in the wavelength region of 470 nm. Incidentally, the light transmission was measured with a sample obtained by forming the contact metal layer and the current diffusion layer in a size for the measurement of light transmission. Then, the negative electrode was formed on the exposed n-type GaN contact layer in accordance with the following procedure. The resist was uniformly applied to the whole surface and it was removed by the known lithography technique from the part for forming the negative electrode on the exposed n-type GaN contact layer and the negative electrode consisting of Ti of a thickness of 100 nm and Au of a thickness of 200 nm sequentially from the semiconductor layer side was formed by the vacuum deposition method usually employed in the situation. Thereafter, the resist was removed by the known method. The wafer having the positive electrode and the negative electrode formed thereon as described above was shaved and polished on the second surface of the substrate till the thickness of the substrate decreased to 80 μm. After mark-off lines were inscribed in the wafer from the semiconductor deposited layer side by the use of a laser scriber, the wafer was severed under pressure into chips each of the square of 350 μm. When these chips were tested for voltage in the forward direction at 20 mA of an electric current applied by electrification with a probe coil, the voltage was found to be 2.9 V. Thereafter, the chips were mounted on a TO-18 can package and tested for the output of light emission by the use of an LED tester. They showed an output of light emission of 5 mW at an applied electric current of 20 mA. By the distribution of light emission on the light-emitting surface, it could be confirmed that the whole surface on the positive electrode was emitting light. COMPARATIVE EXAMPLE 1 A bonding pad having a first layer made of Ti was formed by imparting a cut-off portion 30 to part of a transparent electrode and causing a p-type semiconductor to contact the cut-off portion directly. The transparent electrode provided with the cut-off portion 30 and used in this comparative example was shaped as illustrated in FIG. 4. A gallium nitride-based compound semiconductor light-emitting device was fabricated by following the procedure of Example 1 while forming the transparent electrode as described above. When this light-emitting device was tested similarly for the voltage in the forward direction, the voltage was found to be 3.3 V, which indicates an increase from the sample of Example 1. The cause for this increase may be explained by a supposition that the formation of the bonding pad in the cut-off portion not destined to form a transparent electrode resulted in elevating the contact resistance of this part and consequently decreasing the area capable of obtaining excellent contact resistance. EXAMPLE 2 In Example 2, an electrode was formed in the following structure with a substrate having the same stacked structure as in Example 1. Specifically, a positive electrode 10 of this invention was formed of a bonding pad 13 in a five-layer structure consisting of a Pt contact metal layer 11 measuring 1.5 nm in thickness, an ITO current diffusion layer 12 measuring 100 nm in thickness and a Cr layer 13a measuring 50 nm in thickness, a Ti layer 13b measuring 20 nm in thickness, an Al layer 13c measuring 10 nm in thickness, a Ti layer 13d measuring 100 nm in thickness and an Au layer 13e measuring 200 nm in thickness. In the five layers which formed the bonding pad, the Cr layer 13a measuring 50 nm in thickness constituted a first layer, the Ti layer 13b measuring 20 nm in thickness a second layer, the Al layer 13c measuring 10 nm in thickness a barrier layer, the Ti layer 13d measuring 100 nm in thickness a layer for preventing Al and Au from being alloyed, and the Au layer 13e measuring 200 nm in thickness the uppermost layer. Then, a negative electrode 20 having a Ti/Au two-layer structure was formed on the n-type GaN contact layer to give rise to a light-emitting device having a light fetching surface on the semiconductor layer side. The positive electrode and the negative electrode were shaped in the same forms as in Example 1. A gallium nitride-based compound semiconductor light-emitting device was fabricated by following the procedure of Example 1 while forming the positive electrode and the negative electrode as described above. When this light-emitting device was tested similarly for the voltage in the forward direction, the voltage was found to be 2.9 V, i.e. a magnitude identical with that of Example 1. Thereafter, the chips were mounted on a TO-18 can package and tested for the output of light emission by the use of an LED tester. They showed an output of light emission of 5 mW at an applied electric current of 20 mA similarly to Example 1. By the distribution of light emission on the light-emitting surface, it could be confirmed that the whole surface on the positive electrode was emitting light. Though the current diffusion layer was made of ITO in Example 2, a thin layer of metal may be deposited thereon with the object of enhancing the adhesive property. A layer of tin or indium, for example, may be used for this purpose. INDUSTRIAL APPLICABILITY The electrode provided by this invention for use in the gallium nitride-based compound semiconductor light-emitting device is useful as a positive electrode for a transparent gallium nitride-based compound semiconductor light-emitting device.	H	67H01	185H01L	33	00
11797401	US20070257302A1-20071108	Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same	ACCEPTED	20071024	20071108	[]	H01L29788	["H01L29788", "H01L21336"]	7776687	20070503	20100817	438	257000	89314.0	PATEL	REEMA	[{"inventor_name_last": "Kang", "inventor_name_first": "Chang-Seok", "inventor_city": "Seongnam-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Shin", "inventor_name_first": "Yoo-Cheol", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Choi", "inventor_name_first": "Jung-Dal", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Sel", "inventor_name_first": "Jong-Sun", "inventor_city": "Yongin-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Kim", "inventor_name_first": "Ju-Hyung", "inventor_city": "Yongin-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Jeon", "inventor_name_first": "Sang-Hun", "inventor_city": "Yongin-si", "inventor_state": "", "inventor_country": "KR"}]	A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.	1. A semiconductor device, comprising: a polysilicon layer on a substrate, the polysilicon layer being a gate electrode of a transistor; a middle conductive layer and a top metal layer on the polysilicon layer; an opening through the middle conductive layer and the top metal layer exposing the polysilicon layer; and a contact plug directly connected with the polysilicon layer through the opening. 2. The semiconductor device as claimed in claim 1, wherein the top metal layer includes at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium, and the middle conductive layer includes at least one of metal nitride, conductive metal oxide, metal silicide, or metal nitride containing at least one of silicon or aluminum. 3. The semiconductor device as claimed in claim 1, wherein the contact plug is directly connected with the top metal layer and the middle conductive layer. 4. The semiconductor device as claimed in claim 1, further comprising an insulating layer between the contact plug and a sidewall of the opening, the insulating layer separating the contact plug from the top metal layer and the middle conductive layer. 5. A semiconductor device, comprising: a semiconductor substrate including a first region and a second region; a first gate structure on the first region, the first gate structure including a polysilicon layer and a first top metal layer; a second gate structure on the second region, the second gate structure including a bottom conductive layer and a second top metal layer; a first contact plug connected directly with the polysilicon layer of the first gate structure; and a second contact plug connected directly with the second top metal layer of the second gate structure. 6. The semiconductor device as claimed in claim 5, wherein the first top metal layer and the second top metal layer are made of a substantially same material, and the first top metal layer and the second top metal layer have a substantially same thickness. 7. The semiconductor device as claimed in claim 5, wherein each of the first top metal layer and the second top metal layer are made of at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium. 8. The semiconductor device as claimed in claim 5, further comprising: a first middle conductive layer between the first top metal layer and the polysilicon layer; and a second middle conductive layer between the second top metal layer and the bottom conductive layer. 9. The semiconductor device as claimed in claim 8, wherein the first gate structure includes an opening penetrating the first top metal layer and the first middle conductive layer and exposing the polysilicon layer, and the first contact plug is directly connected to the polysilicon layer through the opening. 10. The semiconductor device as claimed in claim 9, wherein the opening penetrates the first top metal layer and the first middle conductive layer, and the first contact plug fills the opening such that the contact plug is directly connected with the first top metal layer and the first middle conductive layer. 11. The semiconductor device as claimed in claim 9, further comprising: an insulating layer between the first contact plug and both the first top metal layer and the first middle conductive layer, wherein the insulating layer separates the first contact plug from the first top metal layer and the first middle conductive layer. 12. The semiconductor device as claimed in claim 8, wherein the first middle conductive layer and the second middle conductive layer are made of a substantially same material having a substantially same thickness. 13. The semiconductor device as claimed in claim 8, wherein the bottom conductive layer is made of at least one metal nitride, and the first middle conductive layer and the second middle conductive layer are made of at least one metal nitride, conductive metal oxide, metal silicide, or metal nitride including at least one of silicon or aluminum. 14. The semiconductor device as claimed in claim 13, wherein: the metal nitride includes at least one of TaN, TiN or WN; the conductive metal oxide includes at least one of IrO2 or RuO2; the metal silicide includes at least one of WSi, TiSi or CoSi; and the metal nitride including at least one of silicon or aluminum includes at least one of TiSiN, TaSiN, TaAlN or TiAlN. 15. The semiconductor device as claimed in claim 5, wherein: the semiconductor substrate contains a memory cell array region where memory transistors and selective transistors are arrayed, and a peripheral circuit region where peripheral transistors connected to the memory and the selective transistors are arrayed; the memory transistors are non-volatile memory transistors each having a memory gate insulating layer and a charge storage structure stacked sequentially between a gate electrode and the semiconductor substrate; the peripheral transistors are MOS transistors each having a peripheral gate insulating layer between a gate electrode and the semiconductor substrate; and the selective transistors are MOS transistors each having a selective gate insulating layer between a gate electrode and the semiconductor substrate. 16. The semiconductor device as claimed in claim 15, wherein the first gate structure is at least one gate electrode of the selective transistors and the peripheral transistors; and the second gate structure is at least one gate electrode of the memory transistors and the selective transistors. 17. A method of forming a semiconductor device, comprising: forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer, and a first top metal layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer, and a second top metal layer stacked sequentially; forming an interlayer dielectric layer on the first and the second gate structures; forming a first gate contact hole and a second gate contact hole to expose top surfaces of the first and the second top metal layers by patterning the interlayer dielectric layer; forming an extended first gate contact hole to expose the polysilicon layer by selectively etching the first top metal layer exposed through the first gate contact hole; and forming contact plugs to fill the extended first gate contact hole and the second gate contact hole. 18. The method as claimed in claim 17, wherein the bottom conductive layer includes at least one metal nitride, and the first middle conductive layer and the second middle conductive layer respectively include at least one metal nitride, conductive metal oxide, metal silicide, or metal nitride including silicon or aluminum. 19. The method as claimed in claim 17, further comprising: forming an etch stopping layer covering and conforming to the first and the second gate structures, wherein forming the first and the second gate contact holes includes: patterning the interlayer dielectric layer using an etchant formulation having etch selectivity to the etch stopping layer; and patterning the etch stopping layer exposed through the patterned interlayer dielectric layer to expose top surfaces of the first and the second top metal layers. 20. The method as claimed in claim 17, wherein patterning the interlayer dielectric layer further comprises: forming source/drain contact holes exposing the semiconductor substrate at sides of the first and the second gate structures, wherein the source/drain contact holes are formed simultaneously when the first and the second gate contact holes are formed. 21. The method as claimed in claim 17, wherein forming the extended first gate contact hole comprises: forming a mask pattern covering the second gate contact hole and exposing the first gate contact hole; and etching the first gate contact hole using the mask pattern as an etch mask. 22. The method as claimed in claim 17, wherein the contact plug filling the first gate contact hole is directly connected with the polysilicon layer, the first middle conductive layer, and the first top metal layer, and the contact plug filling the second gate contact hole is directly connected with the bottom conductive layer, the second middle conductive layer, and the second top metal layer. 23. A method of forming a semiconductor device, comprising: forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer and a first top metal layer, the first middle conductive layer and the first top metal layer exposing a portion of a top surface of the polysilicon layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer and a second top metal layer; forming an interlayer dielectric layer on the first and the second gate structures; patterning the interlayer dielectric layer to form a first gate contact hole and a second gate contact hole respectively exposing top surfaces of the polysilicon layer of the first gate structure and the second top metal layer of the second gate structure; and forming contact plugs connected with the polysilicon layer and the second top metal layer through the first gate contact hole and the second contact hole. 24. The method as claimed in claim 23, wherein the bottom conductive layer includes at least one metal nitride, and the first middle conductive layer and the second middle conductive layer include at least one metal nitride, conductive metal oxide, metal silicide, or metal nitride including at least one of silicon or aluminum. 25. The method as claimed in claim 23, further comprising: forming source/drain contact holes exposing the semiconductor substrate at sides of the first and the second gate structures, wherein the source/drain contact holes are formed simultaneously when the first and the second gate contact holes are formed. 26. The method as claimed in claim 23, wherein the first gate contact hole is formed on a top surface of the polysilicon layer exposed by the first middle conductive layer and the first top metal layer, such that the interlayer dielectric is interposed between the contact plug and an internal sidewall of the first gate contact hole.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to a semiconductor device having a gate contact structure capable of reducing interfacial resistance and a method of forming the same. 2. Description of the Related Art The line width of patterns composing a semiconductor device constitute an important parameter which determines an integration density of the semiconductor device. In order to increase the integration density of the semiconductor device, the line width of the patterns may be decreased to a level corresponding to an increase of the integration density. However, with conductive patterns such as gate electrodes and interconnections, the line width decrease results in an electric resistance increase which leads to resistive capacitive (RC) delay. Conventional gate electrodes may be made of a silicon-based conductive material, e.g., n+ polysilicon and/or silicide having high specific resistance, etc. Technical problems due to the line width decrease become more serious for the gate electrode than the interconnections made of metallic material. Metal gate technologies have been proposed for forming the gate electrodes with a metallic material having low specific resistance. One of these suggested technologies for forming the gate electrodes may utilize tungsten gate (W-gate) technology, where the specific resistance may be about 5.5×10 −8 Ωnm. Compared to this, the specific resistance of tungsten silicide (WSi x ) may be about 3×10 −7 Ωm to 7×10 −7 Ωm, and the specific resistance of n+ polysilicon may be about 10 5− Ωm. Notwithstanding the low specific resistance of tungsten, if the tungsten comes in direct contact with a gate insulating layer, technical problems such as degradation of reliability of the gate insulating layer may occur. Therefore, when using the tungsten-gate, as illustrated in FIG. 1 , a polysilicon layer 30 and a barrier metal layer 40 may be sequentially stacked between a tungsten layer 50 and a gate insulating layer 20 over a substrate 10 . Impurity regions 25 may define source/drain regions. The barrier metal layer 40 may serve to prevent interfacial reaction and inter-diffusion between the polysilicon layer 30 and the tungsten layer 50 . Metal nitride, e.g., tungsten nitride (WN) and/or titanium nitride (TiN), may be used for the barrier metal layer 40 . However, when the barrier metal layer 40 made of metal nitride is in contact with the polysilicon layer 30 , an electrical contact resistance between them may appear to violate Ohm's Law. Specifically, the contact resistance may be larger compared with when an ohmic contact layer is used. This increase of contact resistance causes various technical problems. For example, as shown in FIG. 2 , an increase of interfacial contact resistance due to non-ohmic contact results in a signal delay of the circuit forming an inverter. The signal delay decreases the width of pulses L 0 . . . Ln generated in the latch circuits LCH 0 . . . LCHn, which constitute a page buffer of a FLASH memory. Therefore, a width of a generating pulse may be shorter than a length required in the nth latch circuit, and thus the FLASH memory may not operate normally. These technical problems may be commonly found in most general metal gate structures having a polysilicon layer. Nonetheless, due to pitting of active region, it is difficult to overcome these technical problems by the methods suggested by related art technologies. More specifically, the gate structure may be electrically connected to the interconnection 70 by using a gate contact plug 60 . In addition, impurity regions 15 may be formed on both sides of the gate structures, and the impurity regions 15 may be electrically connected to the interconnection 70 by using source/drain contact plugs 65 . Contact holes for the gate contact plug 60 and source/drain contact plugs 65 may be formed simultaneously. Accordingly, the tungsten layer 50 and the barrier metal layer 40 may be further etched by a sum of their width (D), such that the gate contact plug 60 may be connected with the polysilicon layer 30 . However, this additional etching may cause an excessive-etching of the impurity regions 15 (i.e. active-fitting). Therefore, although the gate contact plug 60 is in direct contact the tungsten layer 50 , it becomes difficult to connect to the polysilicon layer 30 . The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is therefore directed to a semiconductor device having a gate contact structure and a method of manufacturing the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art. At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device which may include a polysilicon layer on a substrate, the polysilicon layer being a gate electrode of a transistor, a middle conductive layer and a top metal layer on the polysilicon layer, an opening through the middle conductive layer and the top metal layer exposing the polysilicon layer, and a contact plug directly connected with the polysilicon layer through the opening. The top metal layer may include at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium, and the middle conductive layer may include at least one of metal nitride, conductive metal oxide, metal silicide, or metal nitride containing at least one of silicon or aluminum. The contact plug may be directly connected with the top metal layer and the middle conductive layer. The device may also include an insulating layer between the contact plug and a sidewall of the opening, the insulating layer separating the contact plug from the top metal layer and the middle conductive layer. At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device which may include a semiconductor substrate including a first region and a second region, a first gate structure on the first region, the first gate structure including a polysilicon layer and a first top metal layer, a second gate structure on the second region, the second gate structure including a bottom conductive layer and a second top metal layer, a first contact plug connected directly with the polysilicon layer of the first gate structure, and a second contact plug connected directly with the second top metal layer of the second gate structure. The first top metal layer and the second top metal layer may be made of a substantially same material, and the first top metal layer and the second top metal layer may have a substantially same thickness. Each of the first top metal layer and the second top metal layer may be made of at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium. The device may further include a first middle conductive layer between the first top metal layer and the polysilicon layer, and a second middle conductive layer between the second top metal layer and the bottom conductive layer. The first gate structure may include an opening penetrating the first top metal layer and the first middle conductive layer and exposing the polysilicon layer, and the first contact plug is directly connected to the polysilicon layer through the opening. The opening may penetrate the first top metal layer and the first middle conductive layer, and the first contact plug may fill the opening such that the contact plug is directly connected with the first top metal layer and the first middle conductive layer. The device may further include an insulating layer between the first contact plug and both the first top metal layer and the first middle conductive layer, where the insulating layer separates the first contact plug from the first top metal layer and the first middle conductive layer. The first middle conductive layer and the second middle conductive layer may be made of a substantially same material having a substantially same thickness. The bottom conductive layer may be made of at least one metal nitride, and the first middle conductive layer and the second middle conductive layer may be made of at least one of metal nitride, conductive metal oxide, metal silicide, or metal nitride including at least one of silicon or aluminum. The metal nitride may be at least one of TaN, TiN or WN, the conductive metal oxide may be at least one of IrO 2 or RuO 2 , the metal silicides may be at least one of WSi, TiSi or CoSi, and the metal nitride may be at least one of TiSiN, TaSiN, TaAlN or TiAlN. The semiconductor substrate may contain a memory cell array region where memory transistors and selective transistors are arrayed, and a peripheral circuit region where peripheral transistors connected to the memory and the selective transistors are arrayed. The memory transistors may be non-volatile memory transistors each having a memory gate insulating layer and a charge storage structure stacked sequentially between a gate electrode and the semiconductor substrate. The peripheral transistors may be MOS transistors each having a peripheral gate insulating layer between a gate electrode and the semiconductor substrate. The selective transistors may be MOS transistors each having a selective gate insulating layer between a gate electrode and the semiconductor substrate. The first gate structure may be at least one gate electrode of the selective transistors and the peripheral transistors, and the second gate structure may be at least one gate electrode of the memory transistors and the selective transistors. At least one of the above and other features and advantages of the present invention may be realized by providing a method of forming a semiconductor device, which may include forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer, and a first top metal layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer, and a second top metal layer stacked sequentially, forming an interlayer dielectric layer on the first and the second gate structures, forming a first gate contact hole and a second gate contact hole to expose top surfaces of the first and the second top metal layers by patterning the interlayer dielectric layer, forming an extended first gate contact hole to expose the polysilicon layer by selectively etching the first top metal layer exposed through the first gate contact hole, and forming contact plugs to fill the extended first gate contact hole and the second gate contact hole. The bottom conductive layer may include at least one metal nitride, and the first middle conductive layer and the second middle conductive layer respectively may include at least one metal nitride, conductive metal oxide, metal silicide, or metal nitride including silicon or aluminum. The method may further include forming an etch stopping layer covering and conforming to the first and the second gate structures, where forming the first and the second gate contact holes may include patterning the interlayer dielectric layer using an etchant formulation having etch selectivity to the etch stopping layer, and patterning the etch stopping layer exposed through the patterned interlayer dielectric layer to expose top surfaces of the first and the second top metal layers. Patterning the dielectric layer may include forming source/drain contact holes exposing the semiconductor substrate at sides of the first and the second gate structures, where the source/drain contact holes are formed simultaneously when the first and the second gate contact holes are formed. Forming the first gate contact hole may include forming a mask pattern covering the second gate contact hole and exposing the first gate contact hole, and etching the first gate contact hole using the mask pattern as an etch mask. The contact plug filling the first gate contact hole may fill the first gate contact hole to be directly connected with the polysilicon layer, the first middle conductive layer, and the first top metal layer, and the contact plug filling the second gate contact hole may be directly connected with the bottom conductive layer, the second middle conductive layer, and the second top metal layer. At least one of the above and other features and advantages of the present invention may be realized by providing a method of forming a semiconductor device, which may include forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer and a first top metal layer, the first middle conductive layer and the first top metal layer exposing a portion of a top surface of the polysilicon layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer and a second top metal layer, forming an interlayer dielectric layer on the first and the second gate structures, patterning the interlayer dielectric layer to form a first gate contact hole and a second gate contact hole respectively exposing top surfaces of the polysilicon layer of the first gate structure and the second top metal layer of the second gate structure, and forming contact plugs connected with the polysilicon layer and the second top metal layer through the first gate contact hole and the second contact hole.	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to a semiconductor device having a gate contact structure capable of reducing interfacial resistance and a method of forming the same. 2. Description of the Related Art The line width of patterns composing a semiconductor device constitute an important parameter which determines an integration density of the semiconductor device. In order to increase the integration density of the semiconductor device, the line width of the patterns may be decreased to a level corresponding to an increase of the integration density. However, with conductive patterns such as gate electrodes and interconnections, the line width decrease results in an electric resistance increase which leads to resistive capacitive (RC) delay. Conventional gate electrodes may be made of a silicon-based conductive material, e.g., n+ polysilicon and/or silicide having high specific resistance, etc. Technical problems due to the line width decrease become more serious for the gate electrode than the interconnections made of metallic material. Metal gate technologies have been proposed for forming the gate electrodes with a metallic material having low specific resistance. One of these suggested technologies for forming the gate electrodes may utilize tungsten gate (W-gate) technology, where the specific resistance may be about 5.5×10−8 Ωnm. Compared to this, the specific resistance of tungsten silicide (WSix) may be about 3×10−7 Ωm to 7×10−7 Ωm, and the specific resistance of n+ polysilicon may be about 105−Ωm. Notwithstanding the low specific resistance of tungsten, if the tungsten comes in direct contact with a gate insulating layer, technical problems such as degradation of reliability of the gate insulating layer may occur. Therefore, when using the tungsten-gate, as illustrated in FIG. 1, a polysilicon layer 30 and a barrier metal layer 40 may be sequentially stacked between a tungsten layer 50 and a gate insulating layer 20 over a substrate 10. Impurity regions 25 may define source/drain regions. The barrier metal layer 40 may serve to prevent interfacial reaction and inter-diffusion between the polysilicon layer 30 and the tungsten layer 50. Metal nitride, e.g., tungsten nitride (WN) and/or titanium nitride (TiN), may be used for the barrier metal layer 40. However, when the barrier metal layer 40 made of metal nitride is in contact with the polysilicon layer 30, an electrical contact resistance between them may appear to violate Ohm's Law. Specifically, the contact resistance may be larger compared with when an ohmic contact layer is used. This increase of contact resistance causes various technical problems. For example, as shown in FIG. 2, an increase of interfacial contact resistance due to non-ohmic contact results in a signal delay of the circuit forming an inverter. The signal delay decreases the width of pulses L0 . . . Ln generated in the latch circuits LCH0 . . . LCHn, which constitute a page buffer of a FLASH memory. Therefore, a width of a generating pulse may be shorter than a length required in the nth latch circuit, and thus the FLASH memory may not operate normally. These technical problems may be commonly found in most general metal gate structures having a polysilicon layer. Nonetheless, due to pitting of active region, it is difficult to overcome these technical problems by the methods suggested by related art technologies. More specifically, the gate structure may be electrically connected to the interconnection 70 by using a gate contact plug 60. In addition, impurity regions 15 may be formed on both sides of the gate structures, and the impurity regions 15 may be electrically connected to the interconnection 70 by using source/drain contact plugs 65. Contact holes for the gate contact plug 60 and source/drain contact plugs 65 may be formed simultaneously. Accordingly, the tungsten layer 50 and the barrier metal layer 40 may be further etched by a sum of their width (D), such that the gate contact plug 60 may be connected with the polysilicon layer 30. However, this additional etching may cause an excessive-etching of the impurity regions 15 (i.e. active-fitting). Therefore, although the gate contact plug 60 is in direct contact the tungsten layer 50, it becomes difficult to connect to the polysilicon layer 30. The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. SUMMARY OF THE INVENTION The present invention is therefore directed to a semiconductor device having a gate contact structure and a method of manufacturing the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art. At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device which may include a polysilicon layer on a substrate, the polysilicon layer being a gate electrode of a transistor, a middle conductive layer and a top metal layer on the polysilicon layer, an opening through the middle conductive layer and the top metal layer exposing the polysilicon layer, and a contact plug directly connected with the polysilicon layer through the opening. The top metal layer may include at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium, and the middle conductive layer may include at least one of metal nitride, conductive metal oxide, metal silicide, or metal nitride containing at least one of silicon or aluminum. The contact plug may be directly connected with the top metal layer and the middle conductive layer. The device may also include an insulating layer between the contact plug and a sidewall of the opening, the insulating layer separating the contact plug from the top metal layer and the middle conductive layer. At least one of the above and other features and advantages of the present invention may be realized by providing a semiconductor device which may include a semiconductor substrate including a first region and a second region, a first gate structure on the first region, the first gate structure including a polysilicon layer and a first top metal layer, a second gate structure on the second region, the second gate structure including a bottom conductive layer and a second top metal layer, a first contact plug connected directly with the polysilicon layer of the first gate structure, and a second contact plug connected directly with the second top metal layer of the second gate structure. The first top metal layer and the second top metal layer may be made of a substantially same material, and the first top metal layer and the second top metal layer may have a substantially same thickness. Each of the first top metal layer and the second top metal layer may be made of at least one of tungsten, copper, aluminum, gold, silver, platinum, or palladium. The device may further include a first middle conductive layer between the first top metal layer and the polysilicon layer, and a second middle conductive layer between the second top metal layer and the bottom conductive layer. The first gate structure may include an opening penetrating the first top metal layer and the first middle conductive layer and exposing the polysilicon layer, and the first contact plug is directly connected to the polysilicon layer through the opening. The opening may penetrate the first top metal layer and the first middle conductive layer, and the first contact plug may fill the opening such that the contact plug is directly connected with the first top metal layer and the first middle conductive layer. The device may further include an insulating layer between the first contact plug and both the first top metal layer and the first middle conductive layer, where the insulating layer separates the first contact plug from the first top metal layer and the first middle conductive layer. The first middle conductive layer and the second middle conductive layer may be made of a substantially same material having a substantially same thickness. The bottom conductive layer may be made of at least one metal nitride, and the first middle conductive layer and the second middle conductive layer may be made of at least one of metal nitride, conductive metal oxide, metal silicide, or metal nitride including at least one of silicon or aluminum. The metal nitride may be at least one of TaN, TiN or WN, the conductive metal oxide may be at least one of IrO2 or RuO2, the metal silicides may be at least one of WSi, TiSi or CoSi, and the metal nitride may be at least one of TiSiN, TaSiN, TaAlN or TiAlN. The semiconductor substrate may contain a memory cell array region where memory transistors and selective transistors are arrayed, and a peripheral circuit region where peripheral transistors connected to the memory and the selective transistors are arrayed. The memory transistors may be non-volatile memory transistors each having a memory gate insulating layer and a charge storage structure stacked sequentially between a gate electrode and the semiconductor substrate. The peripheral transistors may be MOS transistors each having a peripheral gate insulating layer between a gate electrode and the semiconductor substrate. The selective transistors may be MOS transistors each having a selective gate insulating layer between a gate electrode and the semiconductor substrate. The first gate structure may be at least one gate electrode of the selective transistors and the peripheral transistors, and the second gate structure may be at least one gate electrode of the memory transistors and the selective transistors. At least one of the above and other features and advantages of the present invention may be realized by providing a method of forming a semiconductor device, which may include forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer, and a first top metal layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer, and a second top metal layer stacked sequentially, forming an interlayer dielectric layer on the first and the second gate structures, forming a first gate contact hole and a second gate contact hole to expose top surfaces of the first and the second top metal layers by patterning the interlayer dielectric layer, forming an extended first gate contact hole to expose the polysilicon layer by selectively etching the first top metal layer exposed through the first gate contact hole, and forming contact plugs to fill the extended first gate contact hole and the second gate contact hole. The bottom conductive layer may include at least one metal nitride, and the first middle conductive layer and the second middle conductive layer respectively may include at least one metal nitride, conductive metal oxide, metal silicide, or metal nitride including silicon or aluminum. The method may further include forming an etch stopping layer covering and conforming to the first and the second gate structures, where forming the first and the second gate contact holes may include patterning the interlayer dielectric layer using an etchant formulation having etch selectivity to the etch stopping layer, and patterning the etch stopping layer exposed through the patterned interlayer dielectric layer to expose top surfaces of the first and the second top metal layers. Patterning the dielectric layer may include forming source/drain contact holes exposing the semiconductor substrate at sides of the first and the second gate structures, where the source/drain contact holes are formed simultaneously when the first and the second gate contact holes are formed. Forming the first gate contact hole may include forming a mask pattern covering the second gate contact hole and exposing the first gate contact hole, and etching the first gate contact hole using the mask pattern as an etch mask. The contact plug filling the first gate contact hole may fill the first gate contact hole to be directly connected with the polysilicon layer, the first middle conductive layer, and the first top metal layer, and the contact plug filling the second gate contact hole may be directly connected with the bottom conductive layer, the second middle conductive layer, and the second top metal layer. At least one of the above and other features and advantages of the present invention may be realized by providing a method of forming a semiconductor device, which may include forming a first gate structure and a second gate structure on a semiconductor substrate, the first gate structure including a polysilicon layer, a first middle conductive layer and a first top metal layer, the first middle conductive layer and the first top metal layer exposing a portion of a top surface of the polysilicon layer, and the second gate structure including a bottom conductive layer, a second middle conductive layer and a second top metal layer, forming an interlayer dielectric layer on the first and the second gate structures, patterning the interlayer dielectric layer to form a first gate contact hole and a second gate contact hole respectively exposing top surfaces of the polysilicon layer of the first gate structure and the second top metal layer of the second gate structure, and forming contact plugs connected with the polysilicon layer and the second top metal layer through the first gate contact hole and the second contact hole. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which: FIG. 1 illustrates a cross-sectional view of a semiconductor device having contact plug structures according to the related art; FIG. 2 illustrates a timing diagram of the decreasing effect of the pulse width in latch circuits configuring a page buffer of a FLASH memory; FIG. 3 illustrates a plan view of a contact plug structure according to an embodiment of the present invention; FIG. 4 illustrates cross-sectional views along lines I-I′ and II-II′ of FIG. 3 according to an embodiment of the present invention; FIG. 5 illustrates a cross-sectional view along line I-I′ of FIG. 3 according to another embodiment of the present invention; FIG. 6 and FIG. 7 illustrate perspective views of a transistor structure having a contact plug structure according to an embodiment of the present invention; FIG. 8 illustrates a plan view of a cell array of a FLASH memory device having a contact plug structure according to an embodiment of the present invention; FIG. 9 illustrates a cross-sectional view of a cell array of a FLASH memory device having a contact plug structure according to an embodiment of the present invention; FIG. 10 illustrates a perspective view of a cell array of FLASH memory device having a contact plug structure according to an embodiment of the present invention; FIG. 11 illustrates a cross-sectional view of peripheral circuit transistors of FLASH memory device having a contact plug structure according to the present invention; FIGS. 12 to 14 illustrate perspective views of a cell array of FLASH memory device having contact plug structures according to embodiments of the present invention; FIGS. 15A to 15D illustrate cross-sectional views of stages of a method of forming semiconductor device according to an embodiment of the present invention; and FIGS. 16A to 16B illustrate cross-sectional views of stages of a method of forming semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Korean Patent Application No. 2006-40121, filed on May 3, 2006, in the Korean Intellectual Property Office, and entitled: “Semiconductor Devices Having Gate Contact Structure Capable of Reducing Interfacial Resistance and Methods of Forming the Same,” is incorporated by reference herein in its entirety. The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout. According to the present invention, a gate contact plug may be in direct contact with a polysilicon layer forming a gate pattern. Therefore, an increase of interfacial resistance occurring between the polysilicon and the metal nitride may be overcome. FIG. 3 illustrates a plan view of a contact plug structure according to an embodiment of the present invention. FIG. 4 illustrates cross-sectional views along lines I-I′ and II-II′ of FIG. 3 according to an embodiment of the present invention. FIG. 5 illustrates a cross-sectional view along line I-I′ of FIG. 3 according to another embodiment of the present invention. FIG. 6 and FIG. 7 illustrate perspective views of transistors having the contact plug structures according to embodiments of the present invention. Referring to FIG. 3 and FIG. 4, a device isolating layer 110 may be formed to define active regions in predetermined regions of the semiconductor substrate 100. A gate insulating layer 120 may be on the active region. A gate pattern 130 may be on top of the gate interlayer dielectric 120, and the gate pattern 130 may extend to a top of the device isolating layer 1 10 across the active region. The gate pattern 130 may be used as a gate electrode of the transistor. Impurity regions 125, which may be used as the source/drain electrodes of the transistors, may be formed in the active region at both sides of the gate pattern 130. An interlayer dielectric 140 may be formed on the gate pattern 130, and the gate pattern 130 and the interconnections 160 crossing over the impurity regions 125 may be formed on the interlayer dielectric 140. The gate pattern 130 may be a metal gate structure composed of at least one layer made of metallic material. The gate pattern 130 may include a polysilicon layer 131, a middle conductive layer 132 and a top metal layer 133, which are sequentially stacked. The polysilicon layer 131 may be formed of n+ polysilicon, and the middle conductive layer 132 may be formed of at least one selected from, e.g., a metal nitride (MNx), a conductive metal oxide (MOx), a metal silicide (MxSiy), a metal nitride composed of silicon and/or aluminum (MSixAlyNz), etc. The top metal layer 133 may be made of at least one metal selected from, e.g., tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), etc. The metal nitride may be one of, e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), etc. The conductive metal oxide may be, e.g., iridium oxide (IrO2), ruthenium oxide (RuO2), etc. The metal silicide may be one of, e.g., tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), etc. The metal nitride containing silicon or aluminum may be, e.g., titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), titanium aluminum nitride (TiAlN), etc. The middle conductive layer 132 and the top metal layer 133 may be a WN layer and a W layer, respectively. The interconnections 160 may be electrically connected to the gate pattern 130 and the impurity regions 125 through the gate contact plug 140 and the active contact plug 155. The gate contact plug 150 and the active contact plug 155 may fill the gate contact hole 145 and the active contact hole 146, respectively, and may penetrate the interlayer dielectric 140, as illustrated in FIG. 4. The gate contact hole 145 may penetrate the top metal layer 133 and the middle conductive layer 132 to expose a top surface of the polysilicon layer 131. As a result, the gate contact plug 150 may be in direct contact with each of the polysilicon layer 131, the middle conductive layer 132 and the top metal layer 133, as illustrated in FIGS. 4 and 6. The interlayer dielectric 140 may include a lower interlayer dielectric 141 and an upper interlayer dielectric 142, which may be sequentially stacked. The upper interlayer dielectric 142 may be formed of insulating material composed of, e.g., silicon oxide, and the lower interlayer dielectric 141 may be formed to cover and conform to the resultant structure where the gate patterns 130 is formed. The lower interlayer dielectric 141 may be made of material having etch selectivity to the upper interlayer dielectric 142. The language “a layer B has etch selectivity to a layer A” means that the layer A may be selectively etched while minimizing the etching of layer B. The upper interlayer dielectric 142 may be made of, e.g., silicon oxide and the lower interlayer dielectric 141 may be made of, e.g., silicon nitride. The gate contact plug 150 may alternately only be in direct contact with the top surface of the polysilicon layer 131 among the layers composing of the gate pattern 130. In other words, the gate contact plug 150 may be separated from the middle conductive layer 132 and the top metal layer 133 to be connected with the polysilicon layer 131. More specifically, referring to FIGS. 3, 5, and 7, the top metal layer 133 and middle conductive layer 132 of the gate pattern 130 may be formed to expose the top surface of the polysilicon layer 131 in the gate contact region GTR, and the gate contact plug 150 may be in the gate contact region GTR to be in contact with the polysilicon layer 131. In this case, the interlayer dielectric 140 and a gate spacer 135 on sidewalls of the gate pattern 130 may be interposed between a sidewall of the gate contact plug 150 and sidewalls of the middle conductive layer 132 and top metal layer 133. The aforementioned gate pattern 130 and gate contact plug 150 may be used for all the transistors constructing a semiconductor device. However, referring to FIGS. 8 to 12, a portion of the transistors constructing the semiconductor device may have the aforementioned structure of gate pattern 130 and gate contact plug 150, but another portion of the transistors may have a different structure. An embodiment of the present invention disclosed will now be described which relates to a FLASH memory having a NAND-type cell array structure. However this technology may also be applied to FLASH memory devices having other types of structure (for example, NOR-type). FIG. 8 illustrates a plane view of a cell array of a FLASH memory device having contact plug structure according to an embodiment of the present invention. FIG. 9 and FIG. 10 illustrate cross-sectional views of a cell array of a FLASH memory device having contact plug structures according to embodiments of the present invention. FIG. 11 illustrates a cross-sectional view of peripheral circuit transistors of a FLASH memory device having contact plug structures according to an embodiment of the present invention. FIGS. 12 to 14 illustrate perspective views of a cell array of a FLASH memory device having contact plug devices according to an embodiment of the present invention. Referring to FIG. 8, device isolating layers 210 defining at least one active region may be formed on a semiconductor substrate 200. Gate patterns 230 may be on the active region. The semiconductor substrate 200 may include a cell array region and a peripheral circuit region. The cell array region may include a memory transistor region MTR and a selective transistor region STR on which memory transistors and selective transistors are respectively disposed. The peripheral circuit region, as shown in FIG. 11, may include a high voltage region HVR and a low voltage region LVR on which high voltage transistors and low voltage transistors are respectively disposed. The gate patterns 230 may be disposed in a direction crossing the active region and the device isolating layer 210. The gate patterns 230 may include cell gate patterns 231 and selective gate patterns 232, which may be respectively disposed in the memory transistor region MTR and the selective transistor region STR. In addition, the gate patterns 230 may include peripheral gate patterns (see 233 of FIG. 11) in the high voltage region HVR and the low voltage region LVR. The gate patterns 230 may include a first gate structure or a second gate structure. As illustrated in FIG. 12 and FIG. 13, the first gate structure may include a polysilicon layer 301, a first middle conductive layer 302 and a first top metal layer 303, which may be sequentially stacked. As illustrated in FIG. 14, the second gate structure may include a bottom conductive layer 311, a second middle conductive layer 312 and a second top metal layer 313, which may be sequentially stacked. The first top metal layer 303 and the second top metal layer 313 may be made of at least one metal selected from, e.g., W, Cu, Al, Au, Ag, Pt, Pd, etc. Also, the first middle conductive layer 302 and the second middle conductive layer 312 may be made of at least one material selected from, e.g., MNx, MOx, MxSiy, MSixAlyNz, etc. The bottom conductive layer 311 may be one of MNx materials. The first and second middle conductive layers 302, 312 and the bottom conductive layer 311 may be composed of at least one material selected from, e.g., TaN, TiN, WN, etc. The MOx may be at least one selected from, e.g., IrO2, RuO2, etc. The MxSiy may be at least one silicide selected from, e.g., WSi, TiSi, CoSi, etc. The metal nitrides composed of the silicon or aluminum may be at least one nitride selected from, e.g., TiSiN, TaAlN, TiAlN, etc. The first top metal layer 303 and the second top metal layer 313 may be made of material of substantially the same type and thickness. The first middle conductive layer 302 and the second middle conductive layer 312 may be made of material of substantially the same type and thickness. Here, “substantially the same” means that a similar result capable of neglecting any process variations may be obtained by using the same process. The first top metal layer 303 and the second top metal layer 313 may be composed of W, and the first middle conductive layer 303 and the second middle conductive layer 312 may be composed of at least one of WN or W. The selective gate patterns 232 and the peripheral gate patterns 233 may be the first gate structure, and the cell gate patterns 231 may be the second gate structure (See FIG. 9). According to another embodiment of the present invention, the peripheral gate patterns 233 may be the first gate structure, and the cell gate patterns 231 and the selective gate patterns 232 may be the second gate structure (See FIG. 10). A charge storage layer 220M may be between the cell gate pattern 231 and the active region. The charge storage layer 220M may be formed of insulating layers composed of, e.g., silicon nitride. In this case, the FLASH memory may have a structure similar to conventional SONOS or MONOS memory devices. Preferably, the charge storage layer 220M may be a high dielectric layer 321, a silicon nitride layer 322 and a silicon oxide layer 323 stacked sequentially, as illustrated in FIG. 14. The high dielectric layer 321 may be formed from at least one selected from, e.g., tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, niobium oxide, cesium oxide, indium oxide, iridium oxide, barium strontium titanate (BST), lead zirconium titanate (PZT), etc. The charge storage layer 220M may have a sequentially stacked tunnel insulating layer, a floating gate electrode and a gate interlayer dielectric. In this case, a cell structure of the FLASH memory may be similar to that of the conventional floating gate FLASH memory device. As illustrated in FIG. 9 and FIG. 10, cell impurity regions 225S may be formed in the active regions at both sides of cell gate patterns 231 and the selective gate patterns 232. A common source line CSL may be on one side of the memory transistor region MTR to connect the cell impurity regions 225S along a direction parallel with the gate pattern 230. Bit line contact plugs 255, which may be connected to each of the cell impurity regions 225S, may be on the other side of the memory transistor region MTR. The common source line CSL and the bit-line contact plugs 255 may be between the selective gate patterns 232, as illustrated in FIGS. 9 and 10. Each of the bit-line contact plugs 255 may be connected to the bit-lines 260 crossing over the gate patterns 230. An interlayer dielectric 240 may be between the bit-lines 260 and the gate patterns 230 to surround the bit-line contact plugs 255. The bit-lines 260 may be interconnections. The gate insulating layer 220H in the high voltage region HVR may be thicker than the gate insulating layer 220L in the low voltage region LVR. The gate insulating layer 220H in the high voltage region HVR may be, e.g., a silicon oxide layer having a thickness of about 200 to about 400 Å. The gate insulating layer 220L in the low voltage region LVR may be, e.g., a silicon oxide layer having a thickness of about 50 Å to about 100 Å. Except for the difference in the thickness of the gate insulating layers, peripheral gate patterns and peripheral gate contact plugs may have substantially the same structure with those illustrated in FIG. 4 or FIG. 5. The gate patterns 230 may be connected to the interconnections 260 through gate contact plugs. The gate contact plugs may include a first gate contact plug 250S connected to the first gate structure and a second gate contact plug 250M connected to the second gate structure. The first gate contact plug 250S may have a different structure from the second gate contact plug 250M. This difference between the gate contact plugs of the present invention will be discussed with reference to FIG. 12 to FIG. 14. Referring to FIG. 12, the gate pattern may include the first gate structure having the sequentially stacked polysilicon layer 301, first middle conductive layer 302 and first top metal layer 303. The first middle conductive layer 302 and the first top metal layer 303 may expose a top surface of the polysilicon layer 301 at the selective gate contact region (SGC of FIG. 8). A first gate contact plug 250S connected to the interconnections 260 may be on the exposed top surface of the polysilicon layer 301. As a result, similar to the embodiment of the present invention described with reference to FIG. 7, the first gate contact plug 250S may be directly connected with the polysilicon layer 301, but it may be separated from the first middle conductive layer 302 and the first top metal layer 303. Referring to FIG. 13, the gate pattern may also be on the first gate structure. According to this embodiment of the present invention, the first gate contact plug 250S may penetrate the first middle conductive layer 302 and the first top metal layer 303 to be connected to the polysilicon layer 301. The first gate contact plug 250S may therefore connect directly to all of the polysilicon layer 301, the first middle conductive layer 302 and the first top metal layer 303, as in the embodiment of the present invention described with reference to FIG. 6. According to the aforementioned embodiments of the present invention, the first gate contact plug 250S may be in direct contact with the polysilicon layer 301. Therefore, an increase of interfacial resistance caused by non-ohmic contact, which has been observed in the related art, may not occur in the present invention. Referring to FIG. 14, a gate pattern may be the second gate structure, which may include the sequentially stacked bottom conductive layer 311, second middle conductive layer 312, and second top metal layer 313. As described above, the bottom conductive layer 311 may be made of one of the metal nitrides. Therefore, even though the second gate contact plug 250M may be connected to the second top metal layer 313, the interfacial resistance problem due to non-ohmic contact may not occur in the second gate structure. As described above, the selective gate patterns 232 may be this second gate structure. In this case, the second gate contact plug may be used to connect the selective gate pattern 232 with the interconnections 260. FIGS. 15A to 15D illustrate process cross-sectional views of stages of a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIGS. 15A to 15D, (a) and (b) illustrate cross-sectional views showing the transistors forming peripheral circuits, and (c) and (d) illustrate cross-sectional views showing a memory cell array of a FLASH memory. Here, (a) and (c) illustrate the cross-sectional view perpendicular to the gate patterns so that the source/drain contact plug may be seen, and (b) and (d) illustrate cross-sectional views parallel to the gate patterns so that the gate contact plug may be seen. Referring to FIG. 15A, device isolating layers 210 defining active regions may be formed in a predetermined region of semiconductor substrate 200. Next, gate insulating layers 220, 220H, and 220L (See also FIG. 11) may be formed on the active region, and a gate structure may then be formed to cross over the active region. The gate structure may include the first gate structure used as the gate electrode of the transistor constructing peripheral circuit and the second gate structure used as the gate electrode of the memory cell transistor. The first and the second gate structures may be same as those illustrated in FIG. 12 to FIG. 14. The impurity regions 225 and 225S may be formed in the active region at both sides of the gate structures. Also, spacers 235 may be disposed on both sidewalls of the gate structure. Referring to FIG. 15B, an interlayer dielectric 240 may be formed on the resultant structure where the impurity regions 225 and 225S are formed. The interlayer dielectric 240 may include a lower interlayer dielectric 241 covering and conforming to the resultant structure where the gate structure is formed. The interlayer dielectric 240 may also include an upper interlayer dielectric 242 on the lower interlayer dielectric 241. The lower interlayer dielectric 241 may be made of insulating material forming the silicon oxide layer and furthermore, may be made of material having etching selectivity with respect to the upper interlayer dielectric 242. The upper interlayer dielectric 242 may be, e.g., a silicon oxide layer, and the lower interlayer dielectric 241 may be, e.g., a silicon nitride layer. Next, a first mask pattern 301 may be formed on the interlayer dielectric 240, and the interlayer dielectric 240 may be patterned using the first mask pattern 301 as an etch mask to form gate contact holes 247a and 247b and active contact holes 245, which may respectively expose the top surfaces of the gate pattern 230 and the impurity regions 225 and 225S. Preferably, the gate contact holes 247a and 247b may be formed over the device isolating layer 210. The gate contact holes may include the first gate contact hole 247a and the second gate contact hole 247b, which may be respectively formed on the first gate structure and the second gate structure. Forming the gate contact holes and active contact hole 247a, 247b, and 245 may include anisotopically etching the upper interlayer dielectric 242 by using an etchant formulation having an etch selectivity with respect to the lower interlayer dielectric 241, and anisotopically etching the lower interlayer dielectric 241 by using an etchant formulation having an etch selectivity with respect to the semiconductor substrate 200. As a result of these etching processes, the top metal layers 303 and 313 of the gate patterns 230 may be exposed by the gate contact holes 247a and 247b. Referring to FIG. 15C, the first mask pattern 301 may be removed, and a second mask pattern 302 may be formed. Here, the second mask pattern 302 may be formed to define an opening 303 exposing the first gate contact hole 247a and the first top metal layer 233 of the first gate structure. Then, the first top metal layer 233 and the first middle conductive layer 232 may be etched by using the second mask pattern 302 as an etch mask to expose the polysilicon layer 231. As a result, the extended first gate contact hole 247a′, which penetrates the first top metal layer 233 and the first middle conductive layer 232, may be formed to expose the polysilicon layer 231. Referring to FIG. 15D, the second mask pattern 302 may be removed such that a top surface of the interlayer dielectric 240 having the extended first gate contact hole 247a′, the second gate contact hole 247b and the active contact holes 245 are exposed. Next, a plug conductive layer may be formed to fill the contact holes 247a′, 247b and 245, and the plug conductive layer may be planarized until the top surface of the interlayer dielectric 240 is exposed. As a result, the process may simultaneously form a first gate contact plug 250S, a second contact plug 250M and active contact plugs 255, which fill the extended first gate contact hole 247a′, the second gate contact hole 247b and the active contact holes 245, respectively. Then, interconnections 260 may be formed to be connected with the contact plugs. The extended first gate contact hole 247a′ may expose the polysilicon layer 231 through the first top metal layer 233 and the first middle conductive layer 232. The first gate contact plug 250S may thus be in contact with all the first top metal later 233, the first middle conductive layer 232 and the polysilicon layer 231. Therefore, the interfacial resistance problem due to the aforementioned non-ohmic contact may not occur in this embodiment of the present invention. FIG. 16A and FIG. 16B illustrate a method of forming the semiconductor device according to another embodiment of the present invention. This embodiment of the present invention is related to the embodiment of the present invention of FIG. 7 and FIG. 12, and may be substantially the same as the embodiment of the present invention of FIG. 15A to FIG. 15D, except for the stages of forming the gate patterns. Therefore, redundant explanation will be omitted. Referring to FIG. 16A and FIG. 16B, after forming the gate pattern 230, the first top metal later 233 and first middle conductive layer 232 of the first gate structure may be etched in the region where the first gate contact plug 255S will be formed. Therefore, the top surface of the polysilicon layer 231 may be exposed. As shown in FIG. 16B, the first gate contact plug 250S may be in direct contact with the polysilicon layer 231 of the first gate structure. As a result, an additional process for forming the extended first gate contact hole 247a′ of the aforementioned embodiment may not be required. Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.	H	67H01	185H01L	297	88
11817597	US20090301556A1-20091210	MULTILAYER ORGANIC SOLAR CELL	ACCEPTED	20091125	20091210	[]	H01L3100	["H01L3100"]	8237048	20070831	20120807	136	256000	63248.0	GARDNER	SHANNON	[{"inventor_name_last": "Kawano", "inventor_name_first": "Kenji", "inventor_city": "Sakai-shi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Ito", "inventor_name_first": "Norihiro", "inventor_city": "Hirakata-shi", "inventor_state": "", "inventor_country": "JP"}]	Disclosed is a multilayer organic solar cell having a structure wherein an inter-layer (3) is arranged between a first photoactive layer (1) and a second photoactive layer (2). This structure is obtained by forming the inter-layer (3) on the first photoactive layer (1) which is formed from an organic compound solution containing a donor material and an acceptor material, and then applying an organic compound solution containing a donor material and an acceptor material over the inter-layer (3) for forming the second photoactive layer (2). The inter-layer (3) is composed of at least either of a transparent oxide and a transparent nitride. By having such a structure, the inter-layer (3) prevents the solvent in the solution for the second photoactive layer (2) from permeating into the first photoactive layer (1) when the second photoactive layer (2) is formed over the first photoactive layer (1) by applying the solution. Consequently, the first photoactive layer (1) is prevented from destruction or deterioration in functions.	1. A multilayer organic solar cell comprising: a first photoactive layer containing a donor material and an acceptor material; an inter-layer formed on the first photoactive layer; and a second photoactive layer formed of a solution of an organic compound containing the donor material and the acceptor material on the inter-layer, wherein the inter-layer is composed of either of a transparent oxide or a transparent nitride. 2. The multilayer organic solar cell as stated in claim 1, wherein light transmittance of the inter-layer is 70% or higher. 3. The multilayer organic solar cell as stated in claim 1, wherein the inter-layer is a layer formed by coating the first photoactive layer with a solution in which particles of at least either of a transparent oxide and a transparent nitride are dispersed in a solvent which does not dissolve the first photoactive layer. 4. The multilayer organic solar cell as stated in claim 1, wherein the inter-layer is a layer formed according to a vapor growth method. 5. The multilayer organic solar cell as stated in claim 1, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm. 6. The multilayer organic solar cell as stated in claim 2, wherein the inter-layer is a layer formed by coating the first photoactive layer with a solution in which particles of at least either of a transparent oxide and a transparent nitride are dispersed in a solvent which does not dissolve the first photoactive layer. 7. The multilayer organic solar cell as stated in claim 2, wherein the inter-layer is a layer formed according to a vapor growth method. 8. The multilayer organic solar cell as stated in claim 2, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm. 9. The multilayer organic solar cell as stated in claim 3, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm. 10. The multilayer organic solar cell as stated in claim 4, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm. 11. The multilayer organic solar cell as stated in claim 6, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm. 12. The multilayer organic solar cell as stated in claim 7, wherein a thickness of the inter-layer falls within a range of 5 to 250 nm.	<SOH> BACKGROUND ART <EOH>In recent years, energy consumption has dramatically increased with growth of industries. In the future, further increase in demand for energy is expected. Against this backdrop, today's demands are placed on the development of production technology of economic and high-performance clean energy which does not put loads the Earth's environment. Among all, a solar cell which utilizes unlimited sunlight has attracted attention as a new energy source. Most of commercialized solar cells are inorganic solar cells using single crystal silicon, polycrystal silicon or amorphous silicon. However, since these inorganic silicon-based solar cells are produced in complicated processes at high costs, the solar cells have not widespread among ordinary households. To solve such drawbacks, an organic solar cell using organic materials which achieves lower costs and large dimensions in simple processes has actively researched. In research of such organic solar cells, Professor Gratzel of Universite de Lausanne in Switzerland discloses a dye-sensitized solar cell as a kind of organic solar cell based on photochemical reaction using porous titanium oxide, ruthenium pigment, iodine and iodine ion, which has high conversion efficiency of 10% (B. O'Regan, M. Gratzel, Nature, 353, 737 (1991)). Concerning an organic thin film solar cell as another kind of organic solar cell, it is reported that a low-molecular organic thin film solar cell which is formed using an electron-donating material (donor material) and an electron-accepting material (acceptor material) as low-molecular materials according to a vacuum evaporation method achieves conversion efficiency of 3.6% (P. Peumans and S. R. Forrest, Appl. Phys. Lett. 79, 126 (2001)). Use of a polymeric material for a photoactive layer which receives light and generates electric power has been considered. In this case, since the costly vacuum evaporation method is not used for forming the photoactive layer, further reduction in costs can be expected. It is reported that a mixed film of a conjugated polymer and a fullerene derivative achieves conversion efficiency of 2.5% (S. E. Shaheen, Appl. Phys. Lett. 78, 841 (2001)). With this as a turning point, research of the organic solar cell attracts attention again and various ideas are devised to obtain an organic solar cell having high efficiency. For example, the following ideas are devised. Irregularity is made on a backside cathode for collecting electrons to improve confinement of light and collection of electrons (M. Niggemann, e-MRS 2003, oral presentation (2003)). Alternatively, by preparing an organic solar cell using a material having high hall mobility as a conjugated polymer and then properly humidifying the organic solar cell, rearrangement of the conjugated polymer and proper mixed state of a hall transport material and an electron transport material are achieved, thereby improving charge separation (F. Padinger, Adv. Funct. Mater. 13, 85 (2003)). Conversion efficiency of 3.5% is obtained according to the above-mentioned techniques. In addition, to improve efficiency of the organic thin film solar cell, stack of photoactive layers has been actively addressed. In the organic thin film solar cell using a low-molecular material, by separating functions by layer, providing a Wiston-type light collection structure on a glass substrate on the incident light side (P. Peumans, V. Bulovic and S. R. Forrest, Appl. Phys. Lett. 76, 2650 (2000)) or stacking photoactive parts with a metal layer of about 0.5 to 5 nm being interposed (A. Yakimov and S. R. Forrest, Appl. Phys. Lett. 80, 1667 (2002)), open end voltage (Voc) is substantially doubled. Also in the case of using a polymeric material, a plurality of photoactive layers are stacked. As described above, stack of photoactive layer is demonstrated to be one of the most effective techniques for improving efficiency of the organic thin film solar cell. However, in the case where the photoactive layer is formed by being coated with a solution of an organic compound containing a donor material and an acceptor material, when a second photoactive layer is stacked to a first photoactive layer, the first photoactive layer may melt due to a solvent for forming the second photoactive layer, thereby causing destruction of structure of the first photoactive layer or deteriorating in functions. For this reason, it is disadvantageously difficult to form stacked structure of the photoactive layers. Japanese Examined Patent Publication No. 8-31616 discloses a multilayer organic solar cell in which a metal layer is interposed between a plurality of photoactive layers formed according to a deposition method or the like. When the photoactive layers are formed by solution coating in this manner, by interposing the metal layer between the photoactive layers, the metal layer can prevent the solvent used for forming the second photoactive layer from penetrating into the first photoactive layer. Consequently, it is prevented from destruction of structure of the first photoactive layer or deterioration in functions due to the solvent. However, in the case where the metal layer is provided between the photoactive layers, when a thickness of the metal layer is thick, light transmittance is lowered and thus, power conversion efficiency of the solar cell is lowered. For this reason, the metal layer needs to have a very small thickness. However, when the thickness of the metal layer is decreased, the solvent is easy to penetrate into and act upon the first photoactive layer. Japanese Unexamined Patent Publication No. 2001-319698 discloses a multilayer organic solar cell in which a single cell formed of a conductive layer, an under coating layer, a photosensitive layer (photoactive layer), a charge transfer layer, a counter electrode conductive layer which are deposited in this order are stacked via a support body made of glass or the like. With such structure, since each cell can be independently formed, deterioration in forming the photoactive layer by solution coating does not occur. However, many layers and complicated structure may cause an increase in production costs and a decrease in light transmittance, leading to deterioration of power conversion efficiency of the solar cell.	<SOH> BRIEF DESCRIPTION OF DRAWING <EOH>FIG. 1 is a schematic sectional view showing configuration of a multilayer organic solar cell as an example of an embodiment according to the present invention. detailed-description description="Detailed Description" end="lead"?	TECHNICAL FIELD The present invention relates to a multilayer organic solar cell in which a plurality of photoactive layers which receive light and generate electric power are stacked to each other. BACKGROUND ART In recent years, energy consumption has dramatically increased with growth of industries. In the future, further increase in demand for energy is expected. Against this backdrop, today's demands are placed on the development of production technology of economic and high-performance clean energy which does not put loads the Earth's environment. Among all, a solar cell which utilizes unlimited sunlight has attracted attention as a new energy source. Most of commercialized solar cells are inorganic solar cells using single crystal silicon, polycrystal silicon or amorphous silicon. However, since these inorganic silicon-based solar cells are produced in complicated processes at high costs, the solar cells have not widespread among ordinary households. To solve such drawbacks, an organic solar cell using organic materials which achieves lower costs and large dimensions in simple processes has actively researched. In research of such organic solar cells, Professor Gratzel of Universite de Lausanne in Switzerland discloses a dye-sensitized solar cell as a kind of organic solar cell based on photochemical reaction using porous titanium oxide, ruthenium pigment, iodine and iodine ion, which has high conversion efficiency of 10% (B. O'Regan, M. Gratzel, Nature, 353, 737 (1991)). Concerning an organic thin film solar cell as another kind of organic solar cell, it is reported that a low-molecular organic thin film solar cell which is formed using an electron-donating material (donor material) and an electron-accepting material (acceptor material) as low-molecular materials according to a vacuum evaporation method achieves conversion efficiency of 3.6% (P. Peumans and S. R. Forrest, Appl. Phys. Lett. 79, 126 (2001)). Use of a polymeric material for a photoactive layer which receives light and generates electric power has been considered. In this case, since the costly vacuum evaporation method is not used for forming the photoactive layer, further reduction in costs can be expected. It is reported that a mixed film of a conjugated polymer and a fullerene derivative achieves conversion efficiency of 2.5% (S. E. Shaheen, Appl. Phys. Lett. 78, 841 (2001)). With this as a turning point, research of the organic solar cell attracts attention again and various ideas are devised to obtain an organic solar cell having high efficiency. For example, the following ideas are devised. Irregularity is made on a backside cathode for collecting electrons to improve confinement of light and collection of electrons (M. Niggemann, e-MRS 2003, oral presentation (2003)). Alternatively, by preparing an organic solar cell using a material having high hall mobility as a conjugated polymer and then properly humidifying the organic solar cell, rearrangement of the conjugated polymer and proper mixed state of a hall transport material and an electron transport material are achieved, thereby improving charge separation (F. Padinger, Adv. Funct. Mater. 13, 85 (2003)). Conversion efficiency of 3.5% is obtained according to the above-mentioned techniques. In addition, to improve efficiency of the organic thin film solar cell, stack of photoactive layers has been actively addressed. In the organic thin film solar cell using a low-molecular material, by separating functions by layer, providing a Wiston-type light collection structure on a glass substrate on the incident light side (P. Peumans, V. Bulovic and S. R. Forrest, Appl. Phys. Lett. 76, 2650 (2000)) or stacking photoactive parts with a metal layer of about 0.5 to 5 nm being interposed (A. Yakimov and S. R. Forrest, Appl. Phys. Lett. 80, 1667 (2002)), open end voltage (Voc) is substantially doubled. Also in the case of using a polymeric material, a plurality of photoactive layers are stacked. As described above, stack of photoactive layer is demonstrated to be one of the most effective techniques for improving efficiency of the organic thin film solar cell. However, in the case where the photoactive layer is formed by being coated with a solution of an organic compound containing a donor material and an acceptor material, when a second photoactive layer is stacked to a first photoactive layer, the first photoactive layer may melt due to a solvent for forming the second photoactive layer, thereby causing destruction of structure of the first photoactive layer or deteriorating in functions. For this reason, it is disadvantageously difficult to form stacked structure of the photoactive layers. Japanese Examined Patent Publication No. 8-31616 discloses a multilayer organic solar cell in which a metal layer is interposed between a plurality of photoactive layers formed according to a deposition method or the like. When the photoactive layers are formed by solution coating in this manner, by interposing the metal layer between the photoactive layers, the metal layer can prevent the solvent used for forming the second photoactive layer from penetrating into the first photoactive layer. Consequently, it is prevented from destruction of structure of the first photoactive layer or deterioration in functions due to the solvent. However, in the case where the metal layer is provided between the photoactive layers, when a thickness of the metal layer is thick, light transmittance is lowered and thus, power conversion efficiency of the solar cell is lowered. For this reason, the metal layer needs to have a very small thickness. However, when the thickness of the metal layer is decreased, the solvent is easy to penetrate into and act upon the first photoactive layer. Japanese Unexamined Patent Publication No. 2001-319698 discloses a multilayer organic solar cell in which a single cell formed of a conductive layer, an under coating layer, a photosensitive layer (photoactive layer), a charge transfer layer, a counter electrode conductive layer which are deposited in this order are stacked via a support body made of glass or the like. With such structure, since each cell can be independently formed, deterioration in forming the photoactive layer by solution coating does not occur. However, many layers and complicated structure may cause an increase in production costs and a decrease in light transmittance, leading to deterioration of power conversion efficiency of the solar cell. DISCLOSURE OF INVENTION An object of the present invention is to provide a multilayer organic solar cell having high power conversion efficiency in which, when a second photoactive layer is stacked over a first photoactive layer by solution coating, the first photoactive layer is prevented from destruction or deterioration in functions due to a solvent in the solution of the second photoactive layer. To achieve the above-mentioned object, a multilayer organic solar cell in accordance with an aspect of the present invention comprises a first photoactive layer containing a donor material and an acceptor material, an inter-layer formed on the first photoactive layer, and a second photoactive layer formed of a solution of an organic compound containing the donor material and the acceptor material on the inter-layer. The inter-layer is composed of either of a transparent oxide or a transparent nitride. In a multilayer organic solar cell in accordance with another aspect of the present invention, light transmittance of the inter-layer is 70% or higher. In a multilayer organic solar cell in accordance with another aspect of the present invention, the inter-layer is a layer formed by coating the first photoactive layer with a solution in which particles of at least either of a transparent oxide and a transparent nitride are dispersed in a solvent which does not dissolve the first photoactive layer. In a multilayer organic solar cell in accordance with another aspect of the present invention, the inter-layer is a layer formed according to a vapor growth method. In a multilayer organic solar cell in accordance with another aspect of the present invention, a thickness of the inter-layer falls within a range of 5 to 250 nm. With such configuration, the inter-layer is formed as a transparent and fine film on the first photoactive layer. Thus, when the second photoactive layer is formed by solution coating, the inter-layer prevents the solvent in the solution forming the second photoactive layer from penetrating into the first photoactive layer, thereby preventing destruction of structure of the first photoactive layer or deterioration in functions due to action of the solvent. Consequently, stacked structure of photoactive layers having high power conversion efficiency can be obtained. BRIEF DESCRIPTION OF DRAWING FIG. 1 is a schematic sectional view showing configuration of a multilayer organic solar cell as an example of an embodiment according to the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a multilayer organic solar cell in accordance with an embodiment of the present invention will be described in detail with reference to a FIGURE. FIG. 1 shows an example of layer structure of the multilayer organic solar cell as an organic photoelectric converter. A transparent cathode layer 11, a hole transport layer 12, a photoactive layer 1 (hereinafter referred to as a first photoactive layer), an inter-layer 3, a hole transport layer 13, a photoactive layer 2 (hereinafter referred to as a second photoactive layer), an electron transport layer 14 and an anode layer 15 are deposited in this order. An outer surface of the deposited body is covered with a surface protection layer 16. When provided on a light incident surface side of the solar cell, a support substrate 10 is formed of a material having optical transparency. The support substrate 10 may be colorless and transparent, slightly colored or formed like a ground glass. For example, a transparent glass plate made of soda-lime glass, no-alkali glass or the like and a plastic film or plate made of resin such as polyester, polyplefin, polyamide, epoxy, fluorocarbon resin or the like manufactured by using an any proper method may be used. The support substrate 10 may include particles, powders, foam or the like having a different refractive index from that of a base material for the substrate so as to have a light diffusion effect. In the case where the support substrate 10 is not provided on the light incident surface side of the solar cell, the material and so on of the solar cell are not specifically limited and only need to support the solar cell. It is preferred that hole transport materials forming the hole transport layers 12, 13 are compounds having a hole transport capability, a hole transfer effect from the photoactive layers 1, 2, an excellent hole transfer effect to the cathode, an electron blocking characteristic and a good thin film formation capability. Specifically, available materials include phthalocyanine derivatives, naphthalocyanine derivatives, porphyrin derivatives, aromatic diamine compounds such as N,N′-bis(3-methylphenyl)-(1,1′-biphenyl)-4′-diamine (TPD) and 4,4′-bis[N-(naphthyl)-N-phenyl-amino]biphenyl(α-NPD), oxazole, oxadiazole, triazole, imidazole, imidazolone, stilbene derivatives, pyrazoline derivatives, tetrahydroimidazole, polyarylalkane, butadiene, 4,4′,4″-tris(N-(3-methylphenyl)N-phenylamino)triphenylamine(m-MTDATA), and polymeric materials such as conductive polymers including polyvinylcarbazole, polysilane, aminopyrazine derivatives, polyethylenedioxythiophene (PEDOT), but are not limited to these. A donor material for donating electrons and an acceptor material for accepting electrons are used as an organic compound forming the first photoactive layer 1 and the second photoactive layer 2. Phthalocyanine pigments, indigo, thioindigo pigments, quinacridone pigments, melocyanine compounds, cyanine compounds, squarium compounds, polycyclic aromatics, charge transfer materials used as xerographic photoreceptor, electrically conductive organic charge transfer complexes and conductive polymers may be adopted as the donor material. Available phthalocyanine pigments include divalent metals having a central metal of Cu, Zn, Co, Ni, Pb, Pt, Fe, Mg, trivalent phthalocyanine to which a halogen atom is coordinated, such as metal-free phthalocyanine, aluminum chlorophthalocyanine, indium chlorophthalocyanine, gallium chlorophthalocyanine, and other phthalocyanines to which an oxygen atom is coordinated, such as vanadyl phthalocyanine, titanyl phthalocyanine. Available polycyclic aromatics include anthracene, tetracene, pentacene, and derivatives thereof. Available charge transfer materials include hydrazone compounds, pyrazoline compounds, triphenylmethane compounds, triphenylamine compounds. Available electrically conductive organic charge transfer complexes include tetrathiofulvalene, tetraphenyltetrathiofulvalene. The conductive polymers may include materials which is soluble in organic solvelt such as toluene, that is, poly(3-alkylthiophene), polyparaphenylenevinylene derivatives, polyfluorene derivatives, conductive polymer oligomers, but are not limited to these. Compound semiconductor particles, especially, compound semiconductor nanocrystals can be used as the acceptor material. The nanocrystals have a size of 1 to 100 nm. The nanocrystals are formed in the shape of a rod, a ball, a tetrapod and the like. Examples of specific materials include III-V compound semiconductor crystals such as InP, InAs, GaP, GaAs, II-VI compound semiconductor crystals such as CdSe, CdS, CdTe, ZnS, oxide semiconductor crystals such as ZnO, SiO2, TiO2, Al2O3, CulnSe, CulnS, but are not limited to these. Low molecular materials formed of fullerene derivatives or the like and conductive polymers may be used as long as they can transport electrons. The inter-layer 3 is composed of at least either of a transparent oxide or a transparent nitride. Examples of the transparent oxide are ITO (indium tin oxide), SnO2, GZO (gallium zinc oxide), AZO (aluminium zinc oxide) and IZO (indium zinc oxide). An example of the transparent nitride is Si3N4. Any materials which can transmit light and do not deteriorate functions of the first photoactive layer 1 may be adopted and are not limited to the above-mentioned materials. Available materials used for the electron transport layer 14 provided on the second photoactive layer 2 include bathocuproin, bathophenanthroline and derivatives thereof, silole compound, triazole compound, tris(8-hydroxyquinolinate)aluminium complex, bis(4-methyl-8-quinolinate)aluminium complex, oxadiazole compound, distyrylarylene derivatives, silole compound, TPBI(2,2′,2″-(1,3,5-benzenetrile)tris-[1-phenyl-1H-benzimidazole]). However, any electron-transporting materials may be used and are not limited to these. Electron mobility of the materials is preferably 10-6 cm2/Vs or more, more preferably 10-5 cm2/Vs or more. The anode layer 15 formed on the electron transport layer 14 is an electrode for effectively collecting electrons generated in the photoactive layers 1, 2. It is preferred that a material for the electrode is a metal, an alloy, a conductive compound or a mixture thereof having small work function of 5 eV or smaller. Examples of electrode materials for the anode layer 15 include alkali metals, alkali metal halides, alkali metal oxides, alkali earth metals, rare earth metals and alloys of these metals and other metals, such as sodium, sodium-potassium alloys, lithium, magnesium, magnesium-silver mixtures, magnesium-indium mixtures, aluminium-lithium alloys and Al/LiF mixtures. Aluminium and Al/Al2O3 mixtures may be used. The anode layer 15 may be formed by using an alkali metal oxide, an alkali metal halide or a metal oxide as a base of the anode layer 15 and laminating one or more layer of the above-mentioned materials or alloys containing these materials having work function of 5 eV or larger. Examples include a lamination layer of alkali metal/Al, a lamination layer of alkali metal halide/alkali earth metal/Al and a lamination layer of Al2O3/Al. The anode layer 15 is prepared by forming the electrode material in a shape of a thin film according to a vacuum evaporation method, a sputtering method or a similar method. Then, the surface protection layer 16 which covers the deposited body thus formed may be formed by laminating a metal such as Al by sputtering or making fluorine-based compound, fluorine-based polymers or other organic molecule and polymers into a thin film by deposition, sputtering, CVD, plasma polymerization, coating, ultraviolet curing, thermal curing or other methods. Alternatively, a film-like structure having optical transparency and gas-barrier properties may be provided. In the case where the surface protection layer 16 is provided on the light incident surface side, it is preferred that a light transmittance of the surface protection layer 16 is 70% or higher so as to allow light to reach the photoactive layers 1, 2. Next, formation of the photoactive layers 1, 2 and the inter-layer 3 will be described. The inter-layer 3 is formed on the first photoactive layer 1 and then, the hole transport layer 13 and the second photoactive layer 2 are formed on the inter-layer 3 in this order. The first photoactive layer 1 may be formed by dissolving or dispersing the organic compound in a solvent, applying the solvent to the hole transport layer 12 and drying it or generating the organic compound on the hole transport layer 12 by a vapor growth method. A method of forming the film is not specifically limited. The inter-layer 3 may be formed by coating the first photoactive layer 1 with a solution in which particles of the transparent oxide or the transparent nitride are dispersed in a solvent to remove the solvent. In this case, it is preferred to use the solvent which prevents deterioration in functions, for example, does not dissolve the first photoactive layer 1. Available solvents are alcohols such as methanol, ethanol, isopropyl alcohol and water. The inter-layer 3 may be formed by the vapor growth method without using any solvent. In this case, functions of the first photoactive layer 1 are not deteriorated by the solvent. A vacuum evaporation method, a vacuum sputtering method and an EB evaporation method may be adopted as the vapor growth method. However, any method of forming the layer in vapor phase without using any solvent may be adopted and is not limited to the above-mentioned methods. A thickness of the inter-layer 3 thus formed falls within the range of 5 to 250 nm. The second photoactive layer 2 is formed by coating the hole transport layer 13 formed on the inter-layer 3 with an organic compound containing the donor material and the acceptor material and then, removing a solvent. The above-mentioned materials may be used as the donor material and the acceptor material. A polar solvent such as chloroform, chlorobenzene, 1,2-dichlorobenzene, 1,2,4-trichlorobenzene and toluene may be used as the solvent. With the above-mentioned structure of the multilayer organic solar cell, the inter-layer 3 formed on the first photoactive layer 1 is interposed between the first photoactive layer 1 and the second photoactive layer 2 formed by solution coating, thereby preventing the solvent in the solution from penetrating into the first photoactive layer 1 and thus preventing the solvent from acting upon the first photoactive layer 1. That is, the photoactive layer 1 is prevented from destruction or deterioration in functions due to dissolution in the solvent. Consequently, the multilayer organic solar cell thus constituted has stacked structure of photoactive layers having high power conversion efficiency. Since the inter-layer 3 is composed of the transparent oxide or the transparent nitride, the layer can be formed as a transparent and fine film. Thus, the inter-layer 3 can ensure a light transmittance of 70% or higher in a predetermined thickness thereof. When the light transmittance of the inter-layer 3 is 70% or higher, the second photoactive layer 2 formed on the first photoactive layer 1 have high light absorption and power conversion efficiency. Light which is not absorbed but reflected as the first photoactive layer 1 is thin can be converted into electricity, thereby improving power conversion efficiency. As the light transmittance of the inter-layer 3 is higher, power conversion efficiency is improved. An upper limit is not specifically set. The predetermined thickness of the inter-layer 3 is preferably 5 to 250 nm. In the following Examples, the thickness of the inter-layer 3 falls within the range. By setting the thickness of the inter-layer 3 at 5 nm or larger, it is possible to prevent the solvent from penetrating into and acting upon the first photoactive layer 1 when the second photoactive layer 2 is formed by solvent coating. By setting the thickness of the inter-layer 3 at 250 nm or smaller, the light transmittance of 70% or higher can be obtained and internal resistance of the organic solar cell cannot be increased. In this embodiment, the hole transport layer 13 is provided between the inter-layer 3 and the second photoactive layer 2. However, another layer may be provided as needed. The second photoactive layer 2 may be formed directly on the inter-layer 3. Also in this case, since the inter-layer 3 can block penetration of the solvent in the solution forming the second photoactive layer 2 as in the above-mentioned embodiment, the first photoactive layer 1 is prevented from destruction or deterioration in functions. Consequently, stacked structure of photoactive layers having high power conversion efficiency can be achieved. Basically, structure of the multilayer organic solar cell is cathode layer/first photoactive layer/inter-layer/second photoactive layer/anode layer. However, specific examples of the structure include cathode layer/hole transport layer/first photoactive layer/inter-layer/hole transport layer/second photoactive layer/electron transport layer/anode layer, cathode layer/hole transport layer/first photoactive layer/inter-layer/hole transport layer/second photoactive layer/anode layer, cathode layer/hole transport layer/first photoactive layer/inter-layer/second photoactive layer/anode layer, and cathode layer/hole transport layer/first photoactive layer/inter-layer/second photoactive layer/electron transport layer/anode layer. In the above-mentioned structure, an electron transport layer may be provided between the first photoactive layer and the inter-layer. The structure of first photoactive layer/electron transport layer without the hole transport layer may be adopted. Next, the present invention will be specifically described using Examples. EXAMPLE 1 A glass substrate with an ITO film (made by Kuramoto Seisakusho Co., Ltd.) which becomes the cathode layer was ultrasonic cleaned in acetone, isopropyl alcohol (made by Kanto Chemical Co., Inc.), Semico Clean (made by Furuuchi Chemical Corporation) and ultrapure water, respectively, for 10 minutes, and then, cleaned in vapor of isopropyl alcohol and dried. Next, a surface of the substrate was treated by an atmospheric pressure plasma surface treatment device (made by Matsushita Electric Works, Ltd.) for 3 minutes. Next, polyethylenedioxythiophene:polystyrene sulfonate (made by Starck Ltd.) having a thickness of 50 nm as the hole transport layer was formed on the cathode layer made of the ITO film. Next, the substrate was transferred to a glove box in a dry Ar atmosphere with oxygen of 1 ppm or less at a dew point of −76° C. or lower. A solution was prepared by dissolving 4 mg of poly(2-methoxy-5-(3,7-dimethyloctyloxy)-1,4-phenylenevinylene (made by American Dye Source, Inc., MDMO-PPV) as the donor material and 20 mg of [6,6]-phenylC61-butyricacid methyl ester (made by American Dye Source, Inc., abbreviated as PCBM) which is a fullerene derivative as the acceptor material in 1 mL of chlorobenzene. The first organic photoactive layer having a thickness of 100 nm was formed by coating the hole transport layer with the solution by spin coating. Next, the substrate was transferred to a DC sputtering device (made by Anelva Corporation). Using a ITO ceramic target (Tosoh Corporation), an ITO thin film having a thickness of 20 nm as the inter-layer was formed on the first organic photoactive layer so as not to damage to the first organic photoactive layer. Next, similarly, the hole transport layer was formed on the inter-layer, and as in the case of the first organic photoactive layer, the second organic photoactive layer was formed on the hole transport layer by solution coating through spin coating. Next, the substrate was set at a vacuum deposition device (made by ULVAC, Inc.). Bathocuproin (made by DOJINDO LABORATORIES) having a thickness of 6 nm as the electron transport layer was formed on the second organic photoactive layer. An Al thin film having a thickness of 150 nm as a counter electrode anode layer was formed on the electron transport layer according to the vacuum evaporation method. Next, the ITO substrate formed of the deposited layers was transferred to a a glove box in a dry nitrogen atmosphere at a dew point of −76° C. or lower without being exposed to the air. Meanwhile, barium oxide powders as water absorption were placed in a perforated bag and the bag was attached to a glass sealing plate with an adhesive. A sealing agent made of ultraviolet curing resin was previously applied to an outer circumference of the sealing plate and the ITO substrate and the sealing plate are stuck together with the sealing agent in the glove box and the sealing agent was cured by UV to form the surface protection layer. As described above, the multilayer organic solar cell as the organic photoelectric converter having the layer structure as shown in FIG. 1 was obtained. EXAMPLE 2 ITO ultrafine particles each having a diameter of 5 to 20 nm were dispersed in isopropyl alcohol at a concentration of 20 mg/mL to obtain a solution. An ITO film having a thickness of 200 nm as the inter-layer was formed on the first organic photoactive layer by spin coating of the solution. Except for these steps, the same processing as that in Example 1 was carried out to obtain a multilayer organic solar cell. COMPARATIVE EXAMPLE 1 By sputtering an Ag metal target with a sputtering device as in Example 1, a Ag film having a thickness of 20 nm as the inter-layer was formed on the first organic photoactive layer. Except for these steps, the same processing as that in Example 1 was carried out to obtain a multilayer organic solar cell. COMPARATIVE EXAMPLE 2 By sputtering an Ag metal target with a sputtering device as in Example 1, a Ag film having a thickness of 5 nm as the inter-layer was formed on the first organic photoactive layer. Except for these steps, the same processing as that in Example 1 was carried out to obtain a multilayer organic solar cell. Light transmittance (light transmittance in visible light having a wavelength of 500 nm) and conversion efficiency in the case where artificial sunlight (AM1.5, lsun) was applied to the multilayer organic solar cells obtained in Examples 1, 2 and Comparative examples 1, 2 by a solar simulator (made by Yamashita Denso Corporation) were acquired. Table 1 shows results. TABLE 1 Light Inter-layer Inter-layer Transmittance Open End Material Thickness @500 nm Electrode Example 1 ITO 20 nm 92% 1.2 V Example 2 ITO 200 nm 90% 1.1 V Comparative Ag 20 nm 55% 0.7 V example 1 Comparative Ag 100 nm 73% 0.7 V example 2 As shown in Table 1, the multilayer organic solar cell in each Example has higher light transmittance, open end voltage and power conversion efficiency than the multilayer organic solar cell in each Comparative example. The present invention has been described in detail using the embodiment with reference to the appended FIGURE. However, it would be apparent for those skilled in the art that various modifications and changes could be made. Thus, it should be recognized that such modifications and changes do not deviate from the scope of the present invention but fall within the scope. This application is based on Japanese Patent Application No. 2005-061364 and contents of the patent application should be incorporated into the present invention by reference of specification and figures thereof.	H	67H01	185H01L	31	00
11948414	US20090140341A1-20090604	INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS	ACCEPTED	20090520	20090604	[]	H01L2976	["H01L2976", "H01L21336"]	7629643	20071130	20091208	257	213000	86613.0	TRAN	TAN	[{"inventor_name_last": "Pillarisetty", "inventor_name_first": "Ravi", "inventor_city": "Portland", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Datta", "inventor_name_first": "Suman", "inventor_city": "University Park", "inventor_state": "PA", "inventor_country": "US"}, {"inventor_name_last": "Kavalieros", "inventor_name_first": "Jack T.", "inventor_city": "Portland", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Doyle", "inventor_name_first": "Brian S.", "inventor_city": "Portland", "inventor_state": "OR", "inventor_country": "US"}]	Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices, and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device.	1. An apparatus comprising: a semiconductor fin comprising a semiconductor fin material; one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices; and one or more multi-gate pass gate (PG) devices coupled with the semiconductor fin, the one or more PG devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PG devices, wherein the n-tip dopant concentration for the PG device is lower than the n-tip dopant concentration for the PD device. 2. An apparatus according to claim 1 wherein the semiconductor fin and the one or more PD and PG devices are part of a static random access memory (SRAM) cell having a β that is about equal to one, β being defined as follows, where ZPD is the total perimeter of the PD device, LPD is an actual gate length of the PD device, ZPG is the total perimeter of the PG device, and LPG is an actual gate length of the PG device: β=(ZPD/LPD)/(ZPG/LPG). 3. An apparatus according to claim 1 wherein the one or more PD devices are tri-gate PD devices and wherein the one or more PG devices are tri-gate PG devices. 4. An apparatus according to claim 1 wherein the semiconductor fin and the one or more PD and PG devices are part of a six-transistor cell, the six-transistor cell comprising two PD devices, two PG devices and two pull-up (PU) devices. 5. An apparatus according to claim 1 wherein an effective gate length of the PG device is greater than an effective gate length of the PD device as a result of using a reduced energy or dose of n-tip implant for the PG device in comparison to an energy or dose of n-tip implant for the PD device to increase static noise margin and read stability. 6. An apparatus according to claim 1 wherein the n-tip dopant comprises arsenic (As). 7. An apparatus according to claim 5 wherein the dose of the n-tip implant for the PD device is about 1×1013 cm−2 to 1×1016 cm−2 and wherein the energy is about 1 to 10 keV. 8. A method comprising: forming one or more non-planar pull down (PD) structures; forming one or more non-planar pass gate (PG) structures; implanting n-tip for the one or more PD structures using a PD dose and energy; and implanting n-tip for the one or more PG structures using a PG dose and energy wherein the PG dose is less than the PD dose or wherein the PG energy is less than the PD energy, or suitable combinations thereof. 9. A method according to claim 8 further comprising: depositing an implant-blocking material to the one or more non-planar PD structures and to the one or more non-planar PG structures; patterning the implant-blocking material to expose the one or more non-planar PD structures prior to implanting n-tip for the one or more PD structures using a PD dose and energy. 10. A method according to claim 9 further comprising: removing the implant-blocking material after implanting n-tip for the one or more PD structures using a PD dose and energy. 11. A method according to claim 8 further comprising: depositing an implant-blocking material to the one or more non-planar PD structures and to the one or more non-planar PG structures; patterning the implant-blocking material to expose the one or more non-planar PG structures prior to implanting n-tip for the one or more PG structures using a PG dose and energy. 12. A method according to claim 11 further comprising: removing the implant-blocking material after implanting n-tip for the one or more PG structures using a PG dose and energy. 13. A method according to claim 8 wherein implanting n-tip for the one or more PD structures using a PD dose and energy comprises using a PD dose of about 1×1013 cm −2 to 1×1016 cm−2 and a PD energy of about 1 to 10 keV. 14. A method according to claim 8 wherein implanting n-tip for the one or more PG structures using a PG dose or energy that is less than the PD dose or energy increases the effective gate length of the PG structure relative to the effective gate length of the PD structure to increase the static noise margin and read stability. 15. A method according to claim 8 wherein forming one or more non-planar pass down (PD) structures and forming one or more non-planar pass gate (PG) structures are part of forming a six-transistor static random access memory (SRAM) cell having a β that is about equal to one, β being defined as follows, where ZPD is the total perimeter of the PD device, LPD is an actual gate length of the PD device, ZPG is the total perimeter of the PG device, and LPG is an actual gate length of the PG device: β(ZPD/LPD)/(ZPG/LPG).	<SOH> BACKGROUND <EOH>Generally, semiconductor devices such as static random access memory (SRAM) require sufficient static noise margin to maintain cell stability during read operations.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to lo similar elements and in which: FIGS. 1 a - 1 c provide a top-down view of independent n-tips for multi-gate transistors, according to but one embodiment; FIG. 2 is a cross-sectional side view of independent n-tips for multi-gate transistors, according to but one embodiment; FIG. 3 is a flow diagram of a method for providing independent n-tips for multi-gate transistors, according to but one embodiment; and FIG. 4 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment. detailed-description description="Detailed Description" end="lead"? It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.	BACKGROUND Generally, semiconductor devices such as static random access memory (SRAM) require sufficient static noise margin to maintain cell stability during read operations. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to lo similar elements and in which: FIGS. 1a-1c provide a top-down view of independent n-tips for multi-gate transistors, according to but one embodiment; FIG. 2 is a cross-sectional side view of independent n-tips for multi-gate transistors, according to but one embodiment; FIG. 3 is a flow diagram of a method for providing independent n-tips for multi-gate transistors, according to but one embodiment; and FIG. 4 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment. It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements. DETAILED DESCRIPTION Embodiments of independent n-tips for multi-gate transistors are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. FIGS. 1a-1c provide a top-down view of independent n-tips for multi-gate transistors 100, according to but one embodiment. In an embodiment according to FIG. 1a, an apparatus 100 includes n-diffusion material 102, p-diffusion material 104, gate electrodes 106, pull down (PD) structures or devices 108, pass gate (PG) structures or devices 110, and pull up (PU) structures or devices 112, each coupled as shown. The particular design layout illustrated in FIG. 1a is merely one embodiment of many that fall within the scope and spirit of this description. Other embodiments include more or less transistor devices 108, 110, 112 and/or different arrangements, for example. Non-planar transistors 108, 110, 112, such as tri-gate transistors, may generally provide exceptional short channel effect control, providing a viable option to support future technology scaling in the semiconductor industry. To enable the use of multi-gate non-planar transistors 108, 110, 112, an on-die memory cache may include tri-gate based six-transistor (6T) SRAM cells 100, according to but one embodiment. A tri-gate based SRAM cell 100 may require sufficient read stability to support array functionality. In an embodiment, SRAM cell read stability is dependent upon static noise margin (SNM), which is strongly dependent upon the conductivity ratio of the PD 108 to PG 110 transistor. This ratio may be called the beta (β) ratio as defined in equation (1) below, where ZPD is the total perimeter of the PD device, LPD is the actual gate length of the PD device, ZPG is the total perimeter of the PG device, and LPG is the actual gate length of the PG device: β=(ZPD/LPD)/(ZPG/LPG) (1) For example, ZPD or ZPG may be twice the height of the semiconductor fin 102 plus the width of the fin in a u-shaped tri-gate device 108, 1 10 in an embodiment. In traditional 6T SRAM cells, based on planar transistors, the β ratio may be modulated using transistor sizing to achieve desired cell read stability. However, non-planar transistors 108, 110, 112 such as tri-gate transistors may not be amenable to biasing ZPD, LPD, ZPG, or LPG relative to each other due to drastically different device physics in non-planar transistors. Modulating the p ratio in non-planar transistors 108, 110, 112 such as tri-gate may degrade cell performance and increase short channel effects, for example. In an embodiment, 6T SRAM cells based upon tri-gate transistors require similar sizing between PD 108 and PG 110 devices resulting in near unity or unity β ratio. In an embodiment according to FIGS. 1b and 1c, independent n-tip implants are used for the PD 108 and PG 110 transistors to increase static noise margin and cell read stability. In an embodiment according to FIG. 1b, an implant blocking material 114 such as oxide, for example, is patterned to expose only the PD devices 108 for n-tip implant. In an embodiment according to FIG. 1c, an implant blocking material 116 such as oxide, for example, is patterned to expose only the PG devices 110 for n-tip implant. In one embodiment, the n-tip implant concentration for the PG device 110 is lower than the n-tip implant concentration for the PD device 108, resulting in an increase in the effective gate length of the PG device relative to the effective gate length of the PD device (the actual and effective gate length is described in more detail with respect to FIG. 2). Reduced n-tip implant concentration for the PG device 110 may increase the PD device 108 conductance relative to the conductance of the PG device 110, which in turn increases static noise margin and cell read stability. In an embodiment, an apparatus 100 includes a semiconductor pillar or fin 102, one or more multi-gate PD devices 108 coupled with the semiconductor fin 102, the one or more PD devices 108 having an n-tip dopant concentration in the semiconductor fin 102 material adjacent to the one or more PD devices 108, and one or more multi-gate PG devices 110 coupled with the semiconductor fin, the one or more PG devices 110 having an n-tip dopant concentration in the semiconductor fin 102 material adjacent to the one or more PG devices 110, wherein the n-tip dopant concentration for the PG devices 110 is lower than the n-tip dopant concentration for the PD devices 108. A semiconductor fin 102 may be a protruding structure coupled with a semiconductor substrate (not shown). In an embodiment, a semiconductor pillar or fin 102 includes p-type material such as p-diffusion 102. No particular order is required for the independent n-tip implants of the PD 108 and PG 110 devices. For example, the n-tip implant of the PG device 110 may occur prior to the n-tip implant of the PD device 108, and vice versa. In an embodiment, the n-tip dopant includes arsenic (As) for either the PG device 110 or the PD device 108, or for both devices 108, 110. The dose of the n-tip implant for the PD device 108 may be about 1×1013 cm−2 to 1×1016 cm−2 and the energy for the PD device 108 may be about 1 to 10 keV. In an embodiment, the semiconductor fin 102 and the one or more PD 108 and PG 110 devices are part of a static random access memory (SRAM) cell having a β that is about equal to one. In another embodiment, the one or more PD devices 108 are tri-gate PD devices and the one or more PG devices 108 are tri-gate PG devices. The PD 108 and/or PG devices may be u-shaped tri-gate transistors. In an embodiment, the semiconductor fin 102 and the one or more PD 108 and PG 110 devices are part of a 6T cell, the 6T cell comprising two PD devices 108, two PG devices 110 and two pull-up (PU) devices 112. FIG. 2 is a cross-sectional side view of independent n-tips for multi-gate transistors 200, according to but one embodiment. In an embodiment, an apparatus 200 includes a semiconductor fin 202, a PD structure or device 204, a PG structure or device 206, and n-tip implant profile 208, each coupled as shown. A semiconductor fin 202 may include p-type material such as p-diffusion. The n-tip implant profile 208 may be a part of p-diffusion material 202 that is doped with n-tip implant such as As, for example. The implant concentration 208 may be reduced for the PG device 206 relative to the PD device 204 by decreasing either the implant dose or energy, or both, in an embodiment. In an embodiment, a reduced energy or dose of the n-tip implant 208 for the PG device 206 relative to the PD device 204 increases the effective gate length, LeffPG, of the PG device 206 relative to the effective gate length, LeffPD, of the PD device 204. The effective gate lengths, LeffPD and LeffPG, may be the distance between n-tip doped material 208 of semiconductor fin 202 adjacent to PD 204 and PG 206 structures, respectively. The actual gate lengths, LactPd and LactPG, of the PD 204 and PG 206 devices may be the distance across the actual gate material of the devices 204, 206 respectively. Effectively increasing the gate length of the transistor may provide the benefits associated with increasing gate length, without actually increasing gate length. In other embodiments, apparatus 200 incorporates embodiments already described with respect to FIGS. 1a-1c. FIG. 3 is a flow diagram of a method for providing independent n-tips for multi-gate transistors 300, according to but one embodiment. In an embodiment, a method 300 includes forming one or more non-planar PD and PG structures 302, depositing a blanket blocking material such as oxide to the one or more non-planar PD and PG structures 304, patterning the blocking material to expose PD structures 306, implanting n-tip for PD structures using a PD dose and energy 308, removing the blocking material 310, depositing a blanket blocking material to the one or more non-planar PD and PG structures 312, patterning the blocking material to expose PG structures 314, implanting n-tip for PG structures using a PG dose and energy, the PG dose and/or energy being less than the PD dose and/or energy 316, and removing the blocking material 318, with arrows providing but one suggested flow. A method 300 is not limited to the order depicted. For example, in another embodiment implanting n-tip for PG structures 316 and associated actions 314 are performed prior to implanting n-tip for PD structures 308 and associated actions 306. In an embodiment, a method 300 includes forming one or more non-planar pass down (PD) structures 302, forming one or more non-planar pass gate (PG) structures 302, implanting n-tip for the one or more PD structures using a PD dose and energy 308, and implanting n-tip for the one or more PG structures using a PG dose and energy wherein the PG dose is less than the PD dose or wherein the PG energy is less than the PD energy 316, or suitable combinations thereof. A method 300 may further include depositing an implant-blocking material to the one or more non-planar PD structures and to the one or more non-planar PG structures 304 and patterning the implant-blocking material to expose the one or more non-planar PD structures 306 prior to implanting n-tip for the one or more PD structures using a PD dose and energy 308. A method 300 may further include removing the implant-blocking material 310 after implanting n-tip for the one or more PD structures using a PD dose and energy. In another embodiment, a method 300 includes depositing an implant-blocking material to the one or more non-planar PD structures and to the one or more non-planar PG structures 312 and patterning the implant-blocking material to expose the one or more non-planar PG structures prior to implanting n-tip for the one or more PG structures using a PG dose and energy 316. A method 300 may further include removing the implant-blocking material 318 after implanting n-tip for the one or more PG structures using a PG dose and energy 318. In an embodiment, implanting n-tip for the one or more PD structures using a PD dose and energy 308 includes using a PD dose of about 1×1013 cm−−2 to 1×1016 cm −2 and a PD energy of about 1 to 10 keV. In another embodiment, implanting n-tip for the one or more PG structures using a PG dose or energy that is less than the PD dose or energy 316 increases the effective gate length of the PG structure relative to the effective gate length of the PD structure to increase the static noise margin and read stability. In one embodiment, forming one or more non-planar pass down (PD) structures 302 and forming one or more non-planar pass gate (PG) structures 302 includes at least gate patterning, defining the semiconductor fins, depositing gate material such as poly or high-k metal gate stack, and/or defining the gate material. In another embodiment, forming one or more non-planar pass down (PD) structures 302 and forming one or more non-planar pass gate (PG) structures 302 are part of forming a six-transistor static random access memory (SRAM) cell having a β that is about equal to one. Method 300 may incorporate embodiments already described with respect to FIGS. 1a-1c and FIG. 2. Various operations may be described as multiple discrete operations in turn, in a manner that is most helpful in understanding the invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments. FIG. 4 is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment. System 400 is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, personal computers (PC), wireless telephones, personal digital assistants (PDA) including cellular-enabled PDAs, set top boxes, pocket PCs, tablet PCs, DVD players, or servers, but is not limited to these examples and may include other electronic systems. Alternative electronic systems may include more, fewer and/or different components. In one embodiment, electronic system 400 includes an apparatus having independent n-tips for multi-gate transistors 100 in accordance with embodiments described with respect to FIGS. 1-3. In an embodiment, an apparatus having independent n-tips for multi-gate transistors 100 as described herein is part of an electronic system's processor 410 or memory 420. Electronic system 400 may include bus 405 or other communication device to communicate information, and processor 410 coupled to bus 405 that may process information. While electronic system 400 may be illustrated with a single processor, system 400 may include multiple processors and/or co-processors. In an embodiment, processor 410 includes an apparatus having independent n-tips for multi-gate transistors 100 in accordance with embodiments described herein. System 400 may also include random access memory (RAM) or other storage device 420 (may be referred to as memory), coupled to bus 405 and may store information and instructions that may be executed by processor 410. Memory 420 may also be used to store temporary variables or other intermediate information during execution of instructions by processor 410. Memory 420 is a flash memory device in one embodiment. In another embodiment, memory 420 includes an apparatus having independent n-tips for multi-gate transistors 100 as described herein. System 400 may also include read only memory (ROM) and/or other static storage device 430 coupled to bus 405 that may store static information and instructions for processor 410. Data storage device 440 may be coupled to bus 405 to store information and instructions. Data storage device 440 such as a magnetic disk or optical disc and corresponding drive may be coupled with electronic system 400. Electronic system 400 may also be coupled via bus 405 to display device 450, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device 460, including alphanumeric and other keys, may be coupled to bus 405 to communicate information and command selections to processor 410. Another type of user input device is cursor control 470, such as a mouse, a trackball, or cursor direction keys to communicate information and command selections to processor 410 and to control cursor movement on display 450. Electronic system 400 further may include one or more network interfaces 480 to provide access to network, such as a local area network. Network interface 480 may include, for example, a wireless network interface having antenna 485, which may represent one or more antennae. Network interface 480 may also include, for example, a wired network interface to communicate with remote devices via network cable 487, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable. In one embodiment, network interface 480 may provide access to a local area network, for example, by conforming to an Institute of Electrical and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or IEEE 802.11 g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported. IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Previous or subsequent versions of the Bluetooth standard may also be supported. In addition to, or instead of, communication via wireless LAN standards, network interface(s) 480 may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol. In an embodiment, a system 400 includes one or more omnidirectional antennae 485, which may refer to an antenna that is at least partially omnidirectional and/or substantially omnidirectional, and a processor 410 coupled to communicate via the antennae. The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of this description, as those skilled in the relevant art will recognize. These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.	H	67H01	185H01L	29	76
11749898	US20080284021A1-20081120	Method for FEOL and BEOL Wiring	ACCEPTED	20081105	20081120	[]	H01L2144	["H01L2144", "H01L2348"]	7790611	20070517	20100907	438	653000	76490.0	PAYEN	MARVIN	[{"inventor_name_last": "Anderson", "inventor_name_first": "Brent A.", "inventor_city": "Jerhico", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Ellis-Monaghan", "inventor_name_first": "John J.", "inventor_city": "Grand Isle", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Nowak", "inventor_name_first": "Edward J.", "inventor_city": "Essex Junction", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Rankin", "inventor_name_first": "Jed H.", "inventor_city": "South Burlington", "inventor_state": "VT", "inventor_country": "US"}]	A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).	1. A method for forming a conductive structure of sub-lithographic dimension comprising: forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of said topographic feature, said exposed pattern corresponding to a conductive structure to be formed; depositing a metal at said exposed portions of said sidewall; forming one or more metal silicide conductive structures at said exposed sidewall portions; removing said dielectric cap layer; and removing said silicon-containing topographic feature, wherein one or more metal silicide conductor structures are formed for a single lithographically defined feature. 2. The method as claimed in claim 1, wherein said metal silicide conductor structure is of high aspect ratio. 3. The method as claimed in claim 1, wherein said high aspect ratio ranges from 1:1 to 20:1 (height to width dimension). 4. The method as claimed in claim 1, wherein said silicon-containing topographic feature is formed on an insulator structure. 5. The method as claimed in claim 1, wherein said silicon-containing topographic feature is formed on a silicon-containing substrate. 6. The method as claimed in claim 1, wherein said silicon-containing material includes polysilicon, polySiGe, or doped polysilicon. 7. The method as claimed in claim 2, wherein the deposited metal includes one of Ti, Ta, Al, W, Co, Mo, Ni, Pt, Pd, or alloys thereof. 8. The method as claimed in claim 2, wherein said forming one or more metal silicide conductive structures at said exposed sidewall portions includes: reacting said deposited metal with said polysilicon topographic feature under temperature and time conditions sufficient for forming said metal silicide conductive structures; and, stripping away any unreacted metal. 9. The method as claimed in claim 1, applicable for forming wire structures for FEOL and BEOL semiconductor processing applications. 10. The method as claimed in claim 1, wherein prior to forming said silicon-containing topographic feature, forming a metal diffusion barrier layer of material underneath said silicon-containing topographic feature. 11. The method as claimed in claim 10, wherein said metal silicide conductor material structure is formed to encircle said topographic feature and contact said metal diffusion barrier layer of material. 12. The method as claimed in claim 11, wherein said steps of removing said silicon-containing topographic feature and said dielectric cap layer form a trench comprising said metal diffusion barrier layer at a bottom and said formed silicide encircled sidewalls, said method further comprising: filling said trench with a conductor material. 13. The method as claimed in claim 9, further comprising: implementing an electroplating technique for forming metal plates out of said one or more metal silicide conductor structures for thickening or reinforcing said one or more metal silicide conductors. 14. The method as claimed in claim 13, further comprising: forming a dielectric material between said formed metal plates to result in a capacitor device. 15. The method as claimed in claim 1, wherein said formed metal silicide conductor structure encircles all said sidewalls of said topographic feature, said steps of removing said silicon-containing mandrel and said dielectric cap layer forming a trench, said method further comprising: depositing a liner material to form a metal diffusion barrier layer on an inside surface sidewalls and bottom of said trench, and filling said diffusion barrier-lined trench with a conductor material. 16. The method as claimed in claim 1, wherein said steps of forming a trench utilizing a damascene technique for forming a damascene trench structure within said formed trench, and forming conductive metal silicide sidewall structures for said formed damascene structure. 17. A method of forming a conductor structure for use in FEOL and BEOL semiconductor processing applications comprising: providing a first structure of material; forming a topographic feature of silicon-containing material on top said first structure and, a dielectric cap layer on top said topographic feature; applying a mask to expose a sidewall portion of said topographic feature corresponding to a conductive structure to be formed; depositing a metal at said exposed sidewall portion; forming a metal silicide structure that encircles said topographic feature; removing said topographic feature and said dielectric cap layer to form a trench; forming a metal diffusion barrier liner layer conforming to bottom and sidewall surface; and depositing a metal conductor material in said trench. 18. The method as claimed in claim 17, wherein said diffusion barrier liner layer for a bottom trench surface is formed beneath said silicon-containing topographic feature prior to forming said topographic feature, said formed metal silicide structure in electrical contact with said prior formed bottom trench diffusion barrier liner layer. 19. The method as claimed in claim 17, wherein said metal conductor material is selected from the group of Cu, Ti, Ta, W, Co, Ni, Pt, Pd or Al. 20. The method as claimed in claim 17, wherein said depositing metal for forming said silicide comprises: Ti, Ta, Al, W, Co, Mo, Ni, Pt, Pd or allow thereof. 21. The method as claimed in claim 17, used for forming complex metal silicide conductor structures. 22. A vertically oriented conductive wire structure of sub lithographic dimension having a metal silicide material as a component, said wire structure exhibiting a high aspect ratio ranging from 1:1 to 20:1 (height to width dimension). 23. The conductive wire structure of sub lithographic dimension as claimed in claim 22, having a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. 24. The conductive wire structure of sub lithographic dimension as claimed in claim 22, comprising an outer material component and inner material component, wherein said inner material component is a silicide and the outside material is plated with a conductive material. 25. A structure consisting of a pair of vertically oriented conductive wires of sub lithographic dimension having a metal silicide material as a component, said wire structure exhibiting a high aspect ratio ranging from 0.5:1 to 10:1 (height to width dimension). 26. A conductive wire structure of sub lithographic dimension as claimed in claim 25, having a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. 27. A pair of conductive wire structures of sub lithographic dimension as claimed in claim 25, each of said pair having a first vertical silicide growth front facing each other and a second vertical silicide non-growth fronts facing to the outside of the structure. 28. The conductive wire structure of sub lithographic dimension as claimed in claim 25, comprising an outer material component and inner material component, wherein said outside material component is said metal silicide material and said inner material component is a conductive material.	<SOH> FIELD OF THE INVENTION <EOH>The present invention relates to semiconductor devices and structures generally, and particularly, to a novel conductive structure that can be used for Front End of Line (FEOL) and Back End of Line (BEOL) applications.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures. The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures that is applicable for both FEOL and BEOL semiconductor fabrication applications. The conductive structures comprise one or more wire structures that are small and spaced close together. The semiconductor conductive structures applicable for both FEOL and BEOL semiconductor fabrication applications comprise one or more wire structures that are small and spaced close together and, in an exemplary embodiment, comprises a metal silicide material of sub-lithographic feature size dimensions. The semiconductor conductive structure that is applicable for both FEOL and BEOL semiconductor fabrication applications, and that comprises a silicide wire structure, is of a high aspect ratio. The conductive structure itself comprises one or more conductive wire structures, and, in one embodiment, two or more parallel wires are created for single lithography defined features. Thus, by using sidewall formed wiring, two or more thin wire structure can be created for a single lithography defined feature. In this example a polysilicon structure with a dielectric cap is silicided, the cap is removed, and the polysilicon is removed—resulting in at least two parallel silicide wires. These structures can be used in the FEOL for dense arrays, local interconnects, strapping, etc. they can also be used in the early wiring levels as standalone wires. According to one aspect of the invention, there is provided a conductive structure and, a method for forming a conductive structure of sub-lithographic dimensions. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductor structures can support a range of aspect ratio's (e.g., 1:1 to 20:1; 0.5:1 to 10:1). Furthermore, conductive structures can be formed that are later filled with conductive material, e.g., to form a via, or, used to define a feature by selective plating of the conductive structures. According to a further aspect of the invention, there is provided a vertically oriented conductive wire structure of sub lithographic dimension having a metal silicide material as a component, the wire structure exhibiting a high aspect ratio ranging from 1:1 to 20:1 (height to width dimension). The conductive wire structure of sub lithographic dimension includes a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. In one embodiment, the conductive wire structure of sub lithographic dimension may further comprise an outer material component and inner material component, wherein the inner material component is a silicide and the outside material is plated with a conductive material. In a further aspect of the invention, there is provided a structure comprising a pair of vertically oriented conductive wires of sub lithographic dimension having a metal silicide material as a component, the wire structures exhibiting a high aspect ratio ranging from 0.5:1 to 10:1 (height to width dimension). The conductive wire structure of sub lithographic dimension includes a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. In one embodiment, the vertical silicide growth fronts of both wires are facing each other and vertical silicide non-growth fronts are facing to the outside of the structure. Moreover, the conductive wire structure of sub lithographic dimension comprises an outer material component and inner material component, wherein the outside material component is the silicide material and the inner material component is a conductive material. In all embodiments, there is provided a method of forming a conductor structure for use in FEOL and BEOL semiconductor processing applications comprising: providing a first structure of material; forming a topographic feature of silicon-containing material on top the first structure and, a dielectric cap layer on top the topographic feature; applying a mask to expose a sidewall portion of the topographic feature corresponding to a conductive structure to be formed; depositing a metal at the exposed sidewall portion; forming a metal silicide structure that encircles the topographic feature; removing the topographic feature and the dielectric cap layer to form a trench; forming a metal diffusion barrier liner layer conforming to bottom and sidewall surface; and depositing a metal conductor material in the trench. Advantageously, the method for forming the conductive structures as described can be used to form structures of complex shapes using standard semiconductor and lithographic processing techniques.	FIELD OF THE INVENTION The present invention relates to semiconductor devices and structures generally, and particularly, to a novel conductive structure that can be used for Front End of Line (FEOL) and Back End of Line (BEOL) applications. Description of the Prior Art Techniques for forming small conductive structures in semiconductor devices abound in the patent literature, e.g., U.S. Pat. Nos. 5,349,229 and 6,989,323 and U.S. Patent Publication No. 2002/0098683 A1 being representative. For example, U.S. Pat. No. 5,349,229 is directed to formation of a local interconnect, defined in a polycrystalline silicon layer. Openings to underlying conducting regions are made through an insulating layer after the local interconnect conductor definition. A thin extra polycrystalline silicon layer is then deposited over the device and etched back to form polycrystalline silicon sidewall elements. These sidewalls connect the polycrystalline silicon local interconnect conductors to the underlying conductive regions. Standard silicidation techniques are then used to form a refractory metal silicide on the exposed underlying conductive regions, the polycrystalline silicon sidewall elements, and the polycrystalline silicon local interconnect conductors. This results in a complete silicided connection between features connected by the local interconnect conductors. U.S. Pat. No. 6,989,323 describes a gate structure for a semiconductor device formed by defining a conductive sacrificial structure on a substrate; forming a reacted metal film on sidewalls of the conductive sacrificial structure; and removing unreacted portions of the conductive sacrificial structure. The uniformity of the gate conductor is largely determined by the uniformity of the growth of the reacted metal film (e.g., cobalt silicide), which does not suffer from the large through-pitch variations that are typically observed with conventional optical lithographic methods. U.S. Patent Publication No. 2002/0098683 A1 describes a wiring of silicon formed on a surface of a semiconductor substrate. Part of the wiring is covered with a resist pattern. Ion implantation is conducted on the substrate using the resist pattern as a mask and then the resist pattern is removed. An upper section of the wiring with a thickness of at least 5 nm is removed to minimize thickness of the wiring. Reaction is caused between a surface section of the wiring of which thickness is thus reduced and a metal which reacts with silicon to thereby form a metal silicide film on a surface of the wiring. Resistance of the wiring can be reduced with good reproducibility. Particular techniques described in the patent literature that require first a patterning polysilicon, depositing and patterning dielectric film, depositing metal and react metal to form silicide; and removing the unreated metal and polysilicon to leave the conducting metal-silicide structure are described to some extent in U.S. Pat. Nos. 5,427,981 and 6,569,767 and U.S. Patent Publication No. 2005/0106859 A1. U.S. Pat. No. 5,427,981, for example, teaches a process for fabricating a metal plug having a uniform surface capable of preventing a junction consumption reaction. The process includes preparing a semiconductor substrate which includes a first wiring layer, an insulating film formed over the first wiring layer and a contact hole formed in the insulating film such that the surface of the insulating film is exposed through the contact hole, forming a polysilicon film to a predetermined thickness over the entire exposed surface of the resulting structure after the formation of the contact hole, forming a photoresist pattern at a bottom portion of the contact hole on which the polysilicon film is disposed, removing an exposed portion of the polysilicon film not hidden by the photoresist pattern and then removing the photoresist pattern, forming a first metal film over the entire exposed surface of the resulting structure after the removal of the photoresist pattern, reacting the first metal film with the polysilicon film by a thermal treatment, thereby forming a metallic silicide film at the bottom portion of the contact hole, removing the remaining first metal film not reacted with the polysilicon film and filling the contact hole with a second metal material for forming a metal plug buried in the contact hole formed with the metallic silicide film. U.S. Pat. No. 6,569,767 for example, teaches a process for producing a semiconductor device comprising the steps of: forming a metal wiring layer containing copper as the main component on a semiconductor substrate; forming an insulating film on the entire surface of the resulting semiconductor substrate; removing the insulating film only from a place where a wire of gold or aluminum is to be bonded, in order to expose a part of the metal wiring layer; forming a layer of copper silicide or a layer of a compound of copper and boron in a surface layer of the exposed part of the metal wiring layer; and bonding a wire to a surface of the layer of copper silicide or the layer of the compound of copper and boron. U.S. Patent Publication No. 2005/0106859 A1 teaches a method of forming a silicide film which can include forming a first metal film on a silicon substrate and forming a second metal film on the first metal film at a temperature sufficient to react a first portion of the first metal film in contact with the silicon substrate to form a metal-silicide film. The second metal film and a second portion of the first metal film can be removed so that a thin metal-silicide film remains on the silicon substrate. Currently, each of these techniques for forming small conductive structures such as local interconnects, plugs, strappings, wires, and other conducting structures in semiconductor devices are increasing in cost and complexity at a faster rate than most other processes. This is primarily due to the reason that features sizes continue to shrink while lithography does not advance at the same rate. Additionally, as features scale, resistance of the conductive structures is becoming a greater detractor to performance. It would thus be highly desirable to provide a conductive structure comprising one or more wire structures, and, in one embodiment, two parallel wires that can be created for single lithography defined features. It would further be highly desirable to provide a technique for forming one or more conductive structures, e.g., wires, on silicon containing structures, that exhibit good resistance characteristics and can be formed during FEOL and BEOL applications. SUMMARY OF THE INVENTION The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures. The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures that is applicable for both FEOL and BEOL semiconductor fabrication applications. The conductive structures comprise one or more wire structures that are small and spaced close together. The semiconductor conductive structures applicable for both FEOL and BEOL semiconductor fabrication applications comprise one or more wire structures that are small and spaced close together and, in an exemplary embodiment, comprises a metal silicide material of sub-lithographic feature size dimensions. The semiconductor conductive structure that is applicable for both FEOL and BEOL semiconductor fabrication applications, and that comprises a silicide wire structure, is of a high aspect ratio. The conductive structure itself comprises one or more conductive wire structures, and, in one embodiment, two or more parallel wires are created for single lithography defined features. Thus, by using sidewall formed wiring, two or more thin wire structure can be created for a single lithography defined feature. In this example a polysilicon structure with a dielectric cap is silicided, the cap is removed, and the polysilicon is removed—resulting in at least two parallel silicide wires. These structures can be used in the FEOL for dense arrays, local interconnects, strapping, etc. they can also be used in the early wiring levels as standalone wires. According to one aspect of the invention, there is provided a conductive structure and, a method for forming a conductive structure of sub-lithographic dimensions. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductor structures can support a range of aspect ratio's (e.g., 1:1 to 20:1; 0.5:1 to 10:1). Furthermore, conductive structures can be formed that are later filled with conductive material, e.g., to form a via, or, used to define a feature by selective plating of the conductive structures. According to a further aspect of the invention, there is provided a vertically oriented conductive wire structure of sub lithographic dimension having a metal silicide material as a component, the wire structure exhibiting a high aspect ratio ranging from 1:1 to 20:1 (height to width dimension). The conductive wire structure of sub lithographic dimension includes a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. In one embodiment, the conductive wire structure of sub lithographic dimension may further comprise an outer material component and inner material component, wherein the inner material component is a silicide and the outside material is plated with a conductive material. In a further aspect of the invention, there is provided a structure comprising a pair of vertically oriented conductive wires of sub lithographic dimension having a metal silicide material as a component, the wire structures exhibiting a high aspect ratio ranging from 0.5:1 to 10:1 (height to width dimension). The conductive wire structure of sub lithographic dimension includes a first vertical side being a silicide growth front and a second vertical side being a silicide non-growth front. In one embodiment, the vertical silicide growth fronts of both wires are facing each other and vertical silicide non-growth fronts are facing to the outside of the structure. Moreover, the conductive wire structure of sub lithographic dimension comprises an outer material component and inner material component, wherein the outside material component is the silicide material and the inner material component is a conductive material. In all embodiments, there is provided a method of forming a conductor structure for use in FEOL and BEOL semiconductor processing applications comprising: providing a first structure of material; forming a topographic feature of silicon-containing material on top the first structure and, a dielectric cap layer on top the topographic feature; applying a mask to expose a sidewall portion of the topographic feature corresponding to a conductive structure to be formed; depositing a metal at the exposed sidewall portion; forming a metal silicide structure that encircles the topographic feature; removing the topographic feature and the dielectric cap layer to form a trench; forming a metal diffusion barrier liner layer conforming to bottom and sidewall surface; and depositing a metal conductor material in the trench. Advantageously, the method for forming the conductive structures as described can be used to form structures of complex shapes using standard semiconductor and lithographic processing techniques. BRIEF DESCRIPTION OF THE DRAWINGS The objects, features and advantages of the present invention will become apparent to one skilled in the art, in view of the following detailed description taken in combination with the attached drawings, in which: FIG. 1 illustrates, through a cross-sectional view, a wiring structure 10 according to a first embodiment of the invention formed during either FEOL and BEOL processes; FIGS. 2A-2B illustrate, through cross-sectional views, exemplary processing steps according to a first embodiment of the invention; FIG. 2C illustrates the interface between the silicide and the silicon (e.g., polysilicon) where contacted which may be referred to herein as a silicide “growth front”; the outer vertical side may also be referred to as a silicide “non-growth front”; FIGS. 3A-3C, through cross-sectional views, depict similar processing steps as described herein with respect to FIGS. 2A and 2B, that result in a conductive structure 50 shown in FIG. 3C according to a second embodiment of the invention; FIGS. 4A-4C, through cross-sectional views, depict similar processing steps as described herein with respect to FIGS. 2A and 2B, to result in silicided wiring structures 75 as shown in FIG. 4C according to a further embodiment of the invention; FIG. 5, through cross-sectional view, depicts a formed structure comprising two silicide wire structures formed in the manner described herein having either a low-k dielectric material formed therebetween for wiring applications or, a high-k dielectric material formed therebetween for use as a capacitor structure 90 according to a further embodiment of the invention; FIGS. 6A-6C, through cross-sectional views, depict similar processing steps as described with respect to FIGS. 2A and 2B, to result in a structure 100 that does not constitute image doubling by silicide or replacement according to a further embodiment of the invention; FIGS. 7A-7C, through cross-sectional views, depict similar processing steps as described with respect to FIGS. 2A and 2B, to result in a structure 160; FIGS. 8A and 8B, through top plan views, show the complex wire shapes 170, 180 respectively, formed according to the techniques of the present invention; FIG. 9 depicts a top plan-view of the formed silicided sidewall portion 15′ encircling the polysilicon topographic feature 25 according to exemplary embodiments of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention. The present invention provides a method for forming small silicide wires spaced close together at or coupled to device regions contained by a semiconductor substrate. The resulting structure contains metal silicide structures characterized as having a substantially high aspect ratio. FIG. 1 illustrates, through a cross-sectional view, a wiring structure 10 according to a first embodiment of the invention formed as a result of either FEOL and BEOL processes. In FIG. 1, the example wire structure 10 includes one or more vertically oriented high aspect ratio silicide structures 15, formed atop a Shallow Trench Isolation (STI) structure 12 as shown in FIG. 1. The silicide structures 15 may additionally be formed atop a semiconductor (e.g., Silicon-containing) substrate 10. Preferably, the height to width ratio of the silicide structure 15 is in the range from 1:1 to 20:1, but this is configurable. In one example embodiment, a silicide wire structure is about 150 nm in height and about 30 nm wide. The exemplary processing steps of the present invention will now be described in greater detail by referring to the accompanying FIGS. 2A-2B. In FIG. 2A, there is shown a topographic feature, e.g., a silicon containing structure 25, having a dielectric cap material 30 formed on top of the STI structure 12 previously formed utilizing a conventional trench isolation process well known to those skilled in the art. For example, lithography, etching and filling of the trench with a trench dielectric material may be used in forming the trench isolation structure 12. The STI may comprise an oxide, nitride, or oxynitride of silicon. Optionally, a liner may be formed in the trench prior to trench fill, a densification step may be performed after the trench fill and a planarization process may follow the trench fill as well. In still alternate embodiments, the silicon containing structure 25 may be formed atop a silicon-containing substrate with or without a thin dielectric liner deposited on the surface thereof underneath the silicon containing structure 25. In one exemplary embodiment, the silicon containing topographic feature 25 is polysilicon or polysilicongermanium (polySi or polySiGe) and formed as an upstanding vertical structure formed in accordance with conventional techniques now described. The polySi structure 25 shown in FIG. 2A may be formed as a layer utilizing a known deposition process such as: CVD, plasma-assisted CVD, sputtering, plating, evaporation and other like deposition processes (e.g., a low pressure CVD). A thin protective dielectric material cap layer 30 is then deposited on top of the thin poly layer surface. Preferably, the dielectric material comprises an oxide, e.g., SiO2, a nitride, or oxynitride material or any combination thereof In one embodiment, a nitride such as, for example, Si3N4, is employed as the dielectric cap layer. The polysilicon structure layer and top dielectric cap layer may then be patterned and etched at the same time by conventional photolithographic techniques to form the structure 20 including silicon containing structure 25 having a top dielectric cap 30 shown in FIG. 2A. It is understood that the layer of polysilicon may be doped or undoped. If doped, an in-situ doping deposition process may be employed in forming the same. Alternatively, a doped polySi layer can be formed by deposition, ion implantation and annealing. The sidewall regions of the polysilicon structure 25 of FIG. 2A are patterned by lithographically forming a mask and etching to expose a pattern on the sides of the polysilicon structure where the silicidation is desired to form the wire structures. The lithography step includes applying a layer of photoresist material to the polysilicon and formed cap, exposing the photoresist to a desired pattern of radiation and developing the exposed photoresist utilizing a conventional resist developer. The pattern in the photoresist is then transferred to the polysilicon structure sidewalls utilizing one or more dry etching steps. Suitable dry etching processes that can be used in the present invention in forming the patterned sidewalls include, but are not limited to: reactive ion etching, ion beam etching, plasma etching or laser ablation. The dry etching process employed should not remove the dielectric cap layer 30 atop the polySi structure 25. Alternatively, a second dielectric layer may be formed and lithographically patterned over the polysilicon feature sidewalls whereby portions of the dielectric layer may be removed to expose the polysilicon sidewalls where a metal may be deposited to react and form the silicide. This second dielectric film enables control over where a formed wire will stop and start. Thus, as a result of etching away the second dielectric covering the polySi structure sidewalls, a pattern of exposed polySi structure sidewall portions is provided that correspond to the desired silicide wire structure 15 to be formed. In one embodiment, one or more exposed sidewall portions are formed on opposite sidewalls of the topographic feature 25 that will result in two upstanding parallel metal silicide wire structures of sub-lithographic feature dimensions. As shown in FIG. 1, the high aspect ratio metal silicide wire structures are formed on opposite sidewalls of the topographic feature. It is understood, however, that many vertically oriented parallel silicide wire structures may be formed according to the process described herein. Moreover, as is understood by a person skilled in the art, the formed silicided sidewall portion 15′ may encircle the polysilicon topographic feature 25 when viewed in plan-view as shown in FIG. 9. Thus, the entire polySi structure sidewall may be exposed which results in a thin hollowed silicide conductive structure that may be further filled with conductor material, as will be described in greater detail hereinbelow. The next step involves forming the silicide wire structures 15 in the exposed polySi structure sidewalls by blanket depositing a metal on the exposed polySi sidewall surfaces, and then performing one or more annealing steps to form a silicide, and then, selectively etching any non-reacted metal and the capping layer. More particularly, the pattern of exposed polySi structure sidewall portions becomes reacted with the silicide metal, i.e., any metal that is capable of reacting with silicon to form a metal silicide. Examples of such metals include, but are not limited to: Ti, Ta, Al, W, Co, Mo, Ni, Pt, Pd or alloys thereof. The metal material used to form the silicide may be deposited using any conventional deposition process including, for example, sputtering, chemical vapor deposition, a physical vapor deposition (PVD) of the silicide evaporation, chemical solution deposition, plating and the like. It should be understood that if the silicide wires are to be formed on a silicon containing substrate and not STI, a thin dielectric layer may be formed on the top surface either prior to or after forming the polysilicon structure 25 so that the silicide is not formed at the underlying silicon substrate. In some embodiment, however, it may be advantageous to remove a portion of any thin dielectric layer in order to form a silicided conductive structure on the substrate surface that may be attached to the formed wires 15. After deposition of the silicide metal on the exposed polysilicon sidewall portions defining dimensions of the silicide wire structures 15, a thermal anneal process is employed to form a silicide phase in the structure; preferably, the silicide representing the lowest resistivity phase of a metal silicide. The anneal is performed utilizing the ambients and temperatures well known in the art that cause the silicide metal to react with the underlying polysilicon to form the metal silicide layer 15 as shown in FIG. 2B. It is understood that the depth of the blanket silicide metal deposition and anneal (temperature and timing) conditions are carefully controlled according to conventional techniques to ensure that the silicide wires 15 are formed of desired dimensions, i.e., aspect ratios achieved. In one embodiment, the silicide metal may comprise Co noting that CoSi2 forms using a two step annealing process as known in the art. In another embodiment of the present invention, the silicide metal is Ni or Pt; NiSi and PtSi being formed using a single annealing step. Then, a selective wet etch step may be employed to remove any non-reactive silicide metal from the structure. In one exemplary embodiment, the structure is annealed at approximately 600° C. to about 800° C. for approximately 30 seconds in a nitrogen environment to react with the portions of the polysilicon 25 to form the conductive silicide wire structures 15 along the sidewalls of the topographic polySi feature 25 as shown in FIG. 2B. FIG. 2B particularly depicts the resulting intermediate structure showing one of two silicide wire structures 15 formed on the polySi structure 25 as a result of said salicidation process. Preferably, the silicide wire structures so formed to have an aspect ratio from 1:1 to 20:1 (height to width dimension), or, for example, 0.5:1 to 10:1 (height to width dimension). FIG. 2C illustrates the interface between the silicide and the silicon (e.g., polysilicon) where contacted (prior to the silicon being removed) that may be referred to as a silicide “growth front”. The outer vertical side of the silicide wire structure may also be referred to as a silicide “non-growth front”. Then, a next step involves removing the dielectric cap 30 from the polySi structure 25. First, the dielectric cap is stripped from the structure using an etching process that is selective to the Si containing material, i.e., polySi. Although any chemical etchant may be used in removing the dielectric cap layer materials 30 in one embodiment dilute hydrofluoric acid (DHF) is used. Next, the underlying polySi structure 25 is removed to leave the remaining upstanding silicide wire structures 15 in tact as shown in FIG. 1. That is, an etching process is performed selective to the silicide and underlying STI to remove the polysilicon from the intermediate structure shown in FIG. 2B. In one embodiment, a chemical etching, e.g., potassium hydroxide (KOH) etch is performed stopping atop the STI layer oxide layer 18. Other techniques including an isotropic etching of the polySi structure using a chlorine-containing wet or dry etch, or alternatively, an anisotropic etch including a KOH or NH4OH based wet solution, may be implemented. Thus, in the example depicted in FIGS. 2A-2B, a polySi line with a dielectric cap is silicided, the cap is removed, and the polySi is removed—resulting in two parallel silicide wires shown in FIG. 1. These structures can be used in the FEOL for dense array wiring, local interconnects, strapping, etc. These structures can also be used in the early wiring levels as standalone wires. These structures can be used in the BEOL as dense pitch metal lines or can be used to define a feature which is later filled or used to define a feature by selective plating. By using sidewall formed wiring, two wires of high aspect ratio can be created for a single lithography defined feature. Thus, what is presented as shown in the example embodiments shown in FIGS. 2A and 2B is effectively an image doubling technique to fabricate high density conductors without complex/expensive lithography. These silicide conductors have lower resistance than polysilicon and the technique offers flexibility to create wires exactly where desired without major changes to existing semiconductor processing techniques. The methods of the present invention enables the fabrication of a variety of alternative silicide conductive structures. For instance as shown in FIGS. 3A-3C, through cross-sectional views, similar steps are performed as described with respect to FIGS. 2A and 2B, that result in a conductive structure 50 shown in FIG. 3C having thin silicide sidewall structures 45 filled with a conductor material 60. In the process of forming the structure of FIG. 3C, however, it is understood that a thin silicide structure, or, preferably any material that acts as a metal (e.g., Copper) diffusion barrier 40 is first formed on top the STI 12 or Si-containing substrate above which is formed the polySi structure 25. Example metal diffusion barrier materials include, but are not limited to Ti, Ta, TiTa, TiN, TaN, TiSiN, W. Then, the steps of forming the polysilicon material layer and top surface dielectric cap layer and etching the same to enable formation of a thin sidewall silicidation 45 of a resultant polysilicon structure 25 as shown in FIG. 3A is performed according to the process as described herein with respect to FIGS. 2A-2B. Although not shown in the cross-sectional view of FIG. 3A, the whole polysSi topographic feature sidewall is encircled with silicide. That is, the whole polySi sidewall structure 25 may be blanket deposited with a metal at a sufficient thickness that, when annealed, forms a thin silicide structure 45 around (encircling) the polySi structure 25, the silicide 45 being in electrical contact with the bottom diffusion barrier 40. After forming the thin silicidation 45, a protective dielectric material layer 55, e.g., oxide, nitride, or oxynitride, is blanket deposited to encapsulate the silicided sidewalls and inner polySi structure 25 such as shown in FIG. 3B, and a chemical-mechanical polish (CMP) step is thereafter formed to planarize the top surface 56 of the structure to the polySi level. With the top surface of the polySi structure 25 exposed, utilizing the chemical etching techniques described herein, an etch process may then be performed to remove the polySi structure leaving a trench 65 defined by the encircled silicided sidewall structure 45 and bottom diffusion barrier layer 40 that prevents diffusion of the copper material as shown in FIG. 3B. Then, the trench may be filled with a conductor material, e.g., Copper, to result in the conductive structure 50 encapsulated with the diffusion barrier 40, 45 or copper cladding as shown in FIG. 3C. Thus, for instance, the resulting conductive structure 50 may function as a conducting via formed in accordance with the invention, rather than formed according to the typical dual damascene techniques currently implemented in the art. In an alternative embodiment shown in FIGS. 4A-4C, through cross-sectional views, similar steps are performed as described with respect to FIGS. 2A and 2B, to result in a silicided wiring structures 75 as shown in FIG. 4C. In the embodiment shown in FIG. 4A, the steps of forming the polysilicon topographic feature include forming a polysilicon layer and a top surface dielectric cap layer on top and etching the same to enable formation of a thin sidewall silicidation 15 of the resultant polysilicon line 25 as shown is performed according to the process as described herein with respect to FIGS. 2A-2B. In the embodiment depicted in FIG. 4A and 4B, two thin sidewall silicidations 15 are formed on opposite sidewall portions. Then, the dielectric cap layer 30 is removed and the polySi 25 is removed to result in the two upstanding silicide wire structures shown in FIG. 4B. Then, using techniques known in the art, these two upstanding silicide wire structures 15 shown in FIG. 4B are plated or coated with another material 70 to stiffen or enlarge the structures 15. In still a further alternative embodiment, as shown in FIG. 5, the two silicide wire structures as formed in the manner described herein after the polySi strip, may have a low-k dielectric material formed therebetween for wiring applications or, may have a high-k dielectric material formed therebetween for use as a capacitor structure 90. The methodology for forming such a structure 90, as shown in FIG. 5, is as follows: first, forming the thin sidewall silicidations 85 along the polySi structure sidewall in the manner as described herein with respect to FIGS. 2A-2C, and then depositing a dielectric material 55 that encircles (surrounds) the structure. Then, a CMP polishing step is performed to remove the dielectric cap previously formed on top of the polySi. Then, the polySi is removed from the selective polySi etch process described herein. Finally, a dielectric material 95, e.g., a low-k or high-k dielectric material, is deposited between the thin sidewall silicidations 85 which is wholly surrounded by the dielectric material 55. In an alternative embodiment shown in FIGS. 6A-6C, through cross-sectional views, similar steps are performed as described with respect to FIGS. 2A and 2B, to result in a structure 100 that does not constitute image doubling by silicide or replacement, i.e., it is a one-dimension structure used to create a structure of the original dimension. This process however implements steps similar to the methodology described hereinabove, namely: first, as shown in FIG. 6A, forming the thin sidewall silicidations 105 along the polySi structure sidewall in the manner as described herein with respect to FIGS. 2A-2C, and then depositing a dielectric material 55 that surrounds the structure. Then, a CMP polishing step is performed to remove the dielectric cap 30 previously formed on top of the polySi. Then, the polySi 25 is removed by the selective polySi etch process described herein as shown in FIG. 6B thus forming a trench structure 115. Then, a standard metal liner, e.g., of a refractory metal or alloy thereof such as Ti, Ta, TiTa, TiN, TaN, TiSiN, W is deposited to form a metal liner layer 125 that conforms along the inner surfaces including the bottom surface of the trench 115. The resultant lined trench structure is then filled with a conductor material to result in the structure 100 shown in FIG. 6C. In a further alternative embodiment shown in FIGS. 7A-7C, through cross-sectional views, similar steps are performed as described with respect to FIGS. 2A and 2B, to result in a structure 160 that does not constitute image doubling by silicide or replacement, i.e., it is a one-dimension structure used to create a structure of the original dimension. The steps shown in FIG. 7A include the formation of a thin sidewall silicadation 140 of a damascene structure 130 formed out of the silicon-containing topographic feature, and in FIG. 7B, the deposition of a conductor material 145, e.g. a metal, and the subsequent CMP step and etch back step to recess the height of the metal material to below the surface to result in the structure shown in FIG. 7B. Subsequently, using chemical deposition techniques as described herein, a dielectric cap layer is formed above the conductive material formed in the recess, e.g., and a polishing step is formed to flatten the resulting surface topography. Then, a dielectric fill step is performed wherein a further dielectric material 150 is formed around the formed conductive structure followed by a CMP step to result in the structure 160 shown in FIG. 7C. Still other embodiments depicted in FIGS. 8A and 8B, through top plan views, show how complex wire shapes 170, 180 respectively can be created by careful sizing of polysilicion structure shape and dielectric coverings according to the processes described herein to prevent undesired silicide formations according to the invention. While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.	H	67H01	185H01L	21	44
11710486	US20070200242A1-20070830	Semiconductor apparatus	ACCEPTED	20070815	20070830	[]	H01L2352	["H01L2352"]	7884478	20070226	20110208	257	690000	69194.0	TRAN	TRANG	[{"inventor_name_last": "Azuma", "inventor_name_first": "Shoji", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}]	In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.	1. A semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus comprising a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. 2. The semiconductor apparatus according to claim 1, wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern. 3. The semiconductor apparatus according to claim 1, wherein the first conductive plug is made of a conductive material harder than aluminum. 4. The semiconductor apparatus according to claim 3, wherein the conductive material includes tungsten. 5. The semiconductor apparatus according to claim 2, further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires and in parallel to the plurality of first-layer plug wires. 6. The semiconductor apparatus according to claim 2, the plurality of first-layer plug wires arranged in the region under the bonding pad has a pattern rate not smaller than 20% and not greater than 50%. 7. The semiconductor apparatus according to claim 5, wherein the plurality of first-layer plug wires and the first-layer pass-through wires in the region under the bonding pad have a total pattern rate not smaller than 20% and not greater than 60%. 8. The semiconductor apparatus according to claim 1, further comprising a second-layer plug wire formed by a second lower wiring layer under the first lower wiring layer, and a second conductive plug connecting the first-layer plug wire and the second-layer plug wire. 9. The semiconductor apparatus according to claim 8, wherein the first and the second conductive plugs are formed at the same position in plan view to overlap each other. 10. The semiconductor apparatus according to claim 8, wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern, the second-layer plug wire comprising a plurality of second-layer plug wires arranged in a stripe pattern to be orthogonal to the plurality of first-layer plug wires. 11. The semiconductor apparatus according to claim 10, further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires, and second-layer pass-through wires arranged between adjacent ones of the plurality of second-layer plug wires, the first-layer pass-through wires being connected to the second-layer pass-through wires.	<SOH> BACKGROUND OF THE INVENTION <EOH>This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a wiring pattern formed in a region under a bonding pad. Following development of a highly-integrated semiconductor apparatus, a device pattern is more and more miniaturized and a design rule thereof becomes finer year after year. However, in comparison with the progress of miniaturization of the device pattern, the progress in miniaturization of a bonding pad of the semiconductor apparatus is little due to limitation imposed upon a bonding technique and an accuracy of a bonding apparatus. In the semiconductor apparatus, for example, in a dynamic random access memory (DRAM), reduction in chip size has a significant influence upon cost reduction in order that mass production is carried out. In order to reduce the chip size, it is necessary to reduce a bonding pad area and to effectively use a region under the bonding pad area. As one approach for effectively using the bonding pad area, it is considered to form the bonding pad on a device region or a wiring region while the bonding pad is traditionally formed in a region except the device region and the wiring region. A related bonding pad comprising a two-layer aluminum wiring structure is shown in FIG. 1 . In a region under the bonding pad formed by a #2 aluminum pad wiring 20 as an upper wiring layer, a #1 aluminum wiring 10 as a lower wiring layer similar in size to the bonding pad is disposed. At both ends of the bonding pad, #1 aluminum pad connecting wirings 13 as internal wirings and the #2 aluminum pad wiring 20 are connected to each other by #1-#2 layer conductive plugs 40 . The #1 aluminum wiring 10 is, throughout a substantially entire area thereof, connected to the #2 aluminum pad wiring 20 via another #1-#2 layer conductive plug 40 . The #1-#2 layer conductive plugs 40 serve as piles (or anchor bolts) for preventing the #2 aluminum pad wiring 20 from being peeled off after bonding. With the above-mentioned structure, since the #1 aluminum wiring 10 is present in the region under the bonding pad, the lower wiring layer can not be used as a signal wiring, resulting in an increase in chip size. In FIG. 1 , a polyimide 5 is provided with an opening. Referring to FIG. 2 , description will be made of a case where the #1 aluminum wiring 10 and the #1-#2 layer conductive plug 40 formed throughout the substantially entire area under the bonding pad are not used. In FIG. 2 , instead of the #1 aluminum wiring 10 under the bonding pad in FIG. 1 , a #1 aluminum pass-through wiring 12 as a signal wiring can be arranged. Thus, in case where the bonding pad of the #2 aluminum pad wiring 20 is not peeled off from an interlayer insulating film by a mechanical shock during bonding, the #1 aluminum pass-through wiring 12 can be disposed under the bonding pad. However, if the pass-through wiring 12 is extended under the bonding pad, the pass-through wiring 12 may be broken due to the mechanical shock during bonding. Japanese Unexamined Patent Application Publication JP S59-181041 A discloses such a technique of forming the lower wiring layer in the region under the bonding pad. In the above-mentioned publication, however, the wiring under the bonding pad is limited to a wiring having a large wiring width in order to prevent breakage due to the mechanical shock during bonding. In addition, in the structure disclosed in the above-mentioned publication, the bonding pad of the #2 aluminum wiring is easily peeled off after bonding. In an etching step or a CMP (Chemical Mechanical Polishing) step, an optimum production condition is different depending upon the density of the pattern. In FIG. 1 , a pattern as the lower wiring layer similar in size to the bonding pad is disposed in the region under the bonding pad. Therefore, the pattern is dense as compared with an internal circuit portion. In FIG. 2 , depending upon the number of wirings extended in the region under the bonding pad, the pattern may be sparse as compared with the internal circuit portion. Therefore, the density of the lower wiring pattern under the bonding pad in FIG. 1 or 2 is considerably different as compared with that of the internal circuit portion. This results in a difficulty in determining etching or CMP conditions during a diffusion process. Another approach for effectively using the bonding pad area is disclosed in Japanese Unexamined Patent Application Publication JP 2005-166959 A. Specifically, a gate region under the bonding pad is protected by a strengthening via. In Japanese Unexamined Patent Application Publication JP 2005-116788 A, a via is formed in order to relax a stress of an insulating film under the bonding pad. However, these publications do not disclose a technique of arranging a fine wiring in the region under the bonding pad. Further, no disclosure is made of a technique of arranging a striped plug wiring in the region under the bonding pad and providing a conductive plug on the plug wiring in order to achieve a density same as that in the internal circuit portion. As described above, in the semiconductor apparatus, it is desired to reduce the chip size for the purpose of cost reduction. In order to reduce the chip size, it is effective to utilize the region under the bonding pad. Accordingly, it is desired to develop a technique of arranging a fine wiring in the region under the bonding pad so as to effectively use the region under the bonding pad. However, because the pad wiring is peeled off or the pass-through wiring is broken due to the mechanical shock during bonding, it is impossible to arrange the fine pass-through wiring in the region under the bonding pad. Therefore, it is impossible to effectively utilize the region under the bonding pad.	<SOH> SUMMARY OF THE INVENTION <EOH>It is therefore an object of this invention to provide a semiconductor apparatus having a bonding pad which is capable of preventing a wiring from being peeled off or broken due to a mechanical shock during bonding and which allows a fine pass-through wiring to be arranged under the bonding pad. Semiconductor apparatuses according to this invention are as follows: (1) A semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus comprising a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. (2) The semiconductor apparatus according to the paragraph (1), wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern. (3) The semiconductor apparatus according to the paragraph (1), wherein the first conductive plug is made of a conductive material harder than aluminum. (4) The semiconductor apparatus according to the paragraph (3), wherein the conductive material includes tungsten. (5) The semiconductor apparatus according to the paragraph (2), further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires and in parallel to the plurality of first-layer plug wires. (6) The semiconductor apparatus according to the paragraph (2), the plurality of first-layer plug wires arranged in the region under the bonding pad has a pattern rate not smaller than 20% and not greater than 50%. (7) The semiconductor apparatus according to the paragraph (5), wherein the plurality of first-layer plug wires and the first-layer pass-through wires in the region under the bonding pad have a total pattern rate not smaller than 20% and not greater than 60%. (8) The semiconductor apparatus according to the paragraph (1), further comprising a second-layer plug wire formed by a second lower wiring layer under the first lower wiring layer, and a second conductive plug connecting the first-layer plug wire and the second-layer plug wire. (9) The semiconductor apparatus according to the paragraph (8), wherein the first and the second conductive plugs are formed at the same position in plan view to overlap each other. (10) The semiconductor apparatus according to the paragraph (8), wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern, the second-layer plug wire comprising a plurality of second-layer plug wires arranged in a stripe pattern to be orthogonal to the plurality of first-layer plug wires. (11) The semiconductor apparatus according to the paragraph (10), further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires, and second-layer pass-through wires arranged between adjacent ones of the plurality of second-layer plug wires, the first-layer pass-through wires being connected to the second-layer pass-through wires. In this invention, the striped plug wiring is arranged in the region under the bonding pad. The plug wiring and the pad wiring are connected to each other by the conductive plug. The plug wiring as a lower layer and the pad wiring as an upper layer are connected by the conductive plug. The conductive plug serves as a pile for preventing the bonding pad from being easily peeled off. Therefore, it is possible to prevent the pad wiring from being peeled off. Since a mechanical shock during bonding is absorbed by the conductive plug, it is possible to prevent breakage of a thin wiring under the bonding pad. Furthermore, a pattern rate is assured by the plug wiring. As the density of a pattern is approximate to the pattern rate of an internal circuit portion, it is easy to determine etching and CMP (Chemical Mechanical Polishing) conditions and so on in a diffusion process. The wiring of a fine pattern equivalent in fineness to the internal circuit portion can be used as a pass-through wiring under the bonding pad. In addition, a diffusion yield is improved.	This application claims priority to prior Japanese patent application JP 2006-49625, the disclosure of which is incorporated herein by reference. BACKGROUND OF THE INVENTION This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a wiring pattern formed in a region under a bonding pad. Following development of a highly-integrated semiconductor apparatus, a device pattern is more and more miniaturized and a design rule thereof becomes finer year after year. However, in comparison with the progress of miniaturization of the device pattern, the progress in miniaturization of a bonding pad of the semiconductor apparatus is little due to limitation imposed upon a bonding technique and an accuracy of a bonding apparatus. In the semiconductor apparatus, for example, in a dynamic random access memory (DRAM), reduction in chip size has a significant influence upon cost reduction in order that mass production is carried out. In order to reduce the chip size, it is necessary to reduce a bonding pad area and to effectively use a region under the bonding pad area. As one approach for effectively using the bonding pad area, it is considered to form the bonding pad on a device region or a wiring region while the bonding pad is traditionally formed in a region except the device region and the wiring region. A related bonding pad comprising a two-layer aluminum wiring structure is shown in FIG. 1. In a region under the bonding pad formed by a #2 aluminum pad wiring 20 as an upper wiring layer, a #1 aluminum wiring 10 as a lower wiring layer similar in size to the bonding pad is disposed. At both ends of the bonding pad, #1 aluminum pad connecting wirings 13 as internal wirings and the #2 aluminum pad wiring 20 are connected to each other by #1-#2 layer conductive plugs 40. The #1 aluminum wiring 10 is, throughout a substantially entire area thereof, connected to the #2 aluminum pad wiring 20 via another #1-#2 layer conductive plug 40. The #1-#2 layer conductive plugs 40 serve as piles (or anchor bolts) for preventing the #2 aluminum pad wiring 20 from being peeled off after bonding. With the above-mentioned structure, since the #1 aluminum wiring 10 is present in the region under the bonding pad, the lower wiring layer can not be used as a signal wiring, resulting in an increase in chip size. In FIG. 1, a polyimide 5 is provided with an opening. Referring to FIG. 2, description will be made of a case where the #1 aluminum wiring 10 and the #1-#2 layer conductive plug 40 formed throughout the substantially entire area under the bonding pad are not used. In FIG. 2, instead of the #1 aluminum wiring 10 under the bonding pad in FIG. 1, a #1 aluminum pass-through wiring 12 as a signal wiring can be arranged. Thus, in case where the bonding pad of the #2 aluminum pad wiring 20 is not peeled off from an interlayer insulating film by a mechanical shock during bonding, the #1 aluminum pass-through wiring 12 can be disposed under the bonding pad. However, if the pass-through wiring 12 is extended under the bonding pad, the pass-through wiring 12 may be broken due to the mechanical shock during bonding. Japanese Unexamined Patent Application Publication JP S59-181041 A discloses such a technique of forming the lower wiring layer in the region under the bonding pad. In the above-mentioned publication, however, the wiring under the bonding pad is limited to a wiring having a large wiring width in order to prevent breakage due to the mechanical shock during bonding. In addition, in the structure disclosed in the above-mentioned publication, the bonding pad of the #2 aluminum wiring is easily peeled off after bonding. In an etching step or a CMP (Chemical Mechanical Polishing) step, an optimum production condition is different depending upon the density of the pattern. In FIG. 1, a pattern as the lower wiring layer similar in size to the bonding pad is disposed in the region under the bonding pad. Therefore, the pattern is dense as compared with an internal circuit portion. In FIG. 2, depending upon the number of wirings extended in the region under the bonding pad, the pattern may be sparse as compared with the internal circuit portion. Therefore, the density of the lower wiring pattern under the bonding pad in FIG. 1 or 2 is considerably different as compared with that of the internal circuit portion. This results in a difficulty in determining etching or CMP conditions during a diffusion process. Another approach for effectively using the bonding pad area is disclosed in Japanese Unexamined Patent Application Publication JP 2005-166959 A. Specifically, a gate region under the bonding pad is protected by a strengthening via. In Japanese Unexamined Patent Application Publication JP 2005-116788 A, a via is formed in order to relax a stress of an insulating film under the bonding pad. However, these publications do not disclose a technique of arranging a fine wiring in the region under the bonding pad. Further, no disclosure is made of a technique of arranging a striped plug wiring in the region under the bonding pad and providing a conductive plug on the plug wiring in order to achieve a density same as that in the internal circuit portion. As described above, in the semiconductor apparatus, it is desired to reduce the chip size for the purpose of cost reduction. In order to reduce the chip size, it is effective to utilize the region under the bonding pad. Accordingly, it is desired to develop a technique of arranging a fine wiring in the region under the bonding pad so as to effectively use the region under the bonding pad. However, because the pad wiring is peeled off or the pass-through wiring is broken due to the mechanical shock during bonding, it is impossible to arrange the fine pass-through wiring in the region under the bonding pad. Therefore, it is impossible to effectively utilize the region under the bonding pad. SUMMARY OF THE INVENTION It is therefore an object of this invention to provide a semiconductor apparatus having a bonding pad which is capable of preventing a wiring from being peeled off or broken due to a mechanical shock during bonding and which allows a fine pass-through wiring to be arranged under the bonding pad. Semiconductor apparatuses according to this invention are as follows: (1) A semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus comprising a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. (2) The semiconductor apparatus according to the paragraph (1), wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern. (3) The semiconductor apparatus according to the paragraph (1), wherein the first conductive plug is made of a conductive material harder than aluminum. (4) The semiconductor apparatus according to the paragraph (3), wherein the conductive material includes tungsten. (5) The semiconductor apparatus according to the paragraph (2), further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires and in parallel to the plurality of first-layer plug wires. (6) The semiconductor apparatus according to the paragraph (2), the plurality of first-layer plug wires arranged in the region under the bonding pad has a pattern rate not smaller than 20% and not greater than 50%. (7) The semiconductor apparatus according to the paragraph (5), wherein the plurality of first-layer plug wires and the first-layer pass-through wires in the region under the bonding pad have a total pattern rate not smaller than 20% and not greater than 60%. (8) The semiconductor apparatus according to the paragraph (1), further comprising a second-layer plug wire formed by a second lower wiring layer under the first lower wiring layer, and a second conductive plug connecting the first-layer plug wire and the second-layer plug wire. (9) The semiconductor apparatus according to the paragraph (8), wherein the first and the second conductive plugs are formed at the same position in plan view to overlap each other. (10) The semiconductor apparatus according to the paragraph (8), wherein the first-layer plug wire comprises a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern, the second-layer plug wire comprising a plurality of second-layer plug wires arranged in a stripe pattern to be orthogonal to the plurality of first-layer plug wires. (11) The semiconductor apparatus according to the paragraph (10), further comprising first-layer pass-through wires arranged between adjacent ones of the plurality of first-layer plug wires, and second-layer pass-through wires arranged between adjacent ones of the plurality of second-layer plug wires, the first-layer pass-through wires being connected to the second-layer pass-through wires. In this invention, the striped plug wiring is arranged in the region under the bonding pad. The plug wiring and the pad wiring are connected to each other by the conductive plug. The plug wiring as a lower layer and the pad wiring as an upper layer are connected by the conductive plug. The conductive plug serves as a pile for preventing the bonding pad from being easily peeled off. Therefore, it is possible to prevent the pad wiring from being peeled off. Since a mechanical shock during bonding is absorbed by the conductive plug, it is possible to prevent breakage of a thin wiring under the bonding pad. Furthermore, a pattern rate is assured by the plug wiring. As the density of a pattern is approximate to the pattern rate of an internal circuit portion, it is easy to determine etching and CMP (Chemical Mechanical Polishing) conditions and so on in a diffusion process. The wiring of a fine pattern equivalent in fineness to the internal circuit portion can be used as a pass-through wiring under the bonding pad. In addition, a diffusion yield is improved. BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a plan view of a related bonding pad using a plug formed throughout an entire area of the bonding pad; FIG. 2 is a plan view of another related bonding pad with a pass-through wiring; FIG. 3 is a plan view for describing a bonding pad in a first embodiment of this invention; FIG. 4 is a sectional view taken along a line 4-4 in FIG. 3; FIG. 5 is a sectional view taken along a line 5-5 in FIG. 3; FIG. 6 is a layout view of a semiconductor chip; FIG. 7 is a view showing wires passing through a region under the bonding pad in an X direction; FIG. 8 is a view showing wires passing through a space between the bonding pads in a Y direction; FIG. 9 is a view showing wires passing through the region under the bonding pad in the Y direction; FIG. 10 is a view showing connection between pass-through wires in the X direction and the Y direction under the bonding pad; FIG. 11 is a view for describing dimensions of wires in the bonding pad; FIG. 12 is a view showing dimensions between the bonding pads; FIG. 13 is a plan view of a bonding pad according to a second embodiment of this invention in which #2 aluminum wires and #1 aluminum wires are arranged in parallel; FIG. 14 is a sectional view taken along a line 14-14 in FIG. 13; FIG. 15 is a plan view of a modification of the bonding pad in the second embodiment without the #1 aluminum wires; and FIG. 16 is a sectional view taken along a line 16-16 in FIG. 15. DESCRIPTION OF THE PREFERRED EMBODIMENTS Now, description will be made of embodiments of this invention with reference to the drawing. First Embodiment Referring to FIGS. 3 to 12, a first embodiment of this invention will be described in detail. Referring to FIGS. 3 through 5, a bonding pad in the first embodiment will be described. In this embodiment, a three-layer aluminum product is described by way of example. The bonding pad comprises a #3 aluminum wiring layer as an uppermost wiring layer, a #2 aluminum wiring layer, and a #1 aluminum wiring layer as a lowermost wiring layer. The #1 aluminum wiring layer has #1 aluminum plug wires 11 and #1 aluminum pass-through wires 12 both of which extend in a Y direction. The #2 aluminum wiring layer has #2 aluminum plug wires 21, #2 aluminum pass-through wires 22, and #2 aluminum pad connection wires 23, all of which extend in an X direction. The #3 aluminum wiring layer has a #3 aluminum pad wire 30 to become the bonding pad. The #1 aluminum plug wires 11 and the #2 aluminum plug wires 21 are connected by #1-#2 layer conductive plugs 41. The #2 aluminum plug wires 21 and the #3 aluminum pad wire 30 are connected by #2-#3 layer conductive plugs 42. The #1-#2 layer conductive plugs 41 and the #2-#3 layer conductive plugs 42 are formed on substantially same positions in plan view and overlap each other. The conductive plugs 41 and 42 serve as piles to prevent the #3 aluminum pad wire 30 from being peeled off during bonding and to protect the #1 aluminum pass-through wires 12 and the #2 aluminum pass-through wires 22. On an upper surface of a first interlayer insulating film 2, the #1 aluminum plug wires 11 and the #1 aluminum pass-through wires 12 are patterned as a #1 aluminum pattern. The #1 aluminum plug wires 11 are aluminum wires for forming the conductive plugs. The #1 aluminum pass-through wires 12 pass through a region under the bonding pad and are connected to internal circuits. Further, a second interlayer insulating film 3 is deposited. The second interlayer insulating film 3 is provided with the #1-#2 layer conductive plugs 41 connecting the #1 aluminum plug wires 11 and the #2 aluminum plug wires 21. On an upper surface of the second interlayer insulating film 3, the #2 aluminum plug wires 21, the #2 aluminum pass-through wires 22, and the #2 aluminum pad connection wires 23 are patterned as a #2 aluminum pattern. The #2 aluminum plug wires 21 are aluminum wires for forming the conductive plugs. The #2 aluminum plug wires 22 pass through the region under the bonding pad and are connected to the internal circuits. The #2 aluminum pad connection wires 23 serve to connect signals from the bonding pad to the internal circuits. Further, a third interlayer insulating film 4 is deposited. The third interlayer insulating film 4 is provided with the #2-#3 layer conductive plugs 42 connecting the #2 aluminum plug wires 21 and the #3 aluminum pad wire 30. On an upper surface of the interlayer insulating film 4, the #3 aluminum pad wire 30 is patterned as a #3 aluminum pattern. On the #3 aluminum pad wire 30, a polyimide 5 is applied. The polyimide 5 on the #3 aluminum pad wire 30 is provided with an opening portion to serve as the bonding pad 1. The bonding pad 1 basically is an area of the #3 aluminum pad wire 30 corresponding to the opening portion formed in the polyimide 5. However, the bonding pad 1 also represents a region including related wires substantially similar in size, such as an outer shape of the #1 aluminum plug wires and the #2 aluminum plug wires or a whole of the #3 aluminum pad wire 30. In a bonding pad region, the #1 aluminum plug wires 11 and the #2 aluminum plug wires 21 are patterned in a stripe fashion and extend in the Y direction and the X direction, respectively, to be orthogonal to each other. At intersection points of the #1 aluminum plug wires 11 and the #2 aluminum plug wires 21, the #1 aluminum plug wires 11 and the #2 aluminum plug wires 21 are connected to each other by the #2-#3 layer conductive plugs 41. Further, at the intersection points of the #2 aluminum plug wires 21 and the #3 aluminum pad wire 30, the #2 aluminum plug wires 21 and the #3 aluminum pad wire 30 are connected to each other by the #2-#3 layer conductive plugs 42. The #1-#2 layer conductive plugs 41 and the #2-#3 layer conductive plugs 42 are formed at substantially same positions in plan view and overlap each other. Although the #2 aluminum layer is interposed therebetween, these plugs serve as a single plug. By such overlapping arrangement, the function as the pile is more effective. The area (or size) and the number of the conductive plugs are selected so as to prevent peeling of the bonding pad and breakage of the pass-through wires. Generally, tungsten is used as a material of the conductive plugs. Tungsten is harder than aluminum so that a mechanical shock from upside during bonding is absorbed by the conductive plugs. Therefore, even if the #1 aluminum pass-through wires 12 and the #2 aluminum pass-through wires 22 which are thin wires are arranged through a space between the #1 aluminum plug wires 11 and the #2 aluminum plug wires 21, the #1 aluminum pass-through wires 12 and the #2 aluminum pass-through wires 22 are not broken under the mechanical shock during bonding. The material of the conductive plugs is not specifically limited and any material harder than aluminum (for example, having a high Young's modulus), including tungsten, may be used. Further, an alloy comprising a plurality of kinds of such materials or a laminated structure comprising a plurality of layers of such materials may be used. The #1 aluminum plug wires 11 and the #2 aluminum plug wires 21 arranged in an area slightly wider than the area of the bonding pad 1 corresponding to the opening portion formed in the polyimide 5. Herein, the #1 aluminum plug wires 11, five in number, are disposed in a stripe pattern. Likewise, the #2 aluminum plug wires 21, five in number, are disposed in a stripe pattern. By presence of the #1 aluminum plug wires and the #2 aluminum plug wires 21, the pattern rates of the #1 aluminum layer and the #2 aluminum layer can be optimized. In the related bonding pad in FIG. 1 or 2, a solid pattern or a substantial no pattern is formed in the region under the bonding pad. On the other hand, in this embodiment, the pattern has a density similar to that of an internal circuit portion by presence of the #1 aluminum plug wires 11, the #2 aluminum plug wires 21, the #1 aluminum pass-through wires 12, and the #2 aluminum pass-through wires 22. Therefore, it is easy to determine etching and CMP conditions in a diffusion process. Since the optimum conditions are obtained, a diffusion yield is improved. Next, description will be made of a case where this embodiment is applied to an actual semiconductor apparatus. Herein, a DRAM chip of a center bonding type is described as the semiconductor apparatus. The DRAM chip of a center bonding type illustrated in FIG. 6 comprises four memory cell portions 6 disposed upper left, upper right, lower left, and lower right, respectively. At a center portion between the upper and the lower memory cell portions 6, a plurality of the bonding pads 1 are arranged in a single row. Signals from the respective bonding pads 1 are connected to the memory cell portions 6 by the use of a space in the center portion. A layout width (H) of a region including the bonding pads is often determined by the limit number of signal lines (or wires) extending in a longitudinal direction of the chip. In this invention, wires to be generally extended in a signal line region other than the bonding pad region can be extended in the bonding pad region. Therefore, it is possible to reduce the layout width (H) which has been determined by the limit number of the signal lines extending in the longitudinal direction of the chip. Thus, it is possible to reduce the chip size. For example, it is possible to lay a power supply line under the bonding pad as illustrated in FIG. 7. If it is desired to extract two power supply lines from a power supply pad, it is possible to connect a power supply for a reference circuit and a power supply for an ordinary circuit through different power supply lines, respectively. In FIG. 7, three bonding pads are shown as a VDD pad 1-1, a GND pad 1-2, and a signal pad 1-3. From each of the VDD pad 1-1 and the GND pad 1-2, a power supply line is extended in the Y direction in the figure as a power supply line for the ordinary circuit. From each of the VDD pad 1-1 and the GND pad 1-2, two power supply lines are extended in the X direction in the figure as power supply lines for the reference circuit. A special power supply for feeding the reference circuit requiring a stable power supply with less fluctuation can be extracted through the region under the bonding pad to a position near a region where the reference circuit is disposed. Therefore, it is possible to reserve a region for signal lines correspondingly. This structure is effective in reducing the chip size. In FIG. 7, for simplicity of illustration, the #1 aluminum plug wires 11, #2 aluminum plug wires 21, the #1-#2 layer conductive plugs 41, and the #2-#3 layer conductive plugs 42 are not illustrated. Hereinafter, illustration of the aluminum plug wires and the layer conductive plugs may similarly be omitted. Description will be made of a case where signal lines or power supply lines must be laid between the bonding pad regions. Referring to FIG. 8, in a conventional related bonding pad, a pad pitch must be widened to a pitch L2 to reserve a signal line region. This results in an increase in chip size. On the other hand, in a bonding pad structure of this invention, signal lines or power supply lines can be laid in the region under the bonding pad as illustrated in FIG. 9. Therefore, a number of wires or a thick power supply line can be laid without widening the pitch L1 of the bonding pads. Thus, this invention is effective in reducing the chip size in the longitudinal direction. In the bonding pad structure of this invention, as shown in FIG. 10, the #1 aluminum pass-through wires 12 and the #2 aluminum pass-through wires 22 as vertical and horizontal wires of a lower wiring layer passing through the region under the bonding pad can be connected via the #1-#2 layer conductive plugs 41 in the bonding pad region. The size and the various standards of the bonding pad are slightly different depending upon the type of a package and the performance of the bonding apparatus. Referring to FIG. 11, description will be made of the dimensions of the bonding pad in connection with the case where a typical bonding apparatus for a TSOP (Thin Small Outline Package) package is used. The #1 aluminum plug wires and the #2 aluminum plug wires have an outer shape having one side (a) equal to 85 μm. Each of the #2 and the #1 aluminum plug wires has a pattern width (b) equal to 5 μm. Then, an interval (c) between every two adjacent ones of the aluminum plug wires is equal to 15 μm. Therefore, one region allowing the pass-through wires in the lower layer to pass through has a size of 15 μm. In this region of 15 μm, 13 pass-through wires are allowed to pass through if each pass-through wire has a width of 0.5 μm, the interval is 0.5 μm, and the pitch is 1 μm. Therefore, in the bonding pad region as a whole, 52 (13×4) pass-through wires are allowed to pass through. In the chip illustrated in FIG. 6, the layout width (H) around the bonding pad is determined by the limit number of the signal lines extending in the longitudinal direction of the chip. In this case, 52 signal lines to be generally extended in the signal line region except the bonding pad region are allowed to pass through the bonding pad region. Therefore, the layout width (H) can be reduced by about 52 μm at maximum. In FIG. 11, the power supply lines are allowed to pass through the region of the interval (c) between the aluminum plug wires. In this event, assuming that an interval margin of 1 μm is secured on opposite sides of each region of 15 μm, the power supply line of 13 μm wide is allowed to pass through. In one bonding pad region as a whole, 4 power supply lines each having a width of 13 μm are allowed to pass through. Therefore, the layout width (H) can be reduced by about 52 μm at maximum. By forming the plug wires in the bonding pad region, the pattern rate of the #1 aluminum and the #2 aluminum layers can be optimized. In case where 5 plug wires each having a width of 5 μm are arranged in the region of 85 μm, the pattern rate is about 30%. If 13 wires each having a width of 0.5 μm are arranged between the plug wires, the pattern rate is about 37%. In case where 52 wires as the maximum number are arranged, the pattern rate is about 60%. At such pattern rate, excellent etching and CMP conditions can be obtained so that a fine pattern can be formed. Therefore, a fine pattern can be used as the aluminum pass-through wires. Generally, the pattern rate at which the excellent etching and CMP conditions are obtained is 20% to 60%, more preferably, 40% to 50%. Therefore, a plug wiring pattern is determined so that the pattern rate is not smaller than the minimum pattern rate. For example, it is assumed that the bonding pad has one side of 100 μm and the plug wires are stripe lines, five in number, each having a width of 4 μm. Then, the pattern rate is 20%. Thus, the minimum pattern rate is assured by the striped plug wiring pattern. Further, the pass-through wires each having a width of 0.5 μm are arranged at a pitch of 1 μm. In this case, 78 pass-through wires can be arranged at maximum. If the maximum number of the pass-through wires are arranged, the pattern rate is 59% (5×4 μm for the plug wires and 0.5×78 μm for the pass-through wires). Thus, the minimum pattern rate is assured by the plug wiring pattern and the pattern rate approaches that of the internal circuit region by presence of the pass-through wires. By making the pattern rate be nearer to that of the internal circuit region, the pass-through wires can be finer. Referring to FIG. 12, in case where a plurality of pads are arranged adjacent to one another, the pitch of the pads is about 98 μm at minimum. The pad size is 85 μm and a space of 13 μm is left between two adjacent pads. Traditionally, by the use of this space, signal lines can be laid between upside and downside of the layout on opposite sides of the bonding pad region. However, if a number of wires or a thick power supply line must be laid and the space of 13 μm is insufficient, the pitch between the two adjacent pads must be widened. This results in an increase in chip size in the longitudinal direction. According to this invention, the signal lines between upside and downside of the layout on opposite sides of the pad region can be extended in the region under the bonding pad as shown in FIG. 9. Therefore, without widening the pitch between two adjacent pads, a number of wires or a thick power supply line can be laid. This is effective in reducing the chip size in the longitudinal direction. As shown in FIG. 10, it is possible to connect, by the conductive plugs, the vertical and the horizontal pass-through wires in the region under the bonding pad. Thus, the signal lines can be freely laid even if the signal lines pass through the region under the bonding pad. In this embodiment, the plug wires are arranged under the bonding pad and connected to the pad wires by the conductive plugs. By the use of a hard material as the conductive plugs, a mechanical shock during bonding is absorbed by the conductive plugs. With this structure, it is possible to prevent peeling of the bonding pad and breakage of the pass-through wires under the bonding pad due to the mechanical shock during bonding. The plug wiring pattern is determined so as to achieve the pattern rate not smaller than the minimum pattern rate. By maintaining the minimum pattern rate by the plug wiring pattern and making the pattern rate be nearer to that of the internal circuit region, the pass-through wires can be finer. Second Embodiment Referring to FIGS. 13 to 16, description will be made of a second embodiment of this invention. In this embodiment, the pass-through wires are laid in the same direction. Like in the first embodiment, a three-layer aluminum product will be described by way of example. As shown in FIGS. 13 and 14, #1 aluminum plug wires 11, #1 aluminum pass-through wires 12, #2 aluminum plug wires 21, and #2 aluminum pass-through wires 22 are arranged to extend in the X direction in the figures. #2 aluminum pad connection wires 23, a #3 aluminum pad wire 30, interlayer insulating films 2, 3, and 4, and polyimide 5 are similar to those in the first embodiment. Therefore, each of #1-#2 layer conductive plugs 41 and #2-#3 layer conductive plugs 42 is formed in a rectangular shape along the respective plug wires. This embodiment is applied in case where a large number of signal wires are arranged in the X direction in the DRAM illustrated in FIG. 6. Referring to FIGS. 15 and 16, a #2 aluminum pattern as a single wiring layer is arranged in a region under a bonding pad without a #1 aluminum pattern. As compared with the example illustrated in FIGS. 13 and 14, the #1 aluminum plug wires 11, the #1 aluminum pass-through wires 12, the #1-#2 layer conductive plugs 21 are omitted. The remaining parts are similar to those in FIGS. 13 and 14 and will not be described. Thus, the #1 aluminum and the #2 aluminum wires are freely arranged without limitation. In this embodiment also, the plug wires are arranged under the bonding pad and connected to the pad wires by the conductive plugs. By the use of a hard material as the conductive plugs, a mechanical shock during bonding is absorbed by the conductive plugs. With this structure, it is possible to prevent peeling of the bonding pad and breakage of the pass-through wires under the bonding pad due to the mechanical shock during bonding. The plug wiring pattern is determined so as to achieve the pattern rate not smaller than the minimum pattern rate. By maintaining the minimum pattern rate by the plug wiring pattern and making the pattern rate be nearer to that of the internal circuit region, the pass-through wires can be finer. While the present invention has thus far been described in connection with the preferred embodiments thereof, the present invention is not limited thereto. It will readily be possible for those skilled in the art to put this invention into practice in various other manners within the scope of the present invention.	H	67H01	185H01L	23	52
11718389	US20070296406A1-20071227	Current Induced Magnetoresistance Device	ACCEPTED	20071212	20071227	[]	H01L4308	["H01L4308", "G01R3309", "G11C1116"]	7626857	20070501	20091201	365	158000	99911.0	LUU	PHO	[{"inventor_name_last": "Shin", "inventor_name_first": "Kyung-Ho", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Hoany Yen", "inventor_name_first": "Nguyen", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Yi", "inventor_name_first": "Hyun-Jung", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}]	The present invention provides for a current induced switching magnetoresistance device comprising a magnetic multilayer composed of a first ferromagnetic layer, a nonferromagnetic layer, and a second ferromagnetic layer, wherein the first ferromagnetic layer has an upper electrode, the second ferromagnetic layer pinned by an antiferromagnet, wherein the antiferromagnet contains a lower electrode at its lower part, and the second ferromagnetic layer is embedded with a nano oxide layer. It is preferable to have at least a part of the lower electrode in contact with the second ferromagnetic layer. The magnetoresistance device of the present invention provides a lower critical current (Ic) for the magnetization reversal and has an increased resistance.	1. A current induced switching magnetoresistance device comprising: a multilayered structure consisted of a first ferromagnetic layer, a non-ferromagnetic layer and a second ferromagnetic layer; an upper electrode provided in the first ferromagnetic layer; an antiferromagnet pinned at the second ferromagnetic layer; and a lower electrode at the lower part of the antiferromagnet, wherein the second ferromagnetic layer is embedded with a nano oxide layer. 2. The current induced switching magnetoresistance device of claim 1, characterized in that the lower electrode is in contact with at least a part of the second ferromagnetic layer. 3. The current induced switching magnetoresistance device of claim 1, characterized in that the second ferromagnetic layer is thicker than the first ferromagnetic layer. 4. The current induced switching magnetoresistance device of claim 1 characterized in that the nano oxide layer has a thickness between 1 to 5 Å. 5. The current induced switching magnetoresistance device of claim 1, characterized in that the current flows perpendicular to the plane of the layers. 6. The current induced switching magnetoresistance device of claim 1, wherein the magnetization direction of the first ferromagnetic layer can be switched depending on the current induced and the magnetization direction of the second ferromagnetic layer can be fixed by the anti-ferromagnetic layer. 7. A current induced switching magnetoresistance device comprising: a multilayered structure consisted of a first ferromagnetic layer, a non-ferromagnetic layer and a second ferromagnetic layer; an upper electrode at an upper part of the first ferromagnetic layer; an anti-ferromagnetic layer at a lower part of the second ferromagnetic layer; and a lower electrode at the lower part of the antiferromagnet, wherein the lower electrode is in contact with at least a part of the second ferromagnetic layer. 8. A magnetic memory apparatus using the current induced switching magnetoresistance device of claim 1.	<SOH> BACKGROUND ART <EOH>Since a great magnetoresistance (GMR) was discovered in a ferromagnetic thin film, its application has been suggested to various fields. A typical application thereof is a magnetic random access memory (MRAM), which is a solid-state memory that can re-write and read recorded data many times by using magnetization direction of ferromagnets. A unit cell in an MRAM has a multilayered ferromagnet-laminated structure. The relative alignment (being parallel or antiparallel) of the magnetization of the multilayers that consists the memory cell corresponds to “0” or “1” in binary data for recording. An MRAM has theoretically zero power consumption for maintaining data, and it corresponds to a nonvolatile memory that can maintain the data even when the power is off. The MRAMs utilize magnetoresistance devices which typically have a tri-layered structure of free-ferromagnet/spacer/fixed-ferromagnet. The spacer can be either an insulator, as in a magnetic tunnel junction (MTJ), or a non-magnetic metal, as in a spin valve. In those devices, the magnetic sensitivity and device's performance can be improved by adding a pinning layer, such as an antiferromagnet (AFM) or a synthetic antiferromagnet (SAF), adjacent to the fixed-ferromagnet to magnetically pin it in one direction. Conventionally, data recording (writing process) is performed by reversing the magnetization direction of the free-ferromagnet through electromagnetic field generated by a current flow in a bit line and a word line, perpendicular to each other, and both parallel to the ferromagnet plane. This field-induced magnetization switching method exhibits an inherent disadvantage that the switching field, therefore the required current, is drastically increased with decreasing size of the cells. Furthermore, crosstalk between the adjoining lines and cells becomes serious when the cell-distance is small. These put a limitation on increasing the density of the magnetic memory device. In contrast, the current-induced magnetization switching (CIMS), a novel attractive alternative, allows to solve those problems. In the CIMS, a current flows perpendicular to plane of a ferromagnet can reverse its magnetization due to spin torque transferred from the spin-polarized conduction electrons to the magnet. The free-ferromagnet can be switched in parallel or antiparallel direction with the fixed ferromagnet when the current flows from the free to the fixed layers, or from the fixed to the free, respectively. In this mechanism, switching occurs when the current density reaches a critical value which is dependent on the spin-transfer efficiency of the current in that device. Therefore, in the same device structure, the smaller the size is, the lower switching current is required. However, there are two critical issues to be solved so that CIMS can be applied in real devices: the switching current density must be lowered and the output signal of the device must be increased.	<SOH> SUMMARY OF THE INVENTION <EOH>In order to solve the above-mentioned critical issues, the present invention provides for a current-induced magnetization switching (CIMS) device comprising a multilayered laminated structure consisting of a first ferromagnetic layer, a nonmagnetic layer and a second ferromagnetic layer, wherein the first ferromagnetic layer contains an upper electrode, the second ferromagnetic layer pinned by an antiferromagnet and a lower electrode at the lower part of the antiferromagnet, and the nano-oxide layer is embedded in the second ferromagnetic layer. Additionally, the present invention provides for a current-induced switching magnetoresistance device comprising a multilayered junctions consisting of a first ferromagnetic layer, a nonmagnetic layer and a second ferromagnetic layer, wherein the upper part of the first ferromagnetic layer contains an upper electrode, the second ferromagnetic layer is pinned with an antiferromagnet, a lower electrode at the lower part of the antiferromagnet, and the lower electrode is in contact with at least a part of the second ferromagnetic layer. The CIMS device according to the present invention provides for a low critical switching current for the magnetization reversal and an increased resistance, thereby achieving an improved critical value, and therefore, the same device structure can be applied in various devices, especially in memory magnetoresistance devices. The current induced magnetization direction of the CIMS device according to the present invention is preferably in perpendicular to each layer of the device and is in contact with at least a part of the second ferromagnetic layer. The CIMS device of the present invention reverses the magnetization direction of the ferromagnetic layers, thereby exhibiting current-induced magnetization switching effect. Particularly, since reversing the magnetization of this structure is by a current perpendicular to the plane of layers, it has an advantage of improving the integration	TECHNICAL FIELD The present invention relates to a current induced magnetoresistance device, more particularly to a newly structured device that, by having an extended exchange biased pinned ferromagnetic thin film with an embedded nano-oxide layer, can be switched at lower current density and simultaneously provides an increasing change in absolute resistance at switching points. BACKGROUND ART Since a great magnetoresistance (GMR) was discovered in a ferromagnetic thin film, its application has been suggested to various fields. A typical application thereof is a magnetic random access memory (MRAM), which is a solid-state memory that can re-write and read recorded data many times by using magnetization direction of ferromagnets. A unit cell in an MRAM has a multilayered ferromagnet-laminated structure. The relative alignment (being parallel or antiparallel) of the magnetization of the multilayers that consists the memory cell corresponds to “0” or “1” in binary data for recording. An MRAM has theoretically zero power consumption for maintaining data, and it corresponds to a nonvolatile memory that can maintain the data even when the power is off. The MRAMs utilize magnetoresistance devices which typically have a tri-layered structure of free-ferromagnet/spacer/fixed-ferromagnet. The spacer can be either an insulator, as in a magnetic tunnel junction (MTJ), or a non-magnetic metal, as in a spin valve. In those devices, the magnetic sensitivity and device's performance can be improved by adding a pinning layer, such as an antiferromagnet (AFM) or a synthetic antiferromagnet (SAF), adjacent to the fixed-ferromagnet to magnetically pin it in one direction. Conventionally, data recording (writing process) is performed by reversing the magnetization direction of the free-ferromagnet through electromagnetic field generated by a current flow in a bit line and a word line, perpendicular to each other, and both parallel to the ferromagnet plane. This field-induced magnetization switching method exhibits an inherent disadvantage that the switching field, therefore the required current, is drastically increased with decreasing size of the cells. Furthermore, crosstalk between the adjoining lines and cells becomes serious when the cell-distance is small. These put a limitation on increasing the density of the magnetic memory device. In contrast, the current-induced magnetization switching (CIMS), a novel attractive alternative, allows to solve those problems. In the CIMS, a current flows perpendicular to plane of a ferromagnet can reverse its magnetization due to spin torque transferred from the spin-polarized conduction electrons to the magnet. The free-ferromagnet can be switched in parallel or antiparallel direction with the fixed ferromagnet when the current flows from the free to the fixed layers, or from the fixed to the free, respectively. In this mechanism, switching occurs when the current density reaches a critical value which is dependent on the spin-transfer efficiency of the current in that device. Therefore, in the same device structure, the smaller the size is, the lower switching current is required. However, there are two critical issues to be solved so that CIMS can be applied in real devices: the switching current density must be lowered and the output signal of the device must be increased. SUMMARY OF THE INVENTION In order to solve the above-mentioned critical issues, the present invention provides for a current-induced magnetization switching (CIMS) device comprising a multilayered laminated structure consisting of a first ferromagnetic layer, a nonmagnetic layer and a second ferromagnetic layer, wherein the first ferromagnetic layer contains an upper electrode, the second ferromagnetic layer pinned by an antiferromagnet and a lower electrode at the lower part of the antiferromagnet, and the nano-oxide layer is embedded in the second ferromagnetic layer. Additionally, the present invention provides for a current-induced switching magnetoresistance device comprising a multilayered junctions consisting of a first ferromagnetic layer, a nonmagnetic layer and a second ferromagnetic layer, wherein the upper part of the first ferromagnetic layer contains an upper electrode, the second ferromagnetic layer is pinned with an antiferromagnet, a lower electrode at the lower part of the antiferromagnet, and the lower electrode is in contact with at least a part of the second ferromagnetic layer. The CIMS device according to the present invention provides for a low critical switching current for the magnetization reversal and an increased resistance, thereby achieving an improved critical value, and therefore, the same device structure can be applied in various devices, especially in memory magnetoresistance devices. The current induced magnetization direction of the CIMS device according to the present invention is preferably in perpendicular to each layer of the device and is in contact with at least a part of the second ferromagnetic layer. The CIMS device of the present invention reverses the magnetization direction of the ferromagnetic layers, thereby exhibiting current-induced magnetization switching effect. Particularly, since reversing the magnetization of this structure is by a current perpendicular to the plane of layers, it has an advantage of improving the integration BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a sectional view of one embodiment of a current induced magnetoresistance switching device of the present invention. FIG. 2 is a sectional view of another embodiment of current induced magnetoresistance switching device of the present invention. FIG. 3 is a sectional view of yet another embodiment of current induced magnetoresistance switching device of the present invention. FIG. 4 is a graph that shows the changes in the resistance of a current induced magnetoresistance switching device of the present invention with or without a nano oxide layer. FIG. 5 is a graph that shows the current-voltage characteristic of a current induced magnetoresistance switching device having a simple spin-valve structure according to the present invention. FIG. 6 is a graph that shows the current-voltage characteristic of a current induced magnetoresistance switching device without a nano oxide layer according to the present invention. FIG. 7 is a graph that shows the current-voltage characteristic of a current induced magnetoresistance switching device that includes a nano oxide layer according to the present invention. DETAILED DESCRIPTION OF THE INVENTION FIG. 1 represents a sectional view of one embodiment of the CIMS according to the present invention. The first ferromagnetic layer (100) and the second ferromagnetic layer (110) are positioned between a nonmagnetic layer (105) which is consisted of a nonmagnetic material that acts as a spacer, thus forming a laminated structure. Such a laminated structure forms a magnetic tunnel junction (MTJ), and by depending on the magnetization direction of the two ferromagnetic layers, the current that tunnels through the nonmagnetic layer changes. By exchange coupling through exchange bias, the antiferromagnet (130) in the second ferromagnetic layer (110) pins the magnetization direction of the second ferromagnetic layer (110) in one direction. By pinning the second ferromagnetic layer (110), the antiferromagnet (130) substantially maintains several magnetic domains inside the second ferromagnetic layer (110) as a single magnetic domain. Unlike the second ferromagnetic layer (110), the magnetization direction of the first ferromagnetic layer (100) can be freely reversed, depending on the induced current. Therefore, the resistance to the magnetic device with the multilayered laminated structure can overall vary by induced current. In other words, the resistance of the device can be controlled by current. The second ferromagnetic layer (110) includes therein a thin, preferably in nanometer thickness, nano-oxide layer (120). The nano-oxide layer (120) inhibits depolarization that is caused by the presence of antiferromagnet (130). The nano-oxide layer (120) acts as a kind of a mirror with respect to electrons so that it promotes the spin-dependent sputtering caused by the specular reflecting of conductive electrons. Accordingly, GMR effect of the device can be increased. A device having such structure decreases the critical current (Ic) at which the magnetization reversal occurs and increases the magnetic resistance as well, so that its applicability to memory devices can be improved. Reference numerals 140a and 140b represent the upper electrode and the lower electrode, respectively. FIGS. 2 and 3 show sectional views of another embodiment of the present invention. In FIG. 2, although this embodiment is similar to the embodiment of FIG. 1 in terms of having a laminated structure, this embodiment shows that the lower electrode (140b) is in contact with at least a part of the second ferromagnetic layer (110). Such structure makes electrons flow smoothly and avoids conduction electrons from getting resistance by the antiferromagnet (130). Since the lower electrode (140b) is in contact with the second ferromagnetic layer (110), the most of the current flows through the second ferromagnetic layer (110) rather than through the lower electrode (140b). Therefore, the critical current (Ic) can be further decreased. FIG. 3 shows a structure where the second ferromagnetic layer (110) is extended to the surface of the lower electrode. The most of current in this structure also flows through the second ferromagnetic layer (110) rather than through the lower electrode (140b). The current induced switching magnetoresistance devices can be manufactured by using standard semiconductor processes. Particularly, reactive ion beam technology can be used for forming the laminated structure. However, there are no special manufacturing limitations that are required, and a variety of conventional thin-film processes could be used. The present invention will be further illustrated by the following examples in order to provide a better understanding of the invention. However, the present invention is not limited to the examples, and particularly, other materials that are within the technical effect of the present invention can be used for the composition of the layers. EXAMPLE After preparing the first ferromagnetic layer and the second ferromagnetic layer using cobalt (Co) thins films of 2 nm and 11 nm in thicknesses respectively, the nonmagnetic layer of copper thin film of 6 nm in thickness to be pinned between the ferromagnetic layers was prepared. After forming the first ferromagnetic layer such that it is thinner than the second ferromagnetic layer, an antiferromagnet was formed using IrMn thin film of 8 nm in thickness through exchange coupling at the lower part of the second ferromagnetic layer. In addition, an oxide layer of less than 5 Å was formed when forming the second ferromagnetic layer. The upper part and the lower part of the laminated structure were formed with copper (Cu) electrode of 5 nm respectively, and the lower part of the electrode was formed such that at least a part of the second ferromagnetic layer is in contact with the electrode. In order to compare the magnetoresistance device of the present invention, a device without a nano-oxide layer embedded and a simple spin-valve structured magnetoresistance device were also prepared using the same materials as the magnetoresistance device of the present invention. FIG. 4 shows the changes in the resistance of the magnetoresistance device of the present invention depending on the presence/non-presence of the nano-oxide layer. According to FIG. 4, the nano-oxide layer could induce an increase in the resistance change of 20%. Conclusively, the resistance was increased due to the presence of nano-oxide layer. To confirm the magnetoresistance and the critical current of the device, the current-voltage characteric by the Four-Point Probe was measured. FIG. 5 shows the current-voltage characteristic of a simple spin-valve, FIG. 6 shows the current voltage characteristic of a magnetoresistance device without nano oxide layer, and FIG. 7 shows the current-voltage characteristic of a magnetoresistance device with nano oxide layer. The following Table 1 compares the results of the critical current (Ic) and the magnetoresistance ratio (ΔR/R) of each of the devices. TABLE 1 Magneto- resistance Ratio Type of Structure Critical Current (lc) (ΔR/R) Simple Spin-Valve 3.5˜2.4 × 107 A/cm2 2.5˜2.7% (without anti-ferromagnetic layer) Nano oxide layer excluded; 1.6 × 108 A/cm2 0.36% Electrode is not in contact with the second ferromagnetic layer Nano oxide layer excluded; 7.5 × 106 A/cm2 0.75% Electrode is in contact with the second ferromagnetic layer Nano oxide layer included; 9.4 × 106 A/cm2 2.5% Electrode is in contact with the second ferromagnetic layer As shown in Table 1, even though the Simple Spin-Valve System neither contains the nano oxide layer nor the antiferromagnet for the exchange bias and has a high magnetoresistance ratio, it has a disadvantage of having the critical current too high. When the antiferromagnetic layer was neither in contact with the second ferromagnetic layer nor had a nano-oxide layer, the results still showed an increased critical current and a poor magnetoresistance. However, by having the electrode in contact with the second ferromagnetic layer, the critical current was significantly lowered, and furthermore, by including a nano-oxide layer, the magnetoresistance was also improved.	H	67H01	185H01L	43	08
11745044	US20080277730A1-20081113	Semiconductor Device Manufactured Using a Laminated Stress Layer	ACCEPTED	20081029	20081113	[]	H01L2144	["H01L2144", "H01L2976"]	7611939	20070507	20091103	257	213000	95355.0	SANDVIK	BENJAMIN	[{"inventor_name_last": "Mehrotra", "inventor_name_first": "Manoj", "inventor_city": "Plano", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Rotondaro", "inventor_name_first": "Antonio L.P", "inventor_city": "Dallas", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Kohli", "inventor_name_first": "Puneet", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}]	There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.	1. A method of manufacturing a semiconductor device, comprising: forming gate structures over a semiconductor substrate, including forming gate electrodes and spacers adjacent the gate electrodes; forming source/drains adjacent the gate structures; forming a laminated stress layer over the gate structures and the semiconductor substrate, including cycling a deposition process to form a first stress layer over the gate electrodes and the semiconductor substrate and at least a second stress layer over the first stress layer; and annealing the laminated stress layer at a temperature of about 900° C. or greater. 2. The method recited in claim 1, wherein a height to gap ratio between electrode structures ranges from about 0.9 to about 1.5. 3. The method recited in claim 1, wherein the first and at least second stress layers are formed by chemical vapor deposition and by flowing SiH4 at a flow rate ranging from about 50 sccm to about 700 sccm and N2 or NH3 at a flow rate ranging from about 500 sccm to about 6000 sccm, and at a pressure ranging from about 1 torr to about 50 torr and a temperature ranging from about 300° C. to about 500° C. 4. The method recited in claim 1, wherein cycling the deposition process includes pausing the deposition between the formation of the at least first and second stress layers for a period of time ranging from about 5 sec to about 5 minutes. 5. The method recited in claim 1, wherein the annealing is performed using a thermal anneal, a laser anneal, or a combination thereof. 6. The method recited in claim 1, wherein the first and at least second stress layers are silicon-rich nitride layers and are formed by plasma enhanced chemical vapor deposition by flowing SiH4 at a rate ranging from about 15 sccm to about 200 sccm and flowing N2 at a rate ranging from about 5000 sccm to about 15000 sccm, flowing NH3 at a rate ranging from about 50 sccm to about 150 sccm, and at a pressure ranging from about 7 torr to about 50 torr, a temperature ranging from about 350° C. to about 450° C. and at a power ranging from about 10 watts to about 200 watts. 7. The method recited in claim 6, wherein annealing includes annealing with ultra violet light. 8. The method recited in claim 7, wherein the annealing includes conducting a thermal anneal, a laser anneal or a combination thereof subsequent to annealing with the ultra violet light. 9. The method recited in claim 1 wherein forming the laminated stress layer includes forming at least a third stress layer over the second stress layer and wherein a thickness of each of the at least first, second, and third stress layers is at least about 100 angstroms. 10. A method of manufacturing a semiconductor device, comprising: forming gate structures over a semiconductor substrate, including forming gate electrodes and forming spacers adjacent the gate electrodes; forming source/drains adjacent the gate structures; forming a laminated silicon nitride stress layer over the gate electrodes and the source/drains, including: depositing a first silicon nitride stress layer over the gate electrodes and the semiconductor substrate; pausing the deposition process a first time; and depositing at least a second silicon nitride stress layer over the first silicon nitride stress layer subsequent to pausing; and annealing the laminated silicon nitride stress layer at a temperature ranging from about 900° C. to about 1300° C. with a thermal anneal, a laser anneal, or a combination thereof. 11. The method recited in claim 10, further including pausing the deposition process a second time subsequent to depositing the second silicon nitride stress layer and depositing a third silicon nitride stress layer over the second silicon nitride stress layer prior to annealing. 12. The method recited in claim 10, wherein a height to gap ratio between electrodes ranges from about 0.9 to about 1.5. 13. The method recited in claim 10, wherein the first and second silicon nitride stress layers are formed by chemical vapor deposition by flowing SiH4 at a rate ranging from about 50 sccm to about 700 sccm and flowing N2 or NH3 at a rate ranging from about 500 sccm to about 6000 sccm, at a pressure ranging from about 1 torr to about 50 torr and a temperature ranging from about 300° C. to about 500° C. 14. The method recited in claim 10, wherein pausing the deposition the first and second times includes pausing the deposition process for a period of time ranging from about 5 sec to about 5 minutes. 15. The method recited in claim 10, wherein the first and at least second silicon nitride stress layers are silicon-rich nitride layers and are formed by plasma enhanced chemical vapor deposition and by flowing SiH4 at a rate ranging from about 15 sccm to about 200 sccm and flowing N2 at a rate ranging from about 5000 sccm to about 15000 sccm, flowing NH3 at a rate ranging from about 50 sccm to about 150 sccm, and at a pressure ranging from about 7 torr to about 50 torr, a temperature ranging from about 350° C. to about 450° C. and at a power ranging from about 10 watts to about 200 watts. 16. The method recited in claim 15, wherein annealing includes annealing with ultra violet (UV) light and annealing with the thermal anneal, a laser anneal, or a combination thereof subsequent to annealing with the UV light. 17. The method recited in claim 10 wherein the semiconductor device is an integrated circuit and annealing activates dopants located within the source/drains and the method further includes removing the laminated silicon stress layer and forming dielectric layers over the gate electrodes and forming interconnects within and over the dielectric layers to interconnect the gate electrodes. 18. A semiconductor device comprising: transistors, including: gate electrodes located over a semiconductor substrate; spacers located adjacent the gate electrodes; source/drains located adjacent the gate electrodes, wherein an intrinsic stress is added to the device by placing a laminated stress layer over the gate electrodes and annealing the laminated stress layer, wherein the laminated layer has a tensile stress ranging from about 1300 MPa to about 1700 MPa; and dielectric layers located over and within the transistors; and interconnects formed within the dielectric layers and configured to connect the transistors to other components. 19. The semiconductor device of claim 18 further including a laminated silicon nitride stress layer located over the gate electrodes and the semiconductor substrate, including at least a first silicon nitride stress layer located over the gate electrodes and the semiconductor substrate and a second silicon nitride stress layer located over the first silicon nitride stress layer. 20. The semiconductor device of claim 18 wherein a height to gap ratio between electrodes ranges from about 0.9 to about 1.5.	<SOH> BACKGROUND <EOH>In the continuing effort to improve performance of transistors and integrated circuits (ICs) in which they are used, semiconductor device designers strive to increase the drive current of the devices to increase switching speeds and overall performance. One aspect of this effort includes incorporating stress into the channel region of the device. However, as overall device size has decreased, problems associated with the manufacturing processes used to accomplish increased drive current have arisen. For example, in typical processes, a relatively thick (800 angstroms to 1000 angstroms) stress inducing layer is deposited over the gate electrode structures. A thick layer is used because more stress can be incorporated into the channel by utilizing a thick layer of material, which allows for a greater increase in drive current. However, when these thick layers are annealed, they can often provide a torque stress on the gate electrode, thereby causing a portion of the gate electrode to crack and break off. This, of course, is unacceptable as it increases defectivities across a semiconductor wafer and consequently decreases yields. Accordingly, what is needed is a method for increasing drive current by stress induction while minimizing damage to the gate electrodes.	<SOH> SUMMARY <EOH>To address the deficiencies as discussed above, the invention, in one embodiment, provides a method of manufacturing a semiconductor device. This particular embodiment comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. This embodiment further includes annealing the laminated stress layer at a temperature of about 900° C. or greater. In another embodiment, there is provided a method of manufacturing a semiconductor device. This embodiment comprises forming gate structures, including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated silicon nitride stress layer is formed over the gate structures and the source/drains. Its formation includes depositing a first silicon nitride stress layer over the gate electrodes and the semiconductor substrate, pausing the deposition process for a first time, and depositing at least a second silicon nitride stress layer over the first silicon nitride stress layer subsequent to pausing. The laminated silicon nitride stress layer is also annealed at a temperature ranging from about 900° C. to about 1300° C. with a thermal anneal, a laser anneal, or a combination thereof. In yet another embodiment, there is provided a semiconductor device. In this embodiment, the device comprises transistors that include gate electrodes located over a semiconductor substrate, spacers located adjacent the gate electrodes, and source/drains located adjacent the gate electrodes. An intrinsic stress is added to the device by placing a laminated stress layer over the gate electrodes and annealing the laminated stress layer, wherein the laminated layer has a tensile stress ranging from about 1300 MPa to about 1700 MPa. Dielectric layers are located over the transistors, and interconnects are formed within and over the dielectric layers and configured to connect the transistors to other components.	TECHNICAL FIELD The invention and the embodiments discussed herein are directed in general to a semiconductor device, and more specifically to a semiconductor device manufactured using a laminated stress layer. BACKGROUND In the continuing effort to improve performance of transistors and integrated circuits (ICs) in which they are used, semiconductor device designers strive to increase the drive current of the devices to increase switching speeds and overall performance. One aspect of this effort includes incorporating stress into the channel region of the device. However, as overall device size has decreased, problems associated with the manufacturing processes used to accomplish increased drive current have arisen. For example, in typical processes, a relatively thick (800 angstroms to 1000 angstroms) stress inducing layer is deposited over the gate electrode structures. A thick layer is used because more stress can be incorporated into the channel by utilizing a thick layer of material, which allows for a greater increase in drive current. However, when these thick layers are annealed, they can often provide a torque stress on the gate electrode, thereby causing a portion of the gate electrode to crack and break off. This, of course, is unacceptable as it increases defectivities across a semiconductor wafer and consequently decreases yields. Accordingly, what is needed is a method for increasing drive current by stress induction while minimizing damage to the gate electrodes. SUMMARY To address the deficiencies as discussed above, the invention, in one embodiment, provides a method of manufacturing a semiconductor device. This particular embodiment comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. This embodiment further includes annealing the laminated stress layer at a temperature of about 900° C. or greater. In another embodiment, there is provided a method of manufacturing a semiconductor device. This embodiment comprises forming gate structures, including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated silicon nitride stress layer is formed over the gate structures and the source/drains. Its formation includes depositing a first silicon nitride stress layer over the gate electrodes and the semiconductor substrate, pausing the deposition process for a first time, and depositing at least a second silicon nitride stress layer over the first silicon nitride stress layer subsequent to pausing. The laminated silicon nitride stress layer is also annealed at a temperature ranging from about 900° C. to about 1300° C. with a thermal anneal, a laser anneal, or a combination thereof. In yet another embodiment, there is provided a semiconductor device. In this embodiment, the device comprises transistors that include gate electrodes located over a semiconductor substrate, spacers located adjacent the gate electrodes, and source/drains located adjacent the gate electrodes. An intrinsic stress is added to the device by placing a laminated stress layer over the gate electrodes and annealing the laminated stress layer, wherein the laminated layer has a tensile stress ranging from about 1300 MPa to about 1700 MPa. Dielectric layers are located over the transistors, and interconnects are formed within and over the dielectric layers and configured to connect the transistors to other components. BRIEF DESCRIPTION OF THE DRAWINGS Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGS. 1-4 illustrate a semiconductor device and the formation of a laminated stress layer over gate structures; FIG. 5 illustrates an annealing step conducted on the device of FIG. 4; and FIG. 6 illustrates the semiconductor device of FIG. 5 incorporated into an integrated circuit (IC). DETAILED DESCRIPTION The invention recognizes the benefits associated with laminating a stress layer and annealing that layer to incorporate stress into a channel region located under the gate electrodes of semiconductor substrate. The embodiments discussed herein not only achieve more stress than conventional processes, but they also provide the added stress with an overall thinner layer and without creating undue torque on the gate electrodes. As such, this reduces damage to the gate electrodes as compared to conventional processes. Further, the thinner laminated layers are more easily deposited between gate structures that are spaced closely together. FIG. 1 illustrates a semiconductor device 100 as provided by the embodiments discussed herein. Reference is made throughout this discussion to the structural elements of FIG. 1. The device 100 may be a MOS device, such as an nMOS or a pMOS transistor, or it may have both types of devices configured as a CMOS device. The embodiments described herein are not limited to only nMOS or pMOS devices, but are applicable to any sub-micron device to incorporate stress into the substrate of any sub-micron active device. The device 100 includes a substrate 110, which may be any layer located over a silicon wafer, such as an epitaxial layer or may be the silicon wafer itself. Isolation structures 120 are located in the substrate 110. Gate structures 130 include a gate electrode 140 and a gate dielectric 150 that isolates the gate structure 130 from wells 155 and 158, respectively. Conventional processes and materials may be used to form these structures. While the length and width of the gate electrodes 140 in the invention may vary, the embodiments discussed herein are particularly useful in those instances where the gate electrodes 140 present a narrow profile. With overall device sizes shrinking, gate structures 130 have become thinner than in previous generations of semiconductor devices. For example, the gate structures 130, which include the spacers 160, may have a height to gap (between gate structures) ratio that ranges from about 0.9 to about 1.5. The height will be approximately the height of gate electrode 140, and the gap between the spacers 160 will depend on spacer width and other design parameters. The higher the ratio number is the greater the problem associated with stress related torque. For reasons discussed more fully below, this narrower profile makes the gate electrodes 140 more susceptible to damage during fabrication processes that are used to incorporate stress into the device 100. Sidewall spacers 160, which may also be conventional, are formed on the sidewalls of the gate structures 130. The device further includes source/drains 170, which may include source/drain extension regions 180. The source/drains 170 and extensions 180 may be formed using conventional dopants and implantation processes. A channel 190, having a stress as provided herein, is located between the source/drains 170. Due to the advantages provided by the embodiments herein, the amount of stress that is incorporated into the channel region 190 is greater for the same device size than the stress achievable using conventional processes and with at least the reduction of stress related torque on the gate. FIG. 2 illustrates the device 100 after the deposition of a first stress layer 210. As used herein a stress layer is one of a multiple number of layers that form a laminated layer (FIG. 4) of material that is used to incorporate stress into the substrate 110, including the channel region 190, upon an annealing process, which, in certain embodiments, can include a UV cure process. The stress layer 210 is the first of several layers that are formed over the gate structures 130 and the adjacent source/drains 170. In one embodiment, the stress layer 210 may be silicon nitride formed by chemical vapor deposition (CVD). It should be understood that the deposition conditions may vary depending on the type of deposition tool being used. However, in one embodiment, SiH4 is flowed at a rate ranging from about 50 sccm to about 700 sccm and either N2 or NH3 is flowed at a rate ranging from about 500 sccm to about 6000 sccm. These gases may be flowed with an inert gas, such as argon or helium at a rate of about 15 liters/sec. The deposition pressure may range from about 1 torr to about 50 torr, and the temperature may range from about 300° C. to about 500° C. Additionally, the lamination or deposition time for the stress layer 210 may range from about 1 second to about 20 seconds, depending on the targeted thickness. In the illustrated embodiment, the dopants in the source/drains 170 and extensions 180 have not been activated, but after the formation of the laminated stress layer, the anneal used to incorporated stress into the channel 190, in one embodiment, can also be used to activate the dopants. The thickness of the stress layer 210 may vary and will depend on the total thickness of the laminated layer and the number of layers comprising the laminated layer. For example, if the total thickness of the laminated layer is to be 300 angstroms and contain three layers, then the thickness of the stress layer 210 may be 100 angstroms. Alternatively, if the total thickness of the laminated layer is to be 500 angstroms and contain three layers, the thicknesses of each of the layers, including stress layer 210 can be manipulated to achieve the targeted thickness. Theses are but two examples that might be applicable, and any number of layers may be used. In another embodiment, the stress layer 210 may be a silicon-rich nitride layer which has more silicon than found in a typical silicon nitride. It should be understood that the deposition conditions may vary depending on the type of deposition tool being used. However, in one embodiment, the silicon-rich nitride stress layer may be formed by a plasma enhanced chemical vapor deposition (PECVD). In this embodiment, SiH4 is flowed at a rate ranging from about 15 sccm to about 200 sccm, N2 is flowed at a rate ranging from about 5000 sccm to about 15000 sccm, and NH3 is flowed at a rate ranging from about 50 sccm to about 150 sccm. The pressure may range from about 7 torr to about 50 torr, and the deposition temperature may range from about 350° C. to about 450° C. The radio frequency (RF) power, which may be a single or dual RF power, may range from about 10 watts to about 200 watts. The lamination or deposition time may also vary. For example, it may range from about 1 second to 20 seconds. Following the deposition of the first stress layer 210, the deposition process is paused such that no significant material is deposited to add to the targeted thickness. In most embodiments, the pause will include discontinuing the deposition process (both gas flows and power) and evacuating the deposition chamber before resuming the deposition process. The pausing and resumption of the deposition process is referred to herein as cycling. In such embodiments, an interface between individual layers most likely will form. In other embodiments, the gas flow rates and power, where applicable, may be substantially decreased such that little to no deposition occurs, or in another embodiment, the gas flows and power may be discontinued altogether before deposition is resumed without chamber evacuation. Without being bound to any theory, it is believed that pausing the deposition process allows the excess surface energy to stabilize and allows the surface atoms and dangling bonds to achieve a relaxed or stable energy state. It is further believed that this relaxation creates stress at the surface of the layer 210. The amount of time that the deposition process is paused may vary. For example, the deposition may be paused for a period ranging from about 5 seconds to about 5 minutes before the deposition process resumes. Further, the amount of pause time may also be tool dependent. For example, the deposition of one stress layer may occur in one chamber, while the deposition of a subsequent stress layer occurs in a separate chamber. Thus, the pause time would include the time of moving the device 100 from one chamber to the other. FIG. 3 illustrates the device 100 after formation of a second stress layer 310 over the first stress layer 210. The second stress layer 310 may also be a silicon nitride or a silicon-rich nitride layer, as discussed above. Moreover, it need not be the same material as the first stress layer 210. For example, the first stress layer 210 may be silicon nitride while the second stress layer 310 may be a silicon-rich nitride or vice-versa. In one embodiment, the second stress layer 310 may be located over but directly on the first stress layer 210, or in an alternative embodiment, there could be an intervening layer located between the first and second stress layers 210 and 310. The same processes used to deposit the stress layer 210 may also be used to form the second stress layer 310, depending on whether the stress layer 310 is silicon nitride or silicon-rich nitride. At this point in the fabrication process, no further stress layers may be required, however, in those embodiments where additional stress layers are required, the deposition process is paused, in the manner discussed above, and resumed to form the next stress layer. FIG. 4 illustrates the device 100 after formation of a third stress layer 410 over the second stress layer 310 to form a laminated stress layer 420. A laminated stress layer 420 is one that has multiple layers 210, 310, and 410 and has an interface between the layers 210, 310, and 410. The interface, which is shown as the solid lines between stress layers 210, 310, and 410, may be attributable to a difference in material or a discontinuity in stress or density between the various layers 210, 310, and 410. The third stress layer 410 may also be a silicon nitride or a silicon-rich nitride layer, as discussed above. Moreover, it need not be the same material as the second stress layer 310. For example, the third stress layer 410 may be silicon nitride while the second stress layer 310 may be a silicon-rich nitride or vice versa. In one embodiment, the third stress layer 410 may be located over but directly on the second stress layer 310, or there could be an intervening layer located between the second and third stress layers 310 and 410. The same above-discussed processes as used to form the first and second stress layers 210, 310 may also be used to form the third stress layer 410. In the illustrated embodiment of FIG. 4, the formation of the third stress layer 410 completes the laminated stress layer 420. As mentioned above, the total thickness of the laminated layer 420 will depend on the combined thicknesses of the individual stress layers 210, 310 and 410 and the number of individual layers present. For example, in one embodiment, the laminated layer's 420 thickness may range from 300 angstroms to 600 angstroms and may comprise any number of individual stress layers whose combined thickness equals the targeted thickness of the laminated layer 420. In such embodiments, the deposition process is cycled the appropriate number of times to achieve the desired number of stress layers within the laminated layer 420. Moreover, the amount of stress that can be incorporated into the channel 190 depends on the number of stress layers that comprise the laminated layer 420; that is, the stress of the individual stress layer 210, 310, and 410 is accumulative. Given this benefit, the amount of stress incorporated into the channel 190 can be easily controlled, thereby allowing for stress optimization of the device 100. FIG. 5 illustrates the device 100 of FIG. 4 being subjected to an anneal process 510 that incorporates a stress 505, such as a tensile stress, into the device 100. As such, an intrinsic stress is added to the device 100 by annealing the laminated layer 420, wherein the laminated layer 420 has a tensile stress ranging from about 1300 MPa to about 1700 MPa. In one embodiment, a thermal anneal is conducted at a temperature that ranges from about 900° C. to about 1050° C. In another embodiment, the thermal anneal is followed by a laser anneal that is conducted at temperatures ranging from about 1200° C. to about 1300° C. In yet another embodiment, the thermal anneal is conducted with the laser anneal at the previously stated temperatures. The thermal or laser anneals, or combinations thereof, are particularly useful in those embodiments where the stress layers 210, 310, and 410 are SiN. In embodiments wherein at least one of the stress layers 210, 310, and 410 is a silicon-rich nitride layer, the anneals, as just described above, may be preceded by a UV cure anneal. However, in an alternative embodiment, the UV cure anneal may be conducted subsequent to the thermal or laser anneals. The UV cure is beneficial in that it enhances the stress of the silicon-rich nitride layers; that is, it was unexpectedly found that more stress can be incorporated using the UV cure than could be incorporated absent the UV cure. For example, the amount of nitride film stress prior to the UV cure ranges from about 400 MPa to about 600 MPa whereas the stress following the UV cure ranges from about 1300 MPa to about 1700 MPa. It should be understood that the above annealing processes may be used in combination with each other. Following the anneal or UV cure processes as discussed above, the laminated stress layer 420, in one embodiment, may be re moved with a conventional hot phosphoric acid process. Alternatively, the laminated stress layer 420 may be left in place. FIG. 6 illustrates the device 100 configured as or incorporated into an integrated circuit (IC) 600. The IC 600 includes device 100 manufactured in a manner as discussed above and configured as complementary transistors 605 and 610. Dielectric layers 615, which may be formed using conventional processes and materials, are located over the transistors 605 and 610 and interconnects 620, which may be conventional interconnects, such as damascene or dual damascene both of which are illustrated, are formed over and within the dielectric layers 615. The interconnects 620 connect other circuit components in the IC 600. Those who are skilled in the art would understand how to incorporate the device 100 into the IC 600. Those skilled in the art will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope the disclosure set forth herein.	H	67H01	185H01L	21	44
11894917	US20090050903A1-20090226	Selective wet etching of gold-tin based solder	ACCEPTED	20090211	20090226	[]	H01L3300	["H01L3300", "H01L2144"]	8617997	20070821	20131231	438	689000	97385.0	JONES	ERIC	[{"inventor_name_last": "Chitnis", "inventor_name_first": "Ashay", "inventor_city": "Goleta", "inventor_state": "CA", "inventor_country": "US"}]	The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.	1. A method for fabricating an electronic device using selective wet etching, the method comprising: providing at least one wafer having at least one first surface; depositing at least one first layer comprising solder material adjacent to the at least one first surface, wherein the solder material comprises Au and Sn; depositing at least one second layer comprising etch mask material adjacent to the at least one first surface; introducing at least one liquid etching composition to the at least one first layer comprising solder material; and etching the at least one layer comprising solder material for a period of time sufficient to selectively etch at least one portion of the at least one solder layer. 2. The method of claim 1, further comprising: depositing at least one additional layer of material adjacent to the least one first surface; and etching the at least one additional layer for a period of time sufficient to selectively etch at least one portion of the at least one additional layer. 3. The method of claim 1, wherein the at least one first layer comprises an AuSn preform. 4. The method of claim 3, further comprising reflow soldering the preform. 5. The method of claim 1, wherein the at least one second layer comprises at least one of photo resist and GaN. 6. The method of claim 2, wherein the at least one additional layer comprises at least one of Ti, Pt, Au, Si, Ti, Ni, and Pt. 7. The method of claim 2, wherein the at least one additional layer comprises SiO2. 8. The method of claim 1, wherein the liquid etching composition comprises at least one of HF, HCl, HNO3 and aqua-regia. 9. The method of claim 8, wherein selective wet etching is achieved using a wet etch process comprising: introducing the at least one first layer to at least one composition comprising at least one of HF, HCl and HNO3; and introducing the at least one first layer to at least one composition comprising aqua-regia. 10. The method of claim 9, wherein introduction of the at least one composition comprising at least one of HF, HC, and HNO3 alternates with the introduction of the at least one composition comprising aqua-regia. 11. A patterned layer fabricated according to the method of claim 1. 12. A device comprising the layer of claim 11. 13. A device fabricated by the method of claim 1. 14. The device of claim 13, wherein the device is at least one of a flip chip device and a light emitting device. 15. The device of claim 14, wherein the device is a light emitting diode. 16. A method for selective wet etching at least one blanket layer comprising AuSn solder material, the method comprising introducing the at least one blanket layer comprising AuSn solder material to at least one etch composition comprising aqua-regia. 17. The method of claim 16, further comprising introducing the at least one layer comprising AuSn solder material to at least one composition comprising at least one of HF, HCl and HNO3. 18. The method of claim 17, wherein introduction of the at least one composition comprising at least one of HF, HC, and HNO3 alternates with the introduction of the at least one composition comprising aqua-regia. 19. A patterned layer fabricated according to the method of claim 16. 20. A device comprising the layer of claim 19.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to light emitting devices and methods of fabricating light emitting devices. 2. Description of Related Art Light emitting diodes and laser diodes are well known solid state electronic devices capable of generating light upon application of a sufficient voltage. Light emitting diodes and laser diodes may be generally referred to as light emitting devices (LEDs). Light emitting devices typically include a p-n junction formed in an epitaxial (epi) layer such as gallium nitride (GaN). The epi layer is usually grown on a substrate such as sapphire (Al 2 O 3 ), silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs). The wavelength distribution of the light generated by the LED depends on the material from which the p-n junction is fabricated and the structure of the thin epitaxial layers that include the active region of the device. Commercial high-efficiency LEDs are typically fabricated from two classes of III-V semiconductor materials. Group-III nitride (III-N) based materials are used for the ultraviolet to blue-green color range, and Group-III arsenide-phosphide (III-AsP) for yellow to near-infrared. There has been a great deal of recent interest in LEDs formed of Group-III nitride based material systems because of their unique combination of material characteristics, including high breakdown fields, wide bandgaps (3.36 eV for GaN at room temperature), large conduction band offset, and high saturated electron drift velocity. The doped and active layers in such devices are typically formed on a substrate which can be made from a variety of different materials such as silicon (Si), silicon carbide (SiC), and sapphire (Al 2 O 3 ). SiC wafers are often preferred for such heterostructures because they have a much closer crystal lattice match to Group-III nitrides, resulting in Group-III nitride films of higher quality. SiC also has a very high thermal conductivity, such that the total output power of Group-III nitride devices on SiC is not limited by the thermal resistance of the wafer, as is the case for many devices formed on sapphire or Si. The availability of semi-insulating SiC wafers also provides the capacity for device isolation and reduced parasitic capacitance, which makes commercial devices possible. During fabrication of semiconductor devices or circuits such as chips and multichip modules (MCM), a substrate (substrate wafer, growth wafer) provides the base or support for subsequent processing operations in which additional layers, components, or other materials are applied (e.g. epitaxial materials or layers, printed circuit boards, and disk platters). Patterning is a fabrication process in which a specific design can be introduced into a layer or surface during semiconductor fabrication. Patterning can be achieved in a number of ways, such as selectively depositing or selectively removing a material. Wet etching (chemical etching, chemical milling) is a patterning process used in semiconductor fabrication that removes a material by relying on chemical reactions in the liquid phase. The process typically uses acids, bases or other chemicals to dissolve away unwanted materials. Based on the nature, etching is broadly classified into isotropic and anisotropic. Isotropic etching is same in all directions while anistropic etching is direction sensitive. Material to be etched and type of the etchant determines the nature of the etch i.e. isotropic or anisotropic. For example, silicon is etched anisotropically in potassium hydroxide (KOH) while most of the commonly used metals (e.g. Au, Ag, Ni, Sn) and dielectrics (e.g. SiO 2 , SiN) in semiconductor technology utilize isotropic etchants. Anisotropic etch provides better control over the patterns or shapes to be produced while isotropic etch is employed in blanket etching or with combination of different materials for selective etching (patterning). Selective wet etch processes rely on the different etch rates of an etchant for different materials. In a typical selective wet etch process, one material is etched rapidly while another is etched very slowly or not etched at all. An aqueous HF solution, for example, can etch SiO 2 very rapidly while not etching silicon. For any particular etchant, the etch rate for the film being etched should be higher than the etching rates for both the mask and/or the substrate. Due to resolution limitations inherent in wet etching processing, the technique is generally used to pattern coarse features such as bond pads or large vias where, for example, an aspect ratio of 1 to 5 can be achieved reliably. However, despite such limitations, wet etch processing has found widespread use because it provides many advantages including low cost, high reliability, high throughput, and excellent selectivity with respect to both mask and substrate materials. A typical wet etch process involves coating the target or etch layer on the semiconductor wafer with a etch mask. One of the most commonly used etch mask is photoresist. Standard Photolithography is performed in the photoresist to expose the regions of the target layer to be etched. Wafer is immersed in the etchant to etch the target layer. After etching, the mask layer, in this case photoresist is usually then removed, leaving one or more patterned target layers which may require further processing in order to cure, clean, or remove residual solvent. Most materials are patterned in this manner, including silicon dioxide (SiO 2 ), Au and Sn. Modern device architectures can require patterning of a composite gold-tin (AuSn) solder material during fabrication. Individually, gold (Au) or tin (Sn) metal films can be wet etched quite readily after deposition and commercial etches suitable for such processes are available and well known. The chemistries of the two metals, however, are quite different, such that no single chemical will etch both metals together. Therefore, patterning of composite AuSn solder material during device fabrication is typically achieved during deposition by using a selective area deposition technique, rather than by post-deposition selective etching of a blanket AuSn layer. Selective deposition techniques typically used to pattern AuSn solder materials can include screen-printing through a patterned foil, electro-plating or vacuum deposition using a patternable sacrificial layer such as photo-resist, and physical cutting of free-standing thick films to create preforms or other materials molded into predetermined shapes, volumes, or dimensions, including without limitation a solder preform. These technologies, however, suffer from certain disadvantages. Due to incorporation of flux in the solder paste, screen-printing of solder paste is not a clean process. The paste typically undergoes reflow to drive off the flux, which can lead to contamination and leave voids in the material. Minimum thickness and dimension requirements are therefore generally large for layers formed in this manner, typically in the range of 20-50 microns. Preforms can be used for selective solder bumping. However, the technology is thickness and size-limited, and also costly due to the need to physically place preform on a wafer. In practice, therefore, the use of selective area deposition restricts the range of device architectures that are possible for AuSn solder due to the inherent limitations of available deposition techniques. Additionally, in some cases it is simply not desirable to pattern the AuSn at the time it is deposited. A uniform bond interface is simpler and preferred over a patterned bond, for example, when AuSn is used to wafer-bond two substrates.	<SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides improved methods for fabricating devices, particularly methods for patterning one or more materials in light emitting devices. These methods use one or more standard available chemistries to wet etch AuSn solder material, thereby circumventing the need for, and limitations of, selective AuSn deposition processes. Briefly, and in general terms, the present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and to devices fabricated using such processes. The processes can be applied to a uniform (blanket) AuSn layer to generate submicron patterning of thin AuSn layers having a wide variety of features (e.g. shape, size, thickness, and pattern). The process can also be used in many different applications such as to etch metals under a solder layer (bump metallization). Furthermore, the processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes. In particular, the present invention utilizes a combination of wet chemistries to selectively etch an AuSn solder layer deposited on a substrate or other areas or layers of a semiconductor device, either before or after the layer is reflowed at the eutectic point. Multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization (e.g. Ti, Ni, Pt, Au). In one of several aspects, the invention relates to a method of fabricating a light emitting device (LED) that includes a selective wet etch process in which a layer of AuSn solder is patterned. In another aspect, additional device layers are selectively patterned at the same time as the solder layer. In yet another aspect, the solder medium is provided as a preform. In a further aspect, the solder medium is reflowed. In another aspect, the invention relates to a method of selectively wet etching an AuSn solder medium including treatment with aqua regia. In yet another aspect, the method includes treatment with aqua regia and other chemical etchants such as HF, HCl and HNO 3 and combinations thereof. In a further aspect, aqua regia and other etchant treatments can alternate. In another aspect, the invention relates to a patterned layer of AuSn solder fabricated by selective wet etching. In another aspect, the invention relates to a device containing such a layer, such as a light emitting device. In a further aspect, the light emitting device is a light emitting diode. In yet a further aspect, the device is a flip chip device. In another aspect, the invention relates to a method for selective wet etching at least one layer containing AuSn solder material. In yet another aspect, the method includes treatment with chemical etchants such as HF, HCl and HNO 3 and combinations thereof that can be used alternatively through the etch process. In a further aspect, the method includes treatments with chemical etchants such as HF, HCl and HNO 3 and combinations thereof that alternate with aqua regia treatments. In yet a further aspect, the invention relates to a patterned layer fabricated according to the method. In another aspect, the invention relates to a device containing such a patterned layer. These and other aspects and advantages of the invention will become apparent from the following detailed description and the accompanying drawings, which illustrate by way of example the features of the invention.	STATEMENT AS TO FEDERALLY SPONSORED RESEARCH This invention was made with Government support under Grant No. 70NANB4H3037 awarded by the Department of Commerce (DOC). The federal government may have certain rights in the invention. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to light emitting devices and methods of fabricating light emitting devices. 2. Description of Related Art Light emitting diodes and laser diodes are well known solid state electronic devices capable of generating light upon application of a sufficient voltage. Light emitting diodes and laser diodes may be generally referred to as light emitting devices (LEDs). Light emitting devices typically include a p-n junction formed in an epitaxial (epi) layer such as gallium nitride (GaN). The epi layer is usually grown on a substrate such as sapphire (Al2O3), silicon (Si), silicon carbide (SiC), or gallium arsenide (GaAs). The wavelength distribution of the light generated by the LED depends on the material from which the p-n junction is fabricated and the structure of the thin epitaxial layers that include the active region of the device. Commercial high-efficiency LEDs are typically fabricated from two classes of III-V semiconductor materials. Group-III nitride (III-N) based materials are used for the ultraviolet to blue-green color range, and Group-III arsenide-phosphide (III-AsP) for yellow to near-infrared. There has been a great deal of recent interest in LEDs formed of Group-III nitride based material systems because of their unique combination of material characteristics, including high breakdown fields, wide bandgaps (3.36 eV for GaN at room temperature), large conduction band offset, and high saturated electron drift velocity. The doped and active layers in such devices are typically formed on a substrate which can be made from a variety of different materials such as silicon (Si), silicon carbide (SiC), and sapphire (Al2O3). SiC wafers are often preferred for such heterostructures because they have a much closer crystal lattice match to Group-III nitrides, resulting in Group-III nitride films of higher quality. SiC also has a very high thermal conductivity, such that the total output power of Group-III nitride devices on SiC is not limited by the thermal resistance of the wafer, as is the case for many devices formed on sapphire or Si. The availability of semi-insulating SiC wafers also provides the capacity for device isolation and reduced parasitic capacitance, which makes commercial devices possible. During fabrication of semiconductor devices or circuits such as chips and multichip modules (MCM), a substrate (substrate wafer, growth wafer) provides the base or support for subsequent processing operations in which additional layers, components, or other materials are applied (e.g. epitaxial materials or layers, printed circuit boards, and disk platters). Patterning is a fabrication process in which a specific design can be introduced into a layer or surface during semiconductor fabrication. Patterning can be achieved in a number of ways, such as selectively depositing or selectively removing a material. Wet etching (chemical etching, chemical milling) is a patterning process used in semiconductor fabrication that removes a material by relying on chemical reactions in the liquid phase. The process typically uses acids, bases or other chemicals to dissolve away unwanted materials. Based on the nature, etching is broadly classified into isotropic and anisotropic. Isotropic etching is same in all directions while anistropic etching is direction sensitive. Material to be etched and type of the etchant determines the nature of the etch i.e. isotropic or anisotropic. For example, silicon is etched anisotropically in potassium hydroxide (KOH) while most of the commonly used metals (e.g. Au, Ag, Ni, Sn) and dielectrics (e.g. SiO2, SiN) in semiconductor technology utilize isotropic etchants. Anisotropic etch provides better control over the patterns or shapes to be produced while isotropic etch is employed in blanket etching or with combination of different materials for selective etching (patterning). Selective wet etch processes rely on the different etch rates of an etchant for different materials. In a typical selective wet etch process, one material is etched rapidly while another is etched very slowly or not etched at all. An aqueous HF solution, for example, can etch SiO2 very rapidly while not etching silicon. For any particular etchant, the etch rate for the film being etched should be higher than the etching rates for both the mask and/or the substrate. Due to resolution limitations inherent in wet etching processing, the technique is generally used to pattern coarse features such as bond pads or large vias where, for example, an aspect ratio of 1 to 5 can be achieved reliably. However, despite such limitations, wet etch processing has found widespread use because it provides many advantages including low cost, high reliability, high throughput, and excellent selectivity with respect to both mask and substrate materials. A typical wet etch process involves coating the target or etch layer on the semiconductor wafer with a etch mask. One of the most commonly used etch mask is photoresist. Standard Photolithography is performed in the photoresist to expose the regions of the target layer to be etched. Wafer is immersed in the etchant to etch the target layer. After etching, the mask layer, in this case photoresist is usually then removed, leaving one or more patterned target layers which may require further processing in order to cure, clean, or remove residual solvent. Most materials are patterned in this manner, including silicon dioxide (SiO2), Au and Sn. Modern device architectures can require patterning of a composite gold-tin (AuSn) solder material during fabrication. Individually, gold (Au) or tin (Sn) metal films can be wet etched quite readily after deposition and commercial etches suitable for such processes are available and well known. The chemistries of the two metals, however, are quite different, such that no single chemical will etch both metals together. Therefore, patterning of composite AuSn solder material during device fabrication is typically achieved during deposition by using a selective area deposition technique, rather than by post-deposition selective etching of a blanket AuSn layer. Selective deposition techniques typically used to pattern AuSn solder materials can include screen-printing through a patterned foil, electro-plating or vacuum deposition using a patternable sacrificial layer such as photo-resist, and physical cutting of free-standing thick films to create preforms or other materials molded into predetermined shapes, volumes, or dimensions, including without limitation a solder preform. These technologies, however, suffer from certain disadvantages. Due to incorporation of flux in the solder paste, screen-printing of solder paste is not a clean process. The paste typically undergoes reflow to drive off the flux, which can lead to contamination and leave voids in the material. Minimum thickness and dimension requirements are therefore generally large for layers formed in this manner, typically in the range of 20-50 microns. Preforms can be used for selective solder bumping. However, the technology is thickness and size-limited, and also costly due to the need to physically place preform on a wafer. In practice, therefore, the use of selective area deposition restricts the range of device architectures that are possible for AuSn solder due to the inherent limitations of available deposition techniques. Additionally, in some cases it is simply not desirable to pattern the AuSn at the time it is deposited. A uniform bond interface is simpler and preferred over a patterned bond, for example, when AuSn is used to wafer-bond two substrates. SUMMARY OF THE INVENTION The present invention provides improved methods for fabricating devices, particularly methods for patterning one or more materials in light emitting devices. These methods use one or more standard available chemistries to wet etch AuSn solder material, thereby circumventing the need for, and limitations of, selective AuSn deposition processes. Briefly, and in general terms, the present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and to devices fabricated using such processes. The processes can be applied to a uniform (blanket) AuSn layer to generate submicron patterning of thin AuSn layers having a wide variety of features (e.g. shape, size, thickness, and pattern). The process can also be used in many different applications such as to etch metals under a solder layer (bump metallization). Furthermore, the processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes. In particular, the present invention utilizes a combination of wet chemistries to selectively etch an AuSn solder layer deposited on a substrate or other areas or layers of a semiconductor device, either before or after the layer is reflowed at the eutectic point. Multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization (e.g. Ti, Ni, Pt, Au). In one of several aspects, the invention relates to a method of fabricating a light emitting device (LED) that includes a selective wet etch process in which a layer of AuSn solder is patterned. In another aspect, additional device layers are selectively patterned at the same time as the solder layer. In yet another aspect, the solder medium is provided as a preform. In a further aspect, the solder medium is reflowed. In another aspect, the invention relates to a method of selectively wet etching an AuSn solder medium including treatment with aqua regia. In yet another aspect, the method includes treatment with aqua regia and other chemical etchants such as HF, HCl and HNO3 and combinations thereof. In a further aspect, aqua regia and other etchant treatments can alternate. In another aspect, the invention relates to a patterned layer of AuSn solder fabricated by selective wet etching. In another aspect, the invention relates to a device containing such a layer, such as a light emitting device. In a further aspect, the light emitting device is a light emitting diode. In yet a further aspect, the device is a flip chip device. In another aspect, the invention relates to a method for selective wet etching at least one layer containing AuSn solder material. In yet another aspect, the method includes treatment with chemical etchants such as HF, HCl and HNO3 and combinations thereof that can be used alternatively through the etch process. In a further aspect, the method includes treatments with chemical etchants such as HF, HCl and HNO3 and combinations thereof that alternate with aqua regia treatments. In yet a further aspect, the invention relates to a patterned layer fabricated according to the method. In another aspect, the invention relates to a device containing such a patterned layer. These and other aspects and advantages of the invention will become apparent from the following detailed description and the accompanying drawings, which illustrate by way of example the features of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic plan view of sub-micron AuSn solder bumps fabricated using methods according to the present invention; FIG. 1B is a schematic plan view of an AuSn solder ring fabricated using methods according to the present invention; FIG. 1C is a schematic plan view of an octagon-shaped AuSn solder fabricated using methods according to the present invention; FIG. 1D is a schematic plan view of a cross-shaped AuSn solder preform. FIG. 2A is a schematic cross sectional view of one embodiment of the invention showing an LED device wafer having a preform containing AuSn solder medium and an adjacent layer of patterned photoresist; FIG. 2B is a plan view optical microscopy image of the embodiment shown in FIG. 2A showing alternating surfaces containing patterned photoresist and exposed AuSn; FIG. 2C is a schematic cross sectional view of the embodiment shown in FIG. 2A after a selective wet etch process according to the invention; FIG. 3A is a schematic cross sectional view of one embodiment of the invention showing an LED device wafer having a layer containing AuSn solder medium sandwiched between a metal stack and a layer of photoresist; and FIG. 3B is a schematic cross sectional view of the embodiment shown in FIG. 3A after a selective wet etch process according to the invention. DETAILED DESCRIPTION OF THE INVENTION The present invention provides improved methods for fabricating semiconductor devices, particularly methods for patterning one or more materials in light emitting devices. These methods use one or more standard available chemistries particularly adapted to wet etch AuSn solder material, thereby circumventing the need for, and limitations of, selective AuSn deposition processes. In particular, the present invention utilizes a combination of wet chemistries to selectively etch an AuSn solder layer, either before or after it is reflowed at the eutectic point. Suitable chemistries for use with the invention include without limitation aqua regia, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl) and combinations thereof. In addition to combining chemicals, the use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively. It is understood that the chemistries used and the amount of time that the AuSn solder is exposed to each of the alternating chemistries can vary depending on a number of factors. One of these factors is the composition of the AuSn solder, i.e. the percentage of Au verses the percentage of Sn, and this thickness of the AuSn. Another is the concentrations of the chemistries. Accordingly, it is understood that different embodiments of the method can be realized depending upon these and other factors. There are several important advantages provided by the present invention, including without limitation those described below: (a) the process can be applied to a uniform (blanket) AuSn layer, which is much easier to deposit on a wafer than a patterned AuSn layer; especially for films >5 um. (b) the process is simple, cost-effective, and compatible with standard cleanroom fabrication processes; (c) solder patterning can be done either before, or after, reflow or bonding of the AuSn layer; (d) there are no film thickness constraints for the process (i.e. dimensions are limited only by the inherent limitations of current lithography techniques); (e) allows dense, fine scale (e.g. submicron) patterning of thin AuSn layers; (f) allows patterning of complex shapes (e.g. rings, polygons) of widely varying sizes on single wafer, limited only by the lithography capabilities of the etch mask layer; (g) no equipment/tool contamination occurs during the process; (h) the same or similar chemicals can be used to etch materials to fabricate under bump metallization (e.g. Ti, Ni, Pt, Au); and (i) feature size (e.g. etch depth and etch profile) is limited only by the inherent limitations of lithography techniques and etch selectivity of the etch mask. The processes of the present invention can facilitate device fabrication in many applications requiring patterned solder or selective removal of solder, including without limitation flip chip packaging in some types of devices; wet etching of sputter deposited AuSn solder layers in dicing streets on devices, patterning of AuSn solder bond layers in chip scale packaging applications (e.g. in order to provide separate electrical contacts for IC-LED technology), and general electronic and optoelectronic packaging applications using solder bumps (e.g. AuSn ball grid arrays). A flip chip device is a device made using flip chip microelectronic assembly/packaging, including without limitation the direct electrical connection of face-down (“flipped”) electronic components onto substrates, circuit boards, carriers or the like by means of conductive bumps on the chip bond pads (e.g. Direct Chip Attach or DCA). Other features and advantages of the invention will be apparent from the following detailed description when taken together with the drawings, and from the claims. The following description presents preferred embodiments of the invention representing the best mode contemplated for practicing the invention. This description is not to be taken in a limiting sense but is made merely for the purpose of describing the general principles of the invention whose scope is defined by the appended claims. Before addressing details of embodiments described below, some terms are defined or clarified. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, “or” refers to an inclusive or and not to an exclusive or. For example, a condition A or B is satisfied by any one of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present). Also, use of the “a” or “an” are employed to describe elements and components of the invention. This is done merely for convenience and to give a general sense of the invention. This description should be read to include one or at least one and the singular also includes the plural unless it is obvious that it is meant otherwise. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, any definitions used refer to the particular embodiments described herein and are not to be taken as limiting; the invention includes equivalents for other undescribed embodiments. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are described below. In case of conflict, the present specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting. Attention is now directed to more specific details of embodiments that illustrate but not limit the invention. The present invention relates to wet etch processes which can be used to fabricate a patterned AuSn solder layer, layers patterned using such processes, and to devices having such patterned layers. The solder medium can be introduced to a device or substrate, prior to patterning, by deposition or as a preform or electroplating. In particular, the present invention utilizes a combination of wet chemistries to selectively etch an AuSn solder layer deposited on a device or substrate surface, either before or after the layer is reflowed at the eutectic point. The use of multiple selective wet etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization (e.g. Ti, Ni, Pt, Au, TiW). The processes of the present invention can be useful in fabricating semiconductor chips and devices. The solder medium can be deposited as a coating or blanket layer using any suitable deposition technique, including without limitation electroplating, vapor deposition, evaporation, sputtering, layering, sprinkling, beading, extruding, printing, patterning, spraying or via the application of a solid or semi-solid material such as a preform. As used herein, the term “layer” or “coating” is intended to mean a thickness, course, or fold laid or lying over or under another layer or support. A layer may be contiguous (e.g. blanket) or non-contiguous (e.g. patterned, beaded or sprinkled). The optimal thickness of the solder layer can vary depending upon the particular application. Preforms may be customized to the required shape and size using commercially available preform formats such as preform ribbon. Preforms may be subjected to a reflow process for surface-bonding prior to patterning. The present invention can be used to fabricate many different AuSn features in many different semiconductor devices. FIG. 1A-1D show schematic plan views of different exemplary features that can be fabricated utilizing methods according to the present invention. FIG. 1A shows sub-micron AuSn solder bumps (1) on a substrate (2) useful for devices including but not limited to photonic crystals, laser diodes, and acoustic devices. The bumps (1) can be etched from a blanket layer of AuSn deposited on the substrate (2) using the methods described above. Non-limiting examples of a substrate include a small, thin circular slice of a semiconducting material, such as pure silicon (Si) or silicon carbide (SiC) on which an integrated circuit or flip chip can be formed, and a device wafer. As used herein, a “chip” (die, integrated circuit or IC) is a single piece of semiconductor wafer containing an entire integrated circuit which has not yet been packaged. It is understood, that the substrate (2) can also include different epitaxial and metal layers to form different semiconductor devices, with the bumps capable of being formed on these different layers, or directly on the substrate (2). FIG. 1B is a schematic plan view of an AuSn solder ring (3) that can also be formed on the substrate (2) using methods according to the present invention. AuSn solder rings are particularly useful for devices such as a vertical-cavity surface-emitting laser (VCSEL). The present invention can also be used to more elaborate shapes from a blanket AuSn layer. FIG. 1C is a schematic plan an octagon-shaped AuSn feature (4) and FIG. 1D is a schematic plan view of a cross-shaped AuSn solder feature (5). Materials adjacent to or below the AuSn solder may also be selectively etched using the processes of the present invention, including without limitation Ti, Ni, Pt, Au or combinations thereof. As used herein, the term “adjacent to” when referring to a layer or coating on a particular surface does not necessarily mean that the layer or coating is immediately next to the surface. There may or may not be another contiguous or non-contiguous layer, coating, or material present between the layer or coating described and the surface, and the surface itself can be another layer or coating. Each etch bath can be either a single chemistry or a combination of two or more chemistries, in concentrated or dilute form, as required. Preferably, at least one chemistry is aqua regia. Aqua regia is generally known in the art and is particularly applicable to dissolving gold and platinum during etching. Other suitable chemistries for use in the present invention include without limitation HF, HCl, HNO3, and combinations thereof. The use of multiple etching steps that alternate between different mixes of such chemicals can enable the etch process to proceed more effectively. The number of steps and the particular chemistries used are dependent upon the target materials and the type of structure required for a particular application (e.g. bond pads). Photoresist patterns can be defined using standard photolithographic techniques, and any suitable etch-resistant masking material can be used as an etch mask for patterning, including with out limitation metals such as silicon nitride (SiN), photoresist, benzocyclobutene (BCB), polyamides, and semiconductor materials such as GaN. EXAMPLE 1 The following describes one embodiment of a method according to the present invention used to etch a structure having an AuSn feature or layer. The structure being etched comprises an AuSn layer that can be formed from a preform that was reflowed onto a thermally oxidized Si carrier wafer having a Ti/Pt/Au blanket metallization. The AuSn layer can have many different thickness and the Si wafer can have many different diameters, with a suitable AuSn layer being 0.5 millimeters thick and the wafer having a 2 inch diameter. A resist mask layer is included on the AuSn layer with a suitable layer comprising commercially available photoresist 220-7 and being approximately 6 μm thick. A standard quartz plate lithography mask layer (i.e. 220-7 photoresist) followed by a 3 minute post-bake at 110° C. Two solutions were then used in an alternating fashion for wet etching, as indicated below: 1. HF/HCl (1:1)—1 min. 2. Aqua-regia—1 min. 3. HF/HCl (1:1)—0.5 min. 4. Aqua-regia—2 min. 5. HF/HCl (1:1)—0.5 min. 6. Aqua-regia—1.5-2 min. The mask layer can then be removed using known mask layer removal processes. FIGS. 2A-2C show a structure that can be etched using the embodiment described in Example 1. For simplicity and ease of interpretation, only a small number of representative patterned features are shown. FIG. 2A is a schematic cross sectional view of one embodiment of the invention showing an LED device wafer (10) having a preform containing AuSn solder medium (11) and an adjacent layer of patterned mask layer (13) that preferably comprises a photoresist. The device wafer (10) also comprises a silicon (Si) substrate (12), two SiO2 insulating layers (14a and 14b), and a Ti/Pt/Au metal stack layer (15). The total thickness of the preform, before and after reflow, was about 12μ (0.5 mil) and about 5-10μ (50-100 kÅ), respectively. As used herein, the term “wafer” is intended to mean a thin slice of semiconductor material used in manufacturing semiconductor devices and integrated circuits. As used herein, the term “device wafer” is intended to mean a wafer populated with multiple chips. A Si wafer supporting multiple LEDs, prior to singulation (i.e. LED wafer), is a non-limiting example of a device wafer. FIG. 2B is a plan view optical microscopy image of the embodiment shown in FIG. 2A showing a portion of the patterned top surface on a device wafer (10). The alternating sections containing patterned photoresist (13) coated on AuSn and exposed AuSn (11) surfaces are clearly delineated. FIG. 2C is a schematic cross sectional view of the embodiment shown in FIG. 2A after the selective wet etch process and subsequent removal of the patterned photoresist (13). There was no electrical continuity between the pads, indicating that the AuSn solder layer (11), as well as the Ti/Pt/Au stack layer (15) and uppermost SiO2 (14a) layer, were selectively etched. The AuSn solder layer (11) was preferably etched using the HF/HCl (1:1) and aqua-regia is alternating times as described above. These and other materials alone or in combination can be used to etch the Ti/Pt/Au stack layer (15) and uppermost SiO2 (14a) layer. EXAMPLE 2 Many different etching chemistries can be used according to the present invention and can be applied for different amounts of time. As another example, a metallized Si carrier wafer with a sputter AuSn layer that was not reflowed, was etched. Two different approaches were used for wet etching experiments: 1. HF/HCl (1:1)—1 min 2. Aqua-regia—1 min OR Aqua-regia—4 min. Both methods successfully etched the AuSn layer. The total etch time was reduced in comparison to Experiment 1, possibly due to the thinner AuSn layer used for this embodiment. The metal stack also appeared to be completely etched. The etch time is also further reduced when using HF/HCL and aqua regia in combination compared to an etch using aqua-regia alone. FIG. 3A is a schematic cross sectional view of one embodiment structure that can be etched using the method this method. An LED device wafer (30) is included containing a substrate 32 having a layer of AuSn solder medium (31) sandwiched between a metal stack (38) and a gold flash (37) overlaid with a layer of patterned photoresist (33). FIG. 3B is a schematic cross sectional view of the embodiment shown in FIG. 3A after a selective wet etch process according to the invention, showing selective and complete etching through the gold flash (37), AuSn solder layer (31), and metal stack (38). As used herein, the term “gold flash” is intended to mean an extremely thin layer of gold, with a thickness measured on the molecular level, which is either electroplated or chemically plated onto a surface. As discussed above additional chemistries can also be employed such as HF/HNO3. For example, one embodiment of a method according to the present invention using HF/HNO3 (1:1) in combination with other chemistries to etch AuSn is as follows: 1. HF/HNO3 (1:1) 2. Aqua-Regia 3. HF/HNO3 (1:1) 4. Aqua-Regia 5. HF/HCl (1:1) 6. Aqua-Regia The time used for each of these chemistries varies depending on the type of adjacent layers and the thickness/composition of the AuSn layer. The embodiments and examples set forth herein were presented to explain the nature of the present invention and its practical application, and thereby to enable those of ordinary skill in the art to make and use the invention. However, those of ordinary skill in the art will recognize that the foregoing description and examples have been presented for the purposes of illustration and example only. The description as set forth is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the teachings above without departing from the spirit and scope of the forthcoming claims. For example, while the use of GaN LED chips is described herein, the invention contemplated is not so limited. One skilled in the art will recognize that the invention may potentially be applied to a variety of bond medium materials in many different types of devices or applications, and that various fabrication technologies may be used.	H	67H01	185H01L	33	00
11704995	US20080169728A1-20080717	Piezoelectric thin film resonator, piezoelectric thin film resonator filter and manufacturing method thereof	ACCEPTED	20080701	20080717	[]	H01L4104	["H01L4104", "H01L4122"]	7745975	20070212	20100629	310	331000	72225.0	BUDD	MARK	[{"inventor_name_last": "Asai", "inventor_name_first": "Kengo", "inventor_city": "Hachioji", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Matsumoto", "inventor_name_first": "Hisanori", "inventor_city": "Kokubunji", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Isobe", "inventor_name_first": "Atsushi", "inventor_city": "Kodaira", "inventor_state": "", "inventor_country": "JP"}]	A piezoelectric thin film resonator includes: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, and which is formed on a substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, wherein the first metal electrode film is formed on the substrate and the second metal electrode film is formed on the first metal electrode film while sandwiching the piezoelectric thin film, and a protection film laminated on the second metal electrode film is provided so as to cover the second metal electrode film.	1. A piezoelectric thin film resonator comprising: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, the laminated structure being formed on a substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, wherein the first metal electrode film is formed on the substrate, and the second metal electrode film is formed on the first metal electrode film while sandwiching the piezoelectric thin film, and wherein a protection film laminated on the second metal electrode film is provided so as to cover the second metal electrode film. 2. The piezoelectric thin film resonator according to claim 1, wherein plane shapes of the piezoelectric thin film and the second metal electrode film are substantially the same, and wherein the protection film is formed on an upper surface of the second metal electrode film so as to cover the whole surface of an area where the laminated structure substantially functions as a resonator. 3. The piezoelectric thin film resonator according to claim 2, further comprising: an electrode pad connected with the second metal electrode film is provided, wherein the substantially whole upper surface of the second metal electrode film is covered with the protection film and the electrode pad. 4. The piezoelectric thin film resonator according to claim 1, wherein the second metal electrode film comes into contact with the protection film through an interface. 5. The piezoelectric thin film resonator according to claim 4, wherein the piezoelectric thin film resonator is a piezoelectric thin film bulk acoustic wave resonator, wherein the piezoelectric thin film resonator further comprises: a support film formed on the acoustic insulating layer, and wherein the laminated structure is provided on the support film. 6. The piezoelectric thin film resonator according to claim 4, wherein the piezoelectric thin film resonator is a thin film tuning-fork-shape distorting oscillator, wherein the piezoelectric thin film resonator further comprises: a support film formed on the acoustic insulating layer is provided, and wherein the laminated structure is provided on the support film. 7. The piezoelectric thin film resonator according to claim 4, wherein the acoustic insulating layer is formed on the substrate at a position corresponding to the laminated structure, and wherein the acoustic insulating layer is a Bragg reflection layer in which low acoustic impedance layers and high acoustic impedance layers are alternately laminated. 8. The piezoelectric thin film resonator according to claim 4, wherein the acoustic insulating layer is formed on the substrate at a position corresponding to the laminated structure, and wherein the acoustic insulating layer is a cavity formed in the substrate. 9. The piezoelectric thin film resonator according to claim 1, wherein the protection film contains silicon dioxide, and has a thickness of 50 nm to 600 nm. 10. The piezoelectric thin film resonator according to claim 1, wherein the protection film contains aluminum nitride, and has a thickness of 50 nm to 600 nm. 11. The piezoelectric thin film resonator according to claim 1, wherein the laminated structure is comprised of two laminated structures laminated above and below, and wherein the protection film is formed on an upper surface of the second metal electrode film in the upper laminated structure. 12. A manufacturing method of a piezoelectric thin film resonator, the piezoelectric thin film resonator comprising: a substrate which includes at least one plane; a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, wherein the laminated structure being formed on the substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, and the manufacturing method comprising the steps of: depositing a support film on the substrate; depositing the first metal electrode film on the support film; depositing the piezoelectric thin film on the first metal electrode film; depositing the second metal electrode film on the piezoelectric thin film; depositing a protection film on the second metal electrode film; etching the deposited protection film, second metal electrode film, and piezoelectric thin film so as to expose the first metal electrode film and areas for forming a pair of electrode pads that are connected with the respective metal electrode films; and etching the first metal electrode film and the pair of electrode pads in arbitrary shapes, wherein the support film, the first metal electrode film, the piezoelectric thin film, the second metal electrode film, and the protection film are sequentially deposited in vacuum. 13. The manufacturing method of a piezoelectric thin film resonator according to claim 12, further comprising the steps of: forming the acoustic insulating layer on the substrate; and depositing the support film on the substrate including the acoustic insulating layer. 14. The manufacturing method of a piezoelectric thin film resonator according to claim 12, further comprising the step of: forming a cavity as the acoustic insulating layer from a back surface of the substrate. 15. The manufacturing method of a piezoelectric thin film resonator according to claim 12, further comprising the steps of: providing a cavity on the substrate; depositing a sacrificial layer on the substrate in which the cavity is formed; making flat a surface of the sacrificial layer after filling only the cavity with the sacrificial layer; sequentially-depositing the support film, the first metal electrode film, the piezoelectric thin film, the second metal electrode film, and the protection film on the substrate which is filled with the sacrificial layer; etching the deposited protection film, second metal electrode film, and piezoelectric thin film in the same shape so as to expose the first metal electrode film; etching the first metal electrode film; and etching the sacrificial layer with which the cavity is filled and the protection film at the same time, wherein a material of the sacrificial layer and the protection film is silicon oxide or phosphoric-silicate glass. 16. A piezoelectric thin film bulk acoustic wave resonator filter comprising: a substrate; and a plurality of piezoelectric thin film bulk acoustic wave resonators provided on the substrate, wherein at least one piezoelectric thin film bulk acoustic wave resonator includes: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, the laminated structure being formed on the substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, wherein the first metal electrode film is formed on the substrate and the second metal electrode film is formed on the first metal electrode film while sandwiching the piezoelectric thin film, and wherein a protection film laminated on the second metal electrode film which is provided so as to cover the second metal electrode film. 17. The piezoelectric thin film bulk acoustic wave resonator filter according to claim 16, wherein the protection film contains silicon dioxide. 18. The piezoelectric thin film bulk acoustic wave resonator filter according to claim 16, wherein the protection film contains aluminum nitride. 19. The piezoelectric thin film bulk acoustic wave resonator filter according to claim 16, wherein the second metal electrode film comes into contact with the protection film through an interface. 20. The piezoelectric thin film bulk acoustic wave resonator filter according to claim 19, further comprising: a plurality of first piezoelectric thin film bulk acoustic wave resonators which are series-connected; and a plurality of second piezoelectric thin film bulk acoustic wave resonators which are parallel-connected, wherein at least one piezoelectric thin film bulk acoustic wave resonator includes a first electrode pad connected with the first metal electrode film and a second electrode pad connected with the second metal electrode film, and wherein the substantially whole upper surface of the second metal electrode film is covered with the protection film and the second electrode pad.	<SOH> BACKGROUND OF THE INVENTION <EOH>A piezoelectric thin film bulk acoustic wave resonator generally includes a piezoelectric thin film deposited by a thin film forming apparatus, and a resonator unit composed of a first metal electrode film and a second metal electrode film, which are located above and below while sandwiching at least a part of the piezoelectric thin film. The first metal electrode film functions as a lower electrode, and the second metal electrode film functions as an upper electrode. The piezoelectric thin film is polarized in the thickness direction. An alternating electric field generated by alternating voltage that is applied between the lower electrode and the upper electrode causes stretching of the piezoelectric thin film in the thickness direction, namely an acoustic wave by piezoelectric/anti-piezoelectric effects. There exist acoustic insulating layers above and below the resonator composed of the piezoelectric thin film, the lower electrode, and the upper electrode. The piezoelectric thin film bulk acoustic wave resonator suitable for a high frequency filter is classified based on methods by which a bulk acoustic wave is sealed inside the piezoelectric thin film, and FBAR (Film Bulk Acoustic wave Resonator) and SMR (Solidly Mounted Resonator) are well known. An interface between a solid body and gaseous matter (or, vacuum) functions as an effective acoustic insulating layer, and therefore areas above and below the resonator are in a gaseous state (or, vacuum state) in FBAR. An area above the upper electrode is in a gaseous state (or, vacuum state), and a Bragg reflector is mounted below the lower electrode in SMR. U.S. Pat. No. 6,496,085 B2 discloses the device configuration of SMR and a process flow thereof. Japanese Patent Application Laid-Open No. 2005-303573 proposes a resonator structure in which AlN is formed only on a lower electrode and no bump is formed on an upper electrode due to AlN high orientation. Further, US 2005/0248232 A1 describes an improvement of AlN orientation by sequential deposition of a lower electrode and a piezoelectric film, and an electromechanical coupling coefficient. The above US 2005/0248232 A1 describes that flatness and cleaning properties immediately after deposition are not maintained on a surface of the lower electrode due to adsorption of impurities in conventional piezoelectric film manufacturing process ([0008]). Further, Japanese Patent Application Laid-Open No. 2004-200843 discloses a manufacturing method which aims at reducing a cost in such a manner that a support film is made of AlN, and a sacrificial layer for forming an oscillation space, the support film, a lower electrode film, a piezoelectric thin film, and an upper electrode film are sequentially deposited in the same apparatus. Further, “Comparison of Micromachined FBAR Band Pass Filters with Different. Structural Geometry” (Park et al, 2003 IEEE MTT-S Digest, pp. 2005-2008) discloses the device configuration of FBAR and a process flow thereof. On the other hand, a thin film tuning-fork-shape distorting oscillator is composed of, as similar to the piezoelectric thin film bulk acoustic wave resonator, a piezoelectric thin film deposited by a thin film forming apparatus, and a first metal electrode film and a second metal electrode film which are located above and below while sandwiching a part of the piezoelectric thin film, and is a distorting oscillator in which the piezoelectric thin film is patterned in a tuning-fork shape. U.S. Pat. No. 7,083,740 B2 discloses the resonance device configuration of a thin film tuning-fork-shape distorting oscillator and a manufacturing method thereof.	<SOH> SUMMARY OF THE INVENTION <EOH>A piezoelectric thin film bulk acoustic wave resonator is characterized in that a Q-value is generally high. However, a trend of new systems requires a much higher Q-value. Similarly, a much higher Q-value as well as downsizing of the system, a high natural resonance frequency, a wide bandwidth, little fluctuation in electric characteristics with respect to process changes, and a low cost is required for a thin film tuning-fork-shape distorting oscillator. In order to produce a piezoelectric thin film bulk acoustic wave resonator filter using a piezoelectric thin film bulk acoustic wave resonator, it is necessary to electrically connect two or more piezoelectric thin film bulk acoustic wave resonators having different resonance frequencies with each other. For this purpose, a general manufacturing process is as follows. A lower electrode layer located below a piezoelectric thin film is formed in an arbitrary shape so as to be connected between plural resonators, and then a piezoelectric layer and an upper electrode layer are formed. The manufacturing process is disclosed in U.S. Pat. No. 6,496,085 B2, Japanese Patent Application Laid-Open No. 2005-303573 and “Comparison of Micromachined FBAR Band Pass Filters with Different Structural Geometry”. The manufacturing process disclosed in the “Comparison of Micromachined FBAR Band Pass Filters with Different Structural Geometry” will be described below as a conventional technique. First, a lower electrode is deposited so as to cover a silicon substrate, and is patterned in an arbitrary shape. Next, a piezoelectric thin film is deposited so as to cover a surface of the lower electrode pattern and a surface of the silicon substrate exposed by removing the lower electrode, and is patterned in an arbitrary shape. By patterning the piezoelectric thin film, a part of the lower electrode is exposed. Next, the lower electrode is deposited so as to cover a surface of the piezoelectric thin film and a surface of the silicon substrate exposed by removing the piezoelectric thin film, and is patterned in an arbitrary shape. Finally, by etching a part of a back surface of the silicon substrate, a cavity is formed immediately below a resonator unit. The piezoelectric thin film bulk acoustic wave resonator can be obtained by the above manufacturing method. In the element structure, each of the first metal electrode film, the piezoelectric thin film, and the second metal electrode film is exposed in the air for pattering in mid-course of manufacturing. Due to this, oxygen and nitrogen are mixed inside the piezoelectric thin film and the metal electrode film. Along with this, inner portions (bulk portions) of the respective piezoelectric film layer and the metal electrode film layer are different from epidermic portions thereof in material composition, and these layers come into contact with each other through an interface. There is concern that such changes of the materials in the epidermic portions of the piezoelectric film layer and the metal electrode film layer have an adverse effect on element characteristics of the piezoelectric thin film bulk acoustic wave resonator. On the other hand, since the first metal electrode film and the piezoelectric thin film are sequentially deposited in US 2005/0248232 A1 ([0034]), and the first metal electrode film, the piezoelectric thin film, and the second metal electrode film are sequentially deposited in Japanese Patent Application Laid-Open No. 2004-200843, it is conceivable that effects on element characteristics of the piezoelectric thin film bulk acoustic wave resonator are alleviated as compared to the former manufacturing method. However, even in the case of the latter manufacturing methods, the piezoelectric thin film and the second metal electrode film (US 2005/0248232 A1), or the second metal electrode film (Japanese Patent Application Laid-Open No. 2004-200843) is exposed in the air in mid-course of manufacturing. Along with this, concern still remains in that mixing of oxygen and nitrogen inside the piezoelectric thin film and the second metal electrode film has an adverse effect on element characteristics of the piezoelectric thin film bulk acoustic wave resonator. Even for a thin film tuning-fork-shape distorting oscillator, the conventional technique disclosed in U.S. Pat. No. 7,083,740 B2 involves a problem similar to the piezoelectric thin film bulk acoustic wave resonator. The issue of the present invention is to address conventional problems according to the above-described resonator structure forming technique, and an object thereof is to provide a piezoelectric thin film bulk acoustic wave resonator or a thin film tuning-fork-shape distorting oscillator which can realize a good characteristic of film quality, and a manufacturing method thereof. A representative example of the present invention is as follows. That is, a piezoelectric thin film resonator comprising: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, wherein the laminated structure being formed on a substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, wherein the first metal electrode film is formed on the substrate, and the second metal electrode film is formed on the first metal electrode film while sandwiching the piezoelectric thin film, and a protection film laminated on the second metal electrode film which is provided so as to cover the second metal electrode film. According to the present invention, deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and a piezoelectric thin film resonator with a good characteristic of film quality can be provided.	CLAIM OF PRIORITY The present invention application claims priority from Japanese application JP2007-6117 filed on Jan. 15, 2007, the content of which is hereby incorporated by reference into this application. FIELD OF THE INVENTION The present invention relates to a piezoelectric thin film resonator, a piezoelectric thin film resonator filter and a manufacturing method thereof, and particularly to a resonator which utilizes piezoelectric/anti-piezoelectric effects of a thin film piezoelectric body and a resonance phenomenon of a bulk acoustic wave (hereinafter, abbreviated as a piezoelectric thin film bulk acoustic wave resonator). In addition, the present invention relates particularly to a piezoelectric thin film bulk acoustic wave resonator filter, a thin film tuning-fork-shape distorting oscillator, and a high frequency module, all of which use the resonator, and a manufacturing method thereof. BACKGROUND OF THE INVENTION A piezoelectric thin film bulk acoustic wave resonator generally includes a piezoelectric thin film deposited by a thin film forming apparatus, and a resonator unit composed of a first metal electrode film and a second metal electrode film, which are located above and below while sandwiching at least a part of the piezoelectric thin film. The first metal electrode film functions as a lower electrode, and the second metal electrode film functions as an upper electrode. The piezoelectric thin film is polarized in the thickness direction. An alternating electric field generated by alternating voltage that is applied between the lower electrode and the upper electrode causes stretching of the piezoelectric thin film in the thickness direction, namely an acoustic wave by piezoelectric/anti-piezoelectric effects. There exist acoustic insulating layers above and below the resonator composed of the piezoelectric thin film, the lower electrode, and the upper electrode. The piezoelectric thin film bulk acoustic wave resonator suitable for a high frequency filter is classified based on methods by which a bulk acoustic wave is sealed inside the piezoelectric thin film, and FBAR (Film Bulk Acoustic wave Resonator) and SMR (Solidly Mounted Resonator) are well known. An interface between a solid body and gaseous matter (or, vacuum) functions as an effective acoustic insulating layer, and therefore areas above and below the resonator are in a gaseous state (or, vacuum state) in FBAR. An area above the upper electrode is in a gaseous state (or, vacuum state), and a Bragg reflector is mounted below the lower electrode in SMR. U.S. Pat. No. 6,496,085 B2 discloses the device configuration of SMR and a process flow thereof. Japanese Patent Application Laid-Open No. 2005-303573 proposes a resonator structure in which AlN is formed only on a lower electrode and no bump is formed on an upper electrode due to AlN high orientation. Further, US 2005/0248232 A1 describes an improvement of AlN orientation by sequential deposition of a lower electrode and a piezoelectric film, and an electromechanical coupling coefficient. The above US 2005/0248232 A1 describes that flatness and cleaning properties immediately after deposition are not maintained on a surface of the lower electrode due to adsorption of impurities in conventional piezoelectric film manufacturing process ([0008]). Further, Japanese Patent Application Laid-Open No. 2004-200843 discloses a manufacturing method which aims at reducing a cost in such a manner that a support film is made of AlN, and a sacrificial layer for forming an oscillation space, the support film, a lower electrode film, a piezoelectric thin film, and an upper electrode film are sequentially deposited in the same apparatus. Further, “Comparison of Micromachined FBAR Band Pass Filters with Different. Structural Geometry” (Park et al, 2003 IEEE MTT-S Digest, pp. 2005-2008) discloses the device configuration of FBAR and a process flow thereof. On the other hand, a thin film tuning-fork-shape distorting oscillator is composed of, as similar to the piezoelectric thin film bulk acoustic wave resonator, a piezoelectric thin film deposited by a thin film forming apparatus, and a first metal electrode film and a second metal electrode film which are located above and below while sandwiching a part of the piezoelectric thin film, and is a distorting oscillator in which the piezoelectric thin film is patterned in a tuning-fork shape. U.S. Pat. No. 7,083,740 B2 discloses the resonance device configuration of a thin film tuning-fork-shape distorting oscillator and a manufacturing method thereof. SUMMARY OF THE INVENTION A piezoelectric thin film bulk acoustic wave resonator is characterized in that a Q-value is generally high. However, a trend of new systems requires a much higher Q-value. Similarly, a much higher Q-value as well as downsizing of the system, a high natural resonance frequency, a wide bandwidth, little fluctuation in electric characteristics with respect to process changes, and a low cost is required for a thin film tuning-fork-shape distorting oscillator. In order to produce a piezoelectric thin film bulk acoustic wave resonator filter using a piezoelectric thin film bulk acoustic wave resonator, it is necessary to electrically connect two or more piezoelectric thin film bulk acoustic wave resonators having different resonance frequencies with each other. For this purpose, a general manufacturing process is as follows. A lower electrode layer located below a piezoelectric thin film is formed in an arbitrary shape so as to be connected between plural resonators, and then a piezoelectric layer and an upper electrode layer are formed. The manufacturing process is disclosed in U.S. Pat. No. 6,496,085 B2, Japanese Patent Application Laid-Open No. 2005-303573 and “Comparison of Micromachined FBAR Band Pass Filters with Different Structural Geometry”. The manufacturing process disclosed in the “Comparison of Micromachined FBAR Band Pass Filters with Different Structural Geometry” will be described below as a conventional technique. First, a lower electrode is deposited so as to cover a silicon substrate, and is patterned in an arbitrary shape. Next, a piezoelectric thin film is deposited so as to cover a surface of the lower electrode pattern and a surface of the silicon substrate exposed by removing the lower electrode, and is patterned in an arbitrary shape. By patterning the piezoelectric thin film, a part of the lower electrode is exposed. Next, the lower electrode is deposited so as to cover a surface of the piezoelectric thin film and a surface of the silicon substrate exposed by removing the piezoelectric thin film, and is patterned in an arbitrary shape. Finally, by etching a part of a back surface of the silicon substrate, a cavity is formed immediately below a resonator unit. The piezoelectric thin film bulk acoustic wave resonator can be obtained by the above manufacturing method. In the element structure, each of the first metal electrode film, the piezoelectric thin film, and the second metal electrode film is exposed in the air for pattering in mid-course of manufacturing. Due to this, oxygen and nitrogen are mixed inside the piezoelectric thin film and the metal electrode film. Along with this, inner portions (bulk portions) of the respective piezoelectric film layer and the metal electrode film layer are different from epidermic portions thereof in material composition, and these layers come into contact with each other through an interface. There is concern that such changes of the materials in the epidermic portions of the piezoelectric film layer and the metal electrode film layer have an adverse effect on element characteristics of the piezoelectric thin film bulk acoustic wave resonator. On the other hand, since the first metal electrode film and the piezoelectric thin film are sequentially deposited in US 2005/0248232 A1 ([0034]), and the first metal electrode film, the piezoelectric thin film, and the second metal electrode film are sequentially deposited in Japanese Patent Application Laid-Open No. 2004-200843, it is conceivable that effects on element characteristics of the piezoelectric thin film bulk acoustic wave resonator are alleviated as compared to the former manufacturing method. However, even in the case of the latter manufacturing methods, the piezoelectric thin film and the second metal electrode film (US 2005/0248232 A1), or the second metal electrode film (Japanese Patent Application Laid-Open No. 2004-200843) is exposed in the air in mid-course of manufacturing. Along with this, concern still remains in that mixing of oxygen and nitrogen inside the piezoelectric thin film and the second metal electrode film has an adverse effect on element characteristics of the piezoelectric thin film bulk acoustic wave resonator. Even for a thin film tuning-fork-shape distorting oscillator, the conventional technique disclosed in U.S. Pat. No. 7,083,740 B2 involves a problem similar to the piezoelectric thin film bulk acoustic wave resonator. The issue of the present invention is to address conventional problems according to the above-described resonator structure forming technique, and an object thereof is to provide a piezoelectric thin film bulk acoustic wave resonator or a thin film tuning-fork-shape distorting oscillator which can realize a good characteristic of film quality, and a manufacturing method thereof. A representative example of the present invention is as follows. That is, a piezoelectric thin film resonator comprising: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, wherein the laminated structure being formed on a substrate; and an acoustic insulating layer which is formed on the substrate at a position corresponding to the laminated structure, wherein the first metal electrode film is formed on the substrate, and the second metal electrode film is formed on the first metal electrode film while sandwiching the piezoelectric thin film, and a protection film laminated on the second metal electrode film which is provided so as to cover the second metal electrode film. According to the present invention, deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and a piezoelectric thin film resonator with a good characteristic of film quality can be provided. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a longitudinal sectional structured view of a piezoelectric thin film bulk acoustic wave resonator according to a first embodiment of the present invention; FIG. 1B is a top view of the piezoelectric thin film bulk acoustic wave resonator shown in FIG. 1A; FIG. 2A to FIG. 2G are sectional structured views showing an example of a manufacturing method of the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment in the order of manufacturing processes; FIG. 3 is analysis data that shows effects of the device structure according to the first embodiment of the present invention, wherein the data shows oxygen contents in a metal electrode film and a piezoelectric thin film; FIG. 4 is analysis data that shows effects of the device structure according to the first embodiment of the present invention, wherein the data shows hydrogen contents in the metal electrode film and the piezoelectric thin film; FIG. 5 is a diagram showing an example of an impedance-frequency characteristic relation between the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment of the present invention and a piezoelectric thin film bulk acoustic wave resonator manufactured by a conventional non-sequential deposition method; FIG. 6 is a sectional structured view showing an example of a piezoelectric thin film bulk acoustic wave resonator as a second embodiment of the present invention; FIG. 7A to FIG. 7E are sectional structured views showing an example of a manufacturing method of the piezoelectric thin film bulk acoustic wave resonator shown in FIG. 6 in the order of manufacturing processes; FIG. 8A to FIG. 8F are sectional structured views showing an example of a manufacturing method of a piezoelectric thin film bulk acoustic wave resonator as a third embodiment according to the present invention in the order of manufacturing processes; FIG. 9 is a perspective view showing an appearance of a thin film tuning-fork-shape distorting oscillator as a fourth embodiment of the present invention; FIG. 10A to FIG. 10E are sectional structured views showing an example of a manufacturing method of the thin film tuning-fork-shape distorting oscillator as the fourth embodiment according to the present invention in the order of manufacturing processes; FIG. 11 is a circuit block diagram showing one example of a front end portion in a common mobile phone of which the present invention is applicable; FIG. 12 is a circuit block diagram of a transmit filter section and a receive filter section configured by an arrangement of the piezoelectric thin film bulk acoustic wave resonators of the front end portion shown in FIG. 11; FIG. 13A is a schematic appearance perspective view in which the transmit filter composed of the piezoelectric thin film bulk acoustic wave resonators according to the present invention is produced on a single substrate; and FIG. 13B is a diagram showing a cross-section taken along the line a-a of FIG. 13A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a piezoelectric thin film resonator, a piezoelectric thin film resonator filter, and a manufacturing method thereof according to the present invention will be described in more detail with reference to several preferred embodiments shown in the drawings. It should be noted that a thin film described in the present invention is a film prepared by a deposition apparatus. Further, the deposition apparatus described in the present invention is an apparatus which is typified by a sputtering apparatus, a vapor deposition apparatus and a CVD apparatus, and which prepares a film by directly laminating molecules, atoms, ions or clusters thereof on a substrate, or by laminating them with chemical reactions. Therefore, the thin film described in the present invention excludes members other than a film prepared by a deposition apparatus, such as a sintered body prepared by sintering and a bulk body formed by a hydrothermal synthesis method, a Czochralski method or the like, irrespective of their thicknesses. First Embodiment A first embodiment of a piezoelectric thin film bulk acoustic wave resonator according to the present invention will be described with reference to FIGS. 1A to 6. First, a structure of the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment will be described with reference to FIG. 1A and FIG. 1B. FIG. 1A is a longitudinal sectional structured view of the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment. FIG. 1B is a top view of the piezoelectric thin film bulk acoustic wave resonator shown in FIG. 1A. The piezoelectric thin film bulk acoustic wave resonator according to the first embodiment includes: a support film 2 made of AlN on an acoustic insulating layer 20 produced on an insulating substrate 1; and a laminated structure, on the support film 2, which has a piezoelectric thin film 4, and a first metal electrode film 3 and a second metal electrode film 5 that interpose at least a part of the piezoelectric thin film 4. As a material of the first metal electrode film 3 and the second metal electrode film 5, for example, Mo is used, and as a material of the piezoelectric thin film 4, AlN is used. A protection film 6 made of an insulating material, or a thin film made of SiO2 in this case is formed so as to cover an upper surface of the second metal electrode film 5 which serves as an upper electrode. Among a pair of pad electrodes 7 (7a, 7b), a first pad electrode 7a is formed on the first metal electrode film 3, and a second pad electrode 7b formed on the support film 2 is connected with an upper surface of the second metal electrode film 5. The numerals 13 and 30 denote a flat layer and an insulating film, respectively. The second metal electrode film 5 is covered with the protection film 6 throughout the whole upper surface of an area where at least the laminated structure substantially functions as a resonator. In the first embodiment, the whole upper surface of the second metal electrode film 5 is covered with the protection film 6 and the second pad electrode 7b. It should be noted that the support film 2, the first metal electrode film 3, the piezoelectric thin film 4, the second metal electrode film 5, and the protection film 6 are sequentially deposited in vacuum, as will be described later, and are not exposed in the air. Accordingly, the respective films of the support film 2 and the first metal electrode film 3, the first metal electrode film 3 and the piezoelectric thin film 4, the piezoelectric thin film 4 and the second metal electrode film 5, and the second metal electrode film 5 and the protection film 6 come into contact with each other through an interface their between, respectively. That is, oxygen, nitrogen, or moisture is mixed between the respective films, so that an epidermic layer that is different in composition from an inner portion (bulk portion) of each layer is present. As a result, forming of an interface between the epidermic portion of the piezoelectric film layer or the metal electrode film layer, and the inner portion thereof, in other words, deterioration of film quality due to oxidization or nitridation of each thin film in a deposition process can be prevented to the minimum degree. Therefore, it is possible to manufacture a piezoelectric thin film bulk acoustic wave resonator which has a good characteristic of film quality and which is excellent in element characteristics. The first embodiment is an embodiment in which a piezoelectric thin film bulk acoustic wave resonator of an SMR type is exemplified, and in which low acoustic impedance films 11 and high acoustic impedance films 10 are alternately formed as the acoustic insulating layer 20 on the insulating substrate 1, the high acoustic impedance films 10 are patterned in a shape of a resonator, and then the low acoustic impedance films 11 are embedded thereto so as to be made flat. Hereinafter, one example of a manufacturing method of the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment will be described along with FIG. 2A to FIG. 2G. First, the acoustic insulating layer 20 is formed on a high-resistance silicon substrate as the insulating substrate 1. A piezoelectric thin film bulk acoustic wave resonator of an SMR type is exemplified in this case, so that the low acoustic impedance film 11 made of SiO2 is deposited so as to have a thickness of 700 nm, and then the high acoustic impedance film 10 made of W is deposited so as to have a thickness of 700 nm by a deposition apparatus. Further, SiO2 is deposited so as to have a thickness of 700 nm, W is deposited so as to have a thickness of 700 nm, and SiO2 is deposited so as to have a thickness of 700 nm. Accordingly the acoustic insulating layer 20 in which two W films and three SiO2 films are alternately deposited can be formed. (Step a) Next, in order to suppress parasitic capacitance coupling among the high acoustic impedance layers 10, the first metal electrode film 3, and the second metal electrode film 5, the high acoustic impedance layers 10 are eliminated by etching except portions immediately below the resonator. (Step b) Next, as the thick flat layer 13, SiO2 is deposited so as to have a thickness of 3000 nm or more by the deposition apparatus. Next, the acoustic insulating layer 20 is polished up to its upper portion by a chemical mechanical polishing method (CMP), thereby completing the acoustic insulating layer 20 whose surface is made flat. (Step c) It is obvious that a method other than the above-described method can be employed without any problems in producing the acoustic insulating layer 20. Next, a producing process of a resonator layer is performed. The support layer 2 made of AlN is deposited so as to have a thickness of 30 nm, the first metal electrode film 3 made of Mo is deposited so as to have a thickness of 400 nm, the piezoelectric thin film 4 made of AlN is deposited so as to have a thickness of 950 nm, the second metal electrode film 5 made of Mo is deposited so as to have a thickness of 400 nm, and the protection film 6 made of SiO2 is deposited so as to have a thickness of 100 nm by the deposition apparatus. (Step d) It should be noted that the producing (Step d) of the above-described five layers configuring the resonator layer is conducted by sequential deposition in vacuum without being opened to the air in mid-course of the deposition process. Thereafter, the protection film 6 made of SiO2 is patterned by an ordinary photoresist process and an ordinary etching process (the layers are appropriately opened to the air in mid-course of the process), so that the protection film 6 in a desired area is obtained. Further, the second metal electrode film 5 made of Mo and the piezoelectric thin film 4 made of AlN are patterned by an ordinary photoresist process and an ordinary etching process, so that the second metal electrode film 5 and the piezoelectric thin film 4 in desired areas are obtained. Furthermore, the first metal electrode film 3 made of Mo is patterned by an ordinary photoresist process and an ordinary etching process, so that the first metal electrode film 3 in a desired area is obtained. At this time, areas where the pair of electrode pads connected with the respective metal electrode films are formed are also patterned at the same time by an ordinary photoresist process and an ordinary etching process. (Step e) Next, the insulating layer 30 made of SiO2 is selectively formed by a liftoff method in an area where the first metal electrode film 3, the piezoelectric thin film 4, and the second metal electrode film 5 are patterned on the same plane. (Step f) Next, the pad electrodes 7 and a wire made of Al are selectively formed by the liftoff method so as to have a thickness of 400 nm. (Step g) By employing the above-described manufacturing method, it is possible to obtain the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment. According to the first embodiment, the support film 2, the first metal electrode film 3, the piezoelectric thin film 4, the second metal electrode film 5, and the protection film 6 are sequentially deposited in vacuum, thereby obtaining a piezoelectric thin film bulk acoustic wave resonator which realizes a low cost and a good characteristic of film quality, and at the same time, has a high Q-value. FIGS. 3 and 4 are analysis data showing oxygen content and hydrogen content of the first metal electrode film 3 and the piezoelectric thin film 4 in the piezoelectric thin film bulk acoustic wave resonator according to the first embodiment of the present invention. As an analysis scheme, SIMS is employed, and a component analysis is conducted while etching the protection film 6 and then the second metal electrode film 5 from a surface of the element. AlN is used for the protection film 6 of a sample by which these measurement results were obtained, and the thickness thereof is about 1000 nm. Mo is used for the second metal electrode film 5, and the thickness thereof is 250 nm. In a conventional method disclosed in U.S. Pat. No. 6,496,085 B2, or the like, the piezoelectric thin film 4 is formed after forming an etching mask on the first metal electrode film 3 by an ordinary photoresist process and patterning the same by an ordinary etching process. Thereafter, the second metal electrode film 5 is formed after forming an etching mask on the piezoelectric thin film 4 by an ordinary photoresist process and patterning the same by an ordinary etching process. Thereafter, the second metal electrode film 5 is formed after forming an etching mask on the second metal electrode film 5 by an ordinary photoresist process and patterning the same by an ordinary etching process. Therefore, the first metal electrode film 3, the piezoelectric thin film 4, and the second metal electrode film 5 are exposed in the air in the manufacturing process. On the other hand, in the present invention, the first metal electrode film 3, the piezoelectric thin film 4, the second metal electrode film 5, and the protection film 6 are sequentially deposited in vacuum, and then an etching mask is formed by an ordinary photoresist process. Thereafter, the protection film 6, the second metal electrode film 5, the piezoelectric thin film 4, and the first metal electrode film 3 are patterned by an ordinary etching process. Therefore, the respective films of the laminated structure including the second metal electrode film 5 and the protection film 6 come into contact with each other through an interface their between, respectively. As being apparent from the results of FIGS. 3 and 4, according to the structure of the present invention, it can be understood that an oxygen amount and a hydrogen amount each contained in the protection film (AlN) and the second metal electrode film (Mo) are lowered. The fact shows that the second metal electrode film comes into contact with the protection film through an interface so as to prevent a change of the material in the epidermic portion of the metal electrode film. On the other hand, in the case of the conventional method, the inner portions of the respective piezoelectric film layer and the metal electrode film layer are different from the epidermic portions thereof in material composition due to the mixture of oxygen and nitrogen into the inner portions of the piezoelectric thin film and the metal electrode film. Accordingly, it is obvious that the fact has an adverse effect on element characteristics of the piezoelectric thin film bulk acoustic wave resonator. This directly leads to an increment of a resistance value, which causes deterioration of the Q-value of the piezoelectric thin film bulk acoustic wave resonator. Application of the piezoelectric thin film bulk acoustic wave resonator in which the Q-value is deteriorated involves a serious problem due to damage of a steep filter characteristic that is a feature of the piezoelectric thin film bulk acoustic wave resonator filter. FIG. 5 is a diagram showing one example of an impedance/frequency characteristic relation between the piezoelectric thin film bulk acoustic wave resonator (SMR1) manufactured by the sequential deposition method of the first embodiment of the present invention and the piezoelectric thin film bulk acoustic wave resonator (SMR2) manufactured by a conventional non-sequential deposition method, both of which were described using FIGS. 3 and 4. The Q-value is considerably improved in the first embodiment, compared to the conventional method. It should be noted that as the protection film 6 becomes thinner, the function as a protection film is insufficient, and as the protection film 6 becomes thicker, it has an adverse effect on frequency characteristics and the like. Therefore, it is desirable to set the thickness of the protection film in a range of 50 nm to 150 nm. In the structure of the first embodiment, an SiO2 film is laminated as the protection film 6 on the second metal electrode film 5 of the resonator element, and, at the same time, the film thickness of the protection film is optimized, so that a resonance frequency characteristic and a temperature characteristic are effectively improved. The film thickness of the protection film 6 is determined based on a relation between the SiO2 film thickness and the temperature characteristic, and it is advantageous to adjust the thickness of the protection film 6 in a range of 500 nm or less in order to improve the temperature characteristic and the like. Thus, it is desirable to appropriately set the thickness of the protection film 6 in a range of 50 nm to 600 nm as a whole. As described above, according to the first embodiment, the first metal electrode film, the piezoelectric thin film, the second metal electrode film, and the protection film are sequentially deposited by the same apparatus, so that deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and the piezoelectric thin film bulk acoustic wave resonator with a good characteristic of film quality can be formed. Further, by adjusting the film thickness of the protection film, it is also possible to improve a resonance frequency characteristic and a temperature characteristic. Second Embodiment FIG. 6 is a sectional structured view showing one example of a piezoelectric thin film bulk acoustic wave resonator of a second embodiment according to the present invention. The second embodiment is characterized in that a laminated structure which includes a piezoelectric thin film 4, and a first metal electrode film 3 and a second metal electrode film 5 that interpose at least a part of the piezoelectric thin film 4 is produced, and an AlN thin film is formed as a protection film 6 so as to cover the second metal electrode film 5 which serves as an upper electrode. At this time, a support film 2, the first metal electrode film 3, the piezoelectric thin film 4, the second metal electrode film 5, and the protection film 6 made of AlN are sequentially deposited in vacuum, so that deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree. Therefore, the piezoelectric thin film bulk acoustic wave resonator with a good characteristic of film quality can be manufactured. The second embodiment is an embodiment in which a piezoelectric thin film bulk acoustic wave resonator of an FBAR type is exemplified, and an acoustic insulating layer 20 is produced in such a manner that an insulating substrate 1 immediately below a resonator is etched from a back surface thereof to form a cavity 60. Hereinafter, one example of a manufacturing method of the piezoelectric thin film bulk acoustic wave resonator according to the second embodiment will be described along with FIG. 7A to FIG. 7E. First, on a high-resistance silicon substrate as the insulating substrate 1, the support layer 2 made of AlN is deposited so as to have a thickness of 30 nm, the first metal electrode film 2 made of Mo is deposited so as to have a thickness of 400 nm, the piezoelectric thin film 4 made of AlN is deposited so as to have a thickness of 950 nm, the second metal electrode film 5 made of Mo is deposited so as to have a thickness of 400 nm, and the protection film 6 made of AlN is deposited so as to have a thickness of 50 nm. The above-described five layers are formed by sequential deposition in vacuum without being opened to the air in mid-course of the deposition process. (Step a) Thereafter, the protection film 6 made of AlN is patterned by an ordinary photoresist process and an ordinary etching process, so that the protection film 6 in a desired area is obtained. Further, the second metal electrode film 5 made of Mo and the piezoelectric thin film 4 made of AlN are patterned by an ordinary photoresist process and an ordinary etching process, so that the upper electrode and the piezoelectric thin film 4 in desired areas are obtained. Furthermore, the first metal electrode film 3 made of Mo is patterned by an ordinary photoresist process and an ordinary etching process, so that the lower electrode in a desired area is obtained. (Step b) Next, an insulating layer 30 made of SiO2 is selectively formed by a liftoff method in a area where the first metal electrode film 3, the piezoelectric thin film 4, and the second metal electrode film 5 are patterned on the same plane. (Step c) Next, pad electrodes 7 and a wire made of Al are selectively formed by the liftoff method so as to have a thickness of 400 nm. (Step d) Next, in order to form the cavity 60 in a lower portion of the piezoelectric thin film bulk acoustic wave resonator, a resist is formed as an etching mask along an area, on a back surface of the insulating substrate 1, corresponding to the piezoelectric thin film bulk acoustic wave resonator. Next, dry etching is performed by Deep-RIE from a back surface of the insulating substrate 1 so as to form the cavity 60 in a substantially vertical shape. (Step e) By employing the above-described manufacturing method, the piezoelectric thin film bulk acoustic wave resonator according to the second embodiment can be obtained. Also in the second embodiment, the first metal electrode film, the piezoelectric thin film, the second metal electrode film, and the protection film are sequentially deposited by the same apparatus, so that deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and the piezoelectric thin film bulk acoustic wave resonator with a good characteristic of film quality can be formed. Further, by adjusting the film thickness of the protection film, it is also possible to improve a resonance frequency characteristic. Third Embodiment FIG. 8A to FIG. 8F show one example of a manufacturing method of a piezoelectric thin film bulk acoustic wave resonator of a third embodiment according to the present invention. First, a cavity 60 having a depth of 800 nm is provided on a high-resistance silicon substrate 1 as an insulating substrate by an ordinary photoresist process and an ordinary etching process. Next, a barrier layer 40 made of Si3N4 is deposited so as to have a thickness of 100 nm on a surface of the insulating substrate 1 where the cavity 60 is formed, and further, a sacrificial layer 50 made of phosphoric-silicate glass (PSG) is deposited so as to have a thickness of 1000 nm. (Step a) Next, the sacrificial layer 50 is made flat by a chemical mechanical polishing method (CMP) in such a manner that a surface of the barrier layer 40 formed on the insulating substrate 1 is exposed, and only the cavity 60 is filled with the sacrificial layer 50. (Step b) Next, on the insulating substrate 1 in which the cavity 60 is filled with the sacrificial layer 50 and whose surface is made flat, a support layer 2 made of AlN is deposited so as to have a thickness of 30 nm, a first metal electrode film 3 made of Mo is deposited so as to have a thickness of 400 nm, a piezoelectric thin film 4 made of AlN is deposited so as to have a thickness of 950 nm, a second metal electrode film 5 made of Mo is deposited so as to have a thickness of 400 nm, and a protection film 6 made of SiO2 is deposited so as to have a thickness of 100 nm. Forming of all five layers of the support layer 2, the first metal electrode film 3, the piezoelectric thin film 4, the second metal electrode film 5, and the protection film 6 is conducted by sequential deposition in vacuum without being opened to the air in mid-course of the deposition. (Step c) Thereafter, the protection film 6 made of SiO2 is patterned by an ordinary photoresist process and an ordinary etching process, so that the protection film 6 in a desired area is obtained. Further, the second metal electrode film 5 made of Mo and the piezoelectric thin film 4 made of AlN are patterned by an ordinary photoresist process and an ordinary etching process, so that the second metal electrode film 5 and the piezoelectric thin film 4 in desired areas are obtained. Furthermore, the first metal electrode film 3 made of Mo is patterned by an ordinary photoresist process and an ordinary etching process, so that the first metal electrode film 3 in a desired area is obtained. (Step d) Next, an insulating layer 30 made of Si3N4 is selectively formed by a liftoff method in an area where the first metal electrode film 3, the piezoelectric thin film 4, and the second metal electrode film 5 are patterned on the same plane. (Step e) Next, pad electrodes 7 and a wire made of Al are selectively formed by the liftoff method so as to have a thickness of 400 nm. Next, in order to form the cavity 60 in a lower area of the piezoelectric thin film bulk acoustic wave resonator, PSG of the sacrificial layer 50 is removed in a liquid solution containing hydrofluoric acid (HF). In the removal process of the sacrificial layer 50, SiO2 of the protection film 6 can be also removed at the same time. (Step f) The piezoelectric thin film bulk acoustic wave resonator in which SiO2 of the protection film 6 is removed is immediately airtight sealed. Therefore, deterioration of film quality due to oxidization or nitridation of the thin film accompanied by mixture of oxygen, nitrogen, or moisture into the second metal electrode film 5 can be prevented to the minimum degree. By employing the above-described manufacturing method, deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, so that the piezoelectric thin film bulk acoustic wave resonator with a good characteristic of film quality can be obtained. Since the characteristics shown in FIG. 6 are utilized also in the third embodiment, the material of the protection film 6 is left as a material different from that of the sacrificial layer, so that a resonance frequency characteristic and a temperature characteristic can be improved. Fourth Embodiment Next, as a fourth embodiment of the present invention, an example in which a thin film tuning-fork-shape distorting oscillator is applied will be described with reference to FIG. 9 and FIGS. 10A to 10E. First, FIG. 9 is a perspective view showing an appearance of the thin film tuning-fork-shape distorting oscillator of the fourth embodiment according to the present invention. The thin film tuning-fork-shape distorting oscillator is configured in such a manner that a thin film distorting oscillator is mounted on a high-resistance silicon substrate as an insulating substrate 1 in parallel with a surface of the insulating substrate 1, and the oscillator is formed in a tuning-fork shape. However, in order to apply the present invention, a first metal electrode film of a lower electrode is arranged on the whole surface of a piezoelectric thin film 4. That is, the thin film tuning-fork-shape distorting oscillator includes: a support film 2 made of AlN on the insulating substrate 1; and a laminated structure, on the support film 2, which has the piezoelectric thin film 4, and a first metal electrode film 3 and a second metal electrode film 5 that interpose the piezoelectric thin film 4. A protection film 6 made of SiO2 is formed so as to cover the second metal electrode film 5 which serves as an upper electrode. The numeral 60 denotes a cavity provided on the insulating substrate 1 while corresponding to the laminated structure. FIG. 10A to FIG. 10E show one example of a manufacturing method of the thin film tuning-fork-shape distorting oscillator of the fourth embodiment according to the present invention. Hereinafter, one example of the manufacturing method of the thin film tuning-fork-shape distorting oscillator of the fourth embodiment will be described. On the high-resistance silicon substrate as the insulating substrate 1, the support film 2 made of AlN is deposited so as to have a thickness of 30 nm, the first metal electrode film 3 made of Mo is deposited so as to have a thickness of 400 nm, the piezoelectric thin film 4 made of AlN is deposited so as to have a thickness of 950 nm, the second metal electrode film 5 made of Mo is deposited so as to have a thickness of 400 nm, and the protection film 6 made of SiO2 is deposited so as to have a thickness of 100 nm. Forming of the five layers is conducted by sequential deposition in vacuum without being opened to the air in mid-course of the deposition. (Step a) Thereafter, the protection film 6 made of SiO2 is patterned by an ordinary photoresist process and an ordinary etching process, so that the protection film 6 in a desired area is obtained. Further, the second metal electrode film 5 made of Mo is patterned by an ordinary photoresist process and an ordinary etching process, so that the second metal electrode film 5 in a desired shape is obtained. Further, the piezoelectric thin film 4 made of AlN, the first metal electrode film 3 made of Mo, and the support layer 2 made of AlN are patterned, so that the piezoelectric thin film 4, the first metal electrode film 3, and the support film 2 in a desired tuning-fork shape are obtained. (Step b) Next, an insulating layer 30 made of SiO2 is selectively formed by a liftoff method in at least one side area where the first metal electrode film 3, the piezoelectric thin film 4, and the second metal electrode film 5 are patterned on the same plane. (Step c) Next, a pad electrode 7 and a wire made of Al are selectively formed by the liftoff method so as to have a thickness of 400 nm. (Step d) Next, in order to form the cavity 60 in a lower area of the thin film tuning-fork-shape distorting oscillator, a resist as an etching mask is formed along an area, on a back surface of the insulating substrate 1, corresponding to the thin film tuning-fork-shape distorting oscillator, and then dry etching is performed from a back surface of the insulating substrate 1 by Deep-RIE to form the cavity 60 whose side walls are substantially vertical and whose cross-section is in a rectangular shape. (Step e) By employing the above-described manufacturing method, the thin film tuning-fork-shape distorting oscillator according to the fourth embodiment can be obtained. According to the fourth embodiment, the first metal electrode film, the piezoelectric thin film, the second metal electrode film, and the protection film are sequentially deposited by the same apparatus, so that deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and the thin film tuning-fork-shape distorting oscillator with a good characteristic of film quality can be formed. Further, by adjusting the film thickness of the protection film, a resonance frequency characteristic and a temperature characteristic can be improved. MODIFIED EXAMPLE In the above-described respective embodiments of the present invention, the high-resistance silicon substrate is used as the insulating substrate 1. However, a substrate made of an insulating material, for example, a glass substrate, a compound semiconductor substrate, a high-resistance silicon substrate, a piezoelectric substrate, or the like can be applied to the insulating substrate 1. Further, a semiconductor substrate, a semiinsulating substrate, or a conductor substrate, each surface of which is covered with an insulating film typified by silicon oxide can be also applied to the insulating substrate 1. Further, Mo is used as a material of the first metal electrode film 3 and the second metal electrode film 5. However, other conductive materials such as Ta, Ni, Nb, Au, Pt, Cu, Pd, Ti, and W can be similarly used. Further, AlN is used as a material of the piezoelectric thin film 4. However, other materials such as ZnO, PZT, PbTiO3, and BaTiO3 can be similarly used. Further, phosphoric-silicate glass is used as a material of the sacrificial layer 50. However, other materials such as SiO2, Ge, and Ti can be similarly used as long as they are easy to etch with hydrofluoric acid. It should be noted that the thickness of each layer is an example, and it is obvious that the design can be appropriately changed in accordance with a material to be used and a necessary resonance frequency. In order to realize downsizing by increasing a package density of a piezoelectric thin film bulk acoustic wave resonator and a filter using the same, two piezoelectric thin film bulk acoustic wave resonators may be deposited above and below on the substrate. In this case, the upper and lower piezoelectric thin film bulk acoustic wave resonators are sequentially deposited on the substrate by the same deposition apparatus. In addition, the protection film is sequentially deposited by the same apparatus on the second metal electrode film of the upper piezoelectric thin film bulk acoustic wave resonator. Thereby, deterioration of film quality due to oxidization of each thin film can be prevented to the minimum degree, and the piezoelectric thin film bulk acoustic wave resonator with a good characteristic of film quality can be formed. Fifth Embodiment FIG. 11 shows one example of a block circuit diagram including high frequency modules in a common mobile phone. Here, there will be described a case that a piezoelectric thin film bulk acoustic wave resonator filter using piezoelectric thin film bulk acoustic wave resonators according to the invention is configured on a single substrate. The numerals 78 and 79 denote a transmit filter and a receive filter, respectively. The numerals 130 is a phase shifter, 150 is a low noise amplifier, 151 is a power amplifier module, 152 is a transmit mixer, 153 is a receive mixer and 154 is a synthesizer, respectively. The numeral 155 is a baseband unit, 160 is a transmit/receive switch module and 161 is a high frequency integrated circuit module, respectively. The transmit/receive switch module 160, the high frequency integrated circuit module 161, and the power amplifier module 151 are independently formed into modules, or integrally formed into a module as a chipset for a mobile phone. The piezoelectric thin film resonators described in the first to fourth embodiments of the present invention are used as, for example, resonant elements of a ladder type configuring a series-arm resonators and a shunt-arm resonators, and accordingly, the transmit filter 78 and the receive filter 79 can be configured. In FIG. 11, a high frequency receive signal Rx received by an antenna ANT passes through the phase shifter 130, and is input to the low noise amplifier 150 for amplifying the high frequency receive signal Rx through the receive filter 79 through which only a predetermined receive-band frequency signal passes while removing an image frequency signal. The high frequency receive signal Rx amplified by the low noise amplifier 150 is transmitted to the baseband unit 155 through the receive mixer 153 to be converted to a baseband. On the other hand, a high frequency transmit signal Tx transmitted from the baseband unit 155 is input to the power amplifier module 151 for amplifying the high frequency transmit signal Tx through the transmit mixer 152 for producing a modulation radio frequency signal. The high frequency transmit signal Tx amplified by the power amplifier module 151 is emitted as a radio wave from the antenna through the transmit filter 78 through which only a predetermined transmit-band frequency signal passes. A common mobile phone includes the phase shifter 130 that enables common use of the antenna between a receive unit and a transmit unit, the synthesizer 154, and the baseband unit 155 that performs a signal process for a receive signal and a transmit signal. Each of such the transmit filter 78 and the receive filter 79 for high frequency signals used at a front end portion can be configured by an assembly of plural piezoelectric thin film bulk acoustic wave resonators. The block diagram shown in FIG. 11 represents a case of a single-band mobile phone. However, even in the configuration of a multiband mobile phone such as dual-band, triple-band and quad-band, the present invention can be similarly applied, and the configuration is not limited to that shown in the embodiment. In the fifth embodiment, as an example of a case of the transmit frequency Tx of 1.85 GHz to 1.91 GHz and the receive frequency Rx of 1.93 GHz to 1.99 GHz, the transmit filter 78 and the receive filter 79 which are configured by the piezoelectric thin film bulk acoustic wave resonator filters composed of plural piezoelectric thin film bulk acoustic wave resonators will be described. FIG. 12 is one example of a circuit block diagram of the transmit/receive switch module 160 shown in FIG. 11. The transmit filter 78 is configured by an arrangement of piezoelectric thin film bulk acoustic wave resonators 71 to 77 enclosed by a dotted line, and the receive filter 79 is configured by an arrangement of piezoelectric thin film bulk acoustic wave resonators 120 to 126 enclosed by a dotted line. The arrangement of the resonators shown herein is an example, and is not limited to that shown in the embodiment because the arrangement of the resonators is determined based on a desired filter characteristic. A circuit used as the phase shifter 130 is well known, and is configured by an inductor and a conductor, or a λ/4 transmitssion line. FIG. 13A shows a schematic appearance perspective view in the case where the transmit filter 78 is produced on a single substrate 70, as an example. Further, FIG. 13B shows a cross-section taken along the line a-a of FIG. 13A. Here, each of the piezoelectric thin film bulk acoustic wave resonators 71 to 77 is represented by a quadrangle. However, the shape is not limited to the quadrangle because the shape of the piezoelectric thin film bulk acoustic wave resonator is determined based on a desired filter characteristic. The piezoelectric thin film bulk acoustic wave resonators 71 to 73 which are connected with each other through a wire 80 configure series-arm resonators, and the piezoelectric thin film bulk acoustic wave resonators 74 to 77 configure shunt-arm resonators. In FIGS. 13A and 13B, a solid line that connects the piezoelectric thin film bulk acoustic wave resonators with each other shows the wire 80 through which an upper electrode layer 5 of the piezoelectric thin film bulk acoustic wave resonator is connected with a pad electrode 7 (7a, 7b), and a dotted line shows the wire 80 which is configured by a lower electrode layer 3 of the piezoelectric thin film bulk acoustic wave resonator (or which is connected with a lower electrode layer). The reference numeral P1 denotes an input wire pad to which a transmit signal is transmitted from an inner circuit (not shown), and is connected with a bonding wire BW and an input pad P11 (namely, pad electrode 7a) of the filter that is connected with the piezoelectric thin film bulk acoustic wave resonator 71 of the transmit filter 78. Further, the input wire pad is connected with an output pad P22 (namely, pad electrode 7b) of the filter through the piezoelectric thin film bulk acoustic wave resonators 72 and 73 which are series-connected through the wire 80 (the pad electrode 7b and the lower electrode layer 3). The output pad P22 of the filter is connected with a pad P2 which is connected with an antenna (not shown), through the bonding wire BW. Each of wire pads P33 and P44 connected with the upper electrode layers 5 of the piezoelectric thin film bulk acoustic wave resonators 74 and 76 and wire pads P55 and P66 connected with the lower electrode layers 3 of the piezoelectric thin film bulk acoustic wave resonators 75 and 77 is connected with a ground pad (not shown) through the bonding wire BW. As described above, the transmit filter 78 shown in the circuit diagram of FIG. 12 is formed on the single substrate 70. The receive filter 79 is also similarly formed on the single substrate 70. Accordingly, the transmit/receive switch module 160, the high frequency integrated circuit module 161, and the power amplifier module 151 can be independently formed into modules, or integrally formed into a module in a simple manner as a chipset for a mobile phone. In the fifth embodiment, since the piezoelectric thin film resonator filter in any embodiment of the above-described invention is used, an element area can be reduced, thereby realizing downsizing and a low cost of a high frequency module. The fifth embodiment shown herein is an example of using the bonding wire BW to connect the inner circuit with the transmit filter. However, it is obvious that the fifth embodiment can be applied to other package methods such as bump bonding, and is not limited thereto. Further, it is obvious that the present invention is not limited to a filter for a mobile phone, but can be applied to various applications as a filter for wireless communications.	H	67H01	185H01L	41	04
11849930	US20090057699A1-20090305	LED with Particles in Encapsulant for Increased Light Extraction and Non-Yellow Off-State Color	ACCEPTED	20090218	20090305	[]	H01L3300	["H01L3300"]	7791093	20070904	20100907	257	098000	81075.0	NGUYEN	NIKI	[{"inventor_name_last": "Basin", "inventor_name_first": "Grigoriy", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Haque", "inventor_name_first": "Ashim Shatil", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "Ching-hui", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "West", "inventor_name_first": "Robert Scott", "inventor_city": "Morgan Hill", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Martin", "inventor_name_first": "Paul", "inventor_city": "Pleasanton", "inventor_state": "CA", "inventor_country": "US"}]	In one embodiment, sub-micron size granules of TiO2, ZrO2, or other white colored non-phosphor inert granules are mixed with a silicone encapsulant and applied over an LED. In one experiment, the granules increased the light output of a GaN LED more than 5% when the inert material was between about 2.5-5% by weight of the encapsulant. Generally, a percentage of the inert material greater than 5% begins to reduce the light output. If the LED has a yellowish YAG phosphor coating, the white granules in the encapsulant make the LED appear whiter when the LED is in an off state, which is a more pleasing color when the LED is used as a white light flash in small cameras. The addition of the granules also reduces the variation of color temperature over the view angle and position over the LED, which is important for a camera flash and projection applications.	1. A light emitting device comprising: a semiconductor light emitting diode (LED); a layer of phosphor over the LED; and an encapsulant over the LED and phosphor directly contacting the phosphor, the encapsulant comprising a substantially transparent material containing inert non-phosphor particles, the particles being between 0.5%-10% by weight of the encapsulant, the particles having a substantially white color under white ambient light. 2. The device of claim 1 wherein the particles comprise TiOx. 3. The device of claim 2 wherein the particles comprise TiO2. 4. The device of claim 1 wherein the particles comprise ZrOx. 5. The device of claim 4 wherein the particles comprise ZrO2. 6. The device of claim 1 wherein the particles comprise between 2.5% and 7% of the encapsulant. 7. The device of claim 1 wherein an average diameter of the particles is less than one micron. 8. The device of claim 1 wherein the encapsulant comprises silicone. 9. The device of claim 1 wherein the encapsulant has a substantially flat surface over the LED. 10. The device of claim 1 wherein the phosphor is over at least a top surface of the LED, the phosphor having a yellowish color under white ambient light, the encapsulant, containing the particles, whitening an appearance of the phosphor when the LED is in an off state. 11. The device of claim 10 wherein the phosphor comprises a yttrium aluminum oxide garnet (YAG) phosphor. 12. The device of claim 1 wherein the particles increase light output power out of the encapsulant when the LED is in an on state, compared to the encapsulant having 0% of the particles. 13. The device of claim 1 wherein the particles lower a color temperature of light output from the encapsulant when the LED is in an on state, compared to the encapsulant having 0% of the particles. 14. The device of claim 1 wherein the particles lower a deviation of color temperature versus viewing angle of light output from the encapsulant when the LED is in an on state, compared to the encapsulant having 0% of the particles. 15. The device of claim 1 wherein the particles lower a deviation of color temperature versus position normal to a top surface of the LED when the LED is in an on state, compared to the encapsulant having 0% of the particles. 16. The device of claim 1 wherein the LED and encapsulant comprise a flash light source in a camera. 17. The device of claim 1 further comprising a camera, wherein the LED and encapsulant comprise a flash light source in the camera. 18. The device of claim 1 wherein a semiconductor portion of the LED emits blue light. 19. A method of manufacturing a light emitting device comprising: forming a layer of phosphor over at least a top surface of a semiconductor light emitting diode (LED); forming an encapsulant over the LED and phosphor so as to directly contact the phosphor, the encapsulant comprising a substantially transparent material containing inert non-phosphor particles, the particles being between 0.5%-10% by weight of the encapsulant and having an average diameter less than one micron, the particles having a substantially white color under white ambient light. 20. The method of claim 19 wherein the particles comprise TiO2. 21. The method of claim 19 wherein the particles comprise ZrO2. 22. The method of claim 19 wherein the phosphor has a yellowish color under white ambient light, the encapsulant containing the particles whitening an appearance of the phosphor when the LED is in an off state.	<SOH> BACKGROUND <EOH>A semiconductor LED, such as a GaN LED, has an index of refraction (e.g., n=2.2-3.0 for GaN) that is much higher than that of air (n=about 1). By encapsulating the LED in a transparent material, such as silicone (n=1.4-1.76), having an intermediate index of refraction, the light extraction is significantly increased. The encapsulant also protects the semiconductor LED die. It is desirable to further increase the light extraction. High power LEDs are now commonly used as flashes in small cameras, including cell phone cameras. The LEDs emit a white light. Such LEDs used as flashes are typically one or more GaN LED dies that emit blue light covered by a layer of yttrium aluminum oxide garnet (YAG) phosphor that emits a yellow-green light when energized by the blue light. The combination of the blue light leaking through the YAG phosphor and the yellow-green light produces white light. The YAG phosphor coating on the LED appears yellow-green under white ambient light when the LED is off. Such a yellow-green color is generally not attractive and typically does not match well with the appearance of the camera. It is desirable to somehow eliminate the yellow-green color of the flash in its off state.	<SOH> SUMMARY <EOH>In one embodiment, granules of TiOx, ZrOx, or other white non-phosphor inert material are mixed with the substantially transparent encapsulant for LEDs. One suitable encapsulant is silicone. It has been discovered by the Applicants that sub-micron size particles of the inert material, such as TiO 2 , in the encapsulant increase the brightness (lumens) of a GaN LED greater than 5% when the inert material is between about 2.5-5% (by weight) of the encapsulant. Generally, a higher percentage of the inert material begins to reduce the light output. Such a small quantity of the particles into the encapsulant produced surprising results that surpassed any results predicted by the inventors. A range of TiO 2 in the encapsulant from 0.5%-10% generally increases the brightness, depending on the actual LED used. A higher percentage begins to significantly reduce the transmission through the encapsulant. Both titanium dioxide and zirconium oxide are used as white pigments in paints and enamels. A color considered to be white has a range of color temperatures, and the color is affected by the viewing light. The term white, as used in the present disclosure, appears to an observer as substantially white under sunlight. The light enhancement achieved by the addition of the particles in the encapsulant occurs whether the LED is coated with a phosphor or not coated with a phosphor. Adding the TiO 2 to the encapsulant, in some experiments, slightly reduces the color temperature of the emitted light when the LED is on, which is not significant. However, the addition of the TiO 2 greatly reduces (e.g., by two-thirds) the variation of color temperature over the entire 180 degree emission angle. This is important in photography since the entire subject is illuminated with substantially uniform light. Further, adding the TiO 2 to the encapsulant also improves the color temperature uniformity across the package. This is especially important when optics are use that project an enlarged image of the LED, such as with a flashlight or projector. Since the inert material (e.g., TiO 2 or ZrO 2 ) is white, the appearance of the LED with a YAG phosphor coating appears much whiter when the LED is off, which is more pleasing than the yellow-green color of the YAG phosphor. In one embodiment, the flash LED module uses a silicone encapsulant with about 5% by weight of TiO 2 , where the encapsulant is formed to have a flat surface so as not to significantly affect the shape of the LED emission (i.e., the encapsulant does not form a lens). The camera includes a lens over the flash to control the light emission pattern of the flash. In another embodiment, the silicone encapsulant may be molded into a lens to shape the light emission pattern.	FIELD OF INVENTION This invention relates to light emitting diodes (LEDs) and, in particular, to techniques for improving light extraction. This invention also relates to creating a non-yellow off-state color of an LED having a yellowish phosphor coating. BACKGROUND A semiconductor LED, such as a GaN LED, has an index of refraction (e.g., n=2.2-3.0 for GaN) that is much higher than that of air (n=about 1). By encapsulating the LED in a transparent material, such as silicone (n=1.4-1.76), having an intermediate index of refraction, the light extraction is significantly increased. The encapsulant also protects the semiconductor LED die. It is desirable to further increase the light extraction. High power LEDs are now commonly used as flashes in small cameras, including cell phone cameras. The LEDs emit a white light. Such LEDs used as flashes are typically one or more GaN LED dies that emit blue light covered by a layer of yttrium aluminum oxide garnet (YAG) phosphor that emits a yellow-green light when energized by the blue light. The combination of the blue light leaking through the YAG phosphor and the yellow-green light produces white light. The YAG phosphor coating on the LED appears yellow-green under white ambient light when the LED is off. Such a yellow-green color is generally not attractive and typically does not match well with the appearance of the camera. It is desirable to somehow eliminate the yellow-green color of the flash in its off state. SUMMARY In one embodiment, granules of TiOx, ZrOx, or other white non-phosphor inert material are mixed with the substantially transparent encapsulant for LEDs. One suitable encapsulant is silicone. It has been discovered by the Applicants that sub-micron size particles of the inert material, such as TiO2, in the encapsulant increase the brightness (lumens) of a GaN LED greater than 5% when the inert material is between about 2.5-5% (by weight) of the encapsulant. Generally, a higher percentage of the inert material begins to reduce the light output. Such a small quantity of the particles into the encapsulant produced surprising results that surpassed any results predicted by the inventors. A range of TiO2 in the encapsulant from 0.5%-10% generally increases the brightness, depending on the actual LED used. A higher percentage begins to significantly reduce the transmission through the encapsulant. Both titanium dioxide and zirconium oxide are used as white pigments in paints and enamels. A color considered to be white has a range of color temperatures, and the color is affected by the viewing light. The term white, as used in the present disclosure, appears to an observer as substantially white under sunlight. The light enhancement achieved by the addition of the particles in the encapsulant occurs whether the LED is coated with a phosphor or not coated with a phosphor. Adding the TiO2 to the encapsulant, in some experiments, slightly reduces the color temperature of the emitted light when the LED is on, which is not significant. However, the addition of the TiO2 greatly reduces (e.g., by two-thirds) the variation of color temperature over the entire 180 degree emission angle. This is important in photography since the entire subject is illuminated with substantially uniform light. Further, adding the TiO2 to the encapsulant also improves the color temperature uniformity across the package. This is especially important when optics are use that project an enlarged image of the LED, such as with a flashlight or projector. Since the inert material (e.g., TiO2 or ZrO2) is white, the appearance of the LED with a YAG phosphor coating appears much whiter when the LED is off, which is more pleasing than the yellow-green color of the YAG phosphor. In one embodiment, the flash LED module uses a silicone encapsulant with about 5% by weight of TiO2, where the encapsulant is formed to have a flat surface so as not to significantly affect the shape of the LED emission (i.e., the encapsulant does not form a lens). The camera includes a lens over the flash to control the light emission pattern of the flash. In another embodiment, the silicone encapsulant may be molded into a lens to shape the light emission pattern. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a prior art flash LED comprising a blue LED die, a YAG phosphor coating, a submount, and a silicone encapsulant. FIG. 2 is a cross-sectional view of a flash LED in accordance with an embodiment of the invention, where TiO2 particles are mixed with the encapsulant. FIG. 3 is a graph illustrating the change in color appearance of the flash in its off state from yellow-green to white by the addition of the TiO2 in the encapsulant. FIG. 4 is a graph illustrating the lowering of the color temperature of the flash in its on state with the addition of the TiO2 in the encapsulant and the lowering of the deviation in color temperature over the viewing angle. FIG. 5 is a graph illustrating the improvement in color temperature uniformity across the LED package when TiO2 is added to the encapsulant. FIG. 6 is a cross-sectional view of a blue LED die without a phosphor coating in accordance with an embodiment of the invention, where TiO2 particles are mixed with the encapsulant. FIG. 7 is a graph of the light power output of the LED of FIG. 5 showing the improvement of power output with an increase in the amount of TiO2 in the encapsulant. FIG. 8 is a front view of a camera, having a flash in accordance with one embodiment of the invention, where TiO2 particles are mixed with the encapsulant. Elements that are similar or identical in the various figures are labeled with the same numeral. DETAILED DESCRIPTION Although the invention can be applied to any type of LED, one particular LED will be described in detail that is used in all examples. FIG. 1 is a cross-sectional view of a conventional white light LED 10 encapsulated in silicone. The active layer of the LED 10 in the example generates blue light. The LED 10 is formed on a starting growth substrate, such as sapphire, SiC, or GaN. Generally, an n-layer 12 is grown followed by an active layer 14, followed by a p-layer 16. The p-layer 16 is etched to expose a portion of the underlying n-layer 12. Reflective metal electrodes 18 (e.g., silver, aluminum, or an alloy) are then formed over the surface of the LED to contact the n and p layers. There may be many distributed electrodes to more evenly spread the current. When the diode is forward biased, the active layer 14 emits light whose wavelength is determined by the composition of the active layer (e.g., AlInGaN). Forming such LEDs is well known and need not be described in further detail. Additional detail of forming LEDs is described in U.S. Pat. No. 6,828,596 to Steigerwald et al. and U.S. Pat. No. 6,876,008 to Bhat et al., both assigned to the present assignee and incorporated herein by reference. The semiconductor LED is then mounted on a submount 22 as a flip chip. The top surface of submount 22 contains metal electrodes that are soldered or ultrasonically welded to the metal electrodes 18 on the LED via solder balls. Other types of bonding can also be used. The solder balls may be deleted if the electrodes themselves can be ultrasonically welded together. The submount electrodes are electrically connected by vias to cathode and anode pads 24 on the bottom of the submount so the submount can be surface mounted to metal pads on a printed circuit board, which typically forms part of the flash module for a camera. Metal traces on the circuit board electrically couple the pads to a power supply. The submount 22 may be formed of any suitable material, such as ceramic, silicon, aluminum, etc. If the submount material is conductive, an insulating layer is formed over the substrate material, and the metal electrode pattern is formed over the insulating layer. The submount 22 acts as a mechanical support, provides an electrical interface between the delicate n and p electrodes on the LED chip and a power supply, and provides heat sinking. Submounts are well known. To cause the LED 10 to have a low profile and to prevent light from being absorbed by the growth substrate, the growth substrate is removed, such as by CMP or using a laser lift-off method, where a laser heats the interface of the GaN and growth substrate to create a high-pressure gas that pushes the substrate away from the GaN. In one embodiment, removal of the growth substrate is performed after an array of LEDs is mounted on a submount wafer and prior to the LEDs/submounts being singulated (e.g., by sawing). The final thickness of the semiconductor layers may be about 40 microns. The LED layers plus submount may be about 0.5 mm thick. Processing of the LED semiconductor layers may occur before or after the LED is mounted on the submount 22. After the growth substrate is removed, a phosphor layer 30 is formed over the top of the LED for wavelength-converting the blue light emitted from the active layer 14. The phosphor layer 30 may be spray deposited, spun-on, thin-film deposited by electrophoresis, preformed as a ceramic plate and affixed to the top of the LED layers, or formed using any other technique. The phosphor layer 30 may be phosphor particles in a transparent or translucent binder, which may be organic or inorganic, or may be sintered phosphor particles. The light emitted by the phosphor layer 30, when mixed with blue light, creates white light or another desired color. In the example, the phosphor is a yttrium aluminum oxide garnet (YAG) phosphor that produces yellow light (Y+B=white). The phosphor may be any other phosphor or combination of phosphors, such as a red phosphor and a green phosphor (R+G+B=white), to create white light. The thickness of the phosphor layer 30 in all examples may be about 20 microns. With a YAG phosphor (i.e., Ce:YAG), the color temperature of the white light depends largely on the Ce doping in the phosphor as well as the thickness of the phosphor layer 30. A silicone encapsulant 32 is then formed over the LED structure to protect the LED and to increase light extraction. In one embodiment, the encapsulant is spun on. In another embodiment, the encapsulant is molded directly over the LED and phosphor. If it is desired to use the encapsulant as a lens, the encapsulant may be shaped using a mold. The prior art LED structure of FIG. 1 is used as a baseline to show the improved characteristics of the structure when employing the present invention. FIG. 2 is a cross-sectional view of an LED structure which is identical to that of FIG. 1 but where TiO2 particles 34 are mixed with the silicone encapsulant 32 before encapsulating the LED. The optimum quantity of TiO2 may vary anywhere between 1-10% of the weight of the silicone depending on the characteristics of the LED structure. In one embodiment, the encapsulant containing the TiO2 is spun on. In another embodiment, the encapsulant containing the TiO2 is molded directly over the LED and phosphor. If it is desired to use the encapsulant as a lens, the encapsulant may be shaped using a mold. In one embodiment, the average TiO2 particle size is 0.25 micron, and the particles are randomly shaped. In a typical embodiment, the thickness of the silicone is about 100 microns. As the weight percentage of the TiO2 is increased to about 5%, the light output of the LED structure increases. In some experiments, the light output diminished after 5%. In one experiment, the light output of the sample was 90 lumens with 0% TiO2, 96 lumens with 5% TiO2, and 93 lumens with 7% TiO2, with the light output lowering thereafter with increasing amounts of TiO2. The color temperature (CCT) also changed with the percentage of TiO2. In one experiment, the CCT was 5815 K with 0% TiO2, 5332 K with 5% TiO2, and 5486 K with 7% TiO2, evidencing that the CCT was lowest at the highest efficiency percentage of TiO2. In another experiment, the light output of the sample was 145 lumens with 0% TiO2, rising to 154 lumens with only 1% TiO2, which is a 6% increase in light output. In another experiment, a significant increase in light output was seen with only 0.5% TiO2. In another experiment, the light output increased 6% with 5% TiO2. The optimum amount of TiO2 may be determined empirically for each type of LED, the materials used, and the application. FIG. 3 is a graph illustrating the change in color appearance of the LED structure of FIG. 2 in its off state plotted using the CIE xy chromaticity system (1931 version). The phosphor is a YAG phosphor. The heated black body curve, also called the Planckian locus, is also shown as a reference, where the coordinate 0.32, 0.33 corresponds to a color temperature of about 5500-6000 K. The LED color becomes generally more yellow-green as the x and y values increase together toward the bulk phosphor color value of 0.42, 0.54 (not plotted). When a thin layer of the phosphor (e.g., about 20 microns) is formed over the LED die and the LED is encapsulated with pure silicone (about 100 microns thick) having 0% TiO2, as shown in FIG. 1, the appearance of the LED (e.g., the flash in a camera) in its off state is a yellow-green color, although less yellow-green than the bulk phosphor. When the encapsulant is mixed with 5% TiO2, the flash is substantially white. When the encapsulant is mixed with 7% TiO2, the flash is even whiter (further away from yellow-green). Although, at the time of filing this disclosure, the inventors are still analyzing the reasons for the improvement in performance, it is believed that the addition of TiO2 to the encapsulant increases the index of refraction of the encapsulant somewhat and that the color of the TiO2 (white) causes the appearance of the LED/phosphor to be closer to pure white. FIG. 4 is a graph of the color temperature of the LED structure of FIG. 2 over a viewing angle of −90 degrees to +90 degrees when the LED is on. The graph illustrates how the color temperature (CCT) of the LED structure of FIG. 2, in its on state, non-linearly varies with the amount of TiO2 added. The desirable lowering of the color deviation over the viewing angle is minimum (about 150 K) for 5% TiO2. This is advantageous for photography since the entire field being photographed is illuminated with substantially the same color flash. The 0% TiO2 plot has very significant deviation, which is about three times the deviation using 5% TiO2. It is believed that the TiO2 particles scatter the light from the LED, which helps to mix the light output to create a more uniform brightness and color over the viewing field. Instead of TiO2, other whitish inert particles such as ZrO2 may also be used. Although the invention is particularly desirable for use with LED flashes, since one effect of the TiO2 particles is to whiten the appearance of the yellow-green YAG phosphor over the LED die, the invention also improves the overall light output of LEDs not using a phosphor coating. The effect of the TiO2 in the encapsulant also effectively filters out significant color variations across the LED package, where the viewing angle is normal to the LED surface. FIG. 5 is a graph approximating actual experimental results, where the color temperature across an LED package (approximately 3 mm across) was measured. The measurements were taken on an LED having no TiO2 in the encapsulant and on a similar LED having TiO2 in the encapsulant. The encapsulant formed an overmolded hemispherical lens over the LED. The LED was a blue LED with a phosphor plate affixed to the top of the LED chip, where the phosphor in combination with the blue light leaking through generated an orange emission. The phosphor plate did not cover the edges of the LED layers. As seen in the graph of FIG. 5, near the left edge of the LED without the TiO2 in the encapsulant, there is a color temperature spike due to the unconverted blue light from the edge of the LED being emitted. The right side has a less severe increase in color temperature near the edge of the LED. Had the LED been used in a flashlight or projector where optics greatly enlarge the LED image, the blue color near the edge would be visible in the projected image. In contrast, as seen in the measurement of the color temperature of the LED with the TiO2 in the encapsulant, there is no significant spike in color temperature near the edge of the LED since the TiO2 effectively filters out any spikes. FIG. 6 is a cross-sectional view of an LED die, without a phosphor layer, with TiO2 particles 32 mixed with the silicone encapsulant 32. The LED die emits blue light. All aspects of the LED except for the phosphor layer are identical to FIG. 2. In the graph of FIG. 7, the square data points represent the light output power (in mW) of the LED structure of FIG. 6 versus the percentage of TiO2 in the encapsulant at 1000 mA driving current. The circles are reference data points showing the light output power of the LED die without an encapsulant. The data point at 0% is estimated; the other data points were measured. As seen, incorporating TiO2 particles in the encapsulant over the bare LED die significantly increases the light output power of the LED, even when the amount of TiO2 is about 0.5%. FIG. 8 is a representation of a camera 40, which may be a cell phone camera, using the invention described herein. The flash module 42 comprises three blue emission LEDs 44, for increased light power output, mounted on a single submount, which is mounted on a circuit board. A YAG phosphor layer covers the LEDs. An ESD protection circuit may also be mounted on the submount and covered by the phosphor. The LEDs, phosphor, and ESD circuit are encapsulated with silicone mixed with TiO2 to achieve the benefits described herein. A camera lens 48 is also shown. Tests have shown no reduced reliability of the LED structures with the addition of the inert particles in the encapsulant. An additional use of the TiO2 or ZrO2 particles in the encapsulant may be to block or reflect light by the encapsulant. By increasing the percentage of the particles over 10%, the reduction in transmission through the encapsulant becomes very significant (from 90% transmission with 0% TiO2 to 25% transmission with 10% TiO2). If the percentage of the particles keeps increasing, the encapsulant becomes more and more like a diffusing reflector, reflecting most light back into the LED and out the sides. Such a side-emitting LED is useful in certain applications such as LCD backlights. In one embodiment, the percentage of the particles exceeds 25% to create a substantially side-emitting LED. Having described the invention in detail, those skilled in the art will appreciate that given the present disclosure, modifications may be made to the invention without departing from the spirit and inventive concepts described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.	H	67H01	185H01L	33	00
11860125	US20090081831A1-20090326	WARPAGE CONTROL USING A PACKAGE CARRIER ASSEMBLY	ACCEPTED	20090311	20090326	[]	H01L2156	["H01L2156"]	7803662	20070924	20100928	438	112000	58589.0	NEWTON	VALERIE	[{"inventor_name_last": "Yuan", "inventor_name_first": "Yuan", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Chopin", "inventor_name_first": "Sheila F.", "inventor_city": "Round Rock", "inventor_state": "TX", "inventor_country": "US"}]	A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing.	1. A method for curing an encapsulant surrounding integrated circuits on a strip to form a strip assembly, wherein the strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit, comprising: placing the strip assembly on a shelf; applying pressure to the strip assembly in regions of the strip assembly wherein the regions are located at one of a group consisting of along unit edges and centered between unit edges; and applying heat of sufficient temperature and for sufficient duration to cure the encapsulant while performing the step of applying pressure. 2. The method of claim 1, wherein the step of applying pressure is further characterized as applying pressure of sufficient magnitude to conform a bottom side of the strip to the shelf. 3. The method of claim 1 further comprising: removing the heat while continuing performing the step of applying pressure. 4. The method of claim 3, further comprising: terminating the step of applying pressure after the strip has reached room temperature. 5. The method of claim 3, wherein the step of removing the heat is performed at a rate sufficiently slow so that the encapsulant is relaxed in relation to the strip. 6. The method of claim 1, wherein the encapsulant has raised molded areas around the integrated circuits with lower regions between the raised molded areas, wherein the step of applying pressure comprises applying the pressure in the lower regions with springs. 7. The method of claim 6, wherein the step of applying the pressure in the lower regions with springs comprises forming piecewise continuous copper spring in regions on a pressing plate and applying the pressing plate such that the piecewise continuous copper spring is applied in the lower regions. 8. The method of claim 1, wherein the step of applying pressure comprises: providing a pressing plate; forming springs on the pressing plate aligned to regions between the integrated circuits; forming compressible layers on the pressing plate aligned to the integrated circuits; and applying the pressing plate to a top side of the strip assembly whereby the springs apply pressure to strip between the integrated circuits and to a top surface of the integrated circuits. 9. The method of claim 1, wherein the step of applying pressure is further characterized by applying pressure over the units. 10. The method of claim 9, wherein the step of applying pressure is further characterized by applying pressure over the units using a compressible layer. 11. A method of forming a strip assembly using a strip, comprising: attaching integrated circuits to the strip; applying an encapsulant over the integrated circuits; placing the strip on a shelf after the step of applying molding compound; applying pressure between the integrated circuits to conform the strip to the shelf; heating the strip after commencing the step of applying pressure until the molding compound is cured, wherein the step of applying pressure continues during the step of heating; and removing the strip from the shelf after the step of heating. 12. The method of claim 11 further comprising cooling the strip, wherein the cooling is sufficiently slow that the encapsulant is relaxed. 13. The method of claim 12, wherein the step of cooling the strip is terminated upon reaching room temperature. 14. The method of claim 12, wherein the step of applying pressure continues during the step of cooling. 15. The method of claim 12, wherein the step of applying pressure is further characterized by applying pressure over the integrated circuits, further comprising: wirebonding the integrated circuits to the strip; and solder bumping the integrated circuits to the strip. 16. A method comprising: providing a strip having integrated circuits thereon; forming an encapsulant over the integrated circuits; placing the strip on a shelf; performing a step for applying pressure to regions between the integrated circuits; and curing the encapsulant during the step for applying pressure. 17. The method of claim 16, wherein the step of performing the step for applying pressure comprises: providing a pressing plate; forming springs on the pressing plate aligned to the regions between the integrated circuits; and applying the pressing plate with the springs to the strip. 18. The method of claim 16, wherein the step of performing the step for applying pressure comprises conforming the strip to the shelf. 19. The method of claim 18, wherein the step of performing the step for applying pressure causes the strip to become planar. 20. The method of claim 18, wherein step of performing the step for applying pressure causes the strip to become non-planar.	<SOH> BACKGROUND <EOH>1. Field This disclosure relates generally to semiconductor packaging, and more specifically, to warpage control of packages using a package carrier assembly. 2. Related Art Packaged semiconductor devices are typically manufactured using various process steps, including die bonding, wire bonding, and molding. Each of these steps may be performed at a different temperature. For example, die bonding may be performed at a temperature ranging between 125 to 150 degrees Centigrade, wire bonding may be performed at a temperature ranging between 175 to 200 degrees Centigrade, and molding may be performed at a temperature ranging between 175 to 200 degrees Centigrade. When package strips, particularly, thin package strips are subjected to these temperature variations at the different processing stages, the package strips can become warped during the post mold cure stage because of mismatches in the coefficient of thermal expansion (CTE) of the various materials used to create the package strips. Warped package strips can create several problems. For example, warped package strips can get jammed in the magazine that may be used to load or off-load the package strips into various processing stations. Warped package strips may also get jammed at the on-loader and the off-loader equipment stations. Furthermore, the warped packages may cause problems with downstream processing, as well, such as ball attachment processing. In particular, solder balls may not attach to some of the individual packages on the package strip and some balls may not be formed correctly for some of the packages on the package strip. Accordingly, there is a need for warpage control using a package carrier assembly.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 shows an exemplary package strip, whose warpage may be reduced; FIG. 2 shows a cross-sectional view of the exemplary package strip of FIG. 1 ; FIG. 3 shows a cross-sectional view of a package carrier assembly used for warpage control; and FIG. 4 shows exemplary warpage control elements for use in the package carrier assembly of FIG. 3 . detailed-description description="Detailed Description" end="lead"?	BACKGROUND 1. Field This disclosure relates generally to semiconductor packaging, and more specifically, to warpage control of packages using a package carrier assembly. 2. Related Art Packaged semiconductor devices are typically manufactured using various process steps, including die bonding, wire bonding, and molding. Each of these steps may be performed at a different temperature. For example, die bonding may be performed at a temperature ranging between 125 to 150 degrees Centigrade, wire bonding may be performed at a temperature ranging between 175 to 200 degrees Centigrade, and molding may be performed at a temperature ranging between 175 to 200 degrees Centigrade. When package strips, particularly, thin package strips are subjected to these temperature variations at the different processing stages, the package strips can become warped during the post mold cure stage because of mismatches in the coefficient of thermal expansion (CTE) of the various materials used to create the package strips. Warped package strips can create several problems. For example, warped package strips can get jammed in the magazine that may be used to load or off-load the package strips into various processing stations. Warped package strips may also get jammed at the on-loader and the off-loader equipment stations. Furthermore, the warped packages may cause problems with downstream processing, as well, such as ball attachment processing. In particular, solder balls may not attach to some of the individual packages on the package strip and some balls may not be formed correctly for some of the packages on the package strip. Accordingly, there is a need for warpage control using a package carrier assembly. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 shows an exemplary package strip, whose warpage may be reduced; FIG. 2 shows a cross-sectional view of the exemplary package strip of FIG. 1; FIG. 3 shows a cross-sectional view of a package carrier assembly used for warpage control; and FIG. 4 shows exemplary warpage control elements for use in the package carrier assembly of FIG. 3. DETAILED DESCRIPTION Warpage control for package strips using a package carrier assembly is provided. Warpage experienced by package strips during post mold cure may be reduced or completely eliminated. Moreover, by integrating warpage control into the post mold cure process, minimum interference to existing workflow may be caused. In one aspect, a method for curing an encapsulant surrounding a plurality of integrated circuits on a strip to form a strip assembly, wherein the strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit is provided. The method includes placing the strip assembly on a shelf. The method further includes applying pressure to the strip assembly in regions of the strip assembly wherein the regions are located at one of a group consisting of along unit edges and centered between unit edges. The method further includes applying heat of sufficient temperature and for sufficient duration to cure the encapsulant while performing the step of applying pressure. In another aspect, a method of forming a strip assembly using a strip is provided. The method includes attaching integrated circuits to the strip. The method further includes applying an encapsulant over the integrated circuits. The method further includes placing the strip on a shelf after the step of applying encapsulant. The method further includes applying pressure between the integrated circuits to conform the strip to the shelf. The method further includes heating the strip after commencing the step of applying pressure until the molding compound is cured, wherein the step of applying pressure continues during the step of heating. The method further includes removing the strip from the shelf after the step of heating. In yet another aspect, a method including providing a strip having integrated circuits thereon is provided. The method further includes forming an encapsulant over the integrated circuits. The method further includes placing the strip on a shelf. The method further includes performing a step for applying pressure to the regions between the integrated circuits. The method further includes curing the molding compound during the step for applying pressure. FIG. 1 shows an exemplary package strip assembly 10, whose warpage may be reduced. Package strip assembly 10 may be a multi-array package including multiple devices 16, 18, and 20 in form of an array overlying a package substrate 12. Package strip assembly 10 may also be a single array package. Each device (16, 18, and 20) may include at least one integrated circuit die and may be part of a standalone packaged device after singulation. Package strip assembly 10 may include a handling region 14. Package substrate 12 may be a laminate package substrate and may include multiple laminate layers. Package strip assembly may be a ball grid array strip assembly, a lead frame strip assembly, or any other suitable package strip assembly. Each device (16, 18, or 20) may include an integrated circuit die, which may be connected to package substrate 12. After physically attaching the integrated circuit die, the integrated circuit die may be electrically coupled to package substrate 12. Subsequently, encapsulant 17 may be formed over each integrated circuit die individually. Encapsulant 17 may be any type of encapsulant, such as a thermal set mold compound or a glob. Moreover, encapsulant 17 may encapsulate all of the integrated circuit dies located on package strip assembly 10 together, groups of integrated circuit dies together, or single integrated circuit dies. The package strip with encapsulated integrated circuit dies may be placed in a package carrier assembly for curing. Subsequent to completion of package strip assemblies, individual packages may be formed by singulating packages. Singulated packages may be leaded packages, such as quad-flat packs (QFPs), small outline integrated circuits (SOICs), power quad-flat no-lead packages (PQFNs), quad-flat no-lead packages (QFNs), ball grid arrays (BGAs), including package-on-packages (PoPs), chip-scale packages (CSPs), redistributed chip packages (RCPs), or any other suitable packages. FIG. 2 shows a cross-sectional view of the exemplary package strip assembly 10 of FIG. 1. As shown in FIG. 2, device 16 includes an integrated circuit die 28. Integrated circuit die 28 is connected to package substrate 12 via wire bonds 30. Although not shown in FIG. 2, other devices 18 and 20 may also include an integrated circuit die connected to package substrate 12 via wire bonds or solder bumps, for example. Dotted lines are shown in FIG. 2 to indicate handling region 14 and units for packaging 22, 24, and 26, which may be formed as single packages after singulation. By way of example, FIG. 2 shows edges defining a perimeter of units for packaging 22, 24, and 26 by dotted lines. Even though the mold cap shown in FIG. 2 is divided by regions along the perimeter of units, the mold cap can be made to cover the edge area between the packages. The package is formed after singulation. FIG. 3 shows a cross-sectional view of a package carrier assembly 32 used for warpage control. After molding integrated circuit dies, the molded strip package assembly may be placed in package carrier assembly 32. After placing package strip assembly 10 in package carrier assembly 32, package strip assembly 10 may be subjected to pressure in selected regions. While applying pressure to package strip assembly 10, heat may be applied to reach a sufficient temperature and for sufficient duration to ensure that the mold compound is cured. The package strip assembly 10 is then cooled down. Application of heat may be controlled at a rate sufficiently slow so that the encapsulant is relaxed in relation to package strip assembly 10. Application of pressure may be terminated after package substrate 12 has reached a desired temperature, such as room temperature. In one embodiment, package carrier assembly 32 may be implemented as a post mold cure magazine. By way of example, package carrier assembly 32 may include a housing 33. Housing 33 may include several compression assemblies 58, 60, and 62 for holding package strip assemblies, such as package strip assembly 10. Although FIG. 3 shows only three compression assemblies, package carrier assembly 32 may include a higher or a lower number of compression assemblies. Compression assembly 58 may include a fixed shelf 34. Package strip assembly 10 may be placed on fixed shelf 34. Compression assembly 58 may further include a pressing plate 36. Pressing plate 36 may be moved up or down within housing 33 to put pressure on selected regions of package strip assembly 10. Any suitable coupling of pressing plate 36 to housing 33 may be used that allows pressing plate 36 to be moved up or down and be locked in those positions. Pressing plate 36 may include several warpage control elements, such as springs attached to it that may be used to compress a package strip assembly placed on fixed shelf 34. Although FIG. 3 shows fixed shelf 34 as having a planar surface, fixed shelf 34 may have a curved surface. By way of example, pressure of sufficient magnitude may be applied to conform a bottom side of package substrate 12 to fixed shelf 34. By way of example, pressing plate 36 may include springs running in both longitudinal and transverse direction. By way of example, springs 38, 40, 42, 44 are referred to as longitudinal springs and springs 52, 54, and 56 are referred to as transverse springs. As shown in FIG. 2, devices 16, 18, and 20 are raised compared to regions between the devices. Longitudinal springs 38, 40, 42, and 44 may be used to compress regions located between devices 16, 18, and 20 in a longitudinal direction. Similarly, transverse springs 52, 54, and 56 may be used to compress regions located between devices 16, 18, and 20 in a transverse direction. In one embodiment, only the regions between devices 16, 18, and 20 are subjected to pressure by the springs. These regions may run in both the longitudinal direction and the transverse direction. In another embodiment, both the regions between devices 16, 18, and 20 and handling region 14 may be subjected to pressure by the springs. Any material with good elasticity may be used to form the springs. For example, spring copper alloy may be used to form the springs. The compressibility of longitudinal and transverse pressing elements facilitates accommodation of height differences among various integrated circuits and the roughness of the top surfaces of the integrated circuits. In one embodiment, pressure may be applied in a region between the integrated circuits by using piecewise continuous copper spring on a pressing plate and applying the pressing plate such that the piecewise continuous copper spring is applied in the region between the integrated circuits, also referred to as the lower region. In another embodiment, heat-resistant compressible material elements 46, 48, and 50 may be attached to pressing plate 36 to compress devices 16, 18, and 20, as well. By way of example, heat-resistant compressible material elements 46, 48, and 50 may be used to apply pressure to the top surface of devices 16, 18, and 20. Any compressible elastic material, such as heat-resistant foam or springs may be used to form heat-resistant compressible material elements 46, 48, and 50. The compressibility of heat-resistant compressible material elements 46, 48, and 50 makes it easy to absorb height differences among various integrated circuits and the roughness of the top surfaces of the strip or the molded packages. In one embodiment, the heat-resistant compressible material elements directly touch a top surface of the molded packages located on the package strip assembly to make the package strip assembly conform to the shelf on which it is placed. FIG. 4 shows exemplary warpage control elements for use in a package carrier assembly 32 of FIG. 3. A longitudinal spring 38 used as a warpage control spring may have the shape shown in FIG. 4. Multiple longitudinal springs may be used to compress selected portion of package strip assembly 10. Alternatively, longitudinal spring 138 used as a warpage control spring may have the shape shown in FIG. 4. Instead of a spring, a structure 238 made of heat-resistant compressible material, such as heat-resistant foam may be used. By way of example, heat-resistant compressible structure 256 may be formed as shown in FIG. 4. Heat-resistant compressible structure 256 may be used in lieu of compressible material element 48 (FIG. 2). Heat-resistant compressive structure 256 may include a housing 260. Housing 260 may further include a heat-resistant compressible material element 258. Although FIG. 4 shows specific structures for the various elements used for warpage control, other structures may be used consistent with other embodiments of the invention. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.	H	67H01	185H01L	21	56
11683023	US20070232034A1-20071004	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE	ACCEPTED	20070920	20071004	[]	H01L2120	["H01L2120"]	7514306	20070307	20090407	438	584000	97291.0	PARKER	JOHN	[{"inventor_name_last": "UTSUNOMIYA", "inventor_name_first": "Sumio", "inventor_city": "Suwa-shi", "inventor_state": "", "inventor_country": "JP"}]	A method for manufacturing a semiconductor device, includes: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof; and c) adding the metal element to at least a vicinity of a surface of the amorphous semiconductor film to enhance recrystallization of a semiconductor.	1. A method for manufacturing a semiconductor device, comprising: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof; and c) adding the metal element to at least a vicinity of a surface of the amorphous semiconductor film to enhance re-crystallization of a semiconductor. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising: d) modifying the amorphous semiconductor film into a polycrystalline semiconductor film by heating the amorphous semiconductor film with the metal element added. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the mixed gas is a gas having a hydrogen gas and an oxygen gas mixed with a ratio of nearly two to one. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the metal element is nickel. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the member is net-shaped. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the step d) includes; spraying a combusted gas onto the amorphous semiconductor film. 7. The method for manufacturing a semiconductor device according to claim 1, further comprising: e) forming a semiconductor oxide film containing the metal element by oxidizing a surface of the polycrystalline semiconductor film with the metal element added; and f) selectively removing the semiconductor oxide film. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the step e) includes; spraying a combusted gas onto the amorphous semiconductor film. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the combusted gas is a gas obtained by mixing and combusting a hydrogen gas and an oxygen gas in such a ratio that the oxygen gas is greater than one-half of the hydrogen gas. 10. The method for manufacturing a semiconductor device according to claim 1, wherein a direction of spraying the combusted gas is substantially identical to a gravitational direction. 11. The method for manufacturing a semiconductor device according to claim 1, wherein the combusted gas is sprayed substantially evenly within a long square having a length in a longitudinal direction greater than a width of the substrate on a surface perpendicular to a spraying direction, the substrate being located on the surface, the substrate and the combusted gas moving relatively to each other at constant speed. 12. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor is silicon.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field Several aspects of the present invention relate to a method for manufacturing a semiconductor thin film and a semiconductor device using the semiconductor thin film. 2. Related Art In displays of forming images using a thin film transistor (hereinafter referred to as a “TFT”) as the switching element, such as liquid crystal displays, achieving higher performance of TFT is demanded. Higher performance can be achieved by what has been referred to as a polysilicon TFT, which uses polycrystalline silicon for the active layer. For the purpose of reducing cost of displays, a method of recrystallizing (modifying) an amorphous silicon layer deposited on a low-cost glass substrate at temperatures equal to or less than the strain point of the glass substrate is generally used. JP-A-9-293687, a first example of related art, discloses a laser annealing method where an amorphous silicon layer is melt and re-crystallized by laser annealing as a technique of recrystallizing an amorphous silicon layer at low temperature. JP-A-9-156916, a second example of related art, discloses a method where a metal element is added onto an amorphous silicon layer to decrease the temperature required for re-crystallization by a chemical vapor deposition (CVD) apparatus using electrodes made of a material containing a metal element to facilitate crystallization of silicon. However, the above-mentioned two methods involve the following problems. In the former, cost reduction is difficult because laser oscillators are expensive. In the latter, achieving higher performance of TFT is difficult, not only because the device is expensive but also because a metal element remaining in the recrystallized silicon film decreases mobility in a silicon film.	<SOH> SUMMARY <EOH>A method for manufacturing a semiconductor device according to one aspect of the invention includes adding a metal element to enhance recrystallization of a semiconductor to at least a vicinity of a surface of an amorphous semiconductor film by spraying a combusted gas onto a member containing the metal element and then onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof, the combusted gas being obtained by combustion of a mixed gas, the mixed gas at least including a gas containing a hydrogen atom and an oxygen gas. According to the above-mentioned method, the combusted gas comes to contain the above-mentioned metal element in the form of hydroxide by being sprayed onto the above-mentioned member. The hydroxide is dissolved into water vapor, and is carried along the flow of the water vapor to the surface of an amorphous semiconductor film. As a result, a metal element to enhance crystallization of a semiconductor is added to at least the vicinity of the surface of the above-mentioned amorphous semiconductor film to reduce the temperature and heating time required to modify (crystallize) the amorphous semiconductor film into a polycrystalline semiconductor film by heating. This manufacturing method therefore enables formation of a polycrystalline semiconductor film on a substrate made of a material having a low strain point such as glass, allowing formation of a semiconductor device on a large-area substrate at low cost. The method for manufacturing a semiconductor device according to one aspect of the invention is a method for manufacturing a semiconductor device including the above-mentioned first step, the method further including, after the above-mentioned first step, a second step for modifying the above-mentioned amorphous semiconductor film to be a polycrystalline semiconductor film by heating the above-mentioned amorphous semiconductor film with the above-mentioned metal element added. In the above-mentioned first step, a flame is sprayed onto an amorphous semiconductor film, and therefore modification into a polycrystalline semiconductor film slightly proceeds. However, addition of a metal element differs from modification into a polycrystalline semiconductor film in terms of required conditions such as the temperature of a flame. Therefore, by performing separately the step for modifying an amorphous semiconductor film into a polycrystalline semiconductor film by heating as the second step, the step for adding a metal element and the step for modifying an amorphous semiconductor film can each be practiced under the optimum conditions. Preferably, the above-mentioned mixed gas is a gas having a hydrogen gas and an oxygen gas mixed with a ratio of nearly two to one. This structure causes most components of the combusted gas obtained by combustion of the above-mentioned mixed gas to become water vapor, allowing efficient addition of a metal element. Therefore, the amount of the above-mentioned mixed gas supplied can be reduced, thereby controlling the temperature increase of the above-mentioned substrate and the substrate deformation due to the temperature increase. Preferably, the above-mentioned metal element is nickel. Nickel has a particularly high effect to enhance crystallization of a semiconductor. Therefore, this structure can reduce the temperature in crystallizing the above-mentioned amorphous semiconductor film, thereby controlling the temperature increase of the above-mentioned substrate and the substrate deformation due to the temperature increase. Preferably, the above-mentioned member is net-shaped. Making the above-mentioned member net-shaped allows a combusted gas to be sprayed through the net-shaped member onto an amorphous semiconductor film. The net-shaped member allows increase of the contact area between the combusted gas and the above-mentioned member without blocking the flow of the combusted gas. This manufacturing method thus allows efficient addition of a metal element to an amorphous semiconductor film, and further allows formation of a large-area polycrystalline semiconductor film at low cost. Preferably, the above-mentioned second step is a step for spraying a combusted gas onto the above-mentioned amorphous semiconductor film. The above-mentioned first step is a step for spraying a combusted gas onto an amorphous semiconductor film. This manufacturing method enables the above-mentioned first and second steps to be continuously performed using the same or a similar device. As a result, a large-area polycrystalline semiconductor film can be obtained at low cost. Preferably, the above-mentioned manufacturing method further includes a third step for forming a semiconductor oxide film containing the above-mentioned metal element by oxidizing the surface of the polycrystalline semiconductor film with the above-mentioned metal element added; and a fourth step for selectively removing the above-mentioned semiconductor oxide film. The above-mentioned metal element facilitates modification of an amorphous semiconductor film to a polycrystalline semiconductor film; however, manufacturing a semiconductor device using a polycrystalline semiconductor film obtained by the modification has adverse effects such as decreased mobility. The above-mentioned metal element remains in the modified polycrystalline semiconductor film, and the remaining concentration increases as the location approaches the surface of the film. On the other hand, a semiconductor oxide film can be selectively etched with respect to the polycrystalline semiconductor film. Accordingly, the surface of the modified polycrystalline semiconductor film is oxidized to form a semiconductor oxide film, and thereafter the semiconductor oxide film is selectively etched, allowing a polycrystalline semiconductor film containing the above-mentioned metal element to a lesser extent to be left on the substrate. This manufacturing method thus enables formation of a semiconductor device with high performance and reliability on a large-area substrate at low cost. Preferably, the above-mentioned third step is a step for spraying a combusted gas onto the above-mentioned amorphous semiconductor film. The above-mentioned first step is a step for spraying a combusted gas onto an amorphous semiconductor film, and the above-mentioned second step is practicable by spraying a combusted gas onto an amorphous semiconductor film. This manufacturing method enables the above-mentioned first and third steps or the above-mentioned first to third steps to be continuously performed using the same or a similar device. As a result, a large-area polycrystalline semiconductor film can be obtained at low cost. Preferably, the above-mentioned combusted gas is a gas obtained by combusting a hydrogen gas and an oxygen gas mixed with a ratio of the oxygen gas to the hydrogen gas greater than one half. Combusting a gas having a hydrogen gas and an oxygen gas mixed with the above ratio generates oxygen radical simultaneously with water vapor, causing improved oxidation rate. This manufacturing method therefore allows surface oxidation of the above-mentioned polycrystalline semiconductor film at further lower temperature for a short time period, and allows distortion of the above-mentioned substrate to be controlled. Preferably, the direction of spraying the above-mentioned combusted gas is substantially identical to the gravitational direction. This manufacturing method allows the above-mentioned combusted gas to be sprayed with a substrate having an amorphous semiconductor film formed thereon mounted on a plane surface. As compared to a manner of spraying a combusted gas from another direction, a mechanism for holding and transferring a substrate can be simplified, allowing formation of a large-area polycrystalline semiconductor film at further low cost. Preferably, the above-mentioned combusted gas is sprayed substantially evenly within a long square having a length in the longitudinal direction greater than a width of the substrate on a surface perpendicular to the spraying direction, the above-mentioned substrate being located on the surface, the substrate and the combusted gas moving relatively to each other at constant speed. This manufacturing method allows scanning of the substrate surface at constant speed with a combusted gas distributing in a curtain shape, thereby spraying the combusted gas evenly over the entire surface of the substrate. This therefore allows formation of a further even polycrystalline semiconductor film on a large-area substrate. Preferably, the above-mentioned semiconductor is silicon. A semiconductor device using silicon, which is generally used as a device for driving of a display, can be formed on a large-area substrate at low cost. BRFSUM description="Brief Summary" end="tail"?	BACKGROUND OF THE INVENTION 1. Technical Field Several aspects of the present invention relate to a method for manufacturing a semiconductor thin film and a semiconductor device using the semiconductor thin film. 2. Related Art In displays of forming images using a thin film transistor (hereinafter referred to as a “TFT”) as the switching element, such as liquid crystal displays, achieving higher performance of TFT is demanded. Higher performance can be achieved by what has been referred to as a polysilicon TFT, which uses polycrystalline silicon for the active layer. For the purpose of reducing cost of displays, a method of recrystallizing (modifying) an amorphous silicon layer deposited on a low-cost glass substrate at temperatures equal to or less than the strain point of the glass substrate is generally used. JP-A-9-293687, a first example of related art, discloses a laser annealing method where an amorphous silicon layer is melt and re-crystallized by laser annealing as a technique of recrystallizing an amorphous silicon layer at low temperature. JP-A-9-156916, a second example of related art, discloses a method where a metal element is added onto an amorphous silicon layer to decrease the temperature required for re-crystallization by a chemical vapor deposition (CVD) apparatus using electrodes made of a material containing a metal element to facilitate crystallization of silicon. However, the above-mentioned two methods involve the following problems. In the former, cost reduction is difficult because laser oscillators are expensive. In the latter, achieving higher performance of TFT is difficult, not only because the device is expensive but also because a metal element remaining in the recrystallized silicon film decreases mobility in a silicon film. SUMMARY A method for manufacturing a semiconductor device according to one aspect of the invention includes adding a metal element to enhance recrystallization of a semiconductor to at least a vicinity of a surface of an amorphous semiconductor film by spraying a combusted gas onto a member containing the metal element and then onto the amorphous semiconductor film placed on a substrate having an insulating surface thereof, the combusted gas being obtained by combustion of a mixed gas, the mixed gas at least including a gas containing a hydrogen atom and an oxygen gas. According to the above-mentioned method, the combusted gas comes to contain the above-mentioned metal element in the form of hydroxide by being sprayed onto the above-mentioned member. The hydroxide is dissolved into water vapor, and is carried along the flow of the water vapor to the surface of an amorphous semiconductor film. As a result, a metal element to enhance crystallization of a semiconductor is added to at least the vicinity of the surface of the above-mentioned amorphous semiconductor film to reduce the temperature and heating time required to modify (crystallize) the amorphous semiconductor film into a polycrystalline semiconductor film by heating. This manufacturing method therefore enables formation of a polycrystalline semiconductor film on a substrate made of a material having a low strain point such as glass, allowing formation of a semiconductor device on a large-area substrate at low cost. The method for manufacturing a semiconductor device according to one aspect of the invention is a method for manufacturing a semiconductor device including the above-mentioned first step, the method further including, after the above-mentioned first step, a second step for modifying the above-mentioned amorphous semiconductor film to be a polycrystalline semiconductor film by heating the above-mentioned amorphous semiconductor film with the above-mentioned metal element added. In the above-mentioned first step, a flame is sprayed onto an amorphous semiconductor film, and therefore modification into a polycrystalline semiconductor film slightly proceeds. However, addition of a metal element differs from modification into a polycrystalline semiconductor film in terms of required conditions such as the temperature of a flame. Therefore, by performing separately the step for modifying an amorphous semiconductor film into a polycrystalline semiconductor film by heating as the second step, the step for adding a metal element and the step for modifying an amorphous semiconductor film can each be practiced under the optimum conditions. Preferably, the above-mentioned mixed gas is a gas having a hydrogen gas and an oxygen gas mixed with a ratio of nearly two to one. This structure causes most components of the combusted gas obtained by combustion of the above-mentioned mixed gas to become water vapor, allowing efficient addition of a metal element. Therefore, the amount of the above-mentioned mixed gas supplied can be reduced, thereby controlling the temperature increase of the above-mentioned substrate and the substrate deformation due to the temperature increase. Preferably, the above-mentioned metal element is nickel. Nickel has a particularly high effect to enhance crystallization of a semiconductor. Therefore, this structure can reduce the temperature in crystallizing the above-mentioned amorphous semiconductor film, thereby controlling the temperature increase of the above-mentioned substrate and the substrate deformation due to the temperature increase. Preferably, the above-mentioned member is net-shaped. Making the above-mentioned member net-shaped allows a combusted gas to be sprayed through the net-shaped member onto an amorphous semiconductor film. The net-shaped member allows increase of the contact area between the combusted gas and the above-mentioned member without blocking the flow of the combusted gas. This manufacturing method thus allows efficient addition of a metal element to an amorphous semiconductor film, and further allows formation of a large-area polycrystalline semiconductor film at low cost. Preferably, the above-mentioned second step is a step for spraying a combusted gas onto the above-mentioned amorphous semiconductor film. The above-mentioned first step is a step for spraying a combusted gas onto an amorphous semiconductor film. This manufacturing method enables the above-mentioned first and second steps to be continuously performed using the same or a similar device. As a result, a large-area polycrystalline semiconductor film can be obtained at low cost. Preferably, the above-mentioned manufacturing method further includes a third step for forming a semiconductor oxide film containing the above-mentioned metal element by oxidizing the surface of the polycrystalline semiconductor film with the above-mentioned metal element added; and a fourth step for selectively removing the above-mentioned semiconductor oxide film. The above-mentioned metal element facilitates modification of an amorphous semiconductor film to a polycrystalline semiconductor film; however, manufacturing a semiconductor device using a polycrystalline semiconductor film obtained by the modification has adverse effects such as decreased mobility. The above-mentioned metal element remains in the modified polycrystalline semiconductor film, and the remaining concentration increases as the location approaches the surface of the film. On the other hand, a semiconductor oxide film can be selectively etched with respect to the polycrystalline semiconductor film. Accordingly, the surface of the modified polycrystalline semiconductor film is oxidized to form a semiconductor oxide film, and thereafter the semiconductor oxide film is selectively etched, allowing a polycrystalline semiconductor film containing the above-mentioned metal element to a lesser extent to be left on the substrate. This manufacturing method thus enables formation of a semiconductor device with high performance and reliability on a large-area substrate at low cost. Preferably, the above-mentioned third step is a step for spraying a combusted gas onto the above-mentioned amorphous semiconductor film. The above-mentioned first step is a step for spraying a combusted gas onto an amorphous semiconductor film, and the above-mentioned second step is practicable by spraying a combusted gas onto an amorphous semiconductor film. This manufacturing method enables the above-mentioned first and third steps or the above-mentioned first to third steps to be continuously performed using the same or a similar device. As a result, a large-area polycrystalline semiconductor film can be obtained at low cost. Preferably, the above-mentioned combusted gas is a gas obtained by combusting a hydrogen gas and an oxygen gas mixed with a ratio of the oxygen gas to the hydrogen gas greater than one half. Combusting a gas having a hydrogen gas and an oxygen gas mixed with the above ratio generates oxygen radical simultaneously with water vapor, causing improved oxidation rate. This manufacturing method therefore allows surface oxidation of the above-mentioned polycrystalline semiconductor film at further lower temperature for a short time period, and allows distortion of the above-mentioned substrate to be controlled. Preferably, the direction of spraying the above-mentioned combusted gas is substantially identical to the gravitational direction. This manufacturing method allows the above-mentioned combusted gas to be sprayed with a substrate having an amorphous semiconductor film formed thereon mounted on a plane surface. As compared to a manner of spraying a combusted gas from another direction, a mechanism for holding and transferring a substrate can be simplified, allowing formation of a large-area polycrystalline semiconductor film at further low cost. Preferably, the above-mentioned combusted gas is sprayed substantially evenly within a long square having a length in the longitudinal direction greater than a width of the substrate on a surface perpendicular to the spraying direction, the above-mentioned substrate being located on the surface, the substrate and the combusted gas moving relatively to each other at constant speed. This manufacturing method allows scanning of the substrate surface at constant speed with a combusted gas distributing in a curtain shape, thereby spraying the combusted gas evenly over the entire surface of the substrate. This therefore allows formation of a further even polycrystalline semiconductor film on a large-area substrate. Preferably, the above-mentioned semiconductor is silicon. A semiconductor device using silicon, which is generally used as a device for driving of a display, can be formed on a large-area substrate at low cost. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements. FIG. 1 is a diagram showing a gas burner used in embodiments. FIG. 2 is a diagram showing the outline of a heating device using the gas burner. FIGS. 3A to 3C are diagrams showing a first embodiment of the invention. FIG. 4 is a diagram showing the first embodiment of the invention. FIG. 5 is a diagram showing the first embodiment of the invention. FIG. 6 is a diagram showing a second embodiment of the invention. FIG. 7 is a diagram showing a third embodiment of the invention. FIG. 8 is a diagram showing a fourth embodiment of the invention. FIGS. 9A to 9D are diagrams showing a method for manufacturing a semiconductor device. DESCRIPTION OF EXEMPLARY EMBODIMENTS Embodiments in which the invention is practiced will be described below. The embodiments of the invention are characterized in that a combusted gas (hereinafter referred to as a “flame”) obtained by combusting a mixed gas is sprayed on a substrate. Referring to FIGS. 1 and 2, the outline of a gas burner used in the embodiments, and the outline of a heating device including the gas burner, a holding base that holds a substrate, and the like will now be described. FIG. 1 is a diagram showing the outline of a gas burner used in the embodiments. A gas burner 1 includes an enclosure 10, a first gas supply source 102 that supplies an oxygen gas, a second gas supply source 104 that supplies a hydrogen gas, a first pipe 106 that introduces the oxygen gas into the enclosure 10, a second pipe 108 that introduces the hydrogen gas into the enclosure 10, and a gas controller 110 that can adjust the gas weight flow. The enclosure 10 includes, in the inside thereof, an igniter, which is not shown, and a combustion chamber, which is not shown, for combusting a mixed gas of hydrogen and oxygen. A plurality of nozzles 12 are also included that blow off flames obtained by combusting the mixed gas in one direction. The shapes of the nozzles 12 are identical, so that the shapes of flames blown off from the nozzles 12 are substantially identical to one another. Placing nozzles 12 lineally at regular intervals therefore allows the flames to make the shape of a curtain, that is, the shape of a long square on a plane surface perpendicular to the direction of the flame blown off. The gas controller 110 can arbitrarily adjust the shape and temperature of a flame 14 by adjusting the gas weight flow. By changing the flow ratio between hydrogen gas and oxygen gas, the flame 14 can be composed of water vapor and an oxygen gas (specifically radicalized oxygen atoms), for example, instead of water vapor alone. Connecting three or more gas supply sources and combusting a gas other than a hydrogen gas can also be used. FIG. 2 is a diagram showing the outline of a heating device using the above-described gas burner. The heating device 2 includes the gas burner 1, a metal member 24, which is produced by forming in a net shape a member made of metal that enhances crystallization of a semiconductor, (hereinafter referred to as a “net”), a net holder 25 that can hold the net 24 between the nozzles 12 and the substrate 20, and a substrate holding base 26 movable in the arrow direction at constant speed while holding the substrate 20 having an amorphous silicon film 22, as an amorphous semiconductor film, formed on the surface thereof. If a mixed gas is combusted while the net 24 is held, the flame 14 is sprayed through the net 24 onto the amorphous silicon film 22 formed on the surface of the substrate 20. By passing through the net 24, the flame 14 is sprayed onto the net 24 made of metal that enhances crystallization of a semiconductor, and then onto the amorphous semiconductor film 22. Note that some components such as the gas controller 110 are omitted in FIG. 2. As shown, the width of the gas burner 1 (the length in the direction perpendicular to the arrow direction or the gravitational direction in the drawing) is sufficiently larger than that of the substrate 20, so that the flames 14 can be sprayed evenly in the width direction of the substrate 20. Moving the substrate holding base 26, which holds the substrate 20 at constant speed, enables the flames 14 to be sprayed evenly onto the entire surface of the substrate 20. While only one gas burner 1 is shown in FIG. 2, a plurality of gas burners 1 may be provided in the arrow direction, allowing the flame 14 to be sprayed a plurality of times per movement of the substrate 20. Without the net 24, the flame 14 may also be sprayed onto the amorphous semiconductor film 22 not through the net 24 by moving the substrate 20. Embodiments in which the invention is practiced will now be described with reference to the accompanying drawings. In the embodiments described later, silicon is used as a semiconductor, and nickel is used as a metal element to facilitate crystallization of silicon as the semiconductor. First Embodiment FIGS. 3A to 3C, 4 and 5 are diagrams showing a first embodiment of the invention. The diagrams show a manner in which an amorphous silicon film formed on the substrate made of glass such as barium borosilicate glass or aluminoborosilicate glass (hereinafter referred to as “substrate”) is crystallized to be modified into a polycrystalline silicon film. FIG. 3A is a diagram showing a manner of a first step, that is, a step for adding a metal element that facilitates crystallization of a semiconductor to the vicinity of the surface of an amorphous semiconductor film. The substrate 20 having the amorphous silicon film 22 formed on the surface thereof is held on the substrate holding base 26 that moves in the direction of arrow in the diagram at constant speed. A first gas burner 31 is provided above the substrate holding base 26. A hydrogen gas and an oxygen gas are supplied from a gas supply source, which is not shown, through a pipe, which is not shown, to the first gas burner 31, and are combusted inside the enclosure 10 to be converted into water vapor. The net 24 made of nickel is provided between the first gas burner 31 and the substrate holding base 26. The flame 14 blown off downwards (in the gravitational direction) from the nozzle 12 by combustion impinges on the net 24, and then is sprayed onto the amorphous silicon film 22. When the flame 14 is sprayed, nickel is converted into nickel hydroxide through reaction represented by the following formula (1). Ni+2H2O→Ni(OH)2+H2 (1) Nickel hydroxide is dissolved in water vapor contained in the flame 14, and is carried to the surface of the amorphous silicon film 22 and is added to the surface. Here, the above-mentioned nickel hydroxide is not implanted into the amorphous silicon film 22 in such a manner as ion implantation method, and therefore does not deeply penetrate into the inside of the amorphous silicon film 22. Accordingly, the nickel element is distributed such that its concentration is high at the surface of the amorphous silicon film 22 and dramatically decreases as the location moves inwards (in the direction towards the interface with the substrate 20). The addition of nickel hydroxide causes the amorphous silicon film 22 in a state where crystallization proceeds easily and hence the film is modified into a polycrystalline silicon film 28 in the following second step (refer to FIG. 3B). In FIG. 3A, one first gas burner 31 and one net 24 are provided; however, embodiments of the first step are not limited to this manner. The plurality of nets 24 may be provided for each gas burner 1 such that they are placed one atop another or apart from one another. The plurality of first gas burners 31 may be placed in parallel such that the flame 14 is sprayed onto the substrate 20 a plurality of times. However, the number of gas burners and the temperature of the substrate 20 naturally affect the temperature of the flame 14, and the movement speed of the substrate holding base 26 also affects the temperature of the substrate 20 during operation. Accordingly, the setting conditions depend on heat resistance of the substrate 20. Corning 7059 glass used for liquid crystal displays and the like, for example, has a strain point of 593 degrees Celsius, and therefore preferably has a maximum temperature of 550 degrees Celsius or less, and more preferably a maximum temperature of 500 degrees Celsius or less. The number of gas burners is therefore preferably set within the range of temperatures of the substrate 20 not more than 500 degrees Celsius to add nickel element efficiently. While the first step is a step for adding nickel element to the amorphous silicon film 22, performing either or both of a second and a third step, which will be described later, without using the flame 14 is one of embodiments of the invention. As described above, addition of nickel element to the amorphous silicon film 22 causes the film to have properties of crystallizing at lower temperatures than the film without anything added. The film is thus crystallized at more lower temperature or for a more shorter time, if means generally used in semiconductor device manufacturing processes such as heating using a diffusion furnace, lamp annealing, laser annealing or the like is used. Hence, combining the above-described first step with conventional methods can form the polycrystalline silicon film 28 of a large area on a glass substrate at low cost. FIG. 3B is a diagram showing a manner of the second step, that is, a step for heating the amorphous silicon film 22 with nickel element added to modify the film into the polycrystalline silicon film 28. Similarly to the first step, the substrate 20 is held on the substrate holding base 26 that moves in the direction of arrow in the diagram at constant speed, and a second first gas burner 32 is provided above the substrate holding base 26. The flame 14 blown off from the second gas burner 32 heats the amorphous silicon film 22 with nickel element added, which is formed on the substrate 20. Different from the first step, no net 24 is provided. As described above, nickel element is added such that its concentration is high at the surface of the amorphous silicon film 22, and therefore modification of the surface starts at low temperature. Once part of the film is crystallized to grow a crystal grain, crystallization proceeds using the crystal grain as a seed crystal even at lower temperatures than those causing beginning crystallization. The amorphous silicon film 22 is therefore polycrystallized up to the inside where the concentration of nickel element is low, that is, the interface with the substrate 20, and thus is modified into the polycrystalline silicon film 28. In addition, the temperature of the flame 14 heating the substrate 20 depends on a glass strain point, just as in the first step. FIGS. 3C and 5 are diagrams showing a manner of the third step, that is, a step of heating the polycrystalline silicon film 28, which is obtained by modification, using the flame 14 to form an oxide film 30 at the surface of the polycrystalline silicon film 28. Similarly to the first and second steps, the substrate 20 is held on the substrate holding base 26 that moves in the direction of arrow in the diagram at constant speed, and a third gas burner 33 is provided above the substrate holding base 26. The flame 14 blown off from the nozzle 12 heats the polycrystalline silicon film 28 formed on the substrate 20, oxidizing the film from the surface to a predetermined depth to form the oxide film 30 that takes in the remaining nickel element. An enlarged diagram of the inside of a circle indicated by A in FIG. 3C is FIG. 5. The polycrystalline silicon film 28 is oxidized from the surface to a predetermined depth by water vapor and oxygen radical constituting the flame 14 to become the oxide film 30 containing nickel element. The polycrystalline silicon film 28 having a thickness less than that when formed remains underneath the oxide film 30. Since nickel element added to the amorphous silicon film 22 functions as a catalyst to enhance crystallization of silicon, the nickel element remains in the modified polycrystalline silicon film 28. Particularly in the vicinity of the surface of the film, the remaining nickel element has a high concentration. However, the nickel element remaining in the polycrystalline silicon film 28 has adverse effects such as decreased mobility as described above. Therefore, the polycrystalline silicon film 28 is initially formed on the substrate 20 in such a manner to have a film thickness equal to or larger than that required for forming a semiconductor device. The oxide film 30 that takes in the remaining nickel element described above is then formed. By selectively removing the oxide film 30 thereafter, the polycrystalline silicon film 28 that has the remaining nickel concentration within the acceptable range is obtained. FIG. 4 is a diagram showing a manner of a fourth step, that is, a step for selectively removing the oxide film 30 to expose the polycrystalline silicon film 28 underneath the oxide film 30. Hydrofluoric acid or an etchant 46 having hydrofluoric acid as its major component is injected into a liquid bath 42. The substrate 20 held by a carrier 44 made of Teflon® is immersed in the liquid bath 42, so that the oxide film 30 at the surface is selectively etched and removed. Thereafter, water washing and drying are performed thereby to obtain the polycrystalline silicon film 28 of a large area on the surface of the substrate 20. Next, required film thicknesses of the polycrystalline silicon film 28 and the oxide film 30 will be described. A concentration of about 1×1018 cm−3 or more is needed for nickel element to effectively decrease the temperature required for crystallization of silicon. If heat treatment is performed for t seconds with a layer containing nickel element of this concentration existing in the surface layer, nickel diffuses in the film thickness direction of the polycrystalline silicon film. The concentration distribution at that time can be calculated by the following equation (2). C/Co=1−erf(x/(2×(Dt)0.5)) (2) where Co is a concentration of the surface layer, X is a distance from the surface, and D is a diffusion coefficient of nickel at the heat treatment temperature. At a temperature of 500 degrees Celsius, the diffusion coefficient of nickel in silicon is about 3.5×10−14 cm2×s−1. On the other hand, given that the concentration of nickel acceptable in silicon that is an active layer of a transistor is 1×10−15 cm−3 (less than 1 ppm), C/Co<1×10−3 is required. Based on these factors, the distance from the surface of the polycrystalline silicon film that has a concentration equal to or less than the acceptable concentration is estimated to be about 50 nm, for example, if heat treatment time is 30 seconds. Accordingly, the nickel concentration of the remaining polycrystalline silicon film can be suppressed to be equal to or less than the acceptable value by applying heat treatment for 30 seconds and selectively removing, after oxidizing, the surface layer at least to a thickness of 50 nm. For example, a polycrystalline silicon film is deposited to a thickness of 100 nm and the surface layer of 50 nm is oxidized and then removed, whereby the remaining film of 50 nm can be obtained as a high-purity polycrystalline silicon film. Second Embodiment Next, a second embodiment of the invention will be described with reference to FIG. 6. This drawing is a diagram showing the state of the heating device 2 seen from the direction perpendicular to the moving direction of the substrate 20 as well as the gravitational direction, similarly to the first embodiment. As shown in FIG. 6, the first gas burner 31, the second gas burner 32 and the third gas burner 33 are placed in this order in the heating device 2. The net 24 made of nickel is placed between the first gas burner 31 and the substrate holding base 26. The steps of gas burners are the same as those in the first embodiment. Therefore, the first step for adding nickel element to the amorphous silicon film 22, the second step for crystallizing the amorphous silicon film 22 to obtain the polycrystalline silicon film 28, and the third step for oxidizing part that contains high concentration nickel element of the surface layer of the polycrystalline silicon film 28 to form the oxide film 30 can be carried out by transferring the substrate 20 one time. The step and device for etching and removing the oxide film 30 formed in the third step are needed separately. By the method used in the first embodiment of immersing the substrate 20 in the etchant 46 filled in the liquid bath 42, the oxide film 30 is removed, allowing the polycrystalline silicon film 28 of a large area to be formed on the surface of the substrate 20. The layout of the three kinds of gas burners mentioned above is not limited to that at the same height as shown, but can be set according to the need for each step. The number of gas burners is not limited to one for each step, but a plurality of gas burners can be used for one step. The height and the number of the foregoing gas burners can therefore be set freely unless the temperature of the substrate 20 exceeds the glass strain point, efficiently obtaining the polycrystalline silicon film 28 of a large area. Third Embodiment Next, the third embodiment of the invention will be described with reference to FIG. 7. This drawing is a diagram showing the state of the heating device 2 seen from the direction perpendicular to the moving direction of the substrate 20 as well as the gravitational direction, similarly to the first embodiment. As shown in FIG. 7, the first gas burner 31 and the third gas burner 33 are placed in this order in the heating device 2. The net 24 made of nickel is placed between the first gas burner 31 and the substrate holding base 26. The second gas burner 32 for performing recrystallization is not provided. By using the first gas burner 31, the first step for adding nickel element to the amorphous silicon film 22 and the second step for modifying (crystallizing) the amorphous silicon film 22 to form the polycrystalline silicon film 28 are performed simultaneously. The first step and the second step are different from each other in terms of the presence of the net 24, but are identical to each other in terms of heating the amorphous silicon film 22 by using the flame 14. The amorphous silicon film 22 starts recrystallization even during addition of nickel element, if the surface temperature and the amount of nickel element added to the surface meet predetermined requirements. Therefore, by determining the amount of nickel element added in consideration of the shape of the net 24, the number of nets 24 to be placed one atop another and the like and setting the temperature of the flame 14 and the like appropriate, the amorphous silicon film 22 can be recrystallized while receiving addition of nickel element. In addition, a step for selectively etching and removing the oxide film 30 formed in the third step needs be performed separately, which is the same as in the second embodiment. Fourth Embodiment Next, the fourth embodiment of the invention will be described with reference to FIG. 8. This drawing is a diagram showing the state of the heating device 2 seen from the direction perpendicular to the moving direction of the substrate 20 as well as the gravitational direction, similarly to the first embodiment. As shown in FIG. 8, only the first gas burner 31 and the net 24 are placed in the heating device 2. By using the first gas burner 31, the first to third steps are performed simultaneously. Similarly to the first and second steps, the third step is a step for heating by blowing off the flame 14 to the substrate 20. Polycrystallization of the amorphous silicon film 22 and oxidation of the surface of the polycrystalline silicon film 28 obtained by polycrystallization have a commonality in terms of heating. Once started, polycrystallization of the amorphous silicon film 22 proceeds not so much depending on an oxide film formed on the surface. In other words, regarding the amorphous silicon film 22, recrystallization towards the interface with the substrate 20 is compatible with oxidation of the surface. Therefore, by appropriately selecting the shape of the net 24 made of nickel, the number of nets 24 to be placed one atop another and the like, and the temperature of the flame 14 and the like, and further the film thickness of the amorphous silicon film 22 formed on the substrate, the polycrystalline silicon film 28 having a film thickness required for forming a semiconductor device and having a nickel element concentration within the acceptable range can be formed on the top surface of the substrate 20 using a single gas burner. In addition, a step for etching and removing the oxide film 30 formed on the polycrystalline silicon film 28 needs be performed separately, which is the same as in the third embodiment. Semiconductor Device Next, a method of manufacturing a TFT as a semiconductor device will be described with reference to FIGS. 9A to 9D. Initially, as shown in FIG. 9A, the polycrystalline silicon film 28 formed on the substrate 20 according to one of the above-described embodiments is patterned, so that a TFT element region (island-shaped region) is formed. Next, as shown in FIG. 9B, a gate insulating film 91 is formed. For example, by a CVD method using tetraethylorthosilicate (TEOS) as the raw material, a silicon oxide film is formed to be the gate insulating film 91. Next, as shown in FIG. 9C, a metal thin film made of aluminum or the like, is formed over the entire surface of the substrate 20 by a sputtering method and then is patterned, thereby forming a gate electrode 92 above a channel region 95. Using the gate electrode 92 as a mask, impurities of high concentration are implanted into the TFT element region by an ion implantation method, thereby forming a source region 93 and a drain region 94. Finally, as shown in FIG. 9D, electrodes are formed. Specifically, a silicon oxide film is formed on the top surface of a TFT element region, forming an interlayer insulating film 96. Next, contact holes are opened in the interlayer insulating film 96 above the source region 93 and the drain region 94. An aluminum layer is formed over the entire surface of the substrate 20 by a sputtering method and the like, and thereafter is patterned, thereby forming the electrodes 97. This allows the TFT element to be electrically connected to outer circuits or other TFT elements. The above-mentioned aluminum layer may be formed after a conductive material has been embedded into the contact holes. First Modification While a substrate made of barium borosilicate glass, aluminoborosilicate glass or the like is used in the above-described embodiments, the invention is applicable to substrates made of quartz glass and the like which are highly resistant to heat. In this case, a polycrystalline silicon film can be formed using a relatively low cost device, allowing control of manufacturing cost, which is the same as in the above-described embodiments. Second Modification While an amorphous silicon film is used as a starting point to obtain a polycrystalline silicon film, a microcrystalline silicon film can be used instead of an amorphous silicon film. As in the case of using an amorphous silicon film, effects such as improvement of mobility can be obtained by recrystallizing the microcrystalline silicon film to be a polycrystalline silicon film. Third Modification While a flame is sprayed onto an amorphous silicon film through a net made of nickel in the above-described embodiments, nozzles of a gas burner used in the first step may be made of nickel. This makes it possible to add nickel without using a net or to improve efficiency of nickel addition by using the nozzles together with the net. Fourth Modification While nozzles are formed in a line in the above-described embodiments, the nozzles may be placed in two or more lines, or in a staggered fashion. The nozzles may also be formed in the shape of a long slit. This increases the density of the flame, leading to improved efficiency of nickel addition, efficiency of oxidation and the like.	H	67H01	185H01L	21	20
11688050	US20080230905A1-20080925	Power Semiconductor Module, Method for Producing a Power Semiconductor Module, and Semiconductor Chip	ACCEPTED	20080911	20080925	[]	H01L2348	["H01L2348", "H01L2144"]	9214442	20070319	20151215	257	772000	69783.0	NGUYEN	CUONG	[{"inventor_name_last": "Guth", "inventor_name_first": "Karsten", "inventor_city": "Soest", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Torwesten", "inventor_name_first": "Holger", "inventor_city": "Regensburg", "inventor_state": "", "inventor_country": "DE"}]	In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.	1. A semiconductor power module, in which a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another, wherein the first soldering partner has a first surface directly abutting against the connection layer; the second soldering partner has a second surface directly abutting against the connection layer; and the connection layer has a portion of intermetallic copper-tin phases of at least 90% by volume. 2. The power semiconductor module according to claim 1, wherein the first surface and/or the second surface have a surface roughness Rz, of less than or equal to 10 μm. 3. The power semiconductor module according to claim 1, wherein the first surface and/or the second surface have a surface roughness Rz, of less than 4 μm. 4. The power semiconductor module according to claim 1, wherein the first surface and/or the second surface have a surface roughness Rz, from 4 μm to 6 μm. 5. The power semiconductor module according to claim 1, wherein the first surface and/or the second surface have a surface roughness Rz, from 6 μm to 8 μm. 6. The power semiconductor module according to claim 1, wherein the first surface and/or the second surface have a surface roughness Rz, from 8 μm to 10 μm. 7. The power semiconductor module according to claim 1, wherein the connection layer comprises at least one of the intermetallic copper-tin phases Cu6Sn5, Cu3Sn, Cu10Sn3, Cu41Sn11. 8. The power semiconductor module according to claim 1, wherein the connection layer comprises intermetallic copper-tin phases which only comprise the intermetallic copper-tin phases Cu6Sn5 and Cu3Sn. 9. The power semiconductor module according to claim 1, wherein the connection layer comprises intermetallic copper-tin phases which only comprise the intermetallic copper-tin phase Cu3Sn. 10. The power semiconductor module according to claim 1, wherein at least 90% by volume of the connection layer has a melting point of at least 415° C. 11. The power semiconductor module according to claim 1, wherein at least 90% by volume of the connection layer has a melting point of at least 676° C. 12. The power semiconductor module according to claim 1, wherein the connection layer comprises a tin-based solder with a portion of 3.5% by weight of silver (Ag). 13. The power semiconductor module according to claim 8, wherein the connection layer comprises a tin-based solder with a portion of 0.1% by weight to 6% by weight of silver (Ag). 14. The power semiconductor module according to claim 1, wherein the connection layer comprises a tin-based solder, which is alloyed with one of the substances silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), germanium (Ge) or lead (Pb). 15. The power semiconductor module according to claim 10, wherein the connection layer comprises a tin-based solder, which is alloyed with at least two of the substances silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), germanium (Ge) or lead (Pb). 16. The power semiconductor module according to claim 1, wherein the first soldering partner and/or the second soldering partner comprises a copper portion of at least 70% by weight or is completely composed of copper. 17. The power semiconductor module according to claim 1, wherein the first soldering partner and/or the second soldering partner is embodied as a metallization of a semiconductor chip, as a copper disk, as a copper ribbon, as a contact wire, as a coating of a contact wire, as a clip, as a coating of a clip, as a circuit carrier for a semiconductor chip or as a coating for a circuit carrier of a semiconductor chip, or as a base plate or a coating for a base plate. 18. The power semiconductor module according to claim 1, wherein the first soldering partner is embodied as base plate or as coating of a base plate of the power semiconductor module, and wherein the second soldering partner is a substrate or a coating of a substrate. 19. The power semiconductor module according to claim 1, wherein the first soldering partner and/or the second soldering partner are substantially made of metal and has a thickness from 1 μm to 5 μm. 20. A semiconductor chip having a semiconductor body with a first surface, on which, starting from said first surface, a buffer layer, a diffusion barrier layer, and a copper-containing metal layer are arranged successively. 21. The semiconductor chip according to claim 20, wherein a tin-containing solder layer directly abuts against the copper-containing metal layer. 22. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a thickness of less than or equal to 10 μm, directly abuts against the copper-containing metal layer the solder layer. 23. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a thickness from 5 μm to 15 μm, directly abuts against the copper-containing metal layer. 24. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a thickness from 4 μm to 13 μm, directly abuts against the copper-containing metal layer. 25. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a thickness from 3 μm to 11 μm, directly abuts against the copper-containing metal layer. 26. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a thickness from 2 μm to 9 μm, directly abuts against the copper-containing metal layer. 27. The semiconductor chip according to claim 20, wherein a solder layer made of pure tin directly abuts against the copper-containing metal layer. 28. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a tin-based solder with a portion of 3.5% by weight of silver (Ag), directly abuts against the copper-containing metal layer. 29. The semiconductor chip according to claim 20, wherein a tin-containing solder layer having a tin-based solder with a portion of 0.1% by weight to 6% by weight of silver (Ag), directly abuts against the copper-containing metal layer. 30. The semiconductor chip according to claim 20, wherein a tin-containing solder layer being alloyed with one of the substances silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), germanium (Ge) or lead (Pb), directly abuts against the copper-containing metal layer. 31. The semiconductor chip according to claim 20, wherein a tin-containing solder layer being alloyed with at least two of the substances silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), germanium (Ge) or lead (Pb), directly abuts against the copper-containing metal layer. 32. The semiconductor chip according to claim 20, wherein the metal layer is made of copper (Cu). 33. The semiconductor chip according to claim 20, wherein the metal layer is made of copper (Cu) and has a thickness from 1 μm to 30 μm. 34. The semiconductor chip according to claim 20, wherein the buffer layer comprises aluminum (Al) or is composed of aluminum (Al). 35. The semiconductor chip according to claim 20, wherein the buffer layer comprises aluminum (Al) or is composed of aluminum (Al) and has a thickness from 200 nm to 700 nm. 36. The semiconductor chip according to claim 20, wherein the buffer layer comprises aluminum (Al) or is composed of aluminum (Al) and has a thickness of 400 nm. 37. The semiconductor chip according to claim 20, wherein the diffusion barrier layer comprises at least one of the materials titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN) or is composed of at least one of these materials, and has a thickness from 50 nm to 600 nm. 38. The semiconductor chip according to claim 20, wherein the diffusion barrier layer comprises titanium (Ti) or is composed of titanium (Ti) and has a thickness from 300 nm to 500 nm. 39. The semiconductor chip according to claim 20, wherein the diffusion barrier layer comprises titanium (Ti) or is composed of titanium (Ti) and has a thickness of 400 nm. 40. The semiconductor chip according to claim 20, wherein a seed layer is arranged between the barrier layer and the metal layer. 41. The semiconductor chip according to claim 40, wherein the seed layer comprises a thickness from 50 nm to 200 nm, and comprises at least one of the materials silver (Ag), gold (Au), nickel (Ni), nickel vanadium (NiV), copper (Cu) or is composed of at least one of these materials. 42. The semiconductor chip according to claim 40, wherein the seed layer comprises copper (Cu) or is composed of copper (Cu) and has a thickness of 100 nm to 200 nm. 43. The semiconductor chip according to claim 40, wherein the seed layer comprises silver (Ag) or is composed of silver (Ag) and has a thickness from 50 nm to 100 mm. 44. A method for producing a power semiconductor module, in which a copper-containing (Cu) first soldering partner, a connection layer, and a copper-containing (Cu) second soldering partner are arranged successively, with the following steps: providing a copper-containing (Cu) first soldering partner, a tin-containing (Sn) solder, and a copper-containing (Cu) second soldering partner; arranging the solder between the first soldering partner and the second soldering partner; melting the solder by heating it to a temperature above its original melting point and below or equal to 415° C.; pressing the first soldering partner and the second soldering partner, as well as the solder arranged between the soldering partners against one another with a predefined pressure from 0.5 N/mm2 to 5 N/mm2; and maintaining the temperature of the solder during pressing above its melting point and below or equal to 4000 for a period of at least 0.1 seconds to 10 seconds. 45. The method according to claim 44, wherein the period of at least 0.1 seconds to 10 seconds is followed by a step of tempering the soldering partners and the solder for more than 0 seconds to 120 seconds at a temperature above its original melting point and below or equal to 415° C. 46. The method according to claim 44, wherein the predefined pressure is more than 0 N/mm2 and less than or equal to 5 N/mm2. 47. The method according to claim 46, wherein the predefined pressure is more than or equal to 0.5 N/mm2 and less than or equal to 3 N/mm. 48. The method according to claim 44, wherein the solder is applied to the first soldering partner and/or the second soldering partner prior to the pressing of the first soldering partner and of the second soldering partner against one another. 49. The method according to claim 48, wherein the application of the solder takes place by means of vapor deposition, sputtering, or by galvanic deposition. 50. The method according to claim 44, wherein the first soldering partner is a metallization of a semiconductor chip and the second soldering partner is a metallization of a substrate. 51. The method according to claim 44, wherein the first soldering partner is a metallization of a semiconductor chip and the second soldering partner is a contact wire or a coating of a contact wire. 52. The method according to claim 44, wherein the first soldering partner is a metallization of a semiconductor chip and the second soldering partner is a clip or a coating of a clip. 53. The method according to claim 44, wherein the first soldering partner is a base plate or a coating of a base plate of the power semiconductor module and the second soldering partner is a substrate or a coating of a substrate. 54. The method according to claim 44, wherein the first soldering partner and/or the second soldering partner has a first surface facing towards the respective other soldering partner, said first surface having a surface roughness Rz less than or equal to 10 μm. 55. The method according to claim 44, wherein the power semiconductor module comprises a semiconductor body, on which a metallization stack and the first soldering partner are arranged successively. 56. The method according to claim 55, wherein the metallization stack comprises a buffer layer and a diffusion barrier layer. 57. The method according to claim 56, wherein the buffer layer comprises aluminum or is composed of aluminum. 58. The method according to claim 56, wherein the buffer layer has a thickness from 200 nm to 700 nm. 59. The method according to claim 56, wherein the diffusion barrier layer comprises at least one of the materials titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN) or is composed of at least one of these materials. 60. The method according to claim 56, wherein the diffusion barrier layer has a thickness from 50 nm to 600 nm. 61. The method according to claim 44, wherein the first soldering partner and/or the second soldering partner have a thickness larger than 1 μm. 62. The method according to claim 44, wherein the solder consists of tin (Sn) or of pure tin (Sn). 63. The method according to claim 44, wherein the solder comprises tin (Sn), as well as at least one of the materials silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), lead (Pb), germanium (Ge). 64. The method according to claim 44, wherein, prior to the melting, the solder has a thickness of less than or equal to 15 μm. 65. The method according to claim 55, wherein a seed layer is arranged between the barrier layer and the first soldering partner. 66. The method according to claim 64, wherein the seed layer has a thickness from 50 nm to 200 nm and consists of at least one of the materials silver (Ag), gold (Au), nickel (N1), nickel vanadium (NiV), copper (Cu) or is composed of at least one of these materials.	<SOH> BACKGROUND <EOH>Power semiconductor modules comprise a number of soldered connections, wherein the most various components must be fixedly and permanently joined with one another. Due to the high temperatures occurring during operation of the power semiconductor modules, as well as due to frequent temperature changes with high temperature shifts, the soldered joints are heavily used, which limits the service life of the power semiconductor modules. Especially if at least one of the soldering partners has large surface roughness, e.g. the metallization of a ceramic substrate, the respective soldering joints are sensitive to temperature cycling. To avoid problems arising with a large surface roughness in many cases the surface of a soldering partner needs to be polished.	<SOH> SUMMARY <EOH>According to an embodiment, in a novel semiconductor power module a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another, wherein the first soldering partner has a first surface directly abutting against the connection layer; the second soldering partner has a second surface directly abutting against the connection layer; and the connection layer comprises a portion of intermetallic copper-tin phases of at least 90% by volume. Further, a novel semiconductor chip is disclosed; the semiconductor chip comprises a semiconductor body with a surface, on which, starting from the semiconductor chip, a buffer layer, a diffusion barrier layer, and a copper-containing metal layer are arranged successively. Further, a novel method for producing a power semiconductor module is disclosed; in the power semiconductor module a copper-containing (Cu) first soldering partner, a connection layer, and a copper-containing (Cu) second soldering partner are arranged successively, with the following steps: providing a copper-containing (Cu) first soldering partner, a tin-containing (Sn) solder, and a copper-containing (Cu) second soldering partner; arranging the solder between the first soldering partner and the second soldering partner; melting the solder by heating it to a temperature above its original melting point and below or equal to 415° C.; pressing the first soldering partner and the second soldering partner, as well as the solder arranged between the soldering partners against one another with a predefined pressure from 0.5 N/mm 2 to 3 N/mm 2 ; and maintaining the temperature of the solder during pressing above its melting point and below or equal to 400° C. for a period of at least 0.1 seconds to 10 seconds.	TECHNICAL FIELD The invention relates to power semiconductor modules, to a method for producing a power semiconductor module and to semiconductor chips. BACKGROUND Power semiconductor modules comprise a number of soldered connections, wherein the most various components must be fixedly and permanently joined with one another. Due to the high temperatures occurring during operation of the power semiconductor modules, as well as due to frequent temperature changes with high temperature shifts, the soldered joints are heavily used, which limits the service life of the power semiconductor modules. Especially if at least one of the soldering partners has large surface roughness, e.g. the metallization of a ceramic substrate, the respective soldering joints are sensitive to temperature cycling. To avoid problems arising with a large surface roughness in many cases the surface of a soldering partner needs to be polished. SUMMARY According to an embodiment, in a novel semiconductor power module a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another, wherein the first soldering partner has a first surface directly abutting against the connection layer; the second soldering partner has a second surface directly abutting against the connection layer; and the connection layer comprises a portion of intermetallic copper-tin phases of at least 90% by volume. Further, a novel semiconductor chip is disclosed; the semiconductor chip comprises a semiconductor body with a surface, on which, starting from the semiconductor chip, a buffer layer, a diffusion barrier layer, and a copper-containing metal layer are arranged successively. Further, a novel method for producing a power semiconductor module is disclosed; in the power semiconductor module a copper-containing (Cu) first soldering partner, a connection layer, and a copper-containing (Cu) second soldering partner are arranged successively, with the following steps: providing a copper-containing (Cu) first soldering partner, a tin-containing (Sn) solder, and a copper-containing (Cu) second soldering partner; arranging the solder between the first soldering partner and the second soldering partner; melting the solder by heating it to a temperature above its original melting point and below or equal to 415° C.; pressing the first soldering partner and the second soldering partner, as well as the solder arranged between the soldering partners against one another with a predefined pressure from 0.5 N/mm2 to 3 N/mm2; and maintaining the temperature of the solder during pressing above its melting point and below or equal to 400° C. for a period of at least 0.1 seconds to 10 seconds. BRIEF DESCRIPTION OF THE DRAWINGS The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, instead emphasis being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings: FIG. 1 is a vertical cross-sectional view through a power semiconductor module with a plurality of soldered joints, which each comprise a connection layer with a portion of at least 90% by volume of intermetallic copper-tin phases; FIG. 2 is a vertical cross-sectional view through an enlarged section of a substrate of the power semiconductor module according to FIG. 1, fitted with a semiconductor chip; FIG. 3 is a vertical cross-sectional view through a section of a not yet installed semiconductor chip, on which a copper-containing metal layer and, directly abutting thereon, a tin-containing solder layer are arranged; FIG. 4 is a vertical cross-sectional view of a semiconductor chip being soldered to a substrate of a power semiconductor module according to FIGS. 1 and 2, at different steps of the soldering process; FIG. 5 is a phase diagram which illustrates the intermetallic copper-tin phases; FIG. 6 is a vertical cross-sectional view of two soldering partners being soldered to one another, at different steps of the soldering process; FIG. 7 is a diagram which illustrates a first example of a temporal characteristics of the temperature of a solder and of the pressure applied to the soldering partners during manufacturing a solder connection; FIG. 8 is a diagram which illustrates a second example of a temporal characteristics of the temperature of a solder and of the pressure applied to the soldering partners during manufacturing a solder connection; FIG. 9 is a diagram which illustrates different temporal characteristics of the pressure applied to the soldering partners during manufacturing a solder connection; and FIG. 10 is an illustration for explaining how to evaluate the surface roughness Rz, by example of a metallization of a substrate. DETAILED DESCRIPTION FIG. 1 is a vertical cross-sectional view through a power semiconductor module 1 with a plurality of soldered joints, wherein pairs of copper-containing soldering partners 20b/12b, 12a/19, 119/9 are each joined by a connection layer 214, 14 or 114, respectively, located therebetween. The connection layers 214, 14 or 114, respectively, each comprise a portion of at least 90% by volume of intermetallic copper-tin phases. The power semiconductor module 1 comprises a base plate 20a with a copper-containing coating 20b, on which a substrate 12 is arranged. Instead of a copper-containing coating 20b, provision may also be made for a base plate comprising copper or being composed of copper. The substrate 12 comprises an electrically insulating, highly heat-conducting carrier 12c, for example a ceramic, such as Al2O3, on which a structured metal layer 12a comprising copper or being composed of copper, and a metal layer 12b comprising copper or being composed of copper, are arranged on sides located opposite one another. On each of these substrates 12, one or several semiconductor chips are arranged with a semiconductor body 18, which comprises chip metallizations 19, 119 at least on one of two sides located opposite one another. The semiconductor chips are contacted by means of contact wires 9 on the side facing away from the substrate 12. The contact wires 9 may be electrically connected and/or mechanically joined with sections of the structured metallization 12a, with the metallization of further semiconductor chips on the same or another substrate 12, with a metallic bus bar 7 for joining two or more substrates 12, with external load connections 2 or with external control connections 3. The base plate 20a with its coating 20b forms a housing of the power semiconductor module 1 together with side walls 20c, as well as with a front wall 20d. For protection against environmental influences, particularly against the permeation of humidity and dirt, as well as for increasing the insulation property, the power semiconductor module 1 optionally is cast as well with a soft sealing compound 6 as with a hard sealing compound 5. The soft sealing compound 6 extends, starting from the base plate 20a and its coating 20b, at least beyond the upper surface of the semiconductor chip. The hard sealing compound 5 is arranged above the soft sealing compound 6 on the side thereof facing away from the base plates 20a, 20b. An enlarged section of the power semiconductor module 1 according to FIG. 1 prior to the casting is shown in FIG. 2 in more detail. The production of a power semiconductor module 1 according to FIGS. 1 and 2 is effected in a plurality of steps. In a first step, a substrate 12 is fitted with one or a number of semiconductor chips. For this, provision is made for a respective connection layer 14, which abuts against a metallization 19 on the lower side of the semiconductor body 18 of the semiconductor chip, as well as against the metallization 12a at the upper side of the substrate 12. The substrates 12 fitted in such a manner each form a unit. To be electrically contacted, the semiconductor chips of the fitted substrates 12 may, in an optional second step, be connected at their upper side by means of contact wires 9. In a third step, one or more substrates 12 each optionally fitted with semiconductor chips are fixedly joined with the base plate 20a, 20b by means of a connection layer 214. Instead of a common connection layer 214 one or more substrates 12 may comprise individual connection layers. The connection layers 14, 114, 214 each comprises a portion of at least 90% by volume of intermetallic copper-tin phases. The copper for the formation of the intermetallic copper-tin phases thereby emanates at least substantially out of the soldering partners, which are to be joined with one another and which directly abut against the respective connection layer 14, 114, 214. In the case of the connection layer 14, these partners are the metallization 12a and the chip metallization 19. In the case of the connection layer 114, these partners are the chip metallization 119 at the upper side and the contact wires 9, and, in the case of the connection layer 214, the metallization 12b at the lower side of the substrate 12 and the base plate 20a, 20b. The contact wires 9 comprise copper, e.g. in the form of a copper coating, of an alloy, or may consist of copper. The production of connections by means of such connection layers 14, 114, 214 having at least 90% by volume of intermetallic copper-tin phases will be explained below in an exemplary manner by means of a semiconductor chip according to FIG. 3, which is mechanically joined with and electrically connected to a metallization 12a at the upper side of a substrate 12 according to FIGS. 1 and 2 in a number of steps illustrated in FIG. 4. FIG. 3 is a vertical cross-sectional view through a section of a semiconductor chip having a semiconductor body 18, which, starting at its lower side, is provided with a chip metallization 19 in which an optional buffer layer 15, an optional diffusion barrier layer 16, an optional seed layer 17, and a copper-containing metal layer 11 are arranged successively. The buffer layer 15 ensures that thermomechanical stresses are removed from the connection layer and relieved within the thickness of said layer. The diffusion barrier layer 16 ensures that an unwanted interdiffusion of atoms into the active area of the semiconductor leads to a change of its electrical parameters. Instead of a buffer layer 15 and a diffusion barrier layer 16 a single layer combining a buffer function and a diffusion barrier function may be provided. A tin-containing solder layer 13 is applied directly onto the copper-containing metal layer 11. Accordingly, the upper side of the semiconductor body 18, starting from the semiconductor chip, is provided with a chip metallization 119, in which an optional buffer layer 115, an optional diffusion barrier layer 116, an optional seed layer 117, and a copper-containing metal layer 111 are arranged successively. It shall be pointed out that except one of all copper-containing metal layers 11 and 111 of the semiconductor chip are optional. A tin-containing solder layer 113 is applied directly onto the copper-containing metal layer 111. Alternatively, at least one of the solder layers 13 or 113 may, instead of being applied to a metal layer 11, 111, respectively, or to a chip metallization 19 or 119, respectively, be applied to a predetermined soldering partner, e.g. as depicted in FIGS. 1 and 2, to a metal layer 12a of substrate 12 or to a bond wire 9. The solder layers 13, 113 may, for example, be created by means of vapor deposition, sputtering, or by galvanic deposition. The copper-containing metal layers 11, 111 are designated to provide copper, which diffuses from the metal layers 11, 111 into the fused solder layers 13 or 113, respectively, which directly abut on the metal layers 11, 111, for the purpose of forming intermetallic copper-tin phases. The semiconductor chip 18 has a thickness d18, the buffer layers 15, 115 have thicknesses d15 or d115, respectively, the diffusion barrier layers 16, 116 have thicknesses d16, d116, the seed layers 17, 117 have thicknesses d17, d117, the copper-containing metal layers 11, 111 have thicknesses d1 or d111, respectively, and the tin-containing solder layers 13, 113 have thicknesses d13 or d113, respectively. The buffer layer 15 and/or the buffer layer 115 may, for example, comprise aluminum (Al) or may be composed of aluminum (Al). The thickness d15 of the buffer layer 15 and/or the thickness d115 of the buffer layer 115 may be, for example, from 200 nm to 700 nm, e.g. about 400 nm. The diffusion barrier layer 16 and/or the diffusion barrier layer 116 may each comprise exactly one, exactly two, or a number of the substances titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), tantalum nitride (TaN) or they may be composed of at least one of these materials. The thicknesses d16 of the diffusion barrier layer 16 and/or d116 of the diffusion barrier layer 116 may, e.g., be from 50 nm to 600 nm. For example, the diffusion barrier layer 16 and/or the diffusion barrier layer 116 may comprise titanium (Ti) or may be composed of titanium (Ti) and may have a thickness d16 or d116, respectively, from 300 nm to 500 nm, e.g. 400 nm. The optional seed layers 17 and 117 are each arranged between a barrier layer 16 and 116, respectively, and one of the metal layers 11 or 111, respectively, and may each comprise at least one of the materials silver (Ag), gold (Au), nickel (Ni), nickel vanadium (NiV) or copper (Cu) or they may be composed of at least one of these substances. The thicknesses d17 and/or d117 of the seed layers 17 or 117, respectively, may be, for example, from 50 nm to 200 nm. In particular, with thicknesses d17 or d117, respectively, from 100 nm to 200 nm, the seed layers 17 and/or 117 may comprise copper (Cu) or may be composed of copper (Cu). For example, the seed layer 17 and/or the seed layer 117 may comprise silver (Ag) or may be composed of silver (Ag) and thereby have a thickness from 50 nm to 100 nm. The metal layer 11 and/or the metal layer 111 comprise copper (Cu) or are composed of copper (Cu) and may thereby have a thickness d11 or d111, respectively, from 1 μm to 30 μm. The solder 13 and/or the solder 113 may, for example, be composed of pure tin (Sn) or may be embodied as tin-containing alloy, which comprises exactly one, exactly two, or more than two of the substances from the group silver (Ag), copper (Cu), nickel (N1), indium (In), bismuth (Bi), zinc (Zn), antimony (Sb), germanium (Ge) or lead (Pb). In particular, the solder 13 and/or the solder 113 may be embodied as tin-containing alloy and may comprise a portion of silver (Ag) from 0.1% by weight to 6% by weight or from 1% by weight to 5% by weight, e.g., 3.5% by weight. For example, if the surface roughness of the metal layers 11 and/or 111, respectively, is small compared with 1 μm, the thickness d13 of the corresponding solder layer 13 and/or the thickness d113 of the solder layer 113 may be chosen to be less than or equal to 10 μm, e.g. from 5 μm to 15 μm, from 4 μm to 13 μm, from 3 μm to 11 μm or from 2 μm to 9 μm. Thicknesses d13 and/or d113 from 5 μm to 10 μm are suited, e.g., if the surface of a soldering partner, with which the respective solder layer 13 or 113 is to connect the semiconductor chip with, has a surface roughness Rz, from 8 μm to 10 μm. For example, for a surface roughness Rz, of the soldering partner from 6 μm to 8 μm, a thickness d13 or d113 of the solder layer 13 or 113, respectively, from 4 μm to 13 μm is particularly suitable, for a surface roughness Rz, of the soldering partner from 4 μm to 6 μm, a thickness d13 or d113 of the solder layer 13 or 113, respectively, from 2 μm to 9 μm is particularly suitable. The way how to determine the surface roughness Rz, will be described in more detail in FIG. 10. If a metal layer 11, 111 has a surface roughness Rz1 on its side facing to the respective solder layer 13, 113 of more than or equal to 1 μm, the thickness d13, d113 of the respective solder layer 13, 113 may be chosen thicker than in the above mentioned case of a substantially smooth metal layer. The following table shows, in μm, possible values for the thickness d13, d113 of a solder layer 13, 113 which is to be soldered to a solder partner, depending of the surface roughness Rz1 of the metal layer 11, 111 and the surface roughness Rz2 of the solder partner: Rz11 Rz2 <4 4 to 6 6 to 8 8 to 10 <4 4 to 18 5 to 20 6 to 22 7 to 24 4 to 6 5 to 20 6 to 22 7 to 24 8 to 26 6 to 8 6 to 22 7 to 24 8 to 26 9 to 28 8 to 10 7 to 24 8 to 26 9 to 28 10 to 30 FIG. 4a shows a section of the semiconductor chip of FIG. 3 comprising the semiconductor body 18 and the metallization 19 at the lower side thereof, as well as the solder layer 13 applied to the metallization 19. The solder layer 13 is arranged between the copper-containing metal layer 11 and the copper-containing metallization 12a of a substrate 12 according to FIGS. 1 and 2. The metallization 12a has a thickness d12 and has a large surface roughness Rz, on an upper surface facing towards the semiconductor body 18. The lower side of the metal layer 11 has a lower surface having a roughness which is low compared to the surface roughness Rz, of the metallization 12a. Therefore, the lower surface of the metal layer 11 is shown as substantially flat. To produce a fixed and permanent joint between the metallization 11 of the semiconductor body 18 and the metallization 12a, the substrate 12 with its metallizations 12a, 12b is heated, according to FIGS. 1 and 2, to a temperature, which is higher than the melting point of the solder layer 13. Subsequently, the solder layer 13 and the metallization 12a are contacted by applying an external, predefined pressure ps and are pressed against one another. The predefined pressure may be, for example, more than 0 N/mm2 and less than or equal to 5 N/mm2, or from 0.5 N/mm2 to 1 N/mm2, or from 0.5 N/mm2 to 3 N/mm2. This creates a thermal contact between the heated metallization 12a and the solder layer 13, as shown in FIG. 4b, so that the solder layer melts and fills trenches 12e formed by the surface roughness of the metallization 12a, which is shown in FIG. 4c. The thickness d13 of the original solder layer 13 according to FIG. 3 is chosen in such a manner that sufficient solder 13 is available to completely fill the trenches 12e under the predefined pressure ps and, at the same time, to avoid that, during the pressing process, too much excessive solder laterally escapes from the intermediate space formed between the metallizations 11 and 12a. As can further be seen from FIG. 4c, a diffusion process takes place at the interfaces between the solder 13 and the copper-containing metallizations 11, 12a, which abut thereon, whereby copper 8 escapes from the metallizations 11, 12a and diffuses into the liquid solder 13, so that one or more intermetallic copper-tin phases are formed in sections 13a of solder 13. By maintaining the external pressure ps as well as the heat supply from the metal layer 12a, the diffusion of copper continues, so that the regions 13a having intermetallic copper-tin phases increase, and, associated therewith, regions 13b of the solder, which do not comprise tin converted into an intermetallic copper-tin phase, decrease, as can be seen from FIGS. 4c to 4e. As shown in FIG. 4d, continuous bridges 13d consisting only of intermetallic copper-tin phases, will form at places where the local distance between the soldering partners 11, 12a is minimal. As soon as at two locations spaced apart from one another two continuous bridges 13d have established, the soldering partners 11, 12a are interconnected and the pressure p may be reduced or removed. To continue the diffusion process of the copper 8 into the solder, the temperature of the solder may be maintained, e.g. below 415° C. and above the melting point of the original solder, for a predetermined duration, until enough solder, e.g. at least 90% by volume, has been converted into intermetallic copper-tin phases. The melting point of the material in the regions 13a comprising intermetallic copper-tin phases is significantly determined by the melting point of that intermetallic copper-tin phase present in the regions 13a having the lowest melting point of all intermetallic copper-tin phases present in the regions 13a. Of all possible intermetallic copper-tin phases, the phase Cu6Sn5, with 415° C., has the lowest melting point, which can be seen from the phase diagram for intermetallic copper-tin phases according to FIG. 5. This means that the regions 13a with intermetallic phases according to FIGS. 4c to 4e have a melting point of at least 415° C., with a sufficiently high portion of the phase Cu6Sn5. Provided that the intermetallic phase Cu6Sn5 does not emerge, the melting point of the sections 13a according to FIGS. 4c and 4d actually lies at 676° C., which is the melting point of the intermetallic copper-tin phase Cu3Sn. If the melting of the solder 13 is effected at a temperature, which lies above the melting point of the solder 13 and below 415° C., due to the diffusion of copper and the formation of intermetallic copper-tin phases associated therewith, a solidification of the material in the sections 13a occurs. In so doing, it is possible to produce a connection layer 14 according to FIG. 4d, which has a melting point being higher than the temperature required for melting the solder layer 13. Once a portion of the tin contained in the liquid solder 13 is converted into one or more intermetallic copper-tin-phases at an amount being sufficient to produce a stable connection layer 14 at the temperature at hand, the external pressure ps may be decreased or withdrawn. Independent on whether or not a pressure ps is further exerted on the configuration, the diffusion and the formation of intermetallic copper-tin phases in the connection layer 14 associated therewith continues, until mostly all tin, e.g., at least 90% by volume, is converted into an intermetallic copper-tin phase. To achieve a sufficiently high degree of conversion of tin into an intermetallic copper-tin phase, the thickness of the solder layer 13 applied onto the lower side of the semiconductor chip may be chosen to match the surface roughness of the metal layer 12a in such a manner that, after the liquefaction of the solder layer 13, the distance d0 (see FIGS. 4c to 4e) between the metal layers 11 and 12a establishing under the influence of the pressure ps, is as short as possible, and that, nevertheless, all of the trenches 12e are basically completely filled. The shorter the distance d0, the smaller the section of the solder 13, through which the copper 8 escaping from the metallizations 11 and 12a must permeate, to effect the highest possible degree of conversion of the tin contained in the liquid solder 13 into an intermetallic copper-tin phase. The distance d0 may, e.g., be shorter than 1 μm, or, be equal to zero. Coming along with a high pressure ps and a short distance d0 the solder needs to be heated to a temperature above its melting point for a short duration only. Therefore, suitable pairs of such a duration and a pressure ps applied to the soldering partners, may be defined. For example, at the same time, when the solder is heated for a predefined duration above its original melting point, i.e. above the melting point the solder has before the formation of copper-tin-phases starts, the pressure ps may be applied to the soldering partners and the solder arranged therebetween, to effect a minimum distance d0 between the soldering partners 11, 12a and to effect the formation of bridges 12d. The pressure ps may be, e.g., less than 5 N/mm2 and the temperature of the solder, e.g., from above its original melting point to 415° C. In the ideal case, all tin from the original solder 13 has been converted into one or more intermetallic copper-tin-phases, which may be seen from FIG. 4e. FIGS. 6a to 6l generally show the production of a connection layer 14 between two copper-containing soldering partners 11, 12a of a power semiconductor module as a function of time t. According to FIG. 6a, copper-containing soldering partners 11a, 12a, as well as a tin-containing solder 13 are provided at a point in time t0. The solder 13 is arranged between the soldering partners 11 and 12a, and may be applied, for example, onto one or both of the sides of the soldering partners 11 and 12a, which are to be joined with one another, for example by means of vapor deposition, sputtering, or by galvanic deposition. At a point in time t0, the soldering partners 11, 12a, and the solder 13 are at ambient temperature, for example at room temperature. According to FIG. 6b, the soldering partner 12a is heated to a temperature T1, which is higher than the temperature t0 and higher than the melting point of the solder 13. According to FIG. 6c, the soldering partners 11 and 12a are subsequently, at a point in time t2, pressed against one another by means of a pressure ps, whereby a thermal contact between the solder 13 and the soldering partner 12a is formed, so that the solder 13 is heated due to the higher temperature T1 of the soldering partner 12a, and is liquefied at a point in time t3, the result of which is shown in FIG. 6d. As arises from FIG. 6e, the liquid solder 13, under the influence of the pressure ps, permeates into the trenches 12e, which are formed by the surface roughness of the soldering partner 12a. At the same time, a displacement of excessive liquid solder 13c takes place from the opening existing between the soldering partners 11 and 12a. Furthermore, in the course of time, the temperature of the soldering partner 11 conforms to the temperature T1 of the soldering partner 12a. Associated with the liquefaction of the solder 13, a diffusion process sets in, wherein copper 8 diffuses from the soldering partners 11 and 12a into the solder 13, so that the copper 8 with tin from the solder 13 forms one or a plurality of intermetallic copper-tin phases, the melting points of which being higher than the melting point of the original solder 13. As time t increases, more and more copper 8 diffuses into the solder layer 13, which can be seen from FIG. 6f to 6i, at points in time t5 to t8. In the configuration according to FIG. 6h, the original solder layer 13 was already converted into a sufficiently stable connection layer 14, so that it was possible to remove the external pressure ps according to FIGS. 6c to 6g. To further advance the diffusion of cooper into tin components contained in the solder 13, which have not yet been converted into an intermetallic copper-tin phase, the temperature of the connection layer 14 and/or of the soldering partners 11, 12a abutting against the connection layer 14 is optionally maintained or at least held at a value being higher than the melting point of the original solder 13. Once the connection layer 14 according to FIG. 6i has, at a point in time t8, a predefined portion of intermetallic copper-tin phases, e.g. of at least 90% per volume, the arrangement is cooled down to a temperature T2, which is lower than the temperature T1, the result of which can be seen from FIG. 6k at a point in time t9. After the further cooling of the configuration to ambient temperature T0, the soldering partners 11 and 12a are permanently joined with one another in a manner, which is stable to temperature changes at a point in time t10, as is shown in FIG. 6l. FIGS. 7 and 8 show examples of temporal characteristics of the temperature T of the solder and of the pressure p applied to the soldering partners during manufacturing a solder connection as described above. Starting from an ambient temperature T0, dependent on time t, the solder is heated to a predefined temperature T1. Further, pressure p is increased to a predefined pressure ps. The characteristics of temperature T and pressure p are coordinated such that within a predefined time ts the solder has a temperature of T1 and the pressure p with which the soldering partners are pressed against one another is ps. In the example according to FIG. 7, temperature T reaches the predefined temperature T1 before pressure p reaches the predefined pressure ps. Further, pressure p is reduced below the predefined pressure ps before temperature T is reduced below the predefined temperature T1. During a tempering time tt following the time ts, the soldering partners and the solder may be tempered without external pressure p or with an external pressure p below the predefined pressure ps for a predefined duration tt, e.g. from more than 0 sec to 120 sec, or 65 sec to 110 sec, at a temperature of less than 415° C., e.g., 400° C. In the example according to FIG. 8, pressure p reaches the predefined pressure ps before temperature T reaches the predefined temperature T1. Further, temperature T is reduced below the predefined temperature T1 before pressure p is reduced below the predefined pressure ps. Similarly, the temperature T may reach the predefined temperature T1 before pressure p reaches the predefined pressure ps and temperature T is may be reduced below the predefined temperature T1 before pressure p is reduced below the predefined pressure ps. Also, pressure p may reach the predefined pressure ps before temperature T reaches the predefined temperature T1 and pressure p may be reduced below the predefined pressure ps before temperature T is reduced below the predefined temperature T1 Within the time ts, temperature T shall not fall below the predefined temperature T1 and pressure p shall not fall below the predefined pressure ps. The predefined temperature T1 may be, e.g., from the original melting point of the used solder to 415° C. and the predefined pressure, e.g., from 0.5 N/mm2 to 5 N/mm2. The predefined time ts may be, e.g., from 0.1 sec to 5 sec. FIG. 9 shows different temporal characteristics of the pressure applied to the soldering partners during manufacturing a solder connection. The external pressure p applied to the soldering partners 11, 12a may start from 0 N/mm2 and rise to ps, e.g., with an almost vertical slope (1), linearly (2), curved right (3) or curved left (4). Over a period of time ts, in which both the temperature T is T1 and the pressure p is p1, first bridges 13d (see FIG. 4d) form. Then, a period of time tt follows, in which the temperature T is maintained below 415° C., e.g., between the solder's original melting point and below or equal to 415° C., and the diffusion process is continued. The pressure p1 may also be maintained after during the period of time tt, e.g. 0 sec to 120 sec. FIG. 10 illustrates how to evaluate the surface roughness Rz, which is defined according to DIN EN ISO 1302 (06/02) by example of a metallization of a substrate as described above. First, a predefined measuring length l along the surface of the metallization is subdivided into five sections 11, 12, 13, 14 and 15 having equal lengths. Then, within each of these five consecutive sections 11, 12, 13, 14 and 15 the peak-to-valley difference Rz1, Rz2, Rz3, Rz4 and Rz5, respectively, is determined. The surface roughness Rz is the average of the five peak-to-valley differences Rz1, Rz2, Rz3, Rz4 and Rz5. The present invention allows for the first time a unique technology to mount a semiconductor chip onto a metallization of a substrate, e.g. a ceramic substrate, the metallization having a large surface roughness Rz of, e.g., 10 μm, for a reliable application at an ambient temperature of about 200° C. or above. In addition, this technology leads to a reduction of the heat transmission resistance of the connection layer. Although various examples to realize the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. Such modifications to the inventive concept are intended to be covered by the appended claims.	H	67H01	185H01L	23	48
11692151	US20070190722A1-20070816	METHOD TO FORM UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT	ACCEPTED	20070801	20070816	[]	H01L21336	["H01L21336"]	7767499	20070327	20100803	438	129000	95301.0	SENE	PAPE	[{"inventor_name_last": "Herner", "inventor_name_first": "S.", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}]	A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.	1. A method for forming a vertically oriented p-i-n diode, the method comprising: forming a first rail-shaped conductor above a substrate; forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor; forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of semiconductor material, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar; forming a top heavily doped n-type region doped with arsenic; and annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step, wherein the p-i-n diode comprises the bottom heavily doped p-type region, the middle intrinsic or lightly doped region, and the top heavily doped n-type region. 2. The method of claim 1 wherein the silicide is titanium silicide, titanium germanide, titanium silicide-germanide, cobalt silicide, cobalt germanide, or cobalt silicide-germanide. 3. The method of claim 1 wherein the top heavily doped n-type region is doped in situ. 4. The method of claim 1 wherein the top heavily doped n-type region is doped by doping the top of the middle intrinsic or lightly doped region by ion implantation. 5. The method of claim 4 wherein ion implantation to form the top heavily doped n-type region takes place before the patterning and etching step. 6. The method of claim 4 wherein ion implantation to form the top heavily doped n-type region takes place after the patterning and etching step. 7. The method of claim 1 further comprising forming a titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer above and in contact with the top heavily doped n-type region, wherein the silicide, germanide, or silicide-germanide is formed when a portion of the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer reacts with the top heavily doped n-type region. 8. The method of claim 7 wherein the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer is a portion of a top conductor. 9. The method of claim 7 wherein the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer is a portion of a hard mask used to etch the pillar during the patterning and etching step. 10. The method of claim 1 wherein the p-i-n diode is a portion of a memory cell, wherein the memory cell further comprises: a portion of the first rail-shaped conductor; a portion of a second rail-shaped conductor above the p-i-n diode, the p-i-n diode disposed between the first rail-shaped conductor and the second rail-shaped conductor. 11. The method of claim 10 wherein the memory cell further comprises a dielectric rupture antifuse, the dielectric rupture antifuse and the p-i-n diode arranged electrically in series between the first conductor and the second conductor. 12. The method of claim 11 wherein the dielectric rupture antifuse comprises HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, or ZrSiAlON. 13. The method of claim 11 wherein the dielectric rupture antifuse comprises silicon dioxide. 14. The method of claim 10 wherein the memory cell further comprises a resistivity-switching element, the resistivity-switching element and the p-i-n diode arranged electrically in series between the first conductor and the second conductor. 15. The method of claim 14 wherein the resistivity-switching element comprises a binary metal oxide. 16. The method of claim 15 wherein the binary metal oxide is selected from the group consisting of NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. 17. The method of claim 14 wherein the resistivity-switching element comprises carbon nanotube fabric. 18. The method of claim 1 wherein the substrate is a monocrystalline silicon wafer. 19. A method for forming a monolithic three dimensional memory array, the method comprising: a) monolithically forming a first memory level above a substrate by: i) forming a first plurality of rail-shaped conductors above the substrate; ii) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductors; iii) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type semiconductor, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; iv) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a first plurality of pillars; v) forming a top heavily doped region doped with arsenic; vi) annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step; and vii) forming a second plurality of rail-shaped conductors above the middle intrinsic or lightly doped region, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising a portion of one of the first rail-shaped conductors, one of a first plurality of pillars, and a portion of one of the second conductors, wherein each of the first pillars comprises a p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region formed by the doping step, and b) monolithically forming a second memory level above the first memory level. 20. The method of claim 17 wherein the second memory level comprises a second plurality of p-i-n diodes, each second p-i-n diode comprising a bottom heavily doped n-type region, a middle intrinsic or lightly doped region, and a top heavily doped p-type region. 21. The method of claim 18 wherein the second conductors are shared by the first memory level and the second memory level.	<SOH> BACKGROUND OF THE INVENTION <EOH>A diode has the characteristic of allowing very little current flow below a certain turn-on voltage, and substantially more current above the turn-on voltage. It has proven difficult to form a large population of vertically oriented p-i-n diodes having a bottom heavily doped p-type region, a middle intrinsic region, and a top heavily doped n-type region with good uniformity of current among the diodes when a voltage above the turn-on voltage is applied. It would be advantageous to form a large population of such upward-pointing diodes having good uniformity, specifically for use in a memory array.	<SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a method to fabricate an upward-pointing p-i-n diode. A first aspect of the invention provides for a method for forming a vertically oriented p-i-n diode, the method comprising: forming a first rail-shaped conductor above a substrate; forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor; forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of semiconductor material, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar; forming a top heavily doped n-type region doped with arsenic; and annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step, wherein the p-i-n diode comprises the bottom heavily doped p-type region, the middle intrinsic or lightly doped region, and the top heavily doped n-type region. Another aspect of the invention provides for a method for forming a monolithic three dimensional memory array, the method comprising: monolithically forming a first memory level above a substrate by: i) forming a first plurality of rail-shaped conductors above the substrate; ii) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductors; iii) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type semiconductor, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; iv) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a first plurality of pillars; v) forming a top heavily doped region doped with arsenic; vi) annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step; and vii) forming a second plurality of rail-shaped conductors above the middle intrinsic or lightly doped region, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising a portion of one of the first rail-shaped conductors, one of a first plurality of pillars, and a portion of one of the second conductors, wherein each of the first pillars comprises a p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region formed by the doping step, and monolithically forming a second memory level above the first memory level. Each of the aspects and embodiments of the invention described herein can be used alone or in combination with one another. The preferred aspects and embodiments will now be described with reference to the attached drawings.	RELATED APPLICATIONS This application is a continuation-in-part of Herner et al., U.S. patent application Ser. No. 10/955,549, “Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States,” filed Sep. 29, 2004, hereinafter the '549 application, which is a continuation-in-part of Herner et al., U.S. Pat. No. 6,952,030, “An Improved Method for Making High-Density Nonvolatile Memory,” hereinafter the '030 patent; which is a continuation of Herner et al., U.S. patent application Ser. No. 10/326,470, “An Improved Method for Making High-Density Nonvolatile Memory,” filed Dec. 19, 2002 (since abandoned) and hereinafter the '470 application, all assigned to the assignee of the present invention and hereby incorporated by reference in their entirety This application is related to Herner, U.S. patent application Ser, No. ______, (Atty. Docket No. SAND-01179US1), Large Array of Upward-Pointing P-I-N Diodes Having Large and Uniform Current”; to Herner et al, U.S. patent application Ser. No. ______, (Atty. Docket No. SAND-01193US0), “Method to Form a Memory Cell Comprising a Carbon Nanotube Fabric Element and a Steering Element”; and to Herner et al, U.S. patent application Ser. No. ______, (Atty. Docket No. SAND-01193US1), “Memory Cell Comprising a Carbon Nanotube Fabric Element and a Steering Element,” all filed on even date herewith and hereby incorporated by reference in their entirety. BACKGROUND OF THE INVENTION A diode has the characteristic of allowing very little current flow below a certain turn-on voltage, and substantially more current above the turn-on voltage. It has proven difficult to form a large population of vertically oriented p-i-n diodes having a bottom heavily doped p-type region, a middle intrinsic region, and a top heavily doped n-type region with good uniformity of current among the diodes when a voltage above the turn-on voltage is applied. It would be advantageous to form a large population of such upward-pointing diodes having good uniformity, specifically for use in a memory array. SUMMARY OF THE PREFERRED EMBODIMENTS The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a method to fabricate an upward-pointing p-i-n diode. A first aspect of the invention provides for a method for forming a vertically oriented p-i-n diode, the method comprising: forming a first rail-shaped conductor above a substrate; forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor; forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of semiconductor material, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar; forming a top heavily doped n-type region doped with arsenic; and annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step, wherein the p-i-n diode comprises the bottom heavily doped p-type region, the middle intrinsic or lightly doped region, and the top heavily doped n-type region. Another aspect of the invention provides for a method for forming a monolithic three dimensional memory array, the method comprising: monolithically forming a first memory level above a substrate by: i) forming a first plurality of rail-shaped conductors above the substrate; ii) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductors; iii) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type semiconductor, wherein the deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy; iv) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a first plurality of pillars; v) forming a top heavily doped region doped with arsenic; vi) annealing to crystallize the semiconductor material, where some portion of the semiconductor material was amorphous as deposited and is in contact with a silicide, germanide, or silicide-germanide after the annealing step; and vii) forming a second plurality of rail-shaped conductors above the middle intrinsic or lightly doped region, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising a portion of one of the first rail-shaped conductors, one of a first plurality of pillars, and a portion of one of the second conductors, wherein each of the first pillars comprises a p-i-n diode comprising a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region formed by the doping step, and monolithically forming a second memory level above the first memory level. Each of the aspects and embodiments of the invention described herein can be used alone or in combination with one another. The preferred aspects and embodiments will now be described with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an embodiment of a memory cell described in the '030 patent. FIG. 2 is a perspective view of a portion of a first memory level comprising memory cells like the cell of FIG. 1. FIG. 3a is a perspective view showing two stacked memory levels sharing conductors. FIG. 3b is a cross-sectional view of the same structure. FIG. 3c is a cross-sectional view showing two stacked memory levels not sharing conductors. FIG. 4a is a probability plot of current at applied voltage of 2 volts for a population of downward-pointing diodes formed according to an embodiment of the '030 patent. FIG. 4b is a probability plot of current at applied voltage of 2 volts for a population of upward-pointing diodes formed according to an embodiment of the '030 patent. FIG. 5 is perspective view of an embodiment of the present invention. FIG. 6 is a probability plot of current at applied voltage of 2 volts for a population of upward-pointing diodes formed according to the present invention. FIGS. 7a-7d are cross-sectional views illustrating stages in formation of two memory levels, the first memory level including upward-pointing diodes formed according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the '470 application, the '030 patent, and the '549 application, all owned by the assignee of the present invention, memory cells are described, each including a vertically oriented p-i-n diode in the form of a pillar. Such a diode is formed of a semiconductor material such as silicon, germanium, or a silicon-germanium alloy, and has a bottom heavily doped region of a first semiconductor type, a middle intrinsic or lightly doped region, and a top heavily doped region of a second semiconductor type opposite the first. It has been described to form this diode in both orientations, either having a bottom heavily doped p-type region and a top heavily doped n-type region; or the reverse, with a bottom heavily doped n-type region and the top heavily doped p-type region. FIG. 1 illustrates a memory cell formed according to an embodiment of the '030 patent. Such a memory cell includes a bottom conductor 200 and a top conductor 400, with a vertically oriented p-i-n diode 302 and a dielectric rupture antifuse 118 arranged electrically in series between them. In its initial, unprogrammed state, when a read voltage, for example of 2 volts, is applied between bottom conductor 200 and top conductor 400, very little current flows between them. Application of a relatively large programming voltage alters the memory cell, and, after programming, significantly more current flows between bottom conductor 200 and top conductor 400 at the same read voltage. This difference in current between the unprogrammed and programmed states is measurable, and each can correspond to a distinct data state; for example an unprogrammed cell can be considered to be a data “0” while a programmed cell is a data “1”. FIG. 2 shows a portion of a first memory level comprising a plurality of bottom conductors 200, a plurality of pillars 300, each pillar including a diode and a dielectric rupture antifuse as in FIG. 1, and a plurality of top conductors 400. Each pillar 300 is disposed between one of the bottom conductors 200 and one of the top conductors 400. Such a memory level can be formed above a substrate such as a conventional monocrystalline silicon wafer. Multiple memory levels can be formed stacked above the first to form a dense monolithic three dimensional memory array. A diode is a rectifying device, conducting current more readily in one direction than in the other. A diode can be said to point in its direction of preferred conduction. A vertically oriented diode having n-type semiconductor material at the bottom and p-type semiconductor material at the top can be said to be downward-pointing, while a vertically oriented diode having p-type semiconductor material at the bottom and n-type semiconductor material at the top can be said to be upward-pointing. Note that in this application, when terms indicating spatial relationships, like “upward”, “downward”, “above”, “below”, and the like are used, these terms are relative to the substrate, which is assumed to be at the bottom of the frame of reference. For example, if a first element is described to be above a second element, the first element is farther from the substrate than the second. In a vertically stacked memory array, it is preferred for vertically adjacent memory levels to share conductors, as shown in perspective view in FIG. 3a, in which the conductors 400 serve both as the top conductors of the first memory level M0 and as the bottom conductors of the second memory level M1. The same structure is shown in a cross-sectional view in FIG. 3b. FIG. 3c show a cross-sectional view of an array in which conductors are not shared. In FIG. 3c, each memory level has bottom conductors (200, 500), pillars (300, 600), and top conductors (400, 700), with an interlevel dielectric separating memory levels M0 and M1, with no conductors shared. The architecture of FIGS. 3a and 3b requires fewer masking steps and reduces fabrication costs to produce the same density of memory cells as shown in FIG. 3c. Sharing of conductors, as in FIGS. 3a and 3b, is most readily achieved electrically if diodes on adjacent levels point in opposite directions, for example if the first memory level M0 diodes are upward-pointing, while the second memory level M1 diodes are downward-pointing. A stacked array of only upward-pointing or only downward-pointing diodes will generally be formed with conductors not shared, as in FIG. 3c. A large memory array will typically include millions of memory cells, each of which must be sensed. There will inevitably be some variation in characteristics between memory cells in such a large array. To improve reliability, for a large array of memory cells, it is advantageous to maximize the difference between the unprogrammed and the programmed states, making them easier to distinguish. It is further advantageous to minimize variation between cells, and for the cells to behave as uniformly as possible. FIG. 4a is a probability plot showing unprogrammed current and programmed current under the same applied read voltage for a population of memory cells like those of the '030 patent (shown in FIG. 1) including a diode and an antifuse in series between conductors in which the diodes are all downward-pointing; i.e. the diodes have a bottom heavily doped n-type region, a middle intrinsic region, and a top heavily doped p-type region. It will be seen that the unprogrammed current for the downward-pointing diodes, shown on line A, is tightly grouped close to 10−12 amps. Similarly, the programmed current, shown on line B, with the exception of one outlier, is tightly grouped between about 10−5 and 10−4 amps. The distributions of unprogrammed current (line A) and programmed current (line B) are spaced well apart from each other and both are tightly grouped. FIG. 4b is a probability plot showing unprogrammed current and programmed current for a population of upward-pointing diodes formed as in the '030 patent. The unprogrammed current, shown on line C, is very similar to the unprogrammed current of the downward pointing diode, line A of FIG. 4a. The programmed current, however, shown on line D, shows a much wider distribution than the programmed current on line B of FIG. 4a. Programmed current for this upward-pointing diode ranges from about 8×10−8 amps to 7×10−5 amps, a difference approaching three orders of magnitude. A large number of the population of these diodes have programmed current less than 1 microamp. This nonuniformity and low programmed current make the upward-pointing diode of the '030 patent a less advantageous diode for use in a large array than the downward-pointing diode. In the present invention, a fabrication technique has been found that yields a large population of upward-pointing vertically oriented p-i-n diodes having good uniformity and large programmed current. FIG. 5 shows an example of a memory cell including an upward-pointing diode formed according to an embodiment of the present invention. In this memory cell, the diode is paired with a dielectric rupture antifuse, but, as will be described, the pictured memory cell is only one of many possible uses for such a diode, and is provided for clarity. The memory cell includes first conductor 200 and second conductor 400. Disposed between them are dielectric rupture antifuse 118 (shown sandwiched between conductive barrier layers 110 and 111) and diode 302. Diode 302 includes bottom heavily doped p-type region 112, middle intrinsic region 114, and top heavily doped n-type region 116. Diode 302 is formed of semiconductor material, for example silicon, germanium, or a silicon-germanium alloy. For simplicity, this semiconductor material will be described as silicon. The silicon is preferably predominantly amorphous as deposited (though p-type region 112, if doped in situ, will likely be polycrystalline as deposited.) Top heavily doped p-type region 116 is doped with arsenic. In preferred embodiments, region 116 is formed by forming middle intrinsic region 114, then doping the top of middle intrinsic region 114 with arsenic by ion implantation. As will be seen, this ion implantation step may take place either before or after the patterning and etching step that forms the pillar. In alternative embodiments, region 116 may be doped in situ by flowing an appropriate source gas such as AsH3 during silicon deposition at flows sufficient to result in an arsenic concentration of at least 5×1020 atoms/cm3. The bottom layer of top conductor 400 is a silicide-forming metal such as titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium. Titanium and cobalt are preferred; titanium is most preferred. During an anneal performed to crystallize the silicon, the silicide-forming metal reacts with the silicon of top heavily doped n-type region 116 and forms a silicide layer, for example titanium silicide. FIG. 6 is a probability plot showing current at a read voltage of about 2 volts for a population of such upward-pointing diodes; as will be seen, this population has good uniformity, with very little variation between diodes, and relative large forward current, with median current of about 35.5 microamps. In particular, note that programmed current at 2 volts for all diodes in this population is above about 3 microamps. As described, memory cells in the array described are sensed by applying a read voltage across the memory cell. Ideally the read voltage applied is the same for every memory cell in the array; in practice there will be some variation due to the location of each memory cell within the array. For example, cells located farther from sensing circuitry have a longer interconnect than cells located closer to it. The increased length of the interconnect results in increased resistance, resulting in smaller voltages across the diodes of more distant cells as compared to closer ones. Small variations in the read current of the diode due to variations in the interconnect length, and resistance, are not inherent properties of the diode of the present invention, however. The term device level will refer to a plurality of substantially coplanar devices formed at the same level above a substrate, and generally by the same processing steps; an example of a device level is a memory level including a plurality of substantially coplanar memory cells formed above a substrate. In one example, in a device level including a population of upward-pointing p-i-n diodes formed according to the present invention, the voltage applied across the diode, i.e. between the bottom p-type region and the top n-type region of the diode, is between about 1.8 volts and about 2.2 volts for any diode in the device level, regardless of its location; and current flowing through 99 percent of the diodes in this device level under this applied voltage is at least 1.5 microamps. In other examples, in the present invention a current of about 1.5 microamps is achievable for 99 percent of diodes in a device level when the voltage applied across the diode (between the bottom p-type region and the top n-type region of the diode) is between about 1.1 volts and about 3.0 volts, preferably between about 1.5 volts and about 3.0 volts, most preferably between about 1.8 volts and about 2.2 volts, for example when the semiconductor material is a silicon-germanium alloy such as Si0.8Ge0.2. This population of p-i-n diodes may be a device level having 100,000 p-i-n diodes or more, for example 1,000,000 p-i-n diodes or more. In preferred embodiments, the device level is a memory level comprising memory cells of the present invention, wherein the first memory cells comprise programmed cells and unprogrammed cells. In such a memory array, during use, some cells will be programmed while others are unprogrammed. In a preferred embodiment, when at least half of the memory cells are programmed cells, current flowing through the p-i-n diodes of at least 99 percent of the programmed cells when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps, wherein the first plurality of memory cells includes every memory cell in the first memory level. In more preferred embodiments, the applied voltage is between about 1.8 volts and about 2.2 volts. This memory level of memory cells may include 100,000 cells or more, for example 1,000,000 cells or more, each cell including an upward-pointing p-i-n diode formed according to the present invention. The upward-pointing diode of the present invention can advantageously be used in an array of stacked memory levels sharing conductors, most preferably having upward-pointing diodes alternating with downward-pointing diodes on each memory level. As described in Herner et al., U.S. patent application Ser. No. 11/148,530, “Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material,” filed Jun. 8, 2005, hereby incorporated by reference, when deposited amorphous silicon is crystallized in contact solely with materials with which it has a high lattice mismatch, such as silicon dioxide and titanium nitride, the polycrystalline silicon or polysilicon forms with a high number of crystalline defects, causing it to be high-resistivity. Application of a programming pulse through this high-defect polysilicon apparently alters the polysilicon, causing it to be lower-resistivity. As described further in the '549 application; as well as in Herner, U.S. Pat. No. 7,176,064, “Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide”; and in Herner, U.S. patent application Ser. No. 11/560,283, “Method for Making a P-I-N Diode Crystallized Adjacent to a Silicide in Series with A Dielectric Antifuse,” filed Nov. 15, 2006, hereinafter the '283 application and hereby incorporated by reference, it has been found that when deposited amorphous silicon is crystallized in contact with a layer of an appropriate silicide, for example titanium silicide, cobalt silicide, or a silicide formed of one of the other named silicide-forming metals, the resulting crystallized silicon is much higher quality, with fewer defects, and has much lower resistivity. The lattice spacing of titanium silicide or cobalt silicide is very close to that of silicon, and it is believed that when amorphous silicon is crystallized in contact with a layer of an appropriate silicide at a favorable orientation, the silicide provides a template for crystal growth of silicon, minimizing formation of defects. Unlike the high-defect silicon crystallized adjacent only to materials with which it has a high lattice mismatch, application of a large electrical pulse does not appreciably change the resistivity of this low-defect, low-resistivity silicon crystallized in contact with the silicide layer. In some memory cells using a vertically oriented p-i-n diode, then, as in the '549 application, the diode is formed of higher-defect, higher-resistivity polysilicon, and the memory cell is programmed by changing the resistivity state of the polysilicon. For these high-defect-diode cells, the data state of the memory cell is stored predominantly in the resistivity state of the polysilicon of the diode. In other memory cells, as in the '283 application, the diode is formed of low-defect, low-resistivity silicon, is paired with a companion state-change element (in this case a dielectric rupture antifuse) and the memory cell is programmed by changing the characteristics of the state-change element (by rupturing the antifuse, for example.) The term state-change element is used to describe an element that can take two or more stable, mutually distinguishable states, usually resistivity states, and can either reversibly or irreversibly be switched between them. For these low-defect-diode cells, the data state of the memory cell is stored predominantly in the state-change element, not in the state of the diode. (Note that this discussion has described the use of silicon crystallized adjacent to a silicide. The same effect can be expected for germanium and silicon-germanium crystallized adjacent to a germanide or silicide-germanide.) The upward-pointing p-i-n diodes of the present invention are crystallized in contact with a silicide, and are thus of low-defect, low-resistivity semiconductor material. If the upward-pointing diodes of the present invention, then, are used in memory cells, they are advantageously used when paired with a state-change element, for example an antifuse or a resistivity-switching element. One example of such a resistivity-switching element is a binary metal oxide, such as NixOy, NbxOy, TixOy, HfxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, or AlxNy, as described in Herner et al., U.S. patent application Ser. No. 11/395,995, “Nonvolatile Memory Cell Comprising a Diode and a Resistance-Switching Material,” filed Mar. 31, 2006, and hereby incorporated by reference. Another example of a resistivity-switching element is a carbon nanotube fabric, as described in Herner et al. (atty. docket no. SAND-01193US0), filed on even date herewith. Note that the upward-pointing diodes of the present invention may advantageously be used in many devices, and is not limited to use in memory cells; or, if used in memory cells, is not limited to use in cells like those specifically described herein. A detailed example will be provided describing fabrication of a first memory level formed above a substrate, the memory level comprising memory cells having an upward-pointing diode and high-K dielectric antifuse arranged in series between a bottom conductor and a top conductor, as well fabrication of a second memory level above it comprising downward-pointing diodes, the two memory levels sharing conductors. Details from the '283 application, and from the other incorporated applications, may prove useful in fabrication of this memory level. To avoid obscuring the invention, not all details from these or other incorporated documents will be included, but it will be understood that none of their teaching is intended to be excluded. For completeness, many details, including materials, steps, and conditions, will be provided, but it will be understood by those skilled in the art that many of these details can be changed, augmented or omitted while the results fall within the scope of the invention. EXAMPLE Turning to FIG. 7a, formation of the memory begins with a substrate 100. This substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon, IV-IV compounds like silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VII compounds, epitaxial layers over such substrates, or any other semiconducting material. The substrate may include integrated circuits fabricated therein. An insulating layer 102 is formed over substrate 100. The insulating layer 102 can be silicon oxide, silicon nitride, Si—C—O—H film, or any other suitable insulating material. The first conductors 200 are formed over the substrate 100 and insulator 102. An adhesion layer 104 may be included between the insulating layer 102 and the conducting layer 106 to help conducting layer 106 adhere to insulating layer 102. If the overlying conducting layer 106 is tungsten, titanium nitride is preferred as adhesion layer 104. Conducting layer 106 can comprise any conducting material known in the art, such as tungsten, or other materials, including tantalum, titanium, or alloys thereof. Once all the layers that will form the conductor rails have been deposited, the layers will be patterned and etched using any suitable masking and etching process to form substantially parallel, substantially coplanar conductors 200, shown in FIG. 7a in cross-section. Conductors 200 extend out of the page. In one embodiment, photoresist is deposited, patterned by photolithography and the layers etched, and then the photoresist removed using standard process techniques. Next a dielectric material 108 is deposited over and between conductor rails 200. Dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide deposited by a high-density plasma method is used as dielectric material 108. Finally, excess dielectric material 108 on top of conductor rails 200 is removed, exposing the tops of conductor rails 200 separated by dielectric material 108, and leaving a substantially planar surface. The resulting structure is shown in FIG. 7a. This removal of dielectric overfill to form the planar surface can be performed by any process known in the art, such as chemical mechanical planarization (CMP) or etchback. In an alternative embodiment, conductors 200 could be formed by a Damascene method instead. Turning to FIG. 7b, next optional conductive layer 110 is deposited. Layer 110 is a conductive material, for example titanium nitride, tantalum nitride, or tungsten. This layer may be any appropriate thickness, for example about 50 to about 200 angstroms, preferably about 100 angstroms. In some embodiments barrier layer 110 may be omitted. Next, in this example, a thin layer 118 of a dielectric material or dielectric stack is deposited to form a dielectric rupture antifuse. In one embodiment, a high-K dielectric, such as HfO2, A12O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, or ZrSiAlON, is deposited, for example by atomic layer deposition. HfO2 and Al2O3 are preferred. If HfO2 is used, layer 118 preferably has a thickness between about 5 and about 100 angstroms, preferably about 40 angstroms. If Al2O3 is used, layer 118 preferably has a thickness between about 5 and about 80 angstroms, preferably about 30 angstroms. In alternative embodiments, the dielectric rupture antifuse may comprise silicon dioxide. Conductive layer 111 is deposited on layer 118. It can be any appropriate conductive material, for example titanium nitride, with any appropriate thickness, for example about 50 to about 200 angstroms, preferably about 100 angstroms. In some embodiments conductive layer 111 may be omitted. Next semiconductor material that will be patterned into pillars is deposited. The semiconductor material can be silicon, germanium, a silicon-germanium alloy, or other suitable semiconductors, or semiconductor alloys. For simplicity, this description will refer to the semiconductor material as silicon, but it will be understood that the skilled practitioner may select any of these other suitable materials instead. Bottom heavily doped region 112 can be formed by any deposition and doping method known in the art. The silicon can be deposited and then doped, but is preferably doped in situ by flowing a donor gas providing a p-type dopant atoms, for example boron, during deposition of the silicon. In preferred embodiments, the donor gas is BCl3, and p-type region 112 is preferably doped to a concentration of about 1×1021 atoms/cm3. Heavily doped region 112 is preferably between about 100 and about 800 angstroms thick, most preferably about 200 angstroms thick. Intrinsic or lightly doped region 114 can be formed next by any method known in the art. Region 114 is preferably silicon and has a thickness between about 1200 and about 4000 angstroms, preferably about 3000 angstroms. In general p-type dopants such as boron tend to promote crystallization; thus the silicon of heavily doped region 112 is like to be polycrystalline as deposited. Intrinsic region 114, however, is preferably amorphous as deposited. Semiconductor regions 114 and 112 just deposited, along with underlying conductive layer 111, dielectric rupture antifuse 118, and conductive layer 110, will be patterned and etched to form pillars 300. Pillars 300 should have about the same pitch and about the same width as conductors 200 below, such that each pillar 300 is formed on top of a conductor 200. Some misalignment can be tolerated. Pillars 300 can be formed using any suitable masking and etching process. For example, photoresist can be deposited, patterned using standard photolithography techniques, and etched, then the photoresist removed. Alternatively, a hard mask of some other material, for example silicon dioxide, can be formed on top of the semiconductor layer stack, with bottom antireflective coating (BARC) on top, then patterned and etched. Similarly, dielectric antireflective coating (DARC) can be used as a hard mask. The photolithography techniques described in Chen, U.S. application Ser. No. 10/728,436, “Photomask Features with Interior Nonprinting Window Using Alternating Phase Shifting,” filed Dec. 5, 2003; or Chen, U.S. application Ser. No. 10/815,312, Photomask Features with Chromeless Nonprinting Phase Shifting Window,” filed Apr. 1, 2004, both owned by the assignee of the present invention and hereby incorporated by reference, can advantageously be used to perform any photolithography step used in formation of a memory array according to the present invention. The diameter of the pillars 300 can be as desired, for example between about 22 nm and about 130 nm, preferably between about 32 nm and about 80 nm, for example about 45 nm. Gaps between pillars 300 are preferably about the same as the diameter of the pillars. Note that when a very small feature is patterned as a pillar, the photolithography process tends to round corners, such that the cross-section of the pillar tends to be circular, regardless of the actual shape of the corresponding feature in the photomask. Dielectric material 108 is deposited over and between the semiconductor pillars 300, filling the gaps between them. Dielectric material 108 can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon dioxide is used as the insulating material. Next the dielectric material on top of pillars 300 is removed, exposing the tops of pillars 300 separated by dielectric material 108, and leaving a substantially planar surface. This removal of dielectric overfill can be performed by any process known in the art, such as CMP or etchback. After CMP or etchback, ion implantation is performed, forming heavily doped n-type top regions 116. The n-type dopant is preferably a shallow implant of arsenic, with implant energy of, for example, 10 keV, and dose of about 3×1015/cm2. This implant step completes formation of diodes 302. Note that some thickness, for example about 300 to about 800 angstroms of silicon is lost during CMP; thus the finished height of diode 302 may be between about 800 and about 4000 angstroms, for example about 2500 angstroms for a diode having a feature size of about 45 nm. Turning to FIG. 7c, next a layer 120 of a silicide-forming metal, for example titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium, is deposited. Layer 120 is preferably titanium or cobalt; if layer 120 is titanium, its thickness is preferably between about 10 and about 100 angstroms, most preferably about 20 angstroms. Layer 120 is followed by titanium nitride layer 404. Layer 404 is preferably between about 20 and about 100 angstroms, most preferably about 80 angstroms. Next a layer 406 of a conductive material, for example tungsten, is deposited; for example this layer may be about 1500 angstroms of tungsten formed by CVD. Layers 406, 404, and 120 are patterned and etched into rail-shaped top conductors 400, which preferably extend in a direction perpendicular to bottom conductors 200. The pitch and orientation of top conductors 400 is such that each conductor 400 is formed on top of and contacting a row of pillars 300, and conductors 400 preferably have about the same width as pillars 300. Some misalignment can be tolerated. Next a dielectric material (not shown) is deposited over and between conductors 400. The dielectric material can be any known electrically insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In a preferred embodiment, silicon oxide is used as this dielectric material. Referring to FIG. 7c, note that layer 120 of a silicide-forming metal is in contact with the silicon of top heavily doped region 116. During subsequent elevated temperature steps, the metal of layer 120 will react with some portion of the silicon of heavily doped region p-type 116 to form a silicide layer (not shown), which is between the diode and top conductor 400; alternatively this silicide layer can be considered to be part of top conductor 400. This silicide layer forms at a temperature lower than the temperature required to crystallize silicon, and thus will form while intrinsic region 114 and heavily doped p-type region 116 are still largely amorphous. If a silicon-germanium alloy is used for top heavily doped region 116, a silicide-germanide layer may form, for example of cobalt silicide-germanide or titanium silicide-germanide. Similarly, if germanium is used, a germanide will form. In the example just described, the diodes 302 of FIG. 7c are upward-pointing, comprising a bottom heavily doped p-type region, a middle intrinsic region, and top heavily doped n-type region. In preferred embodiments, the next memory level to be monolithically formed above this one shares conductor 400 with the first memory level just formed; i.e., the top conductor 400 of the first memory level serves as the bottom conductor of the second memory level. If conductors are shared in this way, then the diodes in the second memory level are preferably downward-pointing, comprising a bottom heavily doped n-type region, a middle intrinsic region, and a top heavily doped p-type region. Turning to FIG. 7d, next optional conductive layer 210, high-K dielectric antifuse layer 218, and optional conductive layer 211 are formed, preferably of the same materials, the same thicknesses, and using the same methods as layers 110, 118, and 111, respectively, of pillars 300 in the first memory level. Diodes are formed next. Bottom heavily doped region 212 can be formed by any deposition and doping method known in the art. The silicon can be deposited and then doped, but is preferably doped in situ by flowing a donor gas providing n-type dopant atoms, for example phosphorus, during deposition of the silicon. Heavily doped region 212 is preferably between about 100 and about 800 angstroms thick, most preferably about 100 to about 200 angstroms thick. The next semiconductor region to be deposited is preferably undoped. In deposited silicon, though, n-type dopants such as phosphorus exhibit strong surfactant behavior, tending to migrate toward the surface as the silicon is deposited. Deposition of silicon will continue with no dopant gas provided, but phosphorus atoms migrating upward, seeking the surface, will unintentionally dope this region. As described in Herner, U.S. patent application Ser. No. 11/298,331, “Deposited Semiconductor Structure to Minimize N-Type Dopant Diffusion and Method of Making,” filed Dec. 9, 2005, hereby incorporated by reference, the surfactant behavior of phosphorus in deposited silicon is inhibited with the addition of germanium. Preferably a layer of a silicon-germanium alloy including at least 10 at % germanium is deposited at this point, for example about 200 angstroms of Si0.8Ge0.2, which is deposited undoped, with no dopant gas providing phosphorus. This thin layer is not shown in FIG. 7d. Use of this thin silicon-germanium layer minimizes unwanted diffusion of n-type dopant into the intrinsic region to be formed, maximizing its thickness. A thicker intrinsic region minimizes leakage current across the diode when the diode is under reverse bias, reducing power loss. This method allows the thickness of the intrinsic region to be increased without increasing the overall height of the diode. As will be seen, the diodes will be patterned into pillars; increasing the height of the diode increases the aspect ratio of the etch step forming these pillars and the step to fill gaps between them. Both etch and fill are more difficult as aspect ratio increases. Intrinsic region 214 can be formed next by any method known in the art. Region 214 is preferably silicon and preferably has a thickness between about 1100 and about 3300 angstroms, preferably about 1700 angstroms. The silicon of heavily doped region 212 and intrinsic region 214 is preferably amorphous as deposited. Semiconductor regions 214 and 212 just deposited, along with underlying conductive layer 211, high-K dielectric layer 218, and conductive layer 210, will be patterned and etched to form pillars 600. Pillars 600 should have about the same pitch and about the same width as conductors 400 below, such that each pillar 600 is formed on top of a conductor 400. Some misalignment can be tolerated. Pillars 600 can be patterned and etched using the same techniques used to form pillars 300 of the first memory level. Dielectric material 108 is deposited over and between the semiconductor pillars 600, filling the gaps between them. As in the first memory level, the dielectric material 108 on top of pillars 600 is removed, exposing the tops of pillars 600 separated by dielectric material 108, and leaving a substantially planar surface. After this planarization step, ion implantation is performed, forming heavily doped p-type top regions 116. The p-type dopant is preferably a shallow implant of boron, with an implant energy of, for example, 2 keV, and dose of about 3×1015/cm2. This implant step completes formation of diodes 602. Some thickness of silicon is lost during the CMP step, so the completed diodes 602 have a height comparable to that of diodes 302. Top conductors 700 are formed in the same manner and of the same materials as conductors 400, which are shared between the first and second memory levels. A layer 220 of a silicide-forming metal is deposited, followed by titanium nitride layer 704 and layer 706 of a conductive material, for example tungsten. Layers 706, 704, and 220 are patterned and etched into rail-shaped top conductors 700, which preferably extend in a direction substantially perpendicular to conductors 400 and substantially parallel to conductors 200. Preferably after all of the memory levels have been formed, a single crystallizing anneal is performed to crystallize the semiconductor material of diodes 302, 602, and those diodes formed on additional levels, for example at 750 degrees C. for about 60 seconds, though each memory level can be annealed as it is formed. The resulting diodes will generally be polycrystalline. Since the semiconductor material of these diodes is crystallized in contact with a silicide or silicide-germanide layer with which it has a good lattice match, the semiconductor material of diodes 302, 602, etc. will be low-defect and low-resistivity. In the embodiment just described, conductors were shared between memory levels; i.e. top conductor 400 of the first memory level serves as the bottom conductor of the second memory level. In other embodiments, an interlevel dielectric can be formed above the first memory level of FIG. 7c, its surface planarized, and construction of a second memory level begun on this planarized interlevel dielectric, with no shared conductors. In the example given, the diodes of the first memory level were upward-pointing, with p-type silicon on the bottom and n-type on top, while the diodes of the second memory level were reversed, pointing downward with n-type silicon on the bottom and p-type on top. In embodiments in which conductors are shared, diode types preferably alternate, upward on one level and downward on the next. In embodiments in which conductors are not shared, diodes may be all one type, either upward- or downward-pointing. The terms upward and downward refer to the direction of current flow when the diode is under forward bias. In some embodiments, it may be preferred for the programming pulse to be applied with the diode in reverse bias. This may have advantages in reducing or eliminating leakage across the unselected cells in the array, as described in Kumar et al., U.S. patent application Ser. No. 11/496,986, “Method For Using A Memory Cell Comprising Switchable Semiconductor Memory Element With Trimmable Resistance,” filed Jul. 28, 2006, owned by the assignee of the present invention and hereby incorporated by reference. Fabrication of two memory levels above a substrate has been described. Additional memory levels can be formed in the same manner, forming a monolithic three dimensional memory array. A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a wafer, with no intervening substrates. The layers forming one memory level are deposited or grown directly over the layers of an existing level or levels. In contrast, stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, “Three dimensional structure memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays. A monolithic three dimensional memory array formed above a substrate comprises at least a first memory level formed at a first height above the substrate and a second memory level formed at a second height different from the first height. Three, four, eight, or indeed any number of memory levels can be formed above the substrate in such a multilevel array. An alternative method for forming a stacked memory array in which conductors are formed using Damascene construction, rather than using subtractive techniques as in the examples provided, is described in Radigan et al., U.S. patent application Ser. No. 11/444,936, “Conductive Hard Mask to Protect Patterned Features During Trench Etch,” filed May 31, 2006, assigned to the assignee of the present invention and hereby incorporated by reference. The methods of Radigan et al. may be used instead to form an array according to the present invention. In the methods of Radigan et al., a conductive hard mask is used to etch the diodes beneath them. In adapting this hard mask to the present invention, in preferred embodiments the bottom layer of the hard mask, which is in contact with the silicon of the diode, is preferably titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium. During anneal, then, a silicide forms, providing the silicide crystallization template. In this embodiment, the ion implantation step to form the top heavily doped p-type region takes place before the patterning step to form the pillars. In the examples provided so far, the silicide is formed at the top contact of the diode. In alternative embodiments, it may be formed elsewhere, for example at the bottom contact. For example, the silicon of the diode can be deposited directly on a silicide-forming metal, and a state-change element, such as an antifuse or a resistivity-switching element (carbon nanotube fabric or a binary metal oxide, for example) formed on top of the diode. The upward-pointing diode of the present invention has been described as used in a one-time programmable memory cell (when paired with an antifuse) or in a rewriteable memory cell (when paired with a resistivity-switching element.) It will be understood, however, it is impractical to list all possible uses of the diode of the present invention, and that these examples are not intended to be limiting. Detailed methods of fabrication have been described herein, but any other methods that form the same structures can be used while the results fall within the scope of the invention. The foregoing detailed description has described only a few of the many forms that this invention can take. For this reason, this detailed description is intended by way of illustration, and not by way of limitation. It is only the following claims, including all equivalents, which are intended to define the scope of this invention.	H	67H01	185H01L	213	36
11724726	US20080150006A1-20080626	Using implanted poly-1 to improve charging protection in dual-poly process	ACCEPTED	20080612	20080626	[]	H01L21336	["H01L21336", "H01L29792"]	7553727	20070316	20090630	438	257000	67400.0	BOOTH	RICHARD	[{"inventor_name_last": "Kwan", "inventor_name_first": "Ming-Sang", "inventor_city": "San Leandro", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Davis", "inventor_name_first": "Bradley Marc", "inventor_city": "Mountain View", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Yang", "inventor_name_first": "Jean Yee-Mei", "inventor_city": "Glendale", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Liu", "inventor_name_first": "Zhizheng", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "He", "inventor_name_first": "Yi", "inventor_city": "Fremont", "inventor_state": "CA", "inventor_country": "US"}]	The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.	1. A method of forming at least a portion of a dual-poly memory core array upon a semiconductor substrate, the method comprising: performing a core implant on the semiconductor substrate; depositing a charge trapping dielectric layer over the semiconductor substrate; forming a first polysilicon layer over the charge trapping dielectric layer; doping of the first polysilicon layer; and performing back end processing. 2. The method of claim 1, wherein forming of a hardmask and patterning of a hardmask are performed subsequent to the doping of the first polysilicon layer. 3. The method of claim 1, wherein the first polysilicon layer is formed to a thickness of between about 500 to 1000 Angstroms 4. The method of claim 1, wherein a second polysilicon layer is formed to a thickness of between about 900 and 1100 Angstroms. 5. The method of claim 1, wherein the first polysilicon layer doping includes an n-type dopant. 6. The method of claim 1, wherein the first polysilicon layer doping is performed at an energy level of around 5 KeV to 15 KeV. 7. The method of claim 1, wherein the first polysilicon layer doping is performed at a dosage of about 1E14/cm2 to 1E15/cm2. 8. The method of claim 1, wherein the first polysilicon layer doping has a resulting dopant concentration of about 2E20/cm3 or less. 9. The method of claim 1, wherein the backend processing comprises at least one of the following: forming a second polysilicon layer, chemical mechanical polishing, forming and patterning hard mask; forming a spacer material, patterning the spacer material, patterning the first polysilicon layer, patterning the composite charge trapping layer, performing bitline implantation, performing high temperature oxide deposition and forming a second polysilicon layer. 10. A method of forming at least a portion of a dual-poly flash memory cell arrangement upon a semiconductor substrate, the method comprising: performing core implantation on the substrate forming a charge trapping dielectric layer over the substrate; forming a first polysilicon layer over the charge trapping dielectric layer; forming a hardmask over the first polysilicon layer; patterning the hardmask to form features; doping the first polysilicon layer; and performing back end processing. 11. The method of claim 9, wherein the forming of a photo resist mask or hardmask and the patterning of a photo resist mask or hardmask are performed prior to the doping of the first polysilicon layer. 12. The method of claim 9, wherein the first polysilicon layer is formed to a thickness of between about 500 to 1000 Angstroms. 13. The method of claim 9, wherein a second polysilicon layer is formed to a thickness of between about 900 to 1100 Angstroms. 14. The method of claim 9, wherein the first polysilicon layer dosing is performed at a dosage of about 1E15/cm2. 15. The method of claim 9, wherein the first polysilicon layer has a resulting dopant concentration of about 2E20/cm3. 16. The method of claim 9, wherein the first polysilicon layer doping includes an n-type dopant. 17. The method of claim 9, wherein a bitline implant is performed at an energy level of about 10 KeV to 40 KeV. 18. The method of claim 10, wherein the backend processing comprises at least one of the following: forming a second polysilicon layer, chemical mechanical polishing, forming and patterning hard mask; forming a spacer material, patterning the spacer material, patterning the first polysilicon layer, patterning the composite charge trapping layer, performing bitline implantation, performing high temperature oxide deposition and forming a second polysilicon layer. 19. A communication device, comprising: a flash memory CPU; the flash memory operatively coupled to the CPU and configured to transfer data to and from the CPU; an input component for entering the data; a display component for displaying information; a plurality of switches; flash memory; and the flash memory is formed by the process of; forming shallow trench isolation structures in the substrate; depositing a composite charge trapping layer over the substrate; forming a first polysilicon layer over the oxide layer; doping the first polysilicon layer; forming and patterning hard mask; forming and patterning spacer material; patterning first polysilicon layer; patterning the composite charge trapping layer; performing bitline implantation; performing high temperature oxide deposition; patterning first polysilicon layer; performing chemical mechanical polishing; forming a second polysilicon layer; and performing back end processing. 20. The method of claim 19, wherein the communication device comprises a computer, a cell phone, a PDA, an MP3 player, and a scanner.	<SOH> BACKGROUND OF THE INVENTION <EOH>It is critical in semiconductor manufacturing and packaging to control wafer level core array threshold voltage (Vt) variation. This is especially true as electronic designs become smaller and more densely packed. In addition, charge can accumulate on a semiconductor surface if the surface is resistive to the point where a catastrophic breakdown or an Electrostatic discharge (ESD) event occurs. ESD events can damage, for example, semiconductors, the photoresist-masks or hard-masks, and the like. Electrostatic discharge can also produce electrical signals or electromagnetic interference (EMI) that interferes with the operation of equipment, such as, the production equipment. These ESD problems can occur, for example, throughout the semiconductor manufacturing and packaging process, including silicon wafer creation, photoresist-mask layering and etching, device manufacturing, and back-end processing, packaging and test. Many of these ESD problems persist through the entire “life” cycle of the semiconductor device. In addition, damage may be more subtle, for example, permanent alteration of the dielectric breakdown properties. Implanted dopant ions, well known in the art, are electrically charged, a consequence of the ion implantation process. Charge imbalance related with ion implantation is attributed to a number of occurrences, for example, ejection of secondary electrons, discharge of other charged species from the wafer, absorption of ions from surrounding area, and the like. The charging properties or effects associated with ion implantation are difficult to model. Furthermore, the charge distribution will fluctuate over the surface of the wafer because of variations in the ion beam, the variable characteristics of the wafer surface, surface areas with different conductivities, excess charge already present on the wafer, and the like. Charge distributions vary over the surface of a wafer, from wafer to wafer, etc. All of these factors contribute to non-uniform charge distributions on the wafer surface which can have serious consequences on semiconductors devices that are continuously being reduced in size. Semiconductor manufacturing technologies will continue to move toward smaller device geometries in the foreseeable future and acceptable ESD levels will continue to decrease with decreasing device dimensions, as well as the need for uniform charge distributions. The use of integrated passive substrate components (e.g., resistors, inductors, capacitors, etc.) offers ESD discharge and charge distribution advantages in semiconductor packaging efficiency, miniaturization, performance, manufacturing, and processing. Decoupling capacitors, for example, act as charge reservoirs and suppress charge buildup and ESD events, promote uniform charge distributions, and the like, by directing charge away from the core array of a flash memory, for example, yet these devices can be expensive to implement in the fabrication process. Thus, there is a need to provide a method which improves the conductivity associated with the poly-1 deposition but which does not suffer from the problems that are currently present with processes employing integrated passive components.	<SOH> SUMMARY OF THE INVENTION <EOH>The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The semiconductors typically employ a solid crystalline material, for example, germanium, silicon, and the like that have an electrical conductivity greater than insulators but less than good conductors. Therefore, when the poly-1 in a dual-bit flash memory process is not yet doped the resistance of the poly-1 is high and as such the poly-1 can not effectively transfer charge buildup to a passive integrated component or charge mitigation device, such as an LV (low voltage) capacitor, for example. The present invention pertains to implementing a dual poly process in forming a transistor based flash memory device. The process utilizes doping the poly-1 prior to poly-2 deposition with or without masking. The doped poly-1 can be utilized to improve the conductivity of the poly-1 layer so that excess charge can be directed to a passive integrated component, for example, a low voltage capacitor, and the like during subsequent processing. The present invention according to one or more aspects pertains to a method to achieve a lower poly resistance, which in turn helps to achieve a more robust charging protection for multi-bit core array. According to one or more aspects of the present invention, a method of doping at least a portion of the poly-1 layer upon a semiconductor substrate is disclosed in order to decrease the resistance of the poly-1 layer during the initial stages of the process. An ESD event or non-uniform charge distribution can take place prior to doping due to electrical charge building up on the substrate and having no pathway to be safely discharged. The method includes doping at least a portion of the poly-1 layer concurrent with or prior to the poly-2 deposition. The deposition can be employed utilizing masking prior to the initial poly-1 doping process or masking after the poly-1 doping. To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.	REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/876,180 which was filed Dec. 20, 2006, entitled USING IMPLANTED POLY-1 TO IMPROVE CHARGING PROTECTION IN DUAL-POLY PROCESS. FIELD OF INVENTION The present invention relates generally to the art of semiconductor devices, and more particularly to electrostatic discharge (ESD) protection in dual-poly processing and to uniform charge distribution on a semiconductor substrate in the formation of flash memory devices. BACKGROUND OF THE INVENTION It is critical in semiconductor manufacturing and packaging to control wafer level core array threshold voltage (Vt) variation. This is especially true as electronic designs become smaller and more densely packed. In addition, charge can accumulate on a semiconductor surface if the surface is resistive to the point where a catastrophic breakdown or an Electrostatic discharge (ESD) event occurs. ESD events can damage, for example, semiconductors, the photoresist-masks or hard-masks, and the like. Electrostatic discharge can also produce electrical signals or electromagnetic interference (EMI) that interferes with the operation of equipment, such as, the production equipment. These ESD problems can occur, for example, throughout the semiconductor manufacturing and packaging process, including silicon wafer creation, photoresist-mask layering and etching, device manufacturing, and back-end processing, packaging and test. Many of these ESD problems persist through the entire “life” cycle of the semiconductor device. In addition, damage may be more subtle, for example, permanent alteration of the dielectric breakdown properties. Implanted dopant ions, well known in the art, are electrically charged, a consequence of the ion implantation process. Charge imbalance related with ion implantation is attributed to a number of occurrences, for example, ejection of secondary electrons, discharge of other charged species from the wafer, absorption of ions from surrounding area, and the like. The charging properties or effects associated with ion implantation are difficult to model. Furthermore, the charge distribution will fluctuate over the surface of the wafer because of variations in the ion beam, the variable characteristics of the wafer surface, surface areas with different conductivities, excess charge already present on the wafer, and the like. Charge distributions vary over the surface of a wafer, from wafer to wafer, etc. All of these factors contribute to non-uniform charge distributions on the wafer surface which can have serious consequences on semiconductors devices that are continuously being reduced in size. Semiconductor manufacturing technologies will continue to move toward smaller device geometries in the foreseeable future and acceptable ESD levels will continue to decrease with decreasing device dimensions, as well as the need for uniform charge distributions. The use of integrated passive substrate components (e.g., resistors, inductors, capacitors, etc.) offers ESD discharge and charge distribution advantages in semiconductor packaging efficiency, miniaturization, performance, manufacturing, and processing. Decoupling capacitors, for example, act as charge reservoirs and suppress charge buildup and ESD events, promote uniform charge distributions, and the like, by directing charge away from the core array of a flash memory, for example, yet these devices can be expensive to implement in the fabrication process. Thus, there is a need to provide a method which improves the conductivity associated with the poly-1 deposition but which does not suffer from the problems that are currently present with processes employing integrated passive components. SUMMARY OF THE INVENTION The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The semiconductors typically employ a solid crystalline material, for example, germanium, silicon, and the like that have an electrical conductivity greater than insulators but less than good conductors. Therefore, when the poly-1 in a dual-bit flash memory process is not yet doped the resistance of the poly-1 is high and as such the poly-1 can not effectively transfer charge buildup to a passive integrated component or charge mitigation device, such as an LV (low voltage) capacitor, for example. The present invention pertains to implementing a dual poly process in forming a transistor based flash memory device. The process utilizes doping the poly-1 prior to poly-2 deposition with or without masking. The doped poly-1 can be utilized to improve the conductivity of the poly-1 layer so that excess charge can be directed to a passive integrated component, for example, a low voltage capacitor, and the like during subsequent processing. The present invention according to one or more aspects pertains to a method to achieve a lower poly resistance, which in turn helps to achieve a more robust charging protection for multi-bit core array. According to one or more aspects of the present invention, a method of doping at least a portion of the poly-1 layer upon a semiconductor substrate is disclosed in order to decrease the resistance of the poly-1 layer during the initial stages of the process. An ESD event or non-uniform charge distribution can take place prior to doping due to electrical charge building up on the substrate and having no pathway to be safely discharged. The method includes doping at least a portion of the poly-1 layer concurrent with or prior to the poly-2 deposition. The deposition can be employed utilizing masking prior to the initial poly-1 doping process or masking after the poly-1 doping. To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a dual bit flash memory device. FIG. 2 is a schematic illustration of a portion of a wordline of a memory core such as may include at least part of one of the cores depicted in FIG. 1. FIG. 3 is a top view of at least a portion of a memory core, such as may include at least part of one of the cores depicted in FIG. 1. FIG. 4 is a cross-sectional isometric illustration of a portion of a dual bit flash memory, such as that taken along line 4-4 of FIG. 3. FIG. 5A is a flow diagram illustrating an example of a methodology for forming a memory device in accordance with one or more aspects of the present invention wherein a poly-1 layer is doped prior to or concurrent with the poly-2 deposition either with or without masking employed prior to the doping process. FIG. 5B is an illustration of the poly-1 process, according to an aspect of the present invention. FIGS. 6-20 are cross-sectional illustrations of memory formed according to one or more aspects of the present invention. FIG. 21 is a graph of the variation in Vt with respect to poly-1 doping, according to yet another aspect of the present invention. FIG. 22 is an isometric view of a device and block diagram according to yet one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION One or more aspects of the present invention are described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the present invention. It may be evident, however, to one skilled in the art that one or more aspects of the present invention may be practiced with a lesser degree of these specific details. In other instances, well-known structures and devices are shown in block diagram or other form in order to facilitate describing one or more aspects of the present invention. The present invention pertains to implementing a dual poly (polysilicon) process in forming a transistor based flash memory device. The process employs utilizing a poly-1 doping process concurrent with or prior to the poly-2 deposition process. The doping process, as mentioned supra, can be performed with or without a masking process performed prior to the doping process. The process facilitates a more uniform charge distribution and a reduction in ESD events allowing more semiconductors to be manufactured and processed without failure, for example. As a result, more devices can be manufactured in a given time frame with a higher yield. In addition the process allows semiconductor devices, for example, flash memory to be manufactured with a more uniform charge distribution resulting in more uniform properties, and the like. In the prior art processes the poly-1 was not doped until after the poly-2 was deposited. The inventors recognized the advantages of doping the poly-1 layer concurrent with or prior to the poly-2 deposition. Those advantages include 1) distributing process induced charges uniformly throughout the core array structures by reducing the poly-1 resistance, and 2) more overall uniform poly-1/poly-2 doping by the end of processing. Referring initially to FIG. 1, a top view of an exemplary dual bit flash EEPROM 100, for example, is illustrated. The memory 100 generally incorporates a semiconductor substrate 102 in which one or further high-density core regions 104 and one or more lower-density peripheral portions are formed. The high-density core regions characteristically include one or more M by N arrays 104 of individually addressable, substantially identical dual bit flash memory cells. The lower-density peripheral portions on the other hand typically include input/output (I/O) circuitry 106 and programming circuitry for selectively addressing the individual memory cells. The programming circuitry is represented in part by and includes one or more x-decoders 108 and one or more y-decoders 110 that collaborate with the I/O circuitry 106 for selectively connecting a source, gate, and/or drain of selected addressed memory cells to predetermined voltages or impedances to effect designated operations on the respective memory cells (e.g., programming, reading, and erasing, and deriving necessary voltages to effect such operations). Turning to FIG. 2, a schematic illustration is presented of a portion 200 of a memory core such as may include at least part of one of the M by N array cores 104 depicted in FIG. 1. The circuit schematic shows a line of memory cells, which includes memory cells 201 through 204 in a virtual ground type implementation, for example. The respective memory cells 201 through 204 are connected to a wordline 206, which serves as a control gate, and pairs of the memory cells share a common bitline. For instance, in the example shown, the memory cell 201 has associated bitlines 208 and 209; the memory cell 202 has associated bitlines 209 and 210; the memory cell 203 has associated bitlines 210 and 211; and the memory cell 204 has associated bitlines 211 and 212. As such, cells 201 and 202 share bitline 209, cells 202 and 203 share bitline 210 and cells 203 and 204 share bitline 211, respectively. Depending upon a signal on the wordline and the connection of the bitlines in a memory cell to an electrical source or drain, the memory cells 201 through 204 are capable of writing, reading, and erasing bits at locations 215 through 222. For example, control of the bit at location 215 is achieved through connection of the drain to the bitline 208 and the source to the bitline 209. Similarly, control of the bit at location 216 is achieved through connection of the drain to the bitline 209 and the source to the bitline 208. It will be appreciated that although adjacent memory cells share common bitlines, the adjacent memory cells do not interfere with each other because the memory cells are typically programmed one at a time and in such instances only one memory cell is active at a time while programming. Referring now to FIG. 3, a top view is presented of at least a portion 300 of a memory core, such as may include at least part of one of the M by N array cores 104 depicted in FIG. 1. The memory 300 is formed upon a semiconductor substrate 102 and has a plurality of implanted bitlines 304 extending substantially parallel to one another, and further includes a plurality of formed wordlines 302 extending substantially in parallel to one another and at substantially right angles to the plurality of implanted bitlines 304. It will be appreciated that the wordlines 302 and bitlines 304 have contacts and interconnections (not shown) to programming circuitry such as may be represented, at least in part, by the x-decoders 108 and y-decoders 110 depicted in FIG. 1. FIG. 4 is a cross-sectional isometric prior art illustration of a portion 400 of a dual bit flash memory, such as that taken along line 4-4 of FIG. 3. A semiconductor substrate 102 upon which the memory is formed is doped with a p-type impurity such as boron, for example, to establish a threshold adjustment implant (Vtadjust) region 402 therein. The threshold adjustment implant provides a region 402 that is more heavily doped than the semiconductor substrate 102. The substrate can, for example, be formed out of silicon and can itself be doped with a p-type impurity. The threshold adjustment implant 402 assists in controlling a threshold voltage of the various cells within the memory 400. A charge-trapping dielectric layer 404 is deposited over the semiconductor substrate 102. The charge-trapping dielectric layer 404 generally can be composed of three separate layers: a first insulating layer 406, a charge-trapping layer 408, and a second insulating layer 410. The first and second insulating layers 406 and 410 are typically formed of an oxide dielectric such as silicon dioxide (SiO2) and the charge-trapping layer 408 is generally formed of a nitride dielectric such as silicon nitride (SixNy). The oxide-nitride-oxide configuration is commonly referred to as an ONO layer for convenience. Alternatively, other types of charge-trapping layers may be employed and are contemplated as falling within the scope of the present invention. First and second conductive bitlines 412 and 414 are depicted in FIG. 4 underlying the charge trapping dielectric layer 404. It will be appreciated that any number of such bitlines can be implanted into the semiconductor substrate 102, and that such bitlines may correspond to the bitlines 304 depicted in FIG. 3. The bitlines are typically formed of an implanted n-type material, such as arsenic, and may include an oxide portion (not shown) in some examples. The first and second conductive bitlines 412 and 414 are spaced apart and define a channel region 416 there-between. First and second conductive wordlines 418, 419 are similarly depicted overlying the charge-trapping dielectric layer 404. It will be appreciated that any number of such wordlines can be formed over the dielectric layer 404, and that such wordlines may correspond to the wordlines 302 depicted in FIG. 3. The wordlines can be formed out of a polysilicon material, for example, where the polysilicon material may be deposited over the dielectric layer 404 and then patterned and etched. Locations 420 and 422 indicate generally where respective bits of data can be stored in one or the cells of the memory 400. It will be appreciated that the channel 416 has an effective length Leff and that the bits 420, 422 will be brought closer together as this length is reduced (e.g., as a result of scaling). As such, the bits themselves may interfere with and/or contaminate one another and operations performed on one bit may affect the other bit should the bits get too close to one another. In addition, if the charge on the conductive wordlines, 418, 419 is non-uniform this can potentially result in errors in storing, reading and erasing of bits in the flash memory. Turning to FIG. 5A, a methodology 500 is illustrated for forming a memory device according to one or more aspects of the present invention. In particular, the memory can be formed with a dual poly process employing doping of the poly-1 layer concurrent with or prior to the deposition of the poly-2 layer. The doping of the poly-1 layer may take place with or without masking the poly-1 surface prior to the doping process. The memory device so formed can, for example, correspond to a portion of a memory core such as may include at least part of one of the M by N array cores depicted in FIG. 1. Although the methodology 500 is illustrated and described hereinafter as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement the methodology in accordance with one or more aspects of the present invention. Further, one or more of the acts may be carried out in one or more separate acts or phases. It will be appreciated that the methodology carried out according to one or more aspects of the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated or described herein. By way of example, the method or variants thereof may be used to fabricate a dual bit memory as illustrated and described below with respect to the figures, as well as to devices not shown or described herein. The memory is formed upon a semiconductor substrate at 502, and a threshold adjustment core implant Vtadjust can be performed to establish a region of the substrate that is more heavily doped than the remainder of the semiconductor substrate. The substrate can, for example, be formed out of silicon and can itself be doped with a p-type impurity such as boron, for example. The threshold adjustment implant may include a greater concentration of and/or a higher energy implant of the same or different p-type dopant utilized in the rest of the substrate, for example, and assists in controlling a threshold voltage of the memory cell. In addition, shallow trench isolation (STI) can be formed, for example, in the substrate. It is to be appreciated that the formation and/or fabrication of STI is well known to those of ordinary skill in the art. At 504 a charge trapping dielectric layer is formed over the semiconductor substrate. The charge trapping dielectric layer may be a multilayer material that may include a first insulating layer, a charge-trapping layer, and a second insulating layer. The first and second insulating layers may be formed of an oxide dielectric such as silicon dioxide (SiO2), for example. The first insulating layer can be formed to a thickness of about 70 Angstroms or less, for example, while the second insulating layer can be formed to a thickness of about 100 Angstroms or less, for example. The charge-trapping layer may be formed of a nitride dielectric such as silicon nitride (SixNy), for example, and may be formed to a thickness between about 60 to 80 Angstroms, for example. The oxide-nitride-oxide configuration is commonly referred to as an ONO layer for convenience. Alternatively, poly-islands or other types of charge trapping dielectrics may be formed in accordance with one or more aspects of the present invention. A first layer of poly (polysilicon) based material(s) is then formed over the charge trapping dielectric layer at 506. This first poly layer (poly-1) can be formed to a thickness of between about 900 to 1100 Angstroms, for example. At 508 the first layer of polysilicon (poly-1, also known as polysilicon-1) can be doped in order to reduce the resistivity of the poly-1. The poly-1 can be doped, for example, utilizing diffusion, in situ doping, ion implantation, and the like. Diffusion doping comprises, for example, depositing a heavily-doped silicon glass over the poly-1 with the glass serving as the source of dopant for the poly-1. The dopant diffusion can take place at a temperature of, for example, 900-1000 deg. C. Ion implantation comprises directly bombarding the poly-1 layer with high-energy ions, for example, while in situ doping employs dopant atoms that are established in the semiconductor during its growth, commonly during epitaxial growth of semiconductor layers, for example. In the case of using ion implantation to dope the poly-1, beside blanket implantation, an implantation mask can also be used to achieve doping to selected area and other techniques known by those of ordinary skill in the art. A layer of hardmask material can be subsequently formed over the poly-1 formation or deposition at 510. An optional antireflective coating (ARC) layer (e.g., of an organic material, such as silicon nitride or silicon oxynitride) can also be formed over the hardmask, and a resist can be formed over the ARC layer to facilitate patterning the hardmask. The ARC layer in particular can assist with mitigating reflection during exposure and thereby improves the fidelity of pattern transfer. The hardmask can, for example, be formed from oxide based material(s) that are applied to a thickness of between about 300 to 700 Angstroms, for example. The spacings within the hardmask can be formed to have respective widths of between about 100 to 140 nanometers, for example. At 512 a layer of spacer material (e.g., oxide based material) is formed over the patterned hardmask. The spacer material can be formed to a thickness of between about 200 to 500 Angstroms, for example, and is utilized to form spacers that assist with establishing narrower buried bitlines. As such, the spacer material is then patterned (e.g., isotropically etched) at 512 to form sidewall spacers adjacent the patterned features of the hardmask, thereby reducing respective spacings between the hardmask features. The spacers can be formed to have respective widths of between about 20 to 40 nanometers, for example. The distance between the spacers defines respective bitline openings having widths somewhere in the neighborhood of around 55 to 85 nanometers, for example. It will be appreciated that should an ARC layer be utilized in patterning the hardmask, the ARC layer would also be patterned and would add to the thickness of the oxide sidewall spacers and would contribute to narrowing the respective bitline openings. The poly-1 is then patterned at 514. The sidewall spacers serve as guides and as such, spacings formed within the poly-1 can have respective widths corresponding to that of the bitline openings. The charge trapping dielectric layer can be similarly patterned at 516 to include spacings having respective widths corresponding to that of the bitline openings. It will be appreciated that the etchants utilized to remove the first and second dielectric layers can also be effective to remove the patterned hardmask features and the sidewall spacers since these features contain the same or a similar type of compound, namely an oxide. Should some traces of the hardmask features remain, these can be stripped or washed away at a later appropriate time. A bitline implant can then, for example, be performed at 518 to establish the buried bitlines within the exposed semiconductor substrate. The bitline implant can include an n-type dopant, such as Arsenic, for example. In one example, the bitlines are formed to a width of about 70 nanometers. A high temperature oxide deposition can then be performed at 520 to fill in the respective spacings formed within the charge trapping dielectric layer. The high temperature oxide deposition can be performed at temperatures between around 700 to 1200 degrees Celsius, for example. The high temperature oxide deposition can cause oxide growth over the respective bitlines while also depositing oxide over the buried bitlines. In one example, about 100 Angstroms of an oxide is grown, while an additional, approximately 100 Angstroms, of an oxide is deposited over the bitlines. A high density plasma (HDP) deposition can be performed (not shown) to fill in the respective spacings formed within the poly-1 with an oxide material. The HDP deposition can, for example, be performed at a temperature of about 300° C. to about 700° C. under a pressure, for example, of about 1-10 mTorr to fill in the first poly spacings. The entire wafer can then be subjected to chemical mechanical polishing (CMP) at 524 to remove any excess oxide and planarize the surface of the structures thereon. At 526 a second layer of poly based material(s) can, for example, then be formed over the poly-1. As with the poly-1, this second poly layer (poly-2) can be formed (not shown) to thickness of between about 900 to 1100 Angstroms, for example. The second poly layer (poly-2) can serve as a wordline material and as such can be patterned into wordlines. Accordingly, the second poly layer can be patterned to establish wordlines over the buried bitlines (e.g., at a substantially 90 degree orientation). The methodology may then continue on for further processing at 528. In addition, processes 510-528 and acts beyond 528 can be referred to as back end processing 530 and can be carried out in numerous ways. Turning now to FIGS. 5B-20, FIG. 5B illustrates a schematic diagram of at least a portion of a memory device at 550, according to another aspect of the present invention. An STI (shallow trench isolation) trench 552 is shown formed in the substrate 554, surrounded on either side by a source/drain 556 and with patterned photoresist 568. A preferred thin oxide capacitor current leakage path 562 by design is illustrated, which supports the discharge of incoming positive charges from the plasma processing environment. The poly-1 is doped in the area 570 where there is no photoresist 568, for example. The current leakage path in the poly-1 can be very resistive without doping of the poly-1. In the situation where the poly-1 is very resistive, an un-wanted current leakage path 564 will become the only or the dominant discharge path. As a result, the core ONO layer 566 will become charged. Doping the poly-1 connection region 560 to reduce poly-1 resistivity will minimize leakage through the core ONO layer 566, and help to avoid excessive changing of the core ONO layer 566. FIG. 6 illustrates an exemplary technique for forming a memory device 600 according to one or more aspects of the present invention is disclosed. In particular, the memory 600 is formed utilizing dual poly layers (e.g., poly-1 and poly-2) wherein the poly-1 can be doped early on in the process. The doping of the poly-1 layer, early in the process has several advantages: 1) distributing process induced charges uniformly throughout the core array structures by reducing the poly-1 resistance, and 2) a more overall uniform poly-1/poly-2 doping by the end of processing. The memory device 600 so formed may, for example, correspond to a portion of a memory core such as may include at least part of one of the M by N array cores depicted in FIG. 1. Initially, a semiconductor substrate 602 upon which the memory is formed can be subjected to a threshold adjustment implant 604 to establish a region 606 of the substrate 602 that is more heavily doped than the remainder of the semiconductor substrate (FIG. 6). The substrate may itself be doped with a p-type dopant such as Boron, for example, and the threshold adjustment implant (Vtadjust) may include a greater concentration of and/or a higher energy implant of the same or different p-type dopant, for example. The threshold adjustment implant 604 assists in controlling a threshold voltage of the memory device 600. The threshold adjustment implant, however, is optional and may be skipped in accordance with the present invention. It is to be appreciated that reference to substrate or semiconductor substrate as used herein can include a base semiconductor wafer (e.g., silicon, SiGe, or an SOI wafer) and any epitaxial layers or other type semiconductor layers formed thereover or associated therewith. It is to be further appreciated that elements depicted herein are illustrated with particular dimensions relative to one another (e.g., layer to layer dimensions and/or orientations) for purposes of simplicity and ease of understanding, and that actual dimensions of the elements may differ substantially from that illustrated herein. A charge trapping dielectric layer 608 is then formed over the semiconductor substrate 602 (FIG. 7). In the example shown, the charge trapping dielectric layer 608 includes a first insulating layer 610, a charge trapping layer 612 and a second insulating layer 614. The first insulating layer 610 can be formed to a thickness of about 70 Angstroms or less, for example, while the second insulating layer 614 can be formed to a thickness of about 100 Angstroms or less, for example. Both the first and second insulating layers can include, for example, silicon dioxide. The charge-trapping layer 612 may be formed of a nitride dielectric such as silicon nitride (SixNy), for example, and may be formed to a thickness between about 60 to 80 Angstroms. The oxide-nitride-oxide configuration is commonly referred to as an ONO layer for convenience. Alternatively, poly-islands or other types of charge trapping dielectrics may be formed in accordance with one or more aspects of the present invention. A first layer of poly based material(s) (poly-1) 616 can then be formed over the charge trapping dielectric layer 608 (FIG. 8). This first poly layer 616 can be formed to a thickness of between about 900 to 1100 Angstroms, for example. The first layer or poly-1 layer can be doped 604 or implanted, as in FIG. 9A, to improve the conductivity of the poly-1 for directing charges to, for example, a passive charge storage device, such as, a low voltage capacitor. The poly-1 layer can be formed (FIG. 9A), where the doping 604 includes, for example, an n-type dopant. In another embodiment of the present invention doping is performed at an energy level of around 5 KeV to 15 KeV. In yet another embodiment of the present invention, a doping or implantation can be performed at a dosage of around 1 E14/cm2 to 1E15/cm2 wherein the dopant concentration can be about 2E20/cm3 or less. A layer of hardmask material 618 can be subsequently formed over the first poly layer 616 (FIG. 9B). An optional antireflective coating (ARC) layer (not shown) that may include an organic material, such as silicon nitride or silicon oxynitride, for example, can be formed over the hardmask 618, and a resist (also not shown) can be formed over the ARC layer to facilitate patterning the hardmask 618. The ARC layer in particular assists with mitigating reflection during exposure and thereby improves the fidelity of pattern transfer. The hardmask 618 can, for example, be formed from oxide based material(s) that are applied to a thickness of between about 300 to 700 Angstroms, for example. The hardmask 618 can then be patterned (e.g., after both the resist and optional ARC layers have been patterned, exposed, etched and/or selectively stripped to form a combined photomask for transferring the pattern onto the hardmask) (FIG. 10). The resulting hardmask features 620 formed (e.g., etched) from the hardmask 618 correspond, at least partially, to buried bitlines which will be formed within the substrate 602. More particularly, respective spacings 622 between the features 620 correspond somewhat to buried bitlines that will be implanted within the substrate 602. The spacings 622 within the hardmask 618 can be formed to have respective widths 624 of between about 100 to 140 nanometers, for example. An optional layer of spacer material 630 (e.g., of oxide based material(s)) can then be formed over the patterned hardmask features 620 and exposed portions of the poly-1 layer 616 (FIG. 11). The spacer material 630 can be formed to a thickness of between about 200 to 500 Angstroms, for example, and is utilized to form spacers that assist with establishing narrower buried bitlines. As such, the spacer material 630 is then patterned (e.g., isotropically etched) to form sidewall spacers 632 adjacent to the patterned features 620 of the hardmask (FIG. 12). The distance between the spacers 632 defines respective bitline openings 634 having widths 636 somewhere in the neighborhood of around 55 to 85 nanometers, for example. The sidewall spacers can have respective widths 638 of between about 20 to 40 nanometers, for example. It will be appreciated that should an ARC layer be utilized in patterning the hardmask 618, the ARC layer would also be patterned and would add to the thickness of the sidewall spacers 632 and thus would contribute to narrowing the respective bitline openings 634. The poly-1 layer 616 is then patterned with the sidewall spacers 632 serving as guides (FIG. 13). As such, spacings 640 formed within the first poly layer 616 can have respective widths 642 corresponding to the widths 636 of the bitline openings 634 (FIG. 12). It will be appreciated that in a three dimensional perspective the first poly layer 616 is patterned into parallel “strips” 644 of first poly material 616. The charge trapping dielectric layer 608 is similarly patterned (FIG. 14) to include spacings 650 having respective widths 652 also corresponding to that 636 of the bitline openings 634 (FIG. 12). It will be appreciated that the etchants utilized to remove the first 610 and second 614 dielectric layers can also be effective to remove the patterned hardmask features 620 and the sidewall spacers 632 (FIG. 13) since these features contain the same or a similar type of compound, namely oxide based materials. Should some traces 656 of the hardmask features remain (FIG. 14), these can be stripped or washed away at a later time to reveal a clean patterned poly-1 layer 644 (FIG. 15A). A bitline implant 660 can be performed to establish the buried bitlines 662 within the semiconductor substrate 602 (FIG. 15B). The bitline implant 660 can include an n-type dopant, such as Arsenic, for example. Similarly, the bitlines 662 can be formed to relatively shallow depths 664 of between about 300 to 500 Angstroms (428, FIG. 4). Additionally, the bitline implant may be performed at a dosage of about 1E15/cm2 for a resulting concentration of about 2E20/cm3, for example. The first poly 616 and ONO 608 layers block the implant 660, and the bitlines 662 are accordingly formed to a width 666 that corresponds substantially to that 636 of the bitline openings 634. This width 666 can be about 70 nanometers, for example (FIG. 4) due, at least in part, to the use of the sidewall spacers 632 (FIG. 12). A high temperature oxide deposition 668 can then be performed to fill the respective spacings 650 formed within the charge trapping dielectric layer 608 with an oxide based material 670 (FIG. 15C). The high temperature oxide deposition can be performed at temperatures between around 700 to 1200 degrees Celsius, for example. The high temperature oxide deposition causes oxide growth over the respective bitlines 662 while also depositing oxide over the buried bitlines. In one example, about 100 Angstroms of an oxide is grown, while an additional approximately 100 Angstroms of an oxide is deposited over the bitlines 662. A high density plasma (HDP) deposition 672 is then performed to fill the respective spacings 640 formed within the first poly layer 616 with an oxide material 674 (FIG. 16A). The HDP deposition 672 can, for example, be performed at a temperature of about 300° C. to about 700° C. and under a pressure of about 1-10 mTorr to fill in the first poly spacings 640. The entire wafer can then be subjected to chemical mechanical polishing (CMP) to remove any excess oxide material 674 and planarize the surface of the structures thereon (FIG. 16B). It will be appreciated that in a three dimensional perspective this results in “strips” of oxide material 674 in parallel with the patterned strips 644 of the first poly material 616. A second layer of poly-2 based material(s) 676 can then be formed over the first poly-1 layer 616 (FIG. 16C). As with the poly-1 layer 616, this poly-2 layer 676 can be formed to thickness of between about 900 to 1100 Angstroms, for example. The poly-2 layer 676 can serve as a wordline material and as such can be patterned into wordlines. Accordingly, the poly-2 layer 676 can then be patterned to establish wordlines 678 over the buried bitlines 662 (FIG. 17). It will be appreciated that the wordlines 678 are formed so as to be oriented at approximately 90 degrees relative to the bitlines 662. This “crossed” orientation allows individual memory cells to be addressed. The illustration depicted in FIG. 17 is accordingly rotated approximately 90 degrees relative to the images illustrated in FIGS. 6-16C. As such, a side view or view along the length of a buried bitline 662 is illustrated in FIG. 17. FIG. 17 can also be thought of as a view into FIG. 16C along lines 16-16 with the poly-2 layer 676 patterned into the wordlines 678. It will be appreciated that since the buried bitlines 662 are substantially parallel to the “strips” 644 of the patterned poly-1 layer 616 as well as the “strips” 674 of oxide material deposited between strips 644, the patterned wordlines 678 are also substantially perpendicular to strips 644, 674. Accordingly, since the wordlines 678 lie immediately over these strips 644, 674, the wordlines may be shorted together by the underlying strips 644 of the patterned first poly layer 616 if these strips 644 are not patterned so as to electrically isolate the overlying wordlines 678 from one another. As such, when the poly-2 layer 676 is patterned to form the wordlines 678, this process continues until underlying portions of the strips 644 between the wordlines 678 are also removed (e.g., to expose the second insulating layer 614). Accordingly, the portions of the strip of oxide material 674a visible in FIG. 17 is revealed by the removed portions of the strip 644a of the first poly layer 616. As such, these visible portions of strip 674a can be set back from the remaining portions of strip 644a by a distance substantially equal to the width 690 of strip 644a (FIG. 17). Referring to FIG. 18, it will be appreciated that the buried bitlines 662 can serve as source and drain regions of the transistor or memory cell 600, and a channel 680 can be defined between these regions. The channel 680 underlies a gate of the transistor, where wordlines generally serve as the gates of transistors operating as memory devices. When a voltage of a sufficient magnitude (e.g., a threshold voltage (Vt)) is applied to the gate of the transistor, electric fields generated within the transistor allow currents to flow between the source and drain regions. This allows charges 682, 684 (which correspond to bits of data) to be stored (programmed) within and/or erased from the charge trapping layer 612. It will be appreciated that dual charges or bits are discussed herein as one or more aspects of the present invention have application to dual bit memory cells. As scaling occurs, however, and channel lengths are correspondingly decreased, the threshold voltage Vt can change. For example, as source and drain regions are brought closer together, smaller and smaller voltages are needed to program and/or erase bits of data. This can promote Vt roll-off and lead to data being unintentionally erased and/or programmed. The shallower bitlines 662, however, serve to mitigate Vt roll-off, thereby providing more predictability as to when data will be programmed and/or erased from the cell 600. Additionally, the oxide regions 670, 674 overlying the bitlines 662 serve to maintain and/or increase a breakdown voltage between the bitlines 662 and the wordlines 678 (e.g., from a more conventional 16V to around 25V). In this manner the transistor 600 exhibits more predictable performance as compared to conventional devices. It will be appreciated that given the substantially perpendicular orientation between the bitlines and the wordlines, a view along the length of the wordline is depicted in FIG. 19. FIG. 19 illustrates the patterned wordlines 678 in the format set forth with respect to FIG. 18, but rotated by about ninety degrees or looking in lines 18-18 of FIG. 18. FIG. 19 is similar to FIG. 17 in that it illustrates the patterned wordlines 678 and is rotated by about 90 degrees relative to corresponding FIG. 19. However, the device depicted in FIG. 19 has more storage capability than the device of FIG. 17. Similarly, FIG. 20 is akin to FIG. 3 in that it illustrates a top view of at least a portion 2400 of a memory core, such as may include at least part of one of the M by N array cores 104 depicted in FIG. 1. Nevertheless, the memory 2000 is condensed in FIG. 20 in accordance with one or more aspects of the present invention. The memory 2000 is formed upon a semiconductor substrate 2002 and has a plurality of implanted bitlines 2004 extending substantially parallel to one another, and further includes a plurality of wordlines 2006 formed over the buried bitlines 2004. The wordlines 2006 extend substantially parallel to one another and at substantially right angles relative to the plurality of implanted bitlines 2004. It will be appreciated that the wordlines 2006 and bitlines 2004 have contacts and interconnections (not shown) to programming circuitry such as may be represented, at least in part, by the x-decoders 108 and y-decoders 110 depicted in FIG. 1. It will also be appreciated that FIG. 18 may, for example, correspond to that which is depicted in FIG. 20 taken along lines 22-22, while FIG. 19 may correspond to that which is depicted in FIG. 20 taken along lines 23-23, for example. Referring to FIG. 21, in one embodiment of the present invention, is a graph at 2100 that illustrates representative Vt data (Vt at a fixed transistor current, at the end of processing) that was obtained, comparing two lots of Vt data. The graph illustrates the variation in Vt, as a range of Vt for each wafer is plotted on a y-axis, while lot 1 and lot 2 with and without doping is plotted on the x-axis. The graph 2100 includes four different exemplary groupings of data points 2102, 2104, 2106 and 2108 corresponding to differing threshold voltages (Vt), for example. The first curve 2102 was obtained for lot 1 by measuring and plotting the threshold voltage without doping the poly-1 layer. The second curve 2104 is representative data plotted based on doping the poly-1 layer of lot 1 and plotting the Vt values. The third curve 1206 represents Vt data plotted on the curve, based on an undoped poly-1 layer of lot 2. Finally, the forth curve 2108 shows Vt data for lot 2 for a poly-1 doped layer. For example, it can be seen in the curve 2102, wherein wafer level threshold voltage varies from 200 mV to 1600 mV over the entire range, whereas the Vt data in graph 2104 is more consistent and only varies by 100 mV to 600 mV. Again, the data for graphs 2106 and 2108 indicates a similar pattern. The undoped Poly-1 layer indicates a wide range of threshold voltage (up to 1600 mV) and in contrast the doped Poly-1 layer shows a tighter distribution of Vt (up to 600 mV). It is apparent from this data that the doping of the Poly-1 layer results in a more consistent threshold voltage. FIG. 22 is an exemplary portable electronic device, for example, a Personal Data Assistant (PDA) 2200 comprising a video display 2202, an input component 2204, a housing 2206, a CPU 2208, a transceiver and/or a receiver 2210, a microphone 2212, a power supply 2214, an audio output device 2216, an audio input 2218, flash memory 2220, various sensors 2222, and speaker(s) 2224. The flash memory 2220 manufactured according to using implanted poly-1 to improve charge protection in a dual-poly process, according to an aspect of the present invention. The audio input device 2218 can be a transducer, for example. The input component 2204 can include a keypad, buttons, dials, pressure keys, and the like. The video display 2202 can be a liquid crystal display, a plasma display, an LED display, and the like, for displaying visual data and information. In accordance with another embodiment of the claimed subject matter, the portable device with flash memory 2220 manufactured according to a thick spacer for BL implant and then remove method, of the present invention, comprises cell phones, memory sticks, flash drive devices, video camcorders, voice recorders, USB flash drives, fax machines, flash memory laptops, MP3 players, digital cameras, home video game consoles, hard drives, memory cards (used as solid-state disks in laptops), and the like. The flash memory 2220 can include random access memory, read only memory, optical memory, audio memory, magnetic memory, and the like. According to one embodiment of the present invention, the CPU 2208 is configured to communicate with the audio input device 2218, the audio output device 2216 and a display component 2226. The display component 2226 can be separate and distinct from the video display 2202. The CPU 2208 can execute control functions based on inputs from the user, entered using the input component 2204, for example. Based on those inputs, for example the display component can display a graph, a photo, a map, a chart, a video, and the like. The PDA 2200 is also configured to output data as an audio signal, for example a song, a message, a warning sound, various tones, recordings, etc. In another embodiment of the present invention the PDA 2200 can communicate with other electronic devices, for example computers, cell phones, other PDAs, and the like. The PDA 2200 is also configured to transmit digital data wirelessly from one user to another. This is done utilizing the transmitter/receiver 2210 to either transmit or receive data. Additionally, sensors 2222 can be utilized to sense data external to the PDA 2200, for example, temperatures, radiation levels, pressures, and the like. It will be further appreciated that any of the layers described herein can be formed in any one or more suitable manners, either alone or in combination, such as with spin-on techniques, sputtering techniques (e.g., magnetron or ion beam sputtering), growth and/or deposition techniques such as chemical vapor deposition (CVD) and/or low pressure chemical vapor deposition (LPCVD), for example. FIG. 15 is an exemplary portable electronic device, for example, a Personal Data Assistant (PDA) 1500 comprising a video display 1502, an input component 1504, a housing 1506, a CPU 1508, a transceiver and/or a receiver 1510, a microphone 1512, a power supply 1514, an audio output device 1516, an audio input 1518, flash memory 1520, various sensors 1522, and speaker(s) 1524. The flash memory 1520 manufactured according to a thin oxide dummy tiling discharge protection method, of the present invention. The audio input device 1518 can be a transducer, for example. The input component 1504 can include a keypad, buttons, dials, pressure keys, and the like. The video display 1502 can be a liquid crystal display, a plasma display, an LED display, and the like, for displaying visual data and information. In accordance with another embodiment of the claimed subject matter, the portable device with flash memory 1520 manufactured according to a thin oxide dummy tiling discharge protection method, of the present invention, comprises cell phones, memory sticks, flash drive devices, video camcorders, voice recorders, USB flash drives, fax machines, flash memory laptops, MP3 players, digital cameras, home video game consoles, hard drives, memory cards (used as solid-state disks in laptops), and the like. The flash memory 1520 can include random access memory, read only memory, optical memory, audio memory, magnetic memory, and the like. According to one embodiment of the present invention, the CPU 1508 is configured to communicate with the audio input device 1518, the audio output device 1516 and a display component 1526. The display component 1526 can be separate and distinct from the video display 1502. The CPU 1508 can execute control functions based on inputs from the user, entered using the input component 1504, for example. Based on those inputs, for example the display component can display a graph, a photo, a map, a chart, a video, and the like. The PDA 1500 is also configured to output data as an audio signal, for example a song, a message, a warning sound, various tones, recordings, etc. In another embodiment of the present invention the PDA 1500 can communicate with other electronic devices, for example computers, cell phones, other PDAs, and the like. The PDA 1500 is also configured to transmit digital data wirelessly from one user to another. This is done utilizing the transmitter/receiver 1510 to either transmit or receive data. Additionally, sensors 1522 can be utilized to sense data external to the PDA 1500, for example, temperatures, radiation levels, pressures, and the like Although the invention has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The invention includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”	H	67H01	185H01L	213	36
11876816	US20080100209A1-20080501	Organic Electroluminescent Display Device	ACCEPTED	20080422	20080501	[]	H01L5154	["H01L5154"]	7982392	20071023	20110719	313	504000	61124.0	PERRY	ANTHONY	[{"inventor_name_last": "Ito", "inventor_name_first": "Masato", "inventor_city": "Mobara", "inventor_state": "", "inventor_country": "JP"}]	To provide an organic electroluminescent display device promoting a color purity of emitted light and promoting a contrast in a top emission type organic electroluminescent display device, there is constructed a constitution including a plurality of pixel electrodes CD arranged at a main face of an insulating substrate SUB, a plurality of organic electroluminescent layers OLE having a multi-layer structure respectively arranged above the plurality of pixel electrodes CD, a light transmitting opposed electrode AD arranged above the organic electroluminescent layer OLE, and a bank BMP arranged between respectives of the plurality of organic electroluminescent layers OLE and including an auxiliary electrode SD in a strip-like shape above the opposed electrode AD.	1. An organic electroluminescent display device having a plurality of pixel electrodes arranged at a main face of an insulating substrate, organic electroluminescent layers having a multi-layer structure respectively arranged above the plurality of pixel electrodes, a light transmitting opposed electrode arranged at an upper layer of the organic electroluminescent layer, and an insulating projection arranged between respectives of the plurality of organic electroluminescent layers and including an organic electroluminescent display device element having a constitution of emitting light from a side of the opposed electrode; wherein an auxiliary electrode which is extended to cover a portion of the insulating projection on the opposed electrode and brought into contact with an upper portion of an extended portion thereof and a width of which is wider than a width of a top portion of the insulating projection. 2. The organic electroluminescent display device according to claim 1, wherein the auxiliary electrode is constructed by a constitution of being arranged substantially concentric with the insulating projection. 3. The organic electroluminescent display device according to claim 1, wherein the auxiliary electrode is constructed by a constitution of including a light absorbing function. 4. The organic electroluminescent display device according to claim 1, wherein the organic electroluminescent layer is constructed by a constitution of including an electron transport layer, a light emitting layer, a hole transport layer and a hole injection layer. 5. The organic electroluminescent display device according to claim 1, wherein the opposed electrode is constituted by V2O5. 6. The organic electroluminescent display device according to claim 5, wherein the organic electroluminescent layer is constructed by a constitution of including an electron transport layer, a light emitting layer, and a hole transport layer.	<SOH> BACKGROUND <EOH>The present invention relates to an organic electroluminescent display device device, particularly relates to an organic electroluminescent display device device including a top emission type organic electroluminescent element.	<SOH> SUMMARY <EOH>According to a top emission type organic electroluminescent display device, depending on an element constitution, a film thickness of an electrode or an organic electroluminescent layer, an influence of interference of light is considerable and it is difficult to promote a luminescence and a contrast. A strictness of a film thickness control of the organic electroluminescent layer is requested in order to alleviate the influence of the interference of light. However, the request incorporates a problem contrary to shortening an operation time period and a reduction in fabrication cost in a fabrication procedure. Further, in addition to the influence of the interference of light, a luminescence non-uniformity is brought about by a resistance of the light transmitting opposed electrode arranged at an upper portion, presence of the luminescence non-uniformity constitutes a considerable factor of hampering large-sized formation of the apparatus and a countermeasure thereagainst has been requested. Further, there poses a problem that the influence of the interference of light makes prevention of reflection difficult and a polarizer is needed to be arranged separately. Furthermore, by the influence of interference of light, in the constitution of multi-color light emittance, there also poses a problem that a color purity of each emitted light is low and a color reproducibility is not sufficient. It is an object of the invention to provide an organic electroluminescent display device resolving the above-described problems having a high luminescence, a high contrast and an excellent color purity. In order to achieve the above-described object, the invention is constructed by a constitution including a light transmitting opposed electrode extended above an insulating projection (hereinafter, refer to as bank) in a shape of a groin for separating respectives of organic electroluminescent layers contiguous to each other from above the organic electroluminescent layer and including an auxiliary electrode above the opposed electrode above the extended portion. Further, the invention provides the auxiliary electrode with a light absorbing function. By constructing the invention by the constitution of including the auxiliary electrode above the opposed electrode above the bank, (1) a resistance value of the opposed electrode can be reduced by the auxiliary electrode and the non-uniformity in the luminance can be resolved. (2) Reflection of external light and generated (emitted) light can be reduced, color purities and luminances of respectives of generated light can be promoted and a contrast can be promoted. (3) Unnecessary emitted light can be shielded, and therefore, rates of emitting blue, green, red components of light are increased and color purities of respectives of RGB of emitted light are promoted. (4) Color interference of light can be reduced, and therefore, a polarizer is not made to be indispensable separately but can be omitted and not only cost is reduced but also a luminance can be expected to promote. (5) A color reproducing range as a full color organic electroluminescent display device is enlarged. (6) The apparatus is thinned and further light-weighted, and therefore, an applicable product range can be enlarged.	CROSS-REFERENCE TO RELATED APPLICATIONS The disclosure of Japanese Patent Application No. 2006-289491 filed on (2006 Oct. 25) including the claims, the specification, the drawings and the abstract is incorporated herein by reference in its entirely. BACKGROUND The present invention relates to an organic electroluminescent display device device, particularly relates to an organic electroluminescent display device device including a top emission type organic electroluminescent element. DESCRIPTION OF RELATED ART As a display device device of a flat panel type, a liquid crystal display device device (LCD), a plasma display device panel (PDP), a field emission type display device device (FED), an organic electroluminescent display device device (OLED) or the like is reduced into practice or brought into an application research stage. Among them, an organic electroluminescent display device device is an extremely promising display device device as a display device device in the future to constitute a typical example of a thinned/light-weighted emissive display device device. There are so-to-speak a bottom emission type and a top emission type in an organic electroluminescent display device. According to an organic electroluminescent display device of a bottom emission type, there is constituted an organic electroluminescent element by a light emitting mechanism successively laminated with a transparent electrode (ITO or the like) as a first electrode or one electrode, multi-layer organic films (also referred to as organic electroluminescent layer) for emitting light by applying an electric field, and a reflecting metal electrode as a second electrode or other electrode at a main face of an insulating substrate constituting a TFT substrate and preferably constituted by a glass substrate. A number of the organic electroluminescent elements are aligned in a matrix shape, other substrate or an encapsulating film referred to as an encapsulating can is provided to cover the structure of laminating these, and the light emitting structure is blocked from an external atmosphere. Further, for example, an anode is constituted by the transparent electrode, a cathode is constituted by the metal electrode and by applying an electric field between the both electrodes, a carrier (electron and hole) are injected into the organic multi-layer film and the organic multi-layer film emits light. There is constructed a constitution of emitting the emitted light from a side of the glass substrate to outside. On the other hand, the top emission type organic electroluminescent display device is characterized by a constitution in which the one electrode is constituted by the reflecting metal electrode, the other electrode is constituted by the transparent electrode of ITO or the like, a light emitting layer emits light by applying an electric field between the two electrodes, and the emitted light is emitted from the side of the other electrode. The top emission type is characterized in that a top side of a driving circuit above the insulating substrate can also be utilized as a light emitting area. Further, according to the top emission type, as a constitution in correspondence with the encapsulating can in the bottom emission type, a transparent plate preferably constituted by a glass plate can be used. With regard to an organic electroluminescent display device of this kind, the following Patent Reference 1 discloses a technology with regard to a surface treatment of a film suitable for an ink jet process in fabricating a top emission type organic electroluminescent display device element, and the following Patent Reference 2 discloses a technology in which a light emitting area comprising an organic light emitting layer formed on one electrode and other electrode arranged on a substrate is surrounded by a bank of an inorganic insulating film having a thin film thickness and a small taper, edge growth is eliminated by reducing a stepped difference of the bank, stray light from a contiguous pixel is prevented from being reflected and a bench stepping of the electrode is avoided, respectively. [Patent Reference 1] JP-A-2004-127551 [Patent Reference 2] JP-A-2005-5227 (corresponding US Patent Publication No. 2004-252088) SUMMARY According to a top emission type organic electroluminescent display device, depending on an element constitution, a film thickness of an electrode or an organic electroluminescent layer, an influence of interference of light is considerable and it is difficult to promote a luminescence and a contrast. A strictness of a film thickness control of the organic electroluminescent layer is requested in order to alleviate the influence of the interference of light. However, the request incorporates a problem contrary to shortening an operation time period and a reduction in fabrication cost in a fabrication procedure. Further, in addition to the influence of the interference of light, a luminescence non-uniformity is brought about by a resistance of the light transmitting opposed electrode arranged at an upper portion, presence of the luminescence non-uniformity constitutes a considerable factor of hampering large-sized formation of the apparatus and a countermeasure thereagainst has been requested. Further, there poses a problem that the influence of the interference of light makes prevention of reflection difficult and a polarizer is needed to be arranged separately. Furthermore, by the influence of interference of light, in the constitution of multi-color light emittance, there also poses a problem that a color purity of each emitted light is low and a color reproducibility is not sufficient. It is an object of the invention to provide an organic electroluminescent display device resolving the above-described problems having a high luminescence, a high contrast and an excellent color purity. In order to achieve the above-described object, the invention is constructed by a constitution including a light transmitting opposed electrode extended above an insulating projection (hereinafter, refer to as bank) in a shape of a groin for separating respectives of organic electroluminescent layers contiguous to each other from above the organic electroluminescent layer and including an auxiliary electrode above the opposed electrode above the extended portion. Further, the invention provides the auxiliary electrode with a light absorbing function. By constructing the invention by the constitution of including the auxiliary electrode above the opposed electrode above the bank, (1) a resistance value of the opposed electrode can be reduced by the auxiliary electrode and the non-uniformity in the luminance can be resolved. (2) Reflection of external light and generated (emitted) light can be reduced, color purities and luminances of respectives of generated light can be promoted and a contrast can be promoted. (3) Unnecessary emitted light can be shielded, and therefore, rates of emitting blue, green, red components of light are increased and color purities of respectives of RGB of emitted light are promoted. (4) Color interference of light can be reduced, and therefore, a polarizer is not made to be indispensable separately but can be omitted and not only cost is reduced but also a luminance can be expected to promote. (5) A color reproducing range as a full color organic electroluminescent display device is enlarged. (6) The apparatus is thinned and further light-weighted, and therefore, an applicable product range can be enlarged. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plane sectional view for explaining an outline structure of an embodiment of an organic electroluminescent display device according to the invention; FIG. 2 is an enlarged sectional view taken along a line A-A of FIG. 1; FIG. 3 is a sectional view enlarging an essential portion of FIG. 2; FIG. 4 is a sectional view enlarging an essential portion for explaining other example of an organic electroluminescent layer used in an organic electroluminescent display device according to the invention; FIG. 5 is a sectional view enlarging an essential portion for explaining still other example of an organic electroluminescent layer used in an organic electroluminescent display device according to the invention; FIG. 6 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of an organic electroluminescent display device according to the invention; FIG. 7 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; FIG. 8 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; FIG. 9 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; FIG. 10 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; FIG. 11 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; FIG. 12 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other embodiment of an organic electroluminescent display device according to the invention; and FIG. 13 is a schematic sectional view for explaining an outline structure of still other embodiment of an organic electroluminescent display device according to the invention. DETAILED DESCRIPTION OF THE INVENTION Embodiments of the invention will be explained in details in reference to the drawings of examples as follows. EXAMPLE 1 FIG. 1 through FIG. 3 are schematic views for explaining an outline structure of an example of an organic electroluminescent display device of the invention, FIG. 1 is a plane view, FIG. 2 is an enlarged sectional view taken along a line A-A of FIG. 1, and FIG. 3 is a sectional view enlarging an organic electroluminescent layer of FIG. 2. In FIG. 1 through FIG. 3, reference notation AD designates an opposed electrode (anode electrode), notation CD designates a pixel electrode (cathode electrode), notation BMP designates a bank, notation OLE designates an organic electroluminescent layer, notation IB designates an insulating flattening film, notation IC designates an insulating film, notation FG designates a first gate, notation SG designates a second gate, notation GI designates a gate insulating film, notation AL designates a wiring between switching elements, notation ALS designates a wiring between switching elements (a portion serving also as a light shield), and notation SUB designates an insulating substrate. The insulating substrate SUB is a substrate preferably constituted by transparent glass formed with silicon nitride SiN, silicon oxide SiO2 at a main face thereof to constitute the above-described TFT substrate. The first gate FG is formed at a switching element region on the film of silicon oxide SiO2 by patterning a semiconductor film. The gate insulating film GI is formed to cover the first gate FG, the second gate SG is patterned on the gate insulating film GI, and the insulating flattening film IB is formed to cover thereon. The wiring AL indicates a wiring between switching elements constituting a drain electrode of the switching element (a wiring between switches, a signal wiring, a drain wiring) to constitute drain electrode of the switching elements, further, the wiring ALS indicates a source electrode and a wiring and shield member between switching elements (a wiring and shield member between switches serving also as a shield member) and is connected to the first gate FG through a contact hole penetrating the flattening film IB and the gate insulating film GI. The insulating film IC is formed to cover the wiring between switches AL and the wiring and shield member between switches ALS. The pixel electrode CD in a flat plate shape connected to the wiring between switches and shield member ALS through the contact hole provided at the insulating film IC. Here, the pixel electrode CD is the cathode electrode. The pixel electrode CD is constituted by, for example, an Mg—Ag alloy and is arranged in a shape of a matrix. The organic electroluminescent layer OLE constituting a light emitting area is arranged to laminate on the pixel electrode CD by being surrounded by the insulating projection (hereinafter, referred to as bank) BMP in a shape of a groin. The organic electroluminescent layer OLE is arranged in a shape of a matrix having a constitution of aligning RGB as one unit (pixel) in X direction and vertically aligning the same color in Y direction. The bank BMP is constituted by an inorganic insulating material of, for example, a silicon oxide film, a silicon nitride film or the like and is constituted by a shape having an opening portion (bank opening) at the light emitting area. Therefore, the bank BMP is constituted by a shape having a recess at the opening portion. In this way, according to the organic electroluminescent display device of the example, the light emitting areas of the organic electroluminescent layers OLE of the pixels contiguous to each other are separated by the bank BMP comprising, for example, an inorganic insulating film. The light transmitting opposed electrode AD comprising, for example, an ITO film is arranged on the organic electroluminescent layer OLE constituting the light emitting area. Here, the opposed electrode AD is an anode electrode. The opposed electrode AD is extended continuously to a side of the bank BMP on the organic electroluminescent layer OLE and is arranged by continuously cover a top face from a side wall of the bank BMP. Further, a portion of a portion on the opposed electrode AD excluding the light emitting area is laminated to arrange with an auxiliary electrode SD including a conductive material such as Al, Ag by a predetermined pattern. The auxiliary electrode SD and the opposed electrode AD are conducted and the auxiliary electrode SD is provided with a function as an auxiliary wiring of the opposed electrode AD. That is, according to the example, as the auxiliary electrode SD, auxiliary electrodes SDy1 through SDy3 in a strip-like shape are arranged to be laminated on the opposed electrode AD at positions in correspondence with the bank BMP between pixels and concentric with the bank BMP. Further, end portions in longitudinal directions of the auxiliary electrodes SDy1 through SDy3 are connected to a power source circuit, not illustrated. A width Wsx in X direction (width direction) of the auxiliary electrode SD is formed to be wider than a width Wbx in the same direction of the top face of the bank BMP. On the other hand, the auxiliary electrodes are constructed by a constitution continuous in Y direction (longitudinal direction) in a strip-like shape. In forming the auxiliary electrode SD, a technology well-known in a background art of a photolithography technology or the like can be utilized. When the opposed electrode AD is operated, the auxiliary electrode SD is operated as a portion of the electrode to contribute to resolve a non-uniformity in a luminance of a display screen. By making the width Wsx of the auxiliary electrode SD wider than the width Wbx of the top face of the bank BMP, there is provided a characteristic capable of controlling a light emitting amount of an entire face of the screen by controlling the light emitting area and capable of increasing a capacity of conducting electricity to the auxiliary electrode SD. When the auxiliary electrode SD is arranged by maximally utilizing an arrangeable space, the function as an auxiliary wiring can effectively and fully utilized. Further, when the auxiliary electrode SD is formed by a conductive film having a light absorption function, an effect of promoting a contrast or the like can be expected similar to a black matrix (BM) film in a general display device. Next, FIG. 3 shows details of an example of the organic electroluminescent layer OLE arranged at inside of the bank opening of the bank BMP. The organic electroluminescent layer OLE shown in FIG. 3 is arranged with an electron transport layer ETL to be brought into contact with the pixel electrode CD, a light emitting layer EML, a hole transport layer HTL, and a hole injection layer HIL are successively and respectively laminated thereabove, and the topmost layer is arranged with the opposed electrode AD over an entire face thereof. The organic electroluminescent layer OLE is formed to be brought into contact with an inner edge of the bank opening. In the above-described constitution, the transparent opposed electrode AD functions as an anode, the pixel electrode CD functions as the cathode, a transparent electrode material having a high work function may be used for the transparent electrode AD constituting the anode and although ITO mentioned above is general therefor, other transparent conductive substance may be used therefor. Al, Mg, an MG/Ag alloy or an Al/Li alloy or the like having a low work function can be used for the pixel electrode CD constituting the cathode. Further, in order to promote a property, not a single substance of Al but an alkaline metal compound of extremely thin lithium fluoride (LiF) or the like may be used between Al and an organic layer. Further, it is preferable to constitute the pixel electrode CD by a material having a low reflectance of light in order to restrain reflection of light emitted from the light emitting layer. The light emitting layer EML uses a material for emitting light by a desired color when a predetermined voltage is applied between the transparent opposed electrode AD constituting the anode and the pixel electrode CD constituting the cathode. As a material of the light emitting layer EML, for emitting red color light, for example, the light emitting layer can use Alq3 (tris (8-quinolinolate) aluminum) dispersed with DCM-1 (4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4 H-pyran), for emitting green color light, the light emitting layer can use, for example, Alq3, Bebq, Alq3 doped by quinacridone, for emitting blue color, the light emitting layer can use, for example, DPVBi (4,4′-bis(2,2-diphenylvinyl) biphenyl), or a material comprising DPVBi and BCzVBi (4,4′-bis (2-carbazole vinylene) biphenyl), or a material doped by constituting a host by distyrylallylene derivative and constituting a guest by distyrylamine derivative. Further, in each of the light emitting layer EML, the hole injection layer HIL can use CuPc (copper phthalocyanine), the hole transport layer HTL can use α-NPD (N,N′-di (α-naphtyl)-N,N′-diphenyl 1,1′-biphenyl-4,4′-diamine) or triphenyldiamine delivative TPD (N,N′-bis(3-methyl phenyl)1,1′-biphenyl-4,4′-diamine), and the electron transport layer ETL can use Alq3. Further, other than the above-described material of low molecular species, a material of polymer species can also be used. According to an organic electroluminescent element having the organic electroluminescent layer OLE of the constitution, when a direct current power source is connected between the opposed electrode AD constituting the anode and the pixel electrode CD constituting the cathode and a direct current voltage is applied between the two electrodes, holes injected from the opposed electrode AD and electrons injected from the pixel electrode CD respectively reach the light emitting layer, recombination of electron-hole is brought about and light emittance of a predetermined wave length is produced. FIG. 4 and FIG. 5 are enlarged sectional views for explaining other constitution examples of the organic electroluminescent layer of the organic electroluminescent display device according to the invention, portions the same as those of the above-described drawings are attached with the same notations. First, in FIG. 4, the organic electroluminescent layer OLE is constructed by a constitution of a 3 layer structure of the electron transport layer ETL and the light emitting layer EML and the hole transport layer HTL laminated with an opposed electrode ADV comprising V2O5 member. Other constitutions are the same as those of FIG. 1 and FIG. 2. Next, in FIG. 5, the organic electroluminescent layer OLE is respectively arranged with a pixel electrode ADL constituting an anode electrode on a back face side and an opposed electrode CDH having a semitransparent property constituting a cathode electrode on a front face side and successively laminated with the hole injection layer HIL, the hole transport layer HTL, the light emitting layer EML and the electron transport layer ETL from a side of the pixel electrode ADL. EXAMPLE 2 FIG. 6 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention and portions the same as those of the above-described drawings are attached with the same notations. In FIG. 6, there is constructed a constitution in which auxiliary electrodes SD (SDx1 through SDx4) in a strip-like shape are arranged on the bank BMP dividing the organic electroluminescent layers OLE in Y direction and continuously extended in X direction by way of the opposed electrode AD. A relationship between a width Wsy in the Y direction (width direction) of the auxiliary electrode SD and a width of a top face in the same direction of the bank BMP is brought into a relationship the same as that of Example 1 in which the width Wsy in Y direction of the auxiliary electrode SD is larger than a width of the top face of the bank BMP. There is constructed a constitution of arranging the auxiliary electrode SD to extend in X direction between respective pixels. Also the auxiliary electrode SD is connected to a power source circuit, not illustrated. EXAMPLE 3 FIG. 7 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. According to Example 3 shown in FIG. 7, there is constructed a constitution in which the pattern of arranging the auxiliary electrodes SDy1 through SDy3 shown in FIG. 1 are additionally arranged with the auxiliary electrodes SDx1, SDx2 extended in X direction at upper and lower ends of the screen, and the organic electroluminescent layer OLE is surrounded by the auxiliary electrodes SD. By aligning the auxiliary electrodes SD, the connection to the power source circuit described above becomes simple and convenient. EXAMPLE 4 FIG. 8 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. In Example 4 shown in FIG. 8, the pattern of arranging the auxiliary electrodes SDx1 through SDx4 shown in FIG. 6 is arranged with auxiliary electrodes SDyb extended in Y direction at left and right ends of the screen for connecting the auxiliary electrodes SDx1 through SDx4, and the auxiliary electrodes SDx1 through SDx4 are connected in series with each other. By aligning the auxiliary electrodes SD, the connection to the power source circuit becomes simple and convenient similar to Example 3 mentioned above. EXAMPLE 5 FIG. 9 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. In Example 5 shown in FIG. 9, a dimension of the auxiliary electrode SD is made to be variable in line with a dimension of the bank BMP, and there is constructed a constitution in which a width of the auxiliary electrode SDx2 arranged at a center portion of the screen is made to be wider than those of the auxiliary electrodes SDx1, SDx3 arranged at upper and lower ends. Further, Example 5 is arranged with a projected portion SDt capable of being utilized as a connection terminal at an end portion of the auxiliary electrode SD. In this way, when an area of the auxiliary electrode SD becomes large, an electricity conducting capacity becomes large in the same film thickness and an auxiliary current can be increased. EXAMPLE 6 FIG. 10 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. In Example 6 shown in FIG. 10, the dimension of the auxiliary electrode SD is made to be variable in line with the dimension of the bank BMP similar to Example 5 mentioned above. In FIG. 10, there is constructed a constitution in which large or small is present in film widths of auxiliary electrodes SDy1 and SDyn arranged at left and right ends of the screen, and the auxiliary electrodes SDy2 and SDyn−1 arranged for respective pixels are constituted by the same width. On the other hand, the auxiliary electrodes SDx1 through SDx4 extended in X direction are constructed by a constitution in which widths of the auxiliary electrodes SDx2, SDx3 arranged at a middle are made to be wider than those of the auxiliary electrodes SDx1, SDx4 arranged at upper and lower ends. EXAMPLE 7 FIG. 11 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. According to Example 7 shown in FIG. 11, there is constructed a constitution in which the auxiliary electrodes SD are arranged in correspondence with all of the banks BMP and the dimension of the auxiliary electrode SD is made to be variable in line with the dimension of the bank BMP. In FIG. 11, there is constructed a constitution in which widths of the auxiliary electrodes SDy1 through SDy7 and SDx1, SDx4 are the same and only a width of the auxiliary electrode SDx2 extended in X direction at a center portion of the screen is made to be wider than those of the others. By arranging the auxiliary electrodes SD in correspondence with all the banks BMP as in Example 7, a highly fine and high contrast display device can further be carried out. EXAMPLE 8 FIG. 12 is a schematic plane view for explaining an auxiliary electrode aligning pattern of still other example of the organic electroluminescent display device according to the invention, and portions the same as those of the above-described drawings are attached with the same notations. In Example 8 shown in FIG. 12, there is constructed a constitution in which the auxiliary electrodes SD are arranged in correspondence with all the banks BMP similar to Example 7 and the dimension of the auxiliary electrode SD is made to be variable in line with the dimension of the bank BMP. In FIG. 12, widths of the auxiliary electrodes SDy2 through SDyn−1 and SDx1, SDx3 are the same and large or small is present in film widths of the auxiliary electrodes SDy1 and SDyn extended in Y direction on left and right of the screen, further, there is constructed a constitution in which widths of the auxiliary electrodes SDx2, SDx3 extended in X direction at a center portion of the screen are made to be wider than those of the others. Example 8 is provided with a characteristic similar to that of Example 7 mentioned above. EXAMPLE 9 FIG. 13 is a schematic sectional view in correspondence with FIG. 2 for explaining an outline structure of still other example of the organic electroluminescent display device of the invention, and portions the same as those of the above-described drawings are attached with the same notations. In Example 9 shown in FIG. 13, there is constructed a constitution in which a width Wsx in X direction of the auxiliary electrode SD is formed to be wider than the width Wbx in the same direction of the top face of the bank BMP, and the center in X direction of the auxiliary electrode SD is displaced from the center of the bank BMP in an outer side direction. According to the constitution, there is constructed a constitution of enlarging the light emitting area by displacing an inner side end portion of the auxiliary electrode SD to the outer side and an efficiency of utilizing emitted light is promoted. Here, the above-described auxiliary electrode SD is provided with a function as an auxiliary wiring of the opposed electrode AD as well as a function of a black matrix for making a contour of the light emitting area clear by providing a light absorbing function on an outer face side of the auxiliary electrode SD to contribute to promote a contrast by also reducing reflection of external light.	H	67H01	185H01L	51	54
11845766	US20070290357A1-20071220	Top layers of metal for high performance IC's	ACCEPTED	20071205	20071220	[]	H01L2350	["H01L2350"]	7382058	20070827	20080603	257	778000	62575.0	PHAM	LONG	[{"inventor_name_last": "Lin", "inventor_name_first": "Mou-Shiung", "inventor_city": "Hsin-Chu", "inventor_state": "", "inventor_country": "TW"}]	A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.	1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said metallization structure, a second opening in said passivation layer exposing a second pad of said metallization structure, and a third opening in said passivation layer exposing a third pad of said metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; a polymer layer over said passivation layer, a fourth opening in said polymer layer exposing said first pad, a fifth opening in said polymer layer exposing said second pad, and a sixth opening in said polymer layer exposing said third pad, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and a ground distribution structure over said polymer layer and over said first, second and third pads, wherein said ground distribution structure comprises electroplated copper, wherein said first pad is connected to said second and third pads through said ground distribution structure, and said second pad is connected to said third pad through said ground distribution structure, and wherein said ground distribution structure comprises a third metal layer having a thickness greater than those of said first and second metal layers. 2. The integrated circuit chip of claim 1, wherein said polymer layer comprises polyimide. 3. The integrated circuit chip of claim 1, wherein said ground distribution structure further comprises nickel. 4. The integrated circuit chip of claim 1, wherein said ground distribution structure further comprises tungsten. 5. The integrated circuit chip of claim 1, wherein said ground distribution structure further comprises chromium. 6. The integrated circuit chip of claim 1, wherein said ground distribution structure further comprises a sputtered metal. 7. The integrated circuit chip of claim 1, wherein said ground distribution structure further comprises an electroless metal. 8. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said metallization structure, a second opening in said passivation layer exposing a second pad of said metallization structure, and a third opening in said passivation layer exposing a third pad of said metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer; a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and a ground distribution structure over said passivation layer and over said first, second and third pads, wherein said ground distribution structure comprises electroplated copper, wherein said first pad is connected to said second and third pads through said ground distribution structure, and said second pad is connected to said third pad through said ground distribution structure, and wherein said ground distribution structure comprises a third metal layer having a thickness greater than those of said first and second metal layers. 9. The integrated circuit chip of claim 8, wherein said polymer layer comprises polyimide. 10. The integrated circuit chip of claim 8, wherein said ground distribution structure further comprises nickel. 11. The integrated circuit chip of claim 8, wherein said ground distribution structure further comprises tungsten. 12. The integrated circuit chip of claim 8, wherein said ground distribution structure further comprises chromium. 13. The integrated circuit chip of claim 8, wherein said ground distribution structure further comprises a sputtered metal. 14. The integrated circuit chip of claim 8, wherein said ground distribution structure further comprises an electroless metal. 15. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said metallization structure, a second opening in said passivation layer exposing a second pad of said metallization structure, and a third opening in said passivation layer exposing a third pad of said metallization structure, wherein said first, second and third pads are separate from one another, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer; a polymer layer over said passivation layer, a fourth opening in said polymer layer exposing said first pad, a fifth opening in said polymer layer exposing said second pad, and a sixth opening in said polymer layer exposing said third pad, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and a ground distribution structure over said polymer layer and over said first, second and third pads, wherein said ground distribution structure comprises electroplated copper, wherein said first pad is connected to said second and third pads through said ground distribution structure, and said second pad is connected to said third pad through said ground distribution structure, and wherein said ground distribution structure comprises a third metal layer having a thickness greater than those of said first and second metal layers. 16. The integrated circuit chip of claim 15, wherein said polymer layer comprises polyimide. 17. The integrated circuit chip of claim 15, wherein said ground distribution structure further comprises nickel. 18. The integrated circuit chip of claim 15, wherein said ground distribution structure further comprises tungsten. 19. The integrated circuit chip of claim 15, wherein said ground distribution structure further comprises chromium. 20. The integrated circuit chip of claim 15, wherein said ground distribution structure further comprises a sputtered metal.	<SOH> BACKGROUND OF THE INVENTION <EOH>(1) Field of the Invention The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and more specifically to methods of achieving high performance of the Integrated Circuits by reducing the parasitic capacitance and resistance of inter-connecting wiring on a chip. (2) Description of the Prior Art When the geometric dimensions of the Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Increased Input-Output (IO) combined with increased demands for high performance IC's has led to the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on chip and interconnect the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Temperature Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations. U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections. U.S. Pat. No. 5,501,006 (Gehman, Jr. et al.) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate. U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention. U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure. U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers. U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/O traces.	<SOH> SUMMARY OF THE INVENTION <EOH>It is the primary objective of the present invention to improve the performance of High Performance Integrated Circuits. Another objective of the present invention is to reduce resistive voltage drop of the power supply lines that connect the IC to surrounding circuitry or circuit components. Another objective of the present invention is to reduce the RC delay constant of the signal paths of high performance IC's. Yet another objective of the present invention is to facilitate the application of IC's of reduced size and increased circuit density. Yet another objective of the present invention is to further facilitate and enhance the application of low resistor conductor metals. Yet another objective of the present invention is to allow for increased I/O pin count for the use of high performance IC's. Yet another objective of the present invention is to simplify chip assembly by reducing the need for re-distribution of I/O chip connections. Yet another objective of the present invention is to facilitate the connection of high-performance IC's to power buses. Yet another objective of the present invention is to facilitate the connection of high-performance IC's to clock distribution networks. Yet another objective of the present invention is to reduce IC manufacturing costs by allowing or facilitating the use of less expensive process equipment and by accommodating less strict application of clean room requirements, this as compared to sub-micron manufacturing requirements. Yet another objective of the present invention is to be a driving force and stimulus for future system-on-chip designs since the present invention allows ready and cost effective interconnection between functional circuits that are positioned at relatively large distances from each other on the chip. Yet another objective of the present design is to form the basis for a computer based routing tool that automatically routes interconnections that exceed a pre-determined length in accordance with the type of interconnection that needs to be established. The present invention adds one or more thick layers of dielectric and one or more layers of wide metal lines on top of the finished device wafer. The thick layer of dielectric can, for example, be of polyimide or benzocyclobutene (BCB) with a thickness of over, for example, 3 um. The wide metal lines can, for instance, be of aluminum or electroplated copper. These layers of dielectric and metal lines can be used for power buses or power planes, clock distribution networks, critical signal, re-distribution of I/O pads for flip chip applications, and for long signal paths.	This application is a continuation of application Ser. No. 11/230,102, filed on Sep. 19, 2005, now pending, which is a continuation of application Ser. No. 11/121,477, filed on May 4, 2005, now pending, which is a continuation of application Ser. No. 10/389,543, filed on Mar. 14, 2003, now U.S. Pat. No. 6,965,165, which is a division of application Ser. No. 09/972,639, filed on Oct. 9, 2001, now U.S. Pat. No. 6,657,310, which is a division of application Ser. No. 09/251,183, filed on Feb. 17, 1999, now U.S. Pat. No. 6,383,916, which is a continuation-in-part of application Ser. No. 09/216,791, filed on Dec. 21, 1998, now abandoned. BACKGROUND OF THE INVENTION (1) Field of the Invention The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and more specifically to methods of achieving high performance of the Integrated Circuits by reducing the parasitic capacitance and resistance of inter-connecting wiring on a chip. (2) Description of the Prior Art When the geometric dimensions of the Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires. To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Increased Input-Output (IO) combined with increased demands for high performance IC's has led to the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on chip and interconnect the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units. The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Temperature Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations. U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiring connections both inside and outside (in a wiring substrate over the chip) for a logic circuit depending on the length of the wire connections. U.S. Pat. No. 5,501,006 (Gehman, Jr. et al.) shows a structure with an insulating layer between the integrated circuit (IC) and the wiring substrate. A distribution lead connects the bonding pads of the IC to the bonding pads of the substrate. U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integration semiconductor structure that allows manufacturers to integrate circuitry beyond the chip boundaries by forming a thin film multi-layer wiring decal on the support substrate and over the chip. However, this reference differs from the invention. U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layer interconnect structure of alternating polyimide (dielectric) and metal layers over an IC in a TAB structure. U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RC delay by a PBGA that separates multiple metal layers. U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate that reduces RC delay by separating the power and I/O traces. SUMMARY OF THE INVENTION It is the primary objective of the present invention to improve the performance of High Performance Integrated Circuits. Another objective of the present invention is to reduce resistive voltage drop of the power supply lines that connect the IC to surrounding circuitry or circuit components. Another objective of the present invention is to reduce the RC delay constant of the signal paths of high performance IC's. Yet another objective of the present invention is to facilitate the application of IC's of reduced size and increased circuit density. Yet another objective of the present invention is to further facilitate and enhance the application of low resistor conductor metals. Yet another objective of the present invention is to allow for increased I/O pin count for the use of high performance IC's. Yet another objective of the present invention is to simplify chip assembly by reducing the need for re-distribution of I/O chip connections. Yet another objective of the present invention is to facilitate the connection of high-performance IC's to power buses. Yet another objective of the present invention is to facilitate the connection of high-performance IC's to clock distribution networks. Yet another objective of the present invention is to reduce IC manufacturing costs by allowing or facilitating the use of less expensive process equipment and by accommodating less strict application of clean room requirements, this as compared to sub-micron manufacturing requirements. Yet another objective of the present invention is to be a driving force and stimulus for future system-on-chip designs since the present invention allows ready and cost effective interconnection between functional circuits that are positioned at relatively large distances from each other on the chip. Yet another objective of the present design is to form the basis for a computer based routing tool that automatically routes interconnections that exceed a pre-determined length in accordance with the type of interconnection that needs to be established. The present invention adds one or more thick layers of dielectric and one or more layers of wide metal lines on top of the finished device wafer. The thick layer of dielectric can, for example, be of polyimide or benzocyclobutene (BCB) with a thickness of over, for example, 3 um. The wide metal lines can, for instance, be of aluminum or electroplated copper. These layers of dielectric and metal lines can be used for power buses or power planes, clock distribution networks, critical signal, re-distribution of I/O pads for flip chip applications, and for long signal paths. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a cross section of the interconnection scheme of the present invention. FIG. 2 shows a cross section of the present invention in a more complex circuit configuration. FIG. 3a shows the top view of a combination power and X-signal plane using the present invention. FIG. 3b shows the top view of a combination power and Y-signal plane using the present invention. FIG. 4 shows the top view of solder bump arrangement using the present invention and is an expanded view of a portion of FIG. 5. FIG. 5 shows the top view of an example of power/ground pads combined with signal pad using the present invention. FIG. 6 shows a basic integrated circuit (IC) interconnect scheme of the invention. FIG. 7 shows an extension of the basic IC interconnect scheme by adding power, ground and signal distribution capabilities. FIG. 8 shows an approach of how to transition from sub-micron metal to wide metal interconnects. FIG. 9 shows detail regarding BGA device fan out using the invention. FIG. 10 shows detail regarding BGA device pad relocation using the invention. FIG. 11 shows detail regarding the usage of common power, ground and signal pads for BGA devices using the invention. DETAILED DESCRIPTION OF THE INVENTION The present invention teaches an Integrated Circuit structure where key re-distribution and interconnection metal layers and dielectric layers are added over a conventional IC. These re-distribution and interconnection layers allow for wider buses and reduce conventional RC delay. Referring now more specifically to FIG. 1, there is shown a cross section of one implementation of the present invention. A silicon substrate 1 has transistors and other devices, typically formed of poly silicon, covered by a dielectric layer 2 deposited over the devices and the substrate. Layer 3 indicates the totality of metal layers and dielectric layers that are typically created on top of the device layer 2. Points of contact 6, such as bonding pads known in the semiconductor art, are in the top surface of layers 3 and are part of layer 3. These points of contact 6 are points within the IC arrangement that need to be further connected to surrounding circuitry, that is to power lines or to signal lines. A passivation layer 4, formed of for example silicon nitride, is deposited on top of layer 3, as is known in the art for protecting underlying layers from moisture, contamination, etc. The key steps of the invention begin with the deposition of a thick layer 5 of polyimide is deposited. A pattern 7 is exposed and etched through the polyimide layer 5 and the passivation layer 4 where the pattern 7 is the same as the pattern of the contact points 6. This opens the contact points 6 up to the surface 8 of the polyimide layer 5. Electrical contact with the contact points 6 can now be established by filling the openings 7 with a conductor. The tops 9 of this metal conductor can now be used for connection of the IC to its environment, and for further integration into the surrounding electrical circuitry. Pads 10, 11 and 12 are formed on top of the top 9 of the metal conductors 7; these pads can be of any design in width and thickness to accommodate specific circuit design requirements. A larger size pad can, for instance, be used as a flip chip pad. A somewhat smaller in size pad can be used for power distribution or as a ground or signal bus. The following connections can, for instance, be made to the pads shown in FIG. 1: pad 10 can serve as a flip chip pad, pad 11 can serve as a flip chip pad or can be connected to electrical power or to electrical ground or to an electrical signal bus, pad 12 can also serve as a flip chip pad. There is no connection between the size of the pads shown in FIG. 1 and the suggested possible electrical connections for which this pad can be used. Pad size and the standard rules and restrictions of electrical circuit design determine the electrical connections to which a given pad lends itself. The following comments relate to the size and the number of the contact points 6, FIG. 1. Because these contact points 6 are located on top of a thin dielectric (layer 3, FIG. 1) the pad size cannot be too large since a large pad size brings with it a large capacitance. In addition, a large pad size will interfere with the routing capability of that layer of metal. It is therefore preferred to keep the size of the pad 6 small. The size of pad 6 is however also directly related with the aspect ratio of via 7. An aspect ratio of about 5 is acceptable for the consideration of via etching and via filling. Based on these considerations, the size of the contact pad 6 can be in the order of 0.3 μm to 5.0 μm, the exact size being dependent on the thickness of layers 4 and 5. The contact points 6 can comprise any appropriate contact material, such as but not limited to tungsten, copper (electroplated or electroless), aluminum, polysilicon, or the like. The present invention does not impose a limitation on the number of contact pads that can be included in the design; this number is dependent on package design requirements. Layer 4 in FIG. 1 can be a typical IC passivation layer. The most frequently used passivation layer in the present state of the art is plasma enhanced CVD (PECVD) oxide and nitride. In creating layer 4, a layer of between about 0.15 and 2.0 μm PECVD oxide is deposited first followed by a layer of between about 0.5 and 2.0 μm, and preferably approximately 0.7 μm nitride. Passivation layer 4 is very important because it protects the device wafer from moisture and foreign ion contamination. The positioning of this layer between the sub-micron process (of the integrated circuit) and the tens-micron process (of the interconnecting metallization structure) is of critical importance since it allows for a cheaper process that possibly has less stringent clean room requirements for the process of creating the interconnecting metallization structure. Layer 5 is a thick polymer dielectric layer (for example polyimide) that has a thickness in excess of 2 μm (after curing). The range of polyimide thickness can vary from 2 μm to 30 μm dependent on electrical design requirements. For the deposition of layer 5 the Hitachi-Dupont polyimide HD 2732 or 2734 can, for example, be used. The polyimide can be spin-on coated and cured. After spin-on coating, the polyimide will be cured at between approximately 250 and 450 degrees C., preferably at 400 degrees C., for between approximately 0.5 and 1.5 hours, preferably for 1 hour, in a vacuum or nitrogen ambient. For thicker polyimide, the polyimide film can be multiple coated and cured. Another material that can be used to create layer 5 is the polymer benzocyclobutene (BCB). This polymer is at this time commercially produced by for instance Dow Chemical and has recently gained acceptance to be used instead of typical polyimide application. The dimensions of opening 7 have previously been discussed. The dimension of the opening together with the dielectric thickness determines the aspect ratio of the opening. The aspect ratio challenges the via etch process and the metal filling capability. This leads to a diameter for opening 7 in the range of approximately 0.5 μm to 3.0 μm while the height for opening 7 can be in the range of approximately 3 μm to 20 μm. The aspect ratio of opening 7 is designed such that filling of the via with metal can be accomplished. The via can be filled with CVD metal such as CVD tungsten or CVD copper, with electro-less nickel, with a damascene metal filling process, with electroplating copper, with sputtering aluminum, etc. It must be noted that the use of polyimide films as inter-level dielectrics has been pursued as a technique for providing partial planarization of a dielectric surface. Polyimides offer the following characteristics for such applications: they produce surfaces in which the step heights of underlying features are reduced, and step slopes are gentle and smooth. they are available to fill small openings without producing the voids that occur when low-temperature CVD oxide films are deposited. the cured polyimide films can tolerate temperatures of up to 500 degrees C. without degradation of their dielectric film characteristics. polyimide films have dielectric breakdowns, which are only slightly lower than that of SiO2. the dielectric constant of polyimides is smaller than that of silicon nitride and of SiO2. the process used to deposit and pattern polyimide films is relatively simple. For all of the above characteristics, polyimides are used and recommended within the scope of the present invention. FIG. 2 shows how the present invention as indicated in FIG. 1 can be further extended to include multiple layers of polyimide and, in so doing, can be adapted to a larger variety of applications. The lower level build up of this cross section is identical to the build up shown in FIG. 1 with a silicon wafer 1, the poly silicon layer 2, the metal and dielectric combined layer 3, the passivation layer 4, the polyimide layer 5 and the pads 10 deposited on top of layer 5. The function of the structure that has been described in FIG. 1 can be further extended by depositing another layer of polyimide 14 on top of the previously deposited layer 5 and overlaying the pads 10. Selective etching and metal deposition can further create contact points 12. These contact points 12 can be connected with pads 10 as shown by connector 13. Depositing pads 12 on top of layer 14 can thus further extend this process. These pads 12 can be further customized to a particular application, the indicated extension of multiple layers of polyimides greatly enhances the flexibility and usefulness of the present invention. Additional alternating layers of polyimide and metal lines and/or power or ground planes may be added above layers 12 and 16, as needed. Dielectric layers 14 and 16 can be formed as described above with reference to FIG. 1 for the dielectric layer 5. FIGS. 3a and 3b show a top view of one possible use of the present invention. Interconnecting a number of pads 32 that have been created as described creates signal lines 30. Additional contact points such as point 34 can allow signal lines to pass vertically between layers. The various contact points can, for instance, be created within the surface of a power plane or ground plane 36. The layers within the interconnecting metallization structure of the present invention can contain signal interconnections in the X-direction, signal interconnections in the Y-direction, signal interconnections between X and or Y directions, interconnections to and/or within power and/or ground buses. The present invention further teaches the interconnection of signal lines, power and ground buses between the connected IC's and the top of the metallization system of the present invention. FIG. 3a shows signal lines formed in the X-direction. FIG. 3b shows signal lines formed in the Y-direction. FIG. 4 presents yet another application of the present invention. Shown in FIG. 4 is an exploded view of a part of FIG. 5 that presents an area array I/O distribution. FIG. 4 shows pads 41 (on which solder bumps can be created) and an example of a layout of the redistribution of the peripheral pads 41′. The exploded view of FIG. 4 is taken along the line 2-2′ shown in FIG. 5; the redistribution of the peripheral pads 41′ (see FIG. 4) is, for clarity of overview, not shown in FIG. 5. The power or ground connections can be made to any point that is required on the bottom device. Furthermore, the power and ground planes can be connected to the power and ground planes of the package substrates. FIG. 4 shows an example of how to use the topmost metal layer to redistribute the peripheral pads 41′ to become area array pads 41. The solder bumps can then be created on pads 41. FIG. 5 shows the top surface of a plane that contains a design pattern of a combination of power or ground pads 52 and signal pads 54. FIG. 5 shows the pad openings in the top dielectric layer. It is to be noted that the ground/power pads 52 are heavier and larger in design relative to the signal pads 54. The present invention ideally lends itself to meeting these differences in design, as they are required within the art of chip and high performance circuit design. The number of power or ground pads 52 shown in FIG. 5 can be reduced if there are power and/or ground planes within the chip 53. From this it is clear that the package number of I/O's can be reduced within the scope of the present invention which leads to a reduction of the package cost by eliminating common signal/power/ground connections within the package. For instance, a 470 I/O count on a BGA chip can, within the scope of the present invention, be reduced to a 256 I/O count using the present invention. This results in considerable savings for the overall package. FIG. 6 shows a basic design advantage of the invention. This advantage allows for the sub-micron or fine-lines, that run in the immediate vicinity of the metal layers 3 and the contact points 6, to be extended in an upward direction 20 through metal interconnect 7′. This extension continues in the direction 22 in the horizontal plane of the metal interconnect 26 and comes back down in the downward direction 24 through metal interconnect 7″. The functions and constructs of the passivation layer 4 and the insulating layer 5 remain as previously highlighted under FIG. 1. This basic design advantage of the invention is to “elevate” or “fan-out” the fine-line interconnects and to remove these interconnects from the micron and sub-micron level to a metal interconnect level that has considerably larger dimensions and is therefore characterized by smaller resistance and capacitance and is easier and more cost effective to manufacture. This aspect of the invention does not include any aspect of conducting line re-distribution and therefore has an inherent quality of simplicity. It therefore further adds to the importance of the invention in that it makes micron and sub-micron wiring accessible at a wide-metal level. The interconnections 7′ and 7″ interconnect the fine-level metal by going up through the passivation and polymer or polyimide dielectric layers, traverses over a distance on the wide-metal level and continues by descending from the wide-metal level back down to the fine-metal level by again traversing down through the passivation and polymer or polyimide dielectric layers. The extensions that are in this manner accomplished need not to be limited to extending fine-metal interconnect points 6 of any particular type, such as signal or power or ground, with wide metal line 26. The laws of physics and electronics will impose limitations, if any, as to what type of interconnect can by established in this manner where limiting factors will be the conventional limiting factors of resistance, propagation delay, RC constants and others. The upper metallization structure over the passivation layer 4 may comprise any appropriate contact material, such as but not limited to tungsten, chromium, copper (electroplated or electroless), aluminum, polysilicon, or the like. The upper metallization structure over the passivation layer 4 and over the contact points 6 can be formed using a process comprising an electroplating process, a sputtering process, an electroless-plating process, or a damascene process. Where the invention is of importance is that the invention provides much broader latitude in being able to apply these laws and, in so doing, provides a considerably extended scope of the application and use of Integrated Circuits and the adaptation of these circuits to a wide-metal environment. The upper metallization structure may have multiple metal layers and multiple dielectric layers as depicted in FIG. 2. The upper metallization structure may comprise multiple metal traces and a metal plane, such as a power plane or ground plane, enclosing the metal traces as shown in FIGS. 3a and 3b. FIG. 7 shows how the basic interconnect aspect of the invention can further be extended to now not only elevate the fine-metal to the plane of the wide-metal but to also add power, ground and signal distribution interconnects of power, ground and signal planes at the wide-metal level. The wide-metal interconnect 26 of FIG. 6 is now extended to further include an interconnection with the via 21. In typical IC design, some pads may not be positioned in a location from which easy fan-out can be accomplished to a location that is required for the next step of circuit assembly. In those cases, the BGA substrate requires additional layers in the package construction in order to accomplish the required fan-out. The invention teaches an approach that makes additional layers in the assembling of an IC feasible while not unduly increasing the cost of creating such a multi-layer interface. Ball formation 28 on the surface of interconnect 23 indicates how the invention replaces part of the conventional BGA interconnect function, the solder bump provides for flip chip assembly. This interconnect 28 now connects the BGA device with surrounding circuitry at the wide-metal level as opposed to previous interconnects of the BGA device at the fine-metal level. The wide-metal interconnect of the BGA has obvious advantages of cost of manufacturing and improved BGA device performance. By being able to readily extend the wide-metal dimensions it also becomes possible to interconnect power, ground and signal lines at a wide-metal level thereby reducing the cost and complexity of performing this function at the fine-metal level. The indication of 28 as a ball does not imply that the invention is limited to solder bumps for making interconnects. The invention is equally applicable to wirebonding for making circuit interconnects. FIG. 8 further shows a cross section wherein the previous linear construction of the metal interconnection running through the passivation layer and the insulation layer is now conical in form. The sub-micron metal layer 60 is covered with a passivation layer 62, a layer 64 of polyimide or polymer is deposited over the passivation layer 62. The wide metal level 66 is formed on the surface of layer 64. The via 70 is shown as having sloping sides, these sloping sides can be achieved by controlling the photolithography process that is used to created the via 70. The etching of the polyimide or polymer can for instance be done under an angle of about 75 degrees with the following curing being done under an angle of 45 degrees. Also, a photosensitive polyimide or polymer can be used, the cone shape of the via 70 can in that case be achieved by variation of exposure combined with time of exposure combined with angle of exposure. Where non-photosensitive polymer or polyimide is used, a wet etch can be applied that has a gradated faster and longer time etch as the top of the via 70 is being approached. The layer of wide-metal pad 68 is deposited on the surface of the polymer or polyimide layer 64, the wide-metal pad deposition 68 mates with the top surface of the via 70 and is centered on top of this surface. FIGS. 9 through 11 show further detail to demonstrate the concepts of BGA chip ball fan-out, pad relocation and the creation of common ground, power and signal pads. The concept of pad relocation, fan-out, pad addition or pad reduction can be realized by forming the wide and thick metal interconnection scheme over the passivation layer described in this invention, to replace the function of BGA substrate 130. FIG. 9 shows a cross section 100 of a BGA chip, five balls 101 through 105 are also shown. By using the BGA substrate 106 and the wiring 107 within the substrate 106, it is clear that ball 101 can be repositioned to location 111, ball 102 to location 112, etc. for the remaining solder bumps 103 through 105. It is clear that the separation of contact points 111 through 115 is considerably larger than the separation of the original solder bumps 101 through 105. The BGA substrate 106 is the subject of the invention, this substrate allows for spreading the distance between the contact points or balls of the BGA device to a considerable degree. FIG. 10 shows the concept of pad relocation. BGA pad 120 connects to any of the contact balls 101 through 105. By using the BGA substrate 130 and the wiring 131 that is provided within the substrate, it is clear that the BGA pads can be arranged in a different and arbitrary sequence that is required for further circuit design or packaging. For instance contact point 101, which is on the far left side of the BGA device 100, is re-routed to location 122 which is on the second far right of the BGA substrate 130. The re-arrangements of the other BGA solder bumps can readily be learned from following the wiring 131 within the substrate 131 and by tracing from solder bump to one of the contact points 122 through 125 of the BGA substrate. FIG. 11 shows the interconnecting of BGA device solder bumps into common power, ground or signal pads. The BGA chip 100 is again shown with five solder bumps 101 through 105. The BGA substrate 130 contains a wiring scheme that contains in this example three wiring units, one for each for the power, ground and signal bumps of the BGA device. It is clear from FIG. 11 that wire arrangement 132 connects BGA device solder bumps 101, 103 and 105 to interconnect point 138 of the BGA substrate 130. It can further be seen that BGA device solder bump 104 is connected to interconnect point 140 of the BGA substrate by means of the wire arrangement 136, while BGA device solder bump 102 is connected to interconnect point 142 of the BGA substrate by means of the wire arrangement 134. The number of pins required to interconnect the BGA device 100 is in this manner reduced from five to three. It is clear that for more BGA device solder bumps, as is the case for an actual BGA device, the numeric effect of the indicated wiring arrangement is considerably more beneficial. The concept of fan-out, pad relocation can be realized by forming the wide and thick metal interconnection scheme over the passivation layer described in this invention, to replace the function of BGA substrate 130. From FIGS. 9, 10 and 11 it can be seen that the extended functionality and extended wiring ability that are provided by the interconnect wiring schemes that are typically created in the BGA substrate 130 can be substituted by forming the wide and thick metal interconnection scheme over the passivation layer, on device 100. Some of the methods and possibilities of interconnect line routing that can be implemented using the method of the invention are highlighted in the following paragraphs. Fan-out capability can be provided by the invention, using the metal conductors within the openings through the insulating layer and through the passivation layer that connect electrical contact pads of the top metallization structure with contact points of the interconnecting metallization structure. Each of the electrical contact points of the interconnecting metallization structure is connected directly and sequentially with at least one electrical contact point of the top metallization structure. In a fan-out scheme, the distance between electrical contact points of the top metallization structure is larger than the distance between electrical contact points of the interconnecting metallization structure by a measurable amount. Alternatively, in a pad-addition scheme, the number of electrical contact pads of the upper metallization structure can exceed the number of contact points of the interconnecting metallization structure by a considerable amount. This provides an addition effect. Pad relocation may also be accomplished by the method of the invention. Electrical contact points of the top metallization structure are connected with the contact points of the interconnecting metallization structure, directly but not necessarily sequentially, thereby creating a pad relocation effect. In this method, the distance between electrical contact points of the top metallization structure is larger than the distance between the electrical contact points of the interconnecting metallization structure by a measurable amount. The positions of the electrical contact points of the top metallization structure over the passivation layer from a top view are different from that of the contact points of the interconnecting metallization structure exposed by the openings in the passivation layer. A reduction effect may also be accomplished by the method of the invention, wherein common nodes are connected together. Electrical contact points on a top surface of the top metallization structure are connected with contact points of the interconnecting metallization structure exposed by the openings in the passivation layer, where fewer contact points are used in the top metallization structure, since functionally equivalent contact points in the interconnecting metallization structure are connected together. That is, the number of contact points for a particular electrical function among the electrical contact points of the top metallization structure is smaller than the number of electrical contact points of the interconnecting metallization structure exposed by the passivation layer by a measurable amount. Some of the advantages of the present invention are: 1) improved speed of the IC interconnections due to the use of wider metal lines (which results in lower resistance) and thicker dielectrics between the interconnecting lines (which results in lower capacitance and reduced RC delay). The improved speed of the IC interconnections results in improved performance of High Performance IC's. 2) an inexpensive manufacturing process since there is no need for expensive equipment that is typically used in sub-micron IC fabrication; there is also no need for the extreme clean room facilities that are typically required for sub-micron manufacturing. 3) reduced packaging costs due to the elimination of the need for redundant I/O and multiple power and ground connection points that are needed in a typical IC packaging. 4) IC's of reduced size can be packaged and inter-connected with other circuit or system components without limiting the performance of the IC's. 5) since dependence on ultra-fine wiring is reduced, the use of low resistance conductor wires is facilitated. 6) structures containing more complicated IC's can be created because the invention allows for increased I/O pin count. 7) more complicated IC's can be created without the need for a significant increase in re-distribution of package I/O connections. 8) power buses and clock distribution networks are easier to integrate within the design of IC's. 9) future system-on-chip designs will benefit from the present invention since it allows ready and cost effective interconnection between functional circuits that are positioned at relatively large distances from each other on the chip. 10) form the basis for a computer based routing tool that automatically routes interconnections that exceed a pre-determined length in accordance with the type of interconnection that needs to be established. 11) provide a means to standardize BGA packaging. 12) be applicable to both solder bumps and wirebonding for making further circuit interconnects. 13) provide a means for BGA device solder bump fan-out thereby facilitating the packing and design of BGA devices. 14) provide a means for BGA device pad relocation thereby providing increased flexibility for the packing and design of BGA devices. 15) provide a means for common BGA device power, ground and signal lines thereby reducing the number of pins required to interconnect the BGA device with the surrounding circuits. 16) provide a means for more relaxed design rules in designing circuit vias by the application of sloped vias. 17) provide the means for extending a fine-wire interconnect scheme to a wide-wire interconnect scheme without the need to apply a passivation layer over the surface of the fine-wire structure. Although the preferred embodiment of the present invention has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.	H	67H01	185H01L	23	50
10594619	US20080006894A1-20080110	Semiconductor Light Detecting Element and Manufacturing Method Thereof	ACCEPTED	20071226	20080110	[]	H01L31101	["H01L31101", "H01L3118"]	7868408	20070619	20110111	257	466000	59628.0	VIEIRA	DIANA	[{"inventor_name_last": "Tanaka", "inventor_name_first": "Akimasa", "inventor_city": "Shizuoka", "inventor_state": "", "inventor_country": "JP"}]	A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (7) which are laminated. A photodetecting region (9) is formed near a first main face (101) of the multilayer structure, whereas a first electrode (21) is provided on the first main face. A second electrode (27) and a third electrode (31) are provided on a second main face (102). A film (10) covering the photodetecting region and first electrode is formed on the first main face. A glass substrate (1) is secured to the front face (10a) of this film.	1. A photodetector device comprising: a multilayer structure including a plurality of compound semiconductor layers laminated and having first and second main faces opposing each other; a photodetecting region formed near the first main face within the multilayer structure; a first electrode arranged on the first main face of the multilayer structure and electrically connected to the photodetecting region; a second electrode arranged on the second main face of the multilayer structure and electrically connected to the first electrode; a third electrode arranged on the second main face of the multilayer structure and electrically connected to a part near the second main face in the multilayer structure; and a light-transmitting layer, optically transparent to incident light and arranged on the first main face of the multilayer structure, covering the photodetecting region and first electrode. 2. A photodetector device according to claim 1, wherein the light-transmitting layer includes a film made of silicon oxide and a glass substrate; and wherein the glass substrate is secured to the multilayer structure through the film made of silicon oxide. 3. A photodetector device according to claim 1, wherein the light-transmitting layer includes a film made of silicon oxide or a resin. 4. A photodetector device according to claim 1, wherein the plurality of compound semiconductor layers include a high-concentration carrier layer of a first conductive type, a light-absorbing layer of the first conductive type, and a cap layer of the first conductive type; and wherein the photodetecting region is a region of a second conductive type including at least a part of the cap layer. 5. A photodetector device according to claim 4, wherein the multilayer structure further comprises a depression formed about the photodetecting region, and a wiring electrode arranged within the depression; wherein the first electrode is electrically connected to the second electrode through the wiring electrode; and wherein the third electrode is electrically connected to a part positioned near the photodetecting region in the high-concentration carrier layer. 6. A photodetector device according to claim 4, further comprising a through lead penetrating through the multilayer structure; wherein the first electrode is electrically connected to the second electrode through the wiring electrode; and wherein the third electrode is electrically connected to the high-concentration carrier layer. 7. A photodetector device according to claim 1, wherein the second and third electrodes include respective pad electrodes, while respective bump electrodes are arranged on the pad electrodes. 8. A photodetector device according to claim 1, further comprising a light-reflecting film, provided on the second main face, covering the photodetecting region. 9. A photodetector device according to claim 1, comprising a plurality of photodetecting regions arranged in a row. 10. A photodetector device according to claim 1, wherein the light-transmitting layer includes a lens part converging the incident light. 11. A method of manufacturing a semiconductor photodetector device, the method comprising the steps of: preparing a semiconductor substrate; providing a multilayer structure on the semiconductor substrate, the multilayer structure including a plurality of compound semiconductor layers laminated and having first and second main faces opposing each other, the second main face facing the semiconductor substrate; forming a photodetecting region near the first main face within the multilayer structure; providing a first electrode electrically connected to the photodetecting region onto the first main face of the multilayer structure; forming a light-transmitting layer optically transparent to incident light onto the first main face of the multilayer structure so as to cover the photodetecting region and first electrode; removing the semiconductor substrate after forming the light-transmitting layer; and forming a second electrode electrically connected to the first electrode onto the second main face of the multilayer structure while forming a third electrode electrically connected to a part near the second main face in the multilayer structure onto the second main face after removing the semiconductor substrate. 12. A method of manufacturing a semiconductor photodetector device according to claim 11, wherein the step of forming the light-transmitting layer includes the steps of: forming a film made of silicon oxide so as to cover the photodetecting region and first electrode; and securing a glass substrate optically transparent to the incident light onto the film made of silicon oxide. 13. A method of manufacturing a semiconductor photodetector device according to claim 11, wherein the step of forming the light-transmitting layer includes the step of forming a film made of silicon oxide or a resin so as to cover the photodetecting region and first electrode. 14. A method of manufacturing a semiconductor photodetector device according to claim 11, wherein the step of removing the semiconductor substrate includes the step of removing the semiconductor substrate by wet etching; and wherein the step of forming the multilayer structure includes the step of forming an etching stop layer for stopping wet etching between the semiconductor substrate and the plurality of compound semiconductor layers. 15. A method of manufacturing a semiconductor photodetector device according to claim 14, further comprising the step of removing the etching stop layer by wet etching after removing the semiconductor substrate. 16. A method of manufacturing a semiconductor photodetector device according to claim 11, wherein the plurality of compound semiconductor layers include a high-concentration carrier layer of a first conductive type, a light-absorbing layer of the first conductive type, and a cap layer of the first conductive type; wherein the step of forming the multilayer structure includes the step of successively laminating the high-concentration carrier layer, light-absorbing layer, and cap layer on the semiconductor substrate; and wherein the step of forming the photodetecting region includes the step of forming a region of a second conductive type including at least a part of the cap layer as the photodetecting region. 17. A method of manufacturing a semiconductor photodetector device according to claim 16, further comprising the steps of forming a depression about the photodetecting region; and providing a wiring electrode for electrically connecting the first electrode to the second electrode in the depression; wherein the step of forming the third electrode includes the step of forming the third electrode such that the third electrode is electrically connected to a part positioned near the photodetecting region in the high-concentration carrier layer. 18. A method of manufacturing a semiconductor photodetector device according to claim 16, wherein the step of forming the second electrode includes the step of forming a through lead penetrating through the multilayer structure, and electrically connecting the first electrode to the second electrode through the through lead; and wherein the step of forming the third electrode includes the step of forming the third electrode such that the third electrode is electrically connected to the high-concentration carrier layer. 19. A method of manufacturing a semiconductor photodetector device according to claim 11, further comprising the step of forming a light-reflecting film covering the photodetecting region onto the second main face of the multilayer structure. 20. A method of manufacturing a semiconductor photodetector device according to claim 11, wherein the light-transmitting layer includes a lens part converging the incident light.	<SOH> BACKGROUND ART <EOH>Recently, as the CPU driving frequency has been becoming higher (e.g., 10 GHz or higher), attention has been directed toward optical interconnection techniques in which signals within and between system apparatus are transmitted by light. Semiconductor devices such as semiconductor photodetector devices and semiconductor light-emitting devices are used in the optical interconnection techniques. When mountability to external substrates is concerned in a semiconductor photodetector device used in the optical interconnection techniques, it will be preferred if an electrode (signal electrode) for taking out signals from the photodetector device is arranged on a surface opposite from a light-incident surface. Examples of such semiconductor photodetector devices are disclosed in Japanese Patent Application Laid-Open Nos. HEI 3-104287, HEI 6-296035, and 2002-353564. These publications disclose semiconductor photodetector devices of back-illuminated type in which a plurality of compound semiconductor layers are formed on one main face side of a semiconductor substrate, while light is incident from the other main face side. For the following purposes, these back-illuminated semiconductor photodetector devices partly thin the portion of the substrate located under the photodetecting part, while surrounding this portion with a part maintaining the thickness of the substrate. The first purpose is to prevent signals from deteriorating or disappearing because of light absorption by the semiconductor substrate. The second purpose is to prevent the semiconductor photodetector devices from being damaged or broken when mounting the semiconductor photodetector devices onto external substrates by wire bonding or bump bonding. However, there is a limit to reducing the size of the above-mentioned back-illuminated semiconductor photodetector devices, since there is a portion maintaining the substrate thickness in order to keep mechanical strength. When forming an array of semiconductor photodetector devices by providing a plurality of photodetecting parts in particular, the pitch between the photodetecting parts is hard to narrow, whereby the semiconductor photodetector device array must increase its size.	<SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a schematic plan view showing the semiconductor photodetector device in accordance with a first embodiment. FIG. 2 is a schematic sectional view taken along the line II-II of FIG. 1 . FIG. 3 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 4 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 5 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 9 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 10 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 11 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 12 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 13 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 14 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 15 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 16 is a schematic sectional view showing the semiconductor photodetector device in accordance with a second embodiment. FIG. 17 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the second embodiment. FIG. 18 is a schematic sectional view showing the semiconductor photodetector device in accordance with a third embodiment. FIG. 19 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the third embodiment. FIG. 20 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the third embodiment. FIG. 21 is a schematic sectional view showing the semiconductor photodetector device in accordance with a fourth embodiment. FIG. 22 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fourth embodiment. FIG. 23 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fourth embodiment. FIG. 24 is a schematic plan view showing the semiconductor photodetector device in accordance with a fifth embodiment. FIG. 25 is a schematic sectional view taken along the line XXV-XXV of the semiconductor photodetector device shown in FIG. 24 . FIG. 26 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 27 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 28 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 29 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 30 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 31 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 32 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 33 is a schematic sectional view showing the semiconductor photodetector device in accordance with a sixth embodiment. FIG. 34 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the sixth embodiment. FIG. 35 is a schematic sectional view showing the semiconductor photodetector device in accordance with a seventh embodiment. FIG. 36 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the seventh embodiment. FIG. 37 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the seventh embodiment. FIG. 38 is a schematic sectional view showing the semiconductor photodetector device in accordance with an eighth embodiment. FIG. 39 is a schematic sectional view of the semiconductor photodetector device array in accordance with an embodiment. FIG. 40 is a schematic sectional view of the semiconductor photodetector device array in accordance with an embodiment. FIG. 41 is a schematic sectional view showing the structure of the optical interconnection system in accordance with an embodiment. detailed-description description="Detailed Description" end="lead"?	TECHNICAL FIELD The present invention relates to a semiconductor photodetector device and a method of manufacturing the same. BACKGROUND ART Recently, as the CPU driving frequency has been becoming higher (e.g., 10 GHz or higher), attention has been directed toward optical interconnection techniques in which signals within and between system apparatus are transmitted by light. Semiconductor devices such as semiconductor photodetector devices and semiconductor light-emitting devices are used in the optical interconnection techniques. When mountability to external substrates is concerned in a semiconductor photodetector device used in the optical interconnection techniques, it will be preferred if an electrode (signal electrode) for taking out signals from the photodetector device is arranged on a surface opposite from a light-incident surface. Examples of such semiconductor photodetector devices are disclosed in Japanese Patent Application Laid-Open Nos. HEI 3-104287, HEI 6-296035, and 2002-353564. These publications disclose semiconductor photodetector devices of back-illuminated type in which a plurality of compound semiconductor layers are formed on one main face side of a semiconductor substrate, while light is incident from the other main face side. For the following purposes, these back-illuminated semiconductor photodetector devices partly thin the portion of the substrate located under the photodetecting part, while surrounding this portion with a part maintaining the thickness of the substrate. The first purpose is to prevent signals from deteriorating or disappearing because of light absorption by the semiconductor substrate. The second purpose is to prevent the semiconductor photodetector devices from being damaged or broken when mounting the semiconductor photodetector devices onto external substrates by wire bonding or bump bonding. However, there is a limit to reducing the size of the above-mentioned back-illuminated semiconductor photodetector devices, since there is a portion maintaining the substrate thickness in order to keep mechanical strength. When forming an array of semiconductor photodetector devices by providing a plurality of photodetecting parts in particular, the pitch between the photodetecting parts is hard to narrow, whereby the semiconductor photodetector device array must increase its size. DISCLOSURE OF THE INVENTION It is the object of the present invention to provide a semiconductor photodetector device which can be made smaller while keeping a sufficient mechanical strength, and a method of manufacturing the same. In one aspect, the present invention relates to a semiconductor photodetector device. This photodetector device comprises a multilayer structure including a plurality of compound semiconductor layers laminated and having first and second main faces opposing each other; a photodetecting region formed near the first main face within the multilayer structure; a first electrode arranged on the first main face of the multilayer structure and electrically connected to the photodetecting region; a second electrode arranged on the second main face of the multilayer structure and electrically connected to the first electrode; a third electrode arranged on the second main face of the multilayer structure and electrically connected to a part near the second main face in the multilayer structure; and a light-transmitting layer, optically transparent to incident light and arranged on the first main face of the multilayer structure, covering the photodetecting region and first electrode. In this photodetector device, the mechanical strength of the multilayer structure is held by the light-transmitting layer even when a plurality of compound semiconductor layers included in the multilayer structure are made thinner. Unlike the prior art mentioned above, there is no need to form a part maintaining the substrate thickness, whereby the device is easily made smaller. In this photodetector device, the second and third electrodes for taking out output signals are arranged on the second main face of the multilayer structure. Therefore, the photodetector device can be mounted while its second main face positioned on the opposite side of the photodetecting region opposes a mounting surface of an external substrate or the like. As a result, the photodetector device can be mounted easily. The light-transmitting layer may include a film made of silicon oxide and a glass substrate. The glass substrate may be secured to the multilayer structure through the film made of silicon oxide. Silicon oxide can be fused to glass, and thus can bond the multilayer structure and glass substrate to each other without using other adhesives. Therefore, the light incident on the glass substrate side can reach the multilayer structure without being absorbed by adhesives. The light-transmitting layer may include a film made of silicon oxide or a resin without a glass substrate. The plurality of compound semiconductor layers may include a high-concentration carrier layer of a first conductive type, a light-absorbing layer of the first conductive type, and a cap layer of the first conductive type. The photodetecting region may be a region of a second conductive type including at least a part of the cap layer. The multilayer structure may further comprise a depression formed about the photodetecting region, and a wiring electrode arranged within the depression. The first electrode may be electrically connected to the second electrode through the wiring electrode. The third electrode may be electrically connected to a part positioned near the photodetecting region in the high-concentration carrier layer. The depression formed about the photodetecting region separates the photodetecting region at least partly from the other parts of the multilayer structure, and thus can reduce parasitic capacitance by a greater amount. When the wiring electrode arranged in the depression is utilized as a through electrode penetrating through the multilayer structure, the through electrode can be formed very easily. When the through electrode is used, the electrode is directly drawn from the high-concentration carrier layer of the photodetecting part, whereby the series resistance can be reduced greatly. The photodetector device of the present invention may further comprise a through lead penetrating through the multilayer structure. The first electrode may be electrically connected to the second electrode through the through electrode. The third electrode may be electrically connected to the high-concentration carrier layer. In this case, the through lead can electrically connect the first and second electrodes to each other reliably. Since the electrode is directly drawn from the high-concentration carrier layer, the series resistance can be reduced greatly. The second and third electrodes may include respective pad electrodes, while respective bump electrodes may be arranged on these pad electrodes. The photodetector device may further comprise a light-reflecting film, provided on the second main face, covering the photodetecting region. Light having passed the multilayer structure without being absorbed is reflected by the light-reflecting film, and then is incident on the multilayer structure again, which increases the quantity of light absorbed by the multilayer structure, whereby photosensitivity can be improved more. The light-transmitting layer may include a lens part converging the incident light. In this case, the incident light can be converged efficiently even when the photodetecting region is smaller than the illuminating area of the incident light. The photodetector device in accordance with the present invention may comprise a plurality of photodetecting regions arranged in a row. Another aspect of the present invention relates to a method of manufacturing a semiconductor photodetector device. This method comprises the steps of preparing a semiconductor substrate; providing a multilayer structure on the semiconductor substrate, the multilayer structure including a plurality of compound semiconductor layers laminated and having first and second main faces opposing each other, the second main face facing the semiconductor substrate; forming a photodetecting region near the first main face within the multilayer structure; providing a first electrode electrically connected to the photodetecting region onto the first main face of the multilayer structure; forming a light-transmitting layer optically transparent to incident light onto the first main face of the multilayer structure so as to cover the photodetecting region and first electrode; removing the semiconductor substrate after forming the light-transmitting layer; and forming a second electrode electrically connected to the first electrode onto the second main face of the multilayer structure while forming a third electrode electrically connected to a part near the second main face in the multilayer structure onto the second main face after removing the semiconductor substrate. Since the semiconductor substrate is removed after forming the light-transmitting layer onto the first main face of the multilayer structure, a semiconductor photodetector device in which the light-transmitting layer is arranged on the opposite side of the second and third electrodes for taking out output signals can be manufactured easily. Since the light-transmitting layer remains after removing the semiconductor substrate, the mechanical strength of the multilayer structure will be held by the light-transmitting layer even if the plurality of compound semiconductor layers included in the multilayer structure are made thinner. Unlike the prior art mentioned above, there is no need to leave a part maintaining the substrate thickness, whereby the device easily reduces its size. Before forming the light-transmitting layer, the semiconductor substrate keeps the mechanical strength. The step of forming the light-transmitting layer may include the steps of forming a film made of silicon oxide so as to cover the photodetecting region and first electrode; and securing a glass substrate optically transparent to the incident light onto the film made of silicon oxide. Silicon oxide can be fused to glass, and thus can bond the multilayer structure and glass substrate to each other without using other adhesives. Therefore, the light incident on the glass substrate side can reach the multilayer structure without being absorbed by adhesives. The step of forming the light-transmitting layer may include the step of forming a film made of silicon oxide or a resin so as to cover the photodetecting region and first electrode. The step of removing the semiconductor substrate may include the step of removing the semiconductor substrate by wet etching. The step of forming the multilayer structure may include the step of forming an etching stop layer for stopping wet etching between the semiconductor substrate and the plurality of compound semiconductor layers. Using an etchant which can etch the semiconductor substrate but not the etching stop layer can selectively remove the semiconductor substrate. Therefore, the semiconductor substrate can be removed reliably and easily while leaving the plurality of compound semiconductor layers. The method in accordance with the present invention may further comprise the step of removing the etching stop layer by wet etching after removing the semiconductor substrate. Using an etchant which can etch the etching stop layer but not the compound semiconductor layers can selectively remove the etching stop layer alone. Therefore, the etching stop layer can be removed reliably and easily while leaving the plurality of compound semiconductor layers. The plurality of compound semiconductor layers may include a high-concentration carrier layer of a first conductive type, a light-absorbing layer of the first conductive type, and a cap layer of the first conductive type. The step of forming the multilayer structure may include the step of successively laminating the high-concentration carrier layer, light-absorbing layer, and cap layer on the semiconductor substrate. The step of forming the photodetecting region may include the step of forming a region of a second conductive type including at least a part of the cap layer as the photodetecting region. This method may further comprise the steps of forming a depression about the photodetecting region; and providing a wiring electrode for electrically connecting the first electrode to the second electrode in the depression. The step of forming the third electrode may include the step of forming the third electrode such that the third electrode is electrically connected to a part positioned near the photodetecting region in the high-concentration carrier layer. The depression formed about the photodetecting region separates the photodetecting region at least partly from the other parts of the multilayer structure, and thus can reduce parasitic capacitance by a greater amount. When the wiring electrode arranged in the depression is utilized as a through electrode penetrating through the multilayer structure, the through electrode can be formed very easily. The step of forming the second electrode may include the step of forming a through lead penetrating through the multilayer structure, and electrically connecting the first electrode to the second electrode through the through lead. The step of forming the third electrode may include the step of forming the third electrode such that the third electrode is electrically connected to the high-concentration carrier layer. In this case, the through lead can electrically connect the first and second electrodes to each other reliably. Also, since the electrode is directly drawn from the high-concentration carrier layer, the series resistance can be reduced greatly. The method in accordance with the present invention may further comprise the step of forming a light-reflecting film covering the photodetecting region onto the second main face of the multilayer structure. In this case, light having passed the multilayer structure without being absorbed is reflected by the light-reflecting film, and then is incident on the multilayer structure again, which increases the quantity of light absorbed by the multilayer structure, whereby photosensitivity can be improved. The light-transmitting layer may include a lens part converging the incident light. In this case, the incident light can be converged efficiently even when the photodetecting region is smaller than the illuminating area of the incident light. The present invention will further be understood from the following detailed descriptions and attached drawings. The attached drawings are given by illustration only, and do not intend to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view showing the semiconductor photodetector device in accordance with a first embodiment. FIG. 2 is a schematic sectional view taken along the line II-II of FIG. 1. FIG. 3 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 4 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 5 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 6 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 7 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 8 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 9 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 10 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 11 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 12 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 13 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 14 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 15 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the first embodiment. FIG. 16 is a schematic sectional view showing the semiconductor photodetector device in accordance with a second embodiment. FIG. 17 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the second embodiment. FIG. 18 is a schematic sectional view showing the semiconductor photodetector device in accordance with a third embodiment. FIG. 19 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the third embodiment. FIG. 20 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the third embodiment. FIG. 21 is a schematic sectional view showing the semiconductor photodetector device in accordance with a fourth embodiment. FIG. 22 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fourth embodiment. FIG. 23 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fourth embodiment. FIG. 24 is a schematic plan view showing the semiconductor photodetector device in accordance with a fifth embodiment. FIG. 25 is a schematic sectional view taken along the line XXV-XXV of the semiconductor photodetector device shown in FIG. 24. FIG. 26 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 27 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 28 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 29 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 30 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 31 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 32 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the fifth embodiment. FIG. 33 is a schematic sectional view showing the semiconductor photodetector device in accordance with a sixth embodiment. FIG. 34 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the sixth embodiment. FIG. 35 is a schematic sectional view showing the semiconductor photodetector device in accordance with a seventh embodiment. FIG. 36 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the seventh embodiment. FIG. 37 is a schematic sectional view showing a manufacturing step of the semiconductor photodetector device in accordance with the seventh embodiment. FIG. 38 is a schematic sectional view showing the semiconductor photodetector device in accordance with an eighth embodiment. FIG. 39 is a schematic sectional view of the semiconductor photodetector device array in accordance with an embodiment. FIG. 40 is a schematic sectional view of the semiconductor photodetector device array in accordance with an embodiment. FIG. 41 is a schematic sectional view showing the structure of the optical interconnection system in accordance with an embodiment. EXPLANATIONS OF NUMERALS OR LETTERS 1: glass substrate; 121a: lens part; 2: etching stop layer; 3 (3a): high-concentration carrier layer; 5 (5a): light-absorbing layer; 7 (7a): cap layer; 9: photodetecting region; 10: film; 11: photodetecting part; 12: depression; 17: contact electrode; 21: first electrode; 23: contact electrode; 25: first wiring electrode; 27: first pad electrode (second electrode); 31: third electrode; 33: second pad electrode; 35: second wiring electrode; 41: bump electrode; 51: semiconductor substrate; 60: film; 131a: lens part; 71: contact electrode; 73: through lead; 81: third electrode; 83: contact electrode; LS1, LS2: layer structure; PD1 to PD8: semiconductor photodetector device; PDA1, PDA2: semiconductor photodetector array. BEST MODES FOR CARRYING OUT THE INVENTION Semiconductor photodetector devices in accordance with embodiments of the present invention will be explained with reference to the drawings. In the explanation, the same numerals will be used for the same constituents or those having the same functions without repeating their overlapping descriptions. FIRST EMBODIMENT FIG. 1 is a schematic plan view showing the semiconductor photodetector device in accordance with a first embodiment. FIG. 2 is a schematic sectional view taken along the line II-II of FIG. 1. FIG. 1 does not depict bump electrodes 41. A semiconductor photodetector device PD1 comprises a multilayer structure LS1 and a glass substrate 1. The glass substrate 1 has two main faces opposing each other, i.e., front face 121 and rear face 122. The multilayer structure LS1 is provided on the rear face 122 of the glass substrate 1. This semiconductor photodetector device PD1 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS1 from the glass substrate 1 side. The semiconductor photodetector device PD1 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The multilayer structure LS1 includes an etching stop layer 2, an n-type (first conductive type) high-concentration carrier layer 3, an n-type light-absorbing layer 5, and an n-type cap layer 7. The multilayer structure LS1 has two main faces opposing each other, i.e., front face 101 and rear face 102. A passivation film 19 which will be explained later is formed on the front face 101, whereas an electrically insulating film (passivation film) 20 is formed on the rear face 102. The electrically insulating film 20 is made of SiNX and has a thickness of about 0.2 μm, for example. The multilayer structure LS1 has a photodetecting part 11 and a depression 12 surrounding the photodetecting part 11. The photodetecting part 11 includes an n-type high-concentration carrier layer 3a, an n-type light-absorbing layer 5a, and an n-type cap layer 7a, and has a mesa form (a truncated cone form in this embodiment). The photodetecting part 11 has a p-type (second conductive type) photodetecting region 9. The photodetecting region 9 includes at least a part of the cap layer 7a. In this embodiment, the cap layer 7a and light-absorbing layer 5 are partly included in the photodetecting region 9. The top part of the photodetecting part 11 and the photodetecting region 9 are circular as seen in the direction along which light is incident. At the top part of the photodetecting part 11, a depression 13 is formed on the outside of photodetecting region 9 as seen in the direction along which light is incident. The depression 13 is formed like a groove such as to reach the high-concentration carrier layer 3a and surround the photodetecting region 9. Thus, the photodetecting part 11 includes a mesa-like inner part 11a containing the photodetecting region 9 and an outer part 11b surrounding the inner part 11a. The depression 13 is formed like letter C extending along the edge of the photodetecting region 9 while leaving a portion of the top part of the photodetecting part 11 as seen in the direction along which light is incident. A contact electrode 17 is arranged on the bottom part of the depression 13. The contact electrode 17 is electrically connected to the high-concentration carrier layer 3a. The contact layer 17 is made of a multilayer body of Au-Ge/Ni/Au, and has a thickness of about 1000 mn. As with the depression 13, the contact electrode 17 is formed like letter C as seen in the direction along which light is incident. On the front face of the photodetecting part 11, i.e., front face 101 of the multilayer structure LS1, the passivation film 19 is formed so as to cover the photodetecting region 9. The passivation film 19 is made of SiNX, for example. In this embodiment, the passivation film 19 functions as an antireflection film. Therefore, the thickness of the passivation film 19 is set to λ/(4n), where n is the refractive index of the passivation film 19, and λ is the received light wavelength. In the case of a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example, the thickness of the passivation film 19 is 1000 to 3000 Å. An antireflection film may be formed separately from the passivation film 19 so as to cover the photodetecting region 9. The high-concentration carrier layers 3 and 3a are compound semiconductor layers and are made of AlGaAs (where Al composition is 0.3) having a carrier concentration of about 1×1018/cm3. The high-concentration carrier layers 3 and 3a have a thickness of about 2 μm. The light-absorbing layers 5 and 5a are compound semiconductor layers and are made of GaAs having a carrier concentration of about 1×1014/cm3, for example. The light-absorbing layers 5 and 5a have a thickness of about 3 μm. The cap layers 7 and 7a are compound semiconductor layers and are made of AlGaAs (where Al composition ratio is 0.3) having a carrier concentration of about 5×1015/cm3, for example. The cap layers 7 and 7a have a thickness of about 0.3 μm. The Al composition ratio in the cap layers 7 and 7a is preferably 0.3 or greater. Though the Al composition ratio x of 0.04 is sufficient for detecting light having a wavelength of 0.85 μm or longer, it will be more preferred if the Al composition ratio is 0.3 or greater. However, the Al composition ratio of the cap layers 7 and 7a can be determined as appropriate according to the wavelength of light to be detected. For detecting short-wavelength light having a wavelength of 0.65 μm, for example, the Al composition ratio of 0.4 or greater is necessary. The photodetecting region 9 is provided on the front face 101 of the multilayer structure LS1. The photodetecting region 9 is formed by thermally diffusing p-type impurities (e.g., Zn) into a desirable area of the cap layer 7a and inverting this area into p-type. The photodetecting region 9 has a depth of about 0.4 μm and a diameter of 5 to 200 μm. The depression (groove) 13 has a width of about 5 μm. The diameter of received light depends on a property required for the photodetector device and can be designed within a broad range of 1 μm to 10 mm. A first electrode 21 is arranged on the front face 101 of the multilayer structure LS1. The first electrode 21 includes a contact electrode 23 and an electrode part 25a which will be explained later. The contact electrode 23 is formed like a ring on the front face of the photodetecting region 9, and is electrically connected to the photodetecting region 9. The contact electrode 23 is made of Ti/Pt/Au, and has a thickness of about 1000 nm. The contact layer 23 is arranged so as to be buried in the photodetecting region 9 in the cap layer 7a in FIG. 2, but may be arranged on the cap layer 7a and photodetecting region 9 as well. A first wiring electrode 25 is electrically connected to the contact electrode 23. The first wiring electrode 25 partly covers the photodetecting part 11 and depression 12, and is arranged on the passivation film 19. The first wiring electrode 25 comprises an electrode part 25a arranged on the top part of the photodetecting part 11 and an electrode part 25b arranged within the depression 12. The first wiring electrode 25 is made of Ti/Pt/Au, and has a thickness of about 1.5 μm. The electrode part 25a positioned on the photodetecting part 11 is arranged on the contact electrode 23 such as to expose at least a part of the photodetecting region 9, and is shaped like a ring. The electrode part 25a is connected to the contact electrode 23 through a contact hole 19a formed in the passivation film 19. As a second electrode, a first pad electrode 27 is arranged on the rear face 102 of the multilayer structure LS1. The first pad electrode 27 is made of Ti/Pt/Au, and has a thickness of about 1.5 μm. The first pad electrode 27 is electrically connected to the first wiring electrode 25 (electrode part 25b) through a contact hole 29 penetrating through the electrically insulating film 20, etching stop layer 2, and passivation film 19. As a result, the contact electrode 23 is electrically connected to the first pad electrode 27 through the first wiring electrode 25. A bump electrode 41 is arranged on the first pad electrode 27. A third electrode 31 is arranged on the rear face 102 of the multilayer structure LS1. The third electrode 31 includes a second pad electrode 33 and a second wiring electrode 35. The second pad electrode 33 and second wiring electrode 35 are made of Ti/Pt/Au, and have a thickness of about 1.5 μm. The second pad electrode 33 is electrically connected to the high-concentration carrier layer 3a and contact electrode 17 through a contact hole 37 penetrating through the electrically insulating film 20, etching stop layer 2, and high-concentration carrier layer 3. The second wiring electrode 35 is formed below the rear face of the photodetecting region 9 such as to cover this rear face, and functions as a light-reflecting film. A light-reflecting film may be formed below the photodetecting region 9 separately from the second wiring electrode 35. A bump electrode 41 is arranged on the second pad electrode 33 as in the first pad electrode 27. The taking out of electrodes from the photodetecting region 9 is realized by the contact electrode 23, first wiring electrode 25, first pad electrode 27, and bump electrode 41. The taking out of electrodes from the high-concentration carrier layer 3a is realized by the contact electrode 17, second pad electrode 33, and bump electrode 41. A film 10 is formed on the front face 101 of the multilayer structure LS1 so as to cover the photodetecting region 9 and first electrode 21 (the contact electrode 23 and the electrode part 25a of the first wiring electrode 25). The film 10 is made of silicon oxide (SiO2) and is optically transparent to incident light. The surface 10a on the side opposite from the multilayer structure LS1 in the film 10 is flattened. The film 10 has a thickness of 3 to 10 μm. The glass substrate 1 is in contact with and attached to the surface 10a of the film 10. The glass substrate 1 has a thickness of about 0.3 mm and is optically transparent to incident light. In the following, a method of manufacturing the semiconductor photodetector device PD1 will be explained with reference to FIGS. 3 to 15. FIGS. 3 to 15 are views for explaining this manufacturing method, and show a vertical section of the semiconductor photodetector device PD1. This manufacturing method successively executes the following steps (1) to (13): Step (1) First, a semiconductor substrate 51 is prepared. The semiconductor substrate 51 has a thickness of 300 to 500 μm and is made of n-type GaAs having a carrier concentration of about 1×1018/cm3, for example. A buffer layer 53 and an etching stop layer 2 are successively grown on one main face (front face) 111 of the semiconductor substrate 51 by hydride vapor-phase growth, chloride vapor-phase growth, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like, so as to be laminated (see FIG. 3). Thereafter, an n-type high-concentration carrier layer 3, an n-type light-absorbing layer 5, and an n-type cap layer 7 are successively grown on the etching stop layer 2 by hydride vapor-phase growth, chloride vapor-phase growth, MOCVD, MBE, or the like, so as to be laminated (see FIG. 3). The buffer layer 53 is made of nondoped GaAs and has a thickness of about 0.05 μm. The etching stop layer 2 is made of nondoped AlGaAs (having an Al composition of 0.5) and has a thickness of about 1.0 μm. The etching stop layer 2 is formed so as to be positioned between the semiconductor substrate 51 and high-concentration carrier layer 3. It will be preferred if the etching stop layer 2 has an Al composition ratio of 0.4 or greater. This is because AlGaAs having an Al composition ratio of 0.4 or greater is harder to be etched by an etchant used when etching GaAs which will be explained later. The foregoing step (1) forms the multilayer structure LS1 and buffer layer 53 on the front face 111 of the semiconductor substrate 51. Step (2) Next, a film made of SiO2 or SiNX is formed on the cap layer 7. Then, the film 55 is patterned, so as to provide an opening 55a at a position to form a photodetecting region 9 (see FIG. 4). Thereafter, using the patterned film 55 as a mask, impurities (e.g., Zn) are thermally diffused into the cap layer 7, so as to invert the conductive type of a portion of the cap layer 7 into p-type. Thus, the photodetecting region 9 is formed near the front face 101 remote from the semiconductor substrate 51 within the multilayer structure LS1 (see FIG. 4). Thereafter, the film 55 is removed by buffered hydrofluoric acid (BHF). Step (3) Next, a resist film 56 having an opening 56a at a position to form a depression 13 is formed on the cap layer 7. The resist film 56 can be formed by using photolithography. Then, using the resist film 56 as a mask, etching (wet etching) is performed with a mixed liquid of Br2 and methanol until the high-concentration carrier layer 3 is exposed. This forms the depression 13 (see FIG. 5). Subsequently, the resist film 56 is removed. Step (4) Next, a resist film 57 having an opening 57a at a position to form a depression 12 is formed on the cap layer 7. The resist film 57 can be formed by using photolithography. Then, using the resist film 57 as a mask, etching (wet etching) is performed with a mixed liquid of Br2 and methanol until the etching stop layer 2 is exposed, so as to form the depression 12. This forms a photodetecting part 11 in a mesa form (see FIG. 6). Namely, the photodetecting part 11 includes the high-concentration carrier layer 3a, light-absorbing layer 5a, and cap layer 7a. Here, arranging the resist film 57 over the outer part 11b can appropriately regulate the advancing of etching not only in the depth direction but also in lateral directions, which makes it possible to form the depression 13 and photodetecting part 11 properly. As a result, the yield at the time of manufacturing the semiconductor photodetector device PD1 can be made higher. Thereafter, the resist film 57 is removed. Step (5) Next, a resist film (not depicted) having an opening at a position corresponding to the depression 13 is formed. Then, on the high-concentration carrier layer 3 (3a) exposed by forming the depression 13, a contact electrode 17 made of Au-Ge/Ni/Au is formed by vapor deposition using this resist film as a mask and liftoff (see FIG. 7). Also, a resist film is formed again such as to have an opening at a position to form a contact electrode 23, and the contact electrode 23 made of Ti/Pt/Au is formed in the photodetecting region 9 by vapor deposition and liftoff while using this resist film as a mask (see FIG. 7). Subsequently, the resist film is removed. The contact electrode 23 is formed so as to be buried in the photodetecting region 9 in the cap layer 7a in FIG. 7, but may be formed on the front face of the cap layer 7a and photodetecting region 9 as well. Step (6) Next, a passivation film 19 made of SiNX is formed on the front face 101 of the multilayer structure LS1 by PCVD. Then, a resist film (not depicted) having openings positioned above the contact electrodes 17, 23 is formed, and a contact hole 19a is formed in the passivation film 19 (see FIG. 8). Subsequently, the resist film is removed. Step (7) Next, a resist film (not depicted) having an opening at a position corresponding to a first wiring electrode 25 is formed. Then, using this resist film as a mask, the first wiring electrode 25 made of Ti/Pt/Au is formed by liftoff (see FIG. 9). The above-mentioned steps (6) and (7) form a first electrode 21 on the front face 101 side of the multilayer structure LS1. Subsequently, the resist film is removed. Thereafter, sintering is performed in an H2 atmosphere. Step (8) Next, a film 10 is formed and flattened oh the front face 101 of the multilayer structure LS1 so as to cover the photodetecting region 9 and first electrode 21 (see FIG. 10). Here, the surface 10a positioned on the side opposite from the multilayer structure LS1 in the film 10 is flattened as a front face of a structure including the multilayer structure LS1 and semiconductor substrate 51. The film 10 can be formed by plasma chemical vapor deposition or coating. Here, “flattened” does not always mean that there are no irregularities at all. Slight irregularities may exist as long as a glass substrate 1 and the film 10 can be fused to each other while a surface of the glass substrate 1 and the surface 10a of the film 10 are in contact with each other when the glass substrate 1 and the semiconductor substrate 51 are pressed and heated while being stacked together with the film 10 interposed therebetween in step (9) which will be explained later. Step (9) Next, the glass substrate 1 is attached to the semiconductor 51 formed with the multilayer structure LS1, buffer layer 53, and film 10 (see FIG. 11). First, the glass substrate 1 is prepared, and one main face (rear face) 122 of the glass substrate 1 is cleaned. Then, the glass substrate 1 and the semiconductor substrate 51 are stacked such that the cleaned rear face 122 of the glass substrate 1 and the surface 10a of the film 10 are in contact with each other. Subsequently, the stacked glass substrate 1 and semiconductor substrate 51 are pressed and heated, so as to attach the glass substrate 1 and film 10 to each other by fusion. Specifically, it will be preferred if the pressure applied to the stacked glass substrate 1 and semiconductor substrate 51 is about 98 kPa while the heating temperature is 500 to 700° C. Since the uppermost film 10 on the semiconductor substrate 51 is made of silicon oxide, the pressing and heating under such a condition fuses the surface 10a of the film 10 to the rear face 122 of the glass substrate 1, thereby securing the multilayer structure LS1 and semiconductor substrate 51 to the glass substrate 1. For performing this attaching step, it is desirable that not only the rear face 122 of the glass substrate 1 but also the surface 10a of the film 10 be clean. To this aim, it will be preferred if a contrivance is made such as to perform the fusing operation immediately after taking out the semiconductor substrate 51 from the PCVD apparatus used for forming the film 10, for example. Preferably, the glass substrate employed has a coefficient of thermal expansion close to that of GaAs. This can minimize the stress occurring between the semiconductor substrate 51 and glass substrate 1 because of the difference between their coefficients of thermal expansion in the cooling step after heating, and thus can suppress the decrease of bonding strength and occurrence of crystal defects due to the stress to the minimum. Step (10) Next, the semiconductor substrate 51 is removed. After the multilayer structure LS1 and semiconductor substrate 51 are secured to the glass substrate 1, the main face positioned on the side opposite from the glass substrate 1 in the semiconductor substrate 51, i.e., the rear face 112, is exposed. In this step, etching is performed from the rear face 112 side of the semiconductor substrate 51, so as to remove the semiconductor substrate 51 and buffer layer 53 (see FIG. 12). Specifically, an etchant exhibiting a lower etching rate to the etching stop layer 2 is used, so as to remove the semiconductor substrate 51 and buffer layer 53. This yields the glass substrate 1 mounted with the multilayer structure LS1. Preferably used as the etchant is a mixed solution (NH4OH:H2O2=1:5) of aqueous ammonia (NH4OH) and aqueous hydrogen peroxide (H2O2). First, the glass substrate 1 and semiconductor substrate 51 attached together are dipped into the mixed solution of NH4OH and H2O2. This etches the semiconductor substrate 51 from the rear side. When the etching advances to such an extent that the semiconductor substrate 51 and buffer layer 53 are removed, the etching stop layer 2 is exposed in the etchant. The etching stop layer 2 (Al0.5Ga0.5As) has a high tolerance to this etchant, whereby its etching rate becomes very low. Therefore, the etching automatically stops at the time when the etching stop layer 2 is exposed. Thus, the semiconductor substrate 51 and buffer layer 53 are removed. The semiconductor substrate 51 and buffer layer 53 may also be removed by chemical mechanical polishing (CMP) instead of etching. Step (11) Next, an electrically insulating film 20 made of SiNX is formed on the rear face 102 of the etching stop layer 2 by PCVD (see FIG. 13). Step (12) Next, a resist film (not depicted) having an opening at a position to form a contact hole 37 is formed on the electrically insulating film 20. Using this resist film as a mask, the electrically insulating film 20, etching stop layer 2, and high-concentration carrier layer 3 are etched (wet-etched) until the contact electrode 17 is exposed. This forms the contact hole 37 (see FIG. 14). Preferably employed as etchants are buffered hydrofluoric acid (BHF) for the electrically insulating film 20, hydrochloric acid (HCl) for the etching stop layer 2, and a mixed solution (NH4OH:H2O2=1:5) of aqueous ammonia (NH4OH) and aqueous hydrogen peroxide (H2O2) for the high-concentration carrier layer 3. Subsequently, the resist film is removed. Next, a resist film (not depicted) having an opening at a position to form a contact hole 29 is formed on the electrically insulating film 20. Using this resist film as a mask, the electrically insulating film 20, etching stop layer 2, and passivation film 19 are etched (wet-etched) until the first wiring electrode 25 (electrode part 25b) is exposed. This forms the contact hole 29 (see FIG. 14). Preferably employed as etchants are buffered hydrofluoric acid (BHF) for the electrically insulating film 20, and hydrochloric acid (HCl) for the passivation film 19. Subsequently, the resist film is removed. Step (13) Next, a resist film (not depicted) having openings at respective positions corresponding to a first pad electrode 27, a second pad electrode 33, and a second wiring electrode 35 is formed. Then, using this resist film as a mask, the first pad electrode 27, second pad electrode 33, and second wiring electrode 35 made of Ti/Pt/Au are formed by liftoff (see FIG. 15). At this time, the second wiring electrode 35 is formed so as to cover the rear face (the surface on the side opposite from the light-incident surface) of the photodetecting region 9. Here, the second pad electrode 33 and second wiring electrode 35 are formed integrally with each other. Subsequently, the resist film is removed. Thereafter, sintering is performed in an H2 atmosphere. Though the second pad electrode 33 and second wiring electrode 35 are formed integrally with each other, they may be formed separately from each other as well. These steps (1) to (13) complete the semiconductor photodetector device PD1 having the structure shown in FIGS. 1 and 2. The bump electrodes 41 can be obtained by forming solder on the first pad electrode (second electrode) 27 and second pad electrode 33 by plating, solder ball mounting, or printing, and then performing reflow. The bump electrodes 41 are not limited to solder, but may be gold bumps, nickel bumps, copper bumps, or conductive resin bumps containing a metal such as conductive filler. In this embodiment, the mechanical strength of the multilayer structure LS1 (high-concentration carrier layer 3, light-absorbing layer 5, cap layer 7, etc.) is held by the glass substrate 1 and film 10 even when the high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7 are made thinner. Unlike the conventional semiconductor photodetector devices, there is no need to form a part maintaining the substrate thickness, which makes it easier to reduce the size of the semiconductor photodetector device PD1. Since the first pad electrode 27 and third electrode 31 (the second pad electrode 33 and second wiring electrode 35) for taking out output signals are arranged on the rear face 102 of the multilayer structure LS1, the semiconductor photodetector device PD1 can be mounted while the rear face 102 (the main face on the side opposite from the front face 101 arranged with the photodetecting region 9) opposes a mounting surface of an external substrate or the like. Therefore, the semiconductor photodetector device PD1 can be mounted easily. Since the multilayer structure LS1 is secured to the glass substrate 1 by way of the film 10, the glass substrate 1 can be attached to the multilayer structure LS1 without using other adhesives. As with the glass substrate 1, silicon oxide constituting the film 10 is optically transparent to light to be detected. Therefore, the incident light transmitted through the glass substrate 1 can reach the multilayer structure LS1 (photodetecting region 9) without being absorbed by adhesives. This can prevent the sensitivity of photodetection from decreasing. The photodetecting part 11 has a mesa structure including the high-concentration carrier layer 3a, light-absorbing layer 5a, cap layer 7a, and photodetecting region 9, thereby being separated from its surrounding semiconductor layers. This can further reduce the parasitic capacitance. The first electrode 21 (the contact electrode 23 and the electrode part 25a of the first wiring electrode 25) is electrically connected to the first pad electrode (second electrode) 27 through the electrode part 25b of the first wiring electrode 25 positioned within the depression 12 formed such as to surround the photodetecting part 11. The third electrode 31 (the second pad electrode 33 and second wiring electrode 35) is electrically connected to the high-concentration carrier layer part 3a included in the photodetecting part 11. Consequently, the electrode part 25b in the depression 12 can be utilized as a part of a through electrode penetrating through the multilayer structure LS1, whereby the through electrode can be formed very easily. Using wet etching as a technique for forming the contact hole 29 can manufacture the semiconductor photodetector device PD1 at low cost with a favorable yield. Since the electrode is directly drawn from the high-concentration carrier layer 3a of the photodetecting part 11, the series resistance can be reduced greatly in this embodiment. The second wiring electrode 35 covering the photodetecting region 9 is formed on the rear face 102 of the multilayer structure LS1. Therefore, light having passed the light-absorbing layer 5a without being absorbed is reflected by the second wiring electrode 35, and then is incident on the light-absorbing layer 5a again and absorbed thereby, whereby photosensitivity can further be improved. In the manufacturing method in accordance with this embodiment, the film 10 covering the photodetecting region 9 and first electrode 21 is formed on the front face 101 of the multilayer structure LS1, the glass substrate 1 is attached to the film 10 such that the surface 10a of the film 10 is in contact with the rear face 122 of the glass substrate 1, and then the semiconductor substrate 51 is removed. This can easily manufacture the semiconductor photodetector device PD1 having a structure in which the glass substrate 1 is attached onto the front face 101 of the multilayer structure LS1 through the film 10. Since the glass substrate 1 and film 10 remain after removing the semiconductor substrate 51, the mechanical strength of the multilayer structure LS1 is held by the glass substrate 1 and film 10 in subsequent manufacturing steps. Before attaching the glass substrate 1, the semiconductor substrate 51 keeps the mechanical strength of the multilayer structure LS1. In the step of forming the multilayer structure LS1, the etching stop layer 2 for stopping wet etching is formed between the semiconductor substrate 51 and high-concentration carrier layer 3. Therefore, using etchants which cannot etch the etching stop layer 2 can selectively remove the semiconductor substrate 51. Consequently, the semiconductor substrate 51 can be removed reliably and easily while leaving the high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7. SECOND EMBODIMENT FIG. 16 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with a second embodiment. This semiconductor photodetector device PD2 differs from the semiconductor photodetector device PD1 in accordance with the first embodiment in that the glass substrate 1 is formed with a lens part 121a. The semiconductor photodetector device PD2 comprises a multilayer structure LS1 and the glass substrate 1. This semiconductor photodetector device PD2 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS1 from the glass substrate 1 side. The semiconductor photodetector device PD2 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The lens part 121a converging incident light is formed on the front face 121 of the glass substrate 1. The other part 121b of the front face 121 is thicker than the lens part 121a. Namely, the lens part 121a is depressed from the thickest part 121b of the front face 121. Next, a method of manufacturing the semiconductor photodetector device PD2 will be explained with reference to FIG. 17. FIG. 17 is a view for explaining this manufacturing method, and shows a vertical section of the semiconductor photodetector device PD2. This manufacturing method successively executes the following steps (1) to (13). Steps (1) to (8) are the same as steps (1) to (8) in the first embodiment, and thus will not be explained. Step (9) Next, the glass substrate 1 is attached to the semiconductor substrate 51 formed with the multilayer structure LS1, buffer layer 53, and film 10 (see FIG. 17). The attaching method is the same as that in step (9) in the first embodiment. Specifically, the glass substrate 1 having the front face 121 formed with the lens part 121a is prepared, and the rear face 122 of the glass substrate 1 is cleaned. Then, the glass substrate 1 and the semiconductor substrate 51 are stacked together such that the cleaned rear face 122 and the surface 10a remote from the multilayer structure LS1 in the film 10 are in contact with each other. Subsequently, the stacked glass substrate 1 and semiconductor substrate 51 are pressed and heated, so that the glass substrate 1 and film 10 are attached together by fusion. Details of this attaching method are the same as those in step (9) in the first embodiment. The alignment between the photodetecting region 9 on the semiconductor substrate 51 and the lens part 121a on the glass substrate 1 can easily be effected with reference to a marker provided on the rear face 122 side of the glass substrate 1 by providing the marker and using a double-sided aligner. Instead of providing the marker, the outer shape of the lens part 121a may be utilized as a marker. Steps (10) to (13) are the same as steps (10) to (13) in the first embodiment, and thus will not be explained here. These steps (1) to (13) complete the semiconductor photodetector device PD2 having the structure shown in FIG. 16. In this embodiment, as in the above-mentioned first embodiment, the mechanical strength of the multilayer structure LS1 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the glass substrate 1 and film 10, while the semiconductor photodetector device PD2 is easily made smaller. Also, the semiconductor photodetector device PD2 can be mounted easily. Since the glass substrate 1 is provided with the lens part 121a, the incident light can be received efficiently even when the photodetecting region 9 is smaller than the illuminating area of the incident light. As a result, the semiconductor photodetector device PD2 with an excellent S/N ratio and high reliability can be obtained. In this embodiment, the lens part 121a is formed as being depressed from the thickest part 121b in the front face 121 of the glass substrate 1. Therefore, the glass substrate 1 formed with the lens part 121a can easily be attached to the multilayer structure LS1. Since the lens part 121a can be processed before being attached, the processing method is less likely to be limited, whereby a higher degree of freedom is attained in terms of lens designing such as lens forms. The lens part 121a may be formed after attaching the glass substrate 1 to the semiconductor substrate 51 mounted with the multilayer structure LS1 and film 10. When the degree of freedom in lens designing is concerned, however, it will be preferred if the glass substrate 1 having the lens part 121a formed beforehand therewith is attached to the semiconductor substrate 51. THIRD EMBODIMENT FIG. 18 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with a third embodiment. This semiconductor photodetector device PD3 differs from the semiconductor photodetector device PD1 in accordance with the first embodiment in that it has a film made of silicon oxide (SiO2) or a resin instead of the glass substrate 1 and film 10. The semiconductor photodetector device PD3 comprises the multilayer structure LS1 and a film 60. The film 60 has two main faces opposing each other, i.e., front face 131 and rear face 132. The multilayer structure LS1 is provided on the rear face 132 of the film 60. This semiconductor photodetector device PD3 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS1 from the film 60 side. The semiconductor photodetector device PD3 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. On the front face 101 of the multilayer structure LS1, the film 60 is formed such as to cover the photodetecting region 9 and the first electrode 21 (the contact electrode 23 and the electrode part 25a of the first wiring electrode 25). The film 60 is made of silicon oxide or a resin (e.g., polyimide resin, PMMA, or epoxy resin). The film 60 has a thickness of about 50 μm and is optically transparent to incident light. A method of manufacturing the semiconductor photodetector device PD3 will now be explained with reference to FIGS. 19 and 20. FIGS. 19 and 20 are views for explaining this manufacturing method, and show a vertical section of the semiconductor photodetector device PD3. This manufacturing method successively executes the following steps (1) to (12). Steps (1) to (7) are the same as steps (1) to (7) in the first embodiment, and thus will not be explained. Step (8) Next, the film 60 is formed on the front face 101 side of the multilayer structure LS1 such as to cover the photodetecting region 9 and first electrode 21 (see FIG. 19). When the film 60 is made of silicon oxide, PCVD employing TEOS (Tetraethylorthosilicate) as a film-forming gas for forming a silicon oxide film (SiO2) can be used for forming the film 60, for example. When the film 60 is made of a resin, on the other hand, coating can be used for forming the film 60, for example. Step (9) Next, the semiconductor substrate 51 is removed. After forming the film 60, the rear face 112 positioned on the side opposite from the film 60 in the semiconductor substrate 51 is exposed. In this step, the semiconductor substrate 51 and buffer layer 53 are removed by etching from the rear face 112 side of the semiconductor substrate 51 (see FIG. 20). The method of etching the semiconductor substrate 51 and buffer layer 53 is the same as the etching method in step (10) in the first embodiment. Steps (10) to (12) are the same as steps (11) to (13) in the first embodiment, and thus will not be explained here. These steps (1) to (12) complete the semiconductor photodetector device PD3 having the structure shown in FIG. 18. In this embodiment, as in the above-mentioned first embodiment, the mechanical strength of the multilayer structure LS1 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the film 60, while the semiconductor photodetector device PD3 is easily made smaller. Also, the semiconductor photodetector device PD3 can be mounted easily. FOURTH EMBODIMENT FIG. 21 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with a fourth embodiment. This semiconductor photodetector device PD4 differs from the semiconductor photodetector device PD3 in accordance with the third embodiment in that the film 60 is formed with a lens part 131a. The semiconductor photodetector device PD4 comprises the multilayer structure LS1 and the film 60. This semiconductor photodetector device PD4 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS1 from the film 60 side. The semiconductor photodetector device PD4 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The front face 131 of the film 60 is formed with the lens part 131a converging incident light. The lens part 131a can be formed by wet etching. For example, as shown in FIG. 22, a resist film 63 having an opening 63a at a desirable position is formed on the front face 131 of the film 60. Then, as shown in FIG. 23, the film 60 is wet-etched while using the resist film 63 as a mask. Since etching proceeds isotropically in the wet etching, the lens part 131 having a lens effect is formed when the opening 63a of the resist film 63 and the photodetecting region 9 are appropriately aligned to each other. In this embodiment, as in the above-mentioned first embodiment, the mechanical strength of the multilayer structure LS1 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the film 60, while the semiconductor photodetector device PD4 is easily made smaller. Also, the semiconductor photodetector device PD4 can be mounted easily. Since the film 60 is provided with the lens part 131a, the incident light can be received efficiently even when the photodetecting region 9 is smaller than the illuminating area of the incident light. As a result, the semiconductor photodetector device PD4 with an excellent S/N ratio and high reliability can be obtained. FIFTH EMBODIMENT FIG. 24 is a schematic plan view showing the semiconductor photodetector device in accordance with a fifth embodiment. FIG. 25 is a schematic sectional view taken along the line XXV-XXV of FIG. 24. FIG. 24 does not depict bump electrodes 41. A semiconductor photodetector device PD5 comprises a multilayer structure LS2 and a glass substrate 1. The multilayer structure LS2 is provided on the rear face 122 of the glass substrate 1. This semiconductor photodetector device PD5 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS2 from the glass substrate 1 side. The semiconductor photodetector device PD5 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The multilayer structure LS2 includes an n-type (first conductive type) high-concentration carrier layer 3, an n-type light-absorbing layer 5, and an n-type cap layer 7. The multilayer structure LS2 has two main faces opposing each other, i.e., front face 103 and rear face 104. The cap layer 7a is formed with a p-type (second conductive type) photodetecting region 9. A passivation film 19 is formed on the front face 103 of the multilayer structure LS2. An electrically insulating film 20 is formed on the rear face 104 of the multilayer structure LS2. On the front face 103 of the multilayer structure LS2, a contact electrode 71 as a first electrode is arranged on the passivation film 19. The contact electrode 71 passes through a contact hole 19a formed in the passivation film 19, so as to be electrically connected to the photodetecting region 9. The contact electrode 71 is made of Ti/Pt/Au and has a thickness of about 1.5 μm. The multilayer structure LS2 is formed with a through hole TH extending from the front face 103 to the rear face 104. The electrically insulating film 20 also extends onto the wall face of the multilayer structure LS2 defining the through hole TH. A through lead 73 is provided inside of the electrically insulating film 20 within the through hole TH. One end part 73a of the through lead 73 passes through a contact hole 20a formed in the electrically insulating film 20, so as to be electrically connected to the contact electrode 71. A first pad electrode 27 (second electrode) and a third electrode 81 are arranged on the rear face 104 of the multilayer structure LS2. The first pad electrode 27 is formed such as to cover the through lead 73, and is electrically connected to an end part 73b on the side opposite from the end part 73a in the through lead 73. A bump electrode 41 is arranged on the first pad electrode 27. The taking out of electrodes from the photodetecting region 9 is realized by the contact electrode 71, through lead 73, first pad electrode 27, and bump electrode 41. The third electrode 81 includes a contact electrode 83, a second pad electrode 33, and a second wiring electrode 35. The contact electrode 83 passes through a contact hole 20b formed in the electrically insulating film 20, so as to be electrically connected to the high-concentration carrier layer 3. The second pad electrode 33 and second wiring electrode 35 are formed so as to cover the contact electrode 83, and are electrically connected to the contact electrode 83. A bump electrode 41 is arranged on the second pad electrode 33 as in the first pad electrode 27. The taking out of electrodes from the high-concentration carrier layer 3 is realized by the contact electrode 83, second pad electrode 33, and bump electrode 41. The second wiring electrode 35 is formed below the rear face of the photodetecting region 9 such as to cover this rear face, and functions as a light-reflecting film. A light-reflecting film may be formed below the photodetecting region 9 separately from the second wiring electrode 35. A film 10 is formed on the front face 103 side of the multilayer structure LS2 so as to cover the photodetecting region 9 and contact electrode 71. The glass substrate 1 is in contact with and attached to the surface 10a on the side opposite from the multilayer structure LS2 in the film 10. The glass substrate 1 has a thickness of about 0.3 mm, and is optically transparent to incident light. In the following, a method of manufacturing the semiconductor photodetector device PD5 will be explained with reference to FIGS. 26 to 32. FIGS. 26 to 32 are views for explaining the method of manufacturing the semiconductor photodetector device PD5, and show a vertical section of the semiconductor photodetector device PD5. This manufacturing method successively executes the following steps (1) to (10). Steps (1) and (2) are the same as steps (1) and (2) in the first embodiment, and thus will not be explained. Step (3) Next, a passivation film 19 made of SiNX is formed on the front face 103 of the cap layer 7 (multilayer structure LS2) by PCVD (see FIG. 26). Step (4) Next, a resist film (not depicted) having an opening at a position corresponding to the contact electrode 71 is formed, and the passivation film 19 is removed by buffered hydrofluoric acid (BHF) while using this resist film as a mask, so as to form a contact hole 19a in the passivation film 19 (see FIG. 27). Subsequently, the resist film is removed. Next, a resist film (not depicted) having an opening at a position corresponding to the contact hole 19a is formed again. Then, using this resist film as a mask, a contact electrode 71 made of Ti/Pt/Au is formed by vapor deposition and liftoff on the part of photodetecting region 9 exposed by the contact hole 19a (see FIG. 27 as above). Subsequently, the resist film is removed. Step (5) Next, a film 10 is formed and flattened on the front face 103 side of the multilayer structure LS2 so as to cover the photodetecting region 9 (passivation film 19) and contact electrode 71 (see FIG. 28). Here, the surface 10a positioned on the side opposite from the multilayer structure LS2 in the film 10 is flattened as a front face of a structure including the multilayer structure LS2 and semiconductor substrate 51. The method of forming the film 10 is the same as the forming method in step (8) in the first embodiment. Step (6) Next, a glass substrate 1 is attached to the semiconductor substrate 51 formed with the multilayer structure LS2, etching stop layer 2, and film 10 (see FIG. 29). The method of attaching the glass substrate 1 is the same as the attaching method in step (9) in the first embodiment. Step (7) Next, the semiconductor substrate 51 is removed. After the glass substrate 1 and semiconductor substrate 51 are attached to each other, the main face (rear face) 112 positioned on the side opposite from the glass substrate 1 in the semiconductor substrate 51 is exposed. This step starts etching from the rear face 112 side of the semiconductor substrate 51, so as to remove the semiconductor substrate 51, buffer layer 53, and etching stop layer 2 (see FIG. 30). Specifically, an etchant exhibiting a lower etching rate to the etching stop layer 2 is used at first, so as to remove the semiconductor substrate 51 and buffer layer 53. Subsequently, an etchant which can etch the etching stop layer 2 and exhibits a lower etching rate to the AlGaAs layer of the high-concentration carrier layer 3 is used, so as to remove the etching stop layer 2. This yields the glass substrate 1 mounted with the multilayer structure LS2. The method of etching the semiconductor substrate 51 and buffer layer 53 is the same as the etching method in step (10) in the first embodiment. After etching the semiconductor substrate 51 and buffer layer 53, the glass substrate 1 with the remaining etching stop layer 2 and multilayer structure LS2 is taken out of the mixed solution of NH4OH and H2O2, washed with water, dried, and thereafter dipped in a mixed solution of phosphoric acid (H3PO4), aqueous hydrogen peroxide, and water (H3PO4:H2O:H2O2=4:90:1). Since AlGaAs is hardly etched by the mixed solution of phosphoric acid, aqueous hydrogen peroxide, and water, only the etching stop layer 2 is etched, whereby the etching automatically stops when the AlGaAs layer of the high-concentration carrier layer 3 is exposed. Thus, the etching stop layer 2 is removed. The semiconductor substrate 51, buffer layer 53, and etching stop layer 2 may be removed by chemical mechanical polishing (CMP) as well. Step (8) Next, a resist film (not depicted) having an opening at a position to form a through hole TH is formed on the high-concentration carrier layer 3. Then, using this resist film as a mask, the multilayer structure LS2 and passivation film 19 are etched (dry-etched) until the contact electrode 71 is exposed. This forms the through hole TH (see FIG. 31). Subsequently, the resist film is removed. This dry etching is etching of about several micrometers and can be performed very easily. Next, an electrically insulating film 20 made of SiNX is formed on the front face of the high-concentration carrier layer 3 by PCVD (see FIG. 31). This forms the electrically insulating film 20 on the wall face of the multilayer structure LS2 defining the through hole TH. Step (9) Next, a resist film (not depicted) having an opening at a position corresponding to a contact electrode 83 is formed on the electrically insulating film 20. Then, using this resist film as a mask, the electrically insulating film 20 is removed by BHF, so as to form a contact hole 20b in the electrically insulating film 20 (see FIG. 31 as above). Subsequently, the resist film is removed. Next, a resist film (not depicted) having an opening at a position corresponding to the contact electrode 83 is formed. Then, using this resist film as a mask, the contact electrode 83 made of Ti/Pt/Au is formed by liftoff (see FIG. 31 as above). Subsequently, the resist film is removed. Step (10) Next, a resist film (not depicted) having openings at respective positions corresponding to a through lead 73 and a first pad electrode 27 is formed on the electrically insulating film 20. Then, using this resist film as a mask, the electrically insulating film 20 is removed by BHF, so as to form a contact film 20a in the electrically insulating film 20 (see FIG. 32). This exposes the contact electrode 71. Subsequently, the resist film is removed. Next, a resist film (not depicted) having openings at respective positions corresponding to a first pad electrode 27 (through lead 73), a second pad electrode 33, and a second wiring electrode 35 is formed. Then, using this resist film as a mask, the first pad electrode 27 (through lead 73), second pad electrode 33, and second wiring electrode 35 made of Ti/Pt/Au are formed by liftoff (see FIG. 32). The first pad electrode 27 and through lead 73 are formed integrally with each other. The second pad electrode 33 and second wiring electrode 35 are formed integrally with each other. Subsequently, the resist film is removed. Thereafter, sintering is performed in an H2 atmosphere. Though the first pad electrode 27 and through lead 73 are formed integrally with each other, they may be formed separately from each other. Similarly, though the second pad electrode 33 and second wiring electrode 35 are formed integrally with each other, they may be formed separately from each other. These steps (1) to (10) complete the semiconductor photodetector device PD5 having the structure shown in FIGS. 24 and 25. In this embodiment, as in the above-mentioned first embodiment, the mechanical strength of the multilayer structure LS2 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the glass substrate 1 and film 10, while the semiconductor photodetector device PD5 is easily made smaller. Also, the semiconductor photodetector device PD5 can be mounted easily. In this embodiment, the contact electrode 71 is electrically connected to the first pad electrode 27 through the through lead 73 penetrating through the multilayer structure LS2. Using the through lead 73 can reliably conduct the contact layer 71 to the first pad electrode 27. The second pad electrode 33 is electrically connected to the high-concentration carrier layer 3. Since an electrode is directly drawn from the high-concentration carrier layer 3, the series resistance can greatly be reduced. In the manufacturing method in accordance with this embodiment, the etching stop layer 2 is removed by wet etching after removing the semiconductor substrate 51. The wet etching selectively removes the etching stop layer 2 alone by using an etchant which can etch the etching stop layer 2 but not the high-concentration carrier layer 3. Therefore, the etching stop layer 2 can be removed reliably and easily while leaving the multilayer structure LS2. SIXTH EMBODIMENT FIG. 33 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with a sixth embodiment. This semiconductor photodetector device PD6 differs from the semiconductor photodetector device PD5 in accordance with the fifth embodiment in that the glass substrate 1 is formed with a lens part 121a. The semiconductor photodetector device PD6 comprises a multilayer structure LS2 and the glass substrate 1. This semiconductor photodetector device PD6 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS2 from the glass substrate 1 side. The semiconductor photodetector device PD6 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The lens part 121a for converging incident light is formed on the front face 121 of the glass substrate 1. The other part 121b of the front face 121 is thicker than the lens part 121a. Namely, the lens part 121a is depressed from the thickest part 121b of the front face 121. Next, a method of manufacturing the semiconductor photodetector device PD6 will be explained with reference to FIG. 34. FIG. 34 is a view for explaining this manufacturing method, and shows a vertical section of the semiconductor photodetector device PD6. This manufacturing method successively executes the following steps (1) to (10). Steps (1) to (5) are the same as steps (1) to (5) in the fifth embodiment, and thus will not be explained. Step (6) Next, the glass substrate 1 is attached to the semiconductor 51 formed with the multilayer structure LS2, etching stop layer 2, and film 10 (see FIG. 34). Specifically, the glass substrate 1 having the front face 121 formed with the lens part 121a is prepared, and the rear face 122 of the glass substrate 1 is cleaned. Then, the glass substrate 1 and the semiconductor substrate 51 are stacked such that the cleaned rear face 122 of the glass substrate 1 and the surface 10a remote from the multilayer structure LS2 in the film 10 are in contact with each other. Subsequently, the stacked glass substrate 1 and semiconductor substrate 51 are pressed and heated, so as to attach the glass substrate 1 and film 10 to each other by fusion. Details of this attaching method are the same as those in step (9) in the first embodiment. Steps (7) to (10) are the same as steps (7) to (13) in the fifth embodiment, and thus will not be explained here. These steps (1) to (10) complete the semiconductor photodetector device PD6 having the structure shown in FIG. 33. In this embodiment, as in the above-mentioned fifth embodiment, the mechanical strength of the multilayer structure LS2 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the glass substrate 1 and film 10, while the semiconductor photodetector device PD6 is easily made smaller. Also, the semiconductor photodetector device PD6 can be mounted easily. Since the glass substrate 1 is provided with the lens part 121a, the incident light can be received efficiently even when the photodetecting region 9 is smaller than the illuminating area of the incident light. As a result, the semiconductor photodetector device PD6 with an excellent S/N ratio and high reliability can be obtained. SEVENTH EMBODIMENT FIG. 35 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with a seventh embodiment. This semiconductor photodetector device PD7 differs from the semiconductor photodetector device PD5 in accordance with the fifth embodiment in that it has a film made of silicon oxide (SiO2) or a resin instead of the glass substrate 1 and film 10. The semiconductor photodetector device PD7 comprises the multilayer structure LS2 and a film 60. The film 60 has two main faces opposing each other, i.e., front face 131 and rear face 132. The multilayer structure LS2 is provided on the rear face 132 of the film 60. This semiconductor photodetector device PD7 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS2 from the film 60 side. The semiconductor photodetector device PD7 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. On the front face 103 of the multilayer structure LS2, the film 60 is formed such as to cover the photodetecting region 9 and the contact electrode 71. The film 60 is made of silicon oxide or a resin (e.g., polyimide resin, PMMA, or epoxy resin). The film 60 has a thickness of about 50 μm and is optically transparent to incident light. A method of manufacturing the semiconductor photodetector device PD7 will now be explained with reference to FIGS. 36 and 37. FIGS. 36 and 37 are views for explaining this manufacturing method, and show a vertical section of the semiconductor photodetector device PD7. This manufacturing method successively executes the following steps (1) to (9). Steps (1) to (4) are the same as steps (1) to (4) in the fifth embodiment, and thus will not be explained. Step (5) Next, a film 60 is formed on the front face 103 side of the multilayer structure LS2 so as to cover the photodetecting region 9 (passivation film 19) and contact electrode 71 (see FIG. 36). The method of forming the film 60 is the same as the forming method in step (8) in the third embodiment. Step (6) Next, the semiconductor substrate 51 is removed. The main face positioned on the side opposite from the film 60 in the semiconductor substrate 51, i.e., the rear face 112, is exposed after forming the film 60. This step removes the semiconductor substrate 51 and etching stop layer 2 by etching from the rear face 112 side of the semiconductor substrate 51 (see FIG. 37). The method of etching the semiconductor substrate 51 and etching stop layer 2 is the same as the etching method in step (7) in the above-mentioned fifth embodiment. Steps (7) to (9) are the same as steps (8) to (10) in the fifth embodiment, and thus will not be explained here. These steps (1) to (9) complete the semiconductor photodetector device PD7 having the structure shown in FIG. 35. In this embodiment, as in the above-mentioned fifth embodiment, the mechanical strength of the multilayer structure LS2 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the film 60, while the semiconductor photodetector device PD7 is easily made smaller. Also, the semiconductor photodetector device PD7 can be mounted easily. EIGHTH EMBODIMENT FIG. 38 is a schematic sectional view showing the structure of the semiconductor photodetector device in accordance with an eighth embodiment. This semiconductor photodetector device PD8 differs from the semiconductor photodetector device PD7 in accordance with the seventh embodiment in that the film 60 is formed with a lens part 131a. The semiconductor photodetector device PD8 comprises the multilayer structure LS2 and the film 60. This semiconductor photodetector device PD8 is a photodetector device of front-illuminated type in which light is incident on the multilayer structure LS2 from the film 60 side. The semiconductor photodetector device PD8 is a photodetector device for short-distance optical communications in the wavelength band of 0.85 μm, for example. The front face 131 of the film 60 is formed with the lens part 131a for converging incident light. The lens part 131a can be formed by wet etching. The wet etching for forming the lens part 131a is the same as the wet etching method explained in the above-mentioned fourth embodiment. In this embodiment, as in the above-mentioned fifth embodiment, the mechanical strength of the multilayer structure LS2 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the film 60, while the semiconductor photodetector device PD8 is easily made smaller. Also, the semiconductor photodetector device PD8 can be mounted easily. Since the film 60 is provided with the lens part 131a, the incident light can be received efficiently even when the photodetecting region 9 is smaller than the illuminating area of the incident light. As a result, the semiconductor photodetector device PD8 with an excellent S/N ratio and high reliability can be obtained. Modified examples of these embodiments will now be explained with reference to FIGS. 39 and 40. These modified examples are semiconductor photodetector device arrays PDA1 and PDA2 in which a plurality of photodetecting regions 9 are provided in a row. These photodetector device arrays PDA1 and PDA2 are of so-called front-illuminated type. In the photodetector array PDA1, a plurality of photodetecting parts 11 and photodetecting regions 9 are arranged one- or two-dimensionally as shown in FIG. 39. In the photodetector array PDA2, a plurality of photodetecting regions 9 are arranged one- or two-dimensionally as shown in FIG. 40. In the photodetector array PDA1, the mechanical strength of the multilayer structure LS1 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the glass substrate 1 as in the above-mentioned first embodiment. Also, the pitch between the photodetecting parts 11 and the pitch between the photodetecting regions 9 can be narrowed, whereby the photodetector array PDA1 is easily made smaller. In the photodetector array PDA2, the mechanical strength of the multilayer structure LS2 (laminated high-concentration carrier layer 3, light-absorbing layer 5, and cap layer 7) is held by the glass substrate 1 as in the above-mentioned fifth embodiment. Also, the pitch between the photodetecting regions 9 can be narrowed, whereby the photodetector array PDA2 is easily made smaller. In the photodetector arrays PDA1 and PDA2, the above-mentioned film 60 may be provided instead of the glass substrate 1 and film 10. Lens parts (e.g., the above-mentioned lens parts 121a and 131a) may be formed so as to correspond to the respective photodetecting regions 9. An optical interconnection system using the above-mentioned semiconductor photodetector device (or photodetector array) will now be explained with reference to FIG. 41. FIG. 41 is a schematic view showing the structure of the optical interconnection system. The optical interconnection system 151 is a system for transmitting optical signals between a plurality of modules (e.g., CPUs, IC chips, and memories) M1 and M2, and includes a semiconductor light-emitting device 153, a driving circuit 155, an optical waveguide substrate 157, a semiconductor photodetector device PD1, an amplifying circuit 159, and the like. A vertical cavity surface emitting laser (VCSEL) of back-illuminated type can be used as the semiconductor light-emitting device 153. The module M1 is electrically connected to the semiconductor light-emitting device 103 through bump electrodes. The driving circuit 155 is electrically connected to the semiconductor light-emitting device 103 through bump electrodes. The semiconductor photodetector device PD1 is electrically connected to the amplifying circuit 159 through bump electrodes 41. The amplifying circuit 159 is electrically connected to the module M2 through bump electrodes. An electric signal outputted from the module M1 is sent to the driving circuit 155, and is converted into an optical signal by the semiconductor light-emitting device 153. The optical signal from the semiconductor light-emitting device 153 passes through an optical waveguide 157a on the optical waveguide substrate 157, so as to be made incident on the semiconductor photodetector device PD1. The optical signal is converted by the semiconductor photodetector device PD1 into an electric signal, which is then sent to the amplifying circuit 109 and amplified therein. The amplified electric signal is sent to the module M2. Thus, the electric signal outputted from the module M1 is transmitted to the module M2. Any of the semiconductor photodetector devices PD2 to PD8 or semiconductor photodetector device arrays PDA1 and PDA2 may be used in place of the semiconductor photodetector device PD1. When the semiconductor photodetector device array PDA1, PDA2 is used, the semiconductor light-emitting device 153, driving circuit 155, optical waveguide substrate 157, and amplifying circuit 159 are also arranged so as to form an array. The present invention is explained in detail with reference to its embodiments in the foregoing. However, the present invention is not limited to the above-mentioned embodiments. The present invention can be modified in various ways within a scope not deviating from its gist. For example, thicknesses, materials, and the like of the semiconductor substrate 51, high-concentration carrier layer 3 (3a, 3b), light-absorbing layer 5 (5a, 5b), cap layer (7a, 7b), and the like are not limited to those mentioned above. Specifically, Si, InP, InGaAs, InSb, or InAsSb may be used as a material of the semiconductor substrate 51 instead of GaAs mentioned above. From the invention thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the following claims. INDUSTRIAL APPLICABILITY The present invention can provide a semiconductor photodetector device which can be made smaller while having a sufficient mechanical strength, and a method of manufacturing the same. Also, the present invention allows the semiconductor photodetector device to be mounted easily.	H	67H01	185H01L	311	01
11952755	US20080173905A1-20080724	SOLID STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME	ACCEPTED	20080709	20080724	[]	H01L27148	["H01L27148", "H01L3118"]	7714401	20071207	20100511	257	431000	59162.0	LAM	CATHY	[{"inventor_name_last": "NAGASE", "inventor_name_first": "Masanori", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Matsuda", "inventor_name_first": "Jiro", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Sasamoto", "inventor_name_first": "Tsuneo", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Hayakawa", "inventor_name_first": "Toshiaki", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}]	A solid state imaging device comprises: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and a gate electrode that transfers the signal charge from the photoelectric converting portion to the charge transfer path, wherein the gate electrode comprises polysilicon having a different conductive type from that of a semiconductor region forming a charge storing portion of the charge transfer path.	1. A solid state imaging device comprising: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and a gate electrode that transfers the signal charge from the photoelectric converting portion to the charge transfer path, wherein the gate electrode comprises polysilicon having a different conductive type from that of a semiconductor region forming a charge storing portion of the charge transfer path. 2. The solid state imaging device according to claim 1, wherein the semiconductor region forming the charge storing portion of the charge transfer path has an N conductive type, and the gate electrode comprises polysilicon having a P conductive type. 3. The solid state imaging device according to claim 2, further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; and a horizontal charge transfer path, formed on a downstream side of the vertical charge transfer path, that transfers the signal charge received through the vertical charge transfer path in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. 4. The solid state imaging device according to claim 2, further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; a line memory, formed on a downstream side of the vertical charge transfer path, that executes to hold and transfer the signal charge received from the vertical charge transfer path; and a horizontal charge transfer path, formed on a downstream side of the line memory, that transfers the signal charge received through the line memory in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths, the line memory and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. 5. The solid state imaging device according to claim 3, wherein the photoelectric converting portions and the vertical charge transfer paths form a plurality of columns, in which each of the columns comprises: a set of ones of the photoelectric converting portions: and one of the vertical charge transfer paths adjacent to the set of ones of the photoelectric converting portions, a first one of the columns comprises: a set of first ones of the photoelectric converting portions; and first one of the vertical charge transfer paths, a second one of the columns comprises: a set of second ones of the photoelectric converting portions; and second one of the vertical charge transfer paths, the first and second ones of the columns are adjacent to each other, a device isolating region is formed between the set of first ones of the photoelectric converting portions and the second one of the vertical charge transfer paths, and the charge transfer electrode controls signal charge transfer of the second one of the vertical charge transfer paths and is formed to be protruded to an intermediate position of the device isolating region from a position of the second one of the vertical charge transfer paths toward the set of first ones of the photoelectric converting portions which is adjacent thereto. 6. The solid state imaging device according to claim 4, wherein the photoelectric converting portions and the vertical charge transfer paths form a plurality of columns, in which each of the columns comprises: a set of ones of the photoelectric converting portions: and one of the vertical charge transfer paths adjacent to the set of ones of the photoelectric converting portions, a first one of the columns comprises: a set of first ones of the photoelectric converting portions; and first one of the vertical charge transfer paths, a second one of the columns comprises: a set of second ones of the photoelectric converting portions; and second one of the vertical charge transfer paths, the first and second ones of the columns are adjacent to each other, a device isolating region is formed between the set of first ones of the photoelectric converting portions and the second one of the vertical charge transfer paths, and the charge transfer electrode controls signal charge transfer of the second one of the vertical charge transfer paths and is formed to be protruded to an intermediate position of the device isolating region from a position of the second one of the vertical charge transfer paths toward the set of first ones of the photoelectric converting portions which is adjacent thereto. 7. A method of manufacturing the solid state imaging device according to claim 1, the method comprising: forming a first conductive type layer for forming the charge storing portion of the charge transfer path on the semiconductor substrate; and forming a gate electrode having a second conductive type which is different from the first conductive type layer on the first conductive type layer through an insulating layer.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a solid state imaging device and a method of manufacturing the solid state imaging device. 2. Description of the Related Art Referring to a solid state imaging device to be used in a digital camera, particularly, a solid state imaging device using a CCD (Charge Coupled Devices), it is necessary to suppress the generation of a smear to be a peculiar noise. In the case in which an object includes a light or sun having a high luminance, the smear easily appears. Actually, the noise seems to be whitish like a stripe or a band in upper and lower parts of a portion having a high luminance in an image which is picked up. It is supposed that the smear appears by a mixture of a charge generated in a pixel portion having a high luminance in an imaging portion provided on the solid state imaging device into charges of other pixels which have been subjected to a photoelectric conversion and are being transferred. For a specific mechanism to generate the smear, four causes shown in (1) to (4) of FIG. 14 can be supposed. In other words, the smear is generated by at least one of the four causes in the following (1) to (4). (1) A photoelectric conversion in a peripheral portion of a photodiode (PD): A light which is incident from an opening of a photodiode is not restricted to a component having a perpendicular incident angle to a surface. Moreover, the light has a property of a wave. For this reason, a light transmitted through the opening spreads and a photoelectric conversion is also carried out in a gate region provided on the periphery of the photodiode so that a charge corresponding to a noise is generated and mixed into a vertical charge transfer portion (VCCD). (2) A diffusion current in a P-type region of an embedded photodiode: an electron generated in a P + region is diffused over a surface of the embedded photodiode and is mixed into the vertical charge transfer portion (VCCD) in an adjacent column. (3) A reflection and diffraction of a light incident from an opening portion of a shielding film (W or Al): an incident light is reflected or scattered at a boundary having a different refractive index, for example, a surface of a silicon substrate in an edge of the opening of the photodiode, and a charge is generated by the influence of the light and is mixed into the vertical charge transfer portion (VCCD). (4) A transmission of the light through the shielding film (Al): If the shielding film (W or Al) which shields the vertical charge transfer portion (VCCD) has a defect, a light leaking out of the defect is incident on the vertical charge transfer portion to generate a charge so that a smear is generated. In a recent solid state imaging device, however, the shielding is sufficiently carried out in many cases. For the actual cause of the smear, a diffusing component of a carrier subjected to the photoelectric conversion in (2) is dominant. A current solid state imaging device of a CCD type is constituted by using an NMOS process as disclosed in JP-A-2005-209714, for example. More specifically, an electron having a high mobility is used as a carrier in the NMOS process. Therefore, a high speed operation can be carried out and the NMOS process is suitable for a device performance in the case in which a solid state imaging device is manufactured. In the NMOS process, each circuit element is basically constituted by using an NMOS transistor having a structure shown in FIG. 15A . In FIG. 15A , an insulating layer 302 is formed on a surface of a substrate (a base material) 301 constituted by a P-type semiconductor (silicon), and a gate electrode 303 is formed on the insulating layer 302 . Moreover, a source region 304 and a drain region 305 are constituted by an N-type semiconductor (silicon), respectively. Furthermore, in the example, N-type polysilicon (N-Poly) to be a general material is used as the gate electrode 303 . In other words, when a positive voltage is applied to the gate electrode 303 by a capacitor formed between the substrate 301 and the gate electrode 303 , an electron is pulled toward a boundary surface between the substrate 301 and the insulating layer 302 so that an inverting layer (N type) is formed between the source region 304 and the drain region 305 . A region (channel) having a high conductivity is formed between the source region 304 and the drain region 305 by the inverting layer, and the electron to be the carrier is moved therebetween. The movement of the electron can be controlled by the voltage to be applied to the gate electrode 303 . Referring to the NMOS transistor, it is necessary to employ a surface channel structure in order to reduce an interference (a short channel effect) generated when a distance between the source and the drain is short (2 μm or less). In the case in which it is necessary to reduce a threshold voltage, moreover, an electric potential distribution shown in FIG. 15B is generally formed by using N-type polysilicon as the gate electrode 303 in such a manner that a slight depletion state is generated even if the voltage to be applied to the gate electrode 303 is 0V, for example. The related-art solid state imaging device of a CCD type using the NMOS process is constituted as shown in FIG. 16 . FIG. 16 shows a sectional structure of an imaging cell corresponding to one pixel and a peripheral portion thereof. More specifically, in the imaging cell for generating signal charges corresponding to respective pixels, an N-type semiconductor region 402 provided in a P-type semiconductor region 401 constitutes a photodiode (PD). A P + region 403 is formed on the N-type semiconductor region 402 . Moreover, an N-type semiconductor region 404 for forming a vertical charge transfer portion (VCCD) to transfer the signal charge in a vertical direction is disposed on a side of the N-type semiconductor region 402 . In order to transfer, to the vertical charge transfer portion, the signal charge generated and stored by the N-type semiconductor region 402 to be the photodiode, a gate electrode 406 is provided above the N-type semiconductor region 404 . The gate electrode 406 and the N-type semiconductor region 404 are isolated from each other through an insulating layer 405 . The gate electrode 406 is constituted by using N-type polysilicon (N-Poly) in the same manner as in a general NMOS transistor. A two-dimensional solid state imaging device includes a large number of imaging cells which are arranged at a regular interval in directions of a row and a column. Therefore, another imaging cell is disposed in an adjacent position to one imaging cell. In the example shown in FIG. 16 , an N-type semiconductor region 404 ( 1 ) on a right side constitutes a vertical charge transfer portion in a column to which the imaging cell belongs, and an N-type semiconductor region 404 ( 2 ) on a left side constitutes a vertical charge transfer portion belonging to another column which is adjacent to the imaging cell. Moreover, a gate electrode 406 ( 1 ) is provided to transfer the signal charge from a photodiode of the imaging cell to the N-type semiconductor region 404 ( 1 ) to be the vertical charge transfer portion in the column to which the imaging cell belongs, and a gate electrode 406 ( 2 ) is provided to transfer the signal charge from a photodiode of the imaging cell belonging to the adjacent column to the N-type semiconductor region 404 ( 2 ) of the column to which the imaging cell belongs. Moreover, the imaging cell and the imaging cell in the adjacent column are isolated from each other thorough the P + region 403 . By the influence of a diffusion current in the P-type region ( 403 ) of the embedded photodiode, however, a part of the signal charges generated in the photodiode of the imaging cell are mixed into the vertical charge transfer portion ( 404 ( 2 )) belonging to the imaging cells in other adjacent columns in some cases. Consequently, the smear is caused. In other words, the signal charge leaks into the other adjacent columns through a path of ( 2 ) shown in FIG. 14 . In order to reduce the cause of the smear, in the related art, a surface shielding layer (corresponding to the P + region 403 in FIG. 16 ) of the embedded photodiode is mainly shallowed as a countermeasure. When the surface shielding layer is excessively shallowed, however, it is impossible to obtain a structure of an embedded photodiode which is an original object. For this reason, there is a problem in that an interface generating current to cause a dark current or a white flaw is increased. Accordingly, the actual shallowness of the surface shielding layer is to be determined by a trade-off of the smear and the interface generating current. In the related-art solid imaging device, a surface shielding layer is shallowed as a countermeasure for decreasing diffusing components of a carrier generated by a photoelectric conversion of a photodiode. Therefore, restrictions are imposed due to an increase in the interface generating current. Therefore, it is hard to effectively suppress a smear. When the photodiode is exposed, moreover, the smear is generated. At this time, either a medium potential (VM) or a low potential (VL) is applied to a gate electrode for controlling an electric potential between the photodiode and the vertical charge transfer portion. When the medium potential (VM) is applied to the gate electrode so that the electric potential of the vertical charge transfer portion is reduced, the smear is generated. By applying a negative bias as the medium potential (VM), accordingly, it is possible to form a potential barrier on an entrance of the vertical charge transfer portion. Therefore, it is possible to prevent the diffusing component of the carrier from flowing into the other adjacent columns, thereby suppressing the generation of the smear. In the case of the solid state imaging device to be particularly used in a household product, however, it is necessary to reduce a consumed power and to decrease the number of power supplies. Under the actual circumstances, therefore, a ground potential (GND) is to be applied as the medium potential (VM) to the gate electrode. For this reason, the negative bias cannot be applied as the medium potential (VM) in the related-art solid state imaging device so that the potential barrier cannot be formed on the entrance of the vertical charge transfer portion.	<SOH> SUMMARY OF THE INVENTION <EOH>It is an object of the invention to provide a solid state imaging device and a method of manufacturing the solid state imaging device which can effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage to a gate electrode. The object according to the invention can be achieved by the following structure. (1) A solid state imaging device comprising: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and a gate electrode that transfers the signal charge from the photoelectric converting portion to the charge transfer path, wherein the gate electrode comprises polysilicon having a different conductive type from that of a semiconductor region forming a charge storing portion of the charge transfer path. According to the solid state imaging device, it is possible to effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negative bias) from an outside of the gate electrode. For example, in the case in which a solid state imaging device using an NMOS process is constituted, a semiconductor region forming the charge storing portion of the charge transfer path is formed by a semiconductor region having an N conductive type (which implies a doping polarity). In that case, therefore, the gate electrode is formed of polysilicon having the N conductive type. On the contrary, in the case in which the solid state imaging device using a PMOS process is constituted, the semiconductor region forming the charge storing portion of the charge transfer path is formed by a semiconductor region having a P conductive type. In that case, therefore, the gate electrode is formed of polysilicon having the P conductive type. In other words, while the gate electrode is formed of the N-type polysilicon in the related-art solid state imaging device using the NMOS process, the gate electrode is formed of the P-type polysilicon having a different conductive type in the invention. A work function has a great difference between the N-type polysilicon and the P-type polysilicon which can be utilized as a material for the gate electrode. For example, the work function has almost a difference in an amount corresponding to a band gap difference (approximately 1.1 V) between N + type polysilicon and P + type polysilicon, for example. The “work function” represents the lowest energy which is required for an electron to get out of a metal. In other words, if the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, an electric potential distribution between the photoelectric converting portion and the charge transfer path is varied depending on a difference between their work functions so that a movement of a carrier generated by the photodiode is changed greatly. More specifically, when the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, the same result as that in an application of a potential of (VM-1.1(V)) is obtained effectively. Even if a negative bias is not applied as the medium potential (VM), therefore, it is possible to obtain the same result as that in the application of the negative bias. The related-art general solid state imaging device is constituted by using an NMOS process, and the N-type polysilicon is used as the gate electrode in the same manner as in a general device using the NMOS process. More specifically, it is also possible to produce an advantage that a high speed operation can be carried out in a fine structure having a line width of approximately 0.25 μm, for example, by using the h-type polysilicon as a material for the gate electrode. For this reason, the N-type polysilicon is generally used as the gate electrode in the solid state imaging device constituted by using the related-art NMOS process. However, it is also possible to constitute the solid state imaging device by using the P-type polysilicon. If the advantage is produced, the P-type polysilicon can be utilized properly. (2) The solid state imaging device according to (1) wherein the semiconductor region forming the charge storing portion of the charge transfer path has an N conductive type, and the gate electrode comprises polysilicon having a P conductive type. According to the solid state imaging device, it is assumed that the solid state imaging device is constituted in the NMOS process. Therefore, the charge storing portion of the charge transfer path is formed by the semiconductor region having the N-type conductive type and the gate electrode is formed of polysilicon having the P-type conductive type. In the same manner as in (1), accordingly, the same result as that in the effective application of the potential of (VM-1.1(V)) as the medium potential (VM) is obtained and the same result as that in the application of a negative bias is obtained even if the negative bias is not applied as the middle potential (VM) as compared with the case in which the N-type polysilicon is used for the gate electrode. Therefore, it is possible to effectively reduce the smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negative bias) from an outside to the gate electrode. (3) The solid state imaging device according to (2) further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; and a horizontal charge transfer path, formed on a downstream side of the vertical charge transfer path, that transfers the signal charge received through the vertical charge transfer path in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. According to the solid state imaging device, the charge transfer electrode for controlling the transfer of the signal charge through the vertical charge transfer path or the horizontal charge transfer path is also formed by the P-type polysilicon in addition to a gate electrode. More specifically, the charge transfer electrode of the vertical charge transfer path or the horizontal charge transfer path is formed by using the same material as the gate electrode. Therefore, it is possible to prevent a manufacturing process from being complicated. (4) The solid state imaging device according to (2) further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; a line memory, formed on a downstream side of the vertical charge transfer path, that executes to hold and transfer the signal charge received from the vertical charge transfer path; and a horizontal charge transfer path, formed on a downstream side of the line memory, that transfers the signal charge received through the line memory in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths, the line memory and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. According to the solid state imaging device, the charge transfer electrode for controlling the transfer of the signal charge through the vertical charge transfer path, the line memory or the horizontal charge transfer path is also formed by the P-type polysilicon in addition to a gate electrode. More specifically, the charge transfer electrode of the vertical charge transfer path, the line memory or the horizontal charge transfer path is formed by using the same material as the gate electrode. Therefore, it is possible to prevent a manufacturing process from being complicated. (5) The solid state imaging device according to (3) or (4), wherein the photoelectric converting portions and the vertical charge transfer paths form a plurality of columns, in which each of the columns comprises: a set of ones of the photoelectric converting portions: and one of the vertical charge transfer paths adjacent to the set of ones of the photoelectric converting portions, a first one of the columns comprises: a set of first ones of the photoelectric converting portions; and first one of the vertical charge transfer paths, a second one of the columns comprises: a set of second ones of the photoelectric converting portions; and second one of the vertical charge transfer paths, the first and second ones of the columns are adjacent to each other, a device isolating region is formed between the set of first ones of the photoelectric converting portions and the second one of the vertical charge transfer paths, and the charge transfer electrode controls signal charge transfer of the second one of the vertical charge transfer paths and is formed to be protruded to an intermediate position of the device isolating region from a position of the second one of the vertical charge transfer paths toward the set of first ones of the photoelectric converting portions which is adjacent thereto. According to the solid state imaging device, it is possible to further enhance the effect of preventing the carrier generated by the photodiode (the first photoelectric converting portion) in each pixel position from leaking as a diffusion current into the vertical charge transfer portion (the second vertical charge transfer path) in another adjacent column. With a general structure, a charge transfer electrode for controlling a signal charge transfer of each vertical charge transfer path is constituted in such a dimension and shape that a width and a position are equal to those of the semiconductor region (channel) of the vertical charge transfer path. In the solid state imaging device in (5), however, the charge transfer electrode for controlling the signal charge transfer of the second vertical charge transfer path is formed to be protruded to the intermediate position of the device isolating region from the position of the second vertical charge transfer path toward the first photoelectric converting portion which is adjacent thereto. Consequently, it is possible to increase the effect of preventing the diffusion current from flowing from the first photoelectric converting portion to the second vertical charge transfer path in the adjacent column. Thus, it is possible to enhance the effect of suppressing a smear. When the charge transfer electrode in the adjacent column is caused to excessively approach the first photoelectric converting portion, conversely, there is a higher possibility that the signal charge is read from the first photoelectric converting portion to the adjacent column. For this reason, it is necessary to hold an amount of the protrusion of the charge transfer electrode up to the intermediate position of the device isolating region. (6) A method of manufacturing the solid state imaging device according to any of (1) to (5), the method comprising: forming a first conductive type layer for forming the charge storing portion of the charge transfer path on the semiconductor substrate; and forming a gate electrode having a second conductive type which is different from the first conductive type layer on the first conductive type layer through an insulating layer. According to the method of manufacturing the solid state imaging device, it is possible to manufacture any of the solid state imaging devices in (1) to (5).	BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state imaging device and a method of manufacturing the solid state imaging device. 2. Description of the Related Art Referring to a solid state imaging device to be used in a digital camera, particularly, a solid state imaging device using a CCD (Charge Coupled Devices), it is necessary to suppress the generation of a smear to be a peculiar noise. In the case in which an object includes a light or sun having a high luminance, the smear easily appears. Actually, the noise seems to be whitish like a stripe or a band in upper and lower parts of a portion having a high luminance in an image which is picked up. It is supposed that the smear appears by a mixture of a charge generated in a pixel portion having a high luminance in an imaging portion provided on the solid state imaging device into charges of other pixels which have been subjected to a photoelectric conversion and are being transferred. For a specific mechanism to generate the smear, four causes shown in (1) to (4) of FIG. 14 can be supposed. In other words, the smear is generated by at least one of the four causes in the following (1) to (4). (1) A photoelectric conversion in a peripheral portion of a photodiode (PD): A light which is incident from an opening of a photodiode is not restricted to a component having a perpendicular incident angle to a surface. Moreover, the light has a property of a wave. For this reason, a light transmitted through the opening spreads and a photoelectric conversion is also carried out in a gate region provided on the periphery of the photodiode so that a charge corresponding to a noise is generated and mixed into a vertical charge transfer portion (VCCD). (2) A diffusion current in a P-type region of an embedded photodiode: an electron generated in a P+ region is diffused over a surface of the embedded photodiode and is mixed into the vertical charge transfer portion (VCCD) in an adjacent column. (3) A reflection and diffraction of a light incident from an opening portion of a shielding film (W or Al): an incident light is reflected or scattered at a boundary having a different refractive index, for example, a surface of a silicon substrate in an edge of the opening of the photodiode, and a charge is generated by the influence of the light and is mixed into the vertical charge transfer portion (VCCD). (4) A transmission of the light through the shielding film (Al): If the shielding film (W or Al) which shields the vertical charge transfer portion (VCCD) has a defect, a light leaking out of the defect is incident on the vertical charge transfer portion to generate a charge so that a smear is generated. In a recent solid state imaging device, however, the shielding is sufficiently carried out in many cases. For the actual cause of the smear, a diffusing component of a carrier subjected to the photoelectric conversion in (2) is dominant. A current solid state imaging device of a CCD type is constituted by using an NMOS process as disclosed in JP-A-2005-209714, for example. More specifically, an electron having a high mobility is used as a carrier in the NMOS process. Therefore, a high speed operation can be carried out and the NMOS process is suitable for a device performance in the case in which a solid state imaging device is manufactured. In the NMOS process, each circuit element is basically constituted by using an NMOS transistor having a structure shown in FIG. 15A. In FIG. 15A, an insulating layer 302 is formed on a surface of a substrate (a base material) 301 constituted by a P-type semiconductor (silicon), and a gate electrode 303 is formed on the insulating layer 302. Moreover, a source region 304 and a drain region 305 are constituted by an N-type semiconductor (silicon), respectively. Furthermore, in the example, N-type polysilicon (N-Poly) to be a general material is used as the gate electrode 303. In other words, when a positive voltage is applied to the gate electrode 303 by a capacitor formed between the substrate 301 and the gate electrode 303, an electron is pulled toward a boundary surface between the substrate 301 and the insulating layer 302 so that an inverting layer (N type) is formed between the source region 304 and the drain region 305. A region (channel) having a high conductivity is formed between the source region 304 and the drain region 305 by the inverting layer, and the electron to be the carrier is moved therebetween. The movement of the electron can be controlled by the voltage to be applied to the gate electrode 303. Referring to the NMOS transistor, it is necessary to employ a surface channel structure in order to reduce an interference (a short channel effect) generated when a distance between the source and the drain is short (2 μm or less). In the case in which it is necessary to reduce a threshold voltage, moreover, an electric potential distribution shown in FIG. 15B is generally formed by using N-type polysilicon as the gate electrode 303 in such a manner that a slight depletion state is generated even if the voltage to be applied to the gate electrode 303 is 0V, for example. The related-art solid state imaging device of a CCD type using the NMOS process is constituted as shown in FIG. 16. FIG. 16 shows a sectional structure of an imaging cell corresponding to one pixel and a peripheral portion thereof. More specifically, in the imaging cell for generating signal charges corresponding to respective pixels, an N-type semiconductor region 402 provided in a P-type semiconductor region 401 constitutes a photodiode (PD). A P+ region 403 is formed on the N-type semiconductor region 402. Moreover, an N-type semiconductor region 404 for forming a vertical charge transfer portion (VCCD) to transfer the signal charge in a vertical direction is disposed on a side of the N-type semiconductor region 402. In order to transfer, to the vertical charge transfer portion, the signal charge generated and stored by the N-type semiconductor region 402 to be the photodiode, a gate electrode 406 is provided above the N-type semiconductor region 404. The gate electrode 406 and the N-type semiconductor region 404 are isolated from each other through an insulating layer 405. The gate electrode 406 is constituted by using N-type polysilicon (N-Poly) in the same manner as in a general NMOS transistor. A two-dimensional solid state imaging device includes a large number of imaging cells which are arranged at a regular interval in directions of a row and a column. Therefore, another imaging cell is disposed in an adjacent position to one imaging cell. In the example shown in FIG. 16, an N-type semiconductor region 404(1) on a right side constitutes a vertical charge transfer portion in a column to which the imaging cell belongs, and an N-type semiconductor region 404(2) on a left side constitutes a vertical charge transfer portion belonging to another column which is adjacent to the imaging cell. Moreover, a gate electrode 406(1) is provided to transfer the signal charge from a photodiode of the imaging cell to the N-type semiconductor region 404(1) to be the vertical charge transfer portion in the column to which the imaging cell belongs, and a gate electrode 406(2) is provided to transfer the signal charge from a photodiode of the imaging cell belonging to the adjacent column to the N-type semiconductor region 404(2) of the column to which the imaging cell belongs. Moreover, the imaging cell and the imaging cell in the adjacent column are isolated from each other thorough the P+ region 403. By the influence of a diffusion current in the P-type region (403) of the embedded photodiode, however, a part of the signal charges generated in the photodiode of the imaging cell are mixed into the vertical charge transfer portion (404(2)) belonging to the imaging cells in other adjacent columns in some cases. Consequently, the smear is caused. In other words, the signal charge leaks into the other adjacent columns through a path of (2) shown in FIG. 14. In order to reduce the cause of the smear, in the related art, a surface shielding layer (corresponding to the P+ region 403 in FIG. 16) of the embedded photodiode is mainly shallowed as a countermeasure. When the surface shielding layer is excessively shallowed, however, it is impossible to obtain a structure of an embedded photodiode which is an original object. For this reason, there is a problem in that an interface generating current to cause a dark current or a white flaw is increased. Accordingly, the actual shallowness of the surface shielding layer is to be determined by a trade-off of the smear and the interface generating current. In the related-art solid imaging device, a surface shielding layer is shallowed as a countermeasure for decreasing diffusing components of a carrier generated by a photoelectric conversion of a photodiode. Therefore, restrictions are imposed due to an increase in the interface generating current. Therefore, it is hard to effectively suppress a smear. When the photodiode is exposed, moreover, the smear is generated. At this time, either a medium potential (VM) or a low potential (VL) is applied to a gate electrode for controlling an electric potential between the photodiode and the vertical charge transfer portion. When the medium potential (VM) is applied to the gate electrode so that the electric potential of the vertical charge transfer portion is reduced, the smear is generated. By applying a negative bias as the medium potential (VM), accordingly, it is possible to form a potential barrier on an entrance of the vertical charge transfer portion. Therefore, it is possible to prevent the diffusing component of the carrier from flowing into the other adjacent columns, thereby suppressing the generation of the smear. In the case of the solid state imaging device to be particularly used in a household product, however, it is necessary to reduce a consumed power and to decrease the number of power supplies. Under the actual circumstances, therefore, a ground potential (GND) is to be applied as the medium potential (VM) to the gate electrode. For this reason, the negative bias cannot be applied as the medium potential (VM) in the related-art solid state imaging device so that the potential barrier cannot be formed on the entrance of the vertical charge transfer portion. SUMMARY OF THE INVENTION It is an object of the invention to provide a solid state imaging device and a method of manufacturing the solid state imaging device which can effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage to a gate electrode. The object according to the invention can be achieved by the following structure. (1) A solid state imaging device comprising: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charge in a predetermined direction; and a gate electrode that transfers the signal charge from the photoelectric converting portion to the charge transfer path, wherein the gate electrode comprises polysilicon having a different conductive type from that of a semiconductor region forming a charge storing portion of the charge transfer path. According to the solid state imaging device, it is possible to effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negative bias) from an outside of the gate electrode. For example, in the case in which a solid state imaging device using an NMOS process is constituted, a semiconductor region forming the charge storing portion of the charge transfer path is formed by a semiconductor region having an N conductive type (which implies a doping polarity). In that case, therefore, the gate electrode is formed of polysilicon having the N conductive type. On the contrary, in the case in which the solid state imaging device using a PMOS process is constituted, the semiconductor region forming the charge storing portion of the charge transfer path is formed by a semiconductor region having a P conductive type. In that case, therefore, the gate electrode is formed of polysilicon having the P conductive type. In other words, while the gate electrode is formed of the N-type polysilicon in the related-art solid state imaging device using the NMOS process, the gate electrode is formed of the P-type polysilicon having a different conductive type in the invention. A work function has a great difference between the N-type polysilicon and the P-type polysilicon which can be utilized as a material for the gate electrode. For example, the work function has almost a difference in an amount corresponding to a band gap difference (approximately 1.1 V) between N+ type polysilicon and P+ type polysilicon, for example. The “work function” represents the lowest energy which is required for an electron to get out of a metal. In other words, if the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, an electric potential distribution between the photoelectric converting portion and the charge transfer path is varied depending on a difference between their work functions so that a movement of a carrier generated by the photodiode is changed greatly. More specifically, when the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, the same result as that in an application of a potential of (VM-1.1(V)) is obtained effectively. Even if a negative bias is not applied as the medium potential (VM), therefore, it is possible to obtain the same result as that in the application of the negative bias. The related-art general solid state imaging device is constituted by using an NMOS process, and the N-type polysilicon is used as the gate electrode in the same manner as in a general device using the NMOS process. More specifically, it is also possible to produce an advantage that a high speed operation can be carried out in a fine structure having a line width of approximately 0.25 μm, for example, by using the h-type polysilicon as a material for the gate electrode. For this reason, the N-type polysilicon is generally used as the gate electrode in the solid state imaging device constituted by using the related-art NMOS process. However, it is also possible to constitute the solid state imaging device by using the P-type polysilicon. If the advantage is produced, the P-type polysilicon can be utilized properly. (2) The solid state imaging device according to (1) wherein the semiconductor region forming the charge storing portion of the charge transfer path has an N conductive type, and the gate electrode comprises polysilicon having a P conductive type. According to the solid state imaging device, it is assumed that the solid state imaging device is constituted in the NMOS process. Therefore, the charge storing portion of the charge transfer path is formed by the semiconductor region having the N-type conductive type and the gate electrode is formed of polysilicon having the P-type conductive type. In the same manner as in (1), accordingly, the same result as that in the effective application of the potential of (VM-1.1(V)) as the medium potential (VM) is obtained and the same result as that in the application of a negative bias is obtained even if the negative bias is not applied as the middle potential (VM) as compared with the case in which the N-type polysilicon is used for the gate electrode. Therefore, it is possible to effectively reduce the smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negative bias) from an outside to the gate electrode. (3) The solid state imaging device according to (2) further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; and a horizontal charge transfer path, formed on a downstream side of the vertical charge transfer path, that transfers the signal charge received through the vertical charge transfer path in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. According to the solid state imaging device, the charge transfer electrode for controlling the transfer of the signal charge through the vertical charge transfer path or the horizontal charge transfer path is also formed by the P-type polysilicon in addition to a gate electrode. More specifically, the charge transfer electrode of the vertical charge transfer path or the horizontal charge transfer path is formed by using the same material as the gate electrode. Therefore, it is possible to prevent a manufacturing process from being complicated. (4) The solid state imaging device according to (2) further comprising, as the charge transfer path: a plurality of vertical charge transfer paths that transfers a signal charge received from the photoelectric converting portion in a vertical direction; a line memory, formed on a downstream side of the vertical charge transfer path, that executes to hold and transfer the signal charge received from the vertical charge transfer path; and a horizontal charge transfer path, formed on a downstream side of the line memory, that transfers the signal charge received through the line memory in a horizontal direction, wherein the solid state imaging device further comprises a charge transfer electrode that controls transfer of the signal charge for at least one of the vertical charge transfer paths, the line memory and the horizontal charge transfer path, the charge transfer electrode comprising polysilicon having a P conductive type. According to the solid state imaging device, the charge transfer electrode for controlling the transfer of the signal charge through the vertical charge transfer path, the line memory or the horizontal charge transfer path is also formed by the P-type polysilicon in addition to a gate electrode. More specifically, the charge transfer electrode of the vertical charge transfer path, the line memory or the horizontal charge transfer path is formed by using the same material as the gate electrode. Therefore, it is possible to prevent a manufacturing process from being complicated. (5) The solid state imaging device according to (3) or (4), wherein the photoelectric converting portions and the vertical charge transfer paths form a plurality of columns, in which each of the columns comprises: a set of ones of the photoelectric converting portions: and one of the vertical charge transfer paths adjacent to the set of ones of the photoelectric converting portions, a first one of the columns comprises: a set of first ones of the photoelectric converting portions; and first one of the vertical charge transfer paths, a second one of the columns comprises: a set of second ones of the photoelectric converting portions; and second one of the vertical charge transfer paths, the first and second ones of the columns are adjacent to each other, a device isolating region is formed between the set of first ones of the photoelectric converting portions and the second one of the vertical charge transfer paths, and the charge transfer electrode controls signal charge transfer of the second one of the vertical charge transfer paths and is formed to be protruded to an intermediate position of the device isolating region from a position of the second one of the vertical charge transfer paths toward the set of first ones of the photoelectric converting portions which is adjacent thereto. According to the solid state imaging device, it is possible to further enhance the effect of preventing the carrier generated by the photodiode (the first photoelectric converting portion) in each pixel position from leaking as a diffusion current into the vertical charge transfer portion (the second vertical charge transfer path) in another adjacent column. With a general structure, a charge transfer electrode for controlling a signal charge transfer of each vertical charge transfer path is constituted in such a dimension and shape that a width and a position are equal to those of the semiconductor region (channel) of the vertical charge transfer path. In the solid state imaging device in (5), however, the charge transfer electrode for controlling the signal charge transfer of the second vertical charge transfer path is formed to be protruded to the intermediate position of the device isolating region from the position of the second vertical charge transfer path toward the first photoelectric converting portion which is adjacent thereto. Consequently, it is possible to increase the effect of preventing the diffusion current from flowing from the first photoelectric converting portion to the second vertical charge transfer path in the adjacent column. Thus, it is possible to enhance the effect of suppressing a smear. When the charge transfer electrode in the adjacent column is caused to excessively approach the first photoelectric converting portion, conversely, there is a higher possibility that the signal charge is read from the first photoelectric converting portion to the adjacent column. For this reason, it is necessary to hold an amount of the protrusion of the charge transfer electrode up to the intermediate position of the device isolating region. (6) A method of manufacturing the solid state imaging device according to any of (1) to (5), the method comprising: forming a first conductive type layer for forming the charge storing portion of the charge transfer path on the semiconductor substrate; and forming a gate electrode having a second conductive type which is different from the first conductive type layer on the first conductive type layer through an insulating layer. According to the method of manufacturing the solid state imaging device, it is possible to manufacture any of the solid state imaging devices in (1) to (5). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an imaging portion of a solid state imaging device according to the invention, FIG. 2 is a plan view showing an example of a structure of a main part in a solid state imaging device according to a first embodiment, FIG. 3 is an enlarged sectional view showing a structure of a section taken along a B1-B2 line in the solid state imaging device illustrated in FIG. 2, FIG. 4 is a sectional view showing a structure in the vicinity of an output terminal of the solid state imaging device illustrated in FIG. 2, FIG. 5 is an enlarged sectional view showing a sectional structure related to an imaging cell and a periphery thereof in the solid state imaging device illustrated in FIG. 2, FIGS. 6A and 6B are typical charts representing a result of a simulation related to the imaging cell and the periphery illustrated in FIG. 5, in which FIG. 6A is a chart showing a model of a structure and FIG. 6B is a chart showing an electric potential and a flow of a diffusion current, FIG. 7 is a graph representing a result of a simulation related to the imaging cell and the periphery illustrated in FIG. 5, FIGS. 8A to 8E is an explanatory view (No. 1) showing an example of a process for manufacturing the solid state imaging device, FIGS. 9A to 9E is an explanatory view (No. 2) showing an example of the process for manufacturing the solid state imaging device, FIG. 10 is an enlarged sectional view showing a sectional structure related to an imaging cell and a periphery thereof in a solid state imaging device according to a second embodiment, FIG. 11 is a plan view showing a structure of a solid state imaging device according to a third embodiment, FIG. 12 is a typical view showing an example of a structure of an electrode in the case of a two-layer polysilicon structure, FIG. 13 is a typical view showing an example of a structure of an electrode in the case of a polycide structure, FIG. 14 is a longitudinal sectional view showing a sectional structure related to an imaging cell and a periphery thereof in a solid state imaging device having a general structure and a smear generating mechanism, FIG. 15A is a longitudinal sectional view showing a structure of an NMOS transistor having a general structure and FIG. 15B is an explanatory diagram showing an electric potential distribution on a D1-D2 line, and FIG. 16 is a sectional view showing a structure of a solid state imaging device using an NMOS process with a general structure. DETAILED DESCRIPTION OF THE INVENTION First Embodiment A preferred embodiment of a solid state imaging device according to the invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing an imaging portion of the solid state imaging device according to the invention and FIG. 2 is an enlarged plan view showing a main part of the solid state imaging device illustrated in FIG. 1. FIG. 1 shows a structure of an A1-A2 section of the solid state imaging device illustrated in FIG. 2. The solid state imaging device shown in FIGS. 1 and 2 constitutes a two-dimensional CCD image sensor. More specifically, there is provided an imaging portion 110 in which a large number of imaging cells 120 are two-dimensionally disposed in a row direction (a direction of an arrow X) and a column direction (a direction of an arrow Y) over a plane. Each of the imaging cells 120 includes a photodiode (PD) constituted by a semiconductor and generates a signal charge corresponding to a light quantity determined by an intensity of a light which is incident on each light receiving surface and a length of an exposure time. In order to fetch a signal charge output from each of the large number of imaging cells 120 which are two-dimensionally disposed as a signal per frame in time series from an output terminal of the solid state imaging device, a plurality of vertical charge transfer portions (VCCDs) 130, a line memory 52, a horizontal charge transfer portion (HCCD) 54 and an output amplifier 55 are provided in the solid state imaging device. Each of the vertical charge transfer portions 130 is provided in an adjacent position to the imaging cell 120 and is extended in a longitudinal direction (the direction of the arrow Y), and receives signal charges from each of the imaging cells 120 corresponding to one column and then transfers the signal charges per column sequentially in the direction of the arrow Y. The line memory 52 is disposed on an output side of the vertical charge transfer portion 130 in each column. The signal charges corresponding to one row which are output from the respective vertical charge transfer portions 130 at the same time are temporarily stored on the line memory 52. The signal charges corresponding to one column which are stored on the line memory 52 are transferred from the line memory 52 toward the horizontal charge transfer portion 54. As a result, the signal charges corresponding to one row appear over the horizontal charge transfer portion 54. The horizontal charge transfer portion 54 sequentially transfers the signal charges corresponding to one row held by itself on a pixel unit in a horizontal direction (the direction of the arrow X). The signal charges appearing on an output of the horizontal charge transfer portion 54 in order is amplified by the output amplifier 55 and appears on an output terminal OUT. Control signals required for implementing the reading operation, that is, a vertical transfer control signal φV (usually, a signal having a plurality of phases), a transfer control signal φLM and a horizontal transfer control signal φH (usually a signal having a plurality of phases) are generated by a timing signal generating circuit (not shown) respectively, and are applied to each of the vertical charge transfer portions 130, the line memory 52 and the horizontal charge transfer portion 54 in the solid state imaging device respectively. In some cases, the line memory 52 is omitted from the structure. In the example shown in FIG. 2, moreover, a large number of imaging cells 120 are disposed to form a honeycomb-shaped pattern (a pattern obtained by shifting positions of the imaging cells to be arranged by a half pitch every row in the horizontal direction). Furthermore, color components to be detected are predetermined for each of the imaging cells 120 as shown in “G1”, “G2”, “B” and “R” in FIG. 2. More specifically, the imaging cells 120 for “G1” and “G2” detect a brightness having a green component, the imaging cells 120 for “B” detect a brightness having a blue component, and the imaging cells 120 for “R” detect a brightness having a red component. The detecting colors are set by spectral characteristics of an optical filter disposed on a front surface of a light receiving plane of the imaging cell 120. In the example shown in FIG. 2, four types of filter columns FC1, FC2, FC3 and FC4 are disposed through a division every column of the imaging cell 120. The optical filter has a so-called array obtained by inclining a Bayer pattern by 45 degrees. As shown in FIG. 2, the vertical charge transfer portion 130 is formed to take a meandering shape in an adjacent position to each of the columns of the imaging cells 120 every column. The vertical charge transfer portion 130 includes a vertical charge transfer channel 37 formed on a semiconductor substrate 35 and large numbers of first vertical transfer electrodes 41, second vertical transfer electrodes 43, first auxiliary transfer electrodes 45, second auxiliary transfer electrodes 46 and third auxiliary transfer electrodes 47 for a charge transfer which are disposed on the semiconductor substrate 35 through an electrical insulating film (not shown). More specifically, by applying a predetermined voltage to each of the electrodes 41, 43, 45, 46 and 47 to form a predetermined potential distribution over the vertical charge transfer channel 37 and sequentially switching the voltage to be applied to the electrode, it is possible to sequentially transfer a signal charge of each pixel in a target direction in the vertical charge transfer portion (VCCD) 130. The first vertical transfer electrodes 41 and the second vertical transfer electrodes 43 are formed one by one every row of the imaging cell 120. Each of the first vertical transfer electrodes 43 also functions as a reading gate for controlling a transfer of a signal charge from the imaging cell 120 to the vertical charge transfer channel 37 of the vertical charge transfer portion 130. Any of the vertical transfer control signals having four phases (which are also referred to as driving pulses) φV1, φV2, φV3 and φV4 is applied to each of the second vertical transfer electrodes 43 and the first vertical transfer electrodes 41 which are alternately arranged in the direction of the arrow Y depending on a positional relationship of the arrangement of the second vertical transfer electrodes 43 and the first vertical transfer electrodes 41 as shown in FIG. 2. Similarly, the vertical transfer control signal φV2 is applied to the first auxiliary transfer electrode 45, the vertical transfer control signal φV3 is applied to the second auxiliary transfer electrode 46, and the vertical transfer control signal φV4 is applied to the third auxiliary transfer electrode 47. As shown in FIG. 2, the line memory 52 is formed in an adjacent position (a downstream side with respect to the direction of the transfer of the signal charge) to a position of a final transfer stage of the vertical charge transfer portion 130 (the electrode 47 for controlling the signal charge on a lower side in FIG. 2). In order to control the transfer of the signal charge in the line memory 52, transfer control electrodes LM1 and LM2 are provided. The transfer control signal φLM is applied to the transfer control electrodes LM1 and LM2. In a section of one of the imaging cells 120 in the solid state imaging device, as shown in FIG. 1, a photodiode (PD) 103 constituted by an N-type region, the vertical charge transfer portion (VCCD) 130 formed by an N-type region, a charge reading region 104 and a channel stop region 105 are formed in an N-type silicon substrate (N-sub corresponding to the semiconductor substrate 35) 101 on which a P-type semiconductor layer 102 is formed. Moreover, a thin P-type region 106 is formed on a surface side of the photodiode 103. Agate electrode 107 is formed above the vertical charge transfer portion (VCCD) 130. The vertical charge transfer portion 130 and the gate electrode 107 are electrically isolated through an insulating layer which is not shown. A vertical charge transfer portion 130(1) shown in FIG. 1 belongs to the same column as the photodiode 103 and a vertical charge transfer portion 130(2) belongs to another adjacent column. In other words, a signal charge generated by a photoelectric conversion of the photodiode 103 shown in FIG. 1 is moved onto a channel of the vertical charge transfer portion 130(1) through the charge reading region 104 by an electric potential control depending on a voltage to be applied to the gate electrode 107 and is not moved to the vertical charge transfer portion 130(2) in an adjacent column. The photodiode 103 and the vertical charge transfer portion 130(2) in the adjacent column are isolated from each other through a channel stop region 105(2). There is a possibility that an electron generated in the P+ region (106) might be diffused over the surface of the embedded photodiode (103) and be mixed into the vertical charge transfer portion (VCCD) 130 (2) in the adjacent column. Consequently, a smear is caused. In order to suppress the influence of the diffusion current, in the solid state imaging device shown in FIG. 1, each of the gate electrodes 107 is formed by using P+-type polysilicon. In the solid state imaging device having the NMOS structure shown in FIGS. 1 and 2, N+-type polysilicon is usually utilized as a material. Herein, the P+-type polysilicon is particularly used. The reason is as follows. A work function has a great difference between the N-type polysilicon and the P-type polysilicon which can be utilized as a material for the gate electrode. For example, the work function has almost a difference in an amount corresponding to a band gap difference (approximately 1.1 V) between N+-type polysilicon and P+-type polysilicon, for example. The “work function” represents the lowest energy which is required for an electron to get out of a metal. In other words, if the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, an electric potential distribution between the photodiode 103 to be a photoelectric converting portion and the vertical charge transfer portion 130 is varied depending on a difference between their work functions so that a movement of a carrier generated by the photodiode is changed greatly. More specifically, when the material of the gate electrode is changed from the N-type polysilicon to the P-type polysilicon, the same result as that in an effective application of a potential of (VM-1.1(V)) is obtained. Even if a negative bias is not applied as the medium potential (VM) from an outside, therefore, it is possible to obtain the same result as that in the application of the negative bias. Therefore, it is possible to effectively reduce the smear while maintaining a characteristic of the embedded photodiode without applying a special voltage (a negative bias) from the outside to the gate electrode. As shown in FIG. 1, a surface side of the silicon substrate 101 is covered with a shielding film 111 except for a region of a light receiving surface of the photodiode 103 in order to prevent an extra light from being incident. Moreover, the filter columns FC2, FC3 and FC4 provided every column are disposed above the light receiving surface of the photodiode 103 so as to be opposed thereto, and a microlens 112 which is independent every cell is further disposed on their upper surfaces. A structure (a section taken along a B1-B2 line) in the vicinity of the line memory 52 and the horizontal charge transfer portion 54 in the solid state imaging device shown in FIG. 2 is illustrated in an enlarging state in FIG. 3. As shown in FIG. 3, the horizontal charge transfer portion 54 has one horizontal charge transfer channel 56 extended like a band in the direction of the arrow X and horizontal transfer electrodes Ha and Hb formed above the horizontal charge transfer channel 56. Large numbers of horizontal transfer electrodes Ha and Hb are provided and disposed alternately. The respective horizontal transfer electrodes Ha are formed to take a rectangular shape seen on a plane, and the respective horizontal transfer electrodes Hb have ends to take an inverted L shape seen on a plane. A pair of horizontal transfer electrodes Ha and Hb present in adjacent positions are electrically connected in common, and any of horizontal transfer control signals (which are also referred to as driving pulses) φH1, φH2, φH3 and φH4 having four phases is applied to the horizontal transfer electrodes Ha and Hb arranged in order depending on positions in which the horizontal transfer electrodes Ha and Hb are arranged. As shown in FIG. 3, the vertical charge transfer channel 37 for the vertical charge transfer portion 130, charge transfer channels 52a and 52b for the line memory 52 and the horizontal charge transfer channel 56 for the horizontal charge transfer portion 54 are formed in the N-type silicon substrate 101 on which the P-type semiconductor layer 102 is formed. The signal charge read from the photodiode 103 of the imaging cell 120 is transferred to the output portion OUT (see FIG. 2) through the vertical charge transfer channel 37, the charge transfer channels 52a and 52b, and the horizontal charge transfer channel 56 in order. Vertical transfer electrodes V2, V3 and V4 are provided above the vertical charge transfer channel 37 in order from an upstream to a downstream in a direction of the charge transfer (the direction of the arrow Y). The vertical transfer electrodes V1, V2, V3 and V4 shown in FIG. 3 correspond to the second vertical transfer electrode 43 on a most downstream, the first auxiliary transfer electrode 45, the second auxiliary transfer electrode 46 and the third auxiliary transfer electrode 47 in FIG. 2, respectively. The vertical charge transfer channel 37 of the vertical charge transfer portion 130 is formed as an N-type impurity region. Referring to the line memory 52, moreover, the charge transfer channel 52a is formed in an N-type impurity region and the charge transfer channel 52b is formed in an N-type impurity region. The horizontal charge transfer channel 56 of the horizontal charge transfer portion 54 is constituted by the N-type impurity region and the N−-type impurity region which are arranged alternately. Each of the horizontal transfer electrodes Ha is disposed in a position placed above the N-type impurity region and each of the horizontal transfer electrodes Hb is disposed in a position placed above the N-type impurity region. The horizontal transfer electrode Hb is provided around a region between the transfer control electrode LM2 of the line memory 52 and the horizontal transfer electrode Ha. The N-type impurity region is also provided below the wraparound portion. FIG. 4 is a sectional view showing a structure in the vicinity of an output terminal of the solid state imaging device illustrated in FIG. 2. As shown in FIG. 4, an N− region 126 and N+ regions 128 and 131 are formed on a surface of the P-type semiconductor layer 102. The N+ region 128 constitutes a floating diffusion layer. The output amplifier 55 is connected to the floating diffusion layer 128. A source follower using an MOCS transistor is utilized for the output amplifier 55. In FIG. 4, VFD represents a potential of the floating diffusion layer 128. Moreover, the N+ region 131 constitutes a reset drain (RD). The reset drain (RD) 131 is set to a reset drain potential VRD. In FIG. 4, 151 to 155 denote an electrode. A driving pulse φ1 is applied to the electrodes 151 and 153 and a driving pulse φ2 is applied to the electrode 152. Moreover, the electrode 154 denotes a horizontal transfer output gate, and a predetermined DC voltage VOC is always applied to the electrode 154. Furthermore, the electrode 155 constitutes a reset gate, and a reset gate clock φRG is applied to the reset gate 155. In FIG. 4, Q shown in a dotted line indicates a charge and an arrow shows a state of a movement (transfer) of the charge Q. Voltages to be applied as the signals (φ1, φ2, φRG, VFD) from the outside to the solid state imaging device are sequentially switched in accordance with a predetermined control procedure so that the charge Q is moved from a position placed under the electrode to which φ1 is applied to a position placed under the electrode to which φ2 is applied, and furthermore, a position placed under the electrode to which φ1 is applied, and subsequently, a position of the floating diffusion layer 128 and is output as a voltage corresponding to an amount of the charge from the output amplifier 55 as shown in an arrow of FIG. 4. As described above, a detected light is converted into the charge and is output as a voltage signal. Next, description will be given to a simulation carried out by using a computer in order to confirm an effect produced by changing the material of the gate material 107 from the N-type polysilicon to the P-type polysilicon in the solid state imaging device having the NMOS structure as in the solid state imaging device illustrated in FIG. 2. FIG. 5 is an enlarged sectional view showing a sectional structure related to an imaging cell and a periphery thereof in the solid state imaging device shown in FIG. 2, and FIGS. 6A and 6B are typical views illustrating a result of the simulation related to the imaging cell and the periphery thereof shown in FIG. 5. In the simulation, there were examined a most surface potential distribution and a diffusion current thus flowing between adjacent cells for a region 160 in the vicinity of a boundary between an imaging cell 120(1) and another imaging cell 120(2) which is adjacent thereto as shown in FIG. 5. More specifically, FIG. 6A shows a model of a structure, illustrating the region 160 of FIG. 5 in the solid state imaging device using the P-type polysilicon as the gate electrode 107 which is enlarged. In FIG. 6B, an electric potential is represented as a contour line and a flow of a diffusion current is shown in a small arrow. Conditions assumed in the simulation are as follows. A size of each imaging cell: 2 μm×2 μm A difference in a work function between P-poly and N-poly: 1.1 V If the material of the gate electrode 107 is simply changed from the N-type polysilicon to the P-type polysilicon, moreover, a potential of the vertical charge transfer portion (VCCD) 130 is shallowed so that a saturation capacity of the VCCD is decreased and a signal charge is also read in the reading portion with difficulty. In the simulation, therefore, a VCCD (BC) dose is regulated (an impurity concentration is increased) in such a manner that a saturation capacity of the VCCD is not changed, and furthermore, a channel dose (TGI) is regulated (the impurity concentration is reduced) in such a manner that a reading characteristic is not varied in addition to the change of the material for the gate electrode 107 from the N-type polysilicon to the P-type polysilicon. With reference to FIG. 6B, a diffusion current flowing downward from the gate electrode 107 appears in a portion of a circled region 161. A smear is caused by the diffusion current. FIG. 7 shows a result obtained by examining the diffusion current in detail. FIG. 7 is a graph showing a surface potential distribution for each of the case in which the P-type polysilicon (P-poly) is used as the material of the gate electrode 107 and the case in which the N-type polysilicon (N-poly) is used as the material of the gate electrode 107. With reference to the graph of FIG. 7, a curve shown in a solid line represents the case in which the P-type polysilicon (P-poly) is used as the material of the gate electrode 107 and a curve shown in a dotted line represents the case in which the N-type polysilicon (N-poly) is used as the material of the gate electrode 107. In their comparison, a clear difference is made in the surface potential distribution, and a region having a small gradient of an electric potential is longer in the P-type polysilicon than that in the N-type polysilicon. Consequently, the generation of the smear is suppressed. In other words, when a carrier (an electron) generated by a photoelectric conversion is dropped into the photodiode 103 or the vertical charge transfer portion 130 by a diffusion in the thin P-type region 106 provided on the surface side of the photodiode 103, the carrier contributes to a sensitivity if it is dropped to the photodiode 103 side and the smear is generated if the carrier is dropped to the vertical charge transfer portion 130 side. At this time, referring to the diffusion of the carrier, a rate of the drop to the photodiode 103 is increased if the region having a small potential gradient is comparatively longer. In the P-type polysilicon, accordingly, the sensitivity can be enhanced more highly and the smear can be suppressed more greatly. More specifically, it is possible to produce an advantage that the smear caused by the diffusion current can be reduced by approximately 15% because of the difference. Referring to the cause of the smear, most of the diffusion current (95% or more based on a calculation) flows into an adjacent pixel VCCD forming a thick device isolating region. When the VCCD dose is regulated, therefore, the effect of reducing the smear is reduced. However, the effect is rarely influenced by the regulation of the channel dose. Moreover, the extent of the smear caused by the foregoing is determined depending on a distance between an open end of the photodiode 103 and the vertical charge transfer portion 130 in an adjacent column. Therefore, it can be anticipated that the extent will be further remarkable in the future by a further microprocessing of each imaging cell. Next, description will be given to a specific example of a process for manufacturing the solid state imaging device. FIGS. 8A to 8E and 9A to 9E show an example of the process for manufacturing the solid state imaging device according to the embodiment. First of all, as shown in FIG. 8A, a silicon oxide film 81a, a silicon nitride film 81b and a silicon oxide film 81c are formed on a surface of the n-type silicon substrate 101 so that a gate oxide film 81 having a three-layer structure is formed. Subsequently, P-type polysilicon doped with B (boron) is formed on the gate oxide film 81 by low pressure CVD using SiH4 and BCl3 or B2H6. Alternatively, non-doped polysilicon may be formed and B (boron) ions may be implanted to obtain a P type. As shown in FIG. 8B, then, a desirable mask is used to carry out exposure, development and washing by photolithograly so that a resist pattern R1 is formed. As shown in FIG. 8C, thereafter, a polycrystalline silicon film 83 is selectively etched and removed by using the silicon nitride film 81b of the gate oxide film 81 as an etching stopper through reactive ion etching using a mixed gas of HBr and O2 utilizing the resist pattern R1 as a mask. Thus, an electrode is formed. It is desirable to use an etching apparatus such as a high density plasma. By using the resist pattern R1 as a mask, subsequently, an ion implantation for compensating for a transfer efficiency is carried out. A boron ion is implanted on a predetermined condition. Then, the resist pattern R1 is then removed by ashing. Thereafter, an interelectrode insulating film 85 constituted by a silicon oxide film is formed on a surface of an electrode pattern by the low pressure CVD (FIG. 8D). Next, a resist is applied to form a resist pattern R2 having an opening in a photodiode formation region to be a photoelectric converting portion by the photolithography (FIG. 8E). Subsequently, the polycrystalline silicon film 83 is selectively etched and removed by using the silicon nitride film 81b of the gate oxide film 81 as an etching stopper through the reactive ion etching using a mixed gas of HBr and O2 utilizing the resist pattern R2 as a mask. Thus, the photodiode formation region is opened (FIG. 9A). As shown in FIG. 9B, then, the resist pattern R2 is exactly left and an ion implantation for forming a pn junction of the photodiode is carried out by using the resist pattern R2 as a mask so that a diffusion region 87 for forming the pn junction with the substrate 101 is formed as shown in FIG. 9C. As shown in FIG. 9D, thereafter, a sidewall of the electrode 83 is oxidized so that a silicon oxide film is also formed on the sidewall of the electrode 83. As shown in FIG. 9E, subsequently, the silicon nitride film 81b is removed by etching to form a solid state imaging device having a single layer electrode structure which includes the P-type gate electrode 83. The manufacturing process is an example of the formation of the P-type gate electrode 83. In addition, various changes can be made. Second Embodiment Next, description will be given to a second embodiment of the solid state imaging device according to the invention. FIG. 10 is an enlarged sectional view showing a sectional structure related to an imaging cell and a periphery thereof in the solid state imaging device according to the second embodiment. The structure of the solid state imaging device according to the embodiment is the same as the structure shown in FIG. 5 except for a shape of a gate electrode 107. In FIG. 10, therefore, elements corresponding to the contents shown in FIG. 5 have the same reference numerals. The structure shown in FIG. 10 has a great feature that a gate electrode 107(2) in an adjacent column is protruded from an end position on a photodiode 103 side of a vertical charge transfer portion 130(2) toward the photodiode 103 side. More specifically, an end 171 of the vertical charge transfer portion 130(2) is not coincident with an end 172 of the gate electrode 107(2) differently from FIG. 5 but their positions are shifted from each other in a horizontal direction and the end 172 of the gate electrode 107(2) is protruded by a distance L toward an imaging cell in an adjacent column. With the structure, it is possible to increase the effect of suppressing the flow of a diffusion current to the vertical charge transfer portion 130(2) in another adjacent column from the photodiode 103 through a surface of a P-type region 106, and the smear can be suppressed more effectively. When the amount (L) of the protrusion of the end 172 of the gate electrode 107(2) is excessively large, there is a high possibility that a signal charge of the photodiode 103 might be read into the vertical charge transfer portion 130(2) in the adjacent column when the signal charge is to be read. Referring to the amount of the protrusion of the end 172, accordingly, it is necessary to determine the amount (L) of the protrusion in a position of an isolating region 106a for partitioning a portion from an end 103a of the photodiode 103 to the end 171 of the vertical charge transfer portion 130(2). Third Embodiment Next, description will be given to a third embodiment related to the solid state imaging device according to the invention. FIG. 11 is a plan view showing a structure of the solid state imaging device according to the third embodiment. The embodiment is a variant of the first embodiment. The solid state imaging device shown in FIG. 11 is also constituted by using an NMOS process in the same manner as in the first embodiment, and comprises an imaging portion 110A, a line memory 52A, a horizontal charge transfer portion 54A and an output amplifier 55. While only the gate electrode 107 is constituted by P+-type polysilicon in the first embodiment, other electrodes are also constituted by the P+-type polysilicon in the solid state imaging device shown in FIG. 11. More specifically, referring to the imaging portion 110A, charge transfer electrodes to be used for transferring a signal charge over a channel of each vertical charge transfer portion 130 (which correspond to the first vertical transfer electrode 41, the second vertical transfer electrode 43, the first auxiliary transfer electrode 45, the second auxiliary transfer electrode 46 and the third auxiliary transfer electrode 47 in FIG. 2) as well as the gate electrode 107 are constituted by the P+-type polysilicon. Referring to the line memory 52A, moreover, charge transfer electrodes (corresponding to LM1 and LM2 in FIG. 3) are also constituted by the P+-type polysilicon. Referring to the horizontal charge transfer portion 54A, furthermore, charge transfer electrodes (corresponding to Ha and Hb in FIGS. 3 and 151 to 154 and 155 in FIG. 4) are constituted by the P+-type polysilicon. Electrodes of the output amplifier 55 and the other circuits are constituted by N-type polysilicon in the same manner as in a general device having an NMOS structure. According to the solid state imaging device, the whole charge transfer electrode is formed by P-type polysilicon so that N- and P-type polysilicon electrodes are not partially mixed in the device. Thus, it is possible to simplify a device structure and a manufacturing process. A specific structure related to the gate electrode 107 provided in the solid state imaging device may be a general two-layer polysilicon layer structure, a dummy single layer structure, a single layer structure or a polycide structure. FIG. 12 typically shows an example of a structure of an electrode in the case of the two-layer polysilicon structure. As shown in FIG. 12, referring to the electrode of a two-phase polysilicon structure, a gate electrode 107A has such a structure that a first electrode 91 and a second electrode 93 partially overlap each other in a vertical direction. Moreover, FIG. 13 typically shows an example of a structure of an electrode in the case of the polycide structure. As shown in FIG. 13, referring to the electrode of the polycide structure, a gate electrode 107B constituted by tungsten polycide is formed by laminating a polycrystalline silicon layer 95 and a tungsten polycide layer 97 provided thereon. The structure of the electrode using the polycide of this type has also been disclosed in JP-A-2005-353766, for example. By forming the gate electrode as a P-type polysilicon electrode, similarly, it is possible to obtain the same advantages. While the solid state imaging device is constituted by using the NMOS process in each of the embodiments, it is a matter of course that the solid state imaging device can also be constituted by using a PMOS process. In the case in which the solid state imaging device is constituted by using the PMOS process, it is preferable to use the N-type polysilicon as the material of the gate electrode 107. Consequently, it is possible to reduce a smear in the same manner as in each of the embodiments. According to the invention, it is possible to effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negate bias) from an outside to a gate electrode. As described above, the solid state imaging device according to the invention can effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage (a negative bias) from an outside to a gate electrode. By applying the invention to a two-dimensional CCD image sensor such as a digital camera, accordingly, it is possible to suppress the smear generated in the case in which a subject having a high luminance is to be photographed. The entire disclosure of each and every foreign patent application from which the benefit of foreign priority has been claimed in the present application is incorporated herein by reference, as if fully set forth.	H	67H01	185H01L	271	48
11787541	US20070194399A1-20070823	Optoelectronic devices and solar cells	ACCEPTED	20070808	20070823	[]	H01L310232	["H01L310232"]	7723166	20070416	20100525	438	149000	68971.0	RAO	SHRINIVAS	[{"inventor_name_last": "Bhattacharyya", "inventor_name_first": "Arup", "inventor_city": "Essex Junction", "inventor_state": "VT", "inventor_country": "US"}]	The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.	1. An optoelectronic device, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being heavily-doped semiconductor material; a second layer of semiconductor material over the first layer of semiconductor material; to the extent that the second layer of semiconductor material comprises any dopant, the second semiconductor layer having a lower concentration of dopant than the first layer of semiconductor material; a layer of semiconductor-enriched insulator over the second layer of semiconductor material; and a second electrode over a first portion of the layer of semiconductor-enriched insulator; the second electrode having at least one window extending therethrough to a second portion of the layer of semiconductor-enriched insulator. 2. The device of claim 1 wherein the semiconductor-enriched insulator comprises germanium-enriched germanium nitride. 3. The device of claim 1 wherein the semiconductor-enriched insulator comprises one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. 4. The device of claim 1 wherein the second electrode is electrically biased to a negative potential relative to the first electrode. 5. The device of claim 1 wherein the first layer of semiconductor material is heavily doped with n-type dopant. 6. The device of claim 1 wherein the first and second layers of semiconductor material are both doped with n-type dopant. 7. The device of claim 1 wherein: the first layer of semiconductor material consists essentially of doped silicon; and the second layer of semiconductor material consists essentially of doped or undoped silicon. 8. The device of claim 1 wherein: the first layer of semiconductor material consists essentially of doped germanium; and the second layer of semiconductor material consists essentially of doped or undoped germanium. 9. The device of claim 8 further comprising a third layer between the second layer and the layer of semiconductor-enriched insulator, the third layer consisting essentially of doped or undoped silicon. 10. The device of claim 9 wherein the third layer consists essentially of undoped silicon. 11. The device of claim 9 wherein the third layer consists essentially of doped silicon. 12. The device of claim 1 wherein: the first layer of semiconductor material consists essentially of doped silicon-germanium; and the second layer of semiconductor material consists essentially of doped or undoped silicon-germanium. 13. The device of claim 1 wherein the semiconductor-enriched insulator consists essentially of silicon-enriched silicon nitride, and comprises from about 1 atomic percent excess silicon to about 20 atomic percent excess silicon, with the excess silicon being measured relative to Si3N4. 14. The device of claim 1 wherein the semiconductor-enriched insulator consists essentially of silicon-enriched silicon oxide, and comprises from about 1 atomic percent excess silicon to about 20 atomic percent excess silicon, with the excess silicon being measured relative to SiO2. 15. An optoelectronic device, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being heavily n-type doped semiconductor material; a second layer of semiconductor material over the first layer of semiconductor material; to the extent that the second layer of semiconductor material comprises any n-type dopant, the second semiconductor layer having a lower concentration of n-type dopant than the first layer of semiconductor material; a layer of silicon-enriched insulator over the second layer of semiconductor material; the silicon-enriched insulator comprising one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride; and a second electrode over a first portion of the layer of silicon-enriched insulator; the second electrode having at least one window extending therethrough to a second portion of the layer of silicon-enriched insulator. 16-55. (canceled) 56. An optoelectronic device configured to detect one or more particular wavelengths of light, comprising: a semiconductor substrate lightly doped with a first type of dopant, the lightly-doped semiconductor substrate comprising a body region of the device; a gate stack over the body region; the gate stack comprising a layer of semiconductor-enriched insulator, and comprising a covering material over the layer of semiconductor-enriched insulator; the covering material being at least partially transparent to the one or more particular wavelengths of light; and a pair of heavily-doped regions within the semiconductor substrate and operatively proximate the gate stack and body region, the heavily-doped regions being doped with a second type of dopant; one of the first and second types of dopant being n-type and the other being p-type. 57-71. (canceled) 72. A solar cell, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being heavily doped with a first dopant type; a second layer of semiconductor material over the first layer of semiconductor material; the second layer of semiconductor material being lightly doped with the first dopant type; a layer of semiconductor-enriched insulator over the second layer of semiconductor material; a second electrode extending over one or more first segments of the layer of semiconductor-enriched insulator; and one or more windows over one or more second segments of the layer of semiconductor-enriched insulator, the one or more windows permitting one or more particular wavelengths of electromagnetic radiation to reach said one or more second segments of the layer of semiconductor-enriched insulator. 73-96. (canceled) 97. A solar cell, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being either heavily n-type doped or heavily p-type doped; a second layer of semiconductor material over the first layer of semiconductor material; a third layer of semiconductor material over the second layer of semiconductor material, one of the second and third layers comprising amorphous silicon and the other of the second and third layers comprising amorphous silicon-germanium; a layer of semiconductor-enriched insulator over the third layer of semiconductor material; a second electrode extending over one or more first segments of the layer of semiconductor-enriched insulator; and one or more windows over one or more second segments of the layer of semiconductor-enriched insulator, the one or more windows permitting one or more particular wavelengths of electromagnetic radiation to reach said one or more second segments of the layer of semiconductor-enriched insulator. 98-126. (canceled) 127. A solar cell, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being either heavily n-type doped or heavily p-type doped; three light-detecting regions over the first layer of semiconductor material; a first of the three light-detecting regions comprising a first silicon-germanium composition, a second of the three light-detecting regions comprising a second silicon-germanium composition, and a third of the three light-detecting regions consisting essentially of amorphous silicon without any substantial concentration of germanium, the first silicon-germanium composition having a different atomic concentration of germanium than the second silicon-germanium composition; a layer of semiconductor-enriched insulator over the three light-detecting regions; a second electrode extending over one or more first segments of the layer of semiconductor-enriched insulator; and one or more windows over one or more second segments of the layer of semiconductor-enriched insulator, the one or more windows permitting one or more particular wavelengths of electromagnetic radiation to reach said one or more second segments of the layer of semiconductor-enriched insulator. 128-174. (canceled)	<SOH> BACKGROUND OF THE INVENTION <EOH>Optoelectronic devices (i.e., devices which detect electromagnetic radiation) have numerous applications. For instance, optoelectronic devices can be utilized as photodetectors in cameras and other imaging equipment. A continuing goal is to decrease the size and complexity of optoelectronic devices, while increasing robustness of the devices. Accordingly, it is desired to develop improved optoelectronic devices. Solar cells (i.e., cells which convert electromagnetic radiation into electrical energy) also have numerous applications. For instance, solar cells can be utilized for providing energy in remote locations, and/or can be utilized to alleviate dependence on other power sources (such as, for example, batteries, petroleum, etc.). A continuing goal is to reduce the cost, size and/or complexity of solar devices, while maintaining, and preferably improving, robustness of the devices. Accordingly, it is desired to develop improved solar cells. Although the term “solar cell” refers to “solar” and thus implies that it is configured to work with sunlight, the term “solar cell” is utilized in the art to refer generically to devices which convert electromagnetic radiation from any source (sunlight or otherwise) to electrical energy. The term “solar cell” is utilized herein to refer to devices which convert electromagnetic radiation from any source (sunlight or otherwise) into electrical energy, and is to be understood to be broad enough to include devices which convert light from regions of the electromagnetic spectrum outside of the wavelengths primarily associated with sunlight.	<SOH> SUMMARY OF THE INVENTION <EOH>In one aspect, the invention includes an optoelectronic device. The device comprises a first electrode, a first layer of semiconductor material over the first electrode, a second layer of semiconductor material over the first layer of semiconductor material, a layer of semiconductor-enriched insulator over the second layer of semiconductor material, and a second electrode over the layer of semiconductor-enriched insulator. The second electrode has at least one window extending therethrough to a portion of the layer of semiconductor-enriched insulator. The first layer of semiconductor material is heavily-doped semiconductor material, and the second layer of semiconductor material is either essentially undoped or doped to a lower concentration of dopant than the first layer of semiconductor material. In particular aspects, the first layer of semiconductor material of the above-described optoelectronic device can be heavily n-type doped semiconductor material, and the second layer of semiconductor material can be lightly n-type doped semiconductor material. Also, in particular aspects, the semiconductor-enriched insulator can comprise one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. In one aspect, the invention encompasses an optoelectronic device comprising a semiconductor substrate lightly doped with a first type of dopant and comprising a defined body region of the device. The device includes a gate stack over the body region, with the gate stack containing a layer of semiconductor-enriched insulator and containing a covering material over the semiconductor-enriched insulator. The covering material is at least partially transparent to one or more wavelengths of light that are to be detected by the device. The optoelectronic device further comprises a pair of source/drain regions within the semiconductor substrate and operatively proximate the gate stack and body region. The source/drain regions are heavily doped with a second type of dopant. One of the first and second types of dopant is n-type and the other is p-type. In one aspect, the invention includes a solar cell. The solar cell comprises a first electrode, a first layer of semiconductor material over the first electrode, a second layer of semiconductor material over the first layer of semiconductor material, a layer of semiconductor-enriched insulator over the second layer of semiconductor material, a second electrode extending over one or more segments of the layer of semiconductor-enriched insulator, and one or more windows over one or more segments of the layer of semiconductor-enriched insulator. The one or more windows permit one or more wavelengths of electromagnetic radiation to reach segments of the layer of semiconductor-enriched insulator beneath the windows. The first layer of semiconductor material is heavily-doped with a first dopant type, and the second layer of semiconductor material is lightly-doped with the first dopant type. In one aspect, the invention encompasses a solar cell which includes a first electrode, a first layer of semiconductor material over the first electrode, a plurality of light-detecting regions over the first layer of semiconductor material (for example, three light-detecting regions can be provided in exemplary aspects of the invention), a layer of semiconductor-enriched insulator over the plurality of light-detecting regions, a second electrode extending over segments of the layer of semiconductor-enriched insulator, and one or more windows which permit electromagnetic radiation to reach the semiconductor-enriched insulator. In exemplary aspects in which three light-detecting regions are utilized, a first of the three light-detecting regions can be a stack of amorphous silicon and amorphous silicon-germanium, a second of the light-detecting regions can be another stack of amorphous silicon and amorphous silicon-germanium, and a third of the light-detecting regions can be amorphous silicon without any substantial concentration of germanium. The amorphous silicon-germanium of the first stack can have a different atomic concentration of germanium than the amorphous silicon-germanium of the second stack. The first layer of semiconductor material can be either heavily n-type doped or heavily p-type doped; and the layer of semiconductor-enriched insulator can comprise one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. The invention also includes methods of forming optoelectronic devices, and methods of forming solar cells.	TECHNICAL FIELD The invention pertains to optoelectronic devices and solar cells, and pertains to methods of making optoelectronic devices and solar cells. BACKGROUND OF THE INVENTION Optoelectronic devices (i.e., devices which detect electromagnetic radiation) have numerous applications. For instance, optoelectronic devices can be utilized as photodetectors in cameras and other imaging equipment. A continuing goal is to decrease the size and complexity of optoelectronic devices, while increasing robustness of the devices. Accordingly, it is desired to develop improved optoelectronic devices. Solar cells (i.e., cells which convert electromagnetic radiation into electrical energy) also have numerous applications. For instance, solar cells can be utilized for providing energy in remote locations, and/or can be utilized to alleviate dependence on other power sources (such as, for example, batteries, petroleum, etc.). A continuing goal is to reduce the cost, size and/or complexity of solar devices, while maintaining, and preferably improving, robustness of the devices. Accordingly, it is desired to develop improved solar cells. Although the term “solar cell” refers to “solar” and thus implies that it is configured to work with sunlight, the term “solar cell” is utilized in the art to refer generically to devices which convert electromagnetic radiation from any source (sunlight or otherwise) to electrical energy. The term “solar cell” is utilized herein to refer to devices which convert electromagnetic radiation from any source (sunlight or otherwise) into electrical energy, and is to be understood to be broad enough to include devices which convert light from regions of the electromagnetic spectrum outside of the wavelengths primarily associated with sunlight. SUMMARY OF THE INVENTION In one aspect, the invention includes an optoelectronic device. The device comprises a first electrode, a first layer of semiconductor material over the first electrode, a second layer of semiconductor material over the first layer of semiconductor material, a layer of semiconductor-enriched insulator over the second layer of semiconductor material, and a second electrode over the layer of semiconductor-enriched insulator. The second electrode has at least one window extending therethrough to a portion of the layer of semiconductor-enriched insulator. The first layer of semiconductor material is heavily-doped semiconductor material, and the second layer of semiconductor material is either essentially undoped or doped to a lower concentration of dopant than the first layer of semiconductor material. In particular aspects, the first layer of semiconductor material of the above-described optoelectronic device can be heavily n-type doped semiconductor material, and the second layer of semiconductor material can be lightly n-type doped semiconductor material. Also, in particular aspects, the semiconductor-enriched insulator can comprise one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. In one aspect, the invention encompasses an optoelectronic device comprising a semiconductor substrate lightly doped with a first type of dopant and comprising a defined body region of the device. The device includes a gate stack over the body region, with the gate stack containing a layer of semiconductor-enriched insulator and containing a covering material over the semiconductor-enriched insulator. The covering material is at least partially transparent to one or more wavelengths of light that are to be detected by the device. The optoelectronic device further comprises a pair of source/drain regions within the semiconductor substrate and operatively proximate the gate stack and body region. The source/drain regions are heavily doped with a second type of dopant. One of the first and second types of dopant is n-type and the other is p-type. In one aspect, the invention includes a solar cell. The solar cell comprises a first electrode, a first layer of semiconductor material over the first electrode, a second layer of semiconductor material over the first layer of semiconductor material, a layer of semiconductor-enriched insulator over the second layer of semiconductor material, a second electrode extending over one or more segments of the layer of semiconductor-enriched insulator, and one or more windows over one or more segments of the layer of semiconductor-enriched insulator. The one or more windows permit one or more wavelengths of electromagnetic radiation to reach segments of the layer of semiconductor-enriched insulator beneath the windows. The first layer of semiconductor material is heavily-doped with a first dopant type, and the second layer of semiconductor material is lightly-doped with the first dopant type. In one aspect, the invention encompasses a solar cell which includes a first electrode, a first layer of semiconductor material over the first electrode, a plurality of light-detecting regions over the first layer of semiconductor material (for example, three light-detecting regions can be provided in exemplary aspects of the invention), a layer of semiconductor-enriched insulator over the plurality of light-detecting regions, a second electrode extending over segments of the layer of semiconductor-enriched insulator, and one or more windows which permit electromagnetic radiation to reach the semiconductor-enriched insulator. In exemplary aspects in which three light-detecting regions are utilized, a first of the three light-detecting regions can be a stack of amorphous silicon and amorphous silicon-germanium, a second of the light-detecting regions can be another stack of amorphous silicon and amorphous silicon-germanium, and a third of the light-detecting regions can be amorphous silicon without any substantial concentration of germanium. The amorphous silicon-germanium of the first stack can have a different atomic concentration of germanium than the amorphous silicon-germanium of the second stack. The first layer of semiconductor material can be either heavily n-type doped or heavily p-type doped; and the layer of semiconductor-enriched insulator can comprise one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. The invention also includes methods of forming optoelectronic devices, and methods of forming solar cells. BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention are described below with reference to the following accompanying drawings. FIG. 1 is a diagrammatic, fragmentary, cross-sectional view of an optoelectronic device in accordance with one aspect of the present invention. FIG. 2 is a diagrammatic, fragmentary, cross-sectional view of an optoelectronic device in accordance with another aspect of the present invention. FIG. 3 is a diagrammatic, cross-sectional view of an optoelectronic device in accordance with yet another aspect of the present invention. FIG. 4 is a diagrammatic, fragmentary cross-sectional view of an optoelectronic device in accordance with yet another aspect of the present invention. FIG. 5 is a diagrammatic, cross-sectional, fragmentary view of a solar cell in accordance with an aspect of the present invention. FIG. 6 is a diagrammatic, cross-sectional, fragmentary view of a solar cell in accordance with another aspect of the present invention. FIG. 7 is a diagrammatic, fragmentary, cross-sectional view of a solar cell in accordance with yet another aspect of the present invention. FIG. 8 is a diagrammatic, cross-sectional, fragmentary view of a solar cell in accordance with yet another aspect of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). Structures containing stacks of metal/semiconductor-enriched insulator/semiconductor can behave like semiconductor junction diodes if appropriate compositions of semiconductor-enriched insulator are employed. Such characteristics of semiconductor-enriched insulators can be exploited in combination with various electrical and optical properties of the materials to form optoelectronic devices and solar cells. The semiconductor-enriched insulator family of materials includes silicon-enriched insulator materials, such as silicon-enriched silicon oxide and silicon-enriched silicon nitride. A silicon-enriched silicon nitride can, for example, comprise from about 1 atomic percent excess silicon to about 20 atomic percent excess silicon as measured relative to Si3N4; and a silicon-enriched silicon oxide can, for example, comprise from about 1 atomic percent excess silicon to about 20 atomic percent excess silicon, as measured relative to SiO2. The amount of excess silicon can be measured by direct measurement of the silicon concentration, or alternatively can be measured by determining the refractive index of a silicon-enriched material. For instance, Si3N4 will have a refractive index of about 2, and silicon enrichment of the silicon nitride will increase the refractive index quantitatively, as is known to persons of ordinary skill in the art. Similarly, silicon dioxide (SiO2) has a refractive index of about 1.5, and silicon enrichment of the silicon dioxide will alter the refractive index in a quantitative manner, as is known to persons of ordinary skill in the art. The semiconductor-enriched insulator family of materials also includes germanium-enriched insulator materials, such as, for example, germanium-enriched germanium nitride. Semiconductor-enriched insulator materials tend to be multiphase materials, with the excess semiconductor material being present in a matrix of the dominate material. For instance, silicon-enriched silicon nitride will generally have a phase of silicon within a matrix of silicon nitride, and silicon-enriched silicon oxide will generally have a phase of silicon present within matrix of silicon dioxide. The physical properties of semiconductor-enriched insulator materials can enable the materials to be utilized for charge trapping, with silicon-enriched materials having from about 1 atomic % to about 20 atomic % excess silicon frequently being capable of a charge trapping density of from about 1% to about 10%. In some aspects of the invention, the semiconductor layer of a stack of metal/semiconductor-enriched insulator/semiconductor (such as a stack of meta/silicon-enriched insulator/silicon) can be essentially undoped (i.e., can contain less than 1×1017 atoms/cm3 of dopant; in other aspects the semiconductor layer can be lightly doped (i.e., can contain from about 1×1017 atoms/cm3 to about 1×1020 atoms/cm3 of dopant); and in yet other aspects the semiconductor layer can be heavily doped (i.e., can contain greater than about 1×1020 atoms/cm3 of dopant). The semiconductor-enriched insulators utilized in the various aspects of the invention described herein can be formed by any suitable methodology. In some aspects, such insulators can be formed utilizing low pressure chemical vapor deposition (LPCVD) technology, or plasma enhanced chemical vapor deposition (PECVD) technology. Deposition temperatures are typically from about 700° C. to about 800° C. for LPCVD, and from about 200° C. to about 400° C. for PECVD. In alternative aspects, electron-cyclotron-resonance plasma enhanced CVD processes (ECR-PECVD) can be utilized for forming semiconductor-enriched insulators. Such technology can enable the semiconductor-enriched insulators to be formed with excellent physical/electrical properties during deposition at room temperature, or near room temperature, followed by a rapid thermal anneal. The ECR-PECVD process can be particularly useful for forming optoelectronics and/or solar cells when low temperature processing is desired. Appropriate control of the deposition conditions utilized to form semiconductor-enriched insulators can enable control of various physical properties of the insulator composition. For instance, appropriate control of the deposition conditions utilized to form silicon-enriched insulators can enable the concentration, size and distribution of excess silicon to be controlled. Various properties of silicon-enriched insulators, such as, for example, refractive index, dielectric permittivity, optical absorption, electrical conductivity, charge trapping characteristics (trap density/trap depth) can be reproducibly and widely altered by controlling the composition (i.e., the amount of silicon enrichment) within the films. Frequently, silicon-enriched silicon nitride films are found to have superior characteristics in terms of interface control, thermal stability, device reproducibility, and radiation hardness as compared to silicon-enriched silicon oxide films. Accordingly, it can be preferable that the devices described herein be formed utilizing silicon-enriched silicon nitride films. It is to be understood, however, that silicon-enriched oxide films can also be utilized in the devices, and further that other semiconductor-enriched insulator materials can be utilized, including, for example, germanium-rich materials and silicon-germanium rich materials. In some aspects, it can be advantageous to utilize a material comprising, consisting essentially of, or consisting of germanium-enriched germanium nitride for detecting infrared radiation. Electrical conductivity of silicon-enriched silicon nitride films can be varied by several orders of magnitude by controlling the concentration of excess silicon (and accordingly the refractive index) of such films. At low excess silicon concentration, the conductivity approaches that of silicon nitride (Si3N4), whereas at high silicon concentrations the materials behave like semiconductors. Similarly, optical properties (for example a refractive index) are also altered by the concentration of excess silicon. The relationship between refractive index and silicon/nitrogen ratio of silicon rich nitride films is published, as is the relationship between current density (J) versus electric field (E) for different silicon/nitrogen ratios of silicon nitride films. Other semiconductor-enriched materials, including, for example, silicon-enriched silicon oxide, also have physical properties which can be varied by controlling the concentration of excess semiconductor within the materials. In particular aspects, the invention pertains to optoelectronic devices and methods of forming such devices. Such aspects are discussed with reference to FIGS. 1-4. In other aspects, the invention pertains to solar cells and methods of forming solar cells. Such aspects are discussed with reference to FIGS. 5-8. Referring initially to FIG. 1, an exemplary optoelectronic device 10 is illustrated. Device 10 comprises a support structure, or base, 12. Such support structure can comprise any suitable material or combination of materials, including, for example, various polymers (such as plastic), glass, metal, etc. A first electrode 14 is supported by base 12. First electrode 14 can comprise any suitable electrically conductive composition, or combination of compositions. In particular aspects, first electrode 14 will comprise, consist essentially of, or consist of one or both of silver and aluminum. A layer 16 is over electrode 14, and in the shown aspect is in direct physical contact with a surface of electrode 14. Layer 16 comprises semiconductor material, and in particular aspects will be heavily doped. For instance, layer 16 can comprise, consist essentially of, or consist of heavily-doped silicon, heavily-doped germanium, or heavily-doped silicon-germanium. The heavy dopant concentration within layer 16 will typically correspond to n-type dopant (such as, for example, phosphorous), but it is to be understood that the invention encompasses other aspects (discussed below) in which the dopant type can be p-type. Construction 10 comprises a layer 18 over layer 16. Layer 18 corresponds to a layer of semiconductor material, and in some aspects layers 16 and 18 can be referred to as a first layer of semiconductor material and a second layer of semiconductor material, respectively, to distinguish the layers from one another. Layer 18 is shown to be thicker than layer 16, but it is to be understood that the relative thicknesses of layers 16 and 18 can vary so that layers 16 and 18 are about the same thicknesses as one another, or so that layer 16 is thicker than layer 18. Second layer 18 can comprise essentially undoped semiconductor material, or can comprise doped semiconductor material. Typically, to the extent that layer 18 comprises any dopant, the layer will have a lower concentration of dopant than first layer 16. If layer 18 is doped, the dopant type within layer 18 can match that within layer 16. Accordingly, layer 16 can correspond to heavily n-type doped semiconductor material and layer 18 can correspond to lightly n-type doped semiconductor material. In particular aspects, layer 16 can comprise, consist essentially of, or consist of heavily n-type doped silicon and layer 18 can comprise, consist essentially of, or consist of lightly n-type doped silicon; and in other aspects, layer 16 can comprise, consist essentially of, or consist of heavily n-type doped germanium and layer 18 can comprise, consist essentially of, or consist of lightly n-type doped germanium; and in yet other aspects layer 16 can comprise, consist essentially of, or consist of heavily n-type doped silicon-germanium and layer 18 can comprise, consist essentially of, or consist of lightly n-type doped silicon-germanium. An electrically insulative material 20 is over second semiconductor layer 18 and patterned to cover a portion 22 of layer 18 while not covering a portion 24 of layer 18. More specifically, insulative material 20 is patterned to have an opening 26 extending therethrough and to an upper surface of layer 18. Insulative material 20 can comprise, consist essentially of, or consist of any suitable material or combination of materials, including, for example, silicon dioxide. A layer 28 of semiconductor-enriched insulator is provided over insulative material 20 and within opening 26. The layer 28 of semiconductor-enriched insulator is shown to be in direct physical contact with an upper surface of second semiconductor layer 18 within the opening 26. Layer 28 can, in particular aspects, correspond to a silicon-enriched insulator. In some aspects, layer 28 can comprise, consist essentially of, or consist of silicon-enriched silicon nitride, and can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon relative to Si3N4. Alternatively, layer 28 can comprise, consist essentially of, or consist of silicon-enriched silicon oxide, and can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon relative to SiO2. In yet other aspects, layer 28 can correspond to a mixture of silicon-enriched silicon nitride and silicon-enriched silicon oxide. Layer 28 can have any suitable thickness, and in particular aspects will have a thickness of from about 10 nanometers to about 50 nanometers. In the shown aspect, layer 28 can be considered to have a portion over insulative material 20 and spaced from layer 18 by the insulative material 20, and to have another portion directly against layer 18. A second electrode 30 is over semiconductor-enriched insulator 28. Second electrode 30 is patterned so that the second electrode is over a first portion of semiconductor-enriched insulator 28, and has a window 32 extending therethrough to a second portion of semiconductor-enriched insulator 28. The first portion of semiconductor-enriched insulator 28 is diagrammatically labeled as 29, and the second portion of semiconductor-enriched insulator 28 is diagrammatically labeled as 31. Second electrode 30 can comprise any suitable electrically conductive composition or combination of compositions. In particular aspects, second electrode 30 will comprise the same composition as first electrode 14, and in other aspects second electrode 30 will comprise a different composition than first electrode 14. In exemplary aspects, second electrode 30 can comprise one or both of silver and aluminum. An antireflective material 34 is provided within window 32 and over the second portion 31 of semiconductor-rich insulator 28. Antireflective material 34 can, for example, comprise, consist essentially of, or consist of indium tin oxide (ITO). The antireflective coating can be utilized to enhance the absorption efficiency of incident photon flux. Circuitry 36 is shown provided to electrically bias second electrode 30 relative to first electrode 14. Specifically, the circuitry is shown biasing the second electrode to a negative potential relative to the first electrode. Such bias assumes that the conductively-doped material of layers 16 and 18 is n-type doped. If the semiconductor material of layers 16 and 18 is p-type doped, the shown bias of circuitry 36 will typically be reversed so that second electrode 30 would have a positive potential relative to first electrode 14. However, it is generally preferred that n-type doping be utilized in devices of the type diagrammatically illustrated as device 10, and accordingly it is generally preferred that circuit 36 be provided to negatively bias second electrode 30 relative to first electrode 14. Electromagnetic radiation 38 is diagrammatically illustrated as being directed toward device 10, and specifically as entering window 32. The electromagnetic radiation can interact with semiconductor-enriched material 18 to cause charge separation to occur, which can be detected as a change in electrical properties by circuit 36. Accordingly, device 10 can be utilized to detect electromagnetic radiation. More specifically, when light having an energy greater than the Eg of the semiconductor material of layer 28 impacts the diode comprising layer 28, the light gets absorbed into the depletion layer of silicon below the silicon-semiconductor rich semiconductor interface, and electron-hole pairs are generated. Electrons get collected at the positively-biased bottom electrode, and holes get collected at the negatively-biased top electrode. Thus, a photocurrent is generated which flows externally through the load resistor of circuit 36 (labeled as 37) to generate an output voltage (Vout). The particular wavelengths of radiation detected by device 10 can be influenced by, among other things, the composition of material 34, the composition of material 28, the semiconductor material utilized for layer 18 and/or layer 16, and the dopant type and concentration utilized in layer 18 and/or layer 16. For instance, material 34 can be chosen to be relatively transparent to particular wavelengths of light, and non-transparent to other wavelengths of light so that the material 34 functions as a filter to determine which wavelengths of light will be detected by device 10. Alternatively, or additionally, the compositions of layers 16, 18 and 28 can be chosen so that device 10 is more sensitive to particular wavelengths of light than to others. Accordingly, device 10 can be configured as an optoelectronic device having sensitivity for particular desired wavelengths of electromagnetic radiation. The discussion above assumes that second electrode 30 is relatively opaque to the wavelength of radiation detected by device 10. It is to be understood, however, that material 30 can, in some aspects, be at least partially transparent to such radiation. In such aspects, window 32 is defined by the location where semiconductor-enriched layer 28 is closely proximate layer 18 (and in the shown aspect directly physically contacts layer 18) as opposed to regions where layer 28 is spaced from layer 18 by the relatively thick intervening material 20. FIG. 2 shows an optoelectronic device 50 illustrating another embodiment of the present invention. In referring to device 50, similar numbering will be used as was utilized above in describing the device 10 of FIG. 1, where appropriate. Device 50 comprises the base 12, first electrode 14, first and second semiconductor layers 16 and 18, insulative material 20 and semiconductor-enriched material 28 described previously. Device 50 also comprises the circuitry 36 described above with reference to FIG. 1. Device 50 comprises the second electrode 30 and antireflective material 34 discussed above with reference to device 10 of FIG. 1. The second electrode 30 of FIG. 2 is shown patterned differently than that of FIG. 1, and specifically is shown not extending into the opening within insulative material 20 of the FIG. 2 embodiment of the invention. Device 50 comprises a thin electrically conductive layer 52 over semiconductor-enriched material 28. Layer 52 can correspond to a metal-containing material, and in particular aspects can be considered a film of metal-containing material. Layer 52 can have a thickness of, for example, approximately 10 nanometers, and can be optically transparent to the particular wavelengths of electromagnetic radiation desired to be detected with device 50. In particular aspects, film 52 can comprise, consist essentially of, or consist of one or both of gold and aluminum. Layer 52 is shown extending over portions of semiconductor-enriched layer 28 within a window exposed to electromagnetic radiation 38, as well as over portions of layer 28 which are not within such window (i.e., portions covered by second electrode 30). Antireflective material 34 of the FIG. 2 embodiment of the invention can comprise silicon nitride, zinc sulfide (ZnS) and/or zirconium oxide (ZrO2) either in addition to ITO, or in place of ITO. In operation, the thin layer of optically transparent metal film 52 can be used as a conducting element for the top electrode 30. FIG. 3 shows an optoelectronic device 60 in accordance with yet another aspect of the invention. The device 60 of FIG. 3 is identical to the device 50 described with reference to FIG. 2 in all respects except that a layer 62 is provided between semiconductor-enriched insulator 28 and the second semiconductor layer 18. In the shown aspect of the invention, layer 62 is in direct physical contact with both layer 28 and layer 18, with layers 18 and 28 being on opposing sides of layer 62 relative to one another. Layer 62 can comprise semiconductor material, and can be referred to as a third layer of semiconductor material to distinguish layer 62 from the layers 16 and 18 described previously. In particular aspects, device 60 is configured for detecting infrared radiation. In such aspects, layer 16 comprises, consists essentially of, or consists of heavily n-type doped germanium; and layer 18 comprises, consists essentially of, or consists of undoped germanium or n-type doped germanium. If layer 18 is n-type doped germanium, the dopant concentration within layer 18 will typically be less than that within layer 16. Layer 62 comprises, consists essentially of, or consists of either undoped silicon or n-type doped silicon. The silicon of layer 62 is relaxed, in the sense that the silicon has a crystallographic orientation compatible with that of the underlying germanium material, as opposed to a strained configuration in which the silicon would have a crystallographic orientation less compatible with the underlying germanium material. Although the dopant described as being utilized with layer 16, 18 and 62 is n-type dopant, it is to be understood that p-type dopant can be utilized in other aspects of the invention. The cutoff wavelength for a device having a configuration of device 60 can be extended to about 1.9 micrometers, which can provide efficient infrared photodetection in the wavelength range of light of from about 700 nanometers to about 1700 nanometers, with good response time. The devices described above with reference to FIGS. 1-3 are exemplary devices, and it is to be understood that the invention encompasses various modifications which are not shown. For instance, additional semiconductor layers can be provided in addition to the layers 16, 18 and 62. Also, additional antireflective materials can be provided in addition to, or alternatively to, the shown material 34. For instance, material 34 can correspond to a stack of antireflective materials. As another example, an antireflective material can be provided between semiconductor-enriched layer 28 and conductive layer 52 in the embodiments of FIGS. 2 and 3. The semiconductor-enriched insulative material 28 of the above-described optoelectronic devices of FIGS. 1-3 functions similarly to a p-i-n diode (where “i” is an intrinsic or undoped layer of semiconductor), or a metal-insulator-semiconductor diode, or a metal-semiconductor diode. Since there is no p-n junction, the diode of the present can have several intrinsic advantages relative to prior art diodes. Such advantages can include, for example, scalability, very low leakage and therefore low power, high quantum efficiency, low noise, and fast response time (greater than 10−11 seconds) similar to metal-semiconductor diodes. Additionally, high density and low temperature processing can provide potential low costs. Application of the photodiodes of the present invention can be utilized primarily in the ultraviolet and visible ranges, or can be utilized for efficient infrared detection, particularly if the semiconductor material of layers 16 and/or 18 comprises germanium in addition to, or instead of silicon. FIG. 4 shows a fragment 100 comprising an optoelectronic device 101 illustrating another aspect of the invention. Fragment 100 includes a semiconductor substrate 102 lightly doped with a first type of dopant. The lightly-doped semiconductor substrate comprises a body region of the optoelectronic device, with such body region being diagrammatically illustrated as extending generally around the location labeled 104. Substrate 102 can comprise any suitable semiconductor material, and in particular aspects will comprise, consist essentially of, or consist of lightly-doped silicon. The dopant utilized for the light doping of substrate 102 can be either n-type or p-type, and in typical applications will be p-type. Suitable p-type dopant which can be utilized is one or both of indium and boron. In particular aspects, a substantial entirety of the dopant within the body region will be both indium and boron, with the term “substantial entirety” indicating that the only dopants within the body region are indium and boron within the tolerances of a process utilized to form the body region. A dielectric material 106 is over the body region. Dielectric material 106 can, for example, comprise, consist essentially of, or consist of silicon dioxide. A gate stack 108 is over the dielectric material. Gate stack 108 comprises a semiconductor-enriched insulator 110 and a covering material 112 over the semiconductor-enriched insulator. Semiconductor-enriched insulator 110 will typically comprise a silicon-enriched insulator, and specifically will typically comprise one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. Covering material 112 will correspond to a material at least partially transparent to one or more wavelengths of light which are to be detected by the optoelectronic device. In particular aspects, device 101 is configured for detecting infrared radiation, and in such aspects covering material 112 can comprise, consist essentially of, or consist of one or both of indium tin oxide and silicon nitride (Si3N4). To the extent that the semiconductor-enriched material 110 comprises silicon-enriched silicon oxide or silicon-enriched silicon nitride, the material can be from about 1 atomic % enriched in silicon to about 20 atomic % enriched in silicon. A pair of heavily-doped regions 114 and 116 extend within substrate 102, and are operatively proximate the gate stack 108 and body region 104 of device 101 to enable the device to detect electromagnetic radiation. Heavily-doped regions 114 and 116 will be oppositely doped relative to the lightly-doped body region surrounding regions 114 and 116. Accordingly, if body region 104 comprises p-type doped semiconductor material, heavily-doped regions 114 and 116 will be n-type doped, and vice versa. In some aspects, regions 1.14 and 116 can be referred to as source/drain regions, in that regions 114 and 116, together with gate stack 108, form a type of transistor device. A pair of conductive pedestals 118 and 120 are provided to extend from regions 114 and 116, respectively, to allow interconnection of regions 114 and 116 to circuitry external of the shown device 101 (such circuitry is not shown). An insulating material 122 is provided around device 101 to electrically isolate device 101 from other circuitry (not shown) which may be adjacent device 101. Insulating material 122 can comprise any suitable material, or combination of materials, and in particular aspects will comprise, consist essentially of, or consist of silicon dioxide. Heavily-doped region 114 and body region 104 are shown to both be electrically connected to ground 130. Semiconductor-enriched layer 110 is electrically coupled with a first voltage 132, and heavily-doped region 116 is electrically coupled with a second voltage 134. Voltages 132 and 134 are different from ground, and generally will be different from one another. The various layers and materials of device 101 can be formed to any suitable thicknesses. Typically, dielectric layer 106 will have a thickness of from about 4 to about 5 nanometers, semiconductor-enriched insulator 110 will have a thickness of from about 10 to about 30 nanometers, and the light-transmissive overcoat 112 will have a thickness of greater than about 30 nanometers. Optoelectronic device 101 can be referred to as a phototransistor. The transistor action can enable device 101 to achieve a significantly higher gain than can photodiodes, although the response time for the phototransistor will typically be slower than the response time of photodiodes. In operation, infrared radiation 38 (i.e., radiation having a wavelength of from about 2 micrometers to about 7 micrometers) photo-ionizes indium centers and generates excess holes in the body region 104 of substrate 102. Such lowers the threshold of the phototransistor 101, and accordingly alters channel conductance. The change in the channel conductance can be detected through circuitry coupled to device 101 to indicate the presence of infrared radiation, and in particular aspects to quantitate the amount of infrared radiation. Referring next to FIG. 5, such illustrates an exemplary embodiment of a solar cell 200 configured in accordance with an aspect of the present invention. The solar cell is supported by a base 202. Such base can comprise any suitable material or combination of materials, including, for example, glass, polymer (such as plastic) or metal (such as, for example, steel). A first electrode 204 is over the base. The first electrode can comprise any suitable electrically conductive material, or combination of materials. In particular aspects, the first electrode will comprise, consist essentially of, or consist of one or both of silver and aluminum. A first layer 206 of semiconductor material is over the first electrode 204, and a second layer 208 of semiconductor material is over the first layer 206. The first layer 206 is heavily doped with a first dopant type, and the second layer 208 is lightly doped with the first dopant type. The layer 206 can comprise, consist essentially of, or consist of conductively-doped silicon, conductively-doped germanium, or conductively-doped silicon-germanium. Similarly, the second semiconductor layer 208 can comprise, consist essentially of, or consist of conductively-doped silicon, conductively-doped germanium, or conductively-doped silicon-germanium. The first dopant type can be either n-type or p-type. In the exemplary embodiment, the first dopant type is p-type. A layer 210 of semiconductor-enriched insulator is over the second layer 208 of semiconductor material. The semiconductor-enriched insulator can be a silicon-enriched insulator, and in particular aspects can comprise, consist essentially of, or consist of one or both of silicon-enriched silicon oxide and silicon-enriched silicon nitride. If the silicon-enriched insulator corresponds to silicon-enriched silicon nitride, such can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon, with the excess silicon being measured relative to Si3N4. If the silicon-enriched insulator corresponds to silicon-enriched silicon oxide, such can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon, with the excess silicon being measured relative to SiO2. The layer 210 can function as a tunnel medium during operation of the solar cell, and preferably has a thickness of from about 1 nanometer to about 100 nanometers. The layer 210 also acts as comprising carrier generation centers wherein electron-hole pairs are created. Additionally, the layer 210 can passivate the silicon surface to reduce recombination of high energy photo-generated electron-hole pairs near the interface of materials 208 and 210, which can enhance energy efficiency of the solar cell 200. An antireflective material 212 is provided over layer 210. Layer 212 can have compositional aspects in common with semiconductor-enriched layer 210. As discussed previously, a semiconductor-enriched layer will typically comprise a matrix phase and an excess semiconductor phase. For instance, if layer 210 corresponds to silicon-enriched silicon nitride, it will typically comprise a phase of Si3N4, defining a matrix, and a phase of excess silicon within the matrix. Layer 212 can correspond to a composition having the same matrix as layer 210. Accordingly, if layer 210 corresponds to silicon-enriched silicon nitride, layer 212 can comprise silicon nitride, and in particular aspects will consist essentially of, or consist of silicon nitride. The layer 212 can serve as an efficient transmitter of incident solar radiation. In some aspects, layers 210 and 212 can both comprise silicon-enriched silicon nitride, with layer 212 having less silicon enrichment than layer 210. For instance, layer 210 can correspond to silicon-enriched silicon nitride having a refractory index of from about 2.5 to about 3, and layer 212 can correspond to a silicon-nitride-containing material having a refractive index of from about 2.0 to about 2.1. In the shown aspect of the invention, layer 212 is patterned to have openings extending therethrough to the underlying layer 210. Accordingly, layer 212 is shown to be in direct physical contact with various segments 209 of layer 210, and to not be indirect physical contact with other segments 211 of layer 210. The segments 211 can be considered to define bottom peripheries of the openings extending through layer 212. Fingers (or stripes) of top electrode, such as 216 and 218 make direct contact to segments 211 of layer 210. A second antireflective material 214 is provided over layer 212. Antireflective material 214 can comprise, for example, indium tin oxide, or any other suitable antireflective material, and can be omitted in some aspects of the invention. Second electrodes 216 and 218 are provided over semiconductor-enriched insulator 210 and in direct physical contact with segments 211 of the semiconductor-enriched insulator. The second electrodes can comprise the same composition as first electrode 204, or can comprise different compositions. In particular aspects, the first and second electrodes comprise one or both of silver and aluminum. The shown second electrodes have been patterned into a pair of spaced blocks. Actually, the second electrodes would typically extend into and out of the plane of the shown cross-sectional view so that the electrodes would be stripes (or strips) along an upper surface of construction 200. Gaps 226, 228 and 230 are between the spaced second electrodes. The gaps correspond to windows over segments of the semiconductor-enriched insulator 210. Such windows permit electromagnetic radiation to reach the segments of the semiconductor-enriched insulator within the windows. The electromagnetic radiation is diagrammatically illustrated as waves 250 in the diagram of FIG. 5. In the shown aspect of the invention, a plurality of second electrodes are spaced over a single continuous first electrode 204. It is to be understood that the invention encompasses other aspects (not shown) in which multiple first electrodes are provided, as well as aspects in which only a single second electrode is utilized. Further, the shown aspect comprising a plurality of second electrodes can correspond to an aspect in which the electrodes appear to be separated in the cross-sectional view of FIG. 5, but join to one another at a location which is not visible in the view of FIG. 5 so that the apparent plurality of second electrodes is actually a single second electrode which has been split into the shown plurality of stripes. Circuitry 240 is provided between first electrode 204, and second electrodes 216 and 218. The circuitry includes a device 452 configured to be powered by an electric field gradient generated between the first electrode and the second electrodes. The thin layer of semiconductor-enriched insulator 210 can be deposited in the same process as the antireflective coating 212. Advantageously, the processing utilized to form the solar cell 200 of FIG. 5 can be accomplished with a series of blanket deposition steps, and a single photolithography step for top electrode stripe formation. In operation, a depletion layer (diagrammatically illustrated by dashed-line 260) is generated within second semiconductor layer 208. Electromagnetic radiation generates electron-hole pairs within the silicon-enriched insulator region. Electrons can be separated from holes both within the silicon-enriched insulator region and within the depletion layer. The electrons migrate toward either the first electrode or the second electrodes, depending on the built-in potential on the respective electrodes. In an exemplary application, the electrons tunnel through the semiconductor-enriched insulator 210 and get collected by the top electrode stripes 216 and 218 when the semiconductor layer 208 is of p-type doped silicon (typically lightly-doped). A thin inversion layer is formed at the silicon/semiconductor-enriched insulator interface (i.e., the interface between layers 208 and 210) which can significantly reduce surface recombination. Holes are collected by the opposite electrode to that which collects electrons, and would be collected by the bottom electrode in the exemplary application in which electrons are collected by the top electrodes. The electric field gradient generated by the separation of the electrons and holes can be utilized to power electrical devices. FIG. 6 illustrates a solar cell 300 illustrating another aspect of the present invention. In referring to solar cell 300, similar numbering will be used as was utilized above in describing solar cell 200, where appropriate. Solar cell 300 comprises the base 202, first electrode 204, first layer of semiconductor material 206, second layer of semiconductor material 208, second electrodes 216 and 218, and circuitry 240 described previously. Construction 300 also comprises the windows 226, 228 and 230 extending between the second electrodes 216 and 218. Construction 300 differs from the construction 200 of FIG. 5 in that construction 300 comprises a very thin dielectric material 302 in direct physical contact with the second layer 208 of semiconductor material, and comprises semiconductor-enriched insulator 304 over the dielectric material. As discussed above, layers 206 and 208 can be either n-type doped or p-type doped. In applications in which layers 206 and 208 are p-type doped, dielectric material 302 can comprise, consist essentially of, or consist of silicon dioxide (SiO2); and in applications in which layers 206 and 208 are n-type doped, dielectric material 302 can comprise, consist essentially of, or consist of aluminum oxide (Al2O3). In the shown aspect of the invention, dielectric material 302 is in direct physical contact with both semiconductor-enriched insulator 304 and second layer 208 of semiconductor material. Further, second electrodes 216 extend through openings in semiconductor-enriched layer 304 to physically contact an upper surface of dielectric material 302. The semiconductor-enriched insulator 304 can comprise silicon-enriched insulator. In particular aspects, the semiconductor-enriched insulator 304 will comprise, consist essentially of, or consist of one or both of silicon-enriched silicon nitride and silicon-enriched silicon oxide. The solar cells of FIGS. 5 and 6 are amenable to low-temperature processing (i.e., can be formed utilizing processing from about room temperature to about 300° C.) which can provide higher efficiency and cost reduction relative to high-temperature processes. The semiconductor material of layers 206 and 208 can comprise, for example, single crystal or polycrystalline silicon. The heavily-doped interface layer 206 can reduce series contact resistance and enhance light absorption. The modification of the solar cell 300 of FIG. 6 relative to solar cell 200 of FIG. 5 creates a thin interface layer of dielectric material (which can be aluminum oxide or silicon dioxide in exemplary aspects of the invention) to reduce surface recombination and to enhance collection and thereby also enhance solar cell efficiency. A strong inversion layer is created in n-type silicon of layer 208 due to fixed negative charges in an aluminum layer 302. Similarly, fixed positive charges in silicon dioxide can create a strong inversion layer in p-type doped semiconductor material 208 to improve cell efficiency. It is noted that for the structures of FIGS. 5 and 6, cell efficiency can be possibly further improved by selecting a dual layer substrate of silicon/silicon-germanium (not shown) for layer 208. Such can enable the band gap in layer 208 to be varied from about 0.8 electron volts to about 1.1 electron volts, which may improve absorption efficiency of the electromagnetic radiation spectrum. Another exemplary solar cell is illustrated as cell 400 in FIG. 7. Cell 400 comprises a base layer 402 which can comprise any suitable material or combination of materials, similar to the base layer 202 described previously. Solar cell 400 comprises a first electrode 404 supported by the base layer. First electrode 404 can comprise any suitable electrically conductive composition or combination of compositions, and in particular aspects will comprise, consist essentially of, or consist of one or both of aluminum and silver. A textured buffer layer 406 is over the first electrode. Textured buffer layer 406 can, for example, comprise, consist essentially of, or consist of a relatively transparent conductive oxide, such as, for example, zinc oxide. A first layer 408 of semiconductor material is over textured buffered layer 406, a second layer 410 of semiconductor material is over first layer 408, and a third layer 412 of semiconductor material is over second layer 410. First layer 408 is heavily-doped with either p-type dopant or n-type dopant, and can comprise, consist essentially of, or consist of doped silicon or doped silicon-germanium. Layers 410 and 412 can be essentially undoped with conductivity-enhancing dopant. In particular aspects, one of layers 410 and 412 comprises consists essentially of, or consists of, silicon without any substantial concentration of germanium (i.e., silicon with less than 0.5 atomic percent germanium, and frequently with no detectable germanium), and the other comprises silicon-germanium. In particular aspects, one of layers 410 and 412 consists essentially of, or consists of silicon and the other consists essentially of or consists of silicon-germanium. The silicon and/or germanium of layers 408, 410 and 412 can be amorphous in particular aspects of the invention. The layers comprising silicon in combination with germanium can comprise any suitable concentration of germanium. In particular aspects such layers will comprise from 1 atomic % germanium to 99 atomic % germanium; and, in some aspects, the layers will comprise from about 5 atomic % germanium to about 50 atomic % germanium. Layer 408 is shown in direct physical contact with layer 406, and layer 406 is shown in direct physical contact with layer 404. Although the illustrated solar cell 400 comprises three semiconductor layers 408, 410 and 412, it is to be understood that the invention encompasses other solar cell devices comprising more than three semiconductor layers or less than three semiconductor layers. For instance, the invention encompasses aspects in which one of the layers 410 and 412 is eliminated, and the remaining layer consists essentially of, or consists of either amorphous silicon or amorphous silicon-germanium. A semiconductor-enriched insulator layer 414 is over the third layer 412 of semiconductor material, and is shown in direct physical contact with an upper surface of layer 412. Semiconductor-enriched insulator layer 414 can comprise any suitable semiconductor-enriched composition, and in particular aspects will comprise, consist essentially of, or consist of one or both of silicon-enriched silicon nitride and silicon-enriched silicon oxide. An exemplary silicon-enriched silicon nitride can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon, relative to Si3N4; and an exemplary silicon-enriched silicon oxide can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon relative to SiO2. An antireflective material 416 is provided over layer 414, and in the shown aspect of the invention is in direct physical contact with an upper surface of layer 414. Antireflective material 416 can comprise any suitable composition, and in particular aspects will comprise, consist essentially of, or consist of indium tin oxide. Second electrodes 418 and 420 are over antireflective material 416, and in the shown aspect of the invention are in direct physical contact with an upper surface of antireflective material 416. Although two electrodes are shown, it is to be understood that the invention encompasses aspects utilizing more than two electrodes or utilizing only a single electrode. Further, it is to be understood that the shown two electrodes could join to one another at a location outside of the shown cross-sectional view so that electrodes 418 and 420 are portions of a common electrode. In the shown aspect, electrodes 418 and 420 are shown electrically connected to one another to form a common second electrode 405. Electrodes 418 and 420 can comprise any suitable composition, and in particular aspects will comprise, consist essentially, or consist of one or both of silver and aluminum. Electrodes 418 and 420 are over segments 422 and 424, respectively, of semiconductor-enriched insulator 414. The electrodes are spaced from one another to form gaps 430, 432 and 434. Segments of semiconductor-enriched insulator 414 are beneath such gaps, and are labeled as 436, 438 and 440. Gaps 430, 432 and 434 can be considered windows which allow one or more particular wavelengths of electromagnetic radiation to reach the segments 436, 438 and 440 of semiconductor-enriched insulator 414. The particular wavelengths of electromagnetic radiation which reach the semiconductor-enriched material 414 are wavelengths which can penetrate materials above semiconductor-enriched insulator 414 within the windows. In the shown aspect, such would be wavelengths which can penetrate antireflective material 416. In some aspects, the segments 422 and 424 blocked by second electrodes and 418 and 420 can be considered first segments, and the segments 436, 438 and 440 within the windows can be considered second segments of the semiconductor-enriched insulator. In operation, electromagnetic radiation 450 generates electron-hole pairs through interaction with semiconductor-enriched material 414, as well as semiconductor materials 412 and 410. Such electron-hole pairs are separated by the electric field gradient of a depletion layer below 414 (not shown). Electrons and holes are subsequently drifted and collected at the top and bottom electrode 405 and 404, respectively, providing power to external circuitry (with such external circuitry being represented by block 452 in the diagram of FIG. 7). The textured buffer layer 406 of solar cell 400 can enhance the efficiency of light trapping by the solar cell. Typical thicknesses for layers 408, 410 and 412 are from about 0.1 micron to about 1 micron, and the relative thicknesses of the layers to one another can be anything suitable, including the exemplary shown relative thicknesses or other relative thicknesses. All of the processing steps utilized to form the structure of FIG. 7 can advantageously be performed in a temperature range of from room temperature to about 250° C., which can be advantageous for achieving high efficiency and low cost of a fabrication process. Another exemplary solar cell is shown in FIG. 8 as a solar cell 500. Such solar cell is supported over a base 502 which can have a similar composition to the base 402 discussed above with reference to FIG. 7. The solar cell 500 comprises a first electrode 504 over base 502, and comprises a textured buffer layer 506 over the first electrode and shown in direct physical contact with the first electrode. Textured buffer layer 506 can comprise the same compositions discussed above for textured buffer layer 406 of the FIG. 7 construction. The solar cell 500 also includes a first layer 508 of semiconductor material over the textured buffer layer, and shown in direct physical contact with the textured buffer layer. Layer 508 can comprise, consist essentially of or consist of heavily-doped semiconductor material, such as, for example, heavily-doped silicon, heavily-doped germanium, or heavily-doped silicon-germanium. The heavily-doped semiconductor material can be in any suitable form, such as, for example, amorphous form. The heavily-doped material can be either n-type doped or p-type doped, and will typically be n-type doped. Three light-detecting regions 510, 512 and 514 are provided over first semiconductor layer 508. Each of the light-detecting regions can be configured to have a different composition than the others of the light-detecting regions so that the specific light-detecting regions are configured to detect different wavelengths of light relative to one another. For instance, one of the light-detecting regions can be configured to detect blue light, another can be configured to detect green light, and another can be configured to detect red light and/or infrared light. It can be desired that the light-detecting regions configured to detect shorter wavelength light be above those configured to detect longer wavelength light, in that shorter wavelength light will generally not penetrate as well into a substrate (i.e., will generally not penetrate as deeply into a substrate) as will longer wavelength light. Although only three light-detecting regions are shown, it is to be understood that the invention encompasses aspects in which more than three light-detecting regions are utilized, and further it is to be understood that the invention can encompass aspects in which less than three light-detecting regions are utilized. The various light-detecting regions can all comprise one or both of amorphous silicon and amorphous germanium, and can differ from one another in the relative concentrations of silicon and germanium. For instance, one of the light-detecting regions can consist essentially of, or consist of, amorphous silicon without any substantial concentration of germanium, and can thus be configured to detect primarily blue light. Another of the light-detecting regions can comprise amorphous silicon-germanium (i.e., can comprise a mixture of amorphous silicon and amorphous germanium), with the germanium concentration being from about 1 atomic % to about 10 atomic % so that the light-detecting region is configured for detecting green light. Yet another of the light-detecting regions could comprise amorphous silicon-germanium, with the germanium concentration being from greater than about 10 atomic % to less than or equal to about 45 atomic % so that the light-detecting region is configured for detecting red and/or infrared light. In such aspects, it can be advantageous that the light-detecting region configured for detecting blue light be the uppermost region 514 of solar cell 500, the light-detecting region configured for detecting green light be the middle region 512 of the solar cell, and the light-detecting region configured for detecting red and/or infrared light be the lower-most region 510 of the solar cell. The light-detecting regions comprising silicon-germanium can further comprise a layer of amorphous silicon stacked with the silicon-germanium. In such cases, the layer of amorphous silicon can be either above the silicon-germanium composition in the stack, or below the silicon-germanium composition in the stack. Also, it is to be understood that a single light-detecting region can comprise multiple layers of amorphous silicon and silicon-germanium stacked with one another. In the shown aspect of the invention, light-detecting region 510 is separated from light-detecting region 512 by a first stack 516 of semiconductor materials 518 and 520; and second light-detecting region 512 is separated from third light-detecting region 514 by a second stack 522 of semiconductor materials 524 and 526. The first and second stacks of semiconductor materials can comprise an n-type doped semiconductor material in combination with a p-type doped semiconductor material. Specifically, the semiconductor materials 518 and 524 can be p-type doped semiconductor materials (such as, for example, p-type doped silicon), and the layers 520 and 526 can correspond to n-type doped semiconductor material (such as n-type doped silicon). In other words, layers 518, 520, 524 and 526 can comprise, consist essentially of, or consist of conductively-doped silicon. The silicon can be in any suitable form, including, for example, amorphous form. It can be advantageous that stacks 516 and 522 be configured to have a layer of n-type doped semiconductor material in combination with a layer of p-type doped semiconductor material, and it can be further advantageous that the layer of p-type doped semiconductor material be beneath the layer of n-type doped semiconductor material within the individual stacks. The stacks 516 and 522 provide depletion layers to separate electron-hole pairs generated from radiation absorbed in regions 510 and 512, respectively. Alternatively, the stacks 516 and 522 could be replaced by appropriate thicknesses of one or more silicon-rich insulators, similar to layer 530. A layer of semiconductor-enriched insulator 530 is provided over the third light-detecting region 514, and in the shown aspect of the invention is in direct physical contact with an uppermost surface of the light-detecting region 514. Semiconductor-enriched insulator 530 can comprise, consist essentially of, or consist of silicon-enriched semiconductor in particular aspects of the invention. Specifically, the semiconductor-enriched insulator 530 can comprise, consist essentially of, or consist of one or both of silicon nitride and silicon oxide in particular aspects of the invention. If the semiconductor-enriched insulator corresponds to silicon-enriched silicon nitride, such can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon, relative to Si3N4; and if the semiconductor-enriched insulator corresponds to silicon-enriched silicon oxide, such can comprise from about 1 atomic % excess silicon to about 20 atomic % excess silicon relative to SiO2. An antireflective material 540 is provided over semiconductor-enriched insulator 530. Antireflective material 540 can correspond to any suitable material, and in particular aspects will comprise, consist essentially of, or consist of indium tin oxide. Second electrodes 542 and 544 are provided over the antireflective material 540. The second electrodes are spaced from one another, and can correspond to either a pair of entirely separate electrodes, or to portions of a common electrode which joins at a location outside of the shown cross-section of FIG. 8. In the shown aspect, electrodes 542 and 544 are shown electrically coupled with one another to form a common top electrode 505. The spaced electrodes 542 and 544 have gaps 546, 548 and 550 beside them. Such gaps define windows where one or more particular wavelengths of electromagnetic radiation can reach underlying portions of semiconductor-enriched insulator 530. Specifically, second electrodes 542 and 544 block some segments of semiconductor-enriched insulator 530, while other segments of the semiconductor-enriched insulator are exposed within the gaps to radiation passing through the gaps. The electromagnetic radiation within the gaps is diagrammatically illustrated by waves 552. In operation, the electromagnetic radiation passing into solar cell 550 generates electron-hole pairs in regions 530, 514, 512 and 510. Depletion layers below 530 and regions 522 and 516 separate electrons and holes from one another. Electrons and holes drifted by the electric field gradients collect at the opposite electrodes 505 and 504, respectively, providing power to external circuitry (shown diagrammatically in FIG. 8 as circuitry 560). The solar cell of FIG. 8 advantageously can generate electricity from multiple components of a spectrum of white light (such as, for example, sunlight). The light-detecting regions 510, 512 and 514 of the solar cell 500, as well as the intervening stacks 516 and 522, can all advantageously be deposited in the same process tool, and in some aspects the semiconductor-enriched material 530 can also be deposited in the same process tool. In particular aspects of the invention, all of the processing steps utilized to form the solar cell 500 of FIG. 8 can be conducted within a temperature range of from about room temperature to about 250° C. In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.	H	67H01	185H01L	3102	32
11858147	US20080009101A1-20080110	COMPRESSIBLE FILMS SURROUNDING SOLDER CONNECTORS	ACCEPTED	20071226	20080110	[]	H01L2100	["H01L2100"]	7566649	20070920	20090728	438	612000	60221.0	THAI	LUAN	[{"inventor_name_last": "Bernier", "inventor_name_first": "William", "inventor_city": "Endwell", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Cheng", "inventor_name_first": "Tien-Jen", "inventor_city": "Bedford", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Cole", "inventor_name_first": "Marie", "inventor_city": "Wappingers Falls", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Eichstadt", "inventor_name_first": "David", "inventor_city": "Chicago", "inventor_state": "IL", "inventor_country": "US"}, {"inventor_name_last": "Farooq", "inventor_name_first": "Mukta", "inventor_city": "Hopewell Junction", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Fitzsimmons", "inventor_name_first": "John", "inventor_city": "Poughkeepsie", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Goldmann", "inventor_name_first": "Lewis", "inventor_city": "Bedford", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Knickerbocker", "inventor_name_first": "John", "inventor_city": "Wappingers Falls", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Lopez", "inventor_name_first": "Tasha", "inventor_city": "Santa Ana", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Welsh", "inventor_name_first": "David", "inventor_city": "Salt point", "inventor_state": "NY", "inventor_country": "US"}]	Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.	1. A method of forming an integrated circuit structure, said method comprising: forming solder connectors on a device; surrounding sides of said solder connectors with a compressible film; connecting said device to a carrier, wherein said solder connectors electrically connect said device to said carrier; and filling gaps between said carrier and said device with an insulating material. 2. The method in claim 1, further comprising melting said solder connectors, wherein said compressible film is stable above the melting point of said solder connectors. 3. The method in claim 1, further comprising melting said solder connectors, wherein said compressible film has sufficient compressibility to accommodate expansion of said solder connections when said solder connections are melted without damaging said insulating material. 4. The method in claim 1, wherein said process of surrounding sides of said solder connectors with said compressible film forms said compressible film into a pattern between said carrier and said device. 5. The method in claim 4, wherein said pattern has channels between said device and said carrier, wherein said channels are filled with said insulating material. 6. The method in claim 4, wherein said pattern comprises diagonal stripes of said compressible film. 7. The method in claim 1, wherein said process of surrounding sides of said solder connectors with said compressible film positions said compressible film partially up sides of said solder connections. 8. A method of forming an integrated circuit structure, said method comprising: forming lead-free connectors on a device; surrounding sides of said lead-free connectors with a compressible film; connecting said device to a carrier, wherein said lead-free connectors electrically connect said device to said carrier; and filling gaps between said carrier and said device with an insulating underfill. 9. The method in claim 8, further comprising melting said solder connectors, wherein said compressible film is stable above the melting point of said solder connectors. 10. The method in claim 8, further comprising melting said lead-free connectors, wherein said compressible film has sufficient compressibility to accommodate expansion of said lead-free connections when said lead-free connections are melted without damaging said underfill. 11. The method in claim 8, wherein said process of surrounding sides of said lead-free connectors with said compressible film forms said compressible film into a pattern between said carrier and said device. 12. The method in claim 11, wherein said pattern has channels between said device and said carrier, wherein said channels are filled with said underfill. 13. The method in claim 11, wherein said pattern comprises diagonal stripes of said compressible film. 14. The method in claim 8, wherein said process of surrounding sides of said solder connectors with said compressible film positions said compressible film partially up sides of said solder connections.	<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The invention generally relates to connectors between devices and carriers and more particularly to connectors that are surrounded by compressible material that prevents delamination of the carrier from the device. 2. Description of the Related Art Devices such as integrated circuit chips are often connected to carriers that include wiring connections to the integrated circuit chips. The integrated circuit chips can be connected to the carriers using a conductive lead solder. These lead connectors are generally formed as balls on the carrier and/or the chip. The carrier and chip are generally heated to cause the solder to melt, after which the structures are allowed to cool so the solder solidifies. This process is described as a “reflow” process and it bonds the lead solder connection to both the carrier and the chip. Often, an insulating underfill material is used to fill in the remaining space between the device and the carrier. This underfill helps increase fatigue life of solder interconnections by absorbing some of the stress that results from the difference in the coefficients of thermal expansion of semiconductor devices and ceramic or organic carriers. Though lead-containing solders have been used for decades and exhibit high yield and reliability due to their extensive utilization, worldwide legislation and environmental concerns have led to considerable interest in the development and use of lead-free solders. One such lead-free solder is SnAgCu, commonly called SAC, which is one of the leading alloys being considered as an alternative to solder connections containing lead. The SAC alloy (available with various levels of Ag and Cu, but typically ranging from 3-4% Ag and 0.5-1% Cu) has numerous advantages including a relatively low melting point, good fatigue life, and compatibility with common lead-free solders. Consequently, SAC is one of the leading candidates for lead-free interconnects between semiconductor devices and chip carriers. One of the drawbacks in using lead-free solders is that their major constituents tend to experience a relatively large (e.g., 3%) volume expansion upon reflow. Unfortunately, the volume expansion of lead-free solders can force the underfill away from the solder connection, which prevents the underfill from being able to maintain support of the solder when the solder cools back to its original volume. As a result, this large volume expansion upon reflow prevents some lead-free solders from being used on ceramic or organic carriers that require underfill.	<SOH> SUMMARY OF THE INVENTION <EOH>Disclosed is a method of forming an integrated circuit structure, where the method forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill. The connectors can be reflowed by heating to melting, and then cooling. Some features of the embodiments herein are that the compressible film has a melting point above the lead-free connectors and the compressible film has sufficient compressibility to accommodate expansion of the lead-free connections when the lead-free connections are melted without damaging the underfill. Also, the process of surrounding the lead-free connectors with the compressible film can form the compressible film into a pattern between the carrier and the device where the compressible film is positioned around less than all the lead-free connections. This pattern can, for example, form channels between the device and the carrier, wherein the channels are filled with the underfill, or the pattern can comprise diagonal stripes of the compressible film. The resulting structure has the device connected to the carrier by lead-free connectors with the compressible film surrounding (or partially surrounding) the lead-free connectors, and the insulating underfill filling gaps between the carrier and the device. These, and other, aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating embodiments of the present invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. application Ser. No. 10/711,076 filed Aug. 20, 2004, the complete disclosure of which, in its entirety, is herein incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The invention generally relates to connectors between devices and carriers and more particularly to connectors that are surrounded by compressible material that prevents delamination of the carrier from the device. 2. Description of the Related Art Devices such as integrated circuit chips are often connected to carriers that include wiring connections to the integrated circuit chips. The integrated circuit chips can be connected to the carriers using a conductive lead solder. These lead connectors are generally formed as balls on the carrier and/or the chip. The carrier and chip are generally heated to cause the solder to melt, after which the structures are allowed to cool so the solder solidifies. This process is described as a “reflow” process and it bonds the lead solder connection to both the carrier and the chip. Often, an insulating underfill material is used to fill in the remaining space between the device and the carrier. This underfill helps increase fatigue life of solder interconnections by absorbing some of the stress that results from the difference in the coefficients of thermal expansion of semiconductor devices and ceramic or organic carriers. Though lead-containing solders have been used for decades and exhibit high yield and reliability due to their extensive utilization, worldwide legislation and environmental concerns have led to considerable interest in the development and use of lead-free solders. One such lead-free solder is SnAgCu, commonly called SAC, which is one of the leading alloys being considered as an alternative to solder connections containing lead. The SAC alloy (available with various levels of Ag and Cu, but typically ranging from 3-4% Ag and 0.5-1% Cu) has numerous advantages including a relatively low melting point, good fatigue life, and compatibility with common lead-free solders. Consequently, SAC is one of the leading candidates for lead-free interconnects between semiconductor devices and chip carriers. One of the drawbacks in using lead-free solders is that their major constituents tend to experience a relatively large (e.g., 3%) volume expansion upon reflow. Unfortunately, the volume expansion of lead-free solders can force the underfill away from the solder connection, which prevents the underfill from being able to maintain support of the solder when the solder cools back to its original volume. As a result, this large volume expansion upon reflow prevents some lead-free solders from being used on ceramic or organic carriers that require underfill. SUMMARY OF THE INVENTION Disclosed is a method of forming an integrated circuit structure, where the method forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill. The connectors can be reflowed by heating to melting, and then cooling. Some features of the embodiments herein are that the compressible film has a melting point above the lead-free connectors and the compressible film has sufficient compressibility to accommodate expansion of the lead-free connections when the lead-free connections are melted without damaging the underfill. Also, the process of surrounding the lead-free connectors with the compressible film can form the compressible film into a pattern between the carrier and the device where the compressible film is positioned around less than all the lead-free connections. This pattern can, for example, form channels between the device and the carrier, wherein the channels are filled with the underfill, or the pattern can comprise diagonal stripes of the compressible film. The resulting structure has the device connected to the carrier by lead-free connectors with the compressible film surrounding (or partially surrounding) the lead-free connectors, and the insulating underfill filling gaps between the carrier and the device. These, and other, aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating embodiments of the present invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood from the following detailed description with reference to the drawings, in which: FIG. 1 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 2 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 3 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 4 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 5 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 6 is a schematic cross-sectional diagram of a partially completed device and carrier structure; FIG. 7 is a schematic cross-sectional diagram of a connection structure; FIG. 8 is a schematic top-view diagram of one pattern of compressible material; FIG. 9 is a schematic top-view diagram of one pattern of compressible material; FIG. 10 is a schematic top-view diagram of one pattern of compressible material; FIG. 11 is a graph showing the relationship between the reduction from maximum pressure verses the compressive modulus for different thicknesses of compressible material; and FIG. 12 is a flow diagram illustrating one embodiment. DETAILED DESCRIPTION The present invention and the various features and advantageous details thereof are explained more fully with reference to the nonlimiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the present invention. The examples used herein are intended merely to facilitate an understanding of ways in which the invention may be practiced and to further enable those of skill in the art to practice the invention. Accordingly, the examples should not be construed as limiting the scope of the invention. The various embodiments herein use a compressible film around the device to carrier connection to provide a volume into which the lead-free solder (e.g., SAC alloy) can expand (before it reaches the underfill), thereby allowing the underfill to support the “bumps” even after numerous thermal excursions. The result is that lead-free solders can be used with all their advantages, without incurring the negative impact of lead-free solder volume expansion. More specifically, as shown in FIG. 1, one embodiment forms lead-free connectors 12 on a device 10. Item 10 can comprise any type of device that is to be connected to any type of carrier. For example, item 10 could comprise an integrated circuit chip having functional devices therein. Alternatively, item 10 can represent the carrier, if the connectors 12 are formed on the carrier first. The connectors 12 are any type of electrically conductive connector that suffers from volume expansion upon reflow. For example, the connectors 12 can comprise a lead-free solder, such as the SAC alloy that is discussed above. As shown in FIG. 2, in this embodiment, a compressible material 20 is formed to surround sides of the connectors 12. In one example, the compressible material 20 can be deposited at the level shown in FIG. 2. Alternatively, additional compressible material can be deposited and the structure can be planarized down to the level shown in FIG. 2. One feature is that the top of the connector 12 is exposed such that it can form an electrical connection to the carrier when it is attached to the carrier. The compressible material 20 can be any compressible material, such as compressible silicone rubber, polyimide foam, or any other material that is thermally stable above the melting point of the connectors 12 (e.g., 260° C.) and has an expansion coefficient in the desired range for the expansion of each connector 12. One feature is that the compressible film 20 has sufficient compressibility to accommodate expansion of the connectors 12 when the connections are melted without damaging the underfill. In FIG. 3, a mask 30 is formed using photolithographic techniques and, in FIG. 4, the compressible material 20 is patterned. This patterning process can be any conventional material removal process, such as etching, laser processing, and other similar methodologies. It is also possible that a photosensitive or electron-beam-sensitive compressible material 20 could be used, which would avoid the need to use the mask 30. Some of the possible patterns that the compressible material 20 can be patterned into are shown in FIGS. 8-10, and are discussed in greater detail below. In FIGS. 1-4, the compressible material 20 is formed before the connectors 12 are reflowed into spheres. However, the compressible material 20 could be applied after the connectors 12 are reflowed into spheres, as shown in FIG. 5. Also note that FIG. 5 illustrates that in some embodiments, the compressible material 20 does not need to come up to the top of the connector 12. Instead, certain designs may see benefit from only using the compressible material 20 along a portion of the sides of the connectors 12. After the connectors 12 are surrounded with the compressible film 20, the device is connected to a carrier 60, as shown in FIG. 6. The connectors 12 electrically connect the device 10 to the carrier 60. Then, an insulating underfill 62 is deposited to fill the gap between the carrier 60 and the device 10. In the resulting structure, the device 10 is connected to the carrier 60 by connectors 12 with the compressible film 20 surrounding (or partially surrounding) the connectors 12, and the insulating underfill 62 filling gaps between the carrier 60 and the device 10. FIG. 7 illustrates one of the connectors 12, the surrounding compressible film 20 and a portion of the underfill 62 in cross-section. FIG. 7 illustrates that the connector 12 can expand when heated and how it may expand permanently after being heated (reflowed). Note that FIG. 7 is not drawn to scale. In FIG. 7, line 74 illustrates the size of the connector 12 before heating, line 70 represents the size of the connector 12 when it is in a liquid or molten state (while it is being heated), and line 72 represents the size of the connector 12 after a reflow process. The compressible material 20 compresses to accommodate the change in size of the connector 12, which avoids deforming the underfill 62. This allows the underfill 62 to remain connected to the compressible material 20, the device 10, and the carrier 60 regardless of the expansion of the connector 12. Further, the compressible material 20 will allow further accommodation of volume expansion during other downstream high temperature processes (card assembly, rework, etc.) as well. With the inventive use of the compressible material 20, the underfill 62 will be able to provide the structural coupling required between the device and carrier. As shown in FIG. 6, the compressible film 20 is patterned between the carrier 60 and the device 10. The patterns shown in FIG. 8-10 allow the underfill 62 to more easily fill all spaces between the carrier 60 and the device 10. Note that FIGS. 8-10 illustrate some exemplary patterns of the compressible material 20 and the invention is not strictly limited to these examples. In FIG. 8, the compressible material 20 forms a film around the ball or sphere shaped conductor connector 12. In FIG. 9, the compressible material 20 is patterned into squares or rectangles, thereby forming channels 90 through which the underfill 62 can be injected. This pattern can, for example, comprise diagonal stripes of the compressible film, as shown in FIG. 10. One feature of the pattern of the compressible material 20 is that it leaves sufficient room for the underfill material 62 to provide a good structural bond between the device 10 and the carrier 60. Note that while these examples show that all the connectors 12 have compressible film 20 thereon, in other embodiments, the compressible film 20 is positioned around less than all the connectors 12. The makeup of the compressible film 20 that is used will vary depending upon the amount of compression that is needed in a specific design. In addition, the thickness of the compressible material 20 will vary, again, depending upon the amount of compression required. FIG. 11 is a graph showing the relationship between the reduction from maximum pressure verses the compressive modulus for different thicknesses of different compressible materials. The left side of the graph illustrates the range of elastomers while the center of the graph illustrates the range of polyimides, polysulfone, nylon, etc. In addition, the curves represent different thicknesses of the compressible material (e.g., 5, 6, and 7 mil). These curves represent that, as the compressible material is made thinner, it must be softer to provide the same degree of pressure reduction. As mentioned above, the compressible material does not need to completely surround the sides of the connector 12. Covering only part of the ball height has significant advantages for flux removal and to facilitate underfill flow to narrow channels. However, pressure buildup will be greater as the entire connector ball 12 expands, but only a portion of its height can accommodate the extra volume. For example, if the compressible material comes up two-thirds of the ball height, the pressure would be 50% higher than if the compressed material covered the entire side of the connector 12. Thus, the specific material and thickness used will vary depending upon each design, as will the amount of the side of the connector that is covered. FIG. 12 shows an embodiment in flowchart form. In FIG. 12, item 120 of this embodiment forms connectors that may expand on a device. In item 122, this embodiment surrounds the connectors with a compressible film. Next, in item 124, this embodiment connects the device to a carrier (the connectors electrically connect the device to the carrier). In item 126, this embodiment fills the gaps between the carrier and the device with an insulating underfill. As shown above, various embodiments herein use a compressible film around the device to carrier connector to provide a volume into which the connector can expand (before it reaches the underfill), thereby allowing the underfill to support the device and carrier, even after numerous thermal excursions. The result is that lead-free solders (and other connector materials that suffer unwanted expansion upon heating) can be used with all their advantages, without incurring the negative impact of connector volume expansion. While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.	H	67H01	185H01L	21	00
11955235	US20080157203A1-20080703	SEMICONDUCTOR DEVICE HAVING EDMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME	ACCEPTED	20080619	20080703	[]	H01L2978	["H01L2978", "H01L21336"]	7851329	20071212	20101214	438	439000	96195.0	TRAN	LONG	[{"inventor_name_last": "Shin", "inventor_name_first": "Hyun-Soo", "inventor_city": "Chungcheongbuk-do", "inventor_state": "", "inventor_country": "KR"}]	A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.	1. An apparatus comprising: a source region and a drain region formed in a semiconductor substrate; a first gate insulating layer filling a trench formed in the semiconductor substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region; a second gate insulating layer formed over the semiconductor substrate between the first gate insulating layer and the source region; a gate electrode formed over the first and second gate insulating layers; and a doped drift region formed in the semiconductor substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. 2. The apparatus of claim 1, wherein the trench has a rounded shape. 3. The apparatus of claim 1, wherein the gate electrode covers a part of the first gate insulating layer and is separated from the drain region. 4. The apparatus of claim 1, wherein the doped drift region has a lower impurity concentration than the drain region. 5. The apparatus of claim 1, wherein the second gate insulating layer is thinner than the first gate insulating layer. 6. The apparatus of claim 1, wherein the substrate, source, gate and drain form an extended drain metal oxide semiconductor transistor. 7. An apparatus comprising: a source region and a drain region formed in a semiconductor substrate; a doped drift region formed in the semiconductor substrate between the source and drain regions, the doped drift region being separated from the source region and in contact with the drain region; a count doped region formed in the doped drift region; and a gate insulating layer and a gate electrode over the semiconductor substrate between the source and drain regions. 8. The apparatus of claim 7, wherein the gate electrode has a first sidewall near the source region and a second sidewall near the drain region, the second sidewall being separated from the drain region. 9. The apparatus of claim 7, wherein the doped drift region has a lower impurity concentration than the drain region. 10. The apparatus of claim 7, wherein the semiconductor substrate and the count doped region are doped with a first conductivity type impurity and the source region, the drain region, and the doped drift region are doped with a second conductivity type impurity. 11. A method comprising: forming a trench in a specific region of a semiconductor substrate; forming a first gate insulating layer to fill the trench; forming a doped drift region in the semiconductor substrate under the first gate insulating layer; forming a source region and a drain region in the semiconductor substrate at both sides of the first gate insulating layer, the source region being separated from the first gate insulating layer and the drain region being in contact with the doped drift region; forming a second gate insulating layer over the semiconductor substrate between the first gate insulating layer and the source region; and forming a gate electrode over the first and second gate insulating layers. 12. The method of claim 11, wherein the trench is formed in a rounded shape. 13. The method of claim 11, wherein the gate electrode is formed to cover only a portion of the first gate insulating layer which lies over the second gate insulating layer. 14. The method of claim 11, wherein the doped drift region is formed to have a lower impurity concentration than the drain region. 15. The method of claim 11, wherein the second gate insulating layer is thinner than the first gate insulating layer 16. A method comprising: forming a doped drift region doped with a second conductivity type impurity in a region of a semiconductor substrate doped with a first conductivity type impurity; forming a drain region in contact with the doped drift region and a source region separated from the doped drift region in the semiconductor substrate at both sides of the doped drift region; implanting first conductivity type impurity ions into the doped drift region to form a count doped region; and sequentially forming a gate insulating layer and a gate electrode over the semiconductor substrate between the source and drain regions, wherein the source and drain regions are doped with the second conductivity type impurity. 17. The method of claim 16, wherein the gate electrode is formed to have a first sidewall near the source region and a second sidewall near the drain region, the second sidewall being horizontally separated from the drain region. 18. The method of claim 16, wherein the doped drift region is formed to have a lower impurity concentration than the drain region. 19. The method of claim 16, wherein the implantation of the first conductivity type impurity ions to form the count doped region is performed by implanting the first conductivity type impurity ions with an energy of about 1 KeV to about 2000 KeV. 20. The method of claim 16, wherein the implantation of the first conductivity type impurity ions to form the count doped region is performed by implanting the first conductivity type impurity ions with an ion dose between about 1011 to about 1016 atoms/cm2 and an ion injection angle between about 0° to 60°.	<SOH> BACKGROUND <EOH>Embodiments relate to a semiconductor device and a method for manufacturing the same, and more particularly, to an Extended Drain Metal Oxide Semiconductor (EDMOS) transistor device and method of manufacture. One of the components a semiconductor device may require is a transistor that controls high voltages. An EDMOS transistor may be used for this purpose. The EDMOS transistor has a relatively thick oxide layer between the gate and drain, for improving the insulating characteristics between the gate and drain to which the high voltage is applied. A related EDMOS transistor is explained with reference to FIG. 1 . FIG. 1 is a cross-sectional view illustrating a method for forming a related EDMOS transistor. As shown in FIG. 1 , a first gate oxide layer 2 is formed over a specific region of a semiconductor substrate 1 . Specifically, the first gate oxide layer 2 is formed in the following manner. First, a nitride layer pattern having an opening is formed over the semiconductor substrate 1 . The opening exposes the specific region of the semiconductor substrate 1 . A thermal oxidation process is performed on the semiconductor substrate 1 including the nitride layer pattern to form the first gate oxide layer 2 . The nitride layer pattern is then removed. A doped drift region 3 is formed in the semiconductor substrate 1 under the first gate oxide layer 2 . A source region 4 s and a drain region 4 d are formed in the semiconductor substrate 1 at both sides of the first gate oxide layer 2 . The source region 4 s is formed to be horizontally separated from the first gate oxide layer 2 . The drain region 4 d is formed to be adjacent to the first gate oxide layer 2 . The doped drift region 3 and the drain region 4 d are in contact with each other. The doped drift region 3 and the source and drain regions 4 s and 4 d are doped with the same type of impurities. A second gate oxide layer 5 is formed over the semiconductor substrate 1 between the source region 4 s and the first gate oxide layer 2 . The second gate oxide layer 5 is formed to be thinner than the first gate oxide layer 2 . A gate electrode 6 is formed over the first and second gate oxide layers 2 and 5 . The gate electrode 6 is formed to cover a part of the first gate oxide layer 2 . Accordingly, the gate electrode 6 and the drain region 4 d are separated from each other. In the EDMOS transistor formed according to the above method, the relatively thick first gate oxide layer 2 provides sufficient insulation between the gate electrode 6 and the drain region 4 d even if a high voltage is applied to the drain region 4 d . The doped drift region 3 is formed with a lower impurity concentration than the drain region 4 d . This improves the breakdown voltage between the source region 4 s and the drain region 4 d. However, the first gate oxide layer 2 in the related EDMOS transistor is formed through a LOCOS process using a nitride layer pattern. This causes a bird's beak phenomenon at the perimeter of the first gate oxide layer 2 , which makes it difficult to reduce the planar area of the EDMOS transistor. However, reducing the planar area of the EDMOS transistor allows the integration density of semiconductor devices to increase.	<SOH> SUMMARY <EOH>Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which are optimized for high integration. Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which can reduce the planar area of the EDMOS transistor. Embodiments relate to a semiconductor device which may include a source region and a drain region formed separately in a semiconductor substrate. A first gate insulating layer may fill a trench formed in the semiconductor substrate between the source and drain regions. The first gate insulating layer may be adjacent to the drain region and separated from the source region. A second gate insulating layer may be formed over the semiconductor substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer. A gate electrode may be formed over the first and second gate insulating layers. A doped drift region may be formed in the semiconductor substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. Embodiments relate to a semiconductor device which may include a source region and a drain region formed separately in a semiconductor substrate. A doped drift region may be formed in the semiconductor substrate between the source and drain regions. The doped drift region may be separated from the source region and in contact with the drain region. A count doped region may be formed in the doped drift region. A gate insulating layer and a gate electrode may be sequentially deposited over the semiconductor substrate between the source and drain regions. The semiconductor substrate and the count doped region may be doped with a first conductivity type impurity and the source region, the drain region, and the doped drift region may be doped with a second conductivity type impurity. In embodiments, the gate insulating layer or the count doped region may be formed to fill the trench between the gate electrode and the doped drift region. This allows a reduction in the planar area of the EDMOS transistor, thereby achieving more highly integrated semiconductor devices. Embodiments relate to a method for forming a semiconductor device which may include forming a trench in a specific region of a semiconductor substrate and forming a first gate insulating layer to fill the trench. In this aspect, a doped drift region is formed in the semiconductor substrate under the first gate insulating layer. A source region and a drain region are formed in the semiconductor substrate at both sides of the first gate insulating layer. The source region is separated from the first gate insulating layer and the drain region is in contact with the doped drift region. A second gate insulating layer may be formed over the semiconductor substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer. A gate electrode may then be over the first and second gate insulating layers. Embodiments relate to a method for forming a semiconductor device which may include forming a doped drift region doped with a second conductivity type impurity in a specific region of a semiconductor substrate doped with a first conductivity type impurity. A drain region may be formed in contact with the doped drift region and a source region separated from the doped drift region in the semiconductor substrate at both sides of the doped drift region. First conductivity type impurity ions may be implanted into the doped drift region to form a count doped region and a gate insulating layer and a gate electrode are then sequentially formed over the semiconductor substrate between the source and drain regions. The source and drain regions are doped with the second conductive impurity.	The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0137337, filed on Dec. 29, 2006, which is hereby incorporated by reference in its entirety. BACKGROUND Embodiments relate to a semiconductor device and a method for manufacturing the same, and more particularly, to an Extended Drain Metal Oxide Semiconductor (EDMOS) transistor device and method of manufacture. One of the components a semiconductor device may require is a transistor that controls high voltages. An EDMOS transistor may be used for this purpose. The EDMOS transistor has a relatively thick oxide layer between the gate and drain, for improving the insulating characteristics between the gate and drain to which the high voltage is applied. A related EDMOS transistor is explained with reference to FIG. 1. FIG. 1 is a cross-sectional view illustrating a method for forming a related EDMOS transistor. As shown in FIG. 1, a first gate oxide layer 2 is formed over a specific region of a semiconductor substrate 1. Specifically, the first gate oxide layer 2 is formed in the following manner. First, a nitride layer pattern having an opening is formed over the semiconductor substrate 1. The opening exposes the specific region of the semiconductor substrate 1. A thermal oxidation process is performed on the semiconductor substrate 1 including the nitride layer pattern to form the first gate oxide layer 2. The nitride layer pattern is then removed. A doped drift region 3 is formed in the semiconductor substrate 1 under the first gate oxide layer 2. A source region 4s and a drain region 4d are formed in the semiconductor substrate 1 at both sides of the first gate oxide layer 2. The source region 4s is formed to be horizontally separated from the first gate oxide layer 2. The drain region 4d is formed to be adjacent to the first gate oxide layer 2. The doped drift region 3 and the drain region 4d are in contact with each other. The doped drift region 3 and the source and drain regions 4s and 4d are doped with the same type of impurities. A second gate oxide layer 5 is formed over the semiconductor substrate 1 between the source region 4s and the first gate oxide layer 2. The second gate oxide layer 5 is formed to be thinner than the first gate oxide layer 2. A gate electrode 6 is formed over the first and second gate oxide layers 2 and 5. The gate electrode 6 is formed to cover a part of the first gate oxide layer 2. Accordingly, the gate electrode 6 and the drain region 4d are separated from each other. In the EDMOS transistor formed according to the above method, the relatively thick first gate oxide layer 2 provides sufficient insulation between the gate electrode 6 and the drain region 4d even if a high voltage is applied to the drain region 4d. The doped drift region 3 is formed with a lower impurity concentration than the drain region 4d. This improves the breakdown voltage between the source region 4s and the drain region 4d. However, the first gate oxide layer 2 in the related EDMOS transistor is formed through a LOCOS process using a nitride layer pattern. This causes a bird's beak phenomenon at the perimeter of the first gate oxide layer 2, which makes it difficult to reduce the planar area of the EDMOS transistor. However, reducing the planar area of the EDMOS transistor allows the integration density of semiconductor devices to increase. SUMMARY Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which are optimized for high integration. Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which can reduce the planar area of the EDMOS transistor. Embodiments relate to a semiconductor device which may include a source region and a drain region formed separately in a semiconductor substrate. A first gate insulating layer may fill a trench formed in the semiconductor substrate between the source and drain regions. The first gate insulating layer may be adjacent to the drain region and separated from the source region. A second gate insulating layer may be formed over the semiconductor substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer. A gate electrode may be formed over the first and second gate insulating layers. A doped drift region may be formed in the semiconductor substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. Embodiments relate to a semiconductor device which may include a source region and a drain region formed separately in a semiconductor substrate. A doped drift region may be formed in the semiconductor substrate between the source and drain regions. The doped drift region may be separated from the source region and in contact with the drain region. A count doped region may be formed in the doped drift region. A gate insulating layer and a gate electrode may be sequentially deposited over the semiconductor substrate between the source and drain regions. The semiconductor substrate and the count doped region may be doped with a first conductivity type impurity and the source region, the drain region, and the doped drift region may be doped with a second conductivity type impurity. In embodiments, the gate insulating layer or the count doped region may be formed to fill the trench between the gate electrode and the doped drift region. This allows a reduction in the planar area of the EDMOS transistor, thereby achieving more highly integrated semiconductor devices. Embodiments relate to a method for forming a semiconductor device which may include forming a trench in a specific region of a semiconductor substrate and forming a first gate insulating layer to fill the trench. In this aspect, a doped drift region is formed in the semiconductor substrate under the first gate insulating layer. A source region and a drain region are formed in the semiconductor substrate at both sides of the first gate insulating layer. The source region is separated from the first gate insulating layer and the drain region is in contact with the doped drift region. A second gate insulating layer may be formed over the semiconductor substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer. A gate electrode may then be over the first and second gate insulating layers. Embodiments relate to a method for forming a semiconductor device which may include forming a doped drift region doped with a second conductivity type impurity in a specific region of a semiconductor substrate doped with a first conductivity type impurity. A drain region may be formed in contact with the doped drift region and a source region separated from the doped drift region in the semiconductor substrate at both sides of the doped drift region. First conductivity type impurity ions may be implanted into the doped drift region to form a count doped region and a gate insulating layer and a gate electrode are then sequentially formed over the semiconductor substrate between the source and drain regions. The source and drain regions are doped with the second conductive impurity. DRAWINGS FIG. 1 is a cross-sectional view illustrating a method for forming a related EDMOS transistor. Example FIG. 2 is a cross-sectional view illustrating a semiconductor device having an EDMOS transistor according to embodiments. Example FIGS. 3 and 4 are cross-sectional views illustrating a method for forming a semiconductor device having an EDMOS transistor according to embodiments. Example FIG. 5 is a cross-sectional view illustrating a semiconductor device having an EDMOS transistor according to embodiments. Example FIG. 6 is a cross-sectional view illustrating a method for forming a semiconductor device having an EDMOS transistor according to embodiments. DESCRIPTION Example FIG. 2 is a cross-sectional view illustrating a semiconductor device having an EDMOS transistor according to embodiments. As shown in example FIG. 2, a first gate insulating layer 104 fills a trench 102 formed in a specific region of a semiconductor substrate 100. In embodiments, the trench 102 may have a rounded shape. In embodiments, the trench 102 may have a depth of about 2000 Å to about 8000 Å from the top surface of the semiconductor substrate 100. A source region 108s and a drain region 108d are formed in the semiconductor substrate 100 at both sides of the first gate insulating layer 104. The source region 108s is separated from the first gate insulating layer 104 and the drain region 108d is adjacent to the first gate insulating layer 104. A doped drift region 106 is formed in the semiconductor substrate 100 under the first gate insulating layer 104. The doped drift region 106 may be in contact with the drain region 108d. The drain region 108d, the source region 108s, and the doped drift region 106 have been doped with the same type of impurities. In embodiments, the doped drift region 106 may have a lower impurity concentration than that of the drain region 108d. The source and drain regions 108s and 108d may have the same impurity concentration. A second gate insulating layer 110 is formed over the semiconductor substrate 100 between the source region 108s and the trench 102, i.e., the first gate insulating layer 104. The second gate insulating layer 110 is in contact with a portion of the first gate insulating layer 104. The first gate insulating layer 104 may include an oxide layer. Particularly, the first gate insulating layer 104 may include a Chemical Vapor Deposition (CVD) oxide layer. The second gate insulating layer 110 may also include an oxide layer. Particularly, the second gate insulating layer 110 may include a thermal oxide layer. A gate electrode 112 is formed over the first and second gate insulating layers 104 and 110. The gate electrode 112 may cover the entire surface of the second gate insulating layer 110 positioned over the semiconductor substrate 100 between the source region 108s and the trench 102. In contrast, the gate electrode 112 may cover only a part of the first gate insulating layer 104. Particularly, the gate electrode 112 may cover a part of the first gate insulating layer 104 adjacent to the second gate insulating layer 110. Accordingly, the gate electrode 112 and the drain region 108d are separated from each other. The gate electrode 112 includes a conductive material. For example, the gate electrode 112 may include at least one material selected from the group consisting of doped polysilicon, a metal such as tungsten or molybdenum, a metal silicide such as tungsten silicide or cobalt silicide, and a conductive metal nitride such as titanium nitride or tantalum nitride. In the EDMOS transistor constructed as described above, the first gate insulating layer 104 fills the trench 102 formed in the semiconductor substrate 100. This significantly reduces the planar area of the first gate insulating layer 104, compared to that of a gate oxide layer formed using the related LOCOS process. This leads to a reduction in the planar area of the EDMOS transistor, thereby achieving more highly integrated semiconductor devices. Example FIGS. 3 and 4 are cross-sectional views illustrating a method for forming a semiconductor device having an EDMOS transistor according to embodiments. As shown in example FIG. 3, a hard mask pattern 101 having an opening is formed over a semiconductor substrate 100. The opening exposes a specific region of the semiconductor substrate 100. The hard mask pattern 101 may include a material (for example, a nitride layer) having a varying etch selectivity with respect to the semiconductor substrate 100. The exposed semiconductor substrate 100 is etched using the hard mask pattern 101 as a mask to form a trench 102. In embodiments, the trench 102 may be formed in a rounded shape. In embodiments, the trench 102 may be formed to a maximum depth of about 2000 Å to about 8000 Å from the top surface of the semiconductor substrate 100. As shown in example FIG. 4, an insulating layer is formed over the semiconductor substrate 100 to fill the trench 102 and is then planarized until the hard mask pattern 101 is exposed, thereby forming a first gate insulating layer 104. The hard mask pattern 101 is then removed. An upper portion of the first gate insulating layer 104 may be etched when the hard mask pattern 101 is removed. First impurity ions are selectively implanted to form a doped drift region 106 in the semiconductor substrate 100 under the first gate insulating layer 104. Second impurity ions are selectively implanted to form a drain region 108d and a source region 108s in the semiconductor substrate 100 at both sides of the first gate insulating layer 104. The first and second impurity ions are of the same type. The drain region 108d may be in contact with the doped drift region 106 and the source region 108s may be separated from the first gate insulating layer 104. A second gate insulating layer 110 is formed over the semiconductor substrate 100 including the doped drift region 106 and the source and drain regions 108s and 108d. The second gate insulating layer 110 may be formed of a thermal oxide layer as described above. The second gate insulating layer 110 may be thinner than the first gate insulating layer 104. A gate conducting layer is formed over the entire surface of the semiconductor substrate 100 including the first and second gate insulating layers 104 and 110 and is then patterned to form the gate electrode 112 shown in example FIG. 2. Portions of the second gate insulating layer 110 at both sides of the gate electrode 112 may be removed so that the source and drain regions 108s and 108d are exposed. Example FIG. 5 is a cross-sectional view illustrating a semiconductor device having an EDMOS transistor according to embodiments. As shown in example FIG. 5, a doped drift region 202 is formed in a specific region of a semiconductor substrate 200. The substrate may be doped with a first conductivity type impurity. The doped drift region 202 may be doped with a second conductivity type impurity. A source region 206s and a drain region 206d are formed in the semiconductor substrate 200 at both sides of the doped drift region 202. The source and drain regions 206s and 206d may be doped with the second conductivity type impurity. The source region 206s may be horizontally separated from the doped drift region 202. In contrast, the drain region 206d is adjacent to the doped drift region 202 so that they may be in contact with each other. A count doped region 204 is formed in the doped drift region 202. Side and bottom surfaces of the count doped region 204 are surrounded by the doped drift region 202. The count doped region 204 is doped with the first conductivity type impurity. That is, the semiconductor substrate 200 and the count doped region 204 are doped with the first conductivity type impurity and the source region 206s, the drain region 206d, and the doped drift region 202 are doped with the second conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity and the second conductivity type impurity may be a p-type impurity. Alternatively, the first conductivity type impurity may be a p-type impurity and the second conductivity type impurity may be an n-type impurity. A gate insulating layer 208 and a gate electrode 210 are sequentially deposited over the semiconductor substrate 200 between the source region 206s and the drain region 206d. The gate electrode 210 may cover the entire surface of the semiconductor substrate 200 between the source region 206s and the doped drift region 202. The gate electrode 210 may additionally cover a part of the doped drift region 202 and a part of the count doped region 204. The gate electrode 210 has first and second sidewalls opposite to each other. The first sidewall of the gate electrode 210 is near the source region 206s and the second sidewall of the gate electrode 210 is near the drain region 206d. The second sidewall of the gate electrode 210 may be horizontally separated from the drain region 206d. The EDMOS transistor constructed as described above has the count doped region 204. When a high voltage is applied to the drain region 206d, the count doped region 204 reduces the electric field between the gate electrode 210 and the drain region 206d, thereby improving breakdown voltage characteristics between the gate electrode 210 and the drain region 206d. In addition, the count doped region 204 has a very small planar area. For example, even though the planar area of the count doped region 204 is reduced to between about 20% and 50% of that of a gate oxide layer formed through the related LOCOS process, the breakdown voltage characteristics are the same as those of the gate oxide layer. As a result, the planar area of the EDMOS transistor can be minimized to achieve more highly integrated semiconductor devices. Example FIG. 6 is a cross-sectional view illustrating a method for forming a semiconductor device having an EDMOS transistor according to embodiments. As shown in example FIG. 6, first impurity ions using a second conductivity type impurity are selectively implanted into a semiconductor substrate 200 doped with a first conductivity type impurity to form a doped drift region 202 in the semiconductor substrate 200. Second impurity ions using the second conductivity type impurity are selectively implanted into the semiconductor substrate 200 to form a source region 206s and a drain region 206d in the semiconductor substrate 200 at both sides of the doped drift region 202. The source region 206s is horizontally separated from the doped drift region 202 and the drain region 206d is in contact with the doped drift region 202. Third impurity ions using the first conductivity type impurity are selectively implanted into the semiconductor substrate 200 to form a count doped region 204. Here, the count doped region 204 is formed in the doped drift region 202. The implantation of third impurity ions to form the count doped region 204 may be performed after or before the implantation of second impurity ions is performed to form the source and drain regions 206s and 206d. In the case where the first conductivity type impurity is a p-type impurity and the second conductivity type impurity is an n-type impurity, the implantation of third impurity ions to form the count doped region 204 may be performed by implanting B or BF2 with an energy of about 1 to 2000 KeV. This process may be performed with an ion dose of about 1011 to about 1016 atoms/cm2 and an ion injection angle of 0° to about 60°. In the case where the first conductivity type impurity is an n-type impurity and the second conductivity type impurity is a p-type impurity, the implantation of third impurity ions to form the count doped region 204 may be performed by implanting P or As with an energy of about 1 to 2000 KeV. This process may be performed with an ion dose of about 1011 to about 1016 atoms/cm2 and an ion injection angle of 0° to about 60°. A gate insulating layer 208 and a gate electrode 210 shown in example FIG. 5 are then formed over the semiconductor substrate 200 including the source and drain regions 206s and 206d, the doped drift region 202, and the count doped region 204. As is apparent from the above description, for example, a gate insulating layer is formed over a doped drift region with filling a trench. This allows formation of an EDMOS transistor having a smaller planar area than an EDMOS transistor with a gate oxide layer formed using the related LOCOS process, thereby achieving more highly integrated semiconductor devices. Alternatively, a count doped region may be formed in the doped drift region, instead of forming a gate oxide layer over it using the related LOCOS process. The count doped region is doped with a different type of impurity from that of the doped drift region. The planar area of the count doped region is significantly reduced compared to that of the gate oxide layer formed using the related LOCOS process. This leads to a reduction in the planar area of the EDMOS transistor, thereby achieving more highly integrated semiconductor devices. It will be obvious and apparent to those skilled in the art that various modifications and variations can be made in the embodiments disclosed. Thus, it is intended that the disclosed embodiments cover the obvious and apparent modifications and variations, provided that they are within the scope of the appended claims and their equivalents.	H	67H01	185H01L	29	78
11769304	US20080121972A1-20080529	SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME	ACCEPTED	20080514	20080529	[]	H01L29788	["H01L29788", "H01L21336"]	7679127	20070627	20100316	257	315000	79459.0	MANDALA	VICTOR	[{"inventor_name_last": "Shiozawa", "inventor_name_first": "Junichi", "inventor_city": "Yokkaichi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Furuhata", "inventor_name_first": "Takeo", "inventor_city": "Yokkaichi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Sekihara", "inventor_name_first": "Akiko", "inventor_city": "Yokohama", "inventor_state": "", "inventor_country": "JP"}]	A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers.	1. A semiconductor device, comprising: a semiconductor substrate including a first upper surface having an element isolation region and an element forming region; a first gate electrode formed on the first upper surface of the semiconductor substrate via a first insulating film in the element forming region, including a second upper surface being higher than the first upper surface of the semiconductor substrate and a first side surface; a second insulating film formed in the element isolation region of the semiconductor substrate, including a third upper surface being lower than the second upper surface and being higher than the first upper surface and a second side surface contacting with the first side surface; a third insulating film including a first portion formed or the second upper surface and the first side surface of the first gate electrode and a second portion formed on the third upper surface of the second insulating film; and a second gate electrode formed on the third insulating film, wherein the first portion of the third insulating film includes a first silicon nitride layer contacting with the first gate electrode, a first silicon oxide layer formed on the first silicon nitride layer, a second silicon nitride layer formed on the first silicon oxide layer, a second silicon oxide layer formed on the second silicon nitride layer and a third silicon nitride layer formed on the second silicon oxide layer, and the second portion of the third insulating film includes a third silicon oxide layer contacting with the third upper surface of the second insulating film, a fourth silicon nitride layer formed or the third silicon oxide layer, a fourth silicon oxide layer formed on the fourth silicon nitride layer and fifth silicon nitride layer formed on the fourth silicon oxide layer. 2. The device of claim 1, wherein the first silicon oxide layer is continuous with the third silicon oxide layer, the second silicon nitride layer is continuous with the fourth silicon nitride layer, the second silicon oxide layer is continuous with the fourth silicon oxide layer and the third silicon nitride layer is continuous with the fifth silicon nitride layer. 3. The device of claim 1, wherein the first gate electrode is a floating gate electrode as a charge storing layer and the second gate electrode is a control gate electrode. 4. A semiconductor device, comprising: a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating films; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and constituting a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers. 5. The device of claim 4, wherein the second gate insulating film layer includes a structure where an oxide film layer is formed to cover an entire upper surface of the element isolation insulating film. 6. The device of claim 4, wherein the second gate insulating film layer includes a structure where an oxide film layer and a nitride film layer of the NONON stacked film structure are formed sequentially on the element isolation insulating film, and the oxide film layer is formed thicker than the nitride film layer. 7. The device of claim 5, wherein the second gate insulating film layer includes a structure where the oxide film layer and the nitride film layer of the NONON stacked film structure are formed sequentially on the element isolation insulating film, and the oxide film layer is formed thicker than the nitride film layer. 8. A method of manufacturing a semiconductor device, comprising: forming a first gate insulating film and a first conductive layer on a semiconductor substrate; separating the first conductive layer by forming an element isolation trench in the first conductive layer, the first gate insulating film and the semiconductor substrate; forming an element isolation insulating film in the element isolation trench so as to provide an exposed surface on at least a portion of the first conductive layer; selectively forming a nitride film layer constituting a lowermost layer of a second gate insulating film layer on the exposed surface of the first conductive layer; and forming an oxide film layer constituting the second gate insulating film layer on the nitride film layer and the element isolation insulating film. 9. The method of claim 8, wherein a silicon nitride film serving as the nitride film layer is selectively formed on the exposed surface of the first conductive layer by a radical nitridation treatment by specifying a plasma-generating energy equal to or greater than Si—Si binding energy but less than a Si—O binding energy.	<SOH> BACKGROUND <EOH>Conventionally, a stacked gate electrode structures composed of a floating gate electrode layer and a control gate electrode layer has been employed to render non-volatile storage of information. In realizing the stacked gate electrode structure, an inter-gate insulating film is formed between the floating gate electrode layer and the control gate electrode layer to provide insulation between the layers. As a result of recent attempts in exploring gate insulating films exhibiting higher performance, ONO film (stack of silicon oxide film, silicon nitride film, and silicon oxide film) has been generally employed as the inter-gate insulating film. However, increasing integration of gate electrodes has given rise to occurrence of bird's beak in the ONO film and difficulties in achieving higher densification due to failure in obtaining the desired coupling ratio. As disclosed in JP H09-219459 A, it has beer considered to employ NONON stacked film structure (silicon nitride film/silicon oxide film/silicon nitride film/silicon oxide film/silicon nitride film) for the inter-gate insulating film. According to JP H09-219459 A, TDDB (Time Dependant Dielectric Break Down) can be reduced by a magnitude of approximately one digit as compared to conventional ONO film, thereby preventing the occurrence of bird's beak. However, it has been observed that due to some unknown reason, employing NONON stacked film structure for inter-gate insulating film increases the occurrence of charge transportation between the neighboring floating gate electrodes when the state of charge accumulation between the neighboring floating gate electrode layers differ. Thus, when the charge accumulation between the floating electrode layers differ, charge transportation may undesirably lead to problems such as change in threshold voltage and data error.	<SOH> SUMMARY <EOH>The present disclosure provides a semiconductor device that prevents charge transportation between the neighboring floating gate electrode layers when NONON stacked film structure is employed for inter-gate insulating film which is formed between the floating gate electrode layer and the control gate electrode layer. The present disclosure also provides a method of manufacturing such semiconductor device. In one aspect, the present disclosure provides a semiconductor substrate including a first upper surface having an element isolation region and an element forming region; a first gate electrode formed on the first upper surface of the semiconductor substrate via a first insulating film in the element forming region, including a second upper surface being higher than the first upper surface of the semiconductor substrate and a first side surface; a second insulating film formed in the element isolation region of the semiconductor substrate, including a third upper surface being lower than the second upper surface and being higher than the first upper surface and a second side surface contacting with the first side surface; a third insulating film including a first portion formed on the second upper surface and the first side surface of the first gate electrode and a second portion formed on the third upper surface of the second insulating film; and a second gate electrode formed on the third insulating film, wherein the first portion of the third insulating film includes a first silicon nitride layer contacting with the first gate electrode, a first silicon oxide layer formed on the first silicon nitride layer, a second silicon nitride layer formed on the first silicon oxide layer, a second silicon oxide layer formed on the second silicon nitride layer and a third silicon nitride layer formed on the second silicon oxide layer, and the second portion of the third insulating film includes a third silicon oxide layer contacting with the third upper surface of the second insulating film, a fourth silicon nitride layer formed on the third silicon oxide layer, a fourth silicon oxide layer formed on the fourth silicon nitride layer and fifth silicon nitride layer formed on the fourth silicon oxide layer. In another aspect, the present disclosure provides a semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating film; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and situated at a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers. Yet, in another aspect, the present disclosure provides a method of manufacturing the semiconductor device involving forming a first gate insulating film and a first conductive layer on a semiconductor substrate; separating the first conductive layer into plurality of portions by forming an element isolation trench in the first conductive layer, the first gate insulating film and the semiconductor substrate; forming an element isolation insulating film in the element isolation trench so as to define an exposed surface on at least a portion of the first conductive layer; selectively forming a nitride film layer constituting a lowermost layer of a second gate insulating film layer on the exposed surface of the first conductive layer; and forming an oxide film layer constituting the second gate insulating film layer on the nitride film layer and the element isolation insulating film.	CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-176646, filed on, Jun. 27, 2006 the entire contents of which are incorporated herein by reference. FIELD The present disclosure is directed to a semiconductor device employing a stacked gate structure and a method of manufacturing the same. BACKGROUND Conventionally, a stacked gate electrode structures composed of a floating gate electrode layer and a control gate electrode layer has been employed to render non-volatile storage of information. In realizing the stacked gate electrode structure, an inter-gate insulating film is formed between the floating gate electrode layer and the control gate electrode layer to provide insulation between the layers. As a result of recent attempts in exploring gate insulating films exhibiting higher performance, ONO film (stack of silicon oxide film, silicon nitride film, and silicon oxide film) has been generally employed as the inter-gate insulating film. However, increasing integration of gate electrodes has given rise to occurrence of bird's beak in the ONO film and difficulties in achieving higher densification due to failure in obtaining the desired coupling ratio. As disclosed in JP H09-219459 A, it has beer considered to employ NONON stacked film structure (silicon nitride film/silicon oxide film/silicon nitride film/silicon oxide film/silicon nitride film) for the inter-gate insulating film. According to JP H09-219459 A, TDDB (Time Dependant Dielectric Break Down) can be reduced by a magnitude of approximately one digit as compared to conventional ONO film, thereby preventing the occurrence of bird's beak. However, it has been observed that due to some unknown reason, employing NONON stacked film structure for inter-gate insulating film increases the occurrence of charge transportation between the neighboring floating gate electrodes when the state of charge accumulation between the neighboring floating gate electrode layers differ. Thus, when the charge accumulation between the floating electrode layers differ, charge transportation may undesirably lead to problems such as change in threshold voltage and data error. SUMMARY The present disclosure provides a semiconductor device that prevents charge transportation between the neighboring floating gate electrode layers when NONON stacked film structure is employed for inter-gate insulating film which is formed between the floating gate electrode layer and the control gate electrode layer. The present disclosure also provides a method of manufacturing such semiconductor device. In one aspect, the present disclosure provides a semiconductor substrate including a first upper surface having an element isolation region and an element forming region; a first gate electrode formed on the first upper surface of the semiconductor substrate via a first insulating film in the element forming region, including a second upper surface being higher than the first upper surface of the semiconductor substrate and a first side surface; a second insulating film formed in the element isolation region of the semiconductor substrate, including a third upper surface being lower than the second upper surface and being higher than the first upper surface and a second side surface contacting with the first side surface; a third insulating film including a first portion formed on the second upper surface and the first side surface of the first gate electrode and a second portion formed on the third upper surface of the second insulating film; and a second gate electrode formed on the third insulating film, wherein the first portion of the third insulating film includes a first silicon nitride layer contacting with the first gate electrode, a first silicon oxide layer formed on the first silicon nitride layer, a second silicon nitride layer formed on the first silicon oxide layer, a second silicon oxide layer formed on the second silicon nitride layer and a third silicon nitride layer formed on the second silicon oxide layer, and the second portion of the third insulating film includes a third silicon oxide layer contacting with the third upper surface of the second insulating film, a fourth silicon nitride layer formed on the third silicon oxide layer, a fourth silicon oxide layer formed on the fourth silicon nitride layer and fifth silicon nitride layer formed on the fourth silicon oxide layer. In another aspect, the present disclosure provides a semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gate insulating film layer formed so as to cover upper surfaces of the plurality of first gate electrode layers and the element isolation insulating film; and a second gate electrode layer formed on the second gate insulating film layer; and the second gate insulating film layer includes a NONON stacked film structure and a nitride film layer contacting the first gate electrode layer and situated at a lowermost layer of the NONON stack film structure is separated at a portion interposing the plurality of neighboring first gate electrode layers. Yet, in another aspect, the present disclosure provides a method of manufacturing the semiconductor device involving forming a first gate insulating film and a first conductive layer on a semiconductor substrate; separating the first conductive layer into plurality of portions by forming an element isolation trench in the first conductive layer, the first gate insulating film and the semiconductor substrate; forming an element isolation insulating film in the element isolation trench so as to define an exposed surface on at least a portion of the first conductive layer; selectively forming a nitride film layer constituting a lowermost layer of a second gate insulating film layer on the exposed surface of the first conductive layer; and forming an oxide film layer constituting the second gate insulating film layer on the nitride film layer and the element isolation insulating film. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the present disclosure will become clear upon reviewing the following description of the embodiment of the present disclosure with reference to the accompanying drawings, in which, FIG. 1 is a diagram of an electrical configuration illustrating a portion of an inner configuration of a semiconductor device in accordance with one embodiment of the present disclosure; FIG. 2 is a schematic plan view of a structure of region A1 in FIG. 1; FIG. 3 is a sectional view taken along line 3-3 of FIG. 2; FIG. 4 is a sectional view taken along line 4-4 of FIG. 2; and FIGS. 5 to 13 are views illustrating the manufacturing process. DETAILED DESCRIPTION One embodiment applying the semiconductor device of the present disclosure to a NAND flash memory device (non-volatile semiconductor storage device) will be described with reference to FIGS. 1 to 13. FIG. 1 illustrates an equivalent circuit of a memory cell array constituting a NAND flash memory device. FIG. 2 is a schematic plan view of the memory cell configuration of region A1 (bit line contact CB, memory cell transistor Trn and select gate transistor Trs) of FIG. 1. FIG. 3 is a schematic sectional view taken along line 3-3 of FIG. 2. More specifically, FIG. 3 is a sectional view taken along the X-direction of a gate electrode of the memory transistor Trn and the silicon substrate 2. FIG. 4 is a schematic sectional view taken along line 4-4 of FIG. 2. More specifically, FIG. 4 is a sectional view taken along the Y-direction of the gate electrode of memory transistor Trn, and the silicon substrate 2. The NAND flash memory device 1, serving as a semiconductor device has formed thereto a compartment of memory cell region M and peripheral circuit region (not shown) on a p-type semiconductor substrate 2. Referring to FIG. 1, memory cell array Ar comprises NAND cell units SU arranged in an array of rows and columns. The NAND cell unit SU is constituted by a couple of select gate transistors Trs and a plurality (eight for example: nth power of 2 (n is a positive integer)) of memory cell transistors Trn disposed between the couple of select gate transistors Trs. The memory cell transistors Trn are connected in series by sharing the source/drain region 2a (refer to FIG. 4) between the neighboring memory cell transistors Trn. Referring to FIG. 1, the memory cell transistors Trn aligned in the X-direction (word line direction) are connected to a common word line (control gate line) WL. Also, the select gate transistors Trs aligned in the X-direction are connected to a common select gate line SL. The select gate transistors Trs are further connected to a bit line BL, extending in the Y-direction (bit line direction) perpendicular to the X-direction in FIG. 1, via a bit line contact CB. Referring to FIG. 2, the plurality of NAND cell units SU are separated from one another by element isolation regions Sb taking an STI (Shallow Trench Isolation) structure. The memory cell transistors Trn are formed at intersections of element forming regions (active area) Sa extending in the Y-direction and the word lines WL formed at predetermined intervals in the Y-direction and extending in the X-direction. The gate electrode structure of the memory cell region M constituting the features of the present embodiment will be described with reference to FIGS. 3 and 4. Referring to FIG. 3, the element forming regions Sa are isolated and insulated from one another by element isolation regions Sb taking an STI structure. A silicon oxide film 3 is formed on each element forming region Sa. The silicon oxide film 3 serves as a first gate insulating film (corresponding to a gate oxide film, a tunnel insulating film, and a first insulating film). A floating gate electrode layer FG serving as a first gate electrode layer is formed on each of the plurality of silicon oxide films 3. An upper surface of the floating gate electrode layer FG is higher than the upper surface of the silicon substrate 2. The floating gate electrode layer FG is configured by a first conductive layer, for example, amorphous silicon layer (polycrystalline silicon layer) 4. The amorphous silicon layer 4 is configured by an upper layer and a lower layer: non-dope amorphous silicon formed in the lower layer and amorphous silicon doped with impurities such as phosphorous formed in the upper layer. The amorphous silicon layer 4 is turned into polycrystalline silicon layer by thermal processing. The element isolation region Sb electrically isolates the neighboring floating gate electrode layers FG. In the element isolation region Sb, an element isolation trench 5 is defined in the silicon substrate 2, and the element isolation trench 5 is filled with an element isolation insulating film 6. The lower portion of the element isolation insulating film 6 is composed of silicon oxide film 6a such as TEOS (Tetra Ethyl Ortho Silicate: Tetra EthOxy Silane), which silicon oxide film 6a is formed on the inner bottom surface of the element isolation trench 5. Coated insulating film (spin on glass film) 6b made of polysilazane solution composed of silica-based coating solution is formed on the silicon oxide film 6a. Continuous shrinking of circuit design rule requires scaling of element isolation region Sb width. Thus, the present embodiment employs coated insulating film 6b exhibiting high-suitability for filling the element isolation trench 5 and the silicon oxide film 6a as element isolation insulating film 6 to render a double layer structure. The element isolation insulating film (a second insulating film) 6 is formed so that the upper surface thereof is higher than the upper surface of the silicon oxide film 3 formed at both sides of the element isolation insulating film 6 and lower than the upper surface of the floating gate electrode layer FG. In other words, the element isolation insulating film 6 is formed so as to project from the silicon substrate 2 surface and separate the neighboring floating gate electrode layers FG. The side surfaces of the element isolation insulating film 6 contact the side surfaces of the neighboring floating gate electrode layers FG. A second gate insulating film layer (corresponding to a third insulating film) 7 is configured to cover the floating gate electrode layer FG and the element isolation insulating film 6. A control gate electrode layer CG is formed on the second gate insulating film layer 7 so as to cover the second gate insulating film layer 7. The second gate insulating film layer 7 is formed on the upper surface and the side surfaces of the floating gate electrode layer FG. The second gate insulating film layer 7 takes a stacked structure of a plurality of insulating films including the NONON stack film structure, and is formed between the floating gate electrode layer FG and the control gate electrode layer CG. The second gate insulating film layer 7 functions as an inter-gate insulating film (inter-poly insulating film) in the regions interposing the electrode layers FG and CG (corresponding to a first portion of the second gate insulating film layer 7); and takes a NONON structure composed of: the lowermost silicon nitride film 7a (nitride film layer), silicon oxide film 7b (oxide film layer), silicon nitride film 7c (nitride film layer), silicon oxide film 7d (oxide film layer) and the uppermost silicon nitride film 7e (nitride film layer). The second gate insulating film layer 7 is also formed on the element isolation insulating film 6 where in such area (portion), at least a portion (for example central portion of element isolation insulating film 6) of the second gate insulating film layer 7 takes an ONON structure. In other words, in such area (corresponding to a second portion), the lowermost silicon nitride film 7a (nitride film layer) is removed as opposed to the region interposing the floating gate electrode layer FG and the control gate electrode layer CG (portion functioning as inter-gate insulating film), exhibiting a structure in which the silicon nitride film 7a is separated at a portion interposing the neighboring floating gate electrodes FG. Each of the aforementioned films 7b to 7e constituting the second gate insulating film layer 7 is formed continuously from the area interposing the floating gate electrode FG and the control gate electrode CG (corresponding to the first portion of the second gate insulating film layer 7) to the area over the element isolation insulating film 6 (corresponding to the second portion of the second gate insulating film layer 7). The inventors having verified that charge is prone to transport through the lower layers of the NONON structure, especially through the interface of the silicon nitride film 7a and the element isolation insulating film 6, have therefore opted to employ the aforementioned structure. Thus, charge transportation between the neighboring floating gate electrodes FG can be prevented. In the light of preventing charge transportation, the silicon oxide film 7b may be formed across the entire upper surface of the element isolation insulating film 6. Suppose the thicknesses of the films are configured as follows: silicon nitride film 7a at 1 [nm], silicon oxide film 7b at 6 [nm], silicon nitride film 7c at 5 [nm], silicon oxide film 7d at 5 [nm] and silicon nitride film 7e at 1 [nm]. In such case, it is desirable to configure the thickness of the silicon oxide film 7b overlying the element isolation insulating film 6 to be thicker as compared with the silicon nitride film 7a, 7c, and 7d. This is in view of also preventing the charge transportation between the neighboring floating gate electrode layers FG in the lateral direction (X-direction) through silicon nitride film 7c by forming the silicon oxide film 7b thicker than the silicon nitride film 7c in particular. The control gate electrode layer CG includes a polycrystalline silicon layer 8 (second conductive layer) doped with impurities such as phosphorous or arsenic and a tungsten silicide layer 9 functioning as a metal silicide layer for reducing resistance formed on the polycrystalline silicon layer 8. The control gate layer CG is formed over and across the plurality of element forming regions Sa and the element isolation regions Sb. A silicon nitride film 10 is formed on the control gate electrode layer CG. As shown in FIG. 4, a protective silicon oxide film 11 is formed on the silicon nitride film 10 so as to cover the layers 4 to 10. An interlayer insulating film composed of silicon oxide films 12 and 13 are further formed on the silicon nitride film 10. A bit line BL (not shown in FIGS. 3 and 4) is formed on the silicon oxide films 12 and 13. According to the configuration of the present embodiment, the second gate insulating film layer 7 takes a NONON stacked film structure and the silicon nitride film 7a situated in the lowermost layer of the structure is formed in the portion in contact with the floating gate electrode 4 but is separated in the portions interposing the plurality of neighboring floating gate electrodes FG. Thus, charge transportation through silicon nitride film 7a and charge transportation between the neighboring floating gate electrode layers FG can be prevented even if NONON stacked film structure is employed for inter-gate insulating film. Since the silicon oxide film 7b is formed substantially across the entire surface of the element isolation insulating film 6, characteristic degradation caused by charge transportation through silicon nitride film 7a can be prevented. Also, since the thickness of the silicon oxide film 7b situated in the lowermost layer of the ONON stacked film structure formed on the element isolation insulating film 6 is made thicker than the silicon nitride film 7c in particular, charge transportation induced by the silicon nitride film 7c formed immediately on the silicon oxide film 7b can be prevented. The method of manufacturing the memory cell region M of the NAND flash memory device 1 will be described in detail hereinafter. The method employs a process where the floating gate electrode layer FG is formed prior to the element isolation region Sb. The steps of the manufacturing process described hereinafter may be omitted or modified or may further incorporate additional well known step(s) as long as the present disclosure can be realized. Referring to FIG. 5, the silicon oxide film 3 serving as a first gate insulating film is formed on the silicon substrate 2 in the thickness of 10 [nm], for example by thermal oxidation process. Amorphous silicon layer 4 constituted by stacking ron-doped amorphous silicon and doped amorphous silicon doped with impurities such as phosphorous is formed on the silicon oxide film 3 by LPCVD (Low-Pressure Chemical Vapor Deposition) process in the thickness of 140 [nm], for example. The amorphous silicon layer 4 is converted to polycrystalline silicon layer by thermal processing step later on. Next, referring to FIG. 6, silicon nitride film 14 is formed on the amorphous silicon layer 4 by LPCVD process in the thickness of 70 [nm] for example. Then, resist (not shown) is coated on the silicon nitride film 14 to pattern the floating gate electrode layer FG forming region, whereafter silicon nitride film 14 is removed by RIE (Reactive Ion Etching) process using the patterned resist as a mask. Next, referring to FIG. 7, amorphous silicon layer 4, silicon oxide film 3, and the silicon substrate 2 are etched by RIE process, and a plurality of element isolation trenches 5 are defined parallel to one another in alignment with a predetermined direction (Y-direction in FIGS. 1 and 2). The resist (not shown) is removed by ashing technique. Thus, the amorphous silicon layer 4 and silicon oxide film 3 are separated into plurality portions respectively. Next, referring to FIG. 8, the silicon oxide film 6a is formed along the inner surface of the element isolation trench 5 in the thickness of about 10 [nm] by LPCVD process on the aforementioned films, and polysilazane solution (a type of silica-based coating solution) is coated in the thickness of about 600 [nm] on the inner side of the silicon oxide film 6a to form the coated insulating film 6b. Then, the polysilazane solution is thermally processed in an oxidizing atmosphere at a temperature in the range of 400 to 500° C. to convert the polysilazane solution into silicon oxide film constituting the coated insulating film 6b. Thereafter, the silicon oxide film 6a and coated insulating film 6b are planarized by CMP (Chemical Mechanical Polishing) process until the surface of the silicon nitride film 14 is exposed. Next, referring to FIG. 9, the surfaces of the coated insulating film 6b and the silicon oxide film 6a are etched by RIE process in the magnitude of 150 [nm] for example. Then the resist (not shown) is removed by ashing technique and silicon nitride film 14 is removed thereafter. Consequently, as shown in FIG. 9, the upper surface of the coated insulating film 6b and the silicon oxide film 6a are positioned above the upper surface of the silicon oxide film 3 but below the upper surface of the amorphous silicon layer 4. Next, referring to FIG. 10, the silicon nitride film 7a (corresponding to the nitride film layer) is selectively formed on the exposed surface of the amorphous silicon layer 4 in the thickness of 2 [nm] or less (1 [nm] for example). The silicon nitride film 7a is formed by radical nitridation treatment. Radical nitridation treatment is executed by generating micro waves in an atmosphere including nitrogen gas which radical nitridation treatment generates nitrogen radical to form the silicon nitride film 7a on the amorphous silicon layer 4. At this time, the energy for generating plasma may be set at 2.2 eV, which is the binding energy of Si—Si bond, or greater; but less than 3.4 eV, which is the binding energy of Si—O bond, by setting the pressure in the range of 1 to 3 Torr. In such case, radical nitridation treatment being executed at an energy equivalent to or greater than the binding energy of Si—Si bond facilitates the cleavage of Si—Si bond and promotes Si—N bond on the surface of the amorphous silicon layer 4. On the other hand, since radical nitridation treatment is executed at an energy level less than the Si—O binding energy, cleavage of the Si—O bond is disallowed in the upper surfaces of the silicon oxide film 6a and the coated insulating film 6b, consequently impairing the growth of the silicon nitride film 7a. Thus, the silicon nitride film 7a can be formed selectively on the exposed surface of the amorphous silicon layer 4. Next, referring to FIG. 11, silicon oxide film 7b, silicon nitride film 7c, and silicon oxide film 7d are formed sequentially by LPCVD process in the thickness of 6 [nm], 5 [nm] and 6 [nm] respectively. Next, referring to FIG. 12, the surface of the silicon oxide film 7d is processed by radical nitridation treatment. At this time, by setting the pressure at about 50 m Torr, the energy for generating plasma is in turn set at 3.4 eV, which is the binding energy for Si—O bond, or greater. Such setting allows cleavage of Si—O bond, thus, silicon nitride film 7e can be formed in the thickness of 1 [nm] by nitridation of the silicon oxide film 7d surface. Thus, 1 [nm] of exposed upper surface of the silicon oxide film 7d can be nitridized by radical nitridation. ONON films 7b to 7e correspond to other layers of nitride film layer (silicon nitride film 7a). Next, referring to FIG. 13, the amorphous silicon layer 8 doped with impurities such as phosphorous or arsenic is formed by CVD process. The amorphous silicon layer 8 is later converted to polycrystalline silicon layer in the thermal oxidation step. Next, referring to FIG. 3, tungsten silicide film 9 is formed on the polycrystalline silicon layer 8 by sputtering process, and the like, and silicon nitride film 10 is formed on the tungsten silicide film 9 by LPCVD process in the thickness of about 300 [nm]. Subsequently, a resist (not shown) is coated and thereafter patterned. Then, the stacked films 3 to 10 of the gate electrode 15 isolation region GV (refer to FIG. 2) is etched by RIE process, or the like, so as to separate the stacked films 3 to 10 in the Y-direction into plurality of portions. Thus, the stacked films 3 to 10 are allowed to remain within the plurality of Y-directional gate electrode forming regions GC (refer to FIG. 2). Next, referring to FIG. 4, a source/drain region 2a is formed in the surface layer of the silicon substrate 2 and silicon oxide film 11 for protecting the gate is formed so as to cover the stacked layers 3 to 10. Subsequently, silicon oxide films 12 and 13 serving as interlayer insulating film are formed on the silicon oxide film 11. A bit line BL (refer to FIGS. 1 and 2 (not shown in FIGS. 3 and 4)) is formed on the interlayer insulating film and the backend process follows thereafter to render the resultant NAND flash memory device 1. A description will not be given on the backend process since it is irrelevant to the features of the present embodiment. As described above, the manufacturing method of the present disclosure involves forming the silicon oxide film 3 and the amorphous silicon layer 4 on the semiconductor substrate 2; dividing the amorphous silicon layer 4 by forming the element isolation trench 5 in the amorphous silicon layer 4, the silicon oxide film 3 and the semiconductor substrate 2; forming an element isolation insulating film 6 in the element isolation trench 5 so as to expose the upper surface of the amorphous silicon layer 4; selectively forming the silicon nitride film 7a constituting the lowermost layer of the second gate insulating layer 7 on the exposed surface of the amorphous silicon layer 4; and forming the oxide film layer 7b constituting the second gate insulating film layer 7 on the silicon nitride film 7a and the element isolation insulating film 6, thus, no silicon nitride film is formed immediately on the element isolation insulating film 6 and charge transportation between the plurality of neighboring floating gate electrode layers FG in the X-direction can be prevented even if NONON stacked film structure is employed for the second gate insulating layer 7 formed between the floating gate electrode layer FG and control gate electrode layer CG. In selectively forming the silicon nitride film 7a on the exposed surface of the amorphous silicon layer 4, the silicon nitride film 7a is formed by radical nitridation treatment by setting the energy for generating plasma at the binding energy of Si—Si bond or greater but less than the binding energy of Si—O. Thus, formation of silicon nitride film 7a on the exposed surface of the amorphous silicon layer 4 is promoted, whereas formation of silicon nitride film 7a on the element isolation insulating film 6 is restrained. A manufacturing step of separating especially the lowermost layer of the NONON structure may be carried out in the same way as the manufacturing step of separating the ONO (Oxide-Nitride-Oxide) film disclosed in JP 2001-168306 A. However; employing such step may lead to cost increase since it requires an additional step for separating the nitride film layer. According to the present embodiment, since the silicon nitride film 7a of the lowermost layer of the second gate insulating film layer 7 is formed by radical nitridation, a structure that does not form the silicon nitride film 7a on the element isolation insulating film 6 can be obtained while selectively forming the silicon nitride film 7a so as to cover the floating gate electrode layer FG. The present disclosure is not limited to the above embodiments but may be modified or expanded as follows. Though the above embodiment employs the silicon substrate 2 as a semiconductor substrate, other types of semiconductor substrates may be employed. In alternative to the NONON stacked film structure serving as the second gate insulating film layer 7 employed in the above embodiment, any type of stacked insulating film structure may be employed as long as it includes the NONON structure. Instead of the silicon oxide film 6a and coated insulating film 6b serving as the element isolation insulating film 6, silicon oxide films such as LP (Low Pressure)-TEOS film or HDP (High Density Plasma)-TEOS film, TEOS-O3, or the like, may be employed. LP-TEOS film is an abbreviation of a TEOS film formed by low pressure chemical vapor deposition and HDP-TEOS film is an abbreviation of a TEOS film formed by high-density plasma chemical vapor deposition. In the above described embodiment, the element isolation insulating film 6 is removed by dry-etch process, however, wet-etch may be employed alternatively. The floating gate electrode layers FG are formed respectively on the plurality of silicon oxide films 3 in the above embodiment; however, plurality of floating gate electrode layers FG may be formed on a single continuous silicon oxide film 3. The silicon nitride film 7a is formed by radical nitridation process in the above described embodiment, however, it may be formed by LPCVD with SiCl2H2 and NH3 as gas source at 700° C. or less instead. The present disclosure is applied to the NAND flash memory device 1, however the present disclosure may be applied to other non-volatile semiconductor storage devices as required such as EEPROM, EPROM and NOR type, or other non-volatile semiconductor storage device, semiconductor storage device and semiconductor device. The foregoing description and drawings are merely illustrative of the principles of the present disclosure and are not to be construed in a limited sense. Various changes and modifications will become apparent to those of ordinary skill in the art. All such changes and modifications are seen to fall within the scope of the disclosure as defined by the appended claims.	H	67H01	185H01L	297	88
11932677	US20080064179A1-20080313	LOW LEAKAGE MIM CAPACITOR	ACCEPTED	20080227	20080313	[]	H01L2120	["H01L2120"]	7435641	20071031	20081014	438	240000	77616.0	TSAI	HUI	[{"inventor_name_last": "Yang", "inventor_name_first": "Sam", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}]	Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.	1. A method of forming a capacitor, comprising: forming a bottom electrode layer having a monoclinic crystal structure; forming a metal oxide buffer layer overlying the bottom electrode layer, converting the metal oxide buffer layer lattice structure from a monoclinic crystalline structure to an orthorhombic crystalline structure, the bottom electrode layer maintaining a monoclinic crystal structure; forming a dielectric layer directly on the metal oxide buffer layer; and forming a top electrode layer overlying the dielectric layer. 2. The method of claim 1, wherein forming a metal oxide buffer layer includes forming WO3. 3. The method of claim 1, wherein converting includes forming a metal oxide buffer layer including WO3. 4. The method of claim 1, wherein forming metal oxide buffer includes forming a metal oxide layer comprising a refractory metal. 5. The method of claim 1, wherein forming metal oxide buffer includes forming a metal oxide layer that includes at least one of chromium, cobalt, hafnium, niobium, vanadium and zirconium. 6. The method of claim 1, wherein forming a bottom electrode includes nitridizing a deposited a metal layer. 7. A method of forming a capacitor, comprising: forming a bottom electrode layer having a monoclinic crystal structure; forming a metal oxide buffer layer adjacent to the bottom electrode layer, the metal oxide buffer layer having a monoclinic crystal structure; annealing the bottom electrode layer and the metal oxide layer to change the monoclinic crystalline structure of the metal oxide buffer layer to an orthorhombic crystalline structure, and retaining the monoclinic crystal structure of the bottom electrode layer; forming a dielectric layer directly on the metal oxide buffer layer; and forming a top electrode layer overlying the dielectric layer. 8. The method of claim 7, wherein forming a metal oxide buffer layer includes forming WOx. 9. The method of claim 7, wherein forming metal oxide buffer includes forming a metal oxide layer comprising a refractory metal. 10. The method of claim 7, wherein forming metal oxide buffer includes forming a metal oxide layer that includes at least one of chromium, cobalt, hafnium, niobium, vanadium and zirconium. 11. A method of forming a capacitor, comprising: forming a first layer including a metal nitride having a monoclinic crystal structure; forming a second layer including a metal oxide adjacent to the first layer, the second layer having a monoclinic crystal structure; changing the monoclinic crystalline structure of the second layer to an orthorhombic crystalline structure; and retaining the monoclinic crystal structure of the first layer. 12. The method of claim 11, wherein forming a first layer includes forming an electrode layer. 13. The method of claim 11, wherein forming a first layer includes forming a first layer adjacent to a metal silicide layer. 14. The method of claim 11, further comprising forming a metal silicide in contact with the first layer. 15. The method of claim 11, wherein forming a first layer includes forming a first layer in contact with a polysilicon layer. 16. The method of claim 15, further comprising annealing the first layer and the polysilicon layer to form a metal silicide. 17. The method of claim 15, further comprising heating the first layer and the polysilicon layer to reduce an electrical contact resistance. 18. The method of claim 11, wherein forming a second layer includes forming a second layer comprising WO3. 19. The method of claim 11, wherein forming a second layer includes forming a second layer comprising MOx, where M is a metal selected from a group consisting of chromium, hafnium, tantalum, titanium, niobium, zirconium, vanadium, molybdenum, and cobalt. 20. The method of claim 11, wherein forming a second layer includes depositing at least one of vanadium, zirconium and niobium. 21. The method of claim 11, wherein forming a second layer includes depositing a refractory metal having a thickness ranging from about 200 angstroms to about 800 angstroms. 22. The method of claim 11, wherein forming a second layer includes oxidizing to form Ta2O3 having a thickness ranging from about 60 angstroms to about 100 angstroms. 23. The method of claim 11, wherein forming a second layer includes oxidizing to form Ta2O3 having a thickness ranging from about 60 angstroms to about 100 angstroms. 24. The method of claim 11, wherein forming a second layer includes heating to form a region of tungsten silicide having a thickness ranging from about 200 angstroms to about 400 angstroms. 25. The method of claim 11, wherein forming a second layer includes heating to form a region of tungsten silicide having a thickness of five times a thickness of the Ta2O3. 26. The method of claim 11, wherein forming a second layer includes heating to reduce an electrical contact resistance.	<SOH> BACKGROUND <EOH>Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor typically includes two conductive electrodes separated by a dielectric layer. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage. Data is stored in the memory cells during a write mode and retrieved from the memory cells during a read mode. The data is transmitted on signal lines, sometimes referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of a digit line pair through an access transistor. Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells, i.e the charge stored in the associated capacitor, are shared with their associated digit lines, and data is sensed and latched to the digit line pairs. As DRAMs increase in memory cell density by decreasing memory cell area, there is an ongoing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is generally a function of electrode area. Additionally, there is a continuing goal to further decrease memory cell area. A principal method of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom electrode of the capacitor. Such container structures may have shapes differing from a substantially cylindrical form, such as an oval or other three-dimensional container. The container structures may further incorporate fins. Another method of increasing cell capacitance is through the use of high dielectric constant material in the dielectric layer of the capacitor. In order to achieve the charge storage efficiency generally needed in 256 megabit (Mb) memories and above, materials having a high dielectric constant, and typically dielectric constants greater than 20, can be used in the dielectric layer between the bottom electrode and the top electrode of the capacitor. The dielectric constant is a characteristic value of a material and is generally defined as the ratio of the amount of charge that can be stored in the material when it is interposed between two electrodes relative to the charge that can be stored when the two electrodes are separated by a vacuum. Unfortunately, high dielectric constant materials are often incompatible with existing processes. One cause of such incompatibility can be adverse chemical reactions or oxygen diffusion between the material of the dielectric layer and the material of an adjoining electrode due to direct contact. For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative capacitor structures and methods for producing same.	<SOH> SUMMARY <EOH>The above mentioned problems with capacitors and associated memory devices, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Embodiments of the invention include capacitors having a metal oxide buffer layer interposed between an electrode and a dielectric layer, and methods of their formation. The metal oxide buffer layer acts to reduce undesirable charge leakage from the capacitor. For one embodiment, the invention includes a capacitor. The capacitor includes two electrodes and a dielectric layer interposed therebetween. The capacitor further includes a metal oxide buffer layer interposed between the dielectric layer and one of the electrodes. For one embodiment, the bottom electrode, the top electrode or both electrodes contain metal nitride. For another embodiment, the dielectric layer contains at least one metal oxide dielectric material. For yet another embodiment, the metal oxide buffer layer contains a metal oxide having a composition of the form MO x . The metal component M may be a refractory metal. In one embodiment of the invention, the refractory metal is tungsten (W). In one embodiment, the electrode adjacent the buffer layer also includes tungsten. In another embodiment of the invention, the dielectric layer is a metal oxide. For another embodiment, the invention includes a method of forming a capacitor. The method includes forming a metal oxide buffer layer adjacent of the electrode layers. In one embodiment, the method includes forming a first electrode layer, forming the metal oxide buffer layer adjacent on the first electrode layer, forming a dielectric layer on the metal oxide buffer layer, and forming a second electrode layer on the dielectric layer. In one embodiment of the invention, the method includes oxidizing the first electrode to form a thin metal oxide buffer layer. In another embodiment of the invention, the thin buffer layer is annealed to further reduce capacitor leakage. In another embodiment of the invention, the anneal temperature of the buffer layer is about 700 degrees. In another embodiment, the buffer layer is annealed for about one minute. Further embodiments of the invention include semiconductor structures and methods of varying scope, as well as apparatus, devices, modules and systems making use of such semiconductor structures and methods.	This application is a Continuation of U.S. application Ser. No. 10/215,462 filed Aug. 9, 2002, which is a Divisional of U.S. application Ser. No. 09/745,114, filed Dec. 20, 2000. These applications are incorporated herein by reference. TECHNICAL FIELD The present invention relates generally to metal-insulator-metal semiconductor capacitors, and in particular to development of semiconductor capacitor structures having a buffer layer, and apparatus including such capacitor structures. BACKGROUND Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor typically includes two conductive electrodes separated by a dielectric layer. The charge stored across the capacitor is representative of a data bit and can be either a high voltage or a low voltage. Data is stored in the memory cells during a write mode and retrieved from the memory cells during a read mode. The data is transmitted on signal lines, sometimes referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of a digit line pair through an access transistor. Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells, i.e the charge stored in the associated capacitor, are shared with their associated digit lines, and data is sensed and latched to the digit line pairs. As DRAMs increase in memory cell density by decreasing memory cell area, there is an ongoing challenge to maintain sufficiently high storage capacitance despite decreasing memory cell area and its accompanying capacitor area, since capacitance is generally a function of electrode area. Additionally, there is a continuing goal to further decrease memory cell area. A principal method of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. One common form of stacked capacitor structure is a cylindrical container stacked capacitor, with a container structure forming the bottom electrode of the capacitor. Such container structures may have shapes differing from a substantially cylindrical form, such as an oval or other three-dimensional container. The container structures may further incorporate fins. Another method of increasing cell capacitance is through the use of high dielectric constant material in the dielectric layer of the capacitor. In order to achieve the charge storage efficiency generally needed in 256 megabit (Mb) memories and above, materials having a high dielectric constant, and typically dielectric constants greater than 20, can be used in the dielectric layer between the bottom electrode and the top electrode of the capacitor. The dielectric constant is a characteristic value of a material and is generally defined as the ratio of the amount of charge that can be stored in the material when it is interposed between two electrodes relative to the charge that can be stored when the two electrodes are separated by a vacuum. Unfortunately, high dielectric constant materials are often incompatible with existing processes. One cause of such incompatibility can be adverse chemical reactions or oxygen diffusion between the material of the dielectric layer and the material of an adjoining electrode due to direct contact. For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative capacitor structures and methods for producing same. SUMMARY The above mentioned problems with capacitors and associated memory devices, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Embodiments of the invention include capacitors having a metal oxide buffer layer interposed between an electrode and a dielectric layer, and methods of their formation. The metal oxide buffer layer acts to reduce undesirable charge leakage from the capacitor. For one embodiment, the invention includes a capacitor. The capacitor includes two electrodes and a dielectric layer interposed therebetween. The capacitor further includes a metal oxide buffer layer interposed between the dielectric layer and one of the electrodes. For one embodiment, the bottom electrode, the top electrode or both electrodes contain metal nitride. For another embodiment, the dielectric layer contains at least one metal oxide dielectric material. For yet another embodiment, the metal oxide buffer layer contains a metal oxide having a composition of the form MOx. The metal component M may be a refractory metal. In one embodiment of the invention, the refractory metal is tungsten (W). In one embodiment, the electrode adjacent the buffer layer also includes tungsten. In another embodiment of the invention, the dielectric layer is a metal oxide. For another embodiment, the invention includes a method of forming a capacitor. The method includes forming a metal oxide buffer layer adjacent of the electrode layers. In one embodiment, the method includes forming a first electrode layer, forming the metal oxide buffer layer adjacent on the first electrode layer, forming a dielectric layer on the metal oxide buffer layer, and forming a second electrode layer on the dielectric layer. In one embodiment of the invention, the method includes oxidizing the first electrode to form a thin metal oxide buffer layer. In another embodiment of the invention, the thin buffer layer is annealed to further reduce capacitor leakage. In another embodiment of the invention, the anneal temperature of the buffer layer is about 700 degrees. In another embodiment, the buffer layer is annealed for about one minute. Further embodiments of the invention include semiconductor structures and methods of varying scope, as well as apparatus, devices, modules and systems making use of such semiconductor structures and methods. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an elevation view of a layout of a portion of a memory array of a memory device according to the teachings of the present invention. FIGS. 2A-2I are cross-sectional views of a portion of the memory device of FIG. 1 at various processing stages according to the teachings of the present invention. FIG. 3 is a block diagram of an integrated circuit memory device. FIG. 4 is an elevation view of a wafer containing semiconductor dies. FIG. 5 is a block diagram of a circuit module. FIG. 6 is a block diagram of a memory module. FIG. 7 is a block diagram of a electronic system. FIG. 8 is a block diagram of a memory system. FIG. 9 is a block diagram of a computer system. FIG. 10 is a graph of capacitor leakage versus capacitance for three different annealing temperatures. FIG. 11 is an X-ray diffraction spectra of O3 annealed WNx at different temperatures. FIG. 12 is a graph of the impact of backend annealing in H2 on performance of a capacitor according to the present invention. DESCRIPTION OF THE EMBODIMENTS In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any base semiconductor structure. Both wafer and substrate are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions on the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The following description will be illustrated in the context of semiconductor container capacitors, and in particular, container capacitor memory cells for dynamic memory devices. It will be apparent to those skilled in the art that other capacitor structures, e.g., trench capacitors and parallel plate capacitors, are suitable for use with the various embodiments of the invention. It will further be apparent to those skilled in the art that the capacitor structures described herein and their methods of fabrication can be adapted to a variety of integrated circuit devices and applications, some of which may be apart from memory devices. Accordingly, the structures of the present invention described herein are not limited to the example embodiments. FIG. 1 depicts the general layout of a portion of a memory array of a memory device in accordance with one embodiment of the invention. The memory array includes container capacitor memory cells 200 formed overlying active areas 208. Active areas 208 are separated by field isolation regions 210. Active areas 208 and field isolation regions 210 are formed overlying a semiconductor substrate. The memory cells 200 are arrayed substantially in rows and columns. Shown in FIG. 1 are portions of three rows 201A, 201B and 201C, collectively 201. Separate digit lines (not shown) would be formed overlying each row 201 and coupled to active areas 208 through digit line contacts 206. Word lines 202 and 204 are further coupled to active areas 208, with word lines 202 coupled to active areas 208 in row 201B and word lines 204 coupled to active areas 208 in rows 201A and 201C. The word lines 202 and 204, coupled to memory cells in this alternating fashion, generally define the columns of the memory array. This folded bit-line architecture is known to one of ordinary skill for permitting higher densities of memory cells 200 on a substrate. FIGS. 2A-2I depict one embodiment of a portion of the processing to fabricate the memory device of FIG. 1. FIGS. 2A-2I are cross-sectional views taken along line A-A′ of FIG. 1 during various processing stages. In FIG. 2A, field isolation regions 210 are formed on a substrate 205. Substrate 205 may be a silicon substrate, such as a P-type silicon substrate. Field isolation regions 210 are generally formed of an insulator material, such as silicon oxides, silicon nitrides or silicon oxynitrides. For this embodiment, field isolation regions 210 are formed of silicon dioxide such as by conventional local oxidation of silicon (LOCOS) which creates substantially planar regions of oxide on the substrate surface. Active areas 208 are those areas not covered by the field isolation regions 210 on substrate 205. The creation of the field isolation regions 210 is preceded or followed by the formation of a gate dielectric layer 212. For this embodiment, gate dielectric layer 212 is a thermally grown silicon dioxide, but may be other insulator materials described herein or known in the art. Following the creation of the field isolation regions 210 and gate dielectric layer 212, a first conductively doped gate polysilicon layer 216, a gate barrier layer 218, a gate conductor layer 220, a gate cap layer 222 and gate spacers 214 are formed by methods known in the art. Gate barrier layer 218 may be a metal nitride, such as titanium nitride or tungsten nitride. Gate conductor layer 220 may be any conductive material, for example a metal. Gate cap layer 222 is often silicon nitride while gate spacers 214 are generally of an insulator material such as silicon oxide, silicon nitride and silicon oxynitride. The foregoing layers are patterned to form word lines 202 and 204 as gates for field effect transistors (FET), which FET's are one type of access devices to a data storage unit (capacitor) in a memory cell. The construction of the word lines 202 and 204 are illustrative only. As a further example, the construction of the word lines 202 and 204 may include a refractory metal silicide layer overlying a polysilicon layer. The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are generally recognized as refractory metals. Other constructions for word lines 202 and 204 are known to those skilled in the art. Source/drain regions 228 are formed in the substrate 205 such as by conductive doping of the substrate. Source/drain regions have a conductivity opposite the substrate 205. For a P-type substrate, source/drain regions 228 would have an N-type conductivity. Such conductive doping may be accomplished through ion implantation of phosphorus or arsenic for this embodiment. As is often the case, source/drain regions 228 include lightly-doped regions 230 created by differential levels of ion concentration or even differing dopant ions. Word lines 202 and 204 are adapted to be coupled to periphery contacts (not shown). The periphery contacts are located at the end of the memory array and are adapted for electrical communication with external circuitry. The formation of the word lines 202 and 204 as described are an example of one application to be used in conjunction with various embodiments of the invention. Other methods of fabrication and other applications are also feasible and perhaps equally viable. For clarity and to focus on the formation of the capacitor structures, many of the reference numbers are eliminated from subsequent drawings, e.g., those pertaining to the structure of the word lines and the source/drain regions. In FIG. 2B, a thick insulating layer 235 is deposited overlying substrate 205, as well as word lines 202 and 204, field isolation regions 210 and active areas 208. Insulating layer 235 is an insulator material such as silicon oxide, silicon nitride and silicon oxynitride materials. For one embodiment, insulating layer 235 is a doped insulator material such as borophosphosilicate glass (BPSG), a boron and phosphorous-doped silicon oxide. It is understood that other insulating materials known to those of skill in the art may be used. The insulating layer 235 is planarized, such as by chemical-mechanical planarization (CMP), in order to provide a uniform height. A mask 237 is formed overlying insulating layer 235 and patterned to define future locations of capacitors. In FIG. 2C, portions of insulating layer 235 exposed by patterned mask 237 are removed and mask 237 is subsequently removed. The portions of insulating layer 235 may be removed by etching or other suitable removal technique known to those skilled in the art. Removal techniques are generally dependent upon the material of construction of the layer to be removed as well as the surrounding layers to be retained. Patterning of insulating layer 235 creates openings having bottom portions 236A overlying exposed portions of the substrate 205 and sidewalls 236B defined by the insulating layer 235. In FIG. 2D, a layer of doped polysilicon is formed overlying exposed portions of active area 208 and top portions of insulating layer 235 to form contact layer 240. Contact layer 240 may be formed by controlled deposition of polysilicon as shown in FIG. 2D. Alternatively, contact layer 240 may be blanket deposited polysilicon followed by an etch-back to leave a layer of polysilicon overlying exposed portions of active area 208 between word lines 202 and 204. For still further embodiments, contact layer 240 is formed from tungsten, titanium nitride, tungsten nitrides, tantalum nitride, aluminum or other conductive materials, metals or alloys. In FIG. 2E, the portions of contact layer 240 overlying insulating layer 235 are removed leaving contacts 240 between the word lines 202 and 204. A bottom electrode 245 is formed overlying the contacts 240 and insulating layer 235. Bottom electrode 245 is any conductive material. For one embodiment, bottom electrode 245 contains a metal nitride. For another embodiment, the metal component of the bottom electrode 245 is a refractory metal, resulting in a refractory metal nitride. For yet another embodiment, bottom electrode 245 contains tungsten nitride (WNn; 0≦n≦=6). Bottom electrode 245 may be formed by any method, such as collimated sputtering, chemical vapor deposition (CVD) or other deposition techniques. In the case of a metal nitride material, bottom electrode 245 may be deposited as a metal layer followed by nitridation. Bottom electrode 245 forms the bottom conductive layer or electrode of the capacitor. For one embodiment, the bottom conductive layer has a closed bottom and sidewalls extending up from the closed bottom as shown in FIG. 2E. For another embodiment, the bottom conductive layer has a substantially planar surface as in a parallel plate capacitor. Bottom electrode 245 may contain more than one conductive layer, e.g., a metal nitride layer overlying a metal silicide layer. Subsequent annealing of the memory device may produce a reaction between bottom electrode 245 and contact 240 such that an interface layer is formed. As an example, where bottom electrode 245 contains a refractory metal or refractory metal nitride, and contact 240 contains polysilicon, subsequent annealing can produce a refractory metal silicide interface between bottom electrode 245 and contact 240. Such metal silicide interface layers are often advantageous in reducing electrical resistance to contact 240. In FIG. 2F, a buffer layer 250 is formed overlying bottom electrode 245. The buffer layer 250 is shown to be directly adjoining bottom electrode 245. But buffer layer 250 is not shown to scale relative to bottom electrode 245 for convenience and clarity of illustration. Buffer layer 250 is a metal oxide material having a composition of the form MOx. In one embodiment, the metal component M is a refractory metal. The refractory metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V) and zirconium (Zr) are included in this definition. For one embodiment, buffer layer 250 contains a tungsten oxide material (WOx). Metal oxide buffer layers can act to reduce capacitor leakage. Benefits may be derived by matching the metal oxide buffer layer to the adjacent metal nitride electrode. For example, the WOx buffer layer 250 can be grown by oxidizing the WNx bottom electrode layer 245. Accordingly, the metal component of the metal oxide buffer layer 250 and the metal component of the metal nitride of bottom electrode 245 are both tungsten. Such matching of the buffer layer to the electrode can be utilized to reduce stress between the two layers, thus improving device reliability. Furthermore, such matching allows formation of bottom electrode 245 and buffer layer 250 using a single deposition process along with an oxidation process. For one embodiment, buffer layer 250 is formed from the bottom electrode 245 containing metal nitride. For this embodiment, the metal nitride of the bottom electrode 245 is oxidized to form the metal oxide. Such oxidation may use a variety of techniques including oxidation in an ambient containing O2 or ozone (O3), with or without the help of plasma, or UV light or remote plasma. Controlled oxidation of the metal nitride can be used to form the metal oxide buffer layer 250, at the upper, exposed surface of bottom electrode 245. For a further embodiment, buffer layer 250 is grown by oxidizing a WNx bottom electrode 245 in an oxygen-containing ambient thereby using tungsten at the surface of the bottom electrode to grow a WO3 buffer layer. In one embodiment, the buffer layer 250 is grown in an O2 or O3 ambient at a temperature in the range of 300 to 550 degrees Celsius. The buffer layer 250 may be grown with or without a plasma in the environment. The bottom electrode 245 now includes W2N film adjacent the WO3 buffer layer 250 due to the oxidation process. In one embodiment, buffer layer 250, bottom electrode 245 and substrate are annealed at a temperature of at least 700 degrees Celsius in an inert gas ambient. The inert gases include, but are not limited to, N2, Ar, or He. The buffer layer is believed to have an orthorhomic crystalline structure due to the high temperature anneal. In FIG. 2G, a dielectric layer 255 is formed overlying buffer layer 250. The dielectric layer 255 is shown to be adjoining buffer layer 250, but there is no prohibition to forming additional layers interposed between dielectric layer 255 and buffer layer 250 as same may be suitable in some applications of the present invention. Note, however, that the nature of any additional layer may adversely affect performance of the resulting capacitor such as creating an undesirable series capacitance. Dielectric layer 255 contains a dielectric material. For one embodiment, dielectric layer 255 contains at least one metal oxide dielectric material. For another embodiment, dielectric layer 255 contains a Tantalum Oxide, such as Ta2O5. Dielectric layer 255 may be deposited by any deposition technique, e.g., RF-magnetron sputtering, chemical vapor deposition (CVD). As one example, a metal oxide, e.g., tantalum oxide, may be formed by depositing a layer of the metal component, e.g., tantalum, followed by annealing in an oxygen-containing ambient. As another example, the metal oxide may be deposited by metal organic chemical vapor deposition (MOCVD). Subsequent to formation, dielectric layer 255 may be annealed in an oxygen-containing ambient, such as an ambient containing O2 or ozone, at a temperature within the range of approximately 200 to 800° C. The actual oxygen-containing ambient, concentration of oxygen species and annealing temperature may vary for the specific dielectric deposited. These variations are known to those skilled in the art. Bottom electrode 245 is generally not oxidized, or is only marginally oxidized, during formation or subsequent processing of dielectric layer 255 due to the protection from the oxygen-containing ambient and diffusion of oxygen as provided by buffer layer 250. However, insulators generally create a series capacitance of the buffer layer and the dielectric layer. Such series capacitance can detrimentally impact the overall capacitance of the capacitor structure when the insulative buffer layer has a dielectric constant less than that of the dielectric layer. Accordingly, the buffer layer has a dielectric constant greater than the dielectric constant of the dielectric layer. For example, the WO3 buffer layer has a dielectric constant of about 300 and a Ta2O5 dielectric layer has a dielectric constant of about 20-25. Accordingly, the dielectric layer determines the capacitance with little detrimental effect, e.g. series capacitance, by the buffer layer. In FIG. 2H, a top electrode 265 is deposited to form the top conductive layer or electrode of the capacitor. The top electrode 265 is shown to be directly adjoining dielectric layer 255, but there is no prohibition to forming additional conductive layers interposed between the top electrode 265 and dielectric layer 255. Top electrode 265 may be of any conductive material and generally follows the same guidelines as bottom electrode 245. For one embodiment, top electrode 265 contains Pt—Rh deposited by CVD. Layers 245 through 270 are then patterned by techniques known in the art to define capacitors of memory cells 200 in FIG. 2I. In addition, the figures were used to aid the understanding of the accompanying text. However, the figures are not drawn to scale and relative sizing of individual features and layers are not necessarily indicative of the relative dimensions of such individual features or layers in application. As an example, while bottom electrode 245 is drawn to have an illustrated thickness of approximately the same as dielectric layer 255, for purposes of clarity and convenience, bottom electrode 245 may have a physical thickness of five times that of dielectric layer 255 in some applications. In one embodiment, bottom electrode 245 has a thickness of about 200-400 Å. In one embodiment, the buffer layer has a thickness of about 50-150 Å. In one embodiment, the dielectric layer 255 has a thickness of about 60-100 Å. In one embodiment, the top electrode 265 has a thickness of about 200-800 Å. One of ordinary skill in the art will understand upon reading the disclosure the suitable thicknesses of such layers for carrying out the present invention. Accordingly, the drawings are not to be used for dimensional characterization. While the foregoing embodiments of capacitor structures may be used in a variety of integrated circuit devices, they are particularly suited for use as storage capacitors of memory cells found in dynamic memory devices. Memory Devices FIG. 3 is a simplified block diagram of a memory device according to one embodiment of the invention. The memory device 300 includes an array of memory cells 302, address decoder 304, row access circuitry 306, column access circuitry 308, control circuitry 310, and Input/Output circuit 312. The memory can be coupled to an external microprocessor 314, or memory controller for memory accessing. The memory receives control signals from the processor 314, such as WE, RAS and CAS* signals. The memory is used to store data which is accessed via I/O lines. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of FIG. 3 has been simplified to help focus on the invention. At least one of the memory cells or associated circuitry has a capacitor in accordance with the present invention. It will be understood that the above description of a DRAM (Dynamic Random Access Memory) is intended to provide a general understanding of the memory and is not a complete description of all the elements and features of a DRAM. Further, the invention is equally applicable to any size and type of memory circuit and is not intended to be limited to the DRAM described above. Other alternative types of devices include SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well as Synchlink or Rambus DRAMs and other emerging DRAM technologies. As recognized by those skilled in the art, memory devices of the type described herein are generally fabricated as an integrated circuit containing a variety of semiconductor devices. The integrated circuit is supported by a substrate. Integrated circuits are typically repeated multiple times on each substrate. The substrate is further processed to separate the integrated circuits into dies as is known in the art. Semiconductor Dies With reference to FIG. 4, for one embodiment, a semiconductor die 410 is produced from a wafer 400. A die is an individual pattern, typically rectangular, on a substrate that contains circuitry, or integrated circuit devices, to perform a specific function. A semiconductor wafer will typically contain a repeated pattern of such dies containing the same functionality. Die 410 may contain circuitry for the inventive memory device, as discussed above. Die 410 may further contain additional circuitry to extend to such complex devices as a monolithic processor with multiple functionality. Die 410 is typically packaged in a protective casing (not shown) with leads extending therefrom (not shown) providing access to the circuitry of the die for unilateral or bilateral communication and control. Each die 410 may contain at least one of the capacitors according to the present invention. Circuit Modules As shown in FIG. 5, two or more dies 410 may be combined, with or without protective casing, into a circuit module 500 to enhance or extend the functionality of an individual die 410. Circuit module 500 may be a combination of dies 410 representing a variety of functions, or a combination of dies 410 containing the same functionality. One or more dies 410 of circuit module 500 contain at least one capacitor in accordance with the invention. Some examples of a circuit module include memory modules, device drivers, power modules, communication modems, processor modules and application-specific modules, and may include multilayer, multichip modules. Circuit module 500 may be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft and others. Circuit module 500 will have a variety of leads 410 extending therefrom and coupled to the dies 410 providing unilateral or bilateral communication and control. FIG. 6 shows one embodiment of a circuit module as memory module 600. Memory module 600 contains multiple memory devices 610 contained on support 615, the number generally depending upon the desired bus width and the desire for parity. Memory module 600 accepts a command signal from an external controller (not shown) on a command link 620 and provides for data input and data output on data links 630. The command link 620 and data links 630 are connected to leads 640 extending from the support 615. Leads 640 are shown for conceptual purposes and are not limited to the positions shown in FIG. 6. At least one of the memory devices 610 contains a capacitor according to the present invention. Electronic Systems FIG. 7 shows one embodiment of an electronic system 700 containing one or more circuit modules 500. Electronic system 700 generally contains a user interface 710. User interface 710 provides a user of the electronic system 700 with some form of control or observation of the results of the electronic system 700. Some examples of user interface 710 include the keyboard, pointing device, monitor or printer of a personal computer; the tuning dial, display or speakers of a radio; the ignition switch, gauges or gas pedal of an automobile; and the card reader, keypad, display or currency dispenser of an automated teller machine. User interface 710 may further describe access ports provided to electronic system 700. Access ports are used to connect an electronic system to the more tangible user interface components previously exemplified. One or more of the circuit modules 500 may be a processor providing some form of manipulation, control or direction of inputs from or outputs to user interface 710, or of other information either preprogrammed into, or otherwise provided to, electronic system 700. As will be apparent from the lists of examples previously given, electronic system 700 will often be associated with certain mechanical components (not shown) in addition to circuit modules 500 and user interface 710. It will be appreciated that the one or more circuit modules 500 in electronic system 700 can be replaced by a single integrated circuit. Furthermore, electronic system 700 may be a subcomponent of a larger electronic system. It will also be appreciated that at least one of the memory modules 500 contains a capacitor according to the present invention. FIG. 8 shows one embodiment of an electronic system as memory system 800. Memory system 800 contains one or more memory modules 600 and a memory controller 810. The memory modules 600 each contain one or more memory devices 610. At least one of memory devices 610 contain a capacitor according to the present invention. Memory controller 810 provides and controls a bidirectional interface between memory system 800 and an external system bus 820. Memory system 800 accepts a command signal from the external bus 820 and relays it to the one or more memory modules 600 on a command link 830. Memory system 800 provides for data input and data output between the one or more memory modules 600 and external system bus 820 on data links 840. It will also be appreciated that at least one of the memory modules 600 contains a capacitor according to the present invention. FIG. 9 shows a further embodiment of an electronic system as a computer system 900. Computer system 900 contains a processor 910 and a memory system 800 housed in a computer unit 905. Computer system 900 is but one example of an electronic system containing another electronic system, i.e., memory system 800, as a subcomponent. Computer system 900 optionally contains user interface components. Depicted in FIG. 9 are a keyboard 1220, a pointing device 930, a monitor 940, a printer 950 and a bulk storage device 960. It will be appreciated that other components are often associated with computer system 900 such as modems, device driver cards, additional storage devices, etc. It will further be appreciated that the processor 910 and memory system 800 of computer system 900 can be incorporated on a single integrated circuit. Such single package processing units reduce the communication time between the processor and the memory circuit. It will be appreciated that at least one of the processor 910 and memory system 800 contain a capacitor according to the present invention. Test Results FIGS. 10-12 show results from various test wafers. The test wafers all include a deep container, high-k MIM capacitor formed of a WNx bottom electrode deposited by CVD on a substrate, an 80 Å Ta2O5 dielectric layer deposited by CVD, and a Pt—Rh alloy top electrode also deposited by CVD. A buffer layer is formed by oxidizing the WNx bottom electrode prior to depositing the dielectric layer. The test wafers were oxidized in an O3 ambient at 475 degrees Celsius for three minutes. The buffer layer comprises a WO3 layer and the bottom electrode includes a W2N layer adjacent the buffer layer. After creation of the WO3 buffer layer and before depositing the dielectric layer, the buffer layer/bottom electrode stack is annealed in an N2 ambient for one minute at various temperatures ranging from 500 to 700 degrees Celsius. The dielectric layer is deposited at 475 degrees Celsius in an O2 ambient. The Pt—Rh alloy top electrode is deposited according to techniques known to those of skill in the art. FIG. 10 shows capacitance and leakage measurements from three wafers having a plurality of MIM container capacitors. All capacitors were created according to the above method with the WO3 buffer layers and adjacent electrodes on each wafer being annealed at various temperatures. Test capacitors 1 (denoted as Δ) were created by annealing the WO3 buffer layer/electrode stack at a temperature of 500 degrees Celsius. Test capacitors 2 (denoted as □) were created by annealing the WO3 buffer layer/electrode stack at a temperature of 600 degrees Celsius. Test capacitors 3 (denoted as ♦) were created by annealing the WO3 buffer layer/electrode stack at a temperature of 700 degrees Celsius. As evident from the plotted data points representing leakage and capacitance, the higher temperature anneal represented by the test capacitors 3 (denoted as ♦) yields higher capacitance and lower leakage relative to the lower temperature anneal represented by test capacitors 1 and 2 (respectively denoted by Δ and □). FIG. 11 shows an X-ray diffraction spectra of two WO3 buffer layer samples. The lighter line represents a first sample which was annealed at a temperature of 650 degrees Celsius. The darker data line represents a second sample which was annealed at a temperature of 700 degrees Celsius. Both stacks were annealed in an N2 ambient for one minute. The graph further indicates the peaks of the W2N layer of the bottom, adjacent electrode. It is noted that the peaks of the W2N layer samples do not shift for the two annealing temperatures. The spectra shows that the WO3 peaks of the 700 degree annealed, second stack shift toward a lower 2-theta angle than the WO3 peaks of the 650 degree annealed, first stack. The shift was about 0.5 to 1 degree. As a result, it is identified that the 700 degree annealed buffer layer has an orthorhomic crystal structure, while the 650 degree annealed buffer layer has a monoclinic crystal structure. Orthorhomic structures are more stable at higher temperatures than monoclinic structures. Shifts in 2-theta angle can at times be attributed to film stress. However, the shift shown in FIG. 11 is believed to not be caused by film stress as the W2N peaks did not shift as a function of the different anneal temperatures. In one embodiment, the anneal temperature of the buffer layer/electrode stack is about 700 degrees Celsius. As discussed in conjunction with the test results, a higher anneal temperature of the buffer layer yields a capacitor with higher capacitance and lower leakage. It is believed that the high temperature anneal (at about, or greater than, 700 degrees Celsius) changes the phase of the WO3 lattice structure from a monoclinic crystalline structure to an orthorhomic crystalline structure, which is more stable than monoclinic lattice structures at higher temperatures. FIG. 12 graphically shows the effect of backend wafer processing on capacitor leakage. Integrated circuits that include transistors are sometimes subjected to backend processing which improves the reliability of the structures. Backend processing typically includes annealing the wafer in a hydrogen ambient, for example in an ambient of 10% hydrogen and 90% nitrogen. Such backend processing results in a more robust interface for the transistors. The sets of capacitors denoted by ⋄, +, and ◯ were not subjected to backend processing. The sets of capacitors denoted by □, Δ, and • were respectively fabricated in the same manner as sets of capacitors ⋄, +, and ◯ and then were subject to backend processing. All of the capacitors ⋄, +, ◯, □, Δ, and • have a structure as shown in FIG. 2I. The sets of capacitors denoted by ◯ and • had their bottom electrodes and buffer layers annealed at 750 degrees Celsius. The sets of capacitors denoted by + and Δ had their bottom electrodes and buffer layers annealed at 550 degrees Celsius. The sets of capacitors denoted by ⋄ and □ did not anneal their bottom electrodes and buffer layers. As shown in the graph of FIG. 12, the leakage of the capacitors which were not subject to backend processing is less than those capacitors which were subject to backend processing. But annealing the bottom electrode and buffer layer did reduce the leakage compared to not annealing. More specifically, the median leakage of capacitors •, which were annealed at 750 degrees Celsius, is about 70 fA. Whereas the median leakages for capacitors Δ and capacitors □, which were respectively annealed at 550 degrees Celsius and not annealed, are about 100 fA and 200 fA, respectively. Accordingly, the high temperature anneal of the buffer layer 250 and bottom electrode 245 resulted in capacitors which have less leakage than those annealed at lower temperatures or not annealed. It is believed that the capacitors which are subjected to the high temperature anneal (greater than 700 degrees Celsius, and in one embodiment at about 750 degrees Celsius) are more stable and thus less effected by the backend hydrogen anneal processing. The other capacitors (denoted by ⋄, +, and ◯) not subject to backend processing have a leakage which is less than the leakage of the capacitors subjected to backend processing. While not visible on the scale of FIG. 12, these capacitors follow the above findings that the capacitor with a buffer layer according to the present invention which is subject to a high temperature anneal has less leakage than the capacitors which were not subject to a high temperature anneal. It is foreseen that the present invention can be practiced with or without the backend processing. For example, it is possible to create the transistors on a wafer and then subject same to backend processing prior to creating the capacitors according to the present invention, e.g. capacitor over digit line structures. While the invention has been described and illustrated with respect to forming container capacitors for a memory cell, it should be apparent that substantially similar processing techniques can be used to form other container capacitors for other applications as well as other capacitor structures. As one example, capacitors formed in accordance with the methods described herein may be used as on-chip capacitors utilized to reduce lead impedance of a packaged integrated circuit chip. As further example, parallel plate or trench capacitors may be formed with a metal oxide barrier layer between a dielectric layer and an electrode. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. For example, other materials and shapes, as well as other deposition and removal processes, may be utilized in conjunction with the invention. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof. CONCLUSION Capacitor structures and methods of their manufacture have been described for use in integrated circuits. The capacitor structures include two electrodes and a dielectric layer interposed between the two electrodes. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and one of the electrodes. The metal oxide buffer layer acts to reduce leakage and yield higher capacitance. The capacitors are suited for use in memory cells and apparatus incorporating such memory cells, as well as in other integrated circuits.	H	67H01	185H01L	21	20
11858624	US20090079075A1-20090326	INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME	ACCEPTED	20090311	20090326	[]	H01L2352	["H01L2352", "H01L214763"]	8084862	20070920	20111227	257	758000	71595.0	HARRISTON	WILLIAM	[{"inventor_name_last": "Lin", "inventor_name_first": "Qinghuang", "inventor_city": "Yorktown Heights", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "Shyng-Tsong", "inventor_city": "Rensselaer", "inventor_state": "NY", "inventor_country": "US"}]	The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.	1. An interconnect structure comprising: at least one patterned and cured low-k dielectric material located on a surface of a patterned and cured antireflective coating located between said at least one patterned and cured low-k dielectric material and a substrate, said at least one cured and patterned low-k material and said patterned and cured antireflective coating having conductively filled regions embedded therein. 2. The interconnect structure of claim 1 further comprising a patterned dielectric cap located between said substrate and said patterned and cured antireflective coating. 3. The interconnect structure of claim 1 wherein said at least one patterned and cured low-k dielectric material comprises a cured functionalized polymer. 4. The interconnect structure of claim 3 wherein said cured functionalized polymer comprises a polymer of a hydrocarbon, a fluorinated hydrocarbon, a siloxane, a silane, a carbosilane, an oxycarbosilane, an organosilicate or a silsesquioxane. 5. The interconnect structure of claim 1 wherein said patterned and cured low-k material includes Si atoms bonded to cyclic rings via oxygen atoms. 6. An interconnect structure comprising: a lower patterned and cured low-k material layer located on a surface of a substrate, and an abutting upper patterned and cured low-k material layer located on said lower patterned and cured low-k material layer, said lower and upper patterned and cured low-k material layers having conductively filled regions and each of said cured and patterned low-k material layers has Si atoms bonded to cyclic rings via oxygen atoms. 7. The interconnect structure of claim 6 further comprising a patterned antireflective coating present on said lower patterned and cured low-k material. 8. The interconnect structure of claim 7 further comprising a patterned dielectric cap located between said substrate and said patterned antireflective coating. 9. The interconnect structure of claim 6 wherein said lower and upper patterned and cured low-k dielectric material layers each comprise a cured functionalized polymer. 10. The interconnect structure of claim 9 wherein said cured functionalized polymer comprises a polymer of a hydrocarbon, a fluorinated hydrocarbon, a siloxane, a silane, a carbosilane, an oxycarbosilane, an organosilicate or a silsesquioxane. 11. An interconnect structure comprising: a lower patterned and cured low-k material layer located on a surface of a substrate, and an abutting upper patterned and cured low-k material layer located on said lower patterned and cured low-k material layer, a patterned and cured antireflective coating located between said lower patterned and cured low-k dielectric material layer and said substrate, said lower and upper patterned and cured low-k material layers having conductively filled regions. 12. The interconnect structure of claim 11 further comprising a patterned dielectric cap located between said substrate and said patterned and cured antireflective coating. 13. A method of fabricating an interconnect structure comprising: providing at least one patternable low-k material on top of a substrate; forming at least one interconnect pattern within said at least one patternable low-k material, said at least one interconnect pattern is formed without utilizing a separate photoresist material; and curing said at least one patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. 14. The method of claim 13 wherein said substrate includes at least an antireflective coating located thereon, and said at least one patternable low-k material is provided on said antireflective coating. 15. The method of claim 13 wherein said at least one low-k material is a functionalized polymer having one or more irradiation/acid-sensitive imageable groups. 16. The method of claim 15 wherein said functionalized polymer comprises a polymer of a hydrocarbon, a fluorinated hydrocarbon, a siloxane, a silane, a carbosilane, an oxycarbosilane, an organosilicate or a silsesquioxane. 17. The method of claim 13 wherein said curing comprises a thermal cure, an electron beam cure, an UV cure, an ion beam cure, a plasma cure, a microwave cure or any combination thereof. 18. A method of fabricating a dual-damascene interconnect structure comprising: providing a first patternable low-k material on top of a substrate; forming first interconnect patterns within the first patternable low-k material; providing a second patternable low-k material on top of the first patternable low-k material including said first interconnect patterns; forming second interconnect patterns within said second patternable low-k material; and curing at least said second patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. 19. The method of claim 18 wherein the first interconnect patterns are vias, and said second interconnect patterns are lines, wherein each line is interconnect to a via. 20. The method of claim 18 wherein said substrate includes at least an antireflective coating located thereon, and said first patternable low-k material is provided on said antireflective coating. 21. The method of claim 18 wherein said first and second patternable low-k materials are the same or different and comprise functionalized polymers having one or more irradiation/acid-sensitive imageable groups. 22. The method of claim 21 wherein said functionalized polymers comprise polymers of hydrocarbons, fluorinated hydrocarbons, siloxanes, silanes, carbosilanes, oxycarbosilanes, organosilicates or silsesquioxanes. 23. The method of claim 18 wherein said curing at least said second patternable low-k material comprises a thermal cure, an electron beam cure, an UV cure, an ion beam cure, a plasma cure, a microwave cure or any combination thereof. 24. The method of claim 18 wherein said first patternable low-k material is a cured negative-tone material and said second patternable low-k material is a positive or negative-tone material. 25. The method of claim 18 wherein said first patternable low-k material is a cured positive-tone material and said second patternable low-k material is a positive or negative-tone material.	<SOH> BACKGROUND OF THE INVENTION <EOH>It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the interlayer dielectric (ILD) materials used to electrically insulate the metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays. State-of-the-art semiconductor chips employ copper (Cu) as the electrical conductor and inorganic organosilicates as the low dielectric constant (low-k) dielectric, and have up to twelve levels of Cu/low-k interconnect layers. These Cu/low-k interconnect layers are fabricated with an interactive additive process, called dual-damascene, which includes several processing steps. For example, a typical dual-damascene process includes film deposition, patterning by lithography and reactive ion etching, liner deposition, Cu metal fill by electrochemical plating, and chemical-mechanical polishing of excessive Cu metal; these steps are described in greater detail in the following paragraphs. When fabricating integrated circuit wiring within a multi-layered scheme, an insulating or dielectric material, e.g., silicon oxide or a low-k insulator will normally be patterned with several thousand openings to create conductive line openings and/or via openings using photo patterning and plasma etching techniques, e.g., photolithography with a photoresist subsequently followed by etching by plasma processes. The via openings are typically filled with a conductive metal material, e.g., aluminum, copper, etc., to interconnect the active and/or passive elements of the integrated circuits. The semiconductor device is then polished to level its surface. A continuous cap layer is then normally deposited over the planarized surface featuring the dielectric material and conductive metal material. Next, a dielectric material is deposited over the continuous cap layer, via and conductive line openings are created within the dielectric layer as before, another conductive metal material is deposited within the openings and another continuous cap layer is deposited thereon. The process is repeated to fabricate a multi-layer interconnect wiring system. The multi-layer interconnect system built thereby is referred to in the art as a dual-damascene integration scheme. Unfortunately, the strategy to introduce low-k materials (typically dielectrics whose dielectric constant is below that of silicon oxide) into advanced interconnects is difficult to implement due to the new materials chemistry of the low-k materials that are being introduced. Moreover, low-k dielectrics exhibit fundamentally weaker electrical and mechanical properties as compared to silicon oxide. Moreover, the low-k dielectric alternatives are typically susceptible to damage during the various interconnect processing steps. The damage observed in the low-k dielectric materials is manifested by an increase in the dielectric constant and increased moisture uptake, which may result in reduced performance and device reliability. One way to overcome the integration challenges of low-k materials is to protect these low-k dielectric materials by adding at least one sacrificial hardmask layer onto a surface of the low-k dielectric material. While the hardmask layer serves to protect the low-k material, the presence of the sacrificial hardmask layer adds enormous process complexity as more film deposition, pattern transfer etch, and removal of hardmask layers are needed. A state-of-the-art back-end-of-the-line (BEOL) integration process, called a low temperature oxide (LTO) process, employs up to eight layers of sacrificial hardmask materials to fabricate a two-layer dual-damascene interconnect structure. For example, a via-first LTO integration for forming a dual-damascene interconnect includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one via in said dielectric material, such that at least one of the vias is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the via; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one trench in the imaging material, barrier material and planarizing material, such that the at least one trench is positioned over the via; removing the imaging material, either after or concurrently with forming the trench in the planarizing material; transferring the at least one trench to the dielectric material, such that at least one of the trenches is positioned over the via; removing the barrier material, either after or concurrently with transferring the at least one trench to the dielectric material; and removing the planarizing material. A line-first LTO integration for forming a dual-damascene interconnect structure includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one trench in the dielectric material, such that the at least one trench is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the trench; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one via in the imaging material, barrier material and planarizing material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the imaging material, either after or concurrently with forming the via in the planarizing material; transferring the at least one via to the dielectric material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the barrier material, either after or concurrently with transferring the at least one via to the dielectric material; and removing the planarizing material. The integration schemes, such as the LTO one mentioned above, are very complex, inefficient, and costly. For example, the via-first LTO integration scheme requires ten layers of films and twenty-one process steps to form a two-layer dual-damascene dielectric structure. In other words, 80% of films are not needed in the final interconnect structure. Although immensely popular in semiconductor manufacturing, the prior art dual-damascene integration scheme described above suffers from several drawbacks including: (I) First, it constitutes a significant portion of manufacturing cost of advanced semiconductor chips as many layers, up to twelve layers for the state-of-the-art chips, are required to connect the minuscule transistors within a chip and to the printed circuit board. (II) Second, it is a main yield detractor as the many layers of films required to form the interconnects generate chances for defect introduction and, thus, degrade manufacturing yields. (III) Third, it is very inefficient and embodies enormous complexity. The current dual-damascene integration scheme requires many sacrificial films (80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating. (IV) Fourth, the performance gain by introduction of new lower-k materials is often offset by the needs for higher-k non-sacrificial materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. (V) Fifth, the prior art complex dual-damascene process lengthens manufacturing turn-around time and R&D development cycle. (VI) Sixth, the plasma etching process is an expensive and often unreliable process and requires significant up-front capital investment. In view of the above, there is a need to simplify the formation of interconnects (single-damascene and dual-damascene) including low-k dielectrics for cost-saving and manufacturing efficiency.	<SOH> SUMMARY OF THE INVENTION <EOH>The problems described above in prior art processes of fabricating interconnect (single-damascene and dual-damascene) structures are solved by using a dramatically simplified integration method of this invention. The present invention thus relates to a method of forming interconnect structures that are part of integrated circuits and microelectronic devices with patternable dielectrics. This invention circumvents the prior art drawbacks of current integration by combining the functions of a photoresist and a dielectric material into one material. This one material, called a photo-patternable low-k dielectric (or patternable low-k material for short), acts as a photoresist during the lithographic patterning process, and as such, no separate photoresist is required. After lithographic patterning, the patternable low-k dielectric is subsequently converted into a low-k material during a post patterning cure. In this way, the inventive method avoids plasma etching and the complex sacrificial film stack and processes required for conventional patterning. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable dielectric. In general terms and in one aspect of the present invention, a method is provided that comprises: providing at least one patternable low-k material on top of a substrate; forming at least one interconnect pattern within said at least one patternable low-k material, said at least one interconnect pattern is formed without utilizing a separate photoresist material; and curing said at least one patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the interconnect patterns. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured low-k material after filling the interconnect patterns with a conductive material. In any of the embodiments mentioned above, the interconnect patterns may comprise via openings, line openings, a combination of via openings located beneath line openings or a combination of line openings located beneath via openings. In one embodiment, it is preferred to have via openings located beneath line openings. It is noted that in the present invention each individual pair of line/via openings or via/line openings is interconnected. The present invention contemplates the use of positive-tone patternable low-k materials, negative-tone patternable low-k materials or any combination thereof. In another aspect of the present invention, the present invention provides a simplified method of fabricating dual-damascene low-k interconnect structures with at least one negative-tone patternable low-k dielectric and/or at least one positive-tone patternable low-k dielectric. This aspect of the present invention includes the steps of: providing a first patternable low-k material on top of a substrate; forming first interconnect patterns within the first patternable low-k material without utilizing a separate photoresist material; providing a second patternable low-k material on top of the first patternable low-k material including said first interconnect patterns; forming second interconnect patterns within said second patternable low-k material without utilizing a separate photoresist material; and curing at least said second patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the first patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the first patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the second interconnect patterns within the second patternable low-k material. In yet other embodiments of the present invention, a curing step is performed after providing the first interconnect patterns to the first patternable low-k material. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the first and second interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the first and second interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured second patternable low-k material after filling the first and second interconnect patterns with a conductive material. In any of the embodiments mentioned above, the first interconnect patterns may comprise via openings, while the second interconnect patterns may comprise line openings. This embodiment is a preferred over an embodiment in which the first interconnect patterns comprise line openings and the second interconnect patterns comprise via openings. This invention also relates to a simplified method of fabricating single-damascene low-k interconnect structures with negative-tone or positive-tone patternable low-k dielectrics. This aspect of the present invention comprises the steps of: providing a patternable low-k material on top of a substrate; forming interconnect patterns within the patternable low-k material without utilizing a separate photoresist material; and curing the patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the interconnect patterns within the patternable low-k material. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured patternable low-k material after filling the interconnect patterns with a conductive material. In any of the embodiments mentioned above, the interconnect patterns may comprise via openings or line openings. This patternable low-k method of the present invention dramatically reduces the complexity in the fabrication of current interconnect structures. The photoresist used in the prior art integration is no longer needed. In addition the present invention also does not utilize a plasma etching step for patterning as also required in the prior art interconnect processing schemes. It is further noted that the inventive method reduces the number of layers required to fabricate the interconnect structure and, as such, the present invention reduces the time and cost of fabricating interconnect structures as compared to prior art processes. In addition to the methods described above, the present invention also relates to interconnect structures which include the patternable low-k dielectric material in a cured state; in the cured state the patternable low-k material serves as the interconnect dielectric. In general terms, the present invention provides an interconnect structure comprising at least one patterned and cured low-k dielectric material located on a surface of a substrate, said at least one patterned and cured low-k film having conductively filled regions embedded therein and including Si atoms bonded to cyclic rings via oxygen atoms. In one embodiment, a dual-damascene interconnect structure including first and second cured and patterned low-k materials each having the above mentioned Si bonding environment present is provided. In yet another embodiment of the present invention, a single-damascene interconnect structure is provided. In yet another embodiment of the present invention, an antireflective coating that is patterned is located between the substrate and the cured and patterned low-k film. In a further embodiment of the present invention a dielectric cap layer is located on top of the substrate. In still another embodiment of the present invention, another dielectric cap can be present atop the patterned low-k film. In yet another embodiment of the present invention, the conductively filled regions comprise Al, Cu or a Cu alloy. In an even further embodiment of the present invention, the conductively filled regions comprise a single via, a single line, a combined via/line or a combined line/via.	FIELD OF THE INVENTION The present invention relates to an interconnect structure and a method of fabricating interconnect structures. Specifically, the present invention relates to interconnect structures that are part of integrated circuits and microelectronic devices with patternable dielectrics and a method of fabricating the same. More specifically, the present invention relates to single-damascene or dual-damascene low-k interconnect structures with a positive-tone or a negative-tone patternable dielectric and methods of fabricating the same. BACKGROUND OF THE INVENTION It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Throughout the semiconductor industry, there has been a strong drive to reduce the dielectric constant, k, of the interlayer dielectric (ILD) materials used to electrically insulate the metal lines. As a result, interconnect signals travel faster through conductors due to a reduction in resistance-capacitance (RC) delays. State-of-the-art semiconductor chips employ copper (Cu) as the electrical conductor and inorganic organosilicates as the low dielectric constant (low-k) dielectric, and have up to twelve levels of Cu/low-k interconnect layers. These Cu/low-k interconnect layers are fabricated with an interactive additive process, called dual-damascene, which includes several processing steps. For example, a typical dual-damascene process includes film deposition, patterning by lithography and reactive ion etching, liner deposition, Cu metal fill by electrochemical plating, and chemical-mechanical polishing of excessive Cu metal; these steps are described in greater detail in the following paragraphs. When fabricating integrated circuit wiring within a multi-layered scheme, an insulating or dielectric material, e.g., silicon oxide or a low-k insulator will normally be patterned with several thousand openings to create conductive line openings and/or via openings using photo patterning and plasma etching techniques, e.g., photolithography with a photoresist subsequently followed by etching by plasma processes. The via openings are typically filled with a conductive metal material, e.g., aluminum, copper, etc., to interconnect the active and/or passive elements of the integrated circuits. The semiconductor device is then polished to level its surface. A continuous cap layer is then normally deposited over the planarized surface featuring the dielectric material and conductive metal material. Next, a dielectric material is deposited over the continuous cap layer, via and conductive line openings are created within the dielectric layer as before, another conductive metal material is deposited within the openings and another continuous cap layer is deposited thereon. The process is repeated to fabricate a multi-layer interconnect wiring system. The multi-layer interconnect system built thereby is referred to in the art as a dual-damascene integration scheme. Unfortunately, the strategy to introduce low-k materials (typically dielectrics whose dielectric constant is below that of silicon oxide) into advanced interconnects is difficult to implement due to the new materials chemistry of the low-k materials that are being introduced. Moreover, low-k dielectrics exhibit fundamentally weaker electrical and mechanical properties as compared to silicon oxide. Moreover, the low-k dielectric alternatives are typically susceptible to damage during the various interconnect processing steps. The damage observed in the low-k dielectric materials is manifested by an increase in the dielectric constant and increased moisture uptake, which may result in reduced performance and device reliability. One way to overcome the integration challenges of low-k materials is to protect these low-k dielectric materials by adding at least one sacrificial hardmask layer onto a surface of the low-k dielectric material. While the hardmask layer serves to protect the low-k material, the presence of the sacrificial hardmask layer adds enormous process complexity as more film deposition, pattern transfer etch, and removal of hardmask layers are needed. A state-of-the-art back-end-of-the-line (BEOL) integration process, called a low temperature oxide (LTO) process, employs up to eight layers of sacrificial hardmask materials to fabricate a two-layer dual-damascene interconnect structure. For example, a via-first LTO integration for forming a dual-damascene interconnect includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one via in said dielectric material, such that at least one of the vias is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the via; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one trench in the imaging material, barrier material and planarizing material, such that the at least one trench is positioned over the via; removing the imaging material, either after or concurrently with forming the trench in the planarizing material; transferring the at least one trench to the dielectric material, such that at least one of the trenches is positioned over the via; removing the barrier material, either after or concurrently with transferring the at least one trench to the dielectric material; and removing the planarizing material. A line-first LTO integration for forming a dual-damascene interconnect structure includes the steps of: depositing a dielectric material on a substrate including a patterned conductor; forming at least one trench in the dielectric material, such that the at least one trench is positioned over the patterned conductor; depositing a layer of planarizing material on the dielectric material and in the trench; depositing a layer of barrier material on the layer of planarizing material; depositing at least one layer of imaging material on the layer of barrier material; forming at least one via in the imaging material, barrier material and planarizing material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the imaging material, either after or concurrently with forming the via in the planarizing material; transferring the at least one via to the dielectric material, such that at least one of the vias is positioned over the trench and the patterned conductor; removing the barrier material, either after or concurrently with transferring the at least one via to the dielectric material; and removing the planarizing material. The integration schemes, such as the LTO one mentioned above, are very complex, inefficient, and costly. For example, the via-first LTO integration scheme requires ten layers of films and twenty-one process steps to form a two-layer dual-damascene dielectric structure. In other words, 80% of films are not needed in the final interconnect structure. Although immensely popular in semiconductor manufacturing, the prior art dual-damascene integration scheme described above suffers from several drawbacks including: (I) First, it constitutes a significant portion of manufacturing cost of advanced semiconductor chips as many layers, up to twelve layers for the state-of-the-art chips, are required to connect the minuscule transistors within a chip and to the printed circuit board. (II) Second, it is a main yield detractor as the many layers of films required to form the interconnects generate chances for defect introduction and, thus, degrade manufacturing yields. (III) Third, it is very inefficient and embodies enormous complexity. The current dual-damascene integration scheme requires many sacrificial films (80% of the film stack) to pattern and protect the fragile interlayer dielectric films from damage during processing. These sacrificial patterning and protective films have to be removed after patterning and copper plating. (IV) Fourth, the performance gain by introduction of new lower-k materials is often offset by the needs for higher-k non-sacrificial materials, such as a cap layer, a hardmask layer, or a thicker copper barrier layer. (V) Fifth, the prior art complex dual-damascene process lengthens manufacturing turn-around time and R&D development cycle. (VI) Sixth, the plasma etching process is an expensive and often unreliable process and requires significant up-front capital investment. In view of the above, there is a need to simplify the formation of interconnects (single-damascene and dual-damascene) including low-k dielectrics for cost-saving and manufacturing efficiency. SUMMARY OF THE INVENTION The problems described above in prior art processes of fabricating interconnect (single-damascene and dual-damascene) structures are solved by using a dramatically simplified integration method of this invention. The present invention thus relates to a method of forming interconnect structures that are part of integrated circuits and microelectronic devices with patternable dielectrics. This invention circumvents the prior art drawbacks of current integration by combining the functions of a photoresist and a dielectric material into one material. This one material, called a photo-patternable low-k dielectric (or patternable low-k material for short), acts as a photoresist during the lithographic patterning process, and as such, no separate photoresist is required. After lithographic patterning, the patternable low-k dielectric is subsequently converted into a low-k material during a post patterning cure. In this way, the inventive method avoids plasma etching and the complex sacrificial film stack and processes required for conventional patterning. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable dielectric. In general terms and in one aspect of the present invention, a method is provided that comprises: providing at least one patternable low-k material on top of a substrate; forming at least one interconnect pattern within said at least one patternable low-k material, said at least one interconnect pattern is formed without utilizing a separate photoresist material; and curing said at least one patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the interconnect patterns. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured low-k material after filling the interconnect patterns with a conductive material. In any of the embodiments mentioned above, the interconnect patterns may comprise via openings, line openings, a combination of via openings located beneath line openings or a combination of line openings located beneath via openings. In one embodiment, it is preferred to have via openings located beneath line openings. It is noted that in the present invention each individual pair of line/via openings or via/line openings is interconnected. The present invention contemplates the use of positive-tone patternable low-k materials, negative-tone patternable low-k materials or any combination thereof. In another aspect of the present invention, the present invention provides a simplified method of fabricating dual-damascene low-k interconnect structures with at least one negative-tone patternable low-k dielectric and/or at least one positive-tone patternable low-k dielectric. This aspect of the present invention includes the steps of: providing a first patternable low-k material on top of a substrate; forming first interconnect patterns within the first patternable low-k material without utilizing a separate photoresist material; providing a second patternable low-k material on top of the first patternable low-k material including said first interconnect patterns; forming second interconnect patterns within said second patternable low-k material without utilizing a separate photoresist material; and curing at least said second patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the first patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the first patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the second interconnect patterns within the second patternable low-k material. In yet other embodiments of the present invention, a curing step is performed after providing the first interconnect patterns to the first patternable low-k material. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the first and second interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the first and second interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured second patternable low-k material after filling the first and second interconnect patterns with a conductive material. In any of the embodiments mentioned above, the first interconnect patterns may comprise via openings, while the second interconnect patterns may comprise line openings. This embodiment is a preferred over an embodiment in which the first interconnect patterns comprise line openings and the second interconnect patterns comprise via openings. This invention also relates to a simplified method of fabricating single-damascene low-k interconnect structures with negative-tone or positive-tone patternable low-k dielectrics. This aspect of the present invention comprises the steps of: providing a patternable low-k material on top of a substrate; forming interconnect patterns within the patternable low-k material without utilizing a separate photoresist material; and curing the patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3. In some embodiments of this method of the present invention, an antireflective coating is formed on the substrate prior to forming the patternable low-k material. In another embodiment of the present invention, a material stack comprising a dielectric cap and an antireflective coating is formed on top of the substrate prior to forming the patternable low-k material. When such materials are present, the present invention also contemplates a step of forming contact holes through the antireflective coating or material stack after forming the interconnect patterns within the patternable low-k material. In yet a further embodiment of the present invention, a conductive material such as Al, Cu, or a Cu alloy is formed into the interconnect patterns. A planarization process such as chemical mechanical polishing may follow the step of filling the interconnect patterns. In an even further embodiment of the present invention, a dielectric cap is formed atop the cured patternable low-k material after filling the interconnect patterns with a conductive material. In any of the embodiments mentioned above, the interconnect patterns may comprise via openings or line openings. This patternable low-k method of the present invention dramatically reduces the complexity in the fabrication of current interconnect structures. The photoresist used in the prior art integration is no longer needed. In addition the present invention also does not utilize a plasma etching step for patterning as also required in the prior art interconnect processing schemes. It is further noted that the inventive method reduces the number of layers required to fabricate the interconnect structure and, as such, the present invention reduces the time and cost of fabricating interconnect structures as compared to prior art processes. In addition to the methods described above, the present invention also relates to interconnect structures which include the patternable low-k dielectric material in a cured state; in the cured state the patternable low-k material serves as the interconnect dielectric. In general terms, the present invention provides an interconnect structure comprising at least one patterned and cured low-k dielectric material located on a surface of a substrate, said at least one patterned and cured low-k film having conductively filled regions embedded therein and including Si atoms bonded to cyclic rings via oxygen atoms. In one embodiment, a dual-damascene interconnect structure including first and second cured and patterned low-k materials each having the above mentioned Si bonding environment present is provided. In yet another embodiment of the present invention, a single-damascene interconnect structure is provided. In yet another embodiment of the present invention, an antireflective coating that is patterned is located between the substrate and the cured and patterned low-k film. In a further embodiment of the present invention a dielectric cap layer is located on top of the substrate. In still another embodiment of the present invention, another dielectric cap can be present atop the patterned low-k film. In yet another embodiment of the present invention, the conductively filled regions comprise Al, Cu or a Cu alloy. In an even further embodiment of the present invention, the conductively filled regions comprise a single via, a single line, a combined via/line or a combined line/via. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1F are pictorial representations (through cross sectional views) depicting the basic processing steps employed for fabricating a dual-damascene interconnect structure using patternable dielectrics (dual-tone) as on-chip electrical insulators on a semiconductor chip. FIG. 2 shows the interconnect structure that is formed after further processing of the structure shown in FIG. 1F. FIGS. 3A-3D are pictorial representations (through cross sectional views) depicting the basic processing steps employed for fabricating a single-damascene interconnect structure using a patternable dielectric as an on-chip electrical insulator on a semiconductor chip. FIG. 4 shows the interconnect structure that is formed after further processing of the structure shown in FIG. 3D. FIG. 5 shows a single damascene build of patterned and cured patternable low-k material embedded in conductively filled Cu in accordance with one embodiment of the present invention. FIG. 6 shows a dual damascene build of patterned and cured patternable low-k material embedded in conductively filled Cu in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention, which provides single-damascene or dual-damascene low-k interconnect structures with a positive-tone or a negative-tone patternable dielectric and methods of fabricating such interconnect structures, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings that accompany the present application are provided for illustrative purposes only, and, as such, these drawings are not drawn to scale. In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known materials, structures or processing steps have not been described in detail in order to avoid obscuring the invention. It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As stated above, this invention circumvents the prior art drawbacks of current integration by combining the functions of a photoresist and a dielectric material into one material. This one material, called a patternable low-k dielectric herein, acts as a photoresist during the lithographic patterning process and, as such a separate photoresist is not required or used in the present invention. After lithographic patterning, the patternable low-k dielectric is subsequently converted into a low-k material during a post patterning cure. In this way, the inventive method avoids plasma etching and the complex sacrificial film stack and processes required for patterning. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable dielectric. In general terms, a method is provided that comprises depositing at least one patternable low-k material on top of a substrate; forming at least one interconnect pattern within said at least one patternable low-k material, said at least one interconnect pattern is formed without utilizing a separate photoresist material; and curing the at least one patternable low-k material into a dielectric material having a dielectric constant of not more than 4.3 (i.e., 4.3 or less). The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures. The present invention will now be described in reference to FIGS. 1A-1F which illustrate an embodiment of the present invention in which a dual-damascene structure is provided using patternable dielectrics as on-chip electrical insulators on a semiconductor chip. FIG. 1A illustrates an initial structure 10 that is utilized in this embodiment of the present invention. The initial structure 10 includes a substrate 12, an optional dielectric cap 14 located on a surface of substrate 12, and optional antireflective coating 14 located on a surface of the optional dielectric cap 12. The substrate 12 may comprise a semiconducting material, an insulating material, a conductive material or any combination thereof (e.g., a lower level of an interconnect structure). When the substrate 12 is comprised of a semiconducting material, any semiconductor such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP and other III/V or II/VI compound semiconductors, or organic semiconductors may be used. In addition to these listed types of semiconducting materials, the present invention also contemplates cases in which the semiconductor substrate is a layered semiconductor such as, for example, Si/SiGe, Si/SiC, silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs). When the substrate 12 is an insulating material, the insulating material can be an organic insulator, an inorganic insulator or a combination thereof including multilayers. The substrate 12 may also include a patternable low-k dielectric material of this invention as well. When the substrate 12 is a conducting material, the substrate may include, for example, polySi, an elemental metal, alloys of elemental metals, a metal silicide, a metal nitride or combinations thereof including multilayers. When the substrate 12 comprises a semiconducting material, one or more semiconductor devices such as, for example, complementary metal oxide semiconductor (CMOS) devices can be fabricated thereon. The optional dielectric cap 14 is formed directly on the surface of substrate 12 utilizing a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), chemical solution deposition, or evaporation. The dielectric cap 14 comprises any suitable dielectric capping material such as, for example, SiC, SiN, SiO2, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof. This dielectric cap can be a continuous layer and a discontinuous layer. It can also be a select cap, such as CoWP. The thickness of the dielectric cap 14 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the dielectric cap 14 has a thickness from about 5 to about 55 nm, with a thickness from about 20 to about 45 nm being more typical. Next, an optional antireflective coating (ARC) 16 is formed on a surface of the optional dielectric cap 14 if present, or directly on a surface of the substrate 12 when the dielectric cap 14 is not present. The ARC 16 may be designed to control reflection of light that is transmitted through the patternable low-k film (to be subsequently formed), reflected off the substrate and back into the patternable low-k film, where it can interfere with incoming light and cause the low-k film to be unevenly exposed. The optical properties and thickness of ARC 16 is optimized to obtain optimal resolution and profile control of the patternable low-k material during the subsequent patterning steps, which is well known to those ordinarily skilled in the art. The thickness of the ARC 16 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the ARC 16 has a thickness from about 5 to about 200 nm, with a thickness from about 20 to about 140 nm being more typical. The antireflective coating 16 may be either organic or inorganic. Antireflective coatings are well known to those skilled in the art and include homopolymers or copolymers of polyesters, polyimides, polyacrylates, polymethacrylates, polysulfones, amorphous carbon, and the like and may be applied by spin-on techniques, spray on techniques, dipping, etc. Inorganic antireflective coatings, such as silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), SiCOH, siloxane, silane, carbosilane, oxycarbosilane, and silsesquioxane, either as a polymer or a copolymer may also be employed in the present invention and may be deposited, for example, by plasma-enhanced chemical vapor deposition, spin-on techniques, dipping, etc. After applying the ARC, particularly those from a liquid phase, a post deposition baking step is usually required to remove unwanted components, such as solvent, and to effect crosslinking. The post deposition baking step of the ARC 16 is typically, but not necessarily always performed at a temperature from about 80° to about 300° C., with a baking temperature from about 120° to about 200° C. being even more typical. Next, and as illustrated in FIG. 1B, a first patternable low-k material 18, which combines the function of a photoresist and low-k material into one single material is provided. In the embodiment illustrated, the first patternable low-k material 18 is provided on the surface of the ARC 16. In other embodiments, the first patternable low-k material 18 can be provided directly on the dielectric cap layer 14 (when no ARC 16 is present) or directly on the surface of substrate 12 (when no ARC 16 or dielectric cap 14 are present). The first patternable low-k material 18 is provided (i.e., formed) utilizing a conventional deposition process including, for example, spin-on-coating, dip coating, brush coating. After applying the first patternable low-k material 18, a post deposition baking step is typically, but not necessarily always, required to remove unwanted components, such as solvent. When performed, the baking step is conducted at a temperature from about 60° to about 200° C., with a baking temperature from about 80° to about 140° C. being even more preferred. The duration of the baking step varies and is not critical to the practice of the present invention. The thickness of the first patternable low-k material 18 may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the first patternable low-k material 18 has a thickness from about 10 to about 10000 nm, with a thickness from about 50 to about 2000 nm being more typical. As stated above, the first patternable low-k material 18 functions as a photoresist and is converted into a low-k material during post patterning processing, by heat, UV light, electron beam, ion beam, microwave, plasma cure, thermal cure or combinations thereof. For instance, the first patternable low-k material 18 may comprise a functionalized polymer having one or more acid-sensitive imageable groups. These polymers or blends of polymers can be converted into low-k polymers after subsequent processing. More specifically, the first patternable low-k material 18 comprises photo/acid-sensitive polymers of hydrocarbons, fluorinated hydrocarbons, siloxane, silane, carbosilane, oxycarbosilane, organosilicates, silsesquioxanes and the like. The polymers include, for example, silsesquioxane-type polymers including caged, linear, branched or combinations thereof. In one embodiment, the first patternable dielectric material 18 comprises a blend of these photo/acid-sensitive polymers. Examples of patternable dielectric materials useable with the present disclosure are disclosed in U.S. Pat. Nos. 7,041,748, 7,056,840, and 6,087,064, all of which are incorporated herein by reference in their entirety. The dielectric constant of the patternable low-k material 18 after cure is generally no more than 4.3. The dielectric constant may be greater than 1 and up to about 4.3, more preferably from about 1 to about 3.6, even more preferably from about 1 to about 3.0, further more preferably from about 1 to about 2.5, with from about 1 to about 2.0 being most preferred. The first patternable low-k material 18 is formed from a composition that includes one of the above mentioned polymers or polymer blends, a photoacid generator, a base additive and a solvent typically used in a photoresists. The photoacid generators, base additives and solvents are well known to those skilled in the art and, as such, details regarding those components are not fully provided. In a preferred embodiment, the first patternable low-k material 18 is a silsesquioxane polymer or copolymer including, for example, poly(methylsilsesquioxane) (PMS), poly(p-hydroxybenzylsilsesquioxane) (PHBS), poly(p-hydroxyphenylethylsilsesquioxane) (PHPES), poly(p-hydroxyphenylethylsilsesquioxane-co-p-hydroxy-alpha-methylbenzyl silsesquioxane) (PHPE/HMBS), poly(p-hydroxyphenylethylsilsesqioxane-co-methoxybenzylsilsesquioxane) (PHPE/MBS), poly(p-hydroxyphenylethylsilsesquioxane-co-t-butylsilsesquioxane) (PHPE/BS), poly(p-hydroxyphenylethylsilsesquioxane-co-cyclohexylsilsesquioxane) (PHPE/CHS), poly(p-hydroxyphenylethylsilsesquioxane-co-phenylsilsesquioxane) (PHPE/PS), poly(p-hydroxyphenylethylsilsesquioxane-co-bicycloheptylsilsesquioxane) (PHPE/BHS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane) (PHMBS), polyp-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-hydroxybenzylsilsesquioxane) (PHMB/HBS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-methoxybenzylsilsesquioxane) (PHMB/MBS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-t-butylsilsesquioxane) (PHMB/BS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-cyclohexylsilsesquioxane) (PHMB/CHS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-phenylsilsesquioxane) (PHMB/PS), poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-bicycloheptylsilsesquioxane) (PHMB/BHS), poly(p-hydroxybenzylsilsesquioxane-co-p-hydroxyphenylethylsilsesquioxane) (PHB/HPES), and poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilsesquioxane) (PHMB/MBS). In the compositions containing a blended polymer component, the silsesquioxane polymer in the blend may be selected from the silsesquioxane polymers described above or may be selected from other silsesquioxane polymers such as, for example, poly(methyl-silsesquioxane) (PMS), poly(p-hydroxybenzylsilsesquioxane) (PHBS), poly(p-hydroxybenzylsilsesquioxane-co-methoxybenzylsilsesquioxane) (PHB/MBS), polyp-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilsesquioxane) (PHMB/MBS), poly(p-hydroxybenzylsilsesquioxane-co-t-butylsilsesquioxane) (PHB/BS), poly(p-hydroxybenzylsilsesquioxane-co-cyclohexylsilsesquioxane) (PHB/CHS), poly(p-hydrooxybenzylsilsesquioxane-co-phenylsilsesquioxane) (PHB/PS), poly(p-hydroxybenzylsilsesquioxane-co-bicycloheptylsilsesquioxane) (PHB/BHS), and caged silsesquioxanes such as octakis(glycidyloxypropyl) dimethylsilyloxy)silsesquioxane, octakis[cyclohexenyl epoxide) dimethylsilyloxy]silsesquioxane, octakis[4-(hydroxyphenylethyl) dimethylsilyloxy]silsesquioxane, and octakis[{2-(1′,1′-bis(trifluoromethyl)-1′-hydroxyethyl)norbornyl}dimethylsilyloxy]silsesquioxane. If desired, a combination of different silsesquioxane polymers may be used in the blend with the non-silsesquioxane polymer. For positive tone patternable low-k material, the silicon-containing polymer employed in the present invention may be a homopolymer or a copolymer. Suitable types of such silicon-containing polymers include homopolymers or copolymers containing at least one monomer selected from the group consisting of a siloxane, a silane, a silsesquioxane and a silyne. Highly preferred silicon-backbone polymers are selected from the group consisting of poly(hydroxyphenyl alkyl)silsesquioxanes and poly(hydroxyphenyl alkyl) siloxanes, wherein the alkyl is a C1-30 moiety. These preferred silicon-containing polymers are preferably fully or partially protected with acid-sensitive protecting groups. Where the silicon-containing polymeric additive contains a silicon-containing substituent bonded to the polymeric backbone, the silicon-containing polymeric additive may be a homopolymer or copolymer containing at least one monomer having a silicon-containing substituent. The silicon-containing substituent may or may not be acid sensitive. Typically, however the substituent is acid sensitive when containing a C2 alkyl moiety. Preferably, the silicon-containing substituent is attached to a monomer selected from the group consisting of hydroxystyrene, an acrylate, a methacrylate, an acrylamide, a methacrylamide, itaconate, an itaconic half ester or a cycloolefin. Preferred silicon-containing substituents include: siloxane, silane and cubic silsesquioxanes. The silicon-containing polymer may further include silicon-free monomers such as those selected from the group consisting of styrene, hydroxystyrene, acrylic acid, methacrylic acid, itaconic acid and an anhydride such as maleic anhydride and itaconic anhydride. Preferred monomers containing silicon-containing substituents are trimethylsilyl alkyl acrylate, trimethylsilyl alkyl methacrylate, trimethylsilyl alkyl itaconate, tris(trimethylsilyl)silyl alkyl acrylate tris(trimethylsilyl)silyl alkyl methacrylate, tris(trimethylsilyl)silyl alkyl itaconate, tris(trimethylsilyloxy)silyl alkyl acrylate, tris(trimethylsilyloxy)silyl alkyl methacrylate, tris(trimethylsilyloxy)silyl alkyl itaconate, alkylsilyl styrene, trimethylsilylmethyl(dimethoxy)silyloxy alkyl acrylate, trimethylsilylmethyl(dimethoxy)silyloxy alkyl methacrylate, trimethylsilymethyl(dimethoxy)silyloxy alkyl itaconate, trimethylsilyl alkyl norbornene-5-carboxylate alkyl, tris(trimethylsilyl)silyl alkyl norbornene-5-carboxylate and tris(trimethylsilyloxy)silyl alkyl norbornene-5-carboxylate, wherein alkyl is a C1-5 moiety. Highly preferred species of these monomers are 3-(3,5,7,9,11,13,15-heptacyclopentylpentacyclo[9.5.1.13,9.15,15.17,13]-octasiloxan-1-yl)propyl methacrylate, 1,3,5,7,9,11,13-heptacyclopentyl-15-vinylpentacyclo[9.5.1.13,9.15,15.17,13]otasiloxane, methacrylamidotrimethylsilane, O-(methacryloxyethyl)-N-(triethoxysilylpropyl)urethane, methacryloxyethoxytrimethylsilane, N-(3-methacryloxy-2-hydroxypropyl)-3-aminopropyltriethoxysilane, (methacryloxymethyl)bis(trimethylsiloxy)methylsilane, (m,p-vinylbenzyloxy)trimethylsilane, methacryloxypropyltris(trimethylsiloxy)silane, methacryloxytrimethylsilane, 3-methacryloxypropylbis(trimethylsiloxy)methylsilane, 3-methacryloxypropyldimethylchlorosilane, methacryloxypropyldimethylethoxysilane, methacryloxypropyldimethylmethoxysilane, methacryloxypropylheptacyclopentyl-T8-silsequioxane, methacryloxypropylmethyldichlorosilane, methacryloxypropylmethyldiethoxysilane, methacryloxypropylmethyldimethoxysilane, (methacryloxymethyl)dimethylethoxysilane, (methacryloxymethyl)phenyldimethylsilane(phenyldimethylsilyl)methylmethacrylate, methacryloxymethyltriethoxysilane, methacryloxymethyltrimethoxysilane, methacryloxymethyltris(trimethylsiloxy)silane, O-methacryloxy(polyethyleneoxy)trimethylsilane, methacryloxypropylpentamethyldisiloxane, methacryloxypropylsilatrane, methacryloxypropylsiloxane macromer, methacryloxypropyl terminated polydimethylsiloxane, methacryloxypropyltrichlorosilane, methacryloxypropyltriethoxysilane, methacryloxypropyltrimethoxysilane, methacryloxypropyltris(methoxyethoxy)silane, p-(t-butyldimethylsiloxy)styrene, butenyltriethoxysilane, 3-butenyltrimethylsilane, (3-acryloxypropyl)trimethoxysilane, (3-acryloxypropyl)iris(trimethylsiloxy)silane, O-(trimethylsilyl)acrylate, 2-trimethylsiloxyethlacrylate, N-(3-acryloxy-2-hydroxypropyl)-3-aminopropyltriethoxysilane, (3-acryloxypropyl)dimethylmethoxysilane, (3-acryloxypropyl)methylbis(trimethylsiloxy)silane, (3-acryloxypropyl)methyldichlorosilane, and (3-acryloxypropyl)methyldimethoxysilane, (3-acryloxypropyl)trichlorosilane. The extent of protection and the amount of co-monomer present in the silicon containing polymeric additive are such that the patternable low-k material resist composition will provide good lithography performance, i.e., high resolution and good process window. Examples of protecting groups which can be employed are cyclic and branched (secondary and tertiary) aliphatic carbonyls, esters or ethers containing from 3 to 30 carbon atoms, acetals, ketals and aliphatic silylethers. Examples of cyclic or branched aliphatic carbonyls that may be employed in the present invention include, but are not limited to: phenolic carbonates; t-alkoxycarbonyloxys such as t-butoxylcarbonyloxy and isopropyloxycarbonyloxy. A highly preferred carbonate is t-butoxylcarbonyloxy. Some examples of cyclic and branched ethers that may be employed in the present invention include, but are not limited to: benzyl ether and t-alkyl ethers such t-butyl ether. Of the aforesaid ethers, it is highly preferred to use t-butyl ether. Examples of cyclic and branched esters that can be employed in the present invention are carboxylic esters having a cyclic or branched aliphatic substituent such as t-butyl ester, isobornyl ester, 2-methyl-2-admantyl ester, benzyl ester, 3-oxocyclohexanyl ester, dimethylpropylmethyl ester, mevalonic lactonyl ester, 3-hydroxy-g-butyrolactonyl ester, 3-methyl-g-butylrolactonyl ester, bis(trimethylsilyl)isopropyl ester, trimethylsilylethyl ester, tris(trimethylsilyl)silylethyl ester and cumyl ester. Some examples of acetals and ketals that can be employed in the present invention include, but are not limited to: phenolic acetals and ketals as well as tetrahydrofuranyl, tetrahydropyranyl, 2-ethoxyethyl, methoxycyclohexanyl, methoxycyclopentanyl, cyclohexanyloxyethyl, ethoxycyclopentanyl, ethoxycyclohexanyl, methoxycycloheptanyl and ethoxycycloheptanyl. Of these, it is preferred that a methoxycyclohexanyl ketal be employed. Illustrative examples of silylethers that can be employed in the present invention include, but are not limited to: trimethylsilylether, dimethylethylsilylether and dimethylpropylsilylether. Of these silylethers, it is preferred that trimethylsilylether be employed. In a preferred embodiment for negative-tone patternable low-k materials of the present invention are two miscible, or compatible, silsesquioxanes. The first silsesquioxane polymer is a linear, branched, caged compound or combination thereof having the following structural formula: wherein each occurrence of R1 is one or more acidic functional groups for base solubility; each occurrence of R2 is a carbon functionality for controlling polymer dissolution in an aqueous base; R1 is not equal to R2; m and n represent the number of repeating units; m is an integer; and n is zero or an integer greater than zero. In the present invention, R1 is not limited to any specific functional group, and is preferably selected from among linear or branched alkyls which are substituted with OH, C(O)OH, and/or F; cycloalkyls which are substituted with OH, C(O)OH, and/or F; aromatics which are substituted with OH, C(O)OH, and/or F; arenes that are substituted with OH, C(O)OH, and/or F; and acrylics which are substituted with OH, C(O)OH, and/or F. Examples of preferred R1 include: In the present invention, R2 is not limited to any specific carbon functional group, and is preferably selected from among linear or branched alkyls, cylcoalkyls, aromatics, arenes, and acrylates. The silsesquioxane polymers of the present invention have a weight averaged molecular weight of about 400 to about 500,000, and more preferable from about 1500 to about 10,000. The R1 and R2 proportions and structures are selected to provide a material suitable for photolithographic processes. A second polymer component of the blend material includes but is not limited to a family of organosilicates known as silsesquioxanes, having the structural formula: wherein R3 is preferable selected from alkyls, cycloalkyls, aryl, or a combination thereof, and are commercially available from Dow Corning, Shin-Etsu, or JSR, for example. The silsesquioxane is preferably poly(methylsilsesquioxane), and n is an integer about 10 to about 1,000 or more (including copolymers). The silsesquioxane polymers possess silanol end groups, but may also include halosilanes, acetoxysilanes, silylamines, and alkoxysilanes. In a preferred embodiment of the present invention, a silsesquioxane polymer LKD-2056 (JSR Corporation) which contains silanol end groups is employed. A third component of the present invention is a photosensitive acid generator (PAG). Examples of preferred PAGs include: -(trifluoro-methylsulfonyloxy)-bicyclo[2.2.1]hept-5-ene-2,3-dicarboximide (MDT), onium salts, aromatic diazonium salts, sulfonium salts, diaryliodonium salts, and sulfonic acid esters of N-hydroxyamides or -imides, as disclosed in U.S. Pat. No. 4,371,605. The content of the '605 patent is incorporated herein by reference. A weaker acid generated from a PAG such as N-hydroxy-naphthalimide (DDSN) may be used. Combinations of PAGs may be used. The composition of the silsesquioxane polymers in the blend formulation is 1 to 99% of the total polymer composition. In the preferred embodiment of the invention, the composition of the acid sensitive polymer is 20 to 80% of the total polymer composition, and even more preferred, 30 to 60%. Condensation in the presence of an acid generated by a photoacid generator under exposure to radiation is not limited to silanols, but may also include halosilanes, acetoxysilanes, silylanines, and alkoxysilanes. Organic crosslinking agents, such as methylphenyltetramethoxymethyl glycouril (methylphenyl powderlink), may also be included in the formulation. Although photoacid generators are preferred for crosslinking, photobase generators can also be used for crosslinking silanol polymers. The patternable low-k material of the present invention also includes a casting solvent to dissolve the other components. Examples of suitable casting solvent include and is not limited to ethoxyethylpropionate (EEP), a combination of EEP and γ-buyrolactone, propylene-glycol monomethylether alcohol and acetate, propyleneglycol monopropyl alcohol and acetate, and ethyl lactate. Combinations of these solvents may also be used. In optimizing the photolithography process, an organic base may be added to the formulation. The base employed in the present invention may be any suitable base known in the resist art. Examples of bases include tetraalkylammonium hydroxides, cetyltrimethylammonium hydroxide, and 1,8-diaminonaphthalene. The compositions of the present invention are not limited to any specific selection of base. The term “acid-sensitive” is used throughout the application to denote imageable functional groups which undergo a chemical reaction in the presence of an acid generated by a photoacid generator under exposure to radiation. The acid-sensitive imageable functional groups employed in the present invention may include acid-sensitive positive-tone functional groups or acid-sensitive negative-tone functional groups. The negative-tone acid-sensitive functional groups are functional groups for causing a crosslinking reaction which causes the exposed areas to be insoluble in a developer to form a negative-tone relief image after development. The positive-tone acid-sensitive functional groups are acid-sensitive protecting groups which cause the exposed region to be soluble in a developer to form positive-tone relief images after development. In one preferred embodiment, a positive-tone patternable low-k material 18 is used for via patterning. Either a positive-tone or a negative-tone patternable low-k material 18 is used for line patterning. The aforementioned patternable low-k materials act as a photoresist in the present invention during patterning; they can be positive-tone or negative-tone, and sensitive to G-line, I-line, DIUV (248 nm, 193 nm, 157 nm, 126 nm, and EUV (13.4 μm), an electron beam, or an ion beam. Next, and as shown in FIG. 1C, the first patternable low-k dielectric material 18 is pattern-wise exposed to form latent images of a desired circuitry. An optional post-exposure baking may be required to effect the photochemical reactions. When performed, the baking step is conducted at a temperature from about 60° to about 200° C., with a baking temperature from about 80° to about 140° C. being even more preferred. The duration of the baking step varies and is not critical to the practice of the present invention. After exposure and post-exposure baking, the latent images are developed into the low-k material. The pattern-wise exposing process can be accomplished in a variety of ways, including, for example, through a mask with a lithography stepper or a scanner with an exposure light source of G-line, I-line (365 nm), DUV (248 nm, 193 nm, 157 nm, 126 nm), Extreme UV (13.4 nm), an electron beam, or an ion beam. The pattern-wise exposing process also includes direct writing without the use of a mask with, for example, light, electron beam, ion beam, and scanning probe lithography. Other patterning techniques that can be used in the present invention include contact printing techniques such as nanoimprint lithography, embroising, micro contact printing, replica molding, microtransfer molding, micromolding in capillaries and solvent-assisted micromolding, thermal assisted embroising, inject printing, and the like. Specifically, FIG. 1C illustrates the structure that is formed after forming first interconnect patterns 20 within the patternable low-k film 18. The first interconnect patterns 20 may include at least one via opening (as shown and as preferred) or at least one line opening (not shown and less preferred that forming a via opening at this stage of the inventive method). As shown, the first interconnect patterns expose a surface of the ARC 16, if present. When the interconnect patterns 20 are via openings, a positive-tone patternable low-k material 18 is preferred. After forming the first interconnect patterns, the low-k material 18 is typically, but not necessarily always, cured forming a cured low-k material 18′ (See, FIG. 1C) in which the cured low-k material has Si atoms that are bonded to cyclic rings (aliphatic or aromatic) through oxygen atoms. The curing is optional when the first patternable low-k material is negative-tone, but it is required when the first patternable low-k material is a positive-tone material. This type of bonding is evident from C13NMR or 29Si NMR. Curing is performed in the present invention by a thermal cure, an electron beam cure, an ultra-violet (UV) cure, an ion beam cure, a plasma cure, a microwave cure or a combination thereof. The conditions for each of the curing processes are well known to those skilled in the art and any condition can be chosen as long as it coverts the patternable low-k material into a low-k film with good electrical and mechanical properties. In another embodiment, the irradiation cure step is performed by a combination of a thermal cure and an ultra-violet (UV) cure wherein the wavelength of the ultra-violet (UV) light is from about 50 to about 300 nm and the light source for the ultra-violet (UV) cure is a UV lamp, an excimer (exciplex) laser or a combination thereof. In one embodiment, this post patterning cure is a combined UV/thermal cure. This combined UV/thermal cure is carried on a UV/thermal cure module under vacuum or inert atmosphere, such as N2, He, Ar or by vacuum. Typically, the UV/thermal cure temperature is ftom about 100° C. to about 500° C., with a cure temperature from about 300° to about 450° C. being more typical. The duration of the UV/thermal cure is from about 0.5 min to about 30 min with a duration from about 1 to about 11 min being more typical. The UV cure module is designed to have a very low oxygen content to avoid degradation of the resultant dielectric materials. The excimer laser may be generated from at least one of the excimers selected from the group consisting of Ar2, Kr2, F2, Xe2*, ArF, KrF, XeBr, XeCl, XeCl, XeF, CaF2, KrCl, and Cl2 wherein the wavelength of the excimer laser is in the range from about 50 to about 300 nm. Additionally, the light of the ultra-violet (UV) cure may be enhanced and/or diffused with a lens or other optical diffusing device known to those skilled in the art. After patterning and optionally curing the first patternable low-k material 18, a second patternable low-k material 22 is then formed providing the structure shown in FIG. 1D. The second patternable low-k material 22 may comprise the same or different material as the first patternable low-k material 18. The deposition processes and thickness mentioned above for the first patternable low-k material 18 are each applicable here for the second patternable low-k material 22. Typically, and in the embodiment illustrated via-first integration scheme, the first patternable low-k material 18 is a positive-tone material, and the second low-k material 22 is either a negative-tone or a positive-tone material. Next, and as shown in FIG. 1E, the second patternable low-k dielectric material 22 is patterned to include second interconnect patterns 24. The patterning of the second patternable low-dielectric material 22 is performed utilizing the same basic processing equipment and steps as those used for patterning the first patternable low-k dielectric material. In the illustrated embodiment of via-first integration scheme, the second interconnect pattern is typically a line. The second interconnect pattern may also be a via, when the first interconnect pattern is a line. When the second interconnect pattern is a via, a positive-tone is preferred for the second patternable low-k material 22. After patterning the second patternable low-k material 22, the structure is cured providing the structure shown in FIG. 1F. In FIG. 1F, reference numeral 22′ denotes the cured second low-k material. Like the first cured low-k material 18′, the cured second low-k material 22′ has a dielectric constant within the ranges mentioned above and it also is characterized as having Si atoms bonding to cyclic rings (aliphatic or aromatic) via oxygen atoms. If not previously cured, this curing step also cures the first patternable low-k material 18 into a cured low-k material 18′ having the Si bonding environment mentioned above. Further interconnect processing is then performed on the structure in FIG. 1F providing the structure shown in FIG. 2. In some embodiments, the substrate 12 illustrated in FIG. 2 may include a conductive feature embedded therein. When this embodiment is employed, layers 16 and 14 are first opened by etching and exposing a surface of the conductive feature in the substrate 12 using the patterned and cured patternable low-k interconnect structure as an etch mask. The conductive material is then filled into the opening contacting the conductive material in the substrate 12. This includes etching through the ARC 16 and dielectric cap 14 if present, utilizing an etching process such as, for example, reactive ion etching. Next, a diffusion barrier liner (not shown), which may comprise Ta, TaN, Ti, TiN, Ru, RuTaN, RuTa, W, WN or any other material that can serve as a barrier to prevent conductive material from diffusing there through, is typically formed into the first and second interconnect patterns by a deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, chemical solution deposition, or plating. In some embodiments (not shown), the diffusion barrier liner may comprise a combination of layers. The thickness of the diffusion barrier liner may vary depending on the exact means of the deposition process employed as well as the material and number of layers employed. Typically, the diffusion barrier liner has a thickness from about 4 to about 40 nm, with a thickness from about 7 to about 20 nm being more typical. Following the formation of the diffusion barrier liner, the remaining region of the first and second interconnect patterns is filled with a conductive material 25 forming a conductive feature. The conductive material 25 used in forming the conductive feature includes, for example, polysi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide or combinations thereof. Preferably, the first conductive material 25 that is used in forming the conductive feature is a conductive metal such as Cu, W or Al, with Cu or a Cu alloy (such as AlCu) being highly preferred in the present invention. The conductive material 25 is filled into the remaining first and second interconnect patterns utilizing a conventional deposition process including, but not limited to CVD, PECVD, sputtering, chemical solution deposition or plating. After deposition, a conventional planarization process such as, for example, chemical mechanical polishing (CMP) can be used to provide a structure in which the diffusion barrier liner and the conductive material 25 each have an upper surface that is substantially coplanar with the upper surface of the cured second low-k material 22′. After forming the at least one conductive material 25, another dielectric cap (not shown) is formed on the surface of the cured second low-k material 22′ utilizing a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), chemical solution deposition, or evaporation. The dielectric cap comprises any suitable dielectric capping material such as, for example, SiC, SiN, SiO2, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof. This dielectric cap can be a continuous layer or a discontinuous layer. It can also be a select cap, such as CoWP. The thickness of the dielectric cap may vary depending on the technique used to form the same as well as the material make-up of the layer. Typically, the dielectric cap has a thickness from about 5 to about 55 nm, with a thickness from about 20 to about 45 nm being more typical. In addition to the dual-damascene embodiment mentioned above, the present invention also contemplates a single-damascene embodiment which will now be described in greater detail in reference to FIGS. 3A-3D. FIG. 3A shows an initial structure 10 that can be used in this embodiment of the present invention. The initial structure 10 shown in FIG. 3A is identical to the initial structure shown in FIG. 1A. Specifically, the initial structure shown in FIG. 3A also includes a substrate 12, an optional dielectric cap 14 located on a surface of the substrate 12, and an optional ARC 16 located on the surface of the dielectric cap 14. The materials, deposition methods, and thickness of each of substrate 12, optional dielectric cap 14 and optional ARC 16 are the same as that described above for the dual-damascene embodiment of the present invention. FIG. 3B shows the structure of FIG. 3A after forming a patternable low-k material 18 on the surface of the ARC 16. The patternable low-k material 18 may be a positive-tone material or a negative-tone material. The composition of the patternable low-k material 18 in this embodiment of the invention is the same as that mentioned above in the dual-damascene embodiment. Also, the patternable low-k material 18 is formed as described above and it has a thickness within the ranges mentioned above as well. FIG. 3C illustrates the structure after forming interconnect patterns 20 within the patternable low-k film 18. The interconnect patterns 20 may include at least one via opening (as shown and as preferred) or at least one line opening. As shown, the first interconnect pattern exposes a surface of the ARC 16, if present. The formation of the interconnect patterns 20 into the patternable low-k material 18 includes the patterning equipment and process mentioned above in the dual-damascene embodiment. FIG. 3D illustrates the structure that is formed after curing the patternable low-k material 18 into cured low-k material 18′. The cured low-k material 18′ has a dielectric constant within the ranges mentioned above and it also has Si atoms bonded to cyclic rings (aliphatic or aromatic) via oxygen atoms, as measured by NMR. In the uncured state, such bonding is not observed. FIG. 4 illustrates the structure that is formed after further interconnect processing steps including at least filling the interconnect patterns with a conductive material 25 and planarizing the same; it is noted that in FIG. 4 an embedded conductive feature may also be within the substrate 12 (in such an embodiment layers 16 and 14 are etched opened prior to filling the conductive material 25 in the structure). The further processing steps of the present invention have been described in greater detail in regard to the dual damascene embodiment. FIG. 5 is an actual SEM of a single-damascene interconnect structure prepared as described above. FIG. 6 is an actual SEM of a dual-damascene interconnect as also prepared above. The following non-limiting examples are provided to illustrate some embodiment of the present invention. EXAMPLES Example 1 Single-Damascene Integration of Negative-Tone Patternable Low-k Dielectric Having a Dielectric Constant of 2.7 as an on-Chip Electrical Insulator A. Material, Composition A patternable low-k composition was formulated with 60 g of a 20 wt % solution of 6:4 poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilsesquioxane) (pHMBS/MBS) in propylene glycol monomethyl ether acetate (PGMEA), 40 g of a 20 wt % solution of the silsesquioxane copolymer LKD-2021, 2 g of a 20 wt % solution of triphenylsulfonium nonaflate in PGMEA, and 2 g of a 0.5 wt % solution of an organic base such as trioctylamine in PGMEA. The resulting patternable low-k formulation was filtered through a 0.2 micron (μm) filter. B. CVD ARC Process A 800 Å silicon carbide (SiC) film was deposited on 350 Å NBLOK substrate a 200 mm wafer as an anti-reflective coating. The tool used was a 200 mm CVD tool (Centura) from Applied Materials Inc. The process conditions were as follows: precursor trimethyl silane (TMS) 160 sccm, He as carrier, 400 sccm, pressure, 8.7 T, ur power 460 W, temperature 400° C., and deposition time of 80 sec. C. Litho Process This patternable low-k composition was spin coated (2000 rpm for 30 seconds) onto an 8 inch silicon wafer deposited with the NBLOK cap layer and the SiC ARC layer to produce an approximately 0.6 μm film. The wafer and film were pre-exposure baked at about 110° C. for 60 seconds (s), pattern-wise exposed to 248 nm deep ultraviolet (DUV) light on an ASML (0.63 NA, ⅝ annular) DUV stepper, and then post exposure baked at 110° C. for 60 s. This was followed by two 30 second puddle development steps with 0.26 N TMAH developer to resolve 250 nm line and space features at a radiant energy dose of 26 mJ/cm2. D. UV Cure Process The wafer with 250 nm line and space pattern was subjected to a UV-thermal cure in an 8 inch Applied Materials Producer broadband UV cure tool. The process conditions were 400° C. for 10 min under a N2 atmosphere and a pressure of 8 Torr. This UV thermal cure led to approximately 13% line width shrinkage by did not result in any loss in pattern fidelity. E. Liner Process Liner-Seed: Liner and Cu seed were deposited in a 200 mm Endura Encore Ta/TaN tool from Applied Materials. About 95 Å TaN, 190 Å Ta, and 600 Å Cu seed were deposited sequentially. F. Cu Plating and Annealing This wafer was electrochemicaly plated on Ebara tool to fill the trenches with about 750 nm Cu. The plating bath used was: 40/10/50 (Cu/H2SO4/Cl) with Shipley additives: 18/5/1.5 (A-3001/Next Suppressor/L-2001) (ml/L). The as-plated wafer was annealed at 350° C. for 1 hr in a N2 atmosphere in a copper anneal oven. G. Cu CMP Process The excessive Cu was removed by chemical-mechanical polishing with an Ebara Frex Polisher. The polishing was conducted in stages with a V3 high-abrasive slurry. The total polish time was 45 s. H. NBLoK Cap A 350 Å of NBLOK cap layer was deposited on top of the polished patternable low-K/Cu interconnect with a 200 mm CVD tool (Centura) from Applied Materials Inc. The process conditions were: precursor trimethyl silane (TMS) 80 sccm, He as carrier gas 200 sccm, NH3 160 sccm, pressure, 2.0 T, RF power 300 W, temperature 400° C., and deposition time 24.5 sec. An 18 sec NH3 pre-clean was performed prior to the NBLOK cap deposition. I. Analysis: 1. X-Section SEM The post UV cure SEM of the patternable low-k dielectric structure was taken on a LEO low voltage SEM 2. Cu/Low-K X-Section The patternable low-k/Cu interconnect structure was cross-sectioned and examined in a Hitachi SEM. The cross-sectioned surface was polished, decorated with a diluted HF aqueous solution. Example 2 Dual-Damascene Integration of Negative-Tone Patternable Low-k Dielectric Having a Dielectric Constant of 2.7 as an on-Chip Electrical Insulator A. Material, Composition A patternable low-k composition was formulated with 60 g of a 20 wt % solution of 6:4 poly(p-hydroxy-alpha-methylbenzylsilsesquioxane-co-p-alpha-methylbenzylsilscsquioxane) (pHMBS/MBS) in propylene glycol monomethyl ether acetate (PGMEA), 40 g of a 20 wt % solution of the silsesquioxane copolymer LKD-2021, 2 g of a 20 wt % solution of triphenylsulfonium nonaflate in PGMEA, and 2 g of a 0.5 wt % solution of an organic base such as trioctylamine in PGMEA. The resulting patternable low-k formulation was filtered through a 0.2 micron (μm) filter. B. CVD ARC Process A 800 Å silicon carbide (SiC) film was deposited on 350 Å NBLOK substrate a 200 mm wafer as a anti-reflective coating. The tool used was 200 mm CVD tool (Centura) from Applied Materials Inc. The process conditions are: precursor trimethyl silane (TMS) 160 sccm, He as carrier, 400 sccm, pressure, 8.7 T, RF power 460 W, temperature 400° C., and deposition time of 80 sec. C. Via Litho Process This patternable low-k composition (AN2-040-3) was spin coated (2000 rpm for 30 seconds) onto an 8 inch silicon wafer deposited with the NBLOK cap layer and the SiC ARC layer to produce an approximately 0.6 μm film. The wafer and film were pre-exposure baked at about 110° C. for 60 seconds (s), pattern-wise exposed to 248 nM deep ultraviolet (DUV) light on an ASML (0.63 NA, 0.75 sigma) DUV stepper, and then post exposure baked at 110° C. for 60 s. This was followed by two 30 second puddle development steps with 0.26 N TMAH developer to resolve 300 nm via features at a radiant energy dose of 16 mJ/cm2. D. UV Cure Process The wafer with 300 nm via pattern was subjected to a UV-thermal cure in an 8 inch Applied Materials Producer broadband UV cure tool. The process conditions were 400° C. for 10 min under a N2 atmosphere and a pressure of 8 Torr. E. Trench Litho process This patternable low-k composition was spin coated (2000 rpm for 30 seconds) onto an 8 inch silicon wafer that had the via patterns. The wafer and film were pre-exposure baked at about 110° C. for 60 seconds (s), pattern-wise exposed to 248 m deep ultraviolet (DUV) light on an ASML (0.63 NA, 0.75 sigma) DUV stepper, and then post exposure baked at 110° C. for 60 s. This was followed by two 60 second puddle development steps with 0.26 N TMAH developer to resolve 300 nm trench features over the via patterns at a radiant energy dose of 37 mJ/cm2. F. UV Cure Process The wafer with 300 nm dual-damascene (via and trench pattern) structure was subjected to a UV-thermal cure in an 8 inch Applied Materials Producer broadband UV cure tool. The process conditions were 400° C. for 10 min under a N2 atmosphere and a pressure of 8 Torr. The dual damascene pattern fidelity was maintained after the UV cure. G. Liner Process Liner-Seed with Sacrificial TaN Degas: Liner and Cu seed were deposited in a 200 mm Endura Encore Ta/TaN tool from Applied Materials. About 95 Å TaN, 190 Å Ta, and 600 Å Cu seed were deposited sequentially. H. Cu Plating and Annealing This wafer was electrochemically plated on SEMITOOL tool to fill the trenches with about 1200 nm Cu. The plating bath used was: 40/10/50 (Cu/H2SO4/Cl) with Shipley additives: 18/5/1.5 (A-3001/Next Suppressor/L-2001) (ml/L). The as-plated wafer was annealed at 350° C. for 1 hr in a N2 atmosphere in a copper anneal oven. I. Cu CMP Process The excessive Cu was removed by chemical-mechanical polishing with an Ebara Frex Polisher. The polishing was conducted in stages with a V3 high-abrasive slurry. The total polish time was 210 sec. J. NBLoK Cap A 350 Å of continuous NBLOK cap layer was deposited on top of the polished patternable low-K/Cu interconnect with a 200 mm CVD tool (Centura) from Applied Materials Inc. The process conditions are: precursor trimethyl silane (TMS) S0 sccm, He as carrier gas 200 sccm, NH3 160 sccm, pressure, 2.0 T, RF power 300 W, temperature 400° C., and deposition time 24.5 sec. An 18 see NH3 pre-clean was performed prior to the NBLOK cap deposition. K. Analysis 1. X-Section SEM The post UV cure SEM of the patternable low-k dielectric structure was taken on a LEO low voltage SEM 2. Cu/Low-K X-Section The patternable low-k/Cu interconnect structure was cross-sectioned and examined in a Hitachi SEM. The cross-sectioned surface was polished, decorated with a diluted HF aqueous solution. While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.	H	67H01	185H01L	23	52

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