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11899216 | US20080004738A1-20080103 | Systems and method providing for remote system design | ACCEPTED | 20071218 | 20080103 | [] | G06F1900 | ["G06F1900"] | 7428441 | 20070905 | 20080923 | 700 | 097000 | 63121.0 | VON BUHR | MARIA | [{"inventor_name_last": "Walters", "inventor_name_first": "Eric", "inventor_city": "Modesto", "inventor_state": "CA", "inventor_country": "US"}] | A two-way communication and data transfer system allows a field technician and a designer to work together to create a retrofit design for a flow system, make a cost estimate for the retrofit, and gather an approval from a customer all in a single visit to the customer site. The field technician can utilize a remote un... | 1. A method of retrofitting elements of an existing circulation system for a pool in order to improve fluid flow comprising the steps of: obtaining a plurality of measurements at a pool site in order to characterize the existing circulation system; inputting the measurements into a data entry device; using the data ent... | <SOH> BACKGROUND <EOH>In many industries in which a flow of fluid is utilized, it is desirable to maximize flow, or minimize flow resistance, in order to reduce the amount of equipment runtime necessary to push through a given volume of fluid. By reducing the amount of runtime, the amount of wear and tear on the equip... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a diagram of a communication system that can be used in accordance with one embodiment of the present invention. FIG. 2 shows diagrams of (a) an equipment system of the prior art and (b) an equipment system that can be designed using the communication system of FI... | PRIORITY This continuation application claims priority to U.S. patent application Ser. No. 11/191,089, filed Jul. 27, 2005, which application is incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to the design of installations such as systems providing for fluid transport. ... | G | 60G06 | 161G06F | 19 | 00 | |||
11678476 | US20080209242A1-20080828 | MODEM CARD CONFIGURED TO COMPENSATE FOR POWER SUPPLY | ACCEPTED | 20080814 | 20080828 | [] | G06F132 | ["G06F132", "G06F126"] | 7876814 | 20070223 | 20110125 | 375 | 222000 | 70649.0 | LUGO | DAVID | [{"inventor_name_last": "Rodriguez", "inventor_name_first": "Romeo Hernandez", "inventor_city": "San Diego", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Matsuo", "inventor_name_first": "Kotaro", "inventor_city": "Poway", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_l... | A modem card includes a connector configured to be detachably connected to a computer. The card also includes electronics configured to be powered by a power supply located in the computer and to transmit wireless signals to a communications network at a transmit power. The electronics are configured to vary the transm... | 1. A modem card, comprising: a connector configured to be connected to a computer; electronics configured to be powered by power supplied from a power supply located in the computer; and the electronics being configured to transmit wireless signals to a communications network, the signals being transmitted at a transmi... | <SOH> BACKGROUND <EOH>Modem cards allow a computer to wirelessly communicate with a communications system. During operation of the modem card, the modem card transmits wireless signals to the communications system. In some instances, the communications system requests that the PC card increase the transmit power of the... | <SOH> SUMMARY <EOH>A modem card includes a connector configured to be detachably connected to a computer. The modem card also includes electronics configured to be powered by a power supply located in the computer. The electronics are configured to transmit wireless signals to a communication network at a transmit powe... | TECHNICAL FIELD The present invention relates to computer peripheral devices and more particularly to modem cards. BACKGROUND Modem cards allow a computer to wirelessly communicate with a communications system. During operation of the modem card, the modem card transmits wireless signals to the communications system. I... | G | 60G06 | 161G06F | 1 | 32 | |||
11823672 | US20090006885A1-20090101 | Heartbeat distribution that facilitates recovery in the event of a server failure during a user dialog | ACCEPTED | 20081216 | 20090101 | [] | G06F1120 | ["G06F1120", "G06F1516"] | 8201016 | 20070628 | 20120612 | 714 | 004000 | 59198.0 | TRUONG | LOAN | [{"inventor_name_last": "Pattabhiraman", "inventor_name_first": "Ramesh V.", "inventor_city": "New Albany", "inventor_state": "OH", "inventor_country": "US"}, {"inventor_name_last": "Vemuri", "inventor_name_first": "Kumar V.", "inventor_city": "Naperville", "inventor_state": "IL", "inventor_country": "US"}] | An exemplary method facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operation... | 1. A method for automatic recovery upon failure of a server in a network responsible for replying to user requests comprising the steps of: generating periodic heartbeat information by each of a plurality of first servers of a first type responsible for replying to user requests where the heartbeat information provides... | <SOH> BACKGROUND <EOH>This invention relates to monitoring the health of a cluster of servers that provide services to users. More specifically, this invention relates to using such health information to facilitate a recovery during a user dialog with a server in view of a failure of the server which had been supportin... | <SOH> SUMMARY <EOH>It is an object of the present invention to satisfy this need. An exemplary method of the present invention facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsib... | BACKGROUND This invention relates to monitoring the health of a cluster of servers that provide services to users. More specifically, this invention relates to using such health information to facilitate a recovery during a user dialog with a server in view of a failure of the server which had been supporting the dialo... | G | 60G06 | 161G06F | 11 | 20 | |||
11873334 | US20080163385A1-20080703 | METHOD AND APPARATUS FOR RAID ON MEMORY | ACCEPTED | 20080619 | 20080703 | [] | G06F1108 | ["G06F1108"] | 7549020 | 20071016 | 20090616 | 711 | 114000 | 67748.0 | FARROKH | HASHEM | [{"inventor_name_last": "Mahmoud", "inventor_name_first": "Fadi", "inventor_city": "Livermore", "inventor_state": "CA", "inventor_country": "US"}] | A method for protecting memory is provided. The method includes reading a block of data from a storage drive and writing the block of data to a first memory portion and a second memory portion. The method also includes managing the first memory portion and the second memory portion to protect the block of data. The blo... | 1. A method for protecting memory, comprising: reading a block of data from a storage drive; writing the block of data to a first dual in-line module (DIMM) and a second DIMM plugged onto a single host adapter card coupled to the storage drive, wherein the first DIMM and the second DIMM are coupled to a single Redundan... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates generally to the field of computing technology, and more particularly, to methods and structures for optimizing the performance and fault tolerance of a computing system. 2. Description of the Related Art As is well known, co... | <SOH> SUMMARY OF THE INVENTION <EOH>Broadly speaking, the present invention fills these needs by providing an apparatus and methods for improving the performance and increasing the fault tolerance of a computing system by using Redundant Array of Independent disks (RAID) on memory. In one implementation, the embodiment... | CLAIM OF PRIORITY This application is a divisional application claiming priority under 35 U.S.C. § 120 of U.S. patent application Ser. No. 10/185,307, entitled “Method and Apparatus for RAID on Memory,” filed on Jun. 27, 2002, which is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invent... | G | 60G06 | 161G06F | 11 | 08 | |||
11744758 | US20070204252A1-20070830 | Methods and Systems for Placement | ACCEPTED | 20070815 | 20070830 | [] | G06F1750 | ["G06F1750"] | 7669160 | 20070504 | 20100223 | 716 | 009000 | 98137.0 | TAT | BINH | [{"inventor_name_last": "Furnish", "inventor_name_first": "Geoffrey", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "LeBrun", "inventor_name_first": "Maurice", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Bos... | Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integra... | 1. A method of generating a cell placement from a circuit netlist, the method comprising: modeling the circuit netlist as an analogous continuous dynamic physical system of nodes and nets of a first plurality of the nodes, wherein a second plurality of the nodes are represented by analogous physical state variables inc... | <SOH> BACKGROUND <EOH>1. Field Advancements in integrated circuit design, including placement and routing of elements in a Computer Aided Design (CAD) context, are needed to provide improvements in performance, efficiency, and utility of use. 2. Related Art Unless expressly identified as being publicly or well known, ... | <SOH> BRIEF DESCRIPTION OF DRAWINGS <EOH>FIG. 1 is a flow diagram illustrating selected details of an embodiment of placing, routing, analyzing, and generating fabrication data for any portion of an integrated circuit according to a Simultaneous Dynamical Integration (SDI)-based flow. FIG. 2 is a flow diagram illustra... | CROSS REFERENCE TO RELATED APPLICATIONS Priority benefit claims for this application are made in the accompanying Application Data Sheet, Request, or Transmittal (as appropriate, if any). To the extent permitted by the type of the instant application, this application incorporates by reference for all purposes the foll... | G | 60G06 | 161G06F | 17 | 50 | |||
11692558 | US20070233715A1-20071004 | RESOURCE MANAGEMENT SYSTEM, METHOD AND PROGRAM FOR SELECTING CANDIDATE TAG | ACCEPTED | 20070920 | 20071004 | [] | G06F700 | ["G06F700", "G06F1730"] | 9069867 | 20070328 | 20150630 | 715 | 234000 | 94935.0 | HILLERY | NATHAN | [{"inventor_name_last": "Rekimoto", "inventor_name_first": "Junichi", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}] | Resource management system, method and program for selecting candidate tag are provided. The tag can be readily attached to a resource by presenting a candidate tag also to a resource newly registered in a database. The degree of similarity of a new registration resource to each of a plurality of already-registered res... | 1. A resource management system comprising: degree-of-similarity calculating means for calculating the degree of similarity of a new registration resource newly registered in a database, to each of a plurality of already-registered resources that have been already registered in the database; and candidate tag selecting... | <SOH> BACKGROUND <EOH>The present invention relates to a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program, and is applicable to the case of managing many resources by using a tag. Hereinafter, on the Internet, a system in which many users attach a tag to a common... | <SOH> SUMMARY <EOH>In view of the foregoing, it is desirable to provide a resource management system, a method for selecting a candidate tag, and a candidate tag selecting program in that a tag can be readily attached to a resource newly registered. The present application can be applied to various resource management ... | CROSS REFERENCE TO RELATED APPLICATION The present application claims priority to Japanese Patent Application JP 2006-095051 filed in the Japanese Patent Office on Mar. 30, 2006, the entire contents of which is being incorporated herein by reference. BACKGROUND The present invention relates to a resource management sys... | G | 60G06 | 161G06F | 7 | 00 | |||
11863902 | US20090089313A1-20090402 | DECENTRALIZED RECORD EXPIRY | ACCEPTED | 20090318 | 20090402 | [] | G06F1730 | ["G06F1730"] | 7783607 | 20070928 | 20100824 | 707 | 662000 | 64848.0 | ARJOMANDI | NOOSHA | [{"inventor_name_last": "Cooper", "inventor_name_first": "Brian", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Weaver", "inventor_name_first": "Daniel", "inventor_city": "Redwood City", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "... | A technique is described that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. In accordance with the technique, a record is checked to see if it has expired only when it has been accessed for a read or a write. If at the time of a read a record ... | 1. A method for automatically deleting an expired record in a distributed database system comprising a plurality of nodes, wherein each node is configured to manage a respective one of a plurality of databases, the method comprising: receiving a write request for a record at one of the plurality of nodes, wherein the r... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The invention generally relates to the deletion of data from a database. In particular, the invention relates to the automatic deletion of expired data in a distributed database system. 2. Background As used herein the term “record expiry” refers to a sys... | <SOH> BRIEF SUMMARY OF THE INVENTION <EOH>The present invention provides a technique that reduces the complexity and resource consumption associated with performing record expiry in a distributed database system. In particular, a method is described herein for automatically deleting an expired record in a distributed d... | BACKGROUND OF THE INVENTION 1. Field of the Invention The invention generally relates to the deletion of data from a database. In particular, the invention relates to the automatic deletion of expired data in a distributed database system. 2. Background As used herein the term “record expiry” refers to a system-initiat... | G | 60G06 | 161G06F | 17 | 30 | |||
11856832 | US20080072254A1-20080320 | DIGITAL VIDEO BROADCASTING SYSTEM, DIGITAL VIDEO BROADCASTING TERMINAL, AND METHOD FOR PROVIDING FILE INFORMATION IN FILE DOWNLOAD SERVICE | ACCEPTED | 20080305 | 20080320 | [] | G06F300 | ["G06F300"] | 8316397 | 20070918 | 20121120 | 725 | 039000 | 98253.0 | FEATHERSTONE | MARK | [{"inventor_name_last": "Jung", "inventor_name_first": "Ji-Wuck", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Kim", "inventor_name_first": "Young-Jip", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Jeon", "... | A digital video broadcasting system, digital video broadcasting terminal, and method for providing file information in a file download service are provided. To this end, the digital broadcasting system includes a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment... | 1. A digital broadcasting system for providing file information in a file download service using broadcasting information, the digital broadcasting system comprising: a broadcasting server for transmitting an Electronic Service Guide (ESG) comprising a schedule event fragment wherein, if files that provide the file dow... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an apparatus and method for a digital video broadcasting system. More particularly, the present invention relates to a digital video broadcasting system, digital video broadcasting terminal, and method for providing inform... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an object of the present invention is to provide a digital video broadcasting system, terminal, and method for providin... | PRIORITY This application claims the benefit under 35 U.S.C. §119(a) of a Korean Patent Application filed in the Korean Intellectual Property Office on Sep. 18, 2006 and assigned Serial No. 2006-90180 and a Korean Patent Application filed in the Korean Intellectual Property Office on Apr. 20, 2007 and assigned Serial N... | G | 60G06 | 161G06F | 3 | 00 | |||
11923664 | US20090113553A1-20090430 | METHOD AND SYSTEM FOR HIDING INFORMATION IN THE INSTRUCTION PROCESSING PIPELINE | ACCEPTED | 20090416 | 20090430 | [] | G06F2100 | ["G06F2100", "H04L900"] | 8141162 | 20071025 | 20120320 | 726 | 026000 | 65882.0 | EL HADY | NABIL | [{"inventor_name_last": "Myles", "inventor_name_first": "Ginger Marie", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}] | A system, article of manufacture and method is provided for transferring secret information from a first location to a second location. The secret information is encoded and stalls in executable code are located. The executable code is configured to perform a predetermined function when executed on a pipeline processor... | 1. A method for embedding information in a computer program comprising: performing data dependency analysis on said computer program to identify locations within said computer program where pipeline processing dependencies require a stall, said locations including no-operation instructions: encoding said information; a... | <SOH> BACKGROUND <EOH>Steganographic and watermarking techniques have been used to hide ancillary information in many different types of media. Steganographic techniques are generally used when the purpose is to conduct some type of secret communication and stealth is critical to prevent the interception of the hidden ... | <SOH> SUMMARY OF THE INVENTION <EOH>To overcome the limitations in the prior art briefly described above, the present invention provides a method, computer program product, and system for hiding information in an instruction processing pipeline. In one embodiment of the present invention a method for embedding informat... | FIELD OF INVENTION The present invention generally relates to computer implemented steganographic and watermarking techniques, and particularly to methods and systems for encoding secret information in arbitrary program binaries. BACKGROUND Steganographic and watermarking techniques have been used to hide ancillary inf... | G | 60G06 | 161G06F | 21 | 00 | |||
11841611 | US20090055583A1-20090226 | STORING REDUNDANT SEGMENTS AND PARITY INFORMATION FOR SEGMENTED LOGICAL VOLUMES | ACCEPTED | 20090212 | 20090226 | [] | G06F1216 | ["G06F1216", "G06F1200", "G06F1300"] | 7877544 | 20070820 | 20110125 | 711 | 114000 | 68066.0 | DAVIDSON | CHAD | [{"inventor_name_last": "Kishi", "inventor_name_first": "Gregory Tad", "inventor_city": "Oro Valley", "inventor_state": "AZ", "inventor_country": "US"}] | Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that has a plurality of segments created by the storage manager application. At least one additional copy of at least one of the plurality of se... | 1. A method, comprising: maintaining, by a storage manager application implemented in a first computational device a virtual logical volume having a plurality of segments created by the storage manager application; maintaining at least one additional copy of at least one of the plurality of segments in at least one lin... | <SOH> BACKGROUND <EOH>1. Field The disclosure relates to a method, system, and article of manufacture for storing redundant segments and parity information for segmented logical volumes. 2. Background In certain virtual tape storage systems, hard disk drive storage may be used to emulate tape drives and tape cartridges... | <SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>Provided are a method, system, and article of manufacture, wherein a storage manager application implemented in a first computational device maintains a virtual logical volume that has a plurality of segments created by the storage manager application. At least one additi... | BACKGROUND 1. Field The disclosure relates to a method, system, and article of manufacture for storing redundant segments and parity information for segmented logical volumes. 2. Background In certain virtual tape storage systems, hard disk drive storage may be used to emulate tape drives and tape cartridges. For insta... | G | 60G06 | 161G06F | 12 | 16 | |||
11872430 | US20080033600A1-20080207 | AUTOMATED PART PROCUREMENT AND SERVICE DISPATCH | ACCEPTED | 20080123 | 20080207 | [] | G06F1900 | ["G06F1900"] | 7424345 | 20071015 | 20080909 | 700 | 107000 | 98614.0 | RAPP | CHAD | [{"inventor_name_last": "Norbeck", "inventor_name_first": "Dean", "inventor_city": "Marco Island", "inventor_state": "FL", "inventor_country": "US"}] | A method for repairing an HVAC system is disclosed. The method includes monitoring a plurality of sensors positioned throughout the HVAC system and receiving data associated therewith, determining whether the data received from the plurality of sensors is within corresponding predetermined operational parameters, analy... | 1. A method for repairing an HVAC system comprising the steps of: monitoring a plurality of sensors positioned throughout the HVAC system; receiving data associated with the sensors outside of predetermined operational parameters; identifying a malfunction of the HVAC system corresponding to the received data outside o... | <SOH> BACKGROUND OF THE INVENTION <EOH>Commercial heating, ventilation and air conditioning (HVAC) units, such as aptly named “rooftop units,” are often assembled onto the flat roofs of structures such as supermarkets, office buildings and other commercial structures. Chillers, or chilled water units, are cost-effecti... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention is a method and system for monitoring operations of a heating ventilating and air conditioning (HVAC) system such as a chiller system or a rooftop unit having a control center, and upon occurrence of a malfunction or other system failure, to automatically order... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 11/388,502, filed Mar. 24, 2006, allowed, which is incorporated by reference in its entirety. FIELD OF THE INVENTION The present invention is directed to self-diagnosis of malfunctioning equipment and more particular... | G | 60G06 | 161G06F | 19 | 00 | |||
11942524 | US20080126775A1-20080529 | ELECTRONIC APPARATUS INCORPORATING A PLURALITY OF MICROPROCESSOR UNITS | ACCEPTED | 20080514 | 20080529 | [] | G06F15177 | ["G06F15177"] | 7987350 | 20071119 | 20110726 | 713 | 001000 | 67150.0 | TRAN | VINCENT | [{"inventor_name_last": "Miwa", "inventor_name_first": "Kenji", "inventor_city": "Kawasaki-shi", "inventor_state": "", "inventor_country": "JP"}] | An electronic apparatus includes an initializing unit configured to, at power-on, execute in parallel a process of initializing data, which is stored in a first nonvolatile memory and requires initialization, into a first volatile memory by a first microprocessor unit and a process of initializing data, which is stored... | 1. An electronic apparatus including: a first nonvolatile memory; a first volatile memory; a first microprocessor unit to which are connected the first nonvolatile memory and the first volatile memory; a second nonvolatile memory; a second volatile memory; a second microprocessor unit to which are connected the second ... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an electronic apparatus, such as an electronic camera, which incorporates a plurality of microprocessor units. 2. Description of the Related Art An electronic camera becoming more widely used at present has a tendency to i... | <SOH> SUMMARY OF THE INVENTION <EOH>In view of the above-described problems, the present invention is directed to an electronic apparatus capable of shortening a startup time. According to one aspect of the present invention, an electronic apparatus includes a first nonvolatile memory, a first volatile memory, a first ... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic apparatus, such as an electronic camera, which incorporates a plurality of microprocessor units. 2. Description of the Related Art An electronic camera becoming more widely used at present has a tendency to increase the... | G | 60G06 | 161G06F | 151 | 77 | |||
11692145 | US20080243960A1-20081002 | DETERMINISTIC FILE CONTENT GENERATION OF SEED-BASED FILES | ACCEPTED | 20080917 | 20081002 | [] | G06F1730 | ["G06F1730"] | 7685211 | 20070327 | 20100323 | 707 | 200000 | 94832.0 | ORTIZ DITREN | BELIX | [{"inventor_name_last": "Bergauer", "inventor_name_first": "Ryan C.", "inventor_city": "Redmond", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Wohlgemuth", "inventor_name_first": "Sean C.", "inventor_city": "Duvall", "inventor_state": "WA", "inventor_country": "US"}] | A method for deterministic file content generation of seed based files is comprised of extracting a seed value from a seeded file signature, passing the seed value to a seeded content generating function to produce a set of generated content, and appending the set of generated content to the seed file signature to prod... | 1. A method, comprising: extracting a seed value and a file length from a seeded file signature; initializing a seeded content generating function using the seed value to produce a set of blocks; and iteratively adding each block included in the set of blocks to produce generated file content. 2. The method of claim 2,... | <SOH> BACKGROUND <EOH>The testing of network servers under load often requires the server to receive and store large amounts of test data in physical storage such as a hard drive. Clients creating the large amounts of test data must also create and store large amounts of data. Due to the finite amount of physical stora... | <SOH> SUMMARY <EOH>The following presents a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and it does not identify key/critical elements of the invention or delineate the scope of the invention. Its sole purpose ... | BACKGROUND The testing of network servers under load often requires the server to receive and store large amounts of test data in physical storage such as a hard drive. Clients creating the large amounts of test data must also create and store large amounts of data. Due to the finite amount of physical storage, each of... | G | 60G06 | 161G06F | 17 | 30 | |||
11866619 | US20080082769A1-20080403 | Mass storage system and method | ACCEPTED | 20080318 | 20080403 | [] | G06F1200 | ["G06F1200"] | 7873790 | 20071003 | 20110118 | 711 | 118000 | 68309.0 | BANSAL | GURTEJ | [{"inventor_name_last": "Bouchou", "inventor_name_first": "Jean-Louis", "inventor_city": "Rosny-Sous-Bois", "inventor_state": "", "inventor_country": "FR"}, {"inventor_name_last": "Dejon", "inventor_name_first": "Christian", "inventor_city": "Paris", "inventor_state": "", "inventor_country": "FR"}] | The present invention concerns a storage method and system (1) comprising processing means (11) and storage resources (20, 100) containing firstly storage means (20) including at least one physical library (P201 to P20n) and secondly memory means (100) called a cache (100), in which the processing means (11) of the sto... | 1. A storage system (1) for data generated, in at least one format, by at least one computer platform (101 to 10n) and transmitted to the storage system (1) via at least one communication network (RC) through access means (101) of computer platforms (101 to 10n) to the storage system (1) comprising processing means (11... | The present invention relates to the area of data processing, and in particular to the mass storage of data of different formats, generated by different heterogeneous computer platforms such as platforms of type GCOS8®, Unix®, Linux® or Windows® for example. These platforms run data-saving software applications e.g. GC... | G | 60G06 | 161G06F | 12 | 00 | |||||
11799030 | US20080270361A1-20081030 | Hierarchical metadata generator for retrieval systems | ACCEPTED | 20081016 | 20081030 | [] | G06F1730 | ["G06F1730"] | 7895197 | 20070430 | 20110222 | 707 | 728000 | 64146.0 | NGUYEN | PHONG | [{"inventor_name_last": "Meyer", "inventor_name_first": "Marek", "inventor_city": "Schwalbach", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Hildebrandt", "inventor_name_first": "Tomas", "inventor_city": "Darmstadt", "inventor_state": "", "inventor_country": "DE"}] | A computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, associating the fragments with the document from which the fragments originated, and associating metadata with the fragments, where the metadata associated with a fragment includes m... | 1. A computer-implemented method of locating information in a database of electronic documents, the method comprising: defining fragments of the documents; associating the fragments with the document from which the fragments originated; associating metadata with the fragments, wherein the metadata associated with a fra... | <SOH> BACKGROUND <EOH>With the advent and proliferation of electronic storage of documents, particularly in networked environment, more and more documents are written, exchanged, modified, and stored. Because of the overwhelming volume of documents that are available to a user, finding a particular document of interest... | <SOH> SUMMARY <EOH>In a general aspect, a computer-implemented method of locating information in a database of electronic documents includes defining fragments of the documents, associating the fragments with the document from which the fragments originated, and associating metadata with the fragments, where the metada... | TECHNICAL FIELD This disclosure relates to techniques of automated search and retrieval of information and, in particular, to a hierarchical metadata generator for retrieval systems. BACKGROUND With the advent and proliferation of electronic storage of documents, particularly in networked environment, more and more doc... | G | 60G06 | 161G06F | 17 | 30 | |||
11619047 | US20070156934A1-20070705 | High-speed PCI Interface System and A Reset Method Thereof | ACCEPTED | 20070621 | 20070705 | [] | G06F1342 | ["G06F1342"] | 7549009 | 20070102 | 20090616 | 710 | 313000 | 73468.0 | AUVE | GLENN | [{"inventor_name_last": "Ho", "inventor_name_first": "Kuan-Jui", "inventor_city": "Taipei", "inventor_state": "", "inventor_country": "TW"}, {"inventor_name_last": "Chen", "inventor_name_first": "Wen-Yun", "inventor_city": "Taipei", "inventor_state": "", "inventor_country": "TW"}] | A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot rest package cannot be executed by the high-speed PCI device, the host controll... | 1. A high-speed PCI interface system with reset function, comprising: a host controller chipset, comprising at least one root port, used to generate a PCI resetting signal; at least one high-speed PCI device, each of said high-speed PCI devices respectively coupled to said corresponding root port within said host contr... | <SOH> BACKGROUND OF THE INVENTION <EOH>Since the electrical industry has changed with each passing day, the CPU and chipset are promoting upwards constantly that the transmission speed of the PCI interface is the choke point for the whole speed of the computer system. Now the high-speed PCI (PCI Express) is presented,... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a high-speed PCI interface system with reset function, comprising: a host controller chipset, comprising at least one root port, used to generate a PCI resetting signal; at least one high-speed PCI device, each of said high-speed PCI devices respective... | FIELD OF THE INVENTION The present invention relates to a high-speed PCI interface, more particularly to a high-speed PCI interface system with reset function and a reset method thereof. BACKGROUND OF THE INVENTION Since the electrical industry has changed with each passing day, the CPU and chipset are promoting upward... | G | 60G06 | 161G06F | 13 | 42 | |||
11671001 | US20080126431A1-20080529 | Method and Device for Data Backup | ACCEPTED | 20080514 | 20080529 | [] | G06F1730 | ["G06F1730", "G06F1200"] | 7822725 | 20070205 | 20101026 | 707 | 698000 | 98964.0 | BIBBEE | JARED | [{"inventor_name_last": "Walliser", "inventor_name_first": "Stefan", "inventor_city": "Zimmern o.R.", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Haug", "inventor_name_first": "Oliver", "inventor_city": "Rottweil", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Jia... | A method for storing data with a first storage system and a second storage system, wherein the second storage system is used for backing up the data from the first storage system, wherein the first storage system comprises a file system on which the data that is to be backed up is stored, with a client that monitors th... | 1. A method for storing data, with a first storage system and a second storage system, wherein the second storage system is used for backing up the data from the first storage system, wherein the first storage system comprises a file system on which the data that is to be backed up is stored, with a client that monitor... | <SOH> FIELD OF THE INVENTION <EOH>The present invention generally relates to a storage system, in particular to a backup- and archival system, which makes it possible to autonomously store and archive data from a multitude of computers and servers (clients). With increased frequency, ecological, political and social as... | <SOH> BRIEF DESCRIPTION OF THE FIGURES <EOH>Below, the figures to which the detailed description refers are described in brief. FIG. 1 : shows a network with a central switch to which a number of PCs are connected, which by way of this switch are connected to the backup system on which the server runs; FIG. 2 : shows a... | FIELD OF THE INVENTION The present invention generally relates to a storage system, in particular to a backup- and archival system, which makes it possible to autonomously store and archive data from a multitude of computers and servers (clients). With increased frequency, ecological, political and social aspects of li... | G | 60G06 | 161G06F | 17 | 30 | |||
11861642 | US20080082681A1-20080403 | Programmable logic control device with integrated database driver | ACCEPTED | 20080318 | 20080403 | [] | G06F15173 | ["G06F15173"] | 8205005 | 20070926 | 20120619 | 709 | 232000 | 66195.0 | HUSSAIN | FARRUKH | [{"inventor_name_last": "Leseberg", "inventor_name_first": "Gerd", "inventor_city": "Bad Pyrmont", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Pollmann", "inventor_name_first": "Werner", "inventor_city": "Hoexter", "inventor_state": "", "inventor_country": "DE"}] | The invention relates, in particular, to an automation system (10; 110), in which a programmable logic control device (20; 120) can be connected via a network (100; 200) to a database system (60; 160). So that the programmable logic control device (20; 120) can exchange data directly with the database system (60; 160),... | 1. Data transmission system (10; 110) with at least one memory-programmable control device (20; 120) and at least one database device (60; 160) that are connected to each other via a network (100; 200), wherein the memory-programmable control device (20; 120) has the following features: a first driver module (42; 133) ... | The invention relates to a data transmission system with at least one programmable logic control device and at least one database device, which are connected to a network, for example, Ethernet. The invention further relates to a programmable logic control device, which is constructed preferably for use in such a data ... | G | 60G06 | 161G06F | 151 | 73 | |||||
11764559 | US20070290795A1-20071220 | DIGITAL ELECTROCHROMIC CIRCUIT WITH A VEHICLE NETWORK | ACCEPTED | 20071205 | 20071220 | [] | G06F1342 | ["G06F1342"] | 7679488 | 20070618 | 20100316 | 340 | 425500 | 66587.0 | CROSLAND | DONNIE | [{"inventor_name_last": "Drummond", "inventor_name_first": "John", "inventor_city": "Glenageary", "inventor_state": "", "inventor_country": "IE"}, {"inventor_name_last": "Lynam", "inventor_name_first": "Niall", "inventor_city": "Holland", "inventor_state": "MI", "inventor_country": "US"}] | A vehicular rearview mirror system includes an interior rearview mirror assembly having an interior electrochromic reflective element, a housing for the interior electrochromic reflective element, and digital circuitry supplying a drive signal to the interior electrochromic reflective element. The interior electrochrom... | 1. (canceled) 2. A vehicular rearview mirror system suitable for use in a vehicle, said vehicular rearview mirror system comprising: an interior rearview mirror assembly comprising an interior electrochromic reflective element, said interior electrochromic reflective element assuming an interior mirror partial reflecta... | <SOH> BACKGROUND OF THE INVENTION <EOH>This invention relates generally to vehicle rearview mirror systems and, more particularly, to digital electrochromic rearview mirror systems. Digital electrochromic mirror systems are described in commonly assigned U.S. Pat. No. 6,089,721 entitled DIGITAL ELECTROCHROMIC MIRROR S... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a new and unique combination of a digital electrochromic mirror system, a vehicle accessory and a vehicle network, and, more particularly, a combination of a digital electrochromic mirror system, a garage door opener and a vehicle network. According to... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 11/288,649, filed Nov. 29, 2005, now U.S. Pat. No. 7,233,230 (Attorney Docket DON01 P-1256), which is a continuation of U.S. patent application Ser. No. 10/694,595, filed Oct. 27, 2003, now U.S. Pat. No. 6,970... | G | 60G06 | 161G06F | 13 | 42 | |||
11981333 | US20080066151A1-20080313 | Locally adaptable central security management in a heterogeneous network environment | ACCEPTED | 20080227 | 20080313 | [] | G06F1700 | ["G06F1700"] | 8181222 | 20071031 | 20120515 | 726 | 001000 | 69571.0 | LOUIE | OSCAR | [{"inventor_name_last": "Thomsen", "inventor_name_first": "Daniel", "inventor_city": "Minneapolis", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "O'Brien", "inventor_name_first": "Richard", "inventor_city": "Brooklyn Park", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_... | A system and method for defining and enforcing a security policy. Security mechanism application specific information for each security mechanism is encapsulated as a key and exported to a semantic layer. Keys are combined to form key chains within the semantic layer. The key chains are in turn encapsulated as keys and... | 1. In a system having a workflow management system and a central policy management system, a computer-implemented method of controlling workflow, comprising: creating a workflow class definition; exporting the workflow class definition to the central policy management system; binding resources and roles to steps within... | <SOH> BACKGROUND INFORMATION <EOH>Administrating security systems is a complex task. In order to enforce a tight security policy many security constraints must be expressed. Security constraints can be classified in to two broad categories: those required by the application and those required by the local security pol... | <SOH> SUMMARY OF THE INVENTION <EOH>The above mentioned problems with defining and enforcing a security policy across a heterogenous set of applications and other problems are addressed by the present invention and will be understood by reading and studying the following specification. According to one aspect of the i... | PRIORITY CLAIM This application is a divisional of U.S. patent application Ser. No. 09/483,164, filed Jan. 14, 2000, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60/168,656, filed on Dec. 2, 1999, both of which are incorporated herein by reference. STATEMEN... | G | 60G06 | 161G06F | 17 | 00 | |||
11928495 | US20090112562A1-20090430 | USER GUIDED GENERATION OF NETWORK LINK OPTIMIZATION PROFILES | ACCEPTED | 20090416 | 20090430 | [] | G06F944 | ["G06F944"] | 9112806 | 20071030 | 20150818 | 709 | 221000 | 59439.0 | PATEL | HARESH | [{"inventor_name_last": "Holcomb", "inventor_name_first": "Justin H.", "inventor_city": "Durham", "inventor_state": "NC", "inventor_country": "US"}] | Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment of the invention, a network optimization profile generation met... | 1. A network optimization profile generation method comprising: ranking different performance criterion for a target network; testing the target network for the different performance criterion; weighting results of the testing according to the ranking of the different performance criterion; generating a set of target n... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to the field of network connectivity for roaming mobile end users and more particularly to the field of network optimization profile generation in performance optimizing network connections during roaming. 2. Description of t... | <SOH> BRIEF SUMMARY OF THE INVENTION <EOH>Embodiments of the present invention address deficiencies of the art in respect to optimization profile generation and provide a novel and non-obvious method, system and computer program product for user guided generation of network link optimization profiles. In one embodiment... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of network connectivity for roaming mobile end users and more particularly to the field of network optimization profile generation in performance optimizing network connections during roaming. 2. Description of the Related ... | G | 60G06 | 161G06F | 9 | 44 | |||
11858030 | US20080016152A1-20080117 | METHOD OF CONTROLLING SERVER APPARATUS WHICH STORES IMAGE DATA RECEIVED VIA NETWORK IN MEMORY, PROGRAM FOR CAUSING COMPUTER APPARATUS TO EXECUTE THE METHOD, STORAGE MEDIUM WHICH STORES THE PROGRAM, AND COMPUER APPARATUS | ACCEPTED | 20080102 | 20080117 | [] | G06F1516 | ["G06F1516"] | 8204894 | 20070919 | 20120619 | 707 | 104100 | 90324.0 | HOLLAND | SHERYL | [{"inventor_name_last": "MORISADA", "inventor_name_first": "Chikara", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "MITANI", "inventor_name_first": "Shigeyuki", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}] | An object of this invention is to provide a method of controlling a server apparatus for disclosing image data with a representation effect to a third party without any operation of a user, a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer appara... | 1.-8. (canceled) 9. A method of controlling a server apparatus which stores in a memory image data received via a network, comprising the steps of: setting a disclosure date of a received image represented by the received image data; processing the received image data so as to create a processed image represented by th... | <SOH> BACKGROUND OF THE INVENTION <EOH>There is a network service which provides a service of storing image data photographed by the user with an image input device in the storage area of a server in a network and allowing the user to browse the image data at desired time. Also, there is a network service which provid... | <SOH> SUMMARY OF THE INVENTION <EOH>According to an aspect of the present invention, there is provided a method of controlling a server apparatus which stores image data received via a network in a memory, comprising the steps of setting a disclosure date of the image data, processing the image data to create processe... | FIELD OF THE INVENTION The present invention relates to a method of controlling a server apparatus which stores image data received via a network in a memory, a program for causing a computer apparatus to execute the method, a storage medium which stores the program, and a computer apparatus. BACKGROUND OF THE INVENTIO... | G | 60G06 | 161G06F | 15 | 16 | |||
11840743 | US20090049317A1-20090219 | Managing Power in a Parallel Computer | ACCEPTED | 20090205 | 20090219 | [] | G06F132 | ["G06F132"] | 7877620 | 20070817 | 20110125 | 713 | 320000 | 58660.0 | CHOUDHURY | ZAHID | [{"inventor_name_last": "Gara", "inventor_name_first": "Alan", "inventor_city": "Mount Kisco", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Gooding", "inventor_name_first": "Thomas M.", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": ... | Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter h... | 1. A method of managing power in a parallel computer, the parallel computer comprising a power supply and a plurality of compute nodes, each compute node comprising a computer processor and computer memory operatively coupled to the computer processor, the plurality of compute nodes powered by the power supply through ... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The field of the invention is data processing, or, more specifically, methods, apparatus, and products for managing power in a parallel computer. 2. Description of Related Art The development of the EDVAC computer system of 1948 is often cited as the begi... | <SOH> SUMMARY OF THE INVENTION <EOH>Methods, apparatus, and products are disclosed for managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, each compute node including a computer processor and computer memory operatively coupled to the computer processo... | BACKGROUND OF THE INVENTION 1. Field of the Invention The field of the invention is data processing, or, more specifically, methods, apparatus, and products for managing power in a parallel computer. 2. Description of Related Art The development of the EDVAC computer system of 1948 is often cited as the beginning of th... | G | 60G06 | 161G06F | 1 | 32 | |||
10573043 | US20070173999A1-20070726 | Controllers for heavy duty industrial vehicle | ACCEPTED | 20070712 | 20070726 | [] | G06F1900 | ["G06F1900"] | 7885744 | 20070223 | 20110208 | 701 | 050000 | 67987.0 | BEAULIEU | YONEL | [{"inventor_name_last": "Shinozaki", "inventor_name_first": "Akiko", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Suzuki", "inventor_name_first": "Hiroyuki", "inventor_city": "Kanagawa", "inventor_state": "", "inventor_country": "JP"}] | Hardware of each of controllers (11, 12, 13) for controlling a plurality of instruments to be controlled, which are provided in a reach stacker as a heavy duty industrial vehicle, for example, a vehicle body (3), a spreader (9), and a cabin (10), is rendered common. The configuration of driver software for performing b... | 1. Controllers for a heavy duty industrial vehicle, which are a plurality of controllers provided in said heavy duty industrial vehicle equipped with a working machine for performing predetermined work, said plurality of controllers being adapted to control, independently of each other, a plurality of instruments to be... | <SOH> BACKGROUND ART <EOH>A heavy duty industrial vehicle not only has a vehicle moving by itself, but also has a working machine unique to the vehicle. Thus, this type of industrial vehicle is adapted to be capable of performing a predetermined working action with the use of the working machine. Some of such heavy du... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a view showing a configuration example in which controllers for a heavy duty industrial vehicle according to the present invention are used. FIG. 2 is a table showing a constitution example of input/output signals of the controllers for the heavy duty industrial v... | TECHNICAL FIELD This invention relates to controllers which are used for heavy duty industrial vehicles, for example, a reach stacker as a cargo handling vehicle, and a motor grader as a road surface maintenance vehicle. BACKGROUND ART A heavy duty industrial vehicle not only has a vehicle moving by itself, but also ha... | G | 60G06 | 161G06F | 19 | 00 | |||
11860532 | US20090083618A1-20090326 | METHODS OF COMPLETING ELECTRONIC FORMS RELATING TO INTERACTIONS WITH CUSTOMERS BY CARRYING OVER CALL BACK NUMBERS BETWEEN FORMS | ACCEPTED | 20090312 | 20090326 | [] | G06F1500 | ["G06F1500"] | 8065602 | 20070924 | 20111122 | 715 | 224000 | 94550.0 | STORK | KYLE | [{"inventor_name_last": "Campbell", "inventor_name_first": "Michelle", "inventor_city": "North Augusta", "inventor_state": "SC", "inventor_country": "US"}] | Interactions between customers and representatives of a service provider are documented by providing multiple electronic forms for completion. Information that is requested for both forms is carried over from one form to the next rather than requiring the representative to manually enter the same information multiple t... | 1. A computer readable medium containing instructions that perform acts comprising: in relation to a particular service account of a customer, displaying a first form containing fields for a name of a customer, an identification number of the service account, and a call back telephone number of the customer and contain... | <SOH> BACKGROUND <EOH>Departments of service providers take calls from customers for many reasons. Customers may contact a customer service or sales department to place a new order for a service, to request assistance with an existing service, to request maintenance or repair for a service, or to cancel the service. In... | <SOH> SUMMARY <EOH>Embodiments address issues such as these and others by providing for the carry over of information between fields of one form being completed for a customer interaction to another form being completed for the customer interaction. In particular, the call back number that has been obtained from the cu... | TECHNICAL FIELD Embodiments relate to completing electronic forms to document interactions with customers. More particularly, embodiments relate to completing the electronic forms by carrying over call back numbers between multiple forms being completed for a given customer interaction. BACKGROUND Departments of servic... | G | 60G06 | 161G06F | 15 | 00 | |||
11754419 | US20070299974A1-20071227 | VIDEO REPRODUCING APPARATUS AND CONTROL METHOD THEREOF | ACCEPTED | 20071213 | 20071227 | [] | G06F1516 | ["G06F1516"] | 7640569 | 20070529 | 20091229 | 725 | 115000 | 92969.0 | LUU | LE | [{"inventor_name_last": "Kitajima", "inventor_name_first": "Kotaro", "inventor_city": "Yokohama-shi", "inventor_state": "", "inventor_country": "JP"}] | A technique for sequentially updating a recording medium as if sub contents, related to a video image as a main content recorded on the recording medium, are stored on the recording medium, such that the sub contents can be reproduced. When reproduction of the video image as a main content recorded on an optical disk h... | 1. A video reproducing apparatus comprising: a reproducing unit to reproduce information recorded on a recording medium; a communication unit to establish connection with a network; an acquisition unit to perform communication with a network server holding sub information related to video information recorded on said r... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a technique for reproducing a video image recorded on a recording medium. 2. Description of the Related Art In recent years, digital contents have been distributed in various forms. In one known distribution form, digital ... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made in view of the above problem, and provides a technique for sequentially updating a recording medium as if sub contents linked with a video image as a main content recorded on the recording medium are stored on the recording medium, such that the su... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reproducing a video image recorded on a recording medium. 2. Description of the Related Art In recent years, digital contents have been distributed in various forms. In one known distribution form, digital contents re... | G | 60G06 | 161G06F | 15 | 16 | |||
11802015 | US20080288677A1-20081120 | KVM switch system with a simplified external controller | ACCEPTED | 20081105 | 20081120 | [] | G06F1312 | ["G06F1312"] | 7730243 | 20070518 | 20100601 | 710 | 062000 | 84674.0 | CHEN | ALAN | [{"inventor_name_last": "Kirshtein", "inventor_name_first": "Philip M.", "inventor_city": "New Market", "inventor_state": "AL", "inventor_country": "US"}] | A KVM switch system with external control functionality is described. A KVM switch is able to be controlled from an external device. The external device can either include a single button dedicated to controlling the desktop KVM switch or indicate a state of the KVM switch. The external device can be connected to the d... | 1. An external controller for use with a peripheral switch coupling user peripheral devices to a plurality of target devices, the external controller comprising: a communications interface for coupling the external controller to the peripheral switch; a selector switch for requesting that the external controller change... | <SOH> FIELD OF DISCLOSURE <EOH>This disclosure relates to a simplified external controller for controlling a KVM (Keyboard, Video, Mouse) switch. | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The following description, given with respect to the attached drawings, may be better understood with reference to the non-limiting examples of the drawing, wherein the drawings show: FIG. 1 : a prior art single user desktop KVM switch with an onboard selection mechanism; FI... | FIELD OF DISCLOSURE This disclosure relates to a simplified external controller for controlling a KVM (Keyboard, Video, Mouse) switch. BRIEF DESCRIPTION OF THE DRAWINGS The following description, given with respect to the attached drawings, may be better understood with reference to the non-limiting examples of the dra... | G | 60G06 | 161G06F | 13 | 12 | |||
11729792 | US20080244285A1-20081002 | Method to control core duty cycles using low power modes | ACCEPTED | 20080917 | 20081002 | [] | G06F126 | ["G06F126"] | 7774626 | 20070329 | 20100810 | 713 | 300000 | 65323.0 | BROWN | MICHAEL | [{"inventor_name_last": "Fleming", "inventor_name_first": "Bruce L.", "inventor_city": "Beaverton", "inventor_state": "OR", "inventor_country": "US"}] | A processor starting a duty cycle timer with a specified duty cycle period and a specified power state, and if the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer, if the timer has not expired and if an interrupt other than a timer tick interrupt is re... | 1. A method comprising: A processor starting a duty cycle timer with a specified duty cycle period and a specified power state; If the duty cycle timer expires, placing the processor in the specified power state in response to the expiry of the timer; and If the timer has not expired and if an interrupt other than a ti... | <SOH> BACKGROUND <EOH>Low power features of processor based platforms are useful for mobile computing, to increase battery life of devices such as notebook computers, handheld computers, “smart” phones, among many others. Similarly thermal requirements in processor based platforms such as densely packed servers may mak... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 depicts a processor based system in one embodiment. FIG. 2 depicts a processor in one embodiment. FIG. 3 depicts the flow of processing in one embodiment. detailed-description description="Detailed Description" end="lead"? | BACKGROUND Low power features of processor based platforms are useful for mobile computing, to increase battery life of devices such as notebook computers, handheld computers, “smart” phones, among many others. Similarly thermal requirements in processor based platforms such as densely packed servers may make it import... | G | 60G06 | 161G06F | 1 | 26 | |||
11840450 | US20090049129A1-20090219 | REAL TIME COLLABORATION FILE FORMAT FOR UNIFIED COMMUNICATION | ACCEPTED | 20090205 | 20090219 | [] | G06F1516 | ["G06F1516"] | 8583733 | 20070817 | 20131112 | 709 | 204000 | 71704.0 | GOLDBERG | ANDREW | [{"inventor_name_last": "Faisal", "inventor_name_first": "Adil", "inventor_city": "Redmond", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Sethi", "inventor_name_first": "Aaron", "inventor_city": "Bellevue", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Wolfe", ... | The claimed subject matter provides a system and/or a method that facilitates enhancing real time unified communications. An interface can receive a portion of data associated with at least one of a client application or an environment that hosts a client application. A real time collaboration (RTC) component can emplo... | 1. A system that facilitates enhancing real time unified communications, comprising: an interface that receives a portion of data associated with at least one of a client application or an environment that hosts a client application; and a real time collaboration (RTC) component that employs an extensible RTC file pack... | <SOH> BACKGROUND <EOH>As computing and network technologies have evolved and have become more robust, secure and reliable, more consumers, wholesalers, retailers, entrepreneurs, educational institutions, and the like have and are shifting business paradigms and are employing the Internet to perform business rather than... | <SOH> SUMMARY <EOH>The following presents a simplified summary of the innovation in order to provide a basic understanding of some aspects described herein. This summary is not an extensive overview of the claimed subject matter. It is intended to neither identify key or critical elements of the claimed subject matter ... | CROSS REFERENCE TO RELATED APPLICATION(S) This application relates to U.S. Application Ser. No. 11/081806, entitled, “Method and System for Installing Applications via a Display Page,” filed Mar. 15, 2005. BACKGROUND As computing and network technologies have evolved and have become more robust, secure and reliable, mo... | G | 60G06 | 161G06F | 15 | 16 | |||
11776332 | US20090019514A1-20090115 | METHOD AND SYSTEM FOR ENFORCING PASSWORD POLICY IN A DISTRIBUTED DIRECTORY | ACCEPTED | 20081230 | 20090115 | [] | G06F1700 | ["G06F1700"] | 8935805 | 20070711 | 20150113 | 726 | 001000 | 77989.0 | JOHNSON | CARLTON | [{"inventor_name_last": "Hazlewood", "inventor_name_first": "Kristin Marie", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Feng", "inventor_name_first": "Daw", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Wi... | The invention describes techniques for enforcing password policy within a distributed directory environment that includes one or more distributed directory servers and a proxy server that acts as an intermediate agent between a client and the distributed directory environment. In one aspect, the proxy server is enhance... | 1. A method for enforcing password policy within a distributed directory that includes a set of directory servers, and a proxy server that acts as an intermediary between a client and the set of directory servers, comprising: at the proxy server, receiving and parsing a password policy response control; at the proxy se... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field The present invention relates to enforcing password policy in a distributed directory environment. 2. Background of the Related Art A directory is a special type of database for managing information about people, organizations, data processing systems, and other... | <SOH> BRIEF SUMMARY OF THE INVENTION <EOH>A method, system, apparatus, or computer program product is presented for enforcing password policy within a distributed directory environment that includes one or more distributed directory servers and a proxy server that acts as an intermediate agent between a client and the ... | CROSS-REFERENCE TO RELATED APPLICATION This application is related to Ser. No. 11/______, filed July 2007, titled “Method and system for enforcing password policy for an external bind operation in a distributed directory.” BACKGROUND OF THE INVENTION 1. Technical Field The present invention relates to enforcing passwor... | G | 60G06 | 161G06F | 17 | 00 | |||
11888597 | US20080046846A1-20080221 | System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization | ACCEPTED | 20080207 | 20080221 | [] | G06F1750 | ["G06F1750"] | 7886262 | 20070801 | 20110208 | 716 | 132000 | 98137.0 | TAT | BINH | [{"inventor_name_last": "Chew", "inventor_name_first": "Marko P.", "inventor_city": "Palo Alto", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Yang", "inventor_name_first": "Yue", "inventor_city": "Cupertino", "inventor_state": "CA", "inventor_country": "US"}] | A system and a method of maximizing the manufacturing yield of integrated circuit (“IC”) design using IC fabrication process simulation driven layout optimization is described. An IC design layout is automatically modified through formulation of a layout optimization problem utilizing the results of layout fabrication ... | 1. A method of improving the manufacturing yield of integrated circuit comprising the steps: receiving a plurality of integrated circuit layout elements; constructing and allocating a plurality of position variables to a plurality of layout elements, wherein position variables represent the location of edges or points ... | <SOH> BACKGROUND OF THE INVENTION <EOH>The electronic circuit of an integrated circuit (“IC”) consists of connected components such as transistors, diodes and resistors. The description of the components and their interconnections is called a netlist. Each component is mapped to one or more layout objects that are two-... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides a system and a method of maximizing IC manufacturing yield with IC fabrication process simulation driven layout optimization. An IC design layout is adaptively and iteratively modified in a layout optimization system consisting of a layout fabrication p... | CLAIM OF BENEFIT TO PROVISIONAL APPLICATION This patent application claims the benefit of the earlier filed U.S. Provisional Patent Application entitled “System and method of maximizing integrated circuit manufacturing yield with fabrication process simulation driven layout optimization”, having Ser. No. 60/838,023, an... | G | 60G06 | 161G06F | 17 | 50 | |||
11833018 | US20080126318A1-20080529 | Method and Apparatus for Remotely Monitoring a Social Website | ACCEPTED | 20080514 | 20080529 | [] | G06F15173 | ["G06F15173", "G06F1730"] | 9858341 | 20070802 | 20180102 | 707 | 010000 | 66381.0 | MITIKU | BERHANU | [{"inventor_name_last": "Frankovitz", "inventor_name_first": "Jason", "inventor_city": "Los Angeles", "inventor_state": "CA", "inventor_country": "US"}] | A computer method, apparatus, system and computer program product for remotely monitoring a social website includes monitoring user activity (events) and producing user activity data. The resulting data may be processed separately from the social website. The processed user activity data may be stored and information i... | 1. A method to remotely monitor a social website, comprising: monitoring user activity on a remote social website, resulting in user activity data; processing the user activity data separate from the social website; storing the processed user activity data; and reporting information indicative of the processed user act... | <SOH> BACKGROUND OF THE INVENTION <EOH>The amount of time that consumers spend on the Internet has steadily increased, as has the variety of web content, such that the Internet is often the first place many people turn to when searching for information, news, or entertainment. Consumers use a variety of methods to sear... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention addresses the foregoing problems in the prior art. In particular, the invention provides a method and apparatus for remotely monitoring a social website for the purpose of centrally aggregating activity. In a preferred embodiment, the inventive computer implemen... | RELATED APPLICATION This application claims the benefit of U.S. Provisional Application No. 60/835,257, filed on Aug. 2, 2006. The entire teachings of the above application(s) are incorporated herein by reference. BACKGROUND OF THE INVENTION The amount of time that consumers spend on the Internet has steadily increased... | G | 60G06 | 161G06F | 151 | 73 | |||
11866484 | US20090094087A1-20090409 | MULTI-TIER CROSS-DEPARTMENT SCHEDULING MODEL FOR ORDER PROCESSING OPERATIONS | ACCEPTED | 20090325 | 20090409 | [] | G06F1900 | ["G06F1900", "G06F1710", "G06Q1000"] | 8117052 | 20071003 | 20120214 | 705 | 007110 | 57223.0 | CLARK | DAVID | [{"inventor_name_last": "Chung", "inventor_name_first": "Casey", "inventor_city": "MCKINNEY", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Sriskandarajah", "inventor_name_first": "Chelliah", "inventor_city": "PLANO", "inventor_state": "TX", "inventor_country": "US"}] | A multi-tier cross-department scheduling model for order processing operations. A scheduling model for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments and the departments share finite capacity resources, includes a progra... | 1. A scheduling model for planning assignment of discrete jobs to multiple departments for shipment, wherein selected jobs are assignable to respective selected departments, and the departments share finite capacity resources, the model comprising: a programmable computer system having loaded therein an objective funct... | <SOH> BACKGROUND <EOH>The present invention relates generally to scheduling models and, in an embodiment described herein, more particularly provides a multi-tier cross-department scheduling model for order processing operations. A hypothetical Company B will be used herein to demonstrate the types of problems faced in... | <SOH> SUMMARY <EOH>In carrying out the principles of the present invention, a short range planning solution is provided which schedules discrete jobs to parallel picking/processing departments while allowing preferred departments by job, in addition to taking into consideration that these parallel departments compete f... | BACKGROUND The present invention relates generally to scheduling models and, in an embodiment described herein, more particularly provides a multi-tier cross-department scheduling model for order processing operations. A hypothetical Company B will be used herein to demonstrate the types of problems faced in typical co... | G | 60G06 | 161G06F | 19 | 00 | |||
11839714 | US20090048700A1-20090219 | METHOD FOR REPORTING THE STATUS OF A CONTROL APPLICATION IN AN AUTOMATED MANUFACTURING ENVIRONMENT | ACCEPTED | 20090205 | 20090219 | [] | G06F1900 | ["G06F1900"] | 7493236 | 20070816 | 20090217 | 702 | 185000 | 97661.0 | WACHSMAN | HAL | [{"inventor_name_last": "Mock", "inventor_name_first": "Michael W.", "inventor_city": "St. George", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Moore", "inventor_name_first": "Gray R.", "inventor_city": "Milton", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "W... | Disclosed are embodiments that provide near real-time monitoring of a control application in a manufacturing environment to detect and determine the root cause of faults within the control application. The embodiments monitor the flow of data within the control application during events (i.e., transactions, stages, pro... | 1. A method for monitoring a control application, said method comprising: accessing a plurality of data sources for said control application; retrieving, from said data sources, data regarding events occurring in a manufacturing environment monitored by said control application; compiling said data to generate, for sai... | <SOH> BACKGROUND <EOH>1. Field of the Invention The embodiments of the invention generally relate to control applications and, more particularly, to a system and method for monitoring and reporting the status of a control application, such as a fault detection and classification application, in an automated manufacturi... | <SOH> SUMMARY <EOH>In view of the foregoing, disclosed herein are embodiments of a system, method, and service that provide near real-time monitoring of a control application in a manufacturing environment in order to detect and determine the root cause of faults within the control application. The embodiments monitor ... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is related to the following co-pending applications filed concurrently herewith by the same Applicants and assigned to the same Assignee, namely, International Business Machines Corporation (IBM Corporation): “A TOOL FOR REPORTING THE STATUS OF A CONTROL APPLICAT... | G | 60G06 | 161G06F | 19 | 00 | |||
11619549 | US20080163164A1-20080703 | SYSTEM AND METHOD FOR MODEL-DRIVEN DASHBOARD FOR BUSINESS PERFORMANCE MANAGEMENT | ACCEPTED | 20080619 | 20080703 | [] | G06F944 | ["G06F944"] | 8843883 | 20070103 | 20140923 | 717 | 104000 | 75570.0 | WEI | ZHENG | [{"inventor_name_last": "Chowdhary", "inventor_name_first": "Pawan Raghunath", "inventor_city": "Montrose", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Pinel", "inventor_name_first": "Florian Alexandre", "inventor_city": "New York", "inventor_state": "NY", "inventor_country": "US"}, {"inv... | A system, method, and framework resulting therefrom, for a model-driven dashboard for business performance management, which includes capturing business dashboard model requirements at a business model level by providing at least one user-customizable model for capturing functionality of a dashboard, and after the user... | 1. A method of capturing business dashboard model requirements at a business model level, the method comprising: providing at least one user-customizable model for capturing functionality of a deployable dashboard. 2. A method of capturing business dashboard model requirements at a business model level, the method comp... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention generally relates to a system and method of generating code for a model-driven dashboard for business performance management and dashboard resulting therefrom, and more particularly, to a system and method of capturing business model... | <SOH> SUMMARY OF THE INVENTION <EOH>The present inventors have recognized that business process and business performance modeling are becoming increasingly important as modern enterprises seek ways to exploit high level design and reasoning, as well as some degree of automation in the code generation process. For examp... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a system and method of generating code for a model-driven dashboard for business performance management and dashboard resulting therefrom, and more particularly, to a system and method of capturing business model requiremen... | G | 60G06 | 161G06F | 9 | 44 | |||
11777180 | US20080141017A1-20080612 | GAMING MACHINE HAVING A SECURE BOOT CHAIN AND METHOD OF USE | ACCEPTED | 20080530 | 20080612 | [] | G06F2100 | ["G06F2100", "G06F15177", "H04L900", "G06F1130"] | 7827397 | 20070712 | 20101102 | 713 | 002000 | 97901.0 | REHMAN | MOHAMMED | [{"inventor_name_last": "McCoull", "inventor_name_first": "James Ross", "inventor_city": "St Peters", "inventor_state": "", "inventor_country": "AU"}, {"inventor_name_last": "Muir", "inventor_name_first": "Robert Linley", "inventor_city": "Artarmon", "inventor_state": "", "inventor_country": "AU"}] | An electronic gaming machine (EGM) comprises a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged to tak... | 1. An electronic gaming machine (EGM) comprising: a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and a monitoring device having or with access to validation code and arranged t... | <SOH> BACKGROUND TO THE INVENTION <EOH>The development of an electronic gaming machine and program code to be run on gaming machines requires a great deal of effort. Further, given the nature of gambling regulations, there is a need for a high degree of confidence in the security of an electronic gaming machine. Accord... | <SOH> SUMMARY OF THE INVENTION <EOH>In a first aspect, the invention provides an electronic gaming machine (EGM) comprising: a memory storing boot program code comprising first code; a central processing unit (CPU) arranged to access the memory and initiate a boot process by reading the first code from the memory; and ... | CROSS-REFERENCE TO RELATED APPLICATIONS The present application relates to, and claims priority from, U.S. application Ser. No. 10/089,759, which claims priority as a national phase application of PCT/AU00/01192, which are herein incorporated by reference in their entirety. The present application also relates to, and ... | G | 60G06 | 161G06F | 21 | 00 | |||
11882514 | US20090037973A1-20090205 | Policy-enabled aggregation of IM User communities | ACCEPTED | 20090122 | 20090205 | [] | G06F2100 | ["G06F2100"] | 8266671 | 20070802 | 20120911 | 726 | 001000 | 81891.0 | ARMOUCHE | HADI | [{"inventor_name_last": "Gustave", "inventor_name_first": "Christophe", "inventor_city": "Ottawa", "inventor_state": "", "inventor_country": "CA"}, {"inventor_name_last": "McFarlane", "inventor_name_first": "Brad", "inventor_city": "Ottawa", "inventor_state": "", "inventor_country": "CA"}, {"inventor_name_last": "Chow"... | A method of automatically aggregating an online user community, and graphical user interface for same, the method including one or more of the following: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the... | 1. A method of automatically aggregating an online user community, comprising: a user creating the online community; the user defining an aggregation policy for the online user community; a service provider retrieving the aggregation policy; the service provider applying the aggregation policy to an other user; determi... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention This invention relates generally to policy enabled aggregation of user communities. 2. Description of Related Art Communication service providers enable communication between pluralities of users in many different ways. An example of communications enable... | <SOH> SUMMARY OF THE INVENTION <EOH>In light of the present need for policy enabled aggregation of user communities, a brief summary of various exemplary embodiments is presented. Some simplifications and omission may be made in the following summary, which is intended to highlight and introduce some aspects of the var... | BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to policy enabled aggregation of user communities. 2. Description of Related Art Communication service providers enable communication between pluralities of users in many different ways. An example of communications enabled between t... | G | 60G06 | 161G06F | 21 | 00 | |||
11871979 | US20080034285A1-20080207 | INFORMATION ARCHITECTURE FOR THE INTERACTIVE ENVIRONMENT | ACCEPTED | 20080123 | 20080207 | [] | G06F1724 | ["G06F1724"] | 7992079 | 20071013 | 20110802 | 715 | 200000 | 79085.0 | HUYNH | THU | [{"inventor_name_last": "Bimson", "inventor_name_first": "Andrea", "inventor_city": "Scottsdale", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Chyung", "inventor_name_first": "Jin", "inventor_city": "Hamburg", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Gopakum... | A system and method for providing management such as creation, manipulation, storage, control, and retrieval of digital content for a company on a global basis. Digital content is created and stored in, for example, the extensible Markup Language (XML) format using the relationship between component mapping information... | 1. A computer-implemented method for managing digital content for a company website on a global basis, including the steps of: receiving, from a computer of a user, a request to view an updated content page; retrieving a category tag click count for a component corresponding to said user; analyzing said category tag cl... | <SOH> BACKGROUND OF INVENTION <EOH>As more and more companies begin to provide a presence on the internet, they are confronted with the issues of presentation of information and conformity within the preparation of the presentations. Various schemes have been presented to assist the companies in preparing the presenta... | <SOH> SUMMARY OF THE INVENTION <EOH>The previously described deficiencies in the prior art are addressed in the present invention which, in conjunction with a content management application, provides an intranet application to provide a system for implementing changes to both an intranet or an internet website and, pe... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 09/769,887 entitled “INFORMATION ARCHITECTURE FOR THE INTERACTIVE ENVIRONMENT” filed on Jan. 25, 2001, which application claims priority to and the benefit of U.S. Provisional Application No. 60/178,456 filed ... | G | 60G06 | 161G06F | 17 | 24 | |||
11741650 | US20080270976A1-20081030 | MANAGEMENT OF GRAPHICAL INFORMATION NOTES | ACCEPTED | 20081016 | 20081030 | [] | G06F944 | ["G06F944"] | 8584091 | 20070427 | 20131112 | 717 | 105000 | 97774.0 | VU | TUAN | [{"inventor_name_last": "Champion", "inventor_name_first": "David Frederick", "inventor_city": "Durham", "inventor_state": "NC", "inventor_country": "US"}, {"inventor_name_last": "Nyeste", "inventor_name_first": "Patrick Gabor", "inventor_city": "Raleigh", "inventor_state": "NC", "inventor_country": "US"}, {"inventor_n... | Provided are a method, system, and article of manufacture, wherein information is associated with a program element that is capable of being processed in a software environment generated by an operating system. A graphical information note application is executed in response to a processing of the program element in th... | 1. An article of manufacture including code, wherein the code when executed by a computer performs operations, the operations comprising: associating information with a program element that is capable of being processed in a software environment generated by an operating system; executing a graphical information note a... | <SOH> BACKGROUND <EOH>1. Field The disclosure relates to a method, system, and article of manufacture for the management of graphical information notes. 2. Background Physical “sticky notes” are widely used in office environments. Such physical sticky notes are relatively small physical pieces of paper on which an adhe... | <SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>Provided are a method, system, and article of manufacture, wherein information is associated with a program element that is capable of being processed in a software environment generated by an operating system. A graphical information note application is executed in respo... | BACKGROUND 1. Field The disclosure relates to a method, system, and article of manufacture for the management of graphical information notes. 2. Background Physical “sticky notes” are widely used in office environments. Such physical sticky notes are relatively small physical pieces of paper on which an adhesive has be... | G | 60G06 | 161G06F | 9 | 44 | |||
11770725 | US20080165136A1-20080710 | System and Method for Managing Lists | ACCEPTED | 20080625 | 20080710 | [] | G06F3041 | ["G06F3041"] | 8091045 | 20070628 | 20120103 | 715 | 863000 | 79338.0 | AUGUSTINE | NICHOLAS | [{"inventor_name_last": "Christie", "inventor_name_first": "Greg", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Forstall", "inventor_name_first": "Scott", "inventor_city": "Mountain View", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last"... | A computer-implemented method for displaying and managing lists on a portable multifunction device with a touch screen display includes displaying a list of items, detecting a finger contact on a moving-affordance icon, detecting movement of the finger contact on the touch screen display, and in response to detecting t... | 1. A computer-implemented method, comprising: at a portable multifunction device with a touch screen display, displaying a list of items on the touch screen display; detecting a finger gesture on an edit initiation icon; in response to detecting the finger gesture on the edit initiation icon, displaying moving-affordan... | <SOH> BACKGROUND <EOH>As portable electronic devices become more compact, and the number of functions performed by a given device increases, it has become a significant challenge to design a user interface that allows users to easily interact with a multifunction device. This challenge is particularly significant for h... | <SOH> SUMMARY <EOH>The above deficiencies and other problems associated with user interfaces for portable devices are reduced or eliminated by the disclosed portable multifunction device. In some embodiments, the device has a touch-sensitive display (also known as a “touch screen”) with a graphical user interface (GUI)... | RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application Nos. 60/883,808, “System and Method for Managing Lists,” filed Jan. 7, 2007; 60/879,469, “Portable Multifunction Device,” filed Jan. 8, 2007; and 60/879,253, “Portable Multifunction Device,” filed Jan. 7, 2007. All of these app... | G | 60G06 | 161G06F | 30 | 41 | |||
11671429 | US20070192423A1-20070816 | DOCUMENT REMINDER SYSTEM | ACCEPTED | 20070801 | 20070816 | [] | G06F1516 | ["G06F1516", "G06F1700", "G06F3048"] | 8365080 | 20070205 | 20130129 | 715 | 739000 | 61650.0 | NGUYEN | CAO | [{"inventor_name_last": "Karlson", "inventor_name_first": "Bruce", "inventor_city": "Mission", "inventor_state": "KS", "inventor_country": "US"}] | A document reminder system is provided. The system provides a user-friendly interface to a user's existing document management, email, calendar and other systems in order to ensure that an appropriate user is notified when action should be taken on a specific document, and also provides notation to the user indicating ... | 1. A document reminder system comprising: a connection with a document management system; a connection with a messaging system; and a database for storing reminder information including information relating to said document management system and said messaging system. 2. The system as claimed in claim 1 wherein said re... | <SOH> BACKGROUND OF THE INVENTION <EOH>In a modern business environment, proper management of documents and relevant dates is essential to success. A key problem in the management of documents and dates is the tracking of documents through time, whether because of a need to follow up on a document at a given time, gen... | <SOH> SUMMARY OF THE INVENTION <EOH>An object of the instant invention is to provide a document reminder system. Another object of the instant invention is to provide a document reminder system that is easy to use. Another object of the instant invention is to provide a document reminder system that is easy to use and... | This application claims priority to U.S. Provisional Patent Application Ser. No. 60/764,845 filed Feb. 4, 2006, the entire disclosure of which is incorporated herein by reference in it entirety. FIELD OF THE INVENTION The present invention relates generally to a document reminder system. More specifically, the present ... | G | 60G06 | 161G06F | 15 | 16 | |||
11623893 | US20080169848A1-20080717 | High-Speed Leaf Clock Frequency-Divider/Splitter | ACCEPTED | 20080701 | 20080717 | [] | G06F110 | ["G06F110", "H03K2100", "H03K515"] | 7915929 | 20070117 | 20110329 | 375 | 354000 | 94225.0 | LE | DINH | [{"inventor_name_last": "Douskey", "inventor_name_first": "Steven Michael", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}, {"inventor_name_last": "Ellavsky", "inventor_name_first": "Matthew Roger", "inventor_city": "Rochester", "inventor_state": "MN", "inventor_country": "US"}] | A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selective... | 1. A clock splitter comprising: an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that h... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field The present disclosure relates in general to the field of electronics, and in particular to timing clocks in electronic circuits. Still more particularly, the present disclosure relates to a clock splitter having an integrated clock frequency-divider. 2. Descrip... | <SOH> SUMMARY OF THE INVENTION <EOH>To address the problem described above, presented herein is a novel clock splitter that has a local internal clock frequency-divider. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and ... | BACKGROUND OF THE INVENTION 1. Technical Field The present disclosure relates in general to the field of electronics, and in particular to timing clocks in electronic circuits. Still more particularly, the present disclosure relates to a clock splitter having an integrated clock frequency-divider. 2. Description of the... | G | 60G06 | 161G06F | 1 | 10 | |||
11867726 | US20090094357A1-20090409 | ROGUE ROUTER HUNTER | ACCEPTED | 20090325 | 20090409 | [] | G06F1516 | ["G06F1516"] | 7991877 | 20071005 | 20110802 | 709 | 224000 | 57270.0 | KHAJURIA | SHRIPAL | [{"inventor_name_last": "Keohane", "inventor_name_first": "Susann Marie", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "McBrearty", "inventor_name_first": "Gerald Francis", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_na... | A computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. The process in the illustrative embodiments first obtains a physical address of a suspected router or destination device. A data packet is created which comprises at least a destinati... | 1. A computer implemented method for detecting unauthorized routers in a distributed network, the computer implemented method comprising: obtaining a physical address of a destination device; creating a data packet comprising at least a destination media access control field, a destination internet protocol field, and ... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates generally to an improved data processing system, and in particular to a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. 2. Description of ... | <SOH> SUMMARY OF THE INVENTION <EOH>The illustrative embodiments provide a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. The process in the illustrative embodiments first obtains a physical address of a suspected router or destinat... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to an improved data processing system, and in particular to a computer implemented method, data processing system, and computer program product for discovering an unauthorized router in a network. 2. Description of the Related... | G | 60G06 | 161G06F | 15 | 16 | |||
11891492 | US20090043939A1-20090212 | Bus node | ACCEPTED | 20090128 | 20090212 | [] | G06F1314 | ["G06F1314"] | 7624219 | 20070809 | 20091124 | 710 | 305000 | 96460.0 | DANG | KHANH | [{"inventor_name_last": "Fuessl", "inventor_name_first": "Bernd", "inventor_city": "Eriskirch", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Riehm", "inventor_name_first": "Thomas", "inventor_city": "Konstanz", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Schoepe"... | The present invention relates to an apparatus for connection to a communication bus, in particular an apparatus for encoding the status of several emergency devices for communication across an AS-interface. A data code indicative of a collective state of one or more subsets of the emergency devices is communicated duri... | 1. A bus node circuit comprising: a coding circuit that receives a plurality of substantially binary input signals and outputs a first output signal and a plurality of other output signals; and a bus interface circuit having a first data input terminal and a plurality of parameter input terminals, wherein said first ou... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to an apparatus for connection to a communication bus. More specifically, it relates to an apparatus for encoding the status of several emergency switches for communication across a so-called AS-interface. 2. Description of t... | <SOH> BRIEF SUMMARY OF THE INVENTION <EOH>In a broad aspect, the invention can be seen in an apparatus for coding a plurality of substantially binary input signals and for outputting the coded signals as bus signals for communication on a bus, i.e. as a bus node circuit. Similarly, the invention can be seen in method c... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a non-provisional application claiming no benefit of an earlier filed application. STATEMENT OF GOVERNMENT INTEREST The subject matter of this application was not carried out under contract with the government of the United States. BACKGROUND OF THE INVENTION ... | G | 60G06 | 161G06F | 13 | 14 | |||
11867244 | US20090093900A1-20090409 | Production Moving Line System and Method | ACCEPTED | 20090325 | 20090409 | [] | G06F1900 | ["G06F1900"] | 7599756 | 20071004 | 20091006 | 700 | 113000 | 93224.0 | PATEL | RAMESH | [{"inventor_name_last": "Reeves", "inventor_name_first": "Brad J.", "inventor_city": "Everett", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": "Bradley", "inventor_name_first": "James S.", "inventor_city": "Arlington", "inventor_state": "WA", "inventor_country": "US"}, {"inventor_name_last": ... | A production moving line system. An illustrative embodiment of the production moving line system includes at least one metallic guide strip and at least one tow vehicle which may be adapted to follow the guide strip. The tow vehicle may include control circuitry and a power source and a wireless transceiver connected t... | 1. A production moving line system, comprising: at least one metallic guide strip; at least one tow vehicle adapted to follow said guide strip; said at least one tow vehicle comprises control circuitry and a power source and a wireless transceiver connected to said control circuitry; an assembly fixture cart coupled to... | <SOH> BACKGROUND <EOH>Part moving lines may be used in assembly facilities to shuttle parts among multiple work stations. A conventional part moving line may utilize an automated guided vehicle (AGV) on which the part is placed and transported among and between the work stations. However, conventional part moving lines... | <SOH> SUMMARY <EOH>The disclosure is generally directed to a production moving line system. An illustrative embodiment of the production moving line system includes at least one metallic guide strip and at least one tow vehicle which may be adapted to follow the guide strip. The tow vehicle may include control circuitr... | TECHNICAL FIELD The disclosure relates to production moving line systems and methods. More particularly, the disclosure relates to a production moving line system and method in which multiple line-following tow vehicles are controlled wirelessly by a central computer. BACKGROUND Part moving lines may be used in assembl... | G | 60G06 | 161G06F | 19 | 00 | |||
11840169 | US20090049251A1-20090219 | SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE | ACCEPTED | 20090205 | 20090219 | [] | G06F1200 | ["G06F1200"] | 8131957 | 20070816 | 20120306 | 711 | 162000 | 67970.0 | KROFCHECK | MICHAEL | [{"inventor_name_last": "Bartfai", "inventor_name_first": "Robert Francis", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Boyd", "inventor_name_first": "Kenneth Wayne", "inventor_city": "Tucson", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_l... | Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is rec... | 1. A method to replicate data performed by a splitter executing in a storage controller managing access to primary volumes, comprising: receiving an initialization command to communicate with a replication engine; receiving a replication command for one primary volume; indicating the primary volume as subject to replic... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. 2. Description of the Related Art In current network storage systems, a splitter can be implemented in ... | <SOH> SUMMARY <EOH>Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replica... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. 2. Description of the Related Art In current network storage systems, a splitter can be implemented in a host or a... | G | 60G06 | 161G06F | 12 | 00 | |||
11801670 | US20080282189A1-20081113 | System and method for simultaneous display of multiple tables | ACCEPTED | 20081030 | 20081113 | [] | G06F3048 | ["G06F3048"] | 7925989 | 20070509 | 20110412 | 715 | 793000 | 78326.0 | ALVESTEFFER | STEPHEN | [{"inventor_name_last": "Hofmann", "inventor_name_first": "Helmut", "inventor_city": "Sandhausen", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Koenigstein", "inventor_name_first": "Markus", "inventor_city": "Bad Schonborn", "inventor_state": "", "inventor_country": "DE"}] | In a system and method for displaying hierarchically related data, a processor may display in a single display window of a display device respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship, where each of at least two of the representations i... | 1. A method for displaying hierarchically related data, comprising: simultaneously displaying in a display window respective representations of a plurality of hierarchically related data records in accordance with the hierarchical relationship; wherein: each of at least two of the representations includes a respective ... | <SOH> BACKGROUND <EOH>Data can be arranged in an hierarchical fashion by a logical assignment of various data elements to classes and sub-classes of data. To allow a user to easily search for a particular data element, a tree structure is often displayed which can be traversed until the sought data element is found. Fo... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a block diagram that illustrates components of a system according to an example embodiment of the present invention. FIG. 2 is a screenshot of a display including nested tables arranged according to an example embodiment of the present invention. FIG. 3 is flowchar... | BACKGROUND Data can be arranged in an hierarchical fashion by a logical assignment of various data elements to classes and sub-classes of data. To allow a user to easily search for a particular data element, a tree structure is often displayed which can be traversed until the sought data element is found. For example, ... | G | 60G06 | 161G06F | 30 | 48 | |||
11833208 | US20080034364A1-20080207 | Sharing Live Appliances | ACCEPTED | 20080123 | 20080207 | [] | G06F9455 | ["G06F9455"] | 8266576 | 20070802 | 20120911 | 717 | 100000 | 59811.0 | RAMPURIA | SATISH | [{"inventor_name_last": "Lam", "inventor_name_first": "Monica", "inventor_city": "Menlo Park", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Berkheimer", "inventor_name_first": "Andrew", "inventor_city": "Boston", "inventor_state": "MA", "inventor_country": "US"}, {"inventor_name_last": "Sa... | Methods, systems, and apparatus, including computer program apparatus, implementing techniques for publishing, subscribing to, or playing live appliances. A live appliance includes a current virtual machine image. In publishing, a proxy file of a live appliance file type is provided to the publisher. The type is mapped... | 1. A computer-implemented method comprising: receiving in a computer a request to run a live appliance, the live appliance providing a computing environment that a user can run on the computer, the live appliance being defined by a data source that includes a version description for a current version of a virtual machi... | <SOH> BACKGROUND <EOH>This specification relates to creating, publishing, subscribing to, and using virtual machines. A virtual machine is software construct that appears to be hardware on which a guest operating system and applications can be installed. In an emulator implementation, the virtual machine is an emulato... | <SOH> SUMMARY <EOH>This specification describes technologies for publishing, distributing, and subscribing to one or more live appliances. A live appliance includes a virtual machine image, and generally a sequence of virtual machine images. In general, one aspect of the subject matter described in this specification ... | CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Patent Application No. 60/835,258, titled “Sharing Live Appliances,” filed Aug. 2, 2006, which is incorporated herein by reference. BACKGROUND This specification relates to creating, publishing, subscribing to, ... | G | 60G06 | 161G06F | 94 | 55 | |||
11699996 | US20070132775A1-20070614 | Buffer management in vector graphics hardware | ACCEPTED | 20070531 | 20070614 | [] | G06F1210 | ["G06F1210"] | 8390634 | 20070131 | 20130305 | 345 | 537000 | 74558.0 | MCDOWELL, JR | MAURICE | [{"inventor_name_last": "Tuomi", "inventor_name_first": "Mika", "inventor_city": "", "inventor_state": "", "inventor_country": "US"}] | A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that... | 1. A processor unit for processing vector graphics primitives, the processor unit comprising: counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel; a first internal buffer configured to store at least one indicator bit value for each pixel; an... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention generally relates to buffer management, and more particularly to buffer management in vector graphics hardware. 2. Discussion of the Background In recent years, vector graphics systems and algorithms have been developed for achievin... | <SOH> SUMMARY OF THE INVENTION <EOH>Therefore, there is a need for decreasing traffic on buses between a main memory, and a graphics accelerator, as described above. The above and other problems are addressed by the exemplary embodiments of the present invention, which provide an exemplary hardware implemented vector ... | CROSS REFERENCE TO RELATED DOCUMENTS The present invention is a continuation of U.S. patent application Ser. No. 11/272,867 of TUOMI, entitled “BUFFER MANAGEMENT IN VECTOR GRAPHICS HARDWARE,” filed Nov. 15, 2005, and is related to U.S. patent application Ser. No. 11/272,866 of TUOMI, entitled “VECTOR GRAPHICS ANTI-ALIA... | G | 60G06 | 161G06F | 12 | 10 | |||
11958072 | US20090089750A1-20090402 | METHOD AND SYSTEM OF PERFORMING JAVA LANGUAGE CLASS EXTENSIONS | ACCEPTED | 20090318 | 20090402 | [] | G06F944 | ["G06F944"] | 8381177 | 20071217 | 20130219 | 717 | 108000 | 97593.0 | MAMO | ELIAS | [{"inventor_name_last": "Cabillic", "inventor_name_first": "Gilbert", "inventor_city": "Brece", "inventor_state": "", "inventor_country": "FR"}, {"inventor_name_last": "Lesot", "inventor_name_first": "Jean-Philippe", "inventor_city": "Argentre du Plessis", "inventor_state": "", "inventor_country": "FR"}] | A method and system of performing Java language class extensions. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to identify a first class having a first name, and create a second class based on the ... | 1. A computer-readable medium storing a program that, when executed by a processor of a host system, causes the processor to: identify a first class having a first name; and create a second class based on the first class, wherein the second class is an abstract view of the first class, and wherein the second class has ... | <SOH> BACKGROUND <EOH>Java™ is a programming language that, at the source code level, is similar to object oriented programming languages such as C++. Java language source code is compiled into an intermediate representation based on a plurality of “bytecodes” that define specific actions. In some implementations, the ... | <SOH> SUMMARY <EOH>The problems noted above are solved in large part by a method and system of performing Java language class extensions. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to identify a ... | CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to EP Application No. 07291168.8, filed on Sep. 28, 2007, hereby incorporated herein by reference. BACKGROUND Java™ is a programming language that, at the source code level, is similar to object oriented programming languages such as C++. Ja... | G | 60G06 | 161G06F | 9 | 44 | |||
11785880 | US20070187825A1-20070816 | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument | ACCEPTED | 20070801 | 20070816 | [] | H01L2348 | ["H01L2348"] | 7307351 | 20070420 | 20071211 | 257 | 784000 | 79459.0 | MANDALA | VICTOR | [{"inventor_name_last": "Hashimoto", "inventor_name_first": "Nobuaki", "inventor_city": "Suwa-shi", "inventor_state": "", "inventor_country": "JP"}] | The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconductor chip (12) and the solder ball (20), a stress relieving layer (16) provi... | 1. An electronic component, comprising: a semiconductor chip; an electrode disposed on the semiconductor chip; a wiring electrically connected to the electrode, the wiring disposed on the semiconductor chip; a first resin layer formed over the semiconductor chip and the wiring, the first resin layer having an opening o... | <SOH> BACKGROUND ART <EOH>To pursue high density mounting in semiconductor devices, bare chip mounting is the ideal. However, quality control and handling of bare chips are difficult. For this reason, CSP (chip size/scale package) technology, in which the package size is close to the chip size, has been developed. In ... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 shows a first embodiment of the semiconductor device. FIG. 2 shows a second embodiment of the semiconductor device. FIG. 3 shows a third embodiment of the semiconductor device. FIGS. 4A and 4B shows a fourth embodiment of the semiconductor device. FIG. 5 shows a fift... | This is a Continuation of application Ser. No. 10/331,510 filed Dec. 31, 2002, which is a Continuation of application Ser. No. 09/953,858 filed Sep. 18, 2001, which is a Continuation of application Ser. No. 09/142,856 filed Mar. 26, 1999 which is a National Stage of PCT/JP98/00130 filed Jan. 16, 1998. TECHNICAL FIELD T... | H | 67H01 | 185H01L | 23 | 48 | |||
11858437 | US20090079038A1-20090326 | Method Of Making An Integrated Circuit Including Singulating A Semiconductor Wafer | ACCEPTED | 20090311 | 20090326 | [] | H01L23544 | ["H01L23544", "H01L2178"] | 7674689 | 20070920 | 20100309 | 438 | 462000 | 72874.0 | HOANG | QUOC | [{"inventor_name_last": "Schneegans", "inventor_name_first": "Manfred", "inventor_city": "Vaterstetten", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Kroninger", "inventor_name_first": "Werner", "inventor_city": "Regensburg", "inventor_state": "", "inventor_country": "DE"}] | A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first ... | 1. A method of making an integrated circuit, the method comprising: providing a semiconductor wafer comprising a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface; forming a first trench in t... | <SOH> BACKGROUND <EOH>Market demand for smaller and more functional electronic devices has driven the development of semiconductor devices, packages, and highly functional chips. Multiples of these functional chips are formed on a surface of a semiconductor wafer and include specific, desired chip properties. The semi... | <SOH> SUMMARY <EOH>One aspect provides a method of making an integrated circuit. The method includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the layers of the first surface and the second surface including a metallization layer deposited o... | BACKGROUND Market demand for smaller and more functional electronic devices has driven the development of semiconductor devices, packages, and highly functional chips. Multiples of these functional chips are formed on a surface of a semiconductor wafer and include specific, desired chip properties. The semiconductor wa... | H | 67H01 | 185H01L | 235 | 44 | |||
11627924 | US20070123013A1-20070531 | CONTROLLED PROCESS AND RESULTING DEVICE | ACCEPTED | 20070519 | 20070531 | [] | H01L21425 | ["H01L21425"] | 7759217 | 20070126 | 20100720 | 438 | 455000 | 77782.0 | LEE | HSIEN MING | [{"inventor_name_last": "HENLEY", "inventor_name_first": "FRANCOIS", "inventor_city": "Aptos", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Cheung", "inventor_name_first": "Nathan", "inventor_city": "Albany", "inventor_state": "CA", "inventor_country": "US"}] | A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate ... | 1-51. (canceled) 52. A process for forming a film of material from a semiconductor substrate using a chemical source, the process comprising steps of: introducing particles through a surface of a semiconductor substrate to a selected depth underneath the surface, the particles being at a concentration at the selected d... | <SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique including a method and device for cleaving a substrate in the fabrication of a silicon-on-insulator substrate for semiconductor integrated circuits, for example. ... | <SOH> SUMMARY OF THE INVENTION <EOH>According to the present invention, an improved technique for removing a thin film of material from a substrate using a controlled cleaving action is provided. This technique allows an initiation of a cleaving process on a substrate using a single or multiple cleave region(s) throug... | CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority from the provisional patent application entitled A CONTROLLED CLEAVAGE PROCESS AND RESULTING DEVICE, filed May 12, 1997 and assigned Application No. 60/046,276, the disclosure of which is hereby incorporated in its entirety for all purposes. BACKG... | H | 67H01 | 185H01L | 214 | 25 | |||
11846874 | US20090057849A1-20090305 | INTERCONNECT IN A MULTI-ELEMENT PACKAGE | ACCEPTED | 20090218 | 20090305 | [] | H01L2348 | ["H01L2348", "H01L2156"] | 7838420 | 20070829 | 20101123 | 438 | 672000 | 67894.0 | DANG | PHUC | [{"inventor_name_last": "Tang", "inventor_name_first": "Jinbang", "inventor_city": "Chandler", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Frear", "inventor_name_first": "Darrel R.", "inventor_city": "Phoenix", "inventor_state": "AZ", "inventor_country": "US"}, {"inventor_name_last": "Lyt... | A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposi... | 1. A packaged semiconductor device comprising: an interconnect layer over a first side of a polymer layer; a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer; a first conductive element over a second side of the polymer layer, wherein the second side is ... | <SOH> BACKGROUND <EOH>1. Field This disclosure relates generally to packages that have more than one element including at least one semiconductor device, and more specifically, to interconnect for such packages. 2. Related Art One technique for increasing density of functionality is to include multiple elements, such a... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 ... | BACKGROUND 1. Field This disclosure relates generally to packages that have more than one element including at least one semiconductor device, and more specifically, to interconnect for such packages. 2. Related Art One technique for increasing density of functionality is to include multiple elements, such as integrate... | H | 67H01 | 185H01L | 23 | 48 | |||
11915921 | US20090309117A1-20091217 | PROTECTION CIRCUIT, AND SEMICONDUCTOR DEVICE AND LIGHT EMITTING DEVICE USING SUCH PROTECTION CIRCUIT | ACCEPTED | 20091202 | 20091217 | [] | H01L3300 | ["H01L3300", "H01L2973", "H02H900"] | 7889467 | 20071129 | 20110215 | 361 | 056000 | 95717.0 | JACKSON | STEPHEN | [{"inventor_name_last": "Okazaki", "inventor_name_first": "Mitsuru", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Takahashi", "inventor_name_first": "Naoki", "inventor_city": "Kyoto", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Shimizu",... | In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to b... | 1. A protection circuit connected via a line including a significant inductance component to a circuit to be protected, comprising: a first transistor arranged on a path to ground from a connection point of the protection circuit and the line; and a second transistor arranged on a path to ground from a connection point... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to circuit protection technology for protecting a circuit to be protected, from surge voltages and the like. 2. Description of the Related Art Many semiconductor integrated circuits are used in various electronic devices, sta... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention has been made in view of these problems, and a general purpose thereof is to provide a protection circuit which enables a voltage clamp that suppresses oscillation, and also a semiconductor device using the protection circuit. An embodiment of the present invent... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to circuit protection technology for protecting a circuit to be protected, from surge voltages and the like. 2. Description of the Related Art Many semiconductor integrated circuits are used in various electronic devices, starting from ... | H | 67H01 | 185H01L | 33 | 00 | |||
11776750 | US20080102594A1-20080501 | METHOD FOR FORMING SEMICONDUCTOR MEMORY CAPACITOR WITHOUT CELL-TO-CELL BRIDGES | ACCEPTED | 20080422 | 20080501 | [] | H01L21306 | ["H01L21306"] | 7498267 | 20070712 | 20090303 | 438 | 706000 | 85142.0 | NHU | DAVID | [{"inventor_name_last": "KIM", "inventor_name_first": "Gyu Hyun", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "CHOI", "inventor_name_first": "Yong Soo", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}] | A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading th... | 1. A method for forming a capacitor comprising steps of: forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate; forming a storage node on the surface of each of the storage node holes in the mold insulating layer; and removing the mold insulating layer comprising steps of... | <SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to a method for forming a capacitor, and more particularly to a method for forming a capacitor capable of preventing the generation of cell-to-cell bridges upon the formation of cylindrical metal storage nodes. A capacitor has a structure in which a d... | <SOH> SUMMARY OF THE INVENTION <EOH>Embodiments of the present invention are directed to a method for forming a capacitor which can prevent the formation of watermarks between metal storage nodes upon the formation of cylindrical metal storage nodes. Further, embodiments of the present invention are directed to a metho... | CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to Korean patent application number 10-2006-0106909 filed on Oct. 31, 2006, which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION The present invention relates to a method for forming a capacitor, and more p... | H | 67H01 | 185H01L | 213 | 06 | |||
11697779 | US20070190694A1-20070816 | INTEGRATED CIRCUIT PACKAGE WITH LEADFRAME LOCKED ENCAPSULATION AND METHOD OF MANUFACTURE THEREFOR | ACCEPTED | 20070801 | 20070816 | [] | H01L2100 | ["H01L2100"] | 7413933 | 20070409 | 20080819 | 438 | 123000 | 72874.0 | HOANG | QUOC | [{"inventor_name_last": "Punzalan", "inventor_name_first": "Jeffrey", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}, {"inventor_name_last": "Ku", "inventor_name_first": "Jae Hun", "inventor_city": "Singapore", "inventor_state": "", "inventor_country": "SG"}, {"inventor_name_last": "Han",... | A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit ... | 1. A method of manufacturing a semiconductor comprising: providing a leadframe having a die attach paddle and a number of leads; forming a recess in the die attach paddle to provide a number of mold dams around the periphery of the die attach paddle; positioning an integrated circuit in the recess; forming electrical c... | <SOH> BACKGROUND ART <EOH>In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of a multiplicity of interconnected int... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a partial cross-sectional view of a leadframe in an intermediate stage of manufacture in accordance with the present invention; FIG. 2 is the structure of FIG. 1 after processing of a mask on the surface of the leadframe; FIG. 3 is the structure of FIG. 2 after an... | CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/478,433 filed Jun. 12, 2003, and the subject matter thereof is hereby incorporated herein by reference thereto. This application is a continuation of U.S. Non Provisional Patent Application Ser.... | H | 67H01 | 185H01L | 21 | 00 | |||
11809719 | US20110068350A1-20110324 | Diamond semiconductor devices and associated methods | ACCEPTED | 20110309 | 20110324 | [] | H01L310312 | ["H01L310312", "H01L21223"] | 8110846 | 20070531 | 20120207 | 257 | 079000 | 63495.0 | TORNOW | MARK | [{"inventor_name_last": "Sung", "inventor_name_first": "Chien-Min", "inventor_city": "Tansui", "inventor_state": "", "inventor_country": "TW"}] | Semiconductor devices and methods for making such devices are provided. One such method may include forming a transparent diamond layer having a SiC layer coupled thereto, where the SiC layer has a crystal structure that is substantially epitaxially matched to the transparent diamond layer, forming epitaxially a plural... | 1. A semiconductor device, comprising: a diamond substrate; a transparent diamond layer positioned parallel to the diamond substrate; a plurality of semiconductor layers coupled between the transparent diamond layer and the diamond substrate; and a SiC layer coupled directly to the transparent diamond layer and facing ... | <SOH> BACKGROUND OF THE INVENTION <EOH>In many developed countries, major portions of the populations consider electronic devices to be integral to their lives. Such increasing use and dependence has generated a demand for electronics devices that are smaller and faster. As electronic circuitry increases in speed and d... | <SOH> SUMMARY OF THE INVENTION <EOH>Accordingly, the present invention provides diamond semiconductor devices having improved thermal properties and methods for making such devices. In one aspect, for example, a semiconductor device is provided having a diamond substrate, a transparent diamond layer positioned parallel... | FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and associated methods. Accordingly, the present invention involves the electrical and material science fields. BACKGROUND OF THE INVENTION In many developed countries, major portions of the populations consider electronic devices t... | H | 67H01 | 185H01L | 3103 | 12 | |||
10534956 | US20070273013A1-20071129 | Packaging for Micro Electro-Mechanical Systems and Methods of Fabricating Thereof | ACCEPTED | 20071114 | 20071129 | [] | H01L2320 | ["H01L2320", "H01L2154"] | 8476096 | 20070427 | 20130702 | 438 | 050000 | 58033.0 | GEBREYESUS | YOSEF | [{"inventor_name_last": "Kohl", "inventor_name_first": "Paul", "inventor_city": "Atlanta", "inventor_state": "GA", "inventor_country": "US"}, {"inventor_name_last": "Ayazi", "inventor_name_first": "Farrokh", "inventor_city": "Atlanta", "inventor_state": "GA", "inventor_country": "US"}] | Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial struc... | 1. A micro electro-mechanical device packaging system, comprising: a micro electro-mechanical device formed on a substrate layer; and a protective structure protecting at least a portion of the micro electro-mechanical device, wherein the protective structure is formed on the substrate layer and surrounds a gas cavity ... | <SOH> BACKGROUND <EOH>Adapting microelectronic packages to micro electro-mechanical system (MEMS) devices involves several challenging packaging requirements. The typical three-dimensional and moving elements of many MEMS devices generally require some sort of cavity package to provide free space above the active surf... | <SOH> SUMMARY <EOH>Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposab... | CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to copending U.S. provisional application entitled, “Hermetic Packaging for MEMS,” having Ser. No. 60/553,178, filed Mar. 15, 2004, which is entirely incorporated herein by reference. TECHNICAL FIELD The present disclosure is generally related to m... | H | 67H01 | 185H01L | 23 | 20 | |||
11862174 | US20080179696A1-20080731 | Micromechanical Device with Microfluidic Lubricant Channel | ACCEPTED | 20080716 | 20080731 | [] | H01L2984 | ["H01L2984"] | 7932569 | 20070926 | 20110426 | 257 | 415000 | 99963.0 | PERT | EVAN | [{"inventor_name_last": "Chen", "inventor_name_first": "Dongmin", "inventor_city": "Saratoga", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Worley", "inventor_name_first": "William Spencer", "inventor_city": "Half Moon Bay", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_nam... | A micromechanical device assembly includes a micromechanical device enclosed within a processing region and a lubricant channel formed through an interior wall of the processing region and in fluid communication with the processing region. Lubricant is injected into the lubricant channel via capillary forces and held t... | 1. A device assembly, comprising: a micromechanical device enclosed within a processing region; and a lubricant channel formed through at least one interior wall of the processing region to be in fluid communication with the processing region, wherein a substantial length of the lubricant channel extends into said at l... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention Embodiments of the present invention relate generally to micro-electro-mechanical and nano-electro-mechanical systems and more specifically to such systems having one or more microfluidic lubricant channels. 2. Description of the Related Art As is well kn... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention generally relates to a micromechanical device that has an improved usable lifetime due to the presence of one or more channels that contain and deliver a lubricant that can reduce the likelihood of stiction occurring between the various moving parts of the devic... | CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/847,831, filed Sep. 27, 2006, entitled “Method of Sealing a Microfluidic Lubricant Channel Formed in a Micromechanical Device,” which is herein incorporated by reference. BACKGROUND OF THE INVE... | H | 67H01 | 185H01L | 29 | 84 | |||
11755814 | US20080157368A1-20080703 | MULTI-LAYERED METAL LINE OF SEMICONDUCTOR DEVICE HAVING EXCELLENT DIFFUSION BARRIER AND METHOD FOR FORMING THE SAME | ACCEPTED | 20080619 | 20080703 | [] | H01L21768 | ["H01L21768", "H01L23538"] | 7531902 | 20070531 | 20090512 | 257 | 751000 | 83468.0 | QUACH | TUAN | [{"inventor_name_last": "KIM", "inventor_name_first": "Jeong Tae", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "KIM", "inventor_name_first": "Baek Mann", "inventor_city": "Kyoungki-do", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "K... | A multi-layered metal line of a semiconductor device has a lower metal line and an upper metal line. The upper metal line includes a diffusion barrier, which is made of a stack of a first WNx layer, a WCyNx layer and a second WNx layer. | 1. A multi-layered metal line of a semiconductor device comprising: a lower metal line; an upper metal line; and a diffusion barrier formed between the lower and upper metal lines, wherein the diffusion barrier comprises a stack of a first WNx layer, a WCyNx layer, and a second WNx layer. 2. The multi-layered metal lin... | <SOH> BACKGROUND OF THE INVENTION <EOH>The present invention relates to a multi-layered metal line of a semiconductor device and a method for forming the same, and more particularly to a multi-layered metal line of a semiconductor device, which has an excellent diffusion barrier and a method for forming the same. Memor... | <SOH> SUMMARY OF THE INVENTION <EOH>An embodiment of the present invention is directed to a multi-layered metal line of a semiconductor device which has a diffusion barrier having superior capability for preventing diffusion of copper and a method for forming the same. In one embodiment, there is provided a multi-layer... | CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to Korean patent application number 10-2006-0137251 filed on Dec. 28, 2006, which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION The present invention relates to a multi-layered metal line of a semiconductor... | H | 67H01 | 185H01L | 217 | 68 | |||
11968099 | US20090166769A1-20090702 | METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES | ACCEPTED | 20090617 | 20090702 | [] | H01L2900 | ["H01L2900", "H01L21336"] | 8021940 | 20071231 | 20110920 | 438 | 199000 | 67292.0 | PHAM | THANHHA | [{"inventor_name_last": "Metz", "inventor_name_first": "Matthew V.", "inventor_city": "Hillsboro", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Doczy", "inventor_name_first": "Mark L.", "inventor_city": "Meridian", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "... | Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. | 1. A method comprising: forming a gate dielectric layer on a substrate; forming a metal gate layer on the gate dielectric layer; and forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. 2. The method of claim 1 further comprising wherein the substrate comprise... | <SOH> BACKGROUND OF THE INVENTION <EOH>Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. The MOSFET may... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conj... | BACKGROUND OF THE INVENTION Microelectronic devices are often manufactured in and on silicon wafers and on other types other substrates. Such integrated circuits may include millions of transistors, such as metal oxide semiconductor (MOS) field effect transistors, as are well known in the art. The MOSFET may comprise a... | H | 67H01 | 185H01L | 29 | 00 | |||
11834367 | US20080035998A1-20080214 | PSEUDO SOI SUBSTRATE AND ASSOCIATED SEMICONDUCTOR DEVICES | ACCEPTED | 20080130 | 20080214 | [] | H01L29786 | ["H01L29786", "H01L2900"] | 7538392 | 20070806 | 20090526 | 257 | 347000 | 67400.0 | BOOTH | RICHARD | [{"inventor_name_last": "Ramaswamy", "inventor_name_first": "Nirmal", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "Blomiley", "inventor_name_first": "Eric", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}, {"inventor_name_last": "Drewes... | The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating... | 1.-34. (canceled) 35. A device, comprising: a substrate comprised of a semiconductor material; and a plurality of spaced apart dielectric layers encapsulated within the substrate. 36. The device of claim 1, wherein each of the plurality of spaced apart dielectric layers are surrounded by the semiconductor material. 37.... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming a pseudo SOI substrate and integrated circuit devices thereabove. 2. Description of the Related Art There ... | <SOH> SUMMARY OF THE INVENTION <EOH>The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to deline... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is generally related to the field of manufacturing integrated circuit devices, and, more particularly, to a method of forming a pseudo SOI substrate and integrated circuit devices thereabove. 2. Description of the Related Art There is a constan... | H | 67H01 | 185H01L | 297 | 86 | |||
11735009 | US20070254456A1-20071101 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | ACCEPTED | 20071018 | 20071101 | [] | H01L2130 | ["H01L2130"] | 8900970 | 20070413 | 20141202 | 438 | 458000 | 75592.0 | HENRY | CALEB | [{"inventor_name_last": "MARUYAMA", "inventor_name_first": "Junya", "inventor_city": "Ebina,", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "JINBO", "inventor_name_first": "Yasuhiro", "inventor_city": "Atsugi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "SHOJI", "... | A technique for peeling an element manufactured through a process at relatively low temperature (lower than 500° C.) from a substrate and transferring the element to a flexible substrate (typically, a plastic film). With the use of an existing manufacturing device for a large glass substrate, a molybdenum film (Mo film... | 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a molybdenum film over a substrate; forming a molybdenum oxide film over the molybdenum film; forming an insulating film over the molybdenum oxide film; forming a semiconductor film having an amorphous structure over the insulating f... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor device which has a circuit including a thin film transistor (hereinafter referred to as a TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an elect... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention discloses a technique for separating (in other words, peeling) an element which is formed through a process at relatively low temperature (lower than 500° C.), typically a TFT using an amorphous silicon film or the like, a TFT using an organic semiconductor film... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which has a circuit including a thin film transistor (hereinafter referred to as a TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electronic devic... | H | 67H01 | 185H01L | 21 | 30 | |||
11962386 | US20080268624A1-20081030 | Method of Fabricating Semiconductor Device | ACCEPTED | 20081016 | 20081030 | [] | H01L21425 | ["H01L21425"] | 7858491 | 20071221 | 20101228 | 438 | 433000 | 96173.0 | NICELY | JOSEPH | [{"inventor_name_last": "Kwak", "inventor_name_first": "Noh Yeal", "inventor_city": "Icheon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Jang", "inventor_name_first": "Min Sik", "inventor_city": "Icheon-si", "inventor_state": "", "inventor_country": "KR"}] | This invention relates to a method of fabricating a semiconductor device. A P well for a cell junction may be formed by performing an ion implantation process employing a zero tilt condition. Stress caused by collision between a dopant and a Si lattice within a semiconductor substrate may be minimized and, therefore st... | 1. A method of fabricating a semiconductor device, the method comprising: forming a Triple N (TN) well in a semiconductor substrate; forming a P well within the TN well by employing a zero tilt-angle; forming an isolation mask over the semiconductor substrate; etching the isolation mask and the semiconductor substrate ... | <SOH> BACKGROUND OF THE INVENTION <EOH>Generally, in a semiconductor device, a well junction may be formed by performing an ion implantation process in order to control the threshold voltage of a transistor. In recent years, as devices are highly integrated, the well junction may be formed by implanting an impurity of ... | <SOH> SUMMARY OF THE INVENTION <EOH>This invention is directed to a method of fabricating a semiconductor device wherein a P well is formed by performing an ion implantation process at a zero tilt condition, so that a stress caused by collision of a dopant and a Si lattice may be minimized. NOP fail due to disturbance ... | CROSS-REFERENCES TO RELATED APPLICATIONS This invention claims priority to Korean patent application number 10-2007-41414, filed on Apr. 27, 2007, the disclosure of which is incorporated by reference in its entirety. TECHNICAL FIELD This invention relates to a method of fabricating a semiconductor device and, more part... | H | 67H01 | 185H01L | 214 | 25 | |||
11752955 | US20080001284A1-20080103 | Heat Dissipation Structure With Aligned Carbon Nanotube Arrays and Methods for Manufacturing And Use | ACCEPTED | 20071218 | 20080103 | [] | H01L23373 | ["H01L23373", "C01B3102"] | 8890312 | 20070524 | 20141118 | 257 | 712000 | 67733.0 | NGUYEN | DUY | [{"inventor_name_last": "Yuen", "inventor_name_first": "Matthew", "inventor_city": "Hong Kong", "inventor_state": "", "inventor_country": "CN"}, {"inventor_name_last": "Zhang", "inventor_name_first": "Kai", "inventor_city": "Hong Kong", "inventor_state": "", "inventor_country": "CN"}] | A heat dissipation structure with aligned carbon nanotube arrays formed on both sides. The carbon nanotube arrays in between a heat source and a cooler are used as thermal interface material extending and dissipating heat directly from a heat source surface to a cooler surface. In some embodiments, an adhesive material... | 1. A packaged semiconductor structure, comprising: a heat source; a heat sink; an aligned array of carbon nanotubes which thermally connects said source to said sink; and a peripheral connecting material which runs along at least some edges of said aligned array, while mechanically contacting said source and said sink ... | <SOH> BACKGROUND OF THE INVENTIONS <EOH>The present application generally relates to thermal management solutions, and more specifically to heat dissipation structures using aligned carbon nanotube arrays, and to methods of fabricating such a heat dissipation structure and applying it to a package. With the developmen... | <SOH> SUMMARY OF THE INVENTIONS <EOH>The present inventions provide a new way to use high thermal conductivity carbon nanotube (CNT) arrays. To avoid the process incompatibility of carbon nanotube growth and device fabrication the aligned CNT arrays are formed on heat dissipation structure surfaces instead of a heat s... | CROSS-REFERENCE TO OTHER APPLICATION The present application claims priority under 35 U.S.C. § 119(e) of U.S. Patent Application No. 60/808,433, filed May 26, 2006, and entitled Heat Dissipation Structure with Carbon Nanotube Arrays and Method for Manufacturing the Same. BACKGROUND OF THE INVENTIONS The present applica... | H | 67H01 | 185H01L | 233 | 73 | |||
11761080 | US20070284566A1-20071213 | COMPOSITE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | ACCEPTED | 20071129 | 20071213 | [] | H01L2906 | ["H01L2906"] | 7880180 | 20070611 | 20110201 | 257 | 088000 | 98225.0 | FOX | BRANDON | [{"inventor_name_last": "Tada", "inventor_name_first": "Yasuhiro", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Hanya", "inventor_name_first": "Akihiko", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}] | The disclosed subject matter provides a composite semiconductor device which can include a common substrate, a first semiconductor light emitting structure, and a second semiconductor light emitting structure. The first semiconductor light emitting structure can include an epitaxial grown layer containing a light emitt... | 1. A composite semiconductor device, comprising: a common substrate; a first semiconductor light emitting structure; and a second semiconductor light emitting structure, wherein the first semiconductor light emitting structure includes an epitaxial grown layer having a light emitting layer and is located adjacent at le... | <SOH> BACKGROUND <EOH>1. Field The present disclosed subject matter relates to a semiconductor composite device and method of manufacturing the same. More particularly, it relates to a composite semiconductor device including a plurality of light emitting units on the same substrate and method of manufacturing the same... | <SOH> SUMMARY <EOH>The disclosed subject matter has been made in consideration of the above described characteristics, deficiencies, problems and features of the above described conventional art and can include providing a composite semiconductor device that is excellent in heat radiation, color mixture, quality, stabi... | This application claims the priority benefit under 35 U.S.C. §119 of Japanese Patent Application No. 2006-162534 filed on Jun. 12, 2006, which is hereby incorporated in its entirety by reference. BACKGROUND 1. Field The present disclosed subject matter relates to a semiconductor composite device and method of manufactu... | H | 67H01 | 185H01L | 29 | 06 | |||
11683648 | US20080220609A1-20080911 | Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing | ACCEPTED | 20080828 | 20080911 | [] | H01L21302 | ["H01L21302"] | 7541290 | 20070308 | 20090602 | 438 | 689000 | 95738.0 | CHEN | KIN CHAN | [{"inventor_name_last": "Chang", "inventor_name_first": "Chong Kwang", "inventor_city": "Kangwon", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Park", "inventor_name_first": "Wan Jae", "inventor_city": "Kyunggi", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Tsou",... | Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved ... | 1. A method of forming an integrated circuit device, comprising the steps of: forming a first electrically insulating layer on a semiconductor wafer; forming mask pattern on the first electrically insulating layer; selectively widening first portions of the mask pattern extending adjacent a periphery of the semiconduct... | <SOH> BACKGROUND OF THE INVENTION <EOH>Processes for fabricating integrated circuit devices typically include the formation of a relatively large array of integrated circuits that are replicated at side-by-side locations on an integrated circuit wafer. These fabricating processes also typically include the formation o... | <SOH> SUMMARY OF THE INVENTION <EOH>Methods of forming integrated circuit devices according to embodiments of the present invention include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are ... | FIELD OF THE INVENTION The present invention relates to integrated circuit fabrication methods and, more particularly, to methods of fabricating mask patterns on semiconductor wafers. BACKGROUND OF THE INVENTION Processes for fabricating integrated circuit devices typically include the formation of a relatively large a... | H | 67H01 | 185H01L | 213 | 02 | |||
11907904 | US20080136293A1-20080612 | Multilayer piezoelectric element | ACCEPTED | 20080530 | 20080612 | [] | H01L41083 | ["H01L41083", "H01L41187"] | 7518295 | 20071018 | 20090414 | 310 | 366000 | 92130.0 | DOUGHERTY | THOMAS | [{"inventor_name_last": "Mochizuki", "inventor_name_first": "Kazuo", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Nagata", "inventor_name_first": "Kazuo", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Sawara", "in... | A multilayer piezoelectric element has a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered. The plurality of internal electrodes comprise a first electrode and a second electrode. The laminate body is provided with a metal oxide laye... | 1. A multilayer piezoelectric element comprising a laminate body in which a plurality of piezoelectric bodies and a plurality of internal electrodes are alternately laminated and sintered, wherein the plurality of internal electrodes comprise a first electrode and a second electrode, wherein the laminate body is provid... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a multilayer piezoelectric element used in a fuel injection device or the like. 2. Related Background Art A conventionally known multilayer piezoelectric element is, for example, the one described in Japanese Patent Applic... | <SOH> SUMMARY OF THE INVENTION <EOH>When the metal oxide layers were provided simply in the same layers as the internal electrodes in the laminate body as in the above-described conventional technology, it was, however, sometimes the case that occurrence of cracks extending in the laminate direction of the laminate bod... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer piezoelectric element used in a fuel injection device or the like. 2. Related Background Art A conventionally known multilayer piezoelectric element is, for example, the one described in Japanese Patent Application Laid-... | H | 67H01 | 185H01L | 410 | 83 | |||
11925352 | US20080044959A1-20080221 | BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES | ACCEPTED | 20080206 | 20080221 | [] | H01L2186 | ["H01L2186"] | 7608506 | 20071026 | 20091027 | 438 | 257000 | 61099.0 | LEBENTRITT | MICHAEL | [{"inventor_name_last": "Cheng", "inventor_name_first": "Kangguo", "inventor_city": "Guilderland", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Hsu", "inventor_name_first": "Louis", "inventor_city": "Fishkill", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Mand... | A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channe... | 1. A method for forming a semiconductor structure in a semiconductor wafer including a semiconductor substrate, a semiconductor layer including a plurality of semiconductor bodies, and a buried dielectric layer separating the semiconductor substrate from the semiconductor layer, the method comprising: forming a plurali... | <SOH> BACKGROUND OF THE INVENTION <EOH>Dynamic random access memory (DRAM) devices are the most commonly used type of semiconductor memory and, thus, are found in many integrated circuit designs. DRAM devices are also frequently embedded into application specific integrated circuits, such as processors and logic devic... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention is generally directed to a semiconductor-on-insulator (SOI) structure that incorporates a body contact extending through the buried dielectric layer and, thereby, coupling an SOI body with an underlying semiconductor substrate and methods of forming such body c... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of application Ser. No. 11/216,386, filed Aug. 31, 2005, which is hereby incorporated by reference herein in its entirety. This application is related to commonly-assigned application Ser. No. 11/216,395, filed on Aug. 31, 2005, entitled “SEMICOND... | H | 67H01 | 185H01L | 21 | 86 | |||
11777276 | US20080054946A1-20080306 | SEMICONDUCTOR INTEGRATED CIRCUIT | ACCEPTED | 20080220 | 20080306 | [] | H01L2702 | ["H01L2702", "H03K190944"] | 7569899 | 20070712 | 20090804 | 257 | 393000 | 79459.0 | MANDALA | VICTOR | [{"inventor_name_last": "KANNO", "inventor_name_first": "Yusuke", "inventor_city": "Kodaira", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Yoshizumi", "inventor_name_first": "Kenichi", "inventor_city": "Fukuoka", "inventor_state": "", "inventor_country": "JP"}] | Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second po... | 1. A semiconductor integrated circuit comprising: a plurality of first power switches for receiving a ground voltage; first ground lines connected to the first power switches; a plurality of second power switches that are connected to the first ground lines, and have gate insulating films being thinner than gate insula... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly relates to a technique useful for use in system LSI for mobile device, microprocessor and the like. 2. Description of Related Art The number of circuit blocks integrated... | <SOH> SUMMARY OF THE INVENTION <EOH>In consideration of layout or area of the power switches, and furthermore thickness of the gate insulating film, the inventor made investigation on a unit that enables high-speed operation of circuit blocks, and performs close power shutdown control while reducing the leakage current... | CLAIM OF PRIORITY The present application claims priority from Japanese application JP 2006-236119 filed on Aug. 31, 2006, the content of which is hereby incorporated by reference into this application. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated cir... | H | 67H01 | 185H01L | 27 | 02 | |||
11630930 | US20080111231A1-20080515 | Semiconductor Device Comprising a Housing and a Semiconductor Chip Partly Embedded in a Plastic Housing Composition, and Method for Producing the Same | ACCEPTED | 20080501 | 20080515 | [] | H01L2314 | ["H01L2314", "H01L2102"] | 7781900 | 20070801 | 20100824 | 257 | 789000 | 80120.0 | NGUYEN | DAO | [{"inventor_name_last": "Carmona", "inventor_name_first": "Manuel", "inventor_city": "Barcelona", "inventor_state": "", "inventor_country": "ES"}, {"inventor_name_last": "Legen", "inventor_name_first": "Anton", "inventor_city": "Muenchen", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Wennemu... | One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an in... | 1.-16. (canceled) 17. A semiconductor device comprising: a housing; and a semiconductor chip partly embedded in a plastic housing composition; wherein the plastic housing composition has at least two mixture components, a host component having a softening temperature range in which the plastic housing composition incre... | <SOH> BACKGROUND <EOH>The invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition, and to a method for producing the same. The power loss that arises in BGA housings (ball grid array), for example, is not generated with a uniform and const... | <SOH> SUMMARY <EOH>One embodiment of the invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition in which the plastic housing composition ensures that a limited heat compensation is provided in the case of an increased power loss occurring... | BACKGROUND The invention provides a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition, and to a method for producing the same. The power loss that arises in BGA housings (ball grid array), for example, is not generated with a uniform and constant magnitud... | H | 67H01 | 185H01L | 23 | 14 | |||
11795251 | US20080122052A1-20080529 | Member for Semiconductor Device and Production Method Thereof | ACCEPTED | 20080514 | 20080529 | [] | H01L2314 | ["H01L2314", "C22C105", "B22F314", "B22F704"] | 7749430 | 20070713 | 20100706 | 419 | 026000 | 69222.0 | CHU | CHRIS | [{"inventor_name_last": "Fukui", "inventor_name_first": "Akira", "inventor_city": "Toyama", "inventor_state": "", "inventor_country": "JP"}] | A member for a semiconductor device of low price, capable of forming a high quality plating layer on a surface, having heat conductivity at high temperature (100° C.) of more than or equal to 180 W/m·K and toughness that will not cause breaking due to screwing, and will not cause solder breaking due to heat stress when... | 1. A member for a semiconductor device (1) having a coefficient of thermal expansion ranging from 6.5×10−6/K to 15×10−6/K inclusive, and heat conductivity at 100° C. of more than or equal to 180 W/m·K, comprising: a base material (11) formed of an aluminum-silicon carbide composite material starting from powder materia... | <SOH> BACKGROUND ART <EOH>For example, in a power device which is a semiconductor device of high performance, for insulation of a silicon (Si) chip serving as a semiconductor integrated circuit device (IC), such a structure is employed that an Si chip is soldered on aluminum nitride (AlN) sintered substrate having copp... | <SOH> BRIEF DESCRIPTION OF DRAWINGS <EOH>FIG. 1 A cross section view showing a schematic section of a member for a semiconductor device which is one embodiment of the present invention. FIG. 2 A schematic section view showing an insulated gate bipolar transistor (IGBT) unit incorporated into an automobile or the like, ... | TECHNICAL FIELD The present invention generally relates to a member for a semiconductor device and a production method thereof, and more specifically to a member for a semiconductor device serving as a heat radiator member such as a heat spreader or lid member constituting a semiconductor device, and a production metho... | H | 67H01 | 185H01L | 23 | 14 | |||
11656759 | US20080173884A1-20080724 | Wafer level phosphor coating method and devices fabricated utilizing method | ACCEPTED | 20080709 | 20080724 | [] | H01L3300 | ["H01L3300"] | 9024349 | 20070122 | 20150505 | 257 | 099000 | 67597.0 | LIGAI | MARIA | [{"inventor_name_last": "Chitnis", "inventor_name_first": "Ashay", "inventor_city": "Santa Barbara", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Ibbetson", "inventor_name_first": "James", "inventor_city": "Santa Barbara", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_... | Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals... | 1. A method for fabricating light emitting diode (LED) chips, comprising: providing a plurality of LEDs; depositing pedestals on said LEDs, each of said pedestals in electrical contact with one of said LEDs; forming a coating over said LEDs, said coating burying at least some of said pedestals; and planarizing said coa... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention This invention relates to methods for fabricating semiconductor devices and in particular methods for wafer level coating of light emitting diodes. 2. Description of the Related Art Light emitting diodes (LED or LEDs) are solid state devices that convert ... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention discloses new methods for fabricating semiconductor devices such as LED chips at the wafer level, and discloses LED chips and LED chip wafers fabricated using the methods. One method for fabricating light emitting diode (LED) chips according to the present inven... | This invention was made with Government support under Contract USAF 05-2-5507. The Government has certain rights in this invention BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to methods for fabricating semiconductor devices and in particular methods for wafer level coating of light emit... | H | 67H01 | 185H01L | 33 | 00 | |||
11659360 | US20080042159A1-20080221 | Transparent Electrode for Semiconductor Light-Emitting Device | ACCEPTED | 20080206 | 20080221 | [] | H01L3300 | ["H01L3300", "H01L2128"] | 7498611 | 20070523 | 20090303 | 257 | 099000 | 87893.0 | HO | TU TU | [{"inventor_name_last": "Eitoh", "inventor_name_first": "Nobuo", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Muraki", "inventor_name_first": "Noritaka", "inventor_city": "Chiba", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Miki", "inven... | A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device includes a p-type semiconductor layer (5), a contact metal layer (1) formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer (12) formed on the contact metal layer and having a lower magnitude ... | 1. A transparent electrode for a gallium nitride-based compound semiconductor light-emitting device, comprising a p-type semiconductor layer, a contact metal layer formed by ohmic contact on the p-type semiconductor layer, an current diffusion layer formed on the contact metal layer and having a lower magnitude of resi... | <SOH> BACKGROUND ART <EOH>In recent years, the GaN-based compound semiconductor materials have been attracting attention as semiconductor materials for use in the short wavelength light-emitting devices. The GaN-based compound semiconductors are formed on sapphire single crystals and various oxides and Group III-V com... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a schematic view illustrating the cross section of a light-emitting device provided with a transparent electrode of this invention. FIG. 2 is a schematic view illustrating the cross section of a gallium nitride-based compound semiconductor light-emitting device pr... | CROSS REFERENCE TO RELATED APPLICATIONS This application is an application filed under 35 U.S.C. §111(a) claiming the benefit pursuant to 35 U.S.C. §119(e)(1) of the filing dates of Provisional Application No. 60/602,648 filed Aug. 19, 2004 and Japanese Application No. 2004-228968 filed Aug. 5, 2004 pursuant to 35 U.S.... | H | 67H01 | 185H01L | 33 | 00 | |||
11797401 | US20070257302A1-20071108 | Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same | ACCEPTED | 20071024 | 20071108 | [] | H01L29788 | ["H01L29788", "H01L21336"] | 7776687 | 20070503 | 20100817 | 438 | 257000 | 89314.0 | PATEL | REEMA | [{"inventor_name_last": "Kang", "inventor_name_first": "Chang-Seok", "inventor_city": "Seongnam-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Shin", "inventor_name_first": "Yoo-Cheol", "inventor_city": "Suwon-si", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "C... | A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycr... | 1. A semiconductor device, comprising: a polysilicon layer on a substrate, the polysilicon layer being a gate electrode of a transistor; a middle conductive layer and a top metal layer on the polysilicon layer; an opening through the middle conductive layer and the top metal layer exposing the polysilicon layer; and a ... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to a semiconductor device having a gate contact structure capable of reducing interfacial resistance and a method of f... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention is therefore directed to a semiconductor device having a gate contact structure and a method of manufacturing the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art. At least one of the abov... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to a semiconductor device having a gate contact structure capable of reducing interfacial resistance and a method of forming the ... | H | 67H01 | 185H01L | 297 | 88 | |||
11817597 | US20090301556A1-20091210 | MULTILAYER ORGANIC SOLAR CELL | ACCEPTED | 20091125 | 20091210 | [] | H01L3100 | ["H01L3100"] | 8237048 | 20070831 | 20120807 | 136 | 256000 | 63248.0 | GARDNER | SHANNON | [{"inventor_name_last": "Kawano", "inventor_name_first": "Kenji", "inventor_city": "Sakai-shi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Ito", "inventor_name_first": "Norihiro", "inventor_city": "Hirakata-shi", "inventor_state": "", "inventor_country": "JP"}] | Disclosed is a multilayer organic solar cell having a structure wherein an inter-layer (3) is arranged between a first photoactive layer (1) and a second photoactive layer (2). This structure is obtained by forming the inter-layer (3) on the first photoactive layer (1) which is formed from an organic compound solution ... | 1. A multilayer organic solar cell comprising: a first photoactive layer containing a donor material and an acceptor material; an inter-layer formed on the first photoactive layer; and a second photoactive layer formed of a solution of an organic compound containing the donor material and the acceptor material on the i... | <SOH> BACKGROUND ART <EOH>In recent years, energy consumption has dramatically increased with growth of industries. In the future, further increase in demand for energy is expected. Against this backdrop, today's demands are placed on the development of production technology of economic and high-performance clean energ... | <SOH> BRIEF DESCRIPTION OF DRAWING <EOH>FIG. 1 is a schematic sectional view showing configuration of a multilayer organic solar cell as an example of an embodiment according to the present invention. detailed-description description="Detailed Description" end="lead"? | TECHNICAL FIELD The present invention relates to a multilayer organic solar cell in which a plurality of photoactive layers which receive light and generate electric power are stacked to each other. BACKGROUND ART In recent years, energy consumption has dramatically increased with growth of industries. In the future, f... | H | 67H01 | 185H01L | 31 | 00 | |||
11948414 | US20090140341A1-20090604 | INDEPENDENT N-TIPS FOR MULTI-GATE TRANSISTORS | ACCEPTED | 20090520 | 20090604 | [] | H01L2976 | ["H01L2976", "H01L21336"] | 7629643 | 20071130 | 20091208 | 257 | 213000 | 86613.0 | TRAN | TAN | [{"inventor_name_last": "Pillarisetty", "inventor_name_first": "Ravi", "inventor_city": "Portland", "inventor_state": "OR", "inventor_country": "US"}, {"inventor_name_last": "Datta", "inventor_name_first": "Suman", "inventor_city": "University Park", "inventor_state": "PA", "inventor_country": "US"}, {"inventor_name_la... | Independent n-tips for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent t... | 1. An apparatus comprising: a semiconductor fin comprising a semiconductor fin material; one or more multi-gate pull down (PD) devices coupled with the semiconductor fin, the one or more PD devices having an n-tip dopant concentration in the semiconductor fin material adjacent to the one or more PD devices; and one or ... | <SOH> BACKGROUND <EOH>Generally, semiconductor devices such as static random access memory (SRAM) require sufficient static noise margin to maintain cell stability during read operations. | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to lo similar elements and in which: FIGS. 1 a - 1 c provide a top-down view of independent n-tips... | BACKGROUND Generally, semiconductor devices such as static random access memory (SRAM) require sufficient static noise margin to maintain cell stability during read operations. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures ... | H | 67H01 | 185H01L | 29 | 76 | |||
11749898 | US20080284021A1-20081120 | Method for FEOL and BEOL Wiring | ACCEPTED | 20081105 | 20081120 | [] | H01L2144 | ["H01L2144", "H01L2348"] | 7790611 | 20070517 | 20100907 | 438 | 653000 | 76490.0 | PAYEN | MARVIN | [{"inventor_name_last": "Anderson", "inventor_name_first": "Brent A.", "inventor_city": "Jerhico", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_name_last": "Ellis-Monaghan", "inventor_name_first": "John J.", "inventor_city": "Grand Isle", "inventor_state": "VT", "inventor_country": "US"}, {"inventor_na... | A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to ... | 1. A method for forming a conductive structure of sub-lithographic dimension comprising: forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of said topographic feature, said exposed... | <SOH> FIELD OF THE INVENTION <EOH>The present invention relates to semiconductor devices and structures generally, and particularly, to a novel conductive structure that can be used for Front End of Line (FEOL) and Back End of Line (BEOL) applications. | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures. The present invention is directed to semiconductor conductive structures and a method for forming the conductive structures that is applicable for both FEOL an... | FIELD OF THE INVENTION The present invention relates to semiconductor devices and structures generally, and particularly, to a novel conductive structure that can be used for Front End of Line (FEOL) and Back End of Line (BEOL) applications. Description of the Prior Art Techniques for forming small conductive structure... | H | 67H01 | 185H01L | 21 | 44 | |||
11710486 | US20070200242A1-20070830 | Semiconductor apparatus | ACCEPTED | 20070815 | 20070830 | [] | H01L2352 | ["H01L2352"] | 7884478 | 20070226 | 20110208 | 257 | 690000 | 69194.0 | TRAN | TRANG | [{"inventor_name_last": "Azuma", "inventor_name_first": "Shoji", "inventor_city": "Tokyo", "inventor_state": "", "inventor_country": "JP"}] | In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-l... | 1. A semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus comprising a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first... | <SOH> BACKGROUND OF THE INVENTION <EOH>This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a wiring pattern formed in a region under a bonding pad. Following development of a highly-integrated semiconductor apparatus, a device pattern is more and more miniaturize... | <SOH> SUMMARY OF THE INVENTION <EOH>It is therefore an object of this invention to provide a semiconductor apparatus having a bonding pad which is capable of preventing a wiring from being peeled off or broken due to a mechanical shock during bonding and which allows a fine pass-through wiring to be arranged under the... | This application claims priority to prior Japanese patent application JP 2006-49625, the disclosure of which is incorporated herein by reference. BACKGROUND OF THE INVENTION This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a wiring pattern formed in a region un... | H | 67H01 | 185H01L | 23 | 52 | |||
11718389 | US20070296406A1-20071227 | Current Induced Magnetoresistance Device | ACCEPTED | 20071212 | 20071227 | [] | H01L4308 | ["H01L4308", "G01R3309", "G11C1116"] | 7626857 | 20070501 | 20091201 | 365 | 158000 | 99911.0 | LUU | PHO | [{"inventor_name_last": "Shin", "inventor_name_first": "Kyung-Ho", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Hoany Yen", "inventor_name_first": "Nguyen", "inventor_city": "Seoul", "inventor_state": "", "inventor_country": "KR"}, {"inventor_name_last": "Yi", "inve... | The present invention provides for a current induced switching magnetoresistance device comprising a magnetic multilayer composed of a first ferromagnetic layer, a nonferromagnetic layer, and a second ferromagnetic layer, wherein the first ferromagnetic layer has an upper electrode, the second ferromagnetic layer pinne... | 1. A current induced switching magnetoresistance device comprising: a multilayered structure consisted of a first ferromagnetic layer, a non-ferromagnetic layer and a second ferromagnetic layer; an upper electrode provided in the first ferromagnetic layer; an antiferromagnet pinned at the second ferromagnetic layer; an... | <SOH> BACKGROUND ART <EOH>Since a great magnetoresistance (GMR) was discovered in a ferromagnetic thin film, its application has been suggested to various fields. A typical application thereof is a magnetic random access memory (MRAM), which is a solid-state memory that can re-write and read recorded data many times b... | <SOH> SUMMARY OF THE INVENTION <EOH>In order to solve the above-mentioned critical issues, the present invention provides for a current-induced magnetization switching (CIMS) device comprising a multilayered laminated structure consisting of a first ferromagnetic layer, a nonmagnetic layer and a second ferromagnetic l... | TECHNICAL FIELD The present invention relates to a current induced magnetoresistance device, more particularly to a newly structured device that, by having an extended exchange biased pinned ferromagnetic thin film with an embedded nano-oxide layer, can be switched at lower current density and simultaneously provides a... | H | 67H01 | 185H01L | 43 | 08 | |||
11745044 | US20080277730A1-20081113 | Semiconductor Device Manufactured Using a Laminated Stress Layer | ACCEPTED | 20081029 | 20081113 | [] | H01L2144 | ["H01L2144", "H01L2976"] | 7611939 | 20070507 | 20091103 | 257 | 213000 | 95355.0 | SANDVIK | BENJAMIN | [{"inventor_name_last": "Mehrotra", "inventor_name_first": "Manoj", "inventor_city": "Plano", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Rotondaro", "inventor_name_first": "Antonio L.P", "inventor_city": "Dallas", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": ... | There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed ove... | 1. A method of manufacturing a semiconductor device, comprising: forming gate structures over a semiconductor substrate, including forming gate electrodes and spacers adjacent the gate electrodes; forming source/drains adjacent the gate structures; forming a laminated stress layer over the gate structures and the semic... | <SOH> BACKGROUND <EOH>In the continuing effort to improve performance of transistors and integrated circuits (ICs) in which they are used, semiconductor device designers strive to increase the drive current of the devices to increase switching speeds and overall performance. One aspect of this effort includes incorpora... | <SOH> SUMMARY <EOH>To address the deficiencies as discussed above, the invention, in one embodiment, provides a method of manufacturing a semiconductor device. This particular embodiment comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the g... | TECHNICAL FIELD The invention and the embodiments discussed herein are directed in general to a semiconductor device, and more specifically to a semiconductor device manufactured using a laminated stress layer. BACKGROUND In the continuing effort to improve performance of transistors and integrated circuits (ICs) in wh... | H | 67H01 | 185H01L | 21 | 44 | |||
11894917 | US20090050903A1-20090226 | Selective wet etching of gold-tin based solder | ACCEPTED | 20090211 | 20090226 | [] | H01L3300 | ["H01L3300", "H01L2144"] | 8617997 | 20070821 | 20131231 | 438 | 689000 | 97385.0 | JONES | ERIC | [{"inventor_name_last": "Chitnis", "inventor_name_first": "Ashay", "inventor_city": "Goleta", "inventor_state": "CA", "inventor_country": "US"}] | The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etchin... | 1. A method for fabricating an electronic device using selective wet etching, the method comprising: providing at least one wafer having at least one first surface; depositing at least one first layer comprising solder material adjacent to the at least one first surface, wherein the solder material comprises Au and Sn;... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to light emitting devices and methods of fabricating light emitting devices. 2. Description of Related Art Light emitting diodes and laser diodes are well known solid state elec... | <SOH> SUMMARY OF THE INVENTION <EOH>The present invention provides improved methods for fabricating devices, particularly methods for patterning one or more materials in light emitting devices. These methods use one or more standard available chemistries to wet etch AuSn solder material, thereby circumventing the need ... | STATEMENT AS TO FEDERALLY SPONSORED RESEARCH This invention was made with Government support under Grant No. 70NANB4H3037 awarded by the Department of Commerce (DOC). The federal government may have certain rights in the invention. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to s... | H | 67H01 | 185H01L | 33 | 00 | |||
11704995 | US20080169728A1-20080717 | Piezoelectric thin film resonator, piezoelectric thin film resonator filter and manufacturing method thereof | ACCEPTED | 20080701 | 20080717 | [] | H01L4104 | ["H01L4104", "H01L4122"] | 7745975 | 20070212 | 20100629 | 310 | 331000 | 72225.0 | BUDD | MARK | [{"inventor_name_last": "Asai", "inventor_name_first": "Kengo", "inventor_city": "Hachioji", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Matsumoto", "inventor_name_first": "Hisanori", "inventor_city": "Kokubunji", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Isob... | A piezoelectric thin film resonator includes: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, and which is formed on a substrate; and an acoustic insulating layer which is formed... | 1. A piezoelectric thin film resonator comprising: a piezoelectric thin film; a laminated structure which includes a first metal electrode film and a second metal electrode film that interpose at least a part of the piezoelectric thin film, the laminated structure being formed on a substrate; and an acoustic insulating... | <SOH> BACKGROUND OF THE INVENTION <EOH>A piezoelectric thin film bulk acoustic wave resonator generally includes a piezoelectric thin film deposited by a thin film forming apparatus, and a resonator unit composed of a first metal electrode film and a second metal electrode film, which are located above and below while ... | <SOH> SUMMARY OF THE INVENTION <EOH>A piezoelectric thin film bulk acoustic wave resonator is characterized in that a Q-value is generally high. However, a trend of new systems requires a much higher Q-value. Similarly, a much higher Q-value as well as downsizing of the system, a high natural resonance frequency, a wid... | CLAIM OF PRIORITY The present invention application claims priority from Japanese application JP2007-6117 filed on Jan. 15, 2007, the content of which is hereby incorporated by reference into this application. FIELD OF THE INVENTION The present invention relates to a piezoelectric thin film resonator, a piezoelectric t... | H | 67H01 | 185H01L | 41 | 04 | |||
11849930 | US20090057699A1-20090305 | LED with Particles in Encapsulant for Increased Light Extraction and Non-Yellow Off-State Color | ACCEPTED | 20090218 | 20090305 | [] | H01L3300 | ["H01L3300"] | 7791093 | 20070904 | 20100907 | 257 | 098000 | 81075.0 | NGUYEN | NIKI | [{"inventor_name_last": "Basin", "inventor_name_first": "Grigoriy", "inventor_city": "San Francisco", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Haque", "inventor_name_first": "Ashim Shatil", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_... | In one embodiment, sub-micron size granules of TiO2, ZrO2, or other white colored non-phosphor inert granules are mixed with a silicone encapsulant and applied over an LED. In one experiment, the granules increased the light output of a GaN LED more than 5% when the inert material was between about 2.5-5% by weight of ... | 1. A light emitting device comprising: a semiconductor light emitting diode (LED); a layer of phosphor over the LED; and an encapsulant over the LED and phosphor directly contacting the phosphor, the encapsulant comprising a substantially transparent material containing inert non-phosphor particles, the particles being... | <SOH> BACKGROUND <EOH>A semiconductor LED, such as a GaN LED, has an index of refraction (e.g., n=2.2-3.0 for GaN) that is much higher than that of air (n=about 1). By encapsulating the LED in a transparent material, such as silicone (n=1.4-1.76), having an intermediate index of refraction, the light extraction is sign... | <SOH> SUMMARY <EOH>In one embodiment, granules of TiOx, ZrOx, or other white non-phosphor inert material are mixed with the substantially transparent encapsulant for LEDs. One suitable encapsulant is silicone. It has been discovered by the Applicants that sub-micron size particles of the inert material, such as TiO 2 ,... | FIELD OF INVENTION This invention relates to light emitting diodes (LEDs) and, in particular, to techniques for improving light extraction. This invention also relates to creating a non-yellow off-state color of an LED having a yellowish phosphor coating. BACKGROUND A semiconductor LED, such as a GaN LED, has an index ... | H | 67H01 | 185H01L | 33 | 00 | |||
11860125 | US20090081831A1-20090326 | WARPAGE CONTROL USING A PACKAGE CARRIER ASSEMBLY | ACCEPTED | 20090311 | 20090326 | [] | H01L2156 | ["H01L2156"] | 7803662 | 20070924 | 20100928 | 438 | 112000 | 58589.0 | NEWTON | VALERIE | [{"inventor_name_last": "Yuan", "inventor_name_first": "Yuan", "inventor_city": "Austin", "inventor_state": "TX", "inventor_country": "US"}, {"inventor_name_last": "Chopin", "inventor_name_first": "Sheila F.", "inventor_city": "Round Rock", "inventor_state": "TX", "inventor_country": "US"}] | A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable... | 1. A method for curing an encapsulant surrounding integrated circuits on a strip to form a strip assembly, wherein the strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit, comprising: placing the strip assembly on a shelf; applying pressure to the strip assem... | <SOH> BACKGROUND <EOH>1. Field This disclosure relates generally to semiconductor packaging, and more specifically, to warpage control of packages using a package carrier assembly. 2. Related Art Packaged semiconductor devices are typically manufactured using various process steps, including die bonding, wire bonding,... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 ... | BACKGROUND 1. Field This disclosure relates generally to semiconductor packaging, and more specifically, to warpage control of packages using a package carrier assembly. 2. Related Art Packaged semiconductor devices are typically manufactured using various process steps, including die bonding, wire bonding, and molding... | H | 67H01 | 185H01L | 21 | 56 | |||
11683023 | US20070232034A1-20071004 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | ACCEPTED | 20070920 | 20071004 | [] | H01L2120 | ["H01L2120"] | 7514306 | 20070307 | 20090407 | 438 | 584000 | 97291.0 | PARKER | JOHN | [{"inventor_name_last": "UTSUNOMIYA", "inventor_name_first": "Sumio", "inventor_city": "Suwa-shi", "inventor_state": "", "inventor_country": "JP"}] | A method for manufacturing a semiconductor device, includes: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous semico... | 1. A method for manufacturing a semiconductor device, comprising: a) spraying a combusted gas onto a member containing a metal element, the combusted gas being obtained by combusting a mixed gas that at least includes a gas containing a hydrogen atom and an oxygen gas; b) spraying the combusted gas onto the amorphous s... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Technical Field Several aspects of the present invention relate to a method for manufacturing a semiconductor thin film and a semiconductor device using the semiconductor thin film. 2. Related Art In displays of forming images using a thin film transistor (hereinafter referred ... | <SOH> SUMMARY <EOH>A method for manufacturing a semiconductor device according to one aspect of the invention includes adding a metal element to enhance recrystallization of a semiconductor to at least a vicinity of a surface of an amorphous semiconductor film by spraying a combusted gas onto a member containing the me... | BACKGROUND OF THE INVENTION 1. Technical Field Several aspects of the present invention relate to a method for manufacturing a semiconductor thin film and a semiconductor device using the semiconductor thin film. 2. Related Art In displays of forming images using a thin film transistor (hereinafter referred to as a “TF... | H | 67H01 | 185H01L | 21 | 20 | |||
11688050 | US20080230905A1-20080925 | Power Semiconductor Module, Method for Producing a Power Semiconductor Module, and Semiconductor Chip | ACCEPTED | 20080911 | 20080925 | [] | H01L2348 | ["H01L2348", "H01L2144"] | 9214442 | 20070319 | 20151215 | 257 | 772000 | 69783.0 | NGUYEN | CUONG | [{"inventor_name_last": "Guth", "inventor_name_first": "Karsten", "inventor_city": "Soest", "inventor_state": "", "inventor_country": "DE"}, {"inventor_name_last": "Torwesten", "inventor_name_first": "Holger", "inventor_city": "Regensburg", "inventor_state": "", "inventor_country": "DE"}] | In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For produc... | 1. A semiconductor power module, in which a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another, wherein the first soldering partner has a first surface directly abutting against the connection l... | <SOH> BACKGROUND <EOH>Power semiconductor modules comprise a number of soldered connections, wherein the most various components must be fixedly and permanently joined with one another. Due to the high temperatures occurring during operation of the power semiconductor modules, as well as due to frequent temperature cha... | <SOH> SUMMARY <EOH>According to an embodiment, in a novel semiconductor power module a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another, wherein the first soldering partner has a first surface... | TECHNICAL FIELD The invention relates to power semiconductor modules, to a method for producing a power semiconductor module and to semiconductor chips. BACKGROUND Power semiconductor modules comprise a number of soldered connections, wherein the most various components must be fixedly and permanently joined with one a... | H | 67H01 | 185H01L | 23 | 48 | |||
11692151 | US20070190722A1-20070816 | METHOD TO FORM UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT | ACCEPTED | 20070801 | 20070816 | [] | H01L21336 | ["H01L21336"] | 7767499 | 20070327 | 20100803 | 438 | 129000 | 95301.0 | SENE | PAPE | [{"inventor_name_last": "Herner", "inventor_name_first": "S.", "inventor_city": "San Jose", "inventor_state": "CA", "inventor_country": "US"}] | A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and... | 1. A method for forming a vertically oriented p-i-n diode, the method comprising: forming a first rail-shaped conductor above a substrate; forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor; forming a middle intrinsic or lightly doped region of deposit... | <SOH> BACKGROUND OF THE INVENTION <EOH>A diode has the characteristic of allowing very little current flow below a certain turn-on voltage, and substantially more current above the turn-on voltage. It has proven difficult to form a large population of vertically oriented p-i-n diodes having a bottom heavily doped p-ty... | <SOH> SUMMARY OF THE PREFERRED EMBODIMENTS <EOH>The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a method to fabricate an upward-pointing p-i-n diode. A first aspect of the invention provides ... | RELATED APPLICATIONS This application is a continuation-in-part of Herner et al., U.S. patent application Ser. No. 10/955,549, “Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States,” filed Sep. 29, 2004, hereinafter the '549 application, which is a continuation-in-part of Herner e... | H | 67H01 | 185H01L | 213 | 36 | |||
11724726 | US20080150006A1-20080626 | Using implanted poly-1 to improve charging protection in dual-poly process | ACCEPTED | 20080612 | 20080626 | [] | H01L21336 | ["H01L21336", "H01L29792"] | 7553727 | 20070316 | 20090630 | 438 | 257000 | 67400.0 | BOOTH | RICHARD | [{"inventor_name_last": "Kwan", "inventor_name_first": "Ming-Sang", "inventor_city": "San Leandro", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_name_last": "Davis", "inventor_name_first": "Bradley Marc", "inventor_city": "Mountain View", "inventor_state": "CA", "inventor_country": "US"}, {"inventor_na... | The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can ac... | 1. A method of forming at least a portion of a dual-poly memory core array upon a semiconductor substrate, the method comprising: performing a core implant on the semiconductor substrate; depositing a charge trapping dielectric layer over the semiconductor substrate; forming a first polysilicon layer over the charge tr... | <SOH> BACKGROUND OF THE INVENTION <EOH>It is critical in semiconductor manufacturing and packaging to control wafer level core array threshold voltage (Vt) variation. This is especially true as electronic designs become smaller and more densely packed. In addition, charge can accumulate on a semiconductor surface if th... | <SOH> SUMMARY OF THE INVENTION <EOH>The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope ... | REFERENCE TO RELATED APPLICATION This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/876,180 which was filed Dec. 20, 2006, entitled USING IMPLANTED POLY-1 TO IMPROVE CHARGING PROTECTION IN DUAL-POLY PROCESS. FIELD OF INVENTION The present invention relates generally to the art of sem... | H | 67H01 | 185H01L | 213 | 36 | |||
11876816 | US20080100209A1-20080501 | Organic Electroluminescent Display Device | ACCEPTED | 20080422 | 20080501 | [] | H01L5154 | ["H01L5154"] | 7982392 | 20071023 | 20110719 | 313 | 504000 | 61124.0 | PERRY | ANTHONY | [{"inventor_name_last": "Ito", "inventor_name_first": "Masato", "inventor_city": "Mobara", "inventor_state": "", "inventor_country": "JP"}] | To provide an organic electroluminescent display device promoting a color purity of emitted light and promoting a contrast in a top emission type organic electroluminescent display device, there is constructed a constitution including a plurality of pixel electrodes CD arranged at a main face of an insulating substrate... | 1. An organic electroluminescent display device having a plurality of pixel electrodes arranged at a main face of an insulating substrate, organic electroluminescent layers having a multi-layer structure respectively arranged above the plurality of pixel electrodes, a light transmitting opposed electrode arranged at an... | <SOH> BACKGROUND <EOH>The present invention relates to an organic electroluminescent display device device, particularly relates to an organic electroluminescent display device device including a top emission type organic electroluminescent element. | <SOH> SUMMARY <EOH>According to a top emission type organic electroluminescent display device, depending on an element constitution, a film thickness of an electrode or an organic electroluminescent layer, an influence of interference of light is considerable and it is difficult to promote a luminescence and a contrast... | CROSS-REFERENCE TO RELATED APPLICATIONS The disclosure of Japanese Patent Application No. 2006-289491 filed on (2006 Oct. 25) including the claims, the specification, the drawings and the abstract is incorporated herein by reference in its entirely. BACKGROUND The present invention relates to an organic electroluminesc... | H | 67H01 | 185H01L | 51 | 54 | |||
11845766 | US20070290357A1-20071220 | Top layers of metal for high performance IC's | ACCEPTED | 20071205 | 20071220 | [] | H01L2350 | ["H01L2350"] | 7382058 | 20070827 | 20080603 | 257 | 778000 | 62575.0 | PHAM | LONG | [{"inventor_name_last": "Lin", "inventor_name_first": "Mou-Shiung", "inventor_city": "Hsin-Chu", "inventor_state": "", "inventor_country": "TW"}] | A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration o... | 1. An integrated circuit chip comprising: a silicon substrate; multiple devices in and on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer ... | <SOH> BACKGROUND OF THE INVENTION <EOH>(1) Field of the Invention The invention relates to the manufacturing of high performance Integrated Circuit (IC's), and more specifically to methods of achieving high performance of the Integrated Circuits by reducing the parasitic capacitance and resistance of inter-connecting ... | <SOH> SUMMARY OF THE INVENTION <EOH>It is the primary objective of the present invention to improve the performance of High Performance Integrated Circuits. Another objective of the present invention is to reduce resistive voltage drop of the power supply lines that connect the IC to surrounding circuitry or circuit c... | This application is a continuation of application Ser. No. 11/230,102, filed on Sep. 19, 2005, now pending, which is a continuation of application Ser. No. 11/121,477, filed on May 4, 2005, now pending, which is a continuation of application Ser. No. 10/389,543, filed on Mar. 14, 2003, now U.S. Pat. No. 6,965,165, whic... | H | 67H01 | 185H01L | 23 | 50 | |||
10594619 | US20080006894A1-20080110 | Semiconductor Light Detecting Element and Manufacturing Method Thereof | ACCEPTED | 20071226 | 20080110 | [] | H01L31101 | ["H01L31101", "H01L3118"] | 7868408 | 20070619 | 20110111 | 257 | 466000 | 59628.0 | VIEIRA | DIANA | [{"inventor_name_last": "Tanaka", "inventor_name_first": "Akimasa", "inventor_city": "Shizuoka", "inventor_state": "", "inventor_country": "JP"}] | A semiconductor photodetector device (PD1) comprises a multilayer structure (LS1) and a glass substrate (1) optically transparent to incident light. The multilayer structure includes an etching stop layer (2), an n-type high-concentration carrier layer (3), an n-type light-absorbing layer (5), and an n-type cap layer (... | 1. A photodetector device comprising: a multilayer structure including a plurality of compound semiconductor layers laminated and having first and second main faces opposing each other; a photodetecting region formed near the first main face within the multilayer structure; a first electrode arranged on the first main ... | <SOH> BACKGROUND ART <EOH>Recently, as the CPU driving frequency has been becoming higher (e.g., 10 GHz or higher), attention has been directed toward optical interconnection techniques in which signals within and between system apparatus are transmitted by light. Semiconductor devices such as semiconductor photodetect... | <SOH> BRIEF DESCRIPTION OF THE DRAWINGS <EOH>FIG. 1 is a schematic plan view showing the semiconductor photodetector device in accordance with a first embodiment. FIG. 2 is a schematic sectional view taken along the line II-II of FIG. 1 . FIG. 3 is a schematic sectional view showing a manufacturing step of the semicon... | TECHNICAL FIELD The present invention relates to a semiconductor photodetector device and a method of manufacturing the same. BACKGROUND ART Recently, as the CPU driving frequency has been becoming higher (e.g., 10 GHz or higher), attention has been directed toward optical interconnection techniques in which signals wi... | H | 67H01 | 185H01L | 311 | 01 | |||
11952755 | US20080173905A1-20080724 | SOLID STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME | ACCEPTED | 20080709 | 20080724 | [] | H01L27148 | ["H01L27148", "H01L3118"] | 7714401 | 20071207 | 20100511 | 257 | 431000 | 59162.0 | LAM | CATHY | [{"inventor_name_last": "NAGASE", "inventor_name_first": "Masanori", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Matsuda", "inventor_name_first": "Jiro", "inventor_city": "Kurokawa-gun", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last":... | A solid state imaging device comprises: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal charg... | 1. A solid state imaging device comprising: a photoelectric converting portion provided on a semiconductor substrate; a charge transfer path, formed in an adjacent position to the photoelectric converting portion, that receives a signal charge generated in the photoelectric converting portion and transfers the signal c... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The present invention relates to a solid state imaging device and a method of manufacturing the solid state imaging device. 2. Description of the Related Art Referring to a solid state imaging device to be used in a digital camera, particularly, a solid s... | <SOH> SUMMARY OF THE INVENTION <EOH>It is an object of the invention to provide a solid state imaging device and a method of manufacturing the solid state imaging device which can effectively reduce a smear while maintaining a characteristic of an embedded photodiode without applying a special voltage to a gate electro... | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state imaging device and a method of manufacturing the solid state imaging device. 2. Description of the Related Art Referring to a solid state imaging device to be used in a digital camera, particularly, a solid state imagin... | H | 67H01 | 185H01L | 271 | 48 | |||
11787541 | US20070194399A1-20070823 | Optoelectronic devices and solar cells | ACCEPTED | 20070808 | 20070823 | [] | H01L310232 | ["H01L310232"] | 7723166 | 20070416 | 20100525 | 438 | 149000 | 68971.0 | RAO | SHRINIVAS | [{"inventor_name_last": "Bhattacharyya", "inventor_name_first": "Arup", "inventor_city": "Essex Junction", "inventor_state": "VT", "inventor_country": "US"}] | The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched in... | 1. An optoelectronic device, comprising: a first electrode; a first layer of semiconductor material over the first electrode, the first layer of semiconductor material being heavily-doped semiconductor material; a second layer of semiconductor material over the first layer of semiconductor material; to the extent that ... | <SOH> BACKGROUND OF THE INVENTION <EOH>Optoelectronic devices (i.e., devices which detect electromagnetic radiation) have numerous applications. For instance, optoelectronic devices can be utilized as photodetectors in cameras and other imaging equipment. A continuing goal is to decrease the size and complexity of opt... | <SOH> SUMMARY OF THE INVENTION <EOH>In one aspect, the invention includes an optoelectronic device. The device comprises a first electrode, a first layer of semiconductor material over the first electrode, a second layer of semiconductor material over the first layer of semiconductor material, a layer of semiconductor... | TECHNICAL FIELD The invention pertains to optoelectronic devices and solar cells, and pertains to methods of making optoelectronic devices and solar cells. BACKGROUND OF THE INVENTION Optoelectronic devices (i.e., devices which detect electromagnetic radiation) have numerous applications. For instance, optoelectronic d... | H | 67H01 | 185H01L | 3102 | 32 | |||
11858147 | US20080009101A1-20080110 | COMPRESSIBLE FILMS SURROUNDING SOLDER CONNECTORS | ACCEPTED | 20071226 | 20080110 | [] | H01L2100 | ["H01L2100"] | 7566649 | 20070920 | 20090728 | 438 | 612000 | 60221.0 | THAI | LUAN | [{"inventor_name_last": "Bernier", "inventor_name_first": "William", "inventor_city": "Endwell", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Cheng", "inventor_name_first": "Tien-Jen", "inventor_city": "Bedford", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Co... | Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier an... | 1. A method of forming an integrated circuit structure, said method comprising: forming solder connectors on a device; surrounding sides of said solder connectors with a compressible film; connecting said device to a carrier, wherein said solder connectors electrically connect said device to said carrier; and filling g... | <SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention The invention generally relates to connectors between devices and carriers and more particularly to connectors that are surrounded by compressible material that prevents delamination of the carrier from the device. 2. Description of the Related Art Devic... | <SOH> SUMMARY OF THE INVENTION <EOH>Disclosed is a method of forming an integrated circuit structure, where the method forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the c... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional of U.S. application Ser. No. 10/711,076 filed Aug. 20, 2004, the complete disclosure of which, in its entirety, is herein incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The invention generally relates to connector... | H | 67H01 | 185H01L | 21 | 00 | |||
11955235 | US20080157203A1-20080703 | SEMICONDUCTOR DEVICE HAVING EDMOS TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME | ACCEPTED | 20080619 | 20080703 | [] | H01L2978 | ["H01L2978", "H01L21336"] | 7851329 | 20071212 | 20101214 | 438 | 439000 | 96195.0 | TRAN | LONG | [{"inventor_name_last": "Shin", "inventor_name_first": "Hyun-Soo", "inventor_city": "Chungcheongbuk-do", "inventor_state": "", "inventor_country": "KR"}] | A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the fi... | 1. An apparatus comprising: a source region and a drain region formed in a semiconductor substrate; a first gate insulating layer filling a trench formed in the semiconductor substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source ... | <SOH> BACKGROUND <EOH>Embodiments relate to a semiconductor device and a method for manufacturing the same, and more particularly, to an Extended Drain Metal Oxide Semiconductor (EDMOS) transistor device and method of manufacture. One of the components a semiconductor device may require is a transistor that controls hi... | <SOH> SUMMARY <EOH>Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which are optimized for high integration. Embodiments relate to a semiconductor device having an EDMOS transistor and a method for forming the same, which can reduce the planar area of the EDMOS... | The present application claims priority under 35 U.S.C. 119 to Korean Patent Application No. 10-2006-0137337, filed on Dec. 29, 2006, which is hereby incorporated by reference in its entirety. BACKGROUND Embodiments relate to a semiconductor device and a method for manufacturing the same, and more particularly, to an E... | H | 67H01 | 185H01L | 29 | 78 | |||
11769304 | US20080121972A1-20080529 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | ACCEPTED | 20080514 | 20080529 | [] | H01L29788 | ["H01L29788", "H01L21336"] | 7679127 | 20070627 | 20100316 | 257 | 315000 | 79459.0 | MANDALA | VICTOR | [{"inventor_name_last": "Shiozawa", "inventor_name_first": "Junichi", "inventor_city": "Yokkaichi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "Furuhata", "inventor_name_first": "Takeo", "inventor_city": "Yokkaichi", "inventor_state": "", "inventor_country": "JP"}, {"inventor_name_last": "S... | A semiconductor device including a semiconductor substrate; a first gate insulating film formed on the semiconductor substrate; a first gate electrode layer formed on the first gate insulating film; an element isolation insulating film formed so as to isolate a plurality of the first gate electrode layers; a second gat... | 1. A semiconductor device, comprising: a semiconductor substrate including a first upper surface having an element isolation region and an element forming region; a first gate electrode formed on the first upper surface of the semiconductor substrate via a first insulating film in the element forming region, including ... | <SOH> BACKGROUND <EOH>Conventionally, a stacked gate electrode structures composed of a floating gate electrode layer and a control gate electrode layer has been employed to render non-volatile storage of information. In realizing the stacked gate electrode structure, an inter-gate insulating film is formed between the... | <SOH> SUMMARY <EOH>The present disclosure provides a semiconductor device that prevents charge transportation between the neighboring floating gate electrode layers when NONON stacked film structure is employed for inter-gate insulating film which is formed between the floating gate electrode layer and the control gate... | CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-176646, filed on, Jun. 27, 2006 the entire contents of which are incorporated herein by reference. FIELD The present disclosure is directed to a semiconductor dev... | H | 67H01 | 185H01L | 297 | 88 | |||
11932677 | US20080064179A1-20080313 | LOW LEAKAGE MIM CAPACITOR | ACCEPTED | 20080227 | 20080313 | [] | H01L2120 | ["H01L2120"] | 7435641 | 20071031 | 20081014 | 438 | 240000 | 77616.0 | TSAI | HUI | [{"inventor_name_last": "Yang", "inventor_name_first": "Sam", "inventor_city": "Boise", "inventor_state": "ID", "inventor_country": "US"}] | Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed ... | 1. A method of forming a capacitor, comprising: forming a bottom electrode layer having a monoclinic crystal structure; forming a metal oxide buffer layer overlying the bottom electrode layer, converting the metal oxide buffer layer lattice structure from a monoclinic crystalline structure to an orthorhombic crystallin... | <SOH> BACKGROUND <EOH>Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The capacitor ... | <SOH> SUMMARY <EOH>The above mentioned problems with capacitors and associated memory devices, and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Embodiments of the invention include capacitors having a metal oxide buffer layer interpos... | This application is a Continuation of U.S. application Ser. No. 10/215,462 filed Aug. 9, 2002, which is a Divisional of U.S. application Ser. No. 09/745,114, filed Dec. 20, 2000. These applications are incorporated herein by reference. TECHNICAL FIELD The present invention relates generally to metal-insulator-metal sem... | H | 67H01 | 185H01L | 21 | 20 | |||
11858624 | US20090079075A1-20090326 | INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME | ACCEPTED | 20090311 | 20090326 | [] | H01L2352 | ["H01L2352", "H01L214763"] | 8084862 | 20070920 | 20111227 | 257 | 758000 | 71595.0 | HARRISTON | WILLIAM | [{"inventor_name_last": "Lin", "inventor_name_first": "Qinghuang", "inventor_city": "Yorktown Heights", "inventor_state": "NY", "inventor_country": "US"}, {"inventor_name_last": "Chen", "inventor_name_first": "Shyng-Tsong", "inventor_city": "Rensselaer", "inventor_state": "NY", "inventor_country": "US"}] | The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, t... | 1. An interconnect structure comprising: at least one patterned and cured low-k dielectric material located on a surface of a patterned and cured antireflective coating located between said at least one patterned and cured low-k dielectric material and a substrate, said at least one cured and patterned low-k material a... | <SOH> BACKGROUND OF THE INVENTION <EOH>It is widely known that the speed of propagation of interconnect signals is one of the most important factors controlling overall circuit speed as feature sizes are reduced and the number of devices per unit area as well as the number of interconnect levels are increased. Througho... | <SOH> SUMMARY OF THE INVENTION <EOH>The problems described above in prior art processes of fabricating interconnect (single-damascene and dual-damascene) structures are solved by using a dramatically simplified integration method of this invention. The present invention thus relates to a method of forming interconnect ... | FIELD OF THE INVENTION The present invention relates to an interconnect structure and a method of fabricating interconnect structures. Specifically, the present invention relates to interconnect structures that are part of integrated circuits and microelectronic devices with patternable dielectrics and a method of fabr... | H | 67H01 | 185H01L | 23 | 52 |
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